diff options
Diffstat (limited to 'libpcsxcore')
-rw-r--r-- | libpcsxcore/new_dynarec/new_dynarec.c | 214 |
1 files changed, 116 insertions, 98 deletions
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 65c8f03..1c0ab56 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -56,6 +56,13 @@ static void __clear_cache(void *start, void *end) { #elif defined(_3DS) #include "3ds_utils.h" #define __clear_cache(start,end) svcFlushProcessDataCache(0xFFFF8001, start, (u32)(end)-(u32)(start)) +#elif defined(VITA) +#define __clear_cache vita_clear_cache +static void __clear_cache(void *start, void *end) { + size_t len = (char *)end - (char *)start; + int block = sceKernelFindMemBlockByAddr(start,len); + sceKernelSyncVMDomain(block, start, len); +} #endif #define MAXBLOCK 4096 @@ -196,7 +203,7 @@ struct ll_entry #define STORE 2 // Store #define LOADLR 3 // Unaligned load #define STORELR 4 // Unaligned store -#define MOV 5 // Move +#define MOV 5 // Move #define ALU 6 // Arithmetic/logic #define MULTDIV 7 // Multiply/divide #define SHIFT 8 // Shift by register @@ -314,18 +321,18 @@ static void tlb_hacks() { u_int addr; int n; - switch (ROM_HEADER->Country_code&0xFF) + switch (ROM_HEADER->Country_code&0xFF) { case 0x45: // U addr=0x34b30; - break; - case 0x4A: // J - addr=0x34b70; - break; - case 0x50: // E + break; + case 0x4A: // J + addr=0x34b70; + break; + case 0x50: // E addr=0x329f0; - break; - default: + break; + default: // Unknown country code addr=0; break; @@ -526,7 +533,7 @@ static void flush_dirty_uppers(struct regstat *cur) for (hr=0;hr<HOST_REGS;hr++) { if((cur->dirty>>hr)&1) { reg=cur->regmap[hr]; - if(reg>=64) + if(reg>=64) if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1; } } @@ -683,7 +690,7 @@ int needed_again(int r, int i) int j; int b=-1; int rn=10; - + if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) { if(ba[i-1]<start || ba[i-1]>start+slen*4-4) @@ -786,7 +793,7 @@ int loop_reg(int i, int r, int hr) void alloc_all(struct regstat *cur,int i) { int hr; - + for(hr=0;hr<HOST_REGS;hr++) { if(hr!=EXCLUDE_REG) { if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&& @@ -827,7 +834,7 @@ void mult64(uint64_t m1,uint64_t m2) unsigned long long int result1, result2, result3, result4; unsigned long long int temp1, temp2, temp3, temp4; int sign = 0; - + if (m1 < 0) { op2 = -m1; @@ -840,22 +847,22 @@ void mult64(uint64_t m1,uint64_t m2) sign = 1 - sign; } else op4 = m2; - + op1 = op2 & 0xFFFFFFFF; op2 = (op2 >> 32) & 0xFFFFFFFF; op3 = op4 & 0xFFFFFFFF; op4 = (op4 >> 32) & 0xFFFFFFFF; - + temp1 = op1 * op3; temp2 = (temp1 >> 32) + op1 * op4; temp3 = op2 * op3; temp4 = (temp3 >> 32) + op2 * op4; - + result1 = temp1 & 0xFFFFFFFF; result2 = temp2 + (temp3 & 0xFFFFFFFF); result3 = (result2 >> 32) + temp4; result4 = (result3 >> 32); - + lo = result1 | (result2 << 32); hi = (result3 & 0xFFFFFFFF) | (result4 << 32); if (sign) @@ -871,25 +878,25 @@ void multu64(uint64_t m1,uint64_t m2) unsigned long long int op1, op2, op3, op4; unsigned long long int result1, result2, result3, result4; unsigned long long int temp1, temp2, temp3, temp4; - + op1 = m1 & 0xFFFFFFFF; op2 = (m1 >> 32) & 0xFFFFFFFF; op3 = m2 & 0xFFFFFFFF; op4 = (m2 >> 32) & 0xFFFFFFFF; - + temp1 = op1 * op3; temp2 = (temp1 >> 32) + op1 * op4; temp3 = op2 * op3; temp4 = (temp3 >> 32) + op2 * op4; - + result1 = temp1 & 0xFFFFFFFF; result2 = temp2 + (temp3 & 0xFFFFFFFF); result3 = (result2 >> 32) + temp4; result4 = (result3 >> 32); - + lo = result1 | (result2 << 32); hi = (result3 & 0xFFFFFFFF) | (result4 << 32); - + //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32) // ,(int)reg[LOREG],(int)(reg[LOREG]>>32)); } @@ -1011,7 +1018,7 @@ void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift) { struct ll_entry *next; while(*head) { - if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || + if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)) { inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr); @@ -1107,7 +1114,7 @@ static void invalidate_block_range(u_int block, u_int first, u_int last) #ifdef __arm__ do_clear_cache(); #endif - + // Don't trap writes invalid_code[block]=1; #ifndef DISABLE_TLB @@ -3386,7 +3393,7 @@ void storelr_assemble(int i,struct regstat *i_regs) if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG); gen_tlb_addr_w(temp,map); #else - if((u_int)rdram!=0x80000000) + if((u_int)rdram!=0x80000000) emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp); #endif }else{ // using tlb @@ -4159,7 +4166,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) int mgr=MGEN1+(i&1); if(itype[i]==LOAD) { ra=get_reg(i_regs->regmap,rt1[i]); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg(i_regs->regmap,-1); assert(ra>=0); } if(itype[i]==LOADLR) { @@ -4757,7 +4764,7 @@ int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr) { return 0; } - else + else if((i_dirty>>hr)&1) { if(i_regmap[hr]<TEMPREG) @@ -5003,7 +5010,7 @@ void do_ccstub(int n) if(rs1[i]) { if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1) emit_loadreg(rs1[i],s1l); - } + } else { if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1) emit_loadreg(rs2[i],s1l); @@ -5194,7 +5201,7 @@ void do_ccstub(int n) load_all_regs(branch_regs[i].regmap); } emit_jmp(stubs[n][2]); // return address - + /* This works but uses a lot of memory... emit_readword((int)&last_count,ECX); emit_add(HOST_CCREG,ECX,EAX); @@ -5228,7 +5235,7 @@ add_to_linker(int addr,int target,int ext) { link_addr[linkcount][0]=addr; link_addr[linkcount][1]=target; - link_addr[linkcount][2]=ext; + link_addr[linkcount][2]=ext; linkcount++; } @@ -5254,7 +5261,7 @@ static void ujump_assemble_write_ra(int i) #endif { #ifdef REG_PREFETCH - if(temp>=0) + if(temp>=0) { if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); } @@ -5275,10 +5282,10 @@ void ujump_assemble(int i,struct regstat *i_regs) address_generation(i+1,i_regs,regs[i].regmap_entry); #ifdef REG_PREFETCH int temp=get_reg(branch_regs[i].regmap,PTEMP); - if(rt1[i]==31&&temp>=0) + if(rt1[i]==31&&temp>=0) { int return_address=start+i*4+8; - if(get_reg(branch_regs[i].regmap,31)>0) + if(get_reg(branch_regs[i].regmap,31)>0) if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); } #endif @@ -5329,7 +5336,7 @@ static void rjump_assemble_write_ra(int i) assert(rt>=0); return_address=start+i*4+8; #ifdef REG_PREFETCH - if(temp>=0) + if(temp>=0) { if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp); } @@ -5358,7 +5365,7 @@ void rjump_assemble(int i,struct regstat *i_regs) } address_generation(i+1,i_regs,regs[i].regmap_entry); #ifdef REG_PREFETCH - if(rt1[i]==31) + if(rt1[i]==31) { if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) { int return_address=start+i*4+8; @@ -5492,7 +5499,7 @@ void cjump_assemble(int i,struct regstat *i_regs) #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if(i>(ba[i]-start)>>2) invert=1; #endif - + if(ooo[i]) { s1l=get_reg(branch_regs[i].regmap,rs1[i]); s1h=get_reg(branch_regs[i].regmap,rs1[i]|64); @@ -5547,7 +5554,7 @@ void cjump_assemble(int i,struct regstat *i_regs) load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG); cc=get_reg(branch_regs[i].regmap,CCREG); assert(cc==HOST_CCREG); - if(unconditional) + if(unconditional) store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); //assem_debug("cycle count (adj)\n"); @@ -5619,7 +5626,7 @@ void cjump_assemble(int i,struct regstat *i_regs) emit_jne(0); } } // if(!only32) - + //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(s1l>=0); if(opcode[i]==4) // BEQ @@ -5749,7 +5756,7 @@ void cjump_assemble(int i,struct regstat *i_regs) emit_jne(1); } } // if(!only32) - + //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(s1l>=0); if((opcode[i]&0x2f)==4) // BEQ @@ -5932,7 +5939,7 @@ void sjump_assemble(int i,struct regstat *i_regs) } cc=get_reg(branch_regs[i].regmap,CCREG); assert(cc==HOST_CCREG); - if(unconditional) + if(unconditional) store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]); //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional); assem_debug("cycle count (adj)\n"); @@ -6019,7 +6026,7 @@ void sjump_assemble(int i,struct regstat *i_regs) } } } // if(!only32) - + if(invert) { #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) { @@ -6267,7 +6274,7 @@ void fjump_assemble(int i,struct regstat *i_regs) { } } // if(!only32) - + if(invert) { if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK @@ -6775,14 +6782,14 @@ void unneeded_registers(int istart,int iend,int r) { // If subroutine call, flag return address as a possible branch target if(rt1[i]==31 && i<slen-2) bt[i+2]=1; - + if(ba[i]<start || ba[i]>=(start+slen*4)) { // Branch out of this block, flush all regs u=1; uu=1; gte_u=gte_u_unknown; - /* Hexagon hack + /* Hexagon hack if(itype[i]==UJUMP&&rt1[i]==31) { uu=u=0x300C00F; // Discard at, v0-v1, t6-t9 @@ -7045,7 +7052,7 @@ static void provisional_32bit() int i,j; uint64_t is32=1; uint64_t lastbranch=1; - + for(i=0;i<slen;i++) { if(i>0) { @@ -7082,13 +7089,13 @@ static void provisional_32bit() uint64_t temp_is32=is32; for(j=i-1;j>=0;j--) { - if(ba[j]==start+i*4) + if(ba[j]==start+i*4) //temp_is32&=branch_regs[j].is32; temp_is32&=p32[j]; } for(j=i;j<slen;j++) { - if(ba[j]==start+i*4) + if(ba[j]==start+i*4) temp_is32=1; } is32=temp_is32; @@ -7275,7 +7282,7 @@ static void provisional_r32() { u_int r32=0; int i; - + for (i=slen-1;i>=0;i--) { int hr; @@ -7373,7 +7380,7 @@ static void provisional_r32() } //requires_32bit[i]=r32; pr32[i]=r32; - + // Dirty registers which are 32-bit, require 32-bit input // as they will be written as 32-bit values for(hr=0;hr<HOST_REGS;hr++) @@ -7726,7 +7733,7 @@ void clean_registers(int istart,int iend,int wr) if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r; if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r; if(i>istart) { - if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP) + if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP) { // Don't store a register immediately after writing it, // may prevent dual-issue. @@ -7974,17 +7981,28 @@ void new_dynarec_init() { SysPrintf("Init new dynarec\n"); out=(u_char *)BASE_ADDR; -#if BASE_ADDR_FIXED +#if defined(VITA) + if (mmap (out, 1<<TARGET_SIZE_2, - PROT_READ | PROT_WRITE | PROT_EXEC, - MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, + 0, + 0, -1, 0) <= 0) { SysPrintf("mmap() failed: %s\n", strerror(errno)); } + #else - // not all systems allow execute in data segment by default - if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0) - SysPrintf("mprotect() failed: %s\n", strerror(errno)); + #if BASE_ADDR_FIXED + if (mmap (out, 1<<TARGET_SIZE_2, + PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, + -1, 0) <= 0) { + SysPrintf("mmap() failed: %s\n", strerror(errno)); + } + #else + // not all systems allow execute in data segment by default + if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0) + SysPrintf("mprotect() failed: %s\n", strerror(errno)); + #endif #endif #ifdef MUPEN64 rdword=&readmem_dword; @@ -8190,7 +8208,7 @@ int new_recompile_block(int addr) assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out); //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out); //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr); - //if(debug) + //if(debug) //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum()); //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29); /*if(Count>=312978186) { @@ -8246,7 +8264,7 @@ int new_recompile_block(int addr) unsigned int type,op,op2; //printf("addr = %x source = %x %x\n", addr,source,source[0]); - + /* Pass 1 disassembly */ for(i=0;!done;i++) { @@ -8906,7 +8924,7 @@ int new_recompile_block(int addr) /* Pass 2 - Register dependencies and branch targets */ unneeded_registers(0,slen-1,0); - + /* Pass 3 - Register allocation */ struct regstat current; // Current register allocations/status @@ -8936,7 +8954,7 @@ int new_recompile_block(int addr) unneeded_reg_upper[0]=1; current.regmap[HOST_BTREG]=BTREG; } - + for(i=0;i<slen;i++) { if(bt[i]) @@ -8977,12 +8995,12 @@ int new_recompile_block(int addr) uint64_t temp_is32=current.is32; for(j=i-1;j>=0;j--) { - if(ba[j]==start+i*4) + if(ba[j]==start+i*4) temp_is32&=branch_regs[j].is32; } for(j=i;j<slen;j++) { - if(ba[j]==start+i*4) + if(ba[j]==start+i*4) //temp_is32=1; temp_is32&=p32[j]; } @@ -9022,12 +9040,12 @@ int new_recompile_block(int addr) uint64_t temp_is32=current.is32; for(j=i-1;j>=0;j--) { - if(ba[j]==start+i*4+4) + if(ba[j]==start+i*4+4) temp_is32&=branch_regs[j].is32; } for(j=i;j<slen;j++) { - if(ba[j]==start+i*4+4) + if(ba[j]==start+i*4+4) //temp_is32=1; temp_is32&=p32[j]; } @@ -9045,7 +9063,7 @@ int new_recompile_block(int addr) { //printf("dump %d/r%d\n",hr,r); current.regmap[hr]=-1; - if(get_reg(current.regmap,r|64)>=0) + if(get_reg(current.regmap,r|64)>=0) current.regmap[get_reg(current.regmap,r|64)]=-1; } } @@ -9059,12 +9077,12 @@ int new_recompile_block(int addr) uint64_t temp_is32=current.is32; for(j=i-1;j>=0;j--) { - if(ba[j]==start+i*4+8) + if(ba[j]==start+i*4+8) temp_is32&=branch_regs[j].is32; } for(j=i;j<slen;j++) { - if(ba[j]==start+i*4+8) + if(ba[j]==start+i*4+8) //temp_is32=1; temp_is32&=p32[j]; } @@ -9080,7 +9098,7 @@ int new_recompile_block(int addr) { //printf("dump %d/r%d\n",hr,r); current.regmap[hr]=-1; - if(get_reg(current.regmap,r|64)>=0) + if(get_reg(current.regmap,r|64)>=0) current.regmap[get_reg(current.regmap,r|64)]=-1; } } @@ -9172,7 +9190,7 @@ int new_recompile_block(int addr) } } else { // First instruction expects CCREG to be allocated - if(i==0&&hr==HOST_CCREG) + if(i==0&&hr==HOST_CCREG) regs[i].regmap_entry[hr]=CCREG; else regs[i].regmap_entry[hr]=-1; @@ -9507,7 +9525,7 @@ int new_recompile_block(int addr) pagespan_alloc(¤t,i); break; } - + // Drop the upper half of registers that have become 32-bit current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i])); if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) { @@ -9568,7 +9586,7 @@ int new_recompile_block(int addr) } } else { // Branches expect CCREG to be allocated at the target - if(regmap_pre[i][hr]==CCREG) + if(regmap_pre[i][hr]==CCREG) regs[i].regmap_entry[hr]=CCREG; else regs[i].regmap_entry[hr]=-1; @@ -9919,11 +9937,11 @@ int new_recompile_block(int addr) if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; regs[i].waswritten=current.waswritten; } - + /* Pass 4 - Cull unused host registers */ - + uint64_t nr=0; - + for (i=slen-1;i>=0;i--) { int hr; @@ -10065,7 +10083,7 @@ int new_recompile_block(int addr) } // Save it needed_reg[i]=nr; - + // Deallocate unneeded registers for(hr=0;hr<HOST_REGS;hr++) { @@ -10194,20 +10212,20 @@ int new_recompile_block(int addr) } } } - + /* Pass 5 - Pre-allocate registers */ - + // If a register is allocated during a loop, try to allocate it for the // entire loop, if possible. This avoids loading/storing registers // inside of the loop. - + signed char f_regmap[HOST_REGS]; clear_all_regs(f_regmap); for(i=0;i<slen-1;i++) { if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) { - if(ba[i]>=start && ba[i]<(start+i*4)) + if(ba[i]>=start && ba[i]<(start+i*4)) if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS @@ -10255,10 +10273,10 @@ int new_recompile_block(int addr) } } if(ooo[i]) { - if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) + if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) f_regmap[hr]=branch_regs[i].regmap[hr]; }else{ - if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) + if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) f_regmap[hr]=branch_regs[i].regmap[hr]; } // Avoid dirty->clean transition @@ -10428,10 +10446,10 @@ int new_recompile_block(int addr) if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) { if(ooo[j]) { - if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) + if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break; }else{ - if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) + if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break; } if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) { @@ -10504,7 +10522,7 @@ int new_recompile_block(int addr) regs[k].isconst&=~(1<<HOST_CCREG); k++; } - regs[j].regmap_entry[HOST_CCREG]=CCREG; + regs[j].regmap_entry[HOST_CCREG]=CCREG; } // Work backwards from the branch target if(j>i&&f_regmap[HOST_CCREG]==CCREG) @@ -10546,7 +10564,7 @@ int new_recompile_block(int addr) } } } - + // Cache memory offset or tlb map pointer if a register is available #ifndef HOST_IMM_ADDR32 #ifndef RAM_OFFSET @@ -10726,7 +10744,7 @@ int new_recompile_block(int addr) } } #endif - + // This allocates registers (if possible) one instruction prior // to use, which can avoid a load-use penalty on certain CPUs. for(i=0;i<slen-1;i++) @@ -10787,7 +10805,7 @@ int new_recompile_block(int addr) } } } - // Load source into target register + // Load source into target register if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) { if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0) { @@ -10901,7 +10919,7 @@ int new_recompile_block(int addr) } } if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) { - if(itype[i+1]==LOAD) + if(itype[i+1]==LOAD) hr=get_reg(regs[i+1].regmap,rt1[i+1]); if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2 hr=get_reg(regs[i+1].regmap,FTEMP); @@ -10925,16 +10943,16 @@ int new_recompile_block(int addr) } } } - + /* Pass 6 - Optimize clean/dirty state */ clean_registers(0,slen-1,1); - + /* Pass 7 - Identify 32-bit registers */ #ifndef FORCE32 provisional_r32(); u_int r32=0; - + for (i=slen-1;i>=0;i--) { int hr; @@ -11030,7 +11048,7 @@ int new_recompile_block(int addr) if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i]; } requires_32bit[i]=r32; - + // Dirty registers which are 32-bit, require 32-bit input // as they will be written as 32-bit values for(hr=0;hr<HOST_REGS;hr++) @@ -11586,15 +11604,15 @@ int new_recompile_block(int addr) //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4); memcpy(copy,source,slen*4); copy+=slen*4; - + #ifdef __arm__ __clear_cache((void *)beginning,out); #endif - + // If we're within 256K of the end of the buffer, // start over from the beginning. (Is 256K enough?) if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR; - + // Trap writes to any of the pages we compiled for(i=start>>12;i<=(start+slen*4)>>12;i++) { invalid_code[i]=0; @@ -11618,9 +11636,9 @@ int new_recompile_block(int addr) invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]= invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0; #endif - + /* Pass 10 - Free memory by expiring oldest blocks */ - + int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535; while(expirep!=end) { @@ -11662,7 +11680,7 @@ int new_recompile_block(int addr) case 3: // Clear jump_out #ifdef __arm__ - if((expirep&2047)==0) + if((expirep&2047)==0) do_clear_cache(); #endif ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift); |