Age | Commit message (Collapse) | Author |
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at least the ones from C source, it looks like there could be more.
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no more need to load psxRegs in each function and all registers are
reachable by ldrh/strh.
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R1 redefined..
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Based on info from Ryphecha.
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otherwise in case interrupt happens, target insn is executed twice,
causing occasional glitches in Tekken 2.
Also clear branch flag for it - it's not in delay slot.
git-svn-id: https://pcsxr.svn.codeplex.com/svn/pcsxr@64369 e17a0e51-4ae3-4d35-97c3-1a29b211df97
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shalma:
- (nhyone) fix load delay bgez, bgezal
Xenogears - psxinterpreter.c
- lbu v1 - beq v1 = no load delay
- fix battle loading (interpreter only)
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