Age | Commit message (Collapse) | Author |
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and refacor a bit yet again
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should save a couple of cachelines
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a bit of refactoring too
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to be used for interlace emulation
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also small refactoring to read function, might be more accurate
(but surely wrong for width 1)
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a bit rough (as usual) and list slots only, but better than nothing
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saves a lot of address space
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it can't work directly on the list because modifies it
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ex_regs must be updated as they are saved and sent to GPU
on frameskip
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we do it in core now
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..that works with vram and display list dumps to produce output
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Tobal No.1 ...
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old value ~1.4 was weird anyway
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that division is not worth the quality increase it might give,
also sinc now can be 0 after resets, causing div0 fault.
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