From 076655d17df35d1f40137e88b7beaf5a039b058c Mon Sep 17 00:00:00 2001 From: notaz Date: Fri, 14 Jan 2011 18:32:17 +0200 Subject: drc: allow reading r31 in delay slot as hlide explained it's ok as long as we do DS first. --- libpcsxcore/new_dynarec/new_dynarec.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index f8a67ff..f1a0def 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -8688,7 +8688,8 @@ int new_recompile_block(int addr) if (rt1[i]==31) { alloc_reg(¤t,i,31); dirty_reg(¤t,31); - assert(rs1[i+1]!=31&&rs2[i+1]!=31); + //assert(rs1[i+1]!=31&&rs2[i+1]!=31); + assert(rt1[i+1]!=rt1[i]); #ifdef REG_PREFETCH alloc_reg(¤t,i,PTEMP); #endif @@ -8712,7 +8713,8 @@ int new_recompile_block(int addr) if (rt1[i]!=0) { alloc_reg(¤t,i,rt1[i]); dirty_reg(¤t,rt1[i]); - assert(rs1[i+1]!=31&&rs2[i+1]!=31); + //assert(rs1[i+1]!=31&&rs2[i+1]!=31); + assert(rt1[i+1]!=rt1[i]); #ifdef REG_PREFETCH alloc_reg(¤t,i,PTEMP); #endif -- cgit v1.2.3