From b96d3df7d4272503a287d243c09173eb6c842609 Mon Sep 17 00:00:00 2001
From: notaz
Date: Tue, 4 Oct 2011 23:37:07 +0300
Subject: rewrite memhandlers (write)

---
 libpcsxcore/new_dynarec/assem_arm.c   | 151 ++++++++++++++++++++++++++++++++--
 libpcsxcore/new_dynarec/emu_if.h      |   6 ++
 libpcsxcore/new_dynarec/linkage_arm.s | 124 ++++++++++++++++++++++++++++
 libpcsxcore/new_dynarec/new_dynarec.c |  14 +++-
 libpcsxcore/new_dynarec/pcsxmem.c     | 141 ++++++++++++++++++++++++++++---
 5 files changed, 415 insertions(+), 21 deletions(-)

(limited to 'libpcsxcore')

diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c
index cda420f..3447874 100644
--- a/libpcsxcore/new_dynarec/assem_arm.c
+++ b/libpcsxcore/new_dynarec/assem_arm.c
@@ -2041,6 +2041,21 @@ void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
     }
   }
 }
+void emit_strcc_dualindexed(int rs1, int rs2, int rt)
+{
+  assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+  output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
+}
+void emit_strccb_dualindexed(int rs1, int rs2, int rt)
+{
+  assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+  output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
+}
+void emit_strcch_dualindexed(int rs1, int rs2, int rt)
+{
+  assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
+  output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
+}
 void emit_writeword(int rt, int addr)
 {
   u_int offset = addr-(u_int)&dynarec_local;
@@ -2665,6 +2680,23 @@ emit_extjump_ds(int addr, int target)
 #include "pcsxmem_inline.c"
 #endif
 
+// trashes r2
+static void pass_args(int a0, int a1)
+{
+  if(a0==1&&a1==0) {
+    // must swap
+    emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
+  }
+  else if(a0!=0&&a1==0) {
+    emit_mov(a1,1);
+    if (a0>=0) emit_mov(a0,0);
+  }
+  else {
+    if(a0>=0&&a0!=0) emit_mov(a0,0);
+    if(a1>=0&&a1!=1) emit_mov(a1,1);
+  }
+}
+
 do_readstub(int n)
 {
   assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
@@ -2734,10 +2766,7 @@ do_readstub(int n)
   if(type==LOADW_STUB)
     handler=(int)jump_handler_read32;
   assert(handler!=0);
-  if(rs!=0)
-    emit_mov(rs,0);
-  if(temp2!=1)
-    emit_mov(temp2,1);
+  pass_args(rs,temp2);
   int cc=get_reg(i_regmap,CCREG);
   if(cc<0)
     emit_loadreg(CCREG,2);
@@ -2853,7 +2882,7 @@ u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
     l1<<=1;
     if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
       l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
-    else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREW_STUB)
+    else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
       l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
     else
       l2=((u_int *)l1)[(addr&0xfff)/4];
@@ -3036,6 +3065,68 @@ do_writestub(int n)
   }
   assert(rs>=0);
   assert(rt>=0);
+#ifdef PCSX
+  int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
+  int reglist2=reglist|(1<<rs)|(1<<rt);
+  for(rtmp=0;rtmp<=12;rtmp++) {
+    if(((1<<rtmp)&0x13ff)&&((1<<rtmp)&reglist2)==0) {
+      temp=rtmp; break;
+    }
+  }
+  if(temp==-1) {
+    save_regs(reglist);
+    regs_saved=1;
+    for(rtmp=0;rtmp<=3;rtmp++)
+      if(rtmp!=rs&&rtmp!=rt)
+        {temp=rtmp;break;}
+  }
+  if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
+    temp2=3;
+  emit_readword((int)&mem_wtab,temp);
+  emit_shrimm(rs,12,temp2);
+  emit_readword_dualindexedx4(temp,temp2,temp2);
+  emit_lsls_imm(temp2,1,temp2);
+  switch(type) {
+    case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
+    case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
+    case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
+    default:          assert(0);
+  }
+  if(regs_saved) {
+    restore_jump=(int)out;
+    emit_jcc(0); // jump to reg restore
+  }
+  else
+    emit_jcc(stubs[n][2]); // return address (invcode check)
+
+  if(!regs_saved)
+    save_regs(reglist);
+  int handler=0;
+  switch(type) {
+    case STOREB_STUB: handler=(int)jump_handler_write8; break;
+    case STOREH_STUB: handler=(int)jump_handler_write16; break;
+    case STOREW_STUB: handler=(int)jump_handler_write32; break;
+  }
+  assert(handler!=0);
+  pass_args(rs,rt);
+  if(temp2!=3)
+    emit_mov(temp2,3);
+  int cc=get_reg(i_regmap,CCREG);
+  if(cc<0)
+    emit_loadreg(CCREG,2);
+  emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
+  // returns new cycle_count
+  emit_call(handler);
+  emit_addimm(0,-CLOCK_DIVIDER*stubs[n][6]-2,cc<0?2:cc);
+  if(cc<0)
+    emit_storereg(CCREG,2);
+  if(restore_jump)
+    set_jump_target(restore_jump,(int)out);
+  restore_regs(reglist);
+  ra=stubs[n][2];
+  if(!restore_jump) ra+=4*3; // skip invcode check
+  emit_jmp(ra);
+#else // if !PCSX
   if(addr<0) addr=get_reg(i_regmap,-1);
   assert(addr>=0);
   int ftable=0;
@@ -3107,6 +3198,7 @@ do_writestub(int n)
   //  emit_loadreg(CCREG,cc);
   //}
   emit_jmp(stubs[n][2]); // return address
+#endif // !PCSX
 }
 
 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
@@ -3117,9 +3209,39 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target,
   assert(rs>=0);
   assert(rt>=0);
 #ifdef PCSX
+  u_int handler,host_addr=0;
   if(pcsx_direct_write(type,addr,rs,rt,regmap))
     return;
-#endif
+  handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
+  if (handler==0) {
+    if(target==0||addr!=host_addr)
+      emit_movimm(host_addr,rs);
+    switch(type) {
+      case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
+      case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
+      case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
+      default:          assert(0);
+    }
+    return;
+  }
+
+  // call a memhandler
+  save_regs(reglist);
+  pass_args(target!=0?rs:-1,rt);
+  if(target==0)
+    emit_movimm(addr,0);
+  int cc=get_reg(regmap,CCREG);
+  if(cc<0)
+    emit_loadreg(CCREG,2);
+  emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*(adj+1),2);
+  emit_movimm(handler,3);
+  // returns new cycle_count
+  emit_call((int)jump_handler_write_h);
+  emit_addimm(0,-CLOCK_DIVIDER*(adj+1),cc<0?2:cc);
+  if(cc<0)
+    emit_storereg(CCREG,2);
+  restore_regs(reglist);
+#else // if !pcsx
   int ftable=0;
   if(type==STOREB_STUB)
     ftable=(int)writememb;
@@ -3194,6 +3316,7 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target,
   }
   //emit_popa();
   restore_regs(reglist);
+#endif
 }
 
 do_unalignedwritestub(int n)
@@ -3217,6 +3340,21 @@ do_unalignedwritestub(int n)
   reglist|=(1<<addr);
   reglist&=~(1<<temp2);
 
+#if 1
+  // don't bother with it and call write handler
+  save_regs(reglist);
+  pass_args(addr,rt);
+  int cc=get_reg(i_regmap,CCREG);
+  if(cc<0)
+    emit_loadreg(CCREG,2);
+  emit_addimm(cc<0?2:cc,CLOCK_DIVIDER*stubs[n][6]+2,2);
+  emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
+  emit_addimm(0,-CLOCK_DIVIDER*stubs[n][6]-2,cc<0?2:cc);
+  if(cc<0)
+    emit_storereg(CCREG,2);
+  restore_regs(reglist);
+  emit_jmp(stubs[n][2]); // return address
+#else
   emit_andimm(addr,0xfffffffc,temp2);
   emit_writeword(temp2,(int)&address);
 
@@ -3279,6 +3417,7 @@ do_unalignedwritestub(int n)
   }
   restore_regs(reglist);
   emit_jmp(stubs[n][2]); // return address
+#endif
 }
 
 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
diff --git a/libpcsxcore/new_dynarec/emu_if.h b/libpcsxcore/new_dynarec/emu_if.h
index f71efc4..0d954df 100644
--- a/libpcsxcore/new_dynarec/emu_if.h
+++ b/libpcsxcore/new_dynarec/emu_if.h
@@ -40,6 +40,12 @@ extern void *mem_wtab;
 void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
 void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
 void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
+void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
+void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
+void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
+void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
+void jump_handle_swl(u32 addr, u32 data, u32 cycles);
+void jump_handle_swr(u32 addr, u32 data, u32 cycles);
 
 extern void (*readmem[0x10000])();
 extern void (*readmemb[0x10000])();
diff --git a/libpcsxcore/new_dynarec/linkage_arm.s b/libpcsxcore/new_dynarec/linkage_arm.s
index 1a4b33f..c1bc8c9 100644
--- a/libpcsxcore/new_dynarec/linkage_arm.s
+++ b/libpcsxcore/new_dynarec/linkage_arm.s
@@ -860,6 +860,12 @@ new_dyna_start:
 .global	jump_handler_read8
 .global	jump_handler_read16
 .global	jump_handler_read32
+.global	jump_handler_write8
+.global	jump_handler_write16
+.global	jump_handler_write32
+.global	jump_handler_write_h
+.global jump_handle_swl
+.global jump_handle_swr
 
 .macro ari_read_ram bic_const op
 	ldr	r0, [fp, #address-dynarec_local]
@@ -1156,4 +1162,122 @@ jump_handler_read16:
 jump_handler_read32:
 	pcsx_read_mem ldrcc, 2
 
+
+.macro pcsx_write_mem wrtop tab_shift
+	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
+	lsl	r12,r0, #20
+	lsr	r12, #(20+\tab_shift)
+	ldr	r3, [r3, r12, lsl #2]
+	str	r0, [fp, #address-dynarec_local]      @ some handlers still need it..
+	lsls	r3, #1
+	mov     r0, r2                                @ cycle return in case of direct store
+.if \tab_shift == 1
+	lsl	r12, #1
+	\wrtop	r1, [r3, r12]
+.else
+	\wrtop	r1, [r3, r12, lsl #\tab_shift]
+.endif
+	movcc	pc, lr
+	ldr	r12, [fp, #last_count-dynarec_local]
+	mov     r0, r1
+	add	r2, r2, r12
+	push	{r2, lr}
+	str	r2, [fp, #cycle-dynarec_local]
+	blx	r3
+
+	ldr	r0, [fp, #next_interupt-dynarec_local]
+	pop	{r2, r3}
+	str	r0, [fp, #last_count-dynarec_local]
+	sub	r0, r2, r0
+	bx	r3
+.endm
+
+jump_handler_write8:
+	add     r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
+	pcsx_write_mem strccb, 0
+
+jump_handler_write16:
+	add     r3, #0x1000/4*4              @ shift to r16 part
+	pcsx_write_mem strcch, 1
+
+jump_handler_write32:
+	pcsx_write_mem strcc, 2
+
+jump_handler_write_h:
+	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
+	ldr	r12, [fp, #last_count-dynarec_local]
+	str	r0, [fp, #address-dynarec_local]      @ some handlers still need it..
+	add	r2, r2, r12
+	mov     r0, r1
+	push	{r2, lr}
+	str	r2, [fp, #cycle-dynarec_local]
+	blx	r3
+
+	ldr	r0, [fp, #next_interupt-dynarec_local]
+	pop	{r2, r3}
+	str	r0, [fp, #last_count-dynarec_local]
+	sub	r0, r2, r0
+	bx	r3
+
+jump_handle_swl:
+	/* r0 = address, r1 = data, r2 = cycles */
+	ldr	r3, [fp, #mem_wtab-dynarec_local]
+	mov	r12,r0,lsr #12
+	ldr	r3, [r3, r12, lsl #2]
+	lsls	r3, #1
+	bcs	4f
+	add	r3, r0, r3
+	mov	r0, r2
+	tst	r3, #2
+	beq	101f
+	tst	r3, #1
+	beq	2f
+3:
+	str	r1, [r3, #-3]
+	bx	lr
+2:
+	lsr	r2, r1, #8
+	lsr	r1, #24
+	strh	r2, [r3, #-2]
+	strb	r1, [r3]
+	bx	lr
+101:
+	tst	r3, #1
+	lsrne	r1, #16		@ 1
+	lsreq	r12, r1, #24	@ 0
+	strneh	r1, [r3, #-1]
+	streqb	r12, [r3]
+	bx	lr
+4:
+	mov	r0, r2
+	b	abort
+	bx	lr		@ TODO?
+
+
+jump_handle_swr:
+	/* r0 = address, r1 = data, r2 = cycles */
+	ldr	r3, [fp, #mem_wtab-dynarec_local]
+	mov	r12,r0,lsr #12
+	ldr	r3, [r3, r12, lsl #2]
+	lsls	r3, #1
+	bcs	4f
+	add	r3, r0, r3
+	and	r12,r3, #3
+	mov	r0, r2
+	cmp	r12,#2
+	strgtb	r1, [r3]	@ 3
+	streqh	r1, [r3]	@ 2
+	cmp	r12,#1
+	strlt	r1, [r3]	@ 0
+	bxne	lr
+	lsr	r2, r1, #8	@ 1
+	strb	r1, [r3]
+	strh	r2, [r3, #1]
+	bx	lr
+4:
+	mov	r0, r2
+	b	abort
+	bx	lr		@ TODO?
+
+
 @ vim:filetype=armasm
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index cbc289e..362e3c6 100644
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -3288,6 +3288,14 @@ void store_assemble(int i,struct regstat *i_regs)
     }
     type=STORED_STUB;
   }
+#ifdef PCSX
+  if(jaddr) {
+    // PCSX store handlers don't check invcode again
+    reglist|=1<<addr;
+    add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
+    jaddr=0;
+  }
+#endif
   if(!using_tlb) {
     if(!c||memtarget) {
       #ifdef DESTRUCTIVE_SHIFT
@@ -11456,10 +11464,12 @@ int new_recompile_block(int addr)
   }
   inv_code_start=inv_code_end=~0;
 #ifdef PCSX
-  // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
+  // for PCSX we need to mark all mirrors too
   if(get_page(start)<(RAM_SIZE>>12))
     for(i=start>>12;i<=(start+slen*4)>>12;i++)
-      invalid_code[((u_int)0x80000000>>12)|i]=0;
+      invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
+      invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
+      invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
 #endif
   
   /* Pass 10 - Free memory by expiring oldest blocks */
diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index 30a04e3..d5ec002 100644
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -60,8 +60,9 @@ static void read_mem_dummy()
 	readmem_word = 0;
 }
 
-static void write_mem_dummy()
+static void write_mem_dummy(u32 data)
 {
+	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
 }
 
 extern void ari_read_ram8();
@@ -94,7 +95,7 @@ void (*writemem[0x10000])();
 void (*writememb[0x10000])();
 void (*writememh[0x10000])();
 
-static void write_biu()
+static void write_biu_()
 {
 	memprintf("write_biu %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
 
@@ -134,9 +135,9 @@ static void io_write_sio16(u32 value)
 static void io_write_sio32(u32 value)
 {
 	sioWrite8((unsigned char)value);
-	sioWrite8((unsigned char)((value&0xff) >>  8));
-	sioWrite8((unsigned char)((value&0xff) >> 16));
-	sioWrite8((unsigned char)((value&0xff) >> 24));
+	sioWrite8((unsigned char)(value >>  8));
+	sioWrite8((unsigned char)(value >> 16));
+	sioWrite8((unsigned char)(value >> 24));
 }
 
 #define make_rcnt_funcs(i) \
@@ -208,6 +209,21 @@ make_dma_func(3)
 make_dma_func(4)
 make_dma_func(6)
 
+static void io_spu_write16(u32 value)
+{
+	// meh
+	SPU_writeRegister(address, value);
+}
+
+static void io_spu_write32(u32 value)
+{
+	SPUwriteRegister wfunc = SPU_writeRegister;
+	u32 a = address;
+
+	wfunc(a, value & 0xffff);
+	wfunc(a + 2, value >> 16);
+}
+
 /* IO tables for 1000-1880 */
 #define IOADR8(a)  ((a) & 0xfff)
 #define IOADR16(a) (((a) & 0xfff) >> 1)
@@ -320,6 +336,7 @@ static u32 *mem_readtab;
 static u32 *mem_writetab;
 static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
 static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
+static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
 //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
 static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
 
@@ -339,6 +356,48 @@ static void map_item(u32 *out, const void *h, u32 flag)
 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
 #define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
 
+static void map_ram_write(void)
+{
+	int i;
+
+	for (i = 0; i < (0x800000 >> 12); i++) {
+		map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
+		map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
+		map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
+	}
+}
+
+static void unmap_ram_write(void)
+{
+	int i;
+
+	for (i = 0; i < (0x800000 >> 12); i++) {
+		map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
+		map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
+		map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
+	}
+}
+
+static void write_biu(u32 value)
+{
+	memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
+
+	if (address != 0xfffe0130)
+		return;
+
+	switch (value) {
+	case 0x800: case 0x804:
+		unmap_ram_write();
+		break;
+	case 0: case 0x1e988:
+		map_ram_write();
+		break;
+	default:
+		printf("write_biu: unexpected val: %08x\n", value);
+		break;
+	}
+}
+
 void new_dyna_pcsx_mem_init(void)
 {
 	int i;
@@ -369,15 +428,10 @@ void new_dyna_pcsx_mem_init(void)
 	// RAM and it's mirrors
 	for (i = 0; i < (0x800000 >> 12); i++) {
 		map_l1_mem(mem_readtab,  i, 0x80000000, 0x200000, psxM);
-		map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
 		map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
-		map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
 		map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
-		map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
 	}
-
-	// stupid BIOS RAM check
-	// TODO
+	map_ram_write();
 
 	// BIOS and it's mirrors
 	for (i = 0; i < (0x80000 >> 12); i++) {
@@ -395,7 +449,7 @@ void new_dyna_pcsx_mem_init(void)
 
 	// L2
 	// unmapped tables
-	for (i = 0; i < 0x1000; i++)
+	for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
 		map_item(&mem_unmwtab[i], write_mem_dummy, 1);
 
 	// fill IO tables
@@ -448,6 +502,64 @@ void new_dyna_pcsx_mem_init(void)
 	map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
 	map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
 
+	// write(u32 data)
+	map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
+	map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
+	map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
+	map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
+	map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
+	map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
+//	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
+//	map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
+
+	map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
+	map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
+	map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
+	map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
+
+	map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
+	map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
+	map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
+	map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
+	map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
+
+	for (i = 0x1c00; i < 0x1e00; i += 2) {
+		map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
+		map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
+	}
+
+	// misc
+	map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
+	for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
+		map_item(&mem_ffwtab[i], write_biu, 1);
+
 	mem_rtab = mem_readtab;
 	mem_wtab = mem_writetab;
 #endif
@@ -503,7 +615,7 @@ void new_dyna_pcsx_mem_init(void)
 	writememh[0x1f80] = ari_write_io16;
 	writemem[0x1f80]  = ari_write_io32;
 
-	writemem[0xfffe] = write_biu;
+	writemem[0xfffe] = write_biu_;
 #endif
 
 	// fill IO tables
@@ -526,6 +638,9 @@ void new_dyna_pcsx_mem_reset(void)
 	for (i = 0x1c00; i < 0x1e00; i += 2)
 		map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
 
+	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
+	map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
+
 	nd_pcsx_io.spu_readf = SPU_readRegister;
 	nd_pcsx_io.spu_writef = SPU_writeRegister;
 
-- 
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