From fe19474dca84b5d00570e3fb5a04c8a359615f70 Mon Sep 17 00:00:00 2001 From: twinaphex Date: Wed, 10 Dec 2014 01:17:37 +0100 Subject: Add macro parameter 'opcode' to some macros --- arm/arm_emit.h | 8 ++++---- cpu.c | 22 +++++++++++----------- cpu_threaded.c | 10 +++++----- disasm.c | 12 ++++++------ psp/mips_emit.h | 10 +++++----- x86/x86_emit.h | 12 ++++++------ 6 files changed, 37 insertions(+), 37 deletions(-) diff --git a/arm/arm_emit.h b/arm/arm_emit.h index aa97ad4..c77d7e1 100644 --- a/arm/arm_emit.h +++ b/arm/arm_emit.h @@ -1097,7 +1097,7 @@ u32 function_cc execute_spsr_restore_body(u32 pc) #define arm_generate_op_reg(name, load_op, store_op, flags_op) \ u32 shift_type = (opcode >> 5) & 0x03; \ - arm_decode_data_proc_reg(); \ + arm_decode_data_proc_reg(opcode); \ prepare_load_rn_##load_op(); \ prepare_store_rd_##store_op(); \ \ @@ -1122,7 +1122,7 @@ u32 function_cc execute_spsr_restore_body(u32 pc) // imm will be loaded by the called function if necessary. #define arm_generate_op_imm(name, load_op, store_op, flags_op) \ - arm_decode_data_proc_imm(); \ + arm_decode_data_proc_imm(opcode); \ prepare_load_rn_##load_op(); \ prepare_store_rd_##store_op(); \ generate_op_##name##_imm(_rd, _rn); \ @@ -1274,7 +1274,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address) #define arm_psr(op_type, transfer_type, psr_reg) \ { \ - arm_decode_psr_##op_type(); \ + arm_decode_psr_##op_type(opcode); \ arm_psr_##transfer_type(op_type, psr_reg); \ } \ @@ -1835,7 +1835,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address) generate_branch(arm) \ #define arm_bx() \ - arm_decode_branchx(); \ + arm_decode_branchx(opcode); \ generate_load_reg(reg_a0, rn); \ generate_indirect_branch_dual(); \ diff --git a/cpu.c b/cpu.c index c1108af..21b61e7 100644 --- a/cpu.c +++ b/cpu.c @@ -159,7 +159,7 @@ void print_register_usage() #endif -#define arm_decode_data_proc_reg() \ +#define arm_decode_data_proc_reg(opcode) \ u32 rn = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 rm = opcode & 0x0F; \ @@ -167,7 +167,7 @@ void print_register_usage() using_register(arm, rn, op_src); \ using_register(arm, rm, op_src) \ -#define arm_decode_data_proc_imm() \ +#define arm_decode_data_proc_imm(opcode) \ u32 rn = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 imm; \ @@ -175,21 +175,21 @@ void print_register_usage() using_register(arm, rd, op_dest); \ using_register(arm, rn, op_src) \ -#define arm_decode_psr_reg() \ +#define arm_decode_psr_reg(opcode) \ u32 psr_field = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 rm = opcode & 0x0F; \ using_register(arm, rd, op_dest); \ using_register(arm, rm, op_src) \ -#define arm_decode_psr_imm() \ +#define arm_decode_psr_imm(opcode) \ u32 psr_field = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 imm; \ ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2); \ using_register(arm, rd, op_dest) \ -#define arm_decode_branchx() \ +#define arm_decode_branchx(opcode) \ u32 rn = opcode & 0x0F; \ using_register(arm, rn, branch_target) \ @@ -748,18 +748,18 @@ u32 high_frequency_branch_targets = 0; } \ #define arm_data_proc_flags_reg() \ - arm_decode_data_proc_reg(); \ + arm_decode_data_proc_reg(opcode); \ calculate_reg_sh_flags() \ #define arm_data_proc_reg() \ - arm_decode_data_proc_reg(); \ + arm_decode_data_proc_reg(opcode); \ calculate_reg_sh() \ #define arm_data_proc_flags_imm() \ - arm_decode_data_proc_imm() \ + arm_decode_data_proc_imm(opcode) \ #define arm_data_proc_imm() \ - arm_decode_data_proc_imm() \ + arm_decode_data_proc_imm(opcode) \ #define arm_data_proc(expr, type) \ { \ @@ -921,7 +921,7 @@ const u32 psr_masks[16] = #define arm_psr(op_type, transfer_type, psr_reg) \ { \ - arm_decode_psr_##op_type(); \ + arm_decode_psr_##op_type(opcode); \ arm_pc_offset(4); \ arm_psr_##transfer_type(arm_psr_src_##op_type, psr_reg); \ } \ @@ -2143,7 +2143,7 @@ char *cpu_mode_names[] = if(opcode & 0x10) \ { \ /* BX rn */ \ - arm_decode_branchx(); \ + arm_decode_branchx(opcode); \ u32 src = reg[rn]; \ if(src & 0x01) \ { \ diff --git a/cpu_threaded.c b/cpu_threaded.c index a490e38..0c4e924 100644 --- a/cpu_threaded.c +++ b/cpu_threaded.c @@ -73,29 +73,29 @@ typedef struct extern u8 bit_count[256]; -#define arm_decode_data_proc_reg() \ +#define arm_decode_data_proc_reg(opcode) \ u32 rn = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 rm = opcode & 0x0F \ -#define arm_decode_data_proc_imm() \ +#define arm_decode_data_proc_imm(opcode) \ u32 rn = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 imm = opcode & 0xFF; \ u32 imm_ror = ((opcode >> 8) & 0x0F) * 2 \ -#define arm_decode_psr_reg() \ +#define arm_decode_psr_reg(opcode) \ u32 psr_field = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 rm = opcode & 0x0F \ -#define arm_decode_psr_imm() \ +#define arm_decode_psr_imm(opcode) \ u32 psr_field = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 imm = opcode & 0xFF; \ u32 imm_ror = ((opcode >> 8) & 0x0F) * 2 \ -#define arm_decode_branchx() \ +#define arm_decode_branchx(opcode) \ u32 rn = opcode & 0x0F \ #define arm_decode_multiply() \ diff --git a/disasm.c b/disasm.c index 601584f..97325b1 100644 --- a/disasm.c +++ b/disasm.c @@ -18,29 +18,29 @@ */ -#define arm_decode_data_proc_reg() \ +#define arm_decode_data_proc_reg(opcode) \ u32 rn = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 rm = opcode & 0x0F \ -#define arm_decode_data_proc_imm() \ +#define arm_decode_data_proc_imm(opcode) \ u32 rn = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 imm; \ ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2) \ -#define arm_decode_psr_reg() \ +#define arm_decode_psr_reg(opcode) \ u32 psr_field = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 rm = opcode & 0x0F \ -#define arm_decode_psr_imm() \ +#define arm_decode_psr_imm(opcode) \ u32 psr_field = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 imm; \ ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2) \ -#define arm_decode_branchx() \ +#define arm_decode_branchx(opcode) \ u32 rn = opcode & 0x0F \ #define arm_decode_multiply() \ @@ -181,4 +181,4 @@ u32 print_disasm_arm_instruction(u32 opcode) // Coprocessor, SWI case 0x7: - } \ No newline at end of file + } diff --git a/psp/mips_emit.h b/psp/mips_emit.h index 8fc95e8..7f5981d 100644 --- a/psp/mips_emit.h +++ b/psp/mips_emit.h @@ -1535,7 +1535,7 @@ typedef enum #define arm_op_check_no() \ #define arm_generate_op_reg_flags(name, load_op) \ - arm_decode_data_proc_reg(); \ + arm_decode_data_proc_reg(opcode); \ if(check_generate_c_flag) \ { \ rm = generate_load_rm_sh_flags(rm); \ @@ -1550,14 +1550,14 @@ typedef enum arm_to_mips_reg[rm]) \ #define arm_generate_op_reg(name, load_op) \ - arm_decode_data_proc_reg(); \ + arm_decode_data_proc_reg(opcode); \ rm = generate_load_rm_sh_no_flags(rm); \ arm_op_check_##load_op(); \ generate_op_##name##_reg(arm_to_mips_reg[rd], arm_to_mips_reg[rn], \ arm_to_mips_reg[rm]) \ #define arm_generate_op_imm(name, load_op) \ - arm_decode_data_proc_imm(); \ + arm_decode_data_proc_imm(opcode); \ arm_op_check_##load_op(); \ generate_op_##name##_imm(arm_to_mips_reg[rd], arm_to_mips_reg[rn]) \ @@ -1662,7 +1662,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address) #define arm_psr(op_type, transfer_type, psr_reg) \ { \ - arm_decode_psr_##op_type(); \ + arm_decode_psr_##op_type(opcode); \ arm_psr_##transfer_type(op_type, psr_reg); \ } \ @@ -2400,7 +2400,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address) generate_branch() \ #define arm_bx() \ - arm_decode_branchx(); \ + arm_decode_branchx(opcode); \ generate_load_reg(reg_a0, rn); \ /*generate_load_pc(reg_a2, pc);*/ \ generate_indirect_branch_dual() \ diff --git a/x86/x86_emit.h b/x86/x86_emit.h index efdceb5..1d4953c 100644 --- a/x86/x86_emit.h +++ b/x86/x86_emit.h @@ -1141,7 +1141,7 @@ typedef enum #define rm_op_imm imm #define arm_data_proc_reg_flags() \ - arm_decode_data_proc_reg(); \ + arm_decode_data_proc_reg(opcode); \ if(flag_status & 0x02) \ { \ generate_load_rm_sh(flags) \ @@ -1152,16 +1152,16 @@ typedef enum } \ #define arm_data_proc_reg() \ - arm_decode_data_proc_reg(); \ + arm_decode_data_proc_reg(opcode); \ generate_load_rm_sh(no_flags) \ #define arm_data_proc_imm() \ - arm_decode_data_proc_imm(); \ + arm_decode_data_proc_imm(opcode); \ ror(imm, imm, imm_ror); \ generate_load_imm(a0, imm) \ #define arm_data_proc_imm_flags() \ - arm_decode_data_proc_imm(); \ + arm_decode_data_proc_imm(opcode); \ if((flag_status & 0x02) && (imm_ror != 0)) \ { \ /* Generate carry flag from integer rotation */ \ @@ -1319,7 +1319,7 @@ void function_cc execute_store_spsr(u32 new_spsr, u32 store_mask) #define arm_psr(op_type, transfer_type, psr_reg) \ { \ - arm_decode_psr_##op_type(); \ + arm_decode_psr_##op_type(opcode); \ arm_psr_##transfer_type(op_type, psr_reg); \ } \ @@ -2196,7 +2196,7 @@ static void function_cc execute_swi(u32 pc) generate_branch() \ #define arm_bx() \ - arm_decode_branchx(); \ + arm_decode_branchx(opcode); \ generate_load_reg(a0, rn); \ generate_indirect_branch_dual(); \ -- cgit v1.2.3