From 7aaa280b9f41ad4e5d29f6471a0a814888b12485 Mon Sep 17 00:00:00 2001
From: David Guillen Fandos
Date: Wed, 10 Feb 2021 02:46:45 +0100
Subject: Fix ARM dynarec

Turns out there were a couple of very interesting and hard to track
bugs. A missing comma made the reg list too short, leaving the 31th
element at the mercy of the linker ordering algorithm, which seems to
work in some cases depending on the compiler version.
Also the cache flush code seemed not to work on my machine (OGA),
not sure why it wored in the past :/
---
 cpu_threaded.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

(limited to 'cpu_threaded.c')

diff --git a/cpu_threaded.c b/cpu_threaded.c
index 16a4852..ef7d83b 100644
--- a/cpu_threaded.c
+++ b/cpu_threaded.c
@@ -272,17 +272,11 @@ extern u8 bit_count[256];
 #define invalidate_icache_region(addr, size) (void)0
 
 #elif defined(ARM_ARCH)
-static int sys_cacheflush(void *addr, unsigned long size)
+static void sys_cacheflush(void *addr, unsigned long size)
 {
    void *start = (void*)addr;
    void *end   = (void*)(char *)addr + size;
-
-	register const unsigned char *r0 asm("r0") = start;
-	register const unsigned char *r1 asm("r1") = end;
-	register const int r2 asm("r2") = 0;
-	register const int r7 asm("r7") = 0xf0002;
-	asm volatile ("svc 0x0" :: "r" (r0), "r" (r1), "r" (r2), "r" (r7));
-   return -1;
+   __clear_cache(start, end);
 }
 
 #define translate_invalidate_dcache_one(which)                                \
-- 
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