From aafde6de7b2a28c1684c0e9fa62fee9a2a5398dd Mon Sep 17 00:00:00 2001
From: David Guillen Fandos
Date: Mon, 17 May 2021 01:14:46 +0200
Subject: Add ROM mirroring and fix mult. cycle count

This should correct some minor issues in some games.
---
 cpu_threaded.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'cpu_threaded.c')

diff --git a/cpu_threaded.c b/cpu_threaded.c
index 3cef5b1..557b197 100644
--- a/cpu_threaded.c
+++ b/cpu_threaded.c
@@ -297,6 +297,7 @@ void translate_icache_sync() {
         {                                                                     \
           /* MUL rd, rm, rs */                                                \
           arm_multiply(no, no);                                               \
+          cycle_count += 2;  /* variable 1..4, pick 2 as an aprox. */         \
         }                                                                     \
       }                                                                       \
       else                                                                    \
@@ -314,6 +315,7 @@ void translate_icache_sync() {
           case 0:                                                             \
             /* MULS rd, rm, rs */                                             \
             arm_multiply(no, yes);                                            \
+            cycle_count += 2;  /* variable 1..4, pick 2 as an aprox. */       \
             break;                                                            \
                                                                               \
           case 1:                                                             \
@@ -351,6 +353,7 @@ void translate_icache_sync() {
         {                                                                     \
           /* MLA rd, rm, rs, rn */                                            \
           arm_multiply(yes, no);                                              \
+          cycle_count += 3;  /* variable 2..5, pick 3 as an aprox. */         \
         }                                                                     \
       }                                                                       \
       else                                                                    \
@@ -368,6 +371,7 @@ void translate_icache_sync() {
           case 0:                                                             \
             /* MLAS rd, rm, rs, rn */                                         \
             arm_multiply(yes, yes);                                           \
+            cycle_count += 3;  /* variable 2..5, pick 3 as an aprox. */       \
             break;                                                            \
                                                                               \
           case 1:                                                             \
@@ -487,6 +491,7 @@ void translate_icache_sync() {
         {                                                                     \
           /* UMULL rd, rm, rs */                                              \
           arm_multiply_long(u64, no, no);                                     \
+          cycle_count += 3;  /* this is an aproximation :P */                 \
         }                                                                     \
       }                                                                       \
       else                                                                    \
@@ -504,6 +509,7 @@ void translate_icache_sync() {
           case 0:                                                             \
             /* UMULLS rdlo, rdhi, rm, rs */                                   \
             arm_multiply_long(u64, no, yes);                                  \
+            cycle_count += 3;  /* this is an aproximation :P */               \
             break;                                                            \
                                                                               \
           case 1:                                                             \
@@ -541,6 +547,7 @@ void translate_icache_sync() {
         {                                                                     \
           /* UMLAL rd, rm, rs */                                              \
           arm_multiply_long(u64_add, yes, no);                                \
+          cycle_count += 3;  /* Between 2 and 5 cycles? */                    \
         }                                                                     \
       }                                                                       \
       else                                                                    \
@@ -558,6 +565,7 @@ void translate_icache_sync() {
           case 0:                                                             \
             /* UMLALS rdlo, rdhi, rm, rs */                                   \
             arm_multiply_long(u64_add, yes, yes);                             \
+            cycle_count += 3;  /* Between 2 and 5 cycles? */                  \
             break;                                                            \
                                                                               \
           case 1:                                                             \
@@ -595,6 +603,7 @@ void translate_icache_sync() {
         {                                                                     \
           /* SMULL rd, rm, rs */                                              \
           arm_multiply_long(s64, no, no);                                     \
+          cycle_count += 2;  /* Between 1 and 4 cycles? */                    \
         }                                                                     \
       }                                                                       \
       else                                                                    \
@@ -612,6 +621,7 @@ void translate_icache_sync() {
           case 0:                                                             \
             /* SMULLS rdlo, rdhi, rm, rs */                                   \
             arm_multiply_long(s64, no, yes);                                  \
+            cycle_count += 2;  /* Between 1 and 4 cycles? */                  \
             break;                                                            \
                                                                               \
           case 1:                                                             \
@@ -649,6 +659,7 @@ void translate_icache_sync() {
         {                                                                     \
           /* SMLAL rd, rm, rs */                                              \
           arm_multiply_long(s64_add, yes, no);                                \
+          cycle_count += 3;  /* Between 2 and 5 cycles? */                    \
         }                                                                     \
       }                                                                       \
       else                                                                    \
@@ -666,6 +677,7 @@ void translate_icache_sync() {
           case 0:                                                             \
             /* SMLALS rdlo, rdhi, rm, rs */                                   \
             arm_multiply_long(s64_add, yes, yes);                             \
+            cycle_count += 3;  /* Between 2 and 5 cycles? */                  \
             break;                                                            \
                                                                               \
           case 1:                                                             \
@@ -1870,6 +1882,7 @@ void translate_icache_sync() {
         case 0x01:                                                            \
           /* MUL rd, rs */                                                    \
           thumb_data_proc(alu_op, muls, reg, rd, rd, rs);                     \
+          cycle_count += 2;  /* Between 1 and 4 extra cycles */               \
           break;                                                              \
                                                                               \
         case 0x02:                                                            \
-- 
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