From fe19474dca84b5d00570e3fb5a04c8a359615f70 Mon Sep 17 00:00:00 2001 From: twinaphex Date: Wed, 10 Dec 2014 01:17:37 +0100 Subject: Add macro parameter 'opcode' to some macros --- x86/x86_emit.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'x86') diff --git a/x86/x86_emit.h b/x86/x86_emit.h index efdceb5..1d4953c 100644 --- a/x86/x86_emit.h +++ b/x86/x86_emit.h @@ -1141,7 +1141,7 @@ typedef enum #define rm_op_imm imm #define arm_data_proc_reg_flags() \ - arm_decode_data_proc_reg(); \ + arm_decode_data_proc_reg(opcode); \ if(flag_status & 0x02) \ { \ generate_load_rm_sh(flags) \ @@ -1152,16 +1152,16 @@ typedef enum } \ #define arm_data_proc_reg() \ - arm_decode_data_proc_reg(); \ + arm_decode_data_proc_reg(opcode); \ generate_load_rm_sh(no_flags) \ #define arm_data_proc_imm() \ - arm_decode_data_proc_imm(); \ + arm_decode_data_proc_imm(opcode); \ ror(imm, imm, imm_ror); \ generate_load_imm(a0, imm) \ #define arm_data_proc_imm_flags() \ - arm_decode_data_proc_imm(); \ + arm_decode_data_proc_imm(opcode); \ if((flag_status & 0x02) && (imm_ror != 0)) \ { \ /* Generate carry flag from integer rotation */ \ @@ -1319,7 +1319,7 @@ void function_cc execute_store_spsr(u32 new_spsr, u32 store_mask) #define arm_psr(op_type, transfer_type, psr_reg) \ { \ - arm_decode_psr_##op_type(); \ + arm_decode_psr_##op_type(opcode); \ arm_psr_##transfer_type(op_type, psr_reg); \ } \ @@ -2196,7 +2196,7 @@ static void function_cc execute_swi(u32 pc) generate_branch() \ #define arm_bx() \ - arm_decode_branchx(); \ + arm_decode_branchx(opcode); \ generate_load_reg(a0, rn); \ generate_indirect_branch_dual(); \ -- cgit v1.2.3