From 6fb0c7a7a53e1eba7a0f5dc5b1ade312a0d76119 Mon Sep 17 00:00:00 2001 From: Toad King Date: Thu, 14 Jun 2012 03:21:06 -0400 Subject: initial pocketsnes commit --- src/2xsaiwin.cpp | 707 + src/3d.h | 100 + src/65c816.h | 123 + src/DSP1_gp32.cpp | 529 + src/Makefile | 241 + src/Makefile.22062010 | 105 + src/Makefile.gp2x | 105 + src/Makefile.last | 99 + src/Makefile.old | 243 + src/Makefile.wiz.OpenWiz | 82 + src/Makefile.wiz.bck | 82 + src/Makefile_giz | 88 + src/VOIMAGE.CPP | 281 + src/VOIMAGE.H | 84 + src/apu.cpp | 1181 ++ src/apu.h | 200 + src/apuaux.cpp | 32 + src/apumem.h | 151 + src/asm_util.S | 85 + src/asmmemfuncs.h | 206 + src/asmout.sh | 37 + src/bsd_mem.h | 2 + src/c4.cpp | 432 + src/c4.h | 114 + src/c4emu.cpp | 1007 + src/caanoo_sdk.c | 806 + src/caanoo_sdk.h | 64 + src/cheats.cpp | 391 + src/cheats.h | 109 + src/cheats2.cpp | 232 + src/clip.cpp | 739 + src/clip.cpp.new | 405 + src/compile.txt | 27 + src/config.c | 39 + src/config.h | 18 + src/copyright.h | 70 + src/cpu.cpp | 170 + src/cpuaddr.h | 325 + src/cpuexec.cpp | 542 + src/cpuexec.h | 235 + src/cpumacro.h | 820 + src/cpuops.cpp | 4265 ++++ src/cpuops.h | 50 + src/data.cpp | 489 + src/debug.h | 63 + src/disk_img.c | 103 + src/disk_img.h | 12 + src/display.h | 86 + src/dma.cpp | 945 + src/dma.h | 51 + src/dsp1.cpp | 1195 ++ src/dsp1.h | 130 + src/dsp1_gp32.h | 244 + src/dsp1emu.c | 1451 ++ src/dsp1emu_fixed.c | 1691 ++ src/dsp1emu_yo.c | 1423 ++ src/dsp2emu.c | 341 + src/dspMixer.s | 837 + src/font.h | 99 + src/frame_skip.cpp | 99 + src/frame_skip.h | 9 + src/fxdbg.cpp | 360 + src/fxemu.cpp | 721 + src/fxemu.h | 178 + src/fxinst.cpp | 1916 ++ src/fxinst.h | 475 + src/fxinst.s | 44480 +++++++++++++++++++++++++++++++++++++++ src/gammatab.h | 22 + src/getset.h | 710 + src/gfx.cpp | 3774 ++++ src/gfx.h | 270 + src/gfx16.cpp | 3445 +++ src/gfx16.cpp.last | 3185 +++ src/gfx16.cpp.old2 | 3201 +++ src/giz_kgsdk.c | 343 + src/giz_kgsdk.h | 58 + src/giz_kgsdkasm.s | 107 + src/giz_sdk_kgsdk.c | 343 + src/giz_sdk_kgsdk.h | 64 + src/globals.cpp | 440 + src/gp2x_highlightbar.c | 341 + src/gp2x_menu_header.c | 983 + src/gp2x_menutile.c | 277 + src/gp2x_sdk.c | 767 + src/gp2x_sdk.h | 68 + src/gp32_func.h | 13 + src/graphics.c | 316 + src/graphics.h | 57 + src/gx.h | 83 + src/imgdecmp.h | 58 + src/imgrendr.h | 270 + src/input.c | 191 + src/ioapi.c | 177 + src/ioapi.h | 75 + src/keycodes.h | 108 + src/language.h | 328 + src/loadzip.cpp | 220 + src/lodepng.c | 5271 +++++ src/lodepng.h | 1851 ++ src/m3d_func.S | 93 + src/main.cpp | 1709 ++ src/memcmp.S | 59 + src/memcpy.S | 496 + src/memmap.cpp | 2782 +++ src/memmap.h | 200 + src/memset.S | 72 + src/menu.c | 2385 +++ src/menu.h | 380 + src/menu_header.bmp | Bin 0 -> 46134 bytes src/menu_header.psp | Bin 0 -> 18587 bytes src/messages.h | 82 + src/minGlue.h | 32 + src/minIni.c | 733 + src/minIni.h | 145 + src/misc.s | 179 + src/missing.h | 114 + src/mmuhack.c | 344 + src/mode7.caanoo.log | 5482 +++++ src/mode7.cpp | 489 + src/mode7.h | 17 + src/mode7.wiz.log | 5280 +++++ src/mode7_t.h | 526 + src/mode7_t.h.gch | Bin 0 -> 1922616 bytes src/mode7_t.h.new | 526 + src/mode7add.cpp | 5 + src/mode7add1_2.cpp | 6 + src/mode7add1_2prio.cpp | 8 + src/mode7addprio.cpp | 5 + src/mode7new.cpp | 439 + src/mode7prio.cpp | 503 + src/mode7prio_t.h | 535 + src/mode7prio_t.h.last | 540 + src/mode7sub.cpp | 6 + src/mode7sub1_2.cpp | 6 + src/mode7sub1_2prio.cpp | 5 + src/mode7subprio.cpp | 6 + src/movie.cpp | 786 + src/movie.h | 146 + src/netplay.h | 282 + src/newres.h | 41 + src/notas | 1 + src/os9x_65c816.s | 4951 +++++ src/os9x_65c816_common.s | 949 + src/os9x_65c816_def.h | 76 + src/os9x_65c816_global.s | 1126 + src/os9x_65c816_global_armv4.s | 6 + src/os9x_65c816_mac_gen.h | 595 + src/os9x_65c816_mac_mem.h | 1599 ++ src/os9x_65c816_mac_op.h | 2408 +++ src/os9x_65c816_opcodes.s | 2976 +++ src/os9x_65c816_spcasm.s | 4927 +++++ src/os9x_65c816_spcasm.s.last | 4927 +++++ src/os9x_65c816_spcc.s | 4990 +++++ src/os9x_asm_cpu.cpp | 255 + src/os9x_asm_cpu.h | 11 + src/osd_disk.c | 45 + src/osnes9xgp_asmfunc.S | 101 + src/out.s | 10697 ++++++++++ src/pixform.h | 272 + src/png.c | 38 + src/png.h | 26 + src/pollux_set.cpp | 380 + src/pollux_set.h | 10 + src/polluxregs.h | 96 + src/port.h | 503 + src/ppu.cpp | 1418 ++ src/ppu.h | 606 + src/ppu_.cpp | 2644 +++ src/ppu_getppu.h | 407 + src/ppu_setppu.h | 1546 ++ src/r.txt | 876 + src/readme.txt | 10 + src/rel/menu_header.bmp | Bin 0 -> 46134 bytes src/rel/readme.txt | 347 + src/rel/snesadvance.dat | 641 + src/rel/warm_2.6.24.ko | Bin 0 -> 86123 bytes src/render8 orr.S | 218 + src/resource.h | 181 + src/rops.cpp | 275 + src/rops.h | 168 + src/rops.h.last | 118 + src/rops.h.old | 118 + src/sa1.cpp | 775 + src/sa1.h | 189 + src/sa1.s | 1 + src/sa1_asm.s | 9 + src/sa1cpu.cpp | 125 + src/sar.h | 132 + src/screenshot.c | 71 + src/screenshot.h | 19 + src/sdd1.cpp | 135 + src/sdd1.h | 48 + src/sdd1emu.cpp | 414 + src/sdd1emu.h | 104 + src/seta.cpp | 107 + src/seta.h | 156 + src/seta010.cpp | 751 + src/seta011.cpp | 233 + src/seta018.cpp | 255 + src/setpcbase.s | 85 + src/snaporig.cpp | 414 + src/snaporig.h | 330 + src/snapshot.cpp | 945 + src/snapshot.h | 63 + src/snapshots/do.sh | 4 + src/snes9x.cpp | 655 + src/snes9x.h | 439 + src/soundux.cpp | 1200 ++ src/soundux.h | 337 + src/spc700.cpp | 2509 +++ src/spc700.h | 139 + src/spc700/Makefile | 13 + src/spc700/Makefile.win | 15 + src/spc700/debug/apu.h | 195 + src/spc700/debug/apumem.h | 222 + src/spc700/debug/port.h | 497 + src/spc700/debug/spc700.cpp | 2600 +++ src/spc700/debug/spc700.h | 172 + src/spc700/spcgen.c | 2164 ++ src/spc700/spcgen.dsp | 88 + src/spc700/spcgen.dsw | 29 + src/spc700/spcgen.ncb | Bin 0 -> 41984 bytes src/spc700/spcgen.opt | Bin 0 -> 53760 bytes src/spc700/spcgen.plg | 32 + src/spc700a.s | 28366 +++++++++++++++++++++++++ src/spc_decode.S | 234 + src/squidgehack.c | 45 + src/squidgehack.h | 15 + src/srtc.cpp | 528 + src/srtc.h | 110 + src/strcmp.S | 50 + src/strlen.S | 61 + src/strncmp.S | 55 + src/sys_cacheflush.S | 29 + src/sys_cacheflush.h | 15 + src/theme.c | 165 + src/theme.h | 32 + src/tile.cpp | 1350 ++ src/tile.h | 314 + src/tile16.cpp | 1920 ++ src/tile16.cpp.bak | 814 + src/tile16.h | 308 + src/tile16_t.h | 519 + src/tile16add.cpp | 48 + src/tile16add1_2.cpp | 48 + src/tile16f_t.h | 340 + src/tile16fadd1_2.cpp | 61 + src/tile16fsub1_2.cpp | 64 + src/tile16noprio.cpp | 407 + src/tile16sub.cpp | 48 + src/tile16sub1_2.cpp | 50 + src/touchscreen.c | 47 + src/touchscreen.h | 10 + src/unzip.c | 1598 ++ src/unzip.h | 356 + src/usbjoy.c | 297 + src/usbjoy.h | 221 + src/warm.cpp | 148 + src/warm.h | 100 + src/wiz_mmuhack.c | 28 + src/wiz_sdk.c | 752 + src/wiz_sdk.h | 64 + src/zip.c | 1218 ++ src/zip.h | 237 + src/zip/do.sh | 4 + 265 files changed, 235166 insertions(+) create mode 100644 src/2xsaiwin.cpp create mode 100644 src/3d.h create mode 100644 src/65c816.h create mode 100644 src/DSP1_gp32.cpp create mode 100644 src/Makefile create mode 100644 src/Makefile.22062010 create mode 100644 src/Makefile.gp2x create mode 100644 src/Makefile.last create mode 100644 src/Makefile.old create mode 100644 src/Makefile.wiz.OpenWiz create mode 100644 src/Makefile.wiz.bck create mode 100644 src/Makefile_giz create mode 100644 src/VOIMAGE.CPP create mode 100644 src/VOIMAGE.H create mode 100644 src/apu.cpp create mode 100644 src/apu.h create mode 100644 src/apuaux.cpp create mode 100644 src/apumem.h create mode 100644 src/asm_util.S create mode 100644 src/asmmemfuncs.h create mode 100644 src/asmout.sh create mode 100644 src/bsd_mem.h create mode 100644 src/c4.cpp create mode 100644 src/c4.h create mode 100644 src/c4emu.cpp create mode 100644 src/caanoo_sdk.c create mode 100644 src/caanoo_sdk.h create mode 100644 src/cheats.cpp create mode 100644 src/cheats.h create mode 100644 src/cheats2.cpp create mode 100644 src/clip.cpp create mode 100644 src/clip.cpp.new create mode 100644 src/compile.txt create mode 100644 src/config.c create mode 100644 src/config.h create mode 100644 src/copyright.h create mode 100644 src/cpu.cpp create mode 100644 src/cpuaddr.h create mode 100644 src/cpuexec.cpp create mode 100644 src/cpuexec.h create mode 100644 src/cpumacro.h create mode 100644 src/cpuops.cpp create mode 100644 src/cpuops.h create mode 100644 src/data.cpp create mode 100644 src/debug.h create mode 100644 src/disk_img.c create mode 100644 src/disk_img.h create mode 100644 src/display.h create mode 100644 src/dma.cpp create mode 100644 src/dma.h create mode 100644 src/dsp1.cpp create mode 100644 src/dsp1.h create mode 100644 src/dsp1_gp32.h create mode 100644 src/dsp1emu.c create mode 100644 src/dsp1emu_fixed.c create mode 100644 src/dsp1emu_yo.c create mode 100644 src/dsp2emu.c create mode 100644 src/dspMixer.s create mode 100644 src/font.h create mode 100644 src/frame_skip.cpp create mode 100644 src/frame_skip.h create mode 100644 src/fxdbg.cpp create mode 100644 src/fxemu.cpp create mode 100644 src/fxemu.h create mode 100644 src/fxinst.cpp create mode 100644 src/fxinst.h create mode 100644 src/fxinst.s create mode 100644 src/gammatab.h create mode 100644 src/getset.h create mode 100644 src/gfx.cpp create mode 100644 src/gfx.h create mode 100644 src/gfx16.cpp create mode 100644 src/gfx16.cpp.last create mode 100644 src/gfx16.cpp.old2 create mode 100644 src/giz_kgsdk.c create mode 100644 src/giz_kgsdk.h create mode 100644 src/giz_kgsdkasm.s create mode 100644 src/giz_sdk_kgsdk.c create mode 100644 src/giz_sdk_kgsdk.h create mode 100644 src/globals.cpp create mode 100644 src/gp2x_highlightbar.c create mode 100644 src/gp2x_menu_header.c create mode 100644 src/gp2x_menutile.c create mode 100644 src/gp2x_sdk.c create mode 100644 src/gp2x_sdk.h create mode 100644 src/gp32_func.h create mode 100644 src/graphics.c create mode 100644 src/graphics.h create mode 100644 src/gx.h create mode 100644 src/imgdecmp.h create mode 100644 src/imgrendr.h create mode 100644 src/input.c create mode 100644 src/ioapi.c create mode 100644 src/ioapi.h create mode 100644 src/keycodes.h create mode 100644 src/language.h create mode 100644 src/loadzip.cpp create mode 100644 src/lodepng.c create mode 100644 src/lodepng.h create mode 100644 src/m3d_func.S create mode 100644 src/main.cpp create mode 100644 src/memcmp.S create mode 100644 src/memcpy.S create mode 100644 src/memmap.cpp create mode 100644 src/memmap.h create mode 100644 src/memset.S create mode 100644 src/menu.c create mode 100644 src/menu.h create mode 100644 src/menu_header.bmp create mode 100644 src/menu_header.psp create mode 100644 src/messages.h create mode 100644 src/minGlue.h create mode 100644 src/minIni.c create mode 100644 src/minIni.h create mode 100644 src/misc.s create mode 100644 src/missing.h create mode 100644 src/mmuhack.c create mode 100644 src/mode7.caanoo.log create mode 100644 src/mode7.cpp create mode 100644 src/mode7.h create mode 100644 src/mode7.wiz.log create mode 100644 src/mode7_t.h create mode 100644 src/mode7_t.h.gch create mode 100644 src/mode7_t.h.new create mode 100644 src/mode7add.cpp create mode 100644 src/mode7add1_2.cpp create mode 100644 src/mode7add1_2prio.cpp create mode 100644 src/mode7addprio.cpp create mode 100644 src/mode7new.cpp create mode 100644 src/mode7prio.cpp create mode 100644 src/mode7prio_t.h create mode 100644 src/mode7prio_t.h.last create mode 100644 src/mode7sub.cpp create mode 100644 src/mode7sub1_2.cpp create mode 100644 src/mode7sub1_2prio.cpp create mode 100644 src/mode7subprio.cpp create mode 100644 src/movie.cpp create mode 100644 src/movie.h create mode 100644 src/netplay.h create mode 100644 src/newres.h create mode 100644 src/notas create mode 100644 src/os9x_65c816.s create mode 100644 src/os9x_65c816_common.s create mode 100644 src/os9x_65c816_def.h create mode 100644 src/os9x_65c816_global.s create mode 100644 src/os9x_65c816_global_armv4.s create mode 100644 src/os9x_65c816_mac_gen.h create mode 100644 src/os9x_65c816_mac_mem.h create mode 100644 src/os9x_65c816_mac_op.h create mode 100644 src/os9x_65c816_opcodes.s create mode 100644 src/os9x_65c816_spcasm.s create mode 100644 src/os9x_65c816_spcasm.s.last create mode 100644 src/os9x_65c816_spcc.s create mode 100644 src/os9x_asm_cpu.cpp create mode 100644 src/os9x_asm_cpu.h create mode 100644 src/osd_disk.c create mode 100644 src/osnes9xgp_asmfunc.S create mode 100644 src/out.s create mode 100644 src/pixform.h create mode 100644 src/png.c create mode 100644 src/png.h create mode 100644 src/pollux_set.cpp create mode 100644 src/pollux_set.h create mode 100644 src/polluxregs.h create mode 100644 src/port.h create mode 100644 src/ppu.cpp create mode 100644 src/ppu.h create mode 100644 src/ppu_.cpp create mode 100644 src/ppu_getppu.h create mode 100644 src/ppu_setppu.h create mode 100644 src/r.txt create mode 100644 src/readme.txt create mode 100644 src/rel/menu_header.bmp create mode 100644 src/rel/readme.txt create mode 100644 src/rel/snesadvance.dat create mode 100644 src/rel/warm_2.6.24.ko create mode 100644 src/render8 orr.S create mode 100644 src/resource.h create mode 100644 src/rops.cpp create mode 100644 src/rops.h create mode 100644 src/rops.h.last create mode 100644 src/rops.h.old create mode 100644 src/sa1.cpp create mode 100644 src/sa1.h create mode 100644 src/sa1.s create mode 100644 src/sa1_asm.s create mode 100644 src/sa1cpu.cpp create mode 100644 src/sar.h create mode 100644 src/screenshot.c create mode 100644 src/screenshot.h create mode 100644 src/sdd1.cpp create mode 100644 src/sdd1.h create mode 100644 src/sdd1emu.cpp create mode 100644 src/sdd1emu.h create mode 100644 src/seta.cpp create mode 100644 src/seta.h create mode 100644 src/seta010.cpp create mode 100644 src/seta011.cpp create mode 100644 src/seta018.cpp create mode 100644 src/setpcbase.s create mode 100644 src/snaporig.cpp create mode 100644 src/snaporig.h create mode 100644 src/snapshot.cpp create mode 100644 src/snapshot.h create mode 100644 src/snapshots/do.sh create mode 100644 src/snes9x.cpp create mode 100644 src/snes9x.h create mode 100644 src/soundux.cpp create mode 100644 src/soundux.h create mode 100644 src/spc700.cpp create mode 100644 src/spc700.h create mode 100644 src/spc700/Makefile create mode 100644 src/spc700/Makefile.win create mode 100644 src/spc700/debug/apu.h create mode 100644 src/spc700/debug/apumem.h create mode 100644 src/spc700/debug/port.h create mode 100644 src/spc700/debug/spc700.cpp create mode 100644 src/spc700/debug/spc700.h create mode 100644 src/spc700/spcgen.c create mode 100644 src/spc700/spcgen.dsp create mode 100644 src/spc700/spcgen.dsw create mode 100644 src/spc700/spcgen.ncb create mode 100644 src/spc700/spcgen.opt create mode 100644 src/spc700/spcgen.plg create mode 100644 src/spc700a.s create mode 100644 src/spc_decode.S create mode 100644 src/squidgehack.c create mode 100644 src/squidgehack.h create mode 100644 src/srtc.cpp create mode 100644 src/srtc.h create mode 100644 src/strcmp.S create mode 100644 src/strlen.S create mode 100644 src/strncmp.S create mode 100644 src/sys_cacheflush.S create mode 100644 src/sys_cacheflush.h create mode 100644 src/theme.c create mode 100644 src/theme.h create mode 100644 src/tile.cpp create mode 100644 src/tile.h create mode 100644 src/tile16.cpp create mode 100644 src/tile16.cpp.bak create mode 100644 src/tile16.h create mode 100644 src/tile16_t.h create mode 100644 src/tile16add.cpp create mode 100644 src/tile16add1_2.cpp create mode 100644 src/tile16f_t.h create mode 100644 src/tile16fadd1_2.cpp create mode 100644 src/tile16fsub1_2.cpp create mode 100644 src/tile16noprio.cpp create mode 100644 src/tile16sub.cpp create mode 100644 src/tile16sub1_2.cpp create mode 100644 src/touchscreen.c create mode 100644 src/touchscreen.h create mode 100644 src/unzip.c create mode 100644 src/unzip.h create mode 100644 src/usbjoy.c create mode 100644 src/usbjoy.h create mode 100644 src/warm.cpp create mode 100644 src/warm.h create mode 100644 src/wiz_mmuhack.c create mode 100644 src/wiz_sdk.c create mode 100644 src/wiz_sdk.h create mode 100644 src/zip.c create mode 100644 src/zip.h create mode 100644 src/zip/do.sh (limited to 'src') diff --git a/src/2xsaiwin.cpp b/src/2xsaiwin.cpp new file mode 100644 index 0000000..fbff856 --- /dev/null +++ b/src/2xsaiwin.cpp @@ -0,0 +1,707 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +//#define MMX + +#if !defined(_SNESPPC) && !defined(__GIZ__) && !defined(__GP2X__) && !defined(__WIZ__) +#include "snes9x/snes9x.h" +#include "snes9x/port.h" +#include "snes9x/gfx.h" +#else +#include "snes9x.h" +#include "port.h" +#include "gfx.h" +#endif + +#ifdef MMX +EXTERN_C void _2xSaILine (uint8 *srcPtr, uint8 *deltaPtr, uint32 srcPitch, uint32 width, + uint8 *dstPtr, uint32 dstPitch); +EXTERN_C void _2xSaISuperEagleLine (uint8 *srcPtr, uint8 *deltaPtr, uint32 srcPitch, uint32 width, + uint8 *dstPtr, uint32 dstPitch); +EXTERN_C int Init_2xSaIMMX (uint32 BitFormat); +#endif + +bool mmx_cpu = false; + +static uint32 colorMask = 0xF7DEF7DE; +static uint32 lowPixelMask = 0x08210821; +static uint32 qcolorMask = 0xE79CE79C; +static uint32 qlowpixelMask = 0x18631863; + + +int Init_2xSaI(uint32 BitFormat) +{ + if (BitFormat == 565) + { + colorMask = 0xF7DEF7DE; + lowPixelMask = 0x08210821; + qcolorMask = 0xE79CE79C; + qlowpixelMask = 0x18631863; + } + else + if (BitFormat == 555) + { + colorMask = 0x7BDE7BDE; + lowPixelMask = 0x04210421; + qcolorMask = 0x739C739C; + qlowpixelMask = 0x0C630C63; + } + else + { + return 0; + } +#ifdef MMX + Init_2xSaIMMX(BitFormat); +#endif + return 1; +} + +STATIC inline int GetResult1(uint32 A, uint32 B, uint32 C, uint32 D, uint32 E) +{ + int x = 0; + int y = 0; + int r = 0; + if (A == C) x+=1; else if (B == C) y+=1; + if (A == D) x+=1; else if (B == D) y+=1; + if (x <= 1) r+=1; + if (y <= 1) r-=1; + return r; +} + +STATIC inline int GetResult2(uint32 A, uint32 B, uint32 C, uint32 D, uint32 E) +{ + int x = 0; + int y = 0; + int r = 0; + if (A == C) x+=1; else if (B == C) y+=1; + if (A == D) x+=1; else if (B == D) y+=1; + if (x <= 1) r-=1; + if (y <= 1) r+=1; + return r; +} + + +STATIC inline int GetResult(uint32 A, uint32 B, uint32 C, uint32 D) +{ + int x = 0; + int y = 0; + int r = 0; + if (A == C) x+=1; else if (B == C) y+=1; + if (A == D) x+=1; else if (B == D) y+=1; + if (x <= 1) r+=1; + if (y <= 1) r-=1; + return r; +} + + +STATIC inline uint32 INTERPOLATE(uint32 A, uint32 B) +{ + if (A !=B) + { + return ( ((A & colorMask) >> 1) + ((B & colorMask) >> 1) + (A & B & lowPixelMask) ); + } + else return A; +} + + +STATIC inline uint32 Q_INTERPOLATE(uint32 A, uint32 B, uint32 C, uint32 D) +{ + register uint32 x = ((A & qcolorMask) >> 2) + + ((B & qcolorMask) >> 2) + + ((C & qcolorMask) >> 2) + + ((D & qcolorMask) >> 2); + register uint32 y = (A & qlowpixelMask) + + (B & qlowpixelMask) + + (C & qlowpixelMask) + + (D & qlowpixelMask); + y = (y>>2) & qlowpixelMask; + return x+y; +} + + + + +#define HOR +#define VER +void Super2xSaI(uint8 *srcPtr, uint32 srcPitch, + uint8 *deltaPtr, + uint8 *dstPtr, uint32 dstPitch, int width, int height) +{ + uint32 *dP; + uint16 *bP; + +#ifdef MMX_BLA //no MMX version yet + if (cpu_mmx && width != 512) + { + for (height; height; height-=1) + { + bP = (uint16 *) srcPtr; + xP = (uint16 *) deltaPtr; + dP = (uint32 *) dstPtr; + _2xSaISuperEagleLine ((uint8 *) bP, (uint8 *) xP, srcPitch, width, (uint8 *) dP, dstPitch); + dstPtr += dstPitch << 1; + srcPtr += srcPitch; + deltaPtr += srcPitch; + } + } + else + { +#endif + uint32 Nextline = srcPitch >> 1; + + for (height; height; height-=1) + { + bP = (uint16 *) srcPtr; + dP = (uint32 *) dstPtr; + for (uint32 finish = width; finish; finish -= 1 ) + { + uint32 color4, color5, color6; + uint32 color1, color2, color3; + uint32 colorA0, colorA1, colorA2, colorA3, + colorB0, colorB1, colorB2, colorB3, + colorS1, colorS2; + uint32 product1a, product1b, + product2a, product2b; + +//--------------------------------------- B1 B2 +// 4 5 6 S2 +// 1 2 3 S1 +// A1 A2 + + colorB0 = *(bP- Nextline - 1); + colorB1 = *(bP- Nextline); + colorB2 = *(bP- Nextline + 1); + colorB3 = *(bP- Nextline + 2); + + color4 = *(bP - 1); + color5 = *(bP); + color6 = *(bP + 1); + colorS2 = *(bP + 2); + + color1 = *(bP + Nextline - 1); + color2 = *(bP + Nextline); + color3 = *(bP + Nextline + 1); + colorS1 = *(bP + Nextline + 2); + + colorA0 = *(bP + Nextline + Nextline - 1); + colorA1 = *(bP + Nextline + Nextline); + colorA2 = *(bP + Nextline + Nextline + 1); + colorA3 = *(bP + Nextline + Nextline + 2); + + +//-------------------------------------- + if (color2 == color6 && color5 != color3) + { + product2b = product1b = color2; + } + else + if (color5 == color3 && color2 != color6) + { + product2b = product1b = color5; + } + else + if (color5 == color3 && color2 == color6 && color5 != color6) + { + register int r = 0; + + r += GetResult (color6, color5, color1, colorA1); + r += GetResult (color6, color5, color4, colorB1); + r += GetResult (color6, color5, colorA2, colorS1); + r += GetResult (color6, color5, colorB2, colorS2); + + if (r > 0) + product2b = product1b = color6; + else + if (r < 0) + product2b = product1b = color5; + else + { + product2b = product1b = INTERPOLATE (color5, color6); + } + + } + else + { + +#ifdef VER + if (color6 == color3 && color3 == colorA1 && color2 != colorA2 && color3 != colorA0) + product2b = Q_INTERPOLATE (color3, color3, color3, color2); + else + if (color5 == color2 && color2 == colorA2 && colorA1 != color3 && color2 != colorA3) + product2b = Q_INTERPOLATE (color2, color2, color2, color3); + else +#endif + product2b = INTERPOLATE (color2, color3); + +#ifdef VER + if (color6 == color3 && color6 == colorB1 && color5 != colorB2 && color6 != colorB0) + product1b = Q_INTERPOLATE (color6, color6, color6, color5); + else + if (color5 == color2 && color5 == colorB2 && colorB1 != color6 && color5 != colorB3) + product1b = Q_INTERPOLATE (color6, color5, color5, color5); + else +#endif + product1b = INTERPOLATE (color5, color6); + } + +#ifdef HOR + if (color5 == color3 && color2 != color6 && color4 == color5 && color5 != colorA2) + product2a = INTERPOLATE (color2, color5); + else + if (color5 == color1 && color6 == color5 && color4 != color2 && color5 != colorA0) + product2a = INTERPOLATE(color2, color5); + else +#endif + product2a = color2; + +#ifdef HOR + if (color2 == color6 && color5 != color3 && color1 == color2 && color2 != colorB2) + product1a = INTERPOLATE (color2, color5); + else + if (color4 == color2 && color3 == color2 && color1 != color5 && color2 != colorB0) + product1a = INTERPOLATE(color2, color5); + else +#endif + product1a = color5; + + + product1a = product1a | (product1b << 16); + product2a = product2a | (product2b << 16); + + *(dP) = product1a; + *(dP+(dstPitch>>2)) = product2a; + + bP += 1; + dP += 1; + }//end of for ( finish= width etc..) + + dstPtr += dstPitch << 1; + srcPtr += srcPitch; + deltaPtr += srcPitch; + }; //endof: for (height; height; height--) +#ifdef MMX_BLA + } +#endif +} + + + + + + +/*ONLY use with 640x480x16 or higher resolutions*/ +/*Only use this if 2*width * 2*height fits on the current screen*/ +void SuperEagle(uint8 *srcPtr, uint32 srcPitch, + uint8 *deltaPtr, + uint8 *dstPtr, uint32 dstPitch, int width, int height) +{ + uint32 *dP; + uint16 *bP; +#if !defined(_SNESPPC) && !defined(__GIZ__) && !defined(__GP2X__) && !defined(__WIZ__) + uint16 *xP; +#endif + +#ifdef MMX + if (mmx_cpu && width != 512) + { + for (height; height; height-=1) + { + bP = (uint16 *) srcPtr; + xP = (uint16 *) deltaPtr; + dP = (uint32 *) dstPtr; + _2xSaISuperEagleLine ((uint8 *) bP, (uint8 *) xP, srcPitch, width, (uint8 *)dP, dstPitch); + dstPtr += dstPitch << 1; + srcPtr += srcPitch; + deltaPtr += srcPitch; + } + } + else + { +#endif + uint32 Nextline = srcPitch >> 1; + + for (height; height; height-=1) + { + bP = (uint16 *) srcPtr; + dP = (uint32 *) dstPtr; + for (uint32 finish = width; finish; finish -= 1 ) + { + + uint32 color4, color5, color6; + uint32 color1, color2, color3; + uint32 colorA0, colorA1, colorA2, colorA3, + colorB0, colorB1, colorB2, colorB3, + colorS1, colorS2; + uint32 product1a, product1b, + product2a, product2b; + + colorB0 = *(bP- Nextline - 1); + colorB1 = *(bP- Nextline); + colorB2 = *(bP- Nextline + 1); + colorB3 = *(bP- Nextline + 2); + + color4 = *(bP - 1); + color5 = *(bP); + color6 = *(bP + 1); + colorS2 = *(bP + 2); + + color1 = *(bP + Nextline - 1); + color2 = *(bP + Nextline); + color3 = *(bP + Nextline + 1); + colorS1 = *(bP + Nextline + 2); + + colorA0 = *(bP + Nextline + Nextline - 1); + colorA1 = *(bP + Nextline + Nextline); + colorA2 = *(bP + Nextline + Nextline + 1); + colorA3 = *(bP + Nextline + Nextline + 2); + + + //-------------------------------------- + if (color2 == color6 && color5 != color3) + { + product1b = product2a = color2; + if ((color1 == color2 && color6 == colorS2) || + (color2 == colorA1 && color6 == colorB2)) + { + product1a = INTERPOLATE (color2, color5); + product1a = INTERPOLATE (color2, product1a); + product2b = INTERPOLATE (color2, color3); + product2b = INTERPOLATE (color2, product2b); +// product1a = color2; +// product2b = color2; + } + else + { + product1a = INTERPOLATE (color5, color6); + product2b = INTERPOLATE (color2, color3); + } + } + else + if (color5 == color3 && color2 != color6) + { + product2b = product1a = color5; + if ((colorB1 == color5 && color3 == colorA2) || + (color4 == color5 && color3 == colorS1)) + { + product1b = INTERPOLATE (color5, color6); + product1b = INTERPOLATE (color5, product1b); + product2a = INTERPOLATE (color5, color2); + product2a = INTERPOLATE (color5, product2a); +// product1b = color5; +// product2a = color5; + } + else + { + product1b = INTERPOLATE (color5, color6); + product2a = INTERPOLATE (color2, color3); + } + } + else + if (color5 == color3 && color2 == color6 && color5 != color6) + { + register int r = 0; + + r += GetResult (color6, color5, color1, colorA1); + r += GetResult (color6, color5, color4, colorB1); + r += GetResult (color6, color5, colorA2, colorS1); + r += GetResult (color6, color5, colorB2, colorS2); + + if (r > 0) + { + product1b = product2a = color2; + product1a = product2b = INTERPOLATE (color5, color6); + } + else + if (r < 0) + { + product2b = product1a = color5; + product1b = product2a = INTERPOLATE (color5, color6); + } + else + { + product2b = product1a = color5; + product1b = product2a = color2; + } + } + else + { + + if ((color2 == color5) || (color3 == color6)) + { + product1a = color5; + product2a = color2; + product1b = color6; + product2b = color3; + + } + else + { + product1b = product1a = INTERPOLATE (color5, color6); + product1a = INTERPOLATE (color5, product1a); + product1b = INTERPOLATE (color6, product1b); + + product2a = product2b = INTERPOLATE (color2, color3); + product2a = INTERPOLATE (color2, product2a); + product2b = INTERPOLATE (color3, product2b); + } + } + + + product1a = product1a | (product1b << 16); + product2a = product2a | (product2b << 16); + + *(dP) = product1a; + *(dP+(dstPitch>>2)) = product2a; + + bP += 1; + dP += 1; + }//end of for ( finish= width etc..) + + dstPtr += dstPitch << 1; + srcPtr += srcPitch; + deltaPtr += srcPitch; + }; //endof: for (height; height; height--) +#ifdef MMX + } +#endif +} + + + +/*ONLY use with 640x480x16 or higher resolutions*/ +/*Only use this if 2*width * 2*height fits on the current screen*/ +void _2xSaI(uint8 *srcPtr, uint32 srcPitch, + uint8 *deltaPtr, + uint8 *dstPtr, uint32 dstPitch, int width, int height) +{ + uint32 *dP; + uint16 *bP; +#if !defined(_SNESPPC) && !defined(__GIZ__) && !defined(__GP2X__) && !defined(__WIZ__) + uint16 *xP; +#endif + +#ifdef MMX + if (mmx_cpu && width != 512) + { + for (height; height; height-=1) + { + + bP = (uint16 *) srcPtr; + xP = (uint16 *) deltaPtr; + dP = (uint32 *) dstPtr; + _2xSaILine ((uint8 *) bP, (uint8 *) xP, srcPitch, width, (uint8 *)dP, dstPitch); + dstPtr += dstPitch << 1; + srcPtr += srcPitch; + deltaPtr += srcPitch; + } + } + else + { +#endif + uint32 Nextline = srcPitch >> 1; + + for (height; height; height-=1) + { + bP = (uint16 *) srcPtr; + dP = (uint32 *) dstPtr; + for (uint32 finish = width; finish; finish -= 1 ) + { + + + register uint32 colorA, colorB; + uint32 colorC, colorD, + colorE, colorF, colorG, colorH, + colorI, colorJ, colorK, colorL, + colorM, colorN, colorO, colorP; + uint32 product, product1, product2; + + +//--------------------------------------- +// Map of the pixels: I|E F|J +// G|A B|K +// H|C D|L +// M|N O|P + colorI = *(bP- Nextline - 1); + colorE = *(bP- Nextline); + colorF = *(bP- Nextline + 1); + colorJ = *(bP- Nextline + 2); + + colorG = *(bP - 1); + colorA = *(bP); + colorB = *(bP + 1); + colorK = *(bP + 2); + + colorH = *(bP + Nextline - 1); + colorC = *(bP + Nextline); + colorD = *(bP + Nextline + 1); + colorL = *(bP + Nextline + 2); + + colorM = *(bP + Nextline + Nextline - 1); + colorN = *(bP + Nextline + Nextline); + colorO = *(bP + Nextline + Nextline + 1); + colorP = *(bP + Nextline + Nextline + 2); + + if ((colorA == colorD) && (colorB != colorC)) + { + if ( ((colorA == colorE) && (colorB == colorL)) || + ((colorA == colorC) && (colorA == colorF) && (colorB != colorE) && (colorB == colorJ)) ) + { + product = colorA; + } + else + { + product = INTERPOLATE(colorA, colorB); + } + + if (((colorA == colorG) && (colorC == colorO)) || + ((colorA == colorB) && (colorA == colorH) && (colorG != colorC) && (colorC == colorM)) ) + { + product1 = colorA; + } + else + { + product1 = INTERPOLATE(colorA, colorC); + } + product2 = colorA; + } + else + if ((colorB == colorC) && (colorA != colorD)) + { + if (((colorB == colorF) && (colorA == colorH)) || + ((colorB == colorE) && (colorB == colorD) && (colorA != colorF) && (colorA == colorI)) ) + { + product = colorB; + } + else + { + product = INTERPOLATE(colorA, colorB); + } + + if (((colorC == colorH) && (colorA == colorF)) || + ((colorC == colorG) && (colorC == colorD) && (colorA != colorH) && (colorA == colorI)) ) + { + product1 = colorC; + } + else + { + product1 = INTERPOLATE(colorA, colorC); + } + product2 = colorB; + } + else + if ((colorA == colorD) && (colorB == colorC)) + { + if (colorA == colorB) + { + product = colorA; + product1 = colorA; + product2 = colorA; + } + else + { + register int r = 0; + product1 = INTERPOLATE(colorA, colorC); + product = INTERPOLATE(colorA, colorB); + + r += GetResult1 (colorA, colorB, colorG, colorE, colorI); + r += GetResult2 (colorB, colorA, colorK, colorF, colorJ); + r += GetResult2 (colorB, colorA, colorH, colorN, colorM); + r += GetResult1 (colorA, colorB, colorL, colorO, colorP); + + if (r > 0) + product2 = colorA; + else + if (r < 0) + product2 = colorB; + else + { + product2 = Q_INTERPOLATE(colorA, colorB, colorC, colorD); + } + } + } + else + { + product2 = Q_INTERPOLATE(colorA, colorB, colorC, colorD); + + if ((colorA == colorC) && (colorA == colorF) && (colorB != colorE) && (colorB == colorJ)) + { + product = colorA; + } + else + if ((colorB == colorE) && (colorB == colorD) && (colorA != colorF) && (colorA == colorI)) + { + product = colorB; + } + else + { + product = INTERPOLATE(colorA, colorB); + } + + if ((colorA == colorB) && (colorA == colorH) && (colorG != colorC) && (colorC == colorM)) + { + product1 = colorA; + } + else + if ((colorC == colorG) && (colorC == colorD) && (colorA != colorH) && (colorA == colorI)) + { + product1 = colorC; + } + else + { + product1 = INTERPOLATE(colorA, colorC); + } + } + product = colorA | (product << 16); + product1 = product1 | (product2 << 16); + *(dP) = product; + *(dP+(dstPitch>>2)) = product1; + + bP += 1; + dP += 1; + }//end of for ( finish= width etc..) + + dstPtr += dstPitch << 1; + srcPtr += srcPitch; + deltaPtr += srcPitch; + }; //endof: for (height; height; height--) +#ifdef MMX + } +#endif +} diff --git a/src/3d.h b/src/3d.h new file mode 100644 index 0000000..6585fa7 --- /dev/null +++ b/src/3d.h @@ -0,0 +1,100 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _3D_H_ +#define _3D_H_ + +#if defined(USE_OPENGL) +#include +#include + +#ifdef __linux__ +//#include +#endif + +typedef struct +{ + bool8 packed_pixels_extension_present; + bool8 draw_cube; + uint32 version; + // Texture format + GLint internal_format; + GLint format; + GLint type; + + GLint max_texture_size;// 256 or 512 + GLint texture_size; + uint32 num_textures; // 1 if max_texture_size == 256, 2 otherwise + GLuint textures [2]; +} OpenGLData; + +extern OpenGLData OpenGL; + +bool8 S9xOpenGLInit (); +bool8 S9xOpenGLInit2 (); +void S9xOpenGLPutImage (int width, int height); +void S9xOpenGLDeinit (); + +#endif + +#ifdef USE_GLIDE +//#include + +typedef struct +{ + bool8 voodoo_present; + GrVertex sq[4]; + GrTexInfo texture; + int32 texture_mem_size; + int32 texture_mem_start; + float x_offset, y_offset; + float x_scale, y_scale; + float voodoo_width; + float voodoo_height; +} GlideData; + +extern GlideData Glide; +bool8 S9xGlideEnable (bool8 enable); +void S9xGlideDeinit (); +bool8 S9xGlideInit (); +bool8 S9xVoodooInitialise (); +#endif + +#endif diff --git a/src/65c816.h b/src/65c816.h new file mode 100644 index 0000000..aa251dc --- /dev/null +++ b/src/65c816.h @@ -0,0 +1,123 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _65c816_h_ +#define _65c816_h_ + +#define AL A.B.l +#define AH A.B.h +#define XL X.B.l +#define XH X.B.h +#define YL Y.B.l +#define YH Y.B.h +#define SL S.B.l +#define SH S.B.h +#define DL D.B.l +#define DH D.B.h +#define PL P.B.l +#define PH P.B.h + +#define Carry 1 +#define Zero 2 +#define IRQ 4 +#define Decimal 8 +#define IndexFlag 16 +#define MemoryFlag 32 +#define Overflow 64 +#define Negative 128 +#define Emulation 256 + +#define ClearCarry() (ICPU._Carry = 0) +#define SetCarry() (ICPU._Carry = 1) +#define SetZero() (ICPU._Zero = 0) +#define ClearZero() (ICPU._Zero = 1) +#define SetIRQ() (Registers.PL |= IRQ) +#define ClearIRQ() (Registers.PL &= ~IRQ) +#define SetDecimal() (Registers.PL |= Decimal) +#define ClearDecimal() (Registers.PL &= ~Decimal) +#define SetIndex() (Registers.PL |= IndexFlag) +#define ClearIndex() (Registers.PL &= ~IndexFlag) +#define SetMemory() (Registers.PL |= MemoryFlag) +#define ClearMemory() (Registers.PL &= ~MemoryFlag) +#define SetOverflow() (ICPU._Overflow = 1) +#define ClearOverflow() (ICPU._Overflow = 0) +#define SetNegative() (ICPU._Negative = 0x80) +#define ClearNegative() (ICPU._Negative = 0) + +#define CheckZero() (ICPU._Zero == 0) +#define CheckCarry() (ICPU._Carry) +#define CheckIRQ() (Registers.PL & IRQ) +#define CheckDecimal() (Registers.PL & Decimal) +#define CheckIndex() (Registers.PL & IndexFlag) +#define CheckMemory() (Registers.PL & MemoryFlag) +#define CheckOverflow() (ICPU._Overflow) +#define CheckNegative() (ICPU._Negative & 0x80) +#define CheckEmulation() (Registers.P.W & Emulation) + +#define ClearFlags(f) (Registers.P.W &= ~(f)) +#define SetFlags(f) (Registers.P.W |= (f)) +#define CheckFlag(f) (Registers.PL & (f)) + +typedef union +{ +#ifdef LSB_FIRST + struct { uint8 l,h; } PACKING B; +#else + struct { uint8 h,l; } PACKING B; +#endif + uint16 W; +} ALIGN_BY_ONE pair; + +struct SRegisters{ + uint8 PB; + uint8 DB; + pair P; + pair A; + pair D; + pair X; + pair S; + pair Y; + uint16 PC; +} PACKING; + +#define Registers CPU.Regs +//EXTERN_C struct SRegisters Registers; + +#endif diff --git a/src/DSP1_gp32.cpp b/src/DSP1_gp32.cpp new file mode 100644 index 0000000..a38763e --- /dev/null +++ b/src/DSP1_gp32.cpp @@ -0,0 +1,529 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" +#include "dsp1.h" +#include "missing.h" +#include "memmap.h" +#include + +#include "dsp1emu_gp32.c" + +void S9xInitDSP1 () +{ + static bool8 init = FALSE; + + if (!init) + { + InitDSP (); + init = TRUE; + } +} + +void S9xResetDSP1 () +{ + S9xInitDSP1 (); + + DSP1.waiting4command = TRUE; + DSP1.in_count = 0; + DSP1.out_count = 0; + DSP1.in_index = 0; + DSP1.out_index = 0; + DSP1.first_parameter = TRUE; +} + +uint8 S9xGetDSP (uint16 address) +{ + uint8 t; + +#ifdef DEBUGGER + if (Settings.TraceDSP) + { + sprintf (String, "DSP read: 0x%04X", address); + S9xMessage (S9X_TRACE, S9X_TRACE_DSP1, String); + } +#endif + if ((address & 0xf000) == 0x6000 || + (address >= 0x8000 && address < 0xc000)) + { + if (DSP1.out_count) + { + if ((address & 1) == 0) + t = (uint8) DSP1.output [DSP1.out_index]; + else + { + t = (uint8) (DSP1.output [DSP1.out_index] >> 8); + DSP1.out_index++; + if (--DSP1.out_count == 0) + { + if (DSP1.command == 0x1a || DSP1.command == 0x0a) + { + DSPOp0A (); + DSP1.out_count = 4; + DSP1.out_index = 0; + DSP1.output [0] = Op0AA; + DSP1.output [1] = Op0AB; + DSP1.output [2] = Op0AC; + DSP1.output [3] = Op0AD; + } + } + DSP1.waiting4command = TRUE; + } + } + else + { + // Top Gear 3000 requires this value.... + t = 0xff; + } + } + else + t = 0x80; + + return (t); +} + +void S9xSetDSP (uint8 byte, uint16 address) +{ +#ifdef DEBUGGER + missing.unknowndsp_write = address; + if (Settings.TraceDSP) + { + sprintf (String, "DSP write: 0x%04X=0x%02X", address, byte); + S9xMessage (S9X_TRACE, S9X_TRACE_DSP1, String); + } +#endif + if ((address & 0xf000) == 0x6000 || + (address >= 0x8000 && address < 0xc000)) + { + if ((address & 1) == 0) + { + if (DSP1.waiting4command) + { + DSP1.command = byte; + DSP1.in_index = 0; + DSP1.waiting4command = FALSE; + DSP1.first_parameter = TRUE; + + // Mario Kart uses 0x00, 0x02, 0x06, 0x0c, 0x28, 0x0a + switch (byte) + { + case 0x00: DSP1.in_count = 2; break; + case 0x10: DSP1.in_count = 2; break; + case 0x04: DSP1.in_count = 2; break; + case 0x08: DSP1.in_count = 3; break; + case 0x18: DSP1.in_count = 4; break; + case 0x28: DSP1.in_count = 3; break; + case 0x0c: DSP1.in_count = 3; break; + case 0x1c: DSP1.in_count = 6; break; + case 0x02: DSP1.in_count = 7; break; + case 0x0a: DSP1.in_count = 1; break; + case 0x1a: DSP1.in_count = 1; break; + case 0x06: DSP1.in_count = 3; break; + case 0x0e: DSP1.in_count = 2; break; + case 0x01: DSP1.in_count = 4; break; + case 0x11: DSP1.in_count = 4; break; + case 0x21: DSP1.in_count = 4; break; + case 0x0d: DSP1.in_count = 3; break; + case 0x1d: DSP1.in_count = 3; break; + case 0x2d: DSP1.in_count = 3; break; + case 0x03: DSP1.in_count = 3; break; + case 0x13: DSP1.in_count = 3; break; + case 0x23: DSP1.in_count = 3; break; + case 0x0b: DSP1.in_count = 3; break; + case 0x1b: DSP1.in_count = 3; break; + case 0x2b: DSP1.in_count = 3; break; + case 0x14: DSP1.in_count = 6; break; +// case 0x80: DSP1.in_count = 2; break; + + default: + case 0x80: + DSP1.in_count = 0; + DSP1.waiting4command = TRUE; + DSP1.first_parameter = TRUE; + break; + } + } + else + { + DSP1.parameters [DSP1.in_index] = byte; + DSP1.first_parameter = FALSE; + } + } + else + { + if (DSP1.waiting4command || + (DSP1.first_parameter && byte == 0x80)) + { + DSP1.waiting4command = TRUE; + DSP1.first_parameter = FALSE; + } + else + if (DSP1.first_parameter) + { + } + else + { + if (DSP1.in_count) + { + DSP1.parameters [DSP1.in_index] |= (byte << 8); + if (--DSP1.in_count == 0) + { + // Actually execute the command + DSP1.waiting4command = TRUE; + DSP1.out_index = 0; + switch (DSP1.command) + { + case 0x00: // Multiple + Op00Multiplicand = (int16) DSP1.parameters [0]; + Op00Multiplier = (int16) DSP1.parameters [1]; + + DSPOp00 (); + + DSP1.out_count = 1; + DSP1.output [0] = Op00Result; + break; + + case 0x10: // Inverse + Op10Coefficient = (int16) DSP1.parameters [0]; + Op10Exponent = (int16) DSP1.parameters [1]; + + DSPOp10 (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint16) (int16) Op10CoefficientR; + DSP1.output [1] = (uint16) (int16) Op10ExponentR; + break; + + case 0x04: // Sin and Cos of angle + Op04Angle = (int16) DSP1.parameters [0]; + Op04Radius = (uint16) DSP1.parameters [1]; + + DSPOp04 (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint16) Op04Sin; + DSP1.output [1] = (uint16) Op04Cos; + break; + + case 0x08: // Radius + Op08X = (int16) DSP1.parameters [0]; + Op08Y = (int16) DSP1.parameters [1]; + Op08Z = (int16) DSP1.parameters [2]; + + DSPOp08 (); + + DSP1.out_count = 2; + DSP1.output [0] = (int16) Op08Ll; + DSP1.output [1] = (int16) Op08Lh; + break; + + case 0x18: // Range + + Op18X = (int16) DSP1.parameters [0]; + Op18Y = (int16) DSP1.parameters [1]; + Op18Z = (int16) DSP1.parameters [2]; + Op18R = (int16) DSP1.parameters [3]; + + DSPOp18 (); + + DSP1.out_count = 1; + DSP1.output [0] = Op18D; + break; + + case 0x28: // Distance (vector length) + Op28X = (int16) DSP1.parameters [0]; + Op28Y = (int16) DSP1.parameters [1]; + Op28Z = (int16) DSP1.parameters [2]; + + DSPOp28 (); + + DSP1.out_count = 1; + DSP1.output [0] = (uint16) Op28R; + break; + + case 0x0c: // Rotate (2D rotate) + Op0CA = (int16) DSP1.parameters [0]; + Op0CX1 = (int16) DSP1.parameters [1]; + Op0CY1 = (int16) DSP1.parameters [2]; + + DSPOp0C (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint16) Op0CX2; + DSP1.output [1] = (uint16) Op0CY2; + break; + + case 0x1c: // Polar (3D rotate) + Op1CZ = DSP1.parameters [0]; + Op1CX = DSP1.parameters [1]; + Op1CY = DSP1.parameters [2]; + Op1CXBR = DSP1.parameters [3]; + Op1CYBR = DSP1.parameters [4]; + Op1CZBR = DSP1.parameters [5]; + + DSPOp1C (); + + DSP1.out_count = 3; + DSP1.output [0] = (uint16) Op1CXAR; + DSP1.output [1] = (uint16) Op1CYAR; + DSP1.output [2] = (uint16) Op1CZAR; + break; + + case 0x02: // Parameter (Projection) + Op02FX = DSP1.parameters [0]; + Op02FY = DSP1.parameters [1]; + Op02FZ = DSP1.parameters [2]; + Op02LFE = DSP1.parameters [3]; + Op02LES = DSP1.parameters [4]; + Op02AAS = DSP1.parameters [5]; + Op02AZS = DSP1.parameters [6]; + + DSPOp02 (); + + DSP1.out_count = 4; + DSP1.output [0] = Op02VOF; + DSP1.output [1] = Op02VVA; + DSP1.output [2] = Op02CX; + DSP1.output [3] = Op02CY; + break; + + case 0x1a: // Raster mode 7 matrix data + case 0x0a: + Op0AVS = DSP1.parameters [0]; + + DSPOp0A (); + + DSP1.out_count = 4; + DSP1.output [0] = Op0AA; + DSP1.output [1] = Op0AB; + DSP1.output [2] = Op0AC; + DSP1.output [3] = Op0AD; + break; + + case 0x06: // Project object + Op06X = (int16) DSP1.parameters [0]; + Op06Y = (int16) DSP1.parameters [1]; + Op06Z = (int16) DSP1.parameters [2]; + + DSPOp06 (); + + DSP1.out_count = 3; + DSP1.output [0] = Op06H; + DSP1.output [1] = Op06V; + DSP1.output [2] = Op06S; + break; + + case 0x0e: // Target + Op0EH = (int16) DSP1.parameters [0]; + Op0EV = (int16) DSP1.parameters [1]; + + DSPOp0E (); + + DSP1.out_count = 2; + DSP1.output [0] = Op0EX; + DSP1.output [1] = Op0EY; + break; + + // Extra commands used by Pilot Wings + case 0x01: // Set attitude matrix A + Op01m = (int16) DSP1.parameters [0]; + Op01Zr = (int16) DSP1.parameters [1]; + Op01Xr = (int16) DSP1.parameters [2]; + Op01Yr = (int16) DSP1.parameters [3]; + + DSPOp01 (); + break; + + case 0x11: // Set attitude matrix B + Op11m = (int16) DSP1.parameters [0]; + Op11Zr = (int16) DSP1.parameters [1]; + Op11Xr = (int16) DSP1.parameters [2]; + Op11Yr = (int16) DSP1.parameters [3]; + + DSPOp11 (); + break; + + case 0x21: // Set attitude matrix C + Op21m = (int16) DSP1.parameters [0]; + Op21Zr = (int16) DSP1.parameters [1]; + Op21Xr = (int16) DSP1.parameters [2]; + Op21Yr = (int16) DSP1.parameters [3]; + + DSPOp21 (); + break; + + case 0x0d: // Objective matrix A + Op0DX = (int16) DSP1.parameters [0]; + Op0DY = (int16) DSP1.parameters [1]; + Op0DZ = (int16) DSP1.parameters [2]; + + DSPOp0D (); + + DSP1.out_count = 3; + DSP1.output [0] = (uint16) Op0DF; + DSP1.output [1] = (uint16) Op0DL; + DSP1.output [2] = (uint16) Op0DU; + break; + + case 0x1d: // Objective matrix B + Op1DX = (int16) DSP1.parameters [0]; + Op1DY = (int16) DSP1.parameters [1]; + Op1DZ = (int16) DSP1.parameters [2]; + + DSPOp1D (); + + DSP1.out_count = 3; + DSP1.output [0] = (uint16) Op1DF; + DSP1.output [1] = (uint16) Op1DL; + DSP1.output [2] = (uint16) Op1DU; + break; + + case 0x2d: // Objective matrix C + Op2DX = (int16) DSP1.parameters [0]; + Op2DY = (int16) DSP1.parameters [1]; + Op2DZ = (int16) DSP1.parameters [2]; + + DSPOp2D (); + + DSP1.out_count = 3; + DSP1.output [0] = (uint16) Op2DF; + DSP1.output [1] = (uint16) Op2DL; + DSP1.output [2] = (uint16) Op2DU; + break; + + case 0x03: // Subjective matrix A + Op03F = (int16) DSP1.parameters [0]; + Op03L = (int16) DSP1.parameters [1]; + Op03U = (int16) DSP1.parameters [2]; + + DSPOp03 (); + + DSP1.out_count = 3; + DSP1.output [0] = (uint16) Op03X; + DSP1.output [1] = (uint16) Op03Y; + DSP1.output [2] = (uint16) Op03Z; + break; + + case 0x13: // Subjective matrix B + Op13F = (int16) DSP1.parameters [0]; + Op13L = (int16) DSP1.parameters [1]; + Op13U = (int16) DSP1.parameters [2]; + + DSPOp13 (); + + DSP1.out_count = 3; + DSP1.output [0] = (uint16) Op13X; + DSP1.output [1] = (uint16) Op13Y; + DSP1.output [2] = (uint16) Op13Z; + break; + + case 0x23: // Subjective matrix C + Op23F = (int16) DSP1.parameters [0]; + Op23L = (int16) DSP1.parameters [1]; + Op23U = (int16) DSP1.parameters [2]; + + DSPOp23 (); + + DSP1.out_count = 3; + DSP1.output [0] = (uint16) Op23X; + DSP1.output [1] = (uint16) Op23Y; + DSP1.output [2] = (uint16) Op23Z; + break; + + case 0x0b: + Op0BX = (int16) DSP1.parameters [0]; + Op0BY = (int16) DSP1.parameters [1]; + Op0BZ = (int16) DSP1.parameters [2]; + + DSPOp0B (); + + DSP1.out_count = 1; + DSP1.output [0] = (uint16) Op0BS; + break; + + case 0x1b: + Op1BX = (int16) DSP1.parameters [0]; + Op1BY = (int16) DSP1.parameters [1]; + Op1BZ = (int16) DSP1.parameters [2]; + + DSPOp1B (); + + DSP1.out_count = 1; + DSP1.output [0] = (uint16) Op1BS; + break; + + case 0x2b: + Op2BX = (int16) DSP1.parameters [0]; + Op2BY = (int16) DSP1.parameters [1]; + Op2BZ = (int16) DSP1.parameters [2]; + + DSPOp0B (); + + DSP1.out_count = 1; + DSP1.output [0] = (uint16) Op2BS; + break; + + case 0x14: // Gyrate + Op14Zr = (int16) DSP1.parameters [0]; + Op14Xr = (int16) DSP1.parameters [1]; + Op14Yr = (int16) DSP1.parameters [2]; + Op14U = (int16) DSP1.parameters [3]; + Op14F = (int16) DSP1.parameters [4]; + Op14L = (int16) DSP1.parameters [5]; + + DSPOp14 (); + + DSP1.out_count = 3; + DSP1.output [0] = (uint16) Op14Zrr; + DSP1.output [1] = (uint16) Op14Xrr; + DSP1.output [2] = (uint16) Op14Yrr; + break; + + default: + break; + } + } + else + DSP1.in_index++; + } + } + } + } +} diff --git a/src/Makefile b/src/Makefile new file mode 100644 index 0000000..c967051 --- /dev/null +++ b/src/Makefile @@ -0,0 +1,241 @@ +# Two stages Makefile + +## Common vars + +DEFAULT = wiz +NFAST = fast +NCOMP = compatible +ALL_TARGETS = wiz caanoo gp2x +ODIR_SUFFIX = objs +PNAME = pocketsnes + +## First stage +ifneq ($(STAGE),2) + +FILE_DATE = $(shell date +%Y-%m-%d) + +export MNAME +export VNAME +export COPT +export OBJS +export ARCH +export SDK +export STAGE +export FILE_DATE + +all: + make wiz + make caanoo + make gp2x + +# default to fast version +default: $(DEFAULT)f + +# clean +clean: ALL_TARGETS_DIRS = $(addsuffix _$(NFAST)_$(ODIR_SUFFIX)/,$(ALL_TARGETS)) $(addsuffix _$(NCOMP)_$(ODIR_SUFFIX)/,$(ALL_TARGETS)) +clean: + rm -f $(addsuffix *.o,$(ALL_TARGETS_DIRS)) + rm -f *.gpe + +# when release is targeted compile both fast and compatible versions +release: + make $(DEFAULT)f + make $(DEFAULT)c + rm -f rel/*.gpe + cp $(PNAME)_$(DEFAULT)_*.gpe rel/. + zip $(PNAME)-$(FILE_DATE).zip rel/* + +# invoke stage 2 +do: STAGE = 2 +do: + make + +# --------------------- +# Wiz +# --------------------- + +# -- Wiz common +wiz_common: MNAME = wiz +wiz_common: COPT += -mcpu=arm926ej-s -mtune=arm926ej-s -g -D__WIZ__ +#wiz_common: COPT += -D__FAST_OBJS__ +#wiz_common: COPT += -O3 +wiz_common: COPT += -Os +wiz_common: COPT += -ffast-math -msoft-float +wiz_common: COPT += -finline -finline-functions -fexpensive-optimizations +wiz_common: COPT += -falign-functions=32 -falign-loops -falign-labels -falign-jumps +wiz_common: COPT += -fomit-frame-pointer +wiz_common: COPT += -fno-common -fno-builtin -fstrict-aliasing -mstructure-size-boundary=32 +# -fweb -frename-registers +# -fsplit-ivs-in-unroller +#wiz_common: COPT += -Wall -Wno-sign-compare -Wunused -Wpointer-arith -Wcast-align -Waggregate-return +wiz_common: OBJS = wiz_sdk.o warm.o squidgehack.o pollux_set.o +wiz_common: OBJS += os9x_65c816_global.o os9x_65c816_spcasm.o os9x_65c816_spcc.o os9x_asm_cpu.o +wiz_common: ARCH = arm-open2x-linux +wiz_common: SDK = /opt/open2x/gcc-4.1.1-glibc-2.3.6 +#/$(ARCH) +#wiz_common: ARCH = arm-openwiz-linux-gnu +#wiz_common: SDK = /opt/openwiz/toolchain/$(ARCH) +wiz_common: do + +# -- Fast version +wizf: VNAME = $(NFAST) +#wizf: COPT = -DASMCPU -D__DEBUG__ +wizf: COPT = -DASMCPU +wizf: wiz_common + +# -- Normal version +wizc: VNAME = $(NCOMP) +wizc: COPT = -DUSE_SA1 +wizc: wiz_common + +wiz: + make $@f + make $@c + +# --------------------- +# Caanoo +# --------------------- + +# -- Caanoo common +caanoo_common: MNAME = caanoo +caanoo_common: COPT += -mcpu=arm926ej-s -mtune=arm926ej-s -g -D__WIZ__ -D__CAANOO__ +caanoo_common: COPT += -Os +caanoo_common: COPT += -finline -finline-functions -fexpensive-optimizations +caanoo_common: COPT += -falign-functions=32 -falign-loops -falign-labels -falign-jumps +caanoo_common: COPT += -fomit-frame-pointer +caanoo_common: COPT += -fno-common -fno-builtin -fstrict-aliasing -mstructure-size-boundary=32 +caanoo_common: OBJS = caanoo_sdk.o warm.o squidgehack.o pollux_set.o +caanoo_common: OBJS += os9x_65c816_global.o os9x_65c816_spcasm.o os9x_65c816_spcc.o os9x_asm_cpu.o +# EABI +#caanoo_common: ARCH = arm-gph-linux-gnueabi +#caanoo_common: SDK = /opt/caanoo_sdk/tools/gcc-4.2.4-glibc-2.7-eabi +# OABI +caanoo_common: COPT += -static -ffast-math -msoft-float +caanoo_common: ARCH = arm-open2x-linux +caanoo_common: SDK = /opt/open2x/gcc-4.1.1-glibc-2.3.6 +caanoo_common: do + +# -- Fast version +caanoof: VNAME = $(NFAST) +#caanoof: COPT = -DASMCPU -D__DEBUG__ +caanoof: COPT = -DASMCPU +caanoof: caanoo_common + +# -- Normal version +caanooc: VNAME = $(NCOMP) +caanooc: COPT = -DUSE_SA1 +caanooc: caanoo_common + +caanoo: + make $@f + make $@c + +# --------------------- +# GP2X +# --------------------- + +# -- GP2X common +gp2x_common: MNAME = gp2x +gp2x_common: COPT += -mcpu=arm920t -mtune=arm920t -static -g -D__GP2X__ +gp2x_common: COPT += -Os +gp2x_common: COPT += -ffast-math -msoft-float +gp2x_common: COPT += -finline -finline-functions -fexpensive-optimizations +gp2x_common: COPT += -falign-functions=32 -falign-loops -falign-labels -falign-jumps +gp2x_common: COPT += -fomit-frame-pointer +gp2x_common: COPT += -fno-common -fstrict-aliasing -mstructure-size-boundary=32 +gp2x_common: OBJS = gp2x_sdk.o warm.o squidgehack.o mmuhack.o +gp2x_common: OBJS += os9x_65c816_global_armv4.o os9x_65c816_spcasm.o os9x_65c816_spcc.o os9x_asm_cpu.o +gp2x_common: ARCH = arm-open2x-linux +gp2x_common: SDK = /opt/open2x/gcc-4.1.1-glibc-2.3.6 +gp2x_common: do + +# -- Fast version +gp2xf: VNAME = $(NFAST) +gp2xf: COPT = -DASMCPU +gp2xf: gp2x_common + +# -- Normal version +gp2xc: VNAME = $(NCOMP) +gp2xc: COPT = -DUSE_SA1 +gp2xc: gp2x_common + +gp2x: + make $@f + make $@c + + +## Second stage +else + +TOOLS = $(SDK)/bin +GCC = $(TOOLS)/$(ARCH)-gcc +STRIP = $(TOOLS)/$(ARCH)-strip +ADSASM = $(TOOLS)/$(ARCH)-as +LIBS = -I$(SDK)/include +INCS = -L$(SDK)/lib +ODIR = $(MNAME)_$(VNAME)_$(ODIR_SUFFIX) +# Inopia's menu system, hacked for the GP2X under rlyeh's sdk +PRELIBS = -lpthread -lz $(LIBS) + +# +# SNES stuff (c-based) +# +#OBJS += touchscreen.o +OBJS += apu.o apuaux.o c4.o c4emu.o cheats.o cheats2.o clip.o data.o screenshot.o +OBJS += dsp1.o fxemu.o fxinst.o globals.o loadzip.o ppu.o +OBJS += dma.o memmap.o +OBJS += cpu.o cpuexec.o +OBJS += cpuops.o +OBJS += sa1.o sa1cpu.o +OBJS += sdd1.o sdd1emu.o snapshot.o soundux.o spc700.o spc700a.o srtc.o +#OBJS += spc_decode.o +OBJS += tile16.o tile16add.o tile16add1_2.o tile16fadd1_2.o tile16sub.o tile16sub1_2.o tile16fsub1_2.o +OBJS += mode7new.o mode7.o mode7add.o mode7add1_2.o mode7sub.o mode7sub1_2.o +OBJS += mode7prio.o mode7addprio.o mode7add1_2prio.o mode7subprio.o mode7sub1_2prio.o +OBJS += gfx16.o rops.o +OBJS += usbjoy.o +# +# and some asm from LJP... +# +#OBJS += m3d_func.o +# +# Dave's minimal SDK +# +OBJS += menu.o config.o input.o gp2x_menutile.o gp2x_highlightbar.o \ + gp2x_menu_header.o unzip.o ioapi.o zip.o asm_util.o png.o graphics.o lodepng.o theme.o minIni.o +OBJS += disk_img.o +OBJS += memset.o memcmp.o memcpy.o strlen.o strcmp.o strncmp.o + +# +# and the glue code that sticks it all together :) +# +OBJS += main.o +FOBJS = $(addprefix $(ODIR)/,$(OBJS)) +COPT += $(INCS) $(LIBS) + +executable: $(FOBJS) + $(GCC) $(COPT) $(FOBJS) $(PRELIBS) -o $(PNAME)d_$(MNAME)_$(VNAME).gpe -lstdc++ -lm + $(STRIP) $(PNAME)d_$(MNAME)_$(VNAME).gpe -o $(PNAME)_$(MNAME)_$(VNAME).gpe + +$(FOBJS): | $(ODIR) + +$(ODIR): + mkdir -p $(ODIR) + +tidy: + rm $(ODIR)/*.o + +# -- Compilation rules +$(ODIR)/%.o: %.cpp + $(GCC) $(COPT) -c $< -o $@ + +$(ODIR)/%.o: %.c + $(GCC) $(COPT) -c $< -o $@ + +$(ODIR)/%.o: %.s + $(GCC) $(COPT) -c $< -o $@ + +$(ODIR)/%.o: %.S + $(GCC) $(COPT) -c $< -o $@ + +endif diff --git a/src/Makefile.22062010 b/src/Makefile.22062010 new file mode 100644 index 0000000..2fa3364 --- /dev/null +++ b/src/Makefile.22062010 @@ -0,0 +1,105 @@ +COPT = -mcpu=arm926ej-s -mtune=arm926ej-s -g -D__WIZ__ +COPT += -DASMCPU +COPT += -DARM +COPT += -DVAR_CYCLES +#COPT += -D_C_GW_ +#COPT = -DUSE_SA1 +COPT += -O3 +# -DFAST_LSB_WORD_ACCESS +COPT += -ffast-math -msoft-float +COPT += -finline -finline-functions -fexpensive-optimizations +COPT += -falign-functions=16 -falign-loops -falign-labels +#COPT += -falign-jumps +COPT += -fomit-frame-pointer +COPT += -fstrict-aliasing -mstructure-size-boundary=32 -fweb -fsigned-char -frename-registers +SDK = /opt/openwiz/toolchain/arm-openwiz-linux-gnu +TOOLS = $(SDK)/bin +ARCH = arm-openwiz-linux-gnu- +GCC = $(TOOLS)/$(ARCH)gcc +STRIP = $(TOOLS)/$(ARCH)strip +ADSASM = $(TOOLS)/$(ARCH)as +COPT += -I$(SDK)/include +COPT += -L$(SDK)/lib +#COPT += -fprofile-generate +#COPT += -fprofile-use +# +# SNES stuff (c-based) +# +OBJS = memset.o memcpy.o +OBJS += 2xsaiwin.o apu.o c4.o c4emu.o cheats.o cheats2.o clip.o data.o +OBJS += dsp1.o fxemu.o fxinst.o globals.o loadzip.o ppu.o +OBJS += dma.o memmap.o +OBJS += cpu.o cpuexec.o +OBJS += cpuops.o +# OBJS += sa1.o sa1cpu.o +OBJS += sdd1.o sdd1emu.o snapshot.o soundux.o spc_decode.o spc700.o spc700a.o srtc.o +OBJS += tile16.o tile16add.cpp tile16sub.cpp gfx16.o +OBJS += os9x_65c816.o os9x_asm_cpu.o +OBJS += usbjoy.o +# +# and some asm from LJP... +# +OBJS += m3d_func.o +# +# Dave's minimal SDK +# +OBJS += wiz_sdk.o warm.o menu.o input.o gp2x_menutile.o gp2x_highlightbar.o \ + gp2x_menu_header.o unzip.o ioapi.o squidgehack.o zip.o asm_util.o pollux_set.o + +# +# and the glue code that sticks it all together :) +# +OBJS += main.o + +# Inopia's menu system, hacked for the GP2X under rlyeh's sdk +PRELIBS = -lpthread -lz $(LIBS) + +all: pocketsnes.gpe +clean: tidy pocketsnes.gpe + +.c.o: + $(GCC) $(COPT) -c $< -o $@ + +.cpp.o: + $(GCC) $(COPT) -c $< -o $@ + +# make seems to lowercase the extensions, so files with '.S' end up being passed to the compiler as '.s', which means thousands of errors. +# this is a small workaround. + +spc700a.o: spc700a.s + $(GCC) $(COPT) -c $< -o $@ + +os9x_65c816.o: os9x_65c816.s + $(GCC) $(COPT) -c $< -o $@ + +osnes9xgp_asmfunc.o: osnes9xgp_asmfunc.s + $(GCC) $(COPT) -c $< -o $@ + +m3d_func.o: m3d_func.S + $(GCC) $(COPT) -c $< -o $@ + +spc_decode.o: spc_decode.S + $(GCC) $(COPT) -c $< -o $@ + +memset.o: memset.s + $(GCC) $(COPT) -c $< -o $@ + +#sa1_asm.o: sa1_asm.s +# $(GCC) $(COPT) -c $< -o $@ + +memcpy.o: memcpy.s + $(GCC) $(COPT) -c $< -o $@ + +dspMixer.o: dspMixer.s + $(GCC) $(COPT) -c $< -o $@ + +asm_util.o: asm_util.S + $(GCC) $(COPT) -c $< -o $@ + +pocketsnesd.gpe: $(OBJS) + $(GCC) $(COPT) $(OBJS) $(PRELIBS) -o $@ -lstdc++ -lm + +pocketsnes.gpe: pocketsnesd.gpe + $(STRIP) pocketsnesd.gpe -o pocketsnes_wiz_fast.gpe +tidy: + rm *.o diff --git a/src/Makefile.gp2x b/src/Makefile.gp2x new file mode 100644 index 0000000..ecc07fd --- /dev/null +++ b/src/Makefile.gp2x @@ -0,0 +1,105 @@ +COPT = -mcpu=arm926ej-s -mtune=arm926ej-s -static -g -D__WIZ__ +COPT += -DASMCPU +COPT += -DARM +COPT += -DVAR_CYCLES +#COPT += -D_C_GW_ +#COPT = -DUSE_SA1 +COPT += -O3 +# -DFAST_LSB_WORD_ACCESS +COPT += -ffast-math -msoft-float +COPT += -finline -finline-functions -fexpensive-optimizations +COPT += -falign-functions=16 -falign-loops -falign-labels +#COPT += -falign-jumps +COPT += -fomit-frame-pointer +COPT += -fstrict-aliasing -mstructure-size-boundary=32 -fweb -fsigned-char -frename-registers +SDK = /opt/openwiz/toolchain/arm-openwiz-linux-gnu +TOOLS = $(SDK)/bin +ARCH = arm-openwiz-linux-gnu- +GCC = $(TOOLS)/$(ARCH)gcc +STRIP = $(TOOLS)/$(ARCH)strip +ADSASM = $(TOOLS)/$(ARCH)as +COPT += -I$(SDK)/include +COPT += -L$(SDK)/lib +#COPT += -fprofile-generate +#COPT += -fprofile-use +# +# SNES stuff (c-based) +# +OBJS = memset.o memcpy.o +OBJS += 2xsaiwin.o apu.o c4.o c4emu.o cheats.o cheats2.o clip.o data.o +OBJS += dsp1.o fxemu.o fxinst.o globals.o loadzip.o ppu.o +OBJS += dma.o memmap.o +OBJS += cpu.o cpuexec.o +OBJS += cpuops.o +# OBJS += sa1.o sa1cpu.o +OBJS += sdd1.o sdd1emu.o snapshot.o soundux.o spc_decode.o spc700.o spc700a.o srtc.o +OBJS += tile16.o tile16add.cpp tile16sub.cpp gfx16.o +OBJS += os9x_65c816.o os9x_asm_cpu.o +OBJS += usbjoy.o +# +# and some asm from LJP... +# +OBJS += m3d_func.o +# +# Dave's minimal SDK +# +OBJS += wiz_sdk.o warm.o menu.o input.o gp2x_menutile.o gp2x_highlightbar.o \ + gp2x_menu_header.o unzip.o ioapi.o squidgehack.o zip.o asm_util.o pollux_set.o + +# +# and the glue code that sticks it all together :) +# +OBJS += main.o + +# Inopia's menu system, hacked for the GP2X under rlyeh's sdk +PRELIBS = -lpthread -lz $(LIBS) + +all: pocketsnes.gpe +clean: tidy pocketsnes.gpe + +.c.o: + $(GCC) $(COPT) -c $< -o $@ + +.cpp.o: + $(GCC) $(COPT) -c $< -o $@ + +# make seems to lowercase the extensions, so files with '.S' end up being passed to the compiler as '.s', which means thousands of errors. +# this is a small workaround. + +spc700a.o: spc700a.s + $(GCC) $(COPT) -c $< -o $@ + +os9x_65c816.o: os9x_65c816.s + $(GCC) $(COPT) -c $< -o $@ + +osnes9xgp_asmfunc.o: osnes9xgp_asmfunc.s + $(GCC) $(COPT) -c $< -o $@ + +m3d_func.o: m3d_func.S + $(GCC) $(COPT) -c $< -o $@ + +spc_decode.o: spc_decode.S + $(GCC) $(COPT) -c $< -o $@ + +memset.o: memset.s + $(GCC) $(COPT) -c $< -o $@ + +#sa1_asm.o: sa1_asm.s +# $(GCC) $(COPT) -c $< -o $@ + +memcpy.o: memcpy.s + $(GCC) $(COPT) -c $< -o $@ + +dspMixer.o: dspMixer.s + $(GCC) $(COPT) -c $< -o $@ + +asm_util.o: asm_util.S + $(GCC) $(COPT) -c $< -o $@ + +pocketsnesd.gpe: $(OBJS) + $(GCC) $(COPT) $(OBJS) $(PRELIBS) -o $@ -lstdc++ -lm + +pocketsnes.gpe: pocketsnesd.gpe + $(STRIP) pocketsnesd.gpe -o pocketsnes_wiz_fast.gpe +tidy: + rm *.o diff --git a/src/Makefile.last b/src/Makefile.last new file mode 100644 index 0000000..9249d22 --- /dev/null +++ b/src/Makefile.last @@ -0,0 +1,99 @@ +MNAME = wiz +COPT = -mcpu=arm926ej-s -mtune=arm926ej-s -g -D__WIZ__ +COPT += -O3 +COPT += -ffast-math -msoft-float +COPT += -finline -finline-functions -fexpensive-optimizations +COPT += -falign-functions=32 -falign-loops -falign-labels +COPT += -falign-jumps +COPT += -fomit-frame-pointer +#COPT += -fprofile-generate +#COPT += -fprofile-use +#COPT += -pg +ARCH = arm-open2x-linux +SDK = /opt/open2x/gcc-4.1.1-glibc-2.3.6/$(ARCH) +TOOLS = $(SDK)/bin +GCC = $(TOOLS)/$(ARCH)-gcc +STRIP = $(TOOLS)/$(ARCH)-strip +ADSASM = $(TOOLS)/$(ARCH)-as +COPT += -I$(SDK)/include +COPT += -L$(SDK)/lib +# +# SNES stuff (c-based) +# +OBJS = memcpy.o +#OBJS += touchscreen.o +OBJS += apu.o apuaux.o c4.o c4emu.o cheats.o cheats2.o clip.o data.o +OBJS += dsp1.o fxemu.o fxinst.o globals.o loadzip.o ppu.o +OBJS += dma.o memmap.o +OBJS += cpu.o cpuexec.o +OBJS += cpuops.o +OBJS += sa1.o sa1cpu.o +OBJS += sdd1.o sdd1emu.o snapshot.o soundux.o spc700.o spc700a.o srtc.o +OBJS += spc_decode.o +OBJS += tile16.o tile16add.o tile16add1_2.o tile16fadd1_2.o tile16sub.o tile16sub1_2.o tile16fsub1_2.o +OBJS += mode7new.o mode7.o mode7add.o mode7add1_2.o mode7sub.o mode7sub1_2.o +OBJS += mode7prio.o mode7addprio.o mode7add1_2prio.o mode7subprio.o mode7sub1_2prio.o +OBJS += gfx16.o +OBJS += os9x_65c816_global.o os9x_65c816_spcasm.o os9x_65c816_spcc.o os9x_asm_cpu.o +OBJS += usbjoy.o +# +# and some asm from LJP... +# +OBJS += m3d_func.o +# +# Dave's minimal SDK +# +OBJS += loadlast.o wiz_sdk.o warm.o menu.o input.o gp2x_menutile.o gp2x_highlightbar.o \ + gp2x_menu_header.o unzip.o ioapi.o squidgehack.o zip.o asm_util.o pollux_set.o + +OBJS += disk_img.o +# +# and the glue code that sticks it all together :) +# +OBJS += main.o + +# Inopia's menu system, hacked for the GP2X under rlyeh's sdk +PRELIBS = -lpthread -lz $(LIBS) + +all: vfast +clean: tidy all + +first: + mkdir -p $(MNAME)_$(VNAME)_obj + +$(OBJS): first + +pocketsnesd.gpe: $(OBJS) + $(GCC) $(COPT) $(addprefix $(MNAME)_$(VNAME)_obj/,$(OBJS)) $(PRELIBS) -o pocketsnesd_$(MNAME)_$(VNAME).gpe -lstdc++ -lm + +pocketsnes.gpe: pocketsnesd.gpe + $(STRIP) pocketsnesd_$(MNAME)_$(VNAME).gpe -o pocketsnes_$(MNAME)_$(VNAME).gpe + +tidy: + rm $(OBJDIR)/*.o + +# -- Fast version +vfast: VNAME = fast +vfast: COPT += -DASMCPU +vfast: OBJDIR = $(MNAME)_$(VNAME)_obj +vfast: pocketsnes.gpe + +# -- Normal version +vnormal: VNAME = normal +vnormal: COPT += -DUSE_SA1 +vnormal: ODIR = $(MNAME)_$(VNAME)_obj +vnormal: pocketsnes.gpe + +# -- Compilation rules +%.o: %.cpp + $(GCC) $(COPT) -c $< -o $(MNAME)_$(VNAME)_obj/$@ + +%.o: %.c + $(GCC) $(COPT) -c $< -o $(MNAME)_$(VNAME)_obj/$@ + +%.o: %.s + $(GCC) $(COPT) -c $< -o $(MNAME)_$(VNAME)_obj/$@ + +%.o: %.S + $(GCC) $(COPT) -c $< -o $(MNAME)_$(VNAME)_obj/$@ + diff --git a/src/Makefile.old b/src/Makefile.old new file mode 100644 index 0000000..1c713c0 --- /dev/null +++ b/src/Makefile.old @@ -0,0 +1,243 @@ +# Two stages Makefile + +## Common vars + +DEFAULT = wiz +NFAST = fast +NCOMP = compatible +ALL_TARGETS = wiz caanoo gp2x +ODIR_SUFFIX = objs +PNAME = pocketsnes + +## First stage +ifneq ($(STAGE),2) + +FILE_DATE = $(shell date +%Y-%m-%d) + +export MNAME +export VNAME +export COPT +export OBJS +export ARCH +export SDK +export STAGE +export FILE_DATE + +all: + make wiz + make caanoo + make gp2x + +# default to fast version +default: $(DEFAULT)f + +# clean +clean: ALL_TARGETS_DIRS = $(addsuffix _$(NFAST)_$(ODIR_SUFFIX)/,$(ALL_TARGETS)) $(addsuffix _$(NCOMP)_$(ODIR_SUFFIX)/,$(ALL_TARGETS)) +clean: + rm -f $(addsuffix *.o,$(ALL_TARGETS_DIRS)) + rm -f *.gpe + +# when release is targeted compile both fast and compatible versions +release: + make $(DEFAULT)f + make $(DEFAULT)c + rm -f rel/*.gpe + cp $(PNAME)_$(DEFAULT)_*.gpe rel/. + zip $(PNAME)-$(FILE_DATE).zip rel/* + +# invoke stage 2 +do: STAGE = 2 +do: + make + +# --------------------- +# Wiz +# --------------------- + +# -- Wiz common +wiz_common: MNAME = wiz +wiz_common: COPT += -mcpu=arm926ej-s -mtune=arm926ej-s -g -D__WIZ__ +#wiz_common: COPT += -D__FAST_OBJS__ +#wiz_common: COPT += -O3 +wiz_common: COPT += -Os +wiz_common: COPT += -ffast-math -msoft-float +wiz_common: COPT += -finline -finline-functions -fexpensive-optimizations +wiz_common: COPT += -falign-functions=32 -falign-loops -falign-labels -falign-jumps +wiz_common: COPT += -fomit-frame-pointer +wiz_common: COPT += -fno-common -fno-builtin -fstrict-aliasing -mstructure-size-boundary=32 +# -fweb -frename-registers +# -fsplit-ivs-in-unroller +#wiz_common: COPT += -Wall -Wno-sign-compare -Wunused -Wpointer-arith -Wcast-align -Waggregate-return +wiz_common: OBJS = wiz_sdk.o warm.o squidgehack.o pollux_set.o +wiz_common: OBJS += os9x_65c816_global.o os9x_65c816_spcasm.o os9x_65c816_spcc.o os9x_asm_cpu.o +wiz_common: ARCH = arm-open2x-linux +wiz_common: SDK = /opt/open2x/gcc-4.1.1-glibc-2.3.6 +#/$(ARCH) +#wiz_common: ARCH = arm-openwiz-linux-gnu +#wiz_common: SDK = /opt/openwiz/toolchain/$(ARCH) +wiz_common: do + +# -- Fast version +wizf: VNAME = $(NFAST) +#wizf: COPT = -DASMCPU -D__DEBUG__ +wizf: COPT = -DASMCPU +wizf: wiz_common + +# -- Normal version +wizc: VNAME = $(NCOMP) +wizc: COPT = -DUSE_SA1 +wizc: wiz_common + +wiz: + make $@f + make $@c + +# --------------------- +# Caanoo +# --------------------- + +# -- Caanoo common +caanoo_common: MNAME = caanoo +caanoo_common: COPT += -mcpu=arm926ej-s -mtune=arm926ej-s -g -D__WIZ__ -D__CAANOO__ +#caanoo_coomon: COPT += -D__FAST_OBJS__ +#caanoo_common: COPT += -O3 +caanoo_common: COPT += -Os +caanoo_common: COPT += -finline -finline-functions -fexpensive-optimizations +caanoo_common: COPT += -falign-functions=32 -falign-loops -falign-labels -falign-jumps +caanoo_common: COPT += -fomit-frame-pointer +caanoo_common: COPT += -fno-common -fno-builtin -fstrict-aliasing -mstructure-size-boundary=32 +caanoo_common: OBJS = caanoo_sdk.o warm.o squidgehack.o pollux_set.o +caanoo_common: OBJS += os9x_65c816_global.o os9x_65c816_spcasm.o os9x_65c816_spcc.o os9x_asm_cpu.o +# EABI +#caanoo_common: ARCH = arm-gph-linux-gnueabi +#caanoo_common: SDK = /opt/caanoo_sdk/tools/gcc-4.2.4-glibc-2.7-eabi +# OABI +caanoo_common: COPT += -static -ffast-math -msoft-float +caanoo_common: ARCH = arm-open2x-linux +caanoo_common: SDK = /opt/open2x/gcc-4.1.1-glibc-2.3.6 +caanoo_common: do + +# -- Fast version +caanoof: VNAME = $(NFAST) +#caanoof: COPT = -DASMCPU -D__DEBUG__ +caanoof: COPT = -DASMCPU +caanoof: caanoo_common + +# -- Normal version +caanooc: VNAME = $(NCOMP) +caanooc: COPT = -DUSE_SA1 +caanooc: caanoo_common + +caanoo: + make $@f + make $@c + +# --------------------- +# GP2X +# --------------------- + +# -- GP2X common +gp2x_common: MNAME = gp2x +gp2x_common: COPT += -mcpu=arm920t -mtune=arm920t -static -g -D__GP2X__ +gp2x_common: COPT += -Os +gp2x_common: COPT += -ffast-math -msoft-float +gp2x_common: COPT += -finline -finline-functions -fexpensive-optimizations +gp2x_common: COPT += -falign-functions=32 -falign-loops -falign-labels -falign-jumps +gp2x_common: COPT += -fomit-frame-pointer +gp2x_common: COPT += -fno-common -fstrict-aliasing -mstructure-size-boundary=32 +gp2x_common: OBJS = gp2x_sdk.o warm.o squidgehack.o mmuhack.o +gp2x_common: OBJS += os9x_65c816_global_armv4.o os9x_65c816_spcasm.o os9x_65c816_spcc.o os9x_asm_cpu.o +gp2x_common: ARCH = arm-open2x-linux +gp2x_common: SDK = /opt/open2x/gcc-4.1.1-glibc-2.3.6 +gp2x_common: do + +# -- Fast version +gp2xf: VNAME = $(NFAST) +gp2xf: COPT = -DASMCPU +gp2xf: gp2x_common + +# -- Normal version +gp2xc: VNAME = $(NCOMP) +gp2xc: COPT = -DUSE_SA1 +gp2xc: gp2x_common + +gp2x: + make $@f + make $@c + + +## Second stage +else + +TOOLS = $(SDK)/bin +GCC = $(TOOLS)/$(ARCH)-gcc +STRIP = $(TOOLS)/$(ARCH)-strip +ADSASM = $(TOOLS)/$(ARCH)-as +LIBS = -I$(SDK)/include +INCS = -L$(SDK)/lib +ODIR = $(MNAME)_$(VNAME)_$(ODIR_SUFFIX) +# Inopia's menu system, hacked for the GP2X under rlyeh's sdk +PRELIBS = -lpthread -lz $(LIBS) + +# +# SNES stuff (c-based) +# +#OBJS += touchscreen.o +OBJS += apu.o apuaux.o c4.o c4emu.o cheats.o cheats2.o clip.o data.o screenshot.o +OBJS += dsp1.o fxemu.o fxinst.o globals.o loadzip.o ppu.o +OBJS += dma.o memmap.o +OBJS += cpu.o cpuexec.o +OBJS += cpuops.o +OBJS += sa1.o sa1cpu.o +OBJS += sdd1.o sdd1emu.o snapshot.o soundux.o spc700.o spc700a.o srtc.o +#OBJS += spc_decode.o +OBJS += tile16.o tile16add.o tile16add1_2.o tile16fadd1_2.o tile16sub.o tile16sub1_2.o tile16fsub1_2.o +OBJS += mode7new.o mode7.o mode7add.o mode7add1_2.o mode7sub.o mode7sub1_2.o +OBJS += mode7prio.o mode7addprio.o mode7add1_2prio.o mode7subprio.o mode7sub1_2prio.o +OBJS += gfx16.o rops.o +OBJS += usbjoy.o +# +# and some asm from LJP... +# +#OBJS += m3d_func.o +# +# Dave's minimal SDK +# +OBJS += menu.o config.o input.o gp2x_menutile.o gp2x_highlightbar.o \ + gp2x_menu_header.o unzip.o ioapi.o zip.o asm_util.o png.o graphics.o lodepng.o theme.o minIni.o +OBJS += disk_img.o +OBJS += memset.o memcmp.o memcpy.o strlen.o strcmp.o strncmp.o + +# +# and the glue code that sticks it all together :) +# +OBJS += main.o +FOBJS = $(addprefix $(ODIR)/,$(OBJS)) +COPT += $(INCS) $(LIBS) + +executable: $(FOBJS) + $(GCC) $(COPT) $(FOBJS) $(PRELIBS) -o $(PNAME)d_$(MNAME)_$(VNAME).gpe -lstdc++ -lm + $(STRIP) $(PNAME)d_$(MNAME)_$(VNAME).gpe -o $(PNAME)_$(MNAME)_$(VNAME).gpe + +$(FOBJS): | $(ODIR) + +$(ODIR): + mkdir -p $(ODIR) + +tidy: + rm $(ODIR)/*.o + +# -- Compilation rules +$(ODIR)/%.o: %.cpp + $(GCC) $(COPT) -c $< -o $@ + +$(ODIR)/%.o: %.c + $(GCC) $(COPT) -c $< -o $@ + +$(ODIR)/%.o: %.s + $(GCC) $(COPT) -c $< -o $@ + +$(ODIR)/%.o: %.S + $(GCC) $(COPT) -c $< -o $@ + +endif diff --git a/src/Makefile.wiz.OpenWiz b/src/Makefile.wiz.OpenWiz new file mode 100644 index 0000000..4950675 --- /dev/null +++ b/src/Makefile.wiz.OpenWiz @@ -0,0 +1,82 @@ +COPT = -mcpu=arm926ej-s -mtune=arm926ej-s -g -O3 -static -D__WIZ__ -DUSE_SA1 +COPT += -ffast-math -fexpensive-optimizations -finline -finline-functions -msoft-float +# -msoft-float +COPT += -falign-functions=32 -falign-loops -falign-labels -falign-jumps -fomit-frame-pointer +SDK = /opt/openwiz/toolchain/arm-openwiz-linux-gnu +TOOLS = $(SDK)/bin +ARCH = arm-openwiz-linux-gnu- +GCC = $(TOOLS)/$(ARCH)gcc +STRIP = $(TOOLS)/$(ARCH)strip +ADSASM = $(TOOLS)/$(ARCH)as +COPT += -I$(SDK)/include +COPT += -L$(SDK)/lib +# +# SNES stuff (c-based) +# +OBJS = memset.o memcpy.o 2xsaiwin.o apu.o c4.o c4emu.o cheats.o cheats2.o clip.o cpu.o cpuexec.o data.o +OBJS += dma.o dsp1.o fxemu.o fxinst.o gfx.o globals.o loadzip.o memmap.o ppu.o sa1.o sa1cpu.o +OBJS += sdd1.o sdd1emu.o snapshot.o soundux.o spc700.o spc700a.o srtc.o tile.o usbjoy.o cpuops.o os9x_asm_cpu.o +# +# and some asm from LJP... +# +OBJS += m3d_func.o +# +# Dave's minimal SDK +# +OBJS += wiz_sdk.o warm.o menu.o input.o gp2x_menutile.o gp2x_highlightbar.o \ + gp2x_menu_header.o unzip.o ioapi.o squidgehack.o zip.o asm_util.o pollux_set.o + +# +# and the glue code that sticks it all together :) +# +OBJS += main.o + +# Inopia's menu system, hacked for the GP2X under rlyeh's sdk +PRELIBS = -lpthread -lz $(LIBS) + +all: pocketsnes.gpe +clean: tidy pocketsnes.gpe + +.c.o: + $(GCC) $(COPT) -c $< -o $@ + +.cpp.o: + $(GCC) $(COPT) -c $< -o $@ + +# make seems to lowercase the extensions, so files with '.S' end up being passed to the compiler as '.s', which means thousands of errors. +# this is a small workaround. + +spc700a.o: spc700a.s + $(GCC) $(COPT) -c $< -o $@ + +os9x_65c816.o: os9x_65c816.s + $(GCC) $(COPT) -c $< -o $@ + +osnes9xgp_asmfunc.o: osnes9xgp_asmfunc.s + $(GCC) $(COPT) -c $< -o $@ + +m3d_func.o: m3d_func.S + $(GCC) $(COPT) -c $< -o $@ + +spc_decode.o: spc_decode.s + $(GCC) $(COPT) -c $< -o $@ + +memset.o: memset.s + $(GCC) $(COPT) -c $< -o $@ + +memcpy.o: memcpy.s + $(GCC) $(COPT) -c $< -o $@ + +dspMixer.o: dspMixer.s + $(GCC) $(COPT) -c $< -o $@ + +asm_util.o: asm_util.S + $(GCC) $(COPT) -c $< -o $@ + +pocketsnesd.gpe: $(OBJS) + $(GCC) $(COPT) $(OBJS) $(PRELIBS) -o $@ -lstdc++ -lm + +pocketsnes.gpe: pocketsnesd.gpe + $(STRIP) pocketsnesd.gpe -o pocketsnes_wiz.gpe +tidy: + rm *.o diff --git a/src/Makefile.wiz.bck b/src/Makefile.wiz.bck new file mode 100644 index 0000000..b682196 --- /dev/null +++ b/src/Makefile.wiz.bck @@ -0,0 +1,82 @@ +COPT = -mcpu=arm926ej-s -mtune=arm926ej-s -g -O3 -static -D__WIZ__ -DUSE_SA1 +COPT += -ffast-math -fexpensive-optimizations -finline -finline-functions -msoft-float +# -msoft-float +COPT += -falign-functions=32 -falign-loops -falign-labels -falign-jumps -fomit-frame-pointer +SDK = $(HOME)/GPH_SDK +TOOLS = $(SDK)/tools/gcc-4.0.2-glibc-2.3.6/arm-linux/bin +ARCH = arm-linux- +GCC = $(TOOLS)/$(ARCH)gcc +STRIP = $(TOOLS)/$(ARCH)strip +ADSASM = $(TOOLS)/$(ARCH)as +COPT += -I$(SDK)/include +COPT += -L$(SDK)/lib/target +# +# SNES stuff (c-based) +# +OBJS = memset.o memcpy.o 2xsaiwin.o apu.o c4.o c4emu.o cheats.o cheats2.o clip.o cpu.o cpuexec.o data.o +OBJS += dma.o dsp1.o fxemu.o fxinst.o gfx.o globals.o loadzip.o memmap.o ppu.o sa1.o sa1cpu.o +OBJS += sdd1.o sdd1emu.o snapshot.o soundux.o spc700.o spc700a.o srtc.o tile.o usbjoy.o cpuops.o os9x_asm_cpu.o +# +# and some asm from LJP... +# +OBJS += m3d_func.o +# +# Dave's minimal SDK +# +OBJS += wiz_sdk.o warm.o menu.o input.o gp2x_menutile.o gp2x_highlightbar.o \ + gp2x_menu_header.o unzip.o ioapi.o squidgehack.o zip.o asm_util.o pollux_set.o + +# +# and the glue code that sticks it all together :) +# +OBJS += main.o + +# Inopia's menu system, hacked for the GP2X under rlyeh's sdk +PRELIBS = -lpthread -lz $(LIBS) + +all: pocketsnes.gpe +clean: tidy pocketsnes.gpe + +.c.o: + $(GCC) $(COPT) -c $< -o $@ + +.cpp.o: + $(GCC) $(COPT) -c $< -o $@ + +# make seems to lowercase the extensions, so files with '.S' end up being passed to the compiler as '.s', which means thousands of errors. +# this is a small workaround. + +spc700a.o: spc700a.s + $(GCC) $(COPT) -c $< -o $@ + +os9x_65c816.o: os9x_65c816.s + $(GCC) $(COPT) -c $< -o $@ + +osnes9xgp_asmfunc.o: osnes9xgp_asmfunc.s + $(GCC) $(COPT) -c $< -o $@ + +m3d_func.o: m3d_func.S + $(GCC) $(COPT) -c $< -o $@ + +spc_decode.o: spc_decode.s + $(GCC) $(COPT) -c $< -o $@ + +memset.o: memset.s + $(GCC) $(COPT) -c $< -o $@ + +memcpy.o: memcpy.s + $(GCC) $(COPT) -c $< -o $@ + +dspMixer.o: dspMixer.s + $(GCC) $(COPT) -c $< -o $@ + +asm_util.o: asm_util.S + $(GCC) $(COPT) -c $< -o $@ + +pocketsnesd.gpe: $(OBJS) + $(GCC) $(COPT) $(OBJS) $(PRELIBS) -o $@ -lstdc++ -lm + +pocketsnes.gpe: pocketsnesd.gpe + $(STRIP) pocketsnesd.gpe -o pocketsnes_wiz.gpe +tidy: + rm *.o diff --git a/src/Makefile_giz b/src/Makefile_giz new file mode 100644 index 0000000..f20d02c --- /dev/null +++ b/src/Makefile_giz @@ -0,0 +1,88 @@ +#COPT = -static -g -I. -I C:/devkitGP2X/include -IC:/devkitGP2X/sysroot/usr/include -O3 -D__GP2X__ + +SDK_BASE = C:/cygwin/usr/local/arm-wince-pe/lib/KGSDK +ZLIB_BASE = C:/cygwin/usr/local/arm-wince-pe/lib/zlib + +#COPT = -IC:/cygwin/usr/local/arm-wince-pe/include -I$(SDK_BASE)/include -static -g -I. -O3 -mtune=arm920t -ftracer -fstrength-reduce -Wno-unused -funroll-loops -fomit-frame-pointer -fstrict-aliasing -ffast-math -D__GP2X__ +COPT = -IC:/cygwin/usr/local/arm-wince-pe/include -I$(SDK_BASE)/include -I$(ZLIB_BASE)/include -I . -mcpu=arm920 \ + -mtune=arm920t -O2 -msoft-float -ffast-math -fstrict-aliasing -mstructure-size-boundary=8 \ + -fexpensive-optimizations -fweb -frename-registers -fomit-frame-pointer -falign-functions -finline -finline-functions \ + -fno-builtin -fno-common -D__GIZ__ +GCC = arm-wince-pe-gcc +STRIP = arm-wince-pe-strip +ADSASM = armasm + +# +# SNES stuff (c-based) +# +OBJS = 2xsaiwin.o apu.o c4.o c4emu.o cheats.o cheats2.o clip.o cpu.o cpuexec.o data.o +OBJS += dma.o dsp1.o fxemu.o fxinst.o gfx.o globals.o loadzip.o memmap.o ppu.o +OBJS += sdd1.o snapshot.o soundux.o spc700.o srtc.o tile.o +# +# ASM CPU Core, ripped from Yoyo's OpenSnes9X +# +OBJS += os9x_asm_cpu.o os9x_65c816.o spc700a.o +#osnes9xgp_asmfunc.o +#RenderASM/render8.o +# +# and some asm from LJP... +# +OBJS += m3d_func.o spc_decode.o +# +# +# +OBJS += giz_kgsdk.o menu.o input.o gp2x_menutile.o gp2x_highlightbar.o \ + gp2x_menu_header.o unzip.o ioapi.o giz_kgsdkasm.o + +# +# and the glue code that sticks it all together :) +# +OBJS += main.o + +# Inopia's menu system, hacked for the GP2X under rlyeh's sdk +PRELIBS = -LC:/cygwin/usr/local/arm-wince-pe/lib -L$(ZLIB_BASE) -lzip -L$(SDK_BASE) -lKGSDK $(LIBS) + +all: squidgesnes.gpe +clean: tidy squidgesnes.gpe + +.c.o: + $(GCC) $(COPT) -c $< -o $@ + +.cpp.o: + $(GCC) $(COPT) -c $< -o $@ + +# make seems to lowercase the extensions, so files with '.S' end up being passed to the compiler as '.s', which means thousands of errors. +# this is a small workaround. + +myuname.o: myuname.S + $(GCC) $(COPT) -c $< -o $@ + +os9x_65c816.o: os9x_65c816.s + $(GCC) $(COPT) -c $< -o $@ + +osnes9xgp_asmfunc.o: osnes9xgp_asmfunc.S + $(GCC) $(COPT) -c $< -o $@ + +m3d_func.o: m3d_func.S + $(GCC) $(COPT) -c $< -o $@ + +spc_decode.o: spc_decode.s + $(GCC) $(COPT) -c $< -o $@ + +spc700a.o: spc700a.s + $(GCC) $(COPT) -c $< -o $@ + +giz_kgsdkasm.o: giz_kgsdkasm.s + $(GCC) $(COPT) -c $< -o $@ + +RenderASM/render8.o: RenderASM/render8.S + $(GCC) $(COPT) -c $< -o $@ + +squidgesnesd.gpe: $(OBJS) + $(GCC) $(COPT) $(OBJS) -static $(PRELIBS) -o $@ -lstdc++ -lm + +squidgesnes.gpe: squidgesnesd.gpe + $(STRIP) squidgesnesd.gpe -o squidgesnes.gpe + cp squidgesnes.gpe autorun.exe +tidy: + del *.o diff --git a/src/VOIMAGE.CPP b/src/VOIMAGE.CPP new file mode 100644 index 0000000..230d707 --- /dev/null +++ b/src/VOIMAGE.CPP @@ -0,0 +1,281 @@ +//------------------------------------------------------------------- +// VOImage implementation +//------------------------------------------------------------------- +// +// Copyright ©2000 Virtual Office Systems Incorporated +// All Rights Reserved +// +// This code may be used in compiled form in any way you desire. This +// file may be redistributed unmodified by any means PROVIDING it is +// not sold for profit without the authors written consent, and +// providing that this notice and the authors name is included. +// +// This code can be compiled, modified and distributed freely, providing +// that this copyright information remains intact in the distribution. +// +// This code may be compiled in original or modified form in any private +// or commercial application. +// +// This file is provided "as is" with no expressed or implied warranty. +// The author accepts no liability for any damage, in any form, caused +// by this code. Use it at your own risk. +//------------------------------------------------------------------- + +#include "stdafx.h" + +#include "VOImage.h" + +#ifdef _DEBUG +#undef THIS_FILE +static char THIS_FILE[]=__FILE__; +#define new DEBUG_NEW +#endif + +////////////////////////////////////////////////////////////////////// +// Construction/Destruction +////////////////////////////////////////////////////////////////////// + +HDC CVOImage::g_hdc; +int CVOImage::g_iScale = 100; +int CVOImage::g_iMaxWidth = 10000; +int CVOImage::g_iMaxHeight = 10000; +BOOL CVOImage::g_bStretchBlt = FALSE; + +CVOImage::CVOImage() +{ + m_hbitmap = 0; +} + +CVOImage::~CVOImage() +{ + if(m_hbitmap) + DeleteObject(m_hbitmap); +} + +BOOL CVOImage::Load(HDC hdc, LPCTSTR pcszFileName) +{ + if(m_hbitmap) + DeleteObject(m_hbitmap); + + if(!g_hdc) + g_hdc = CreateCompatibleDC(hdc); + + HRESULT hr; + BYTE szBuffer[1024] = {0}; + HANDLE hFile = INVALID_HANDLE_VALUE; + + DecompressImageInfo dii; + + hFile = CreateFile(pcszFileName, GENERIC_READ, FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); + if (hFile == INVALID_HANDLE_VALUE) + return FALSE; + + // Fill in the 'DecompressImageInfo' structure + dii.dwSize = sizeof( DecompressImageInfo ); // Size of this structure + dii.pbBuffer = szBuffer; // Pointer to the buffer to use for data + dii.dwBufferMax = 1024; // Size of the buffer + dii.dwBufferCurrent = 0; // The amount of data which is current in the buffer + dii.phBM = &m_hbitmap; // Pointer to the bitmap returned (can be NULL) + dii.ppImageRender = NULL; // Pointer to an IImageRender object (can be NULL) + dii.iBitDepth = GetDeviceCaps(hdc,BITSPIXEL); // Bit depth of the output image + dii.lParam = ( LPARAM ) hFile; // User parameter for callback functions + dii.hdc = g_hdc; // HDC to use for retrieving palettes + dii.iScale = g_iScale; // Scale factor (1 - 100) + dii.iMaxWidth = g_iMaxWidth; // Maximum width of the output image + dii.iMaxHeight = g_iMaxHeight; // Maxumum height of the output image + dii.pfnGetData = GetImageData; // Callback function to get image data + dii.pfnImageProgress = ImageProgress; // Callback function to notify caller of progress decoding the image + dii.crTransparentOverride = ( UINT ) -1; // If this color is not (UINT)-1, it will override the + // transparent color in the image with this color. (GIF ONLY) + + // Process and decompress the image data + hr = DecompressImageIndirect( &dii ); + + // Clean up + CloseHandle( hFile ); + + BITMAP bmp; + + GetObject(m_hbitmap, sizeof(BITMAP), &bmp); + + m_dwWidth = bmp.bmWidth; + m_dwHeight = bmp.bmHeight; + + return TRUE; +} + +HBITMAP CVOImage::Copy() +{ + BITMAP bm, bmNew; + HBITMAP hNew; + + SelectObject(g_hdc, m_hbitmap); + + ::GetObject(m_hbitmap, sizeof(BITMAP), &bm); + + HDC hdc = CreateCompatibleDC(g_hdc); + hNew = CreateCompatibleBitmap(g_hdc, bm.bmWidth, bm.bmHeight); + SelectObject(hdc, hNew); + + if(BitBlt(hdc, 0, 0, bm.bmWidth, bm.bmHeight, g_hdc, 0, 0, SRCCOPY)) + { + HBITMAP hPrev = (HBITMAP) ::GetObject(hNew, sizeof(BITMAP), &bmNew); + + ::SelectObject(hdc, hPrev); + } + + DeleteDC(hdc); + return hNew; +} + +BOOL CVOImage::Draw(HDC hdc, int x, int y, int cx, int cy) +{ + BITMAP bmp; + HGDIOBJ hOldBitmap; + + g_bStretchBlt = !(cx == -1 && cy == -1); + hOldBitmap = SelectObject(g_hdc, m_hbitmap); + GetObject(m_hbitmap, sizeof(BITMAP), &bmp); + + if (g_bStretchBlt) + { + // Stretch to fit + StretchBlt(hdc, x , y, cx, cy, g_hdc,0,0,bmp.bmWidth,bmp.bmHeight,SRCCOPY ); + } + else + { + BitBlt(hdc, x, y, bmp.bmWidth, bmp.bmHeight, g_hdc,0,0,SRCCOPY ); + } + + SelectObject(g_hdc, hOldBitmap); + + return TRUE; +} + +DWORD CVOImage::GetHeight() +{ + return m_dwHeight; +} + +DWORD CVOImage::GetWidth() +{ + return m_dwWidth; +} + +BOOL CVOImage::SetBitmap(HDC hdc, DWORD dwResourceID, LPCTSTR pcszClass, HMODULE hModule) +{ + if(!g_hdc) + g_hdc = CreateCompatibleDC(hdc); + + HRESULT hr; + BYTE szBuffer[1024] = {0}; + DecompressImageInfo dii; + + CVOResource res(hModule, dwResourceID, pcszClass); + + if(!res.IsLoaded()) + return FALSE; + + res.SetUserData(0); // Use this for the current resource offset + + // Fill in the 'DecompressImageInfo' structure + dii.dwSize = sizeof( DecompressImageInfo ); // Size of this structure + dii.pbBuffer = szBuffer; // Pointer to the buffer to use for data + dii.dwBufferMax = 1024; // Size of the buffer + dii.dwBufferCurrent = 0; // The amount of data which is current in the buffer + dii.phBM = &m_hbitmap; // Pointer to the bitmap returned (can be NULL) + dii.ppImageRender = NULL; // Pointer to an IImageRender object (can be NULL) + dii.iBitDepth = GetDeviceCaps(hdc,BITSPIXEL); // Bit depth of the output image + dii.lParam = ( LPARAM ) &res; // User parameter for callback functions + dii.hdc = g_hdc; // HDC to use for retrieving palettes + dii.iScale = g_iScale; // Scale factor (1 - 100) + dii.iMaxWidth = g_iMaxWidth; // Maximum width of the output image + dii.iMaxHeight = g_iMaxHeight; // Maxumum height of the output image + dii.pfnGetData = GetImageResourceData; // Callback function to get image data + dii.pfnImageProgress = ImageProgress; // Callback function to notify caller of progress decoding the image + dii.crTransparentOverride = ( UINT ) -1; // If this color is not (UINT)-1, it will override the + // transparent color in the image with this color. (GIF ONLY) + // Process and decompress the image data + hr = DecompressImageIndirect( &dii ); + + BITMAP bmp; + + GetObject(m_hbitmap, sizeof(BITMAP), &bmp); + + m_dwWidth = bmp.bmWidth; + m_dwHeight = bmp.bmHeight; + + return TRUE; +} + +DWORD CALLBACK CVOImage::GetImageData(LPSTR szBuffer, DWORD dwBufferMax, LPARAM lParam ) +{ + DWORD dwNumberOfBytesRead; + + if ( (HANDLE)lParam == INVALID_HANDLE_VALUE ) + return 0; + + ReadFile( (HANDLE)lParam, szBuffer, dwBufferMax, &dwNumberOfBytesRead, NULL ); + + // Return number of bytes read + return dwNumberOfBytesRead; +} + +DWORD CALLBACK CVOImage::GetImageResourceData(LPSTR szBuffer, DWORD dwBufferMax, LPARAM lParam) +{ + DWORD dwNumberOfBytesToRead = dwBufferMax; + CVOResource* pRes = (CVOResource*) lParam; + + if(!pRes) + return 0; + + DWORD dwResourceOffset = pRes->GetUserData(); + + if(dwResourceOffset + dwNumberOfBytesToRead > pRes->GetSize() ) + dwNumberOfBytesToRead = pRes->GetSize() - dwResourceOffset; + + memmove(szBuffer, pRes->GetData() + dwResourceOffset, dwNumberOfBytesToRead); + + pRes->SetUserData(dwResourceOffset + dwNumberOfBytesToRead); + return dwNumberOfBytesToRead; // return amount read +} + +void CALLBACK CVOImage::ImageProgress(IImageRender *pRender, BOOL bComplete, LPARAM lParam ) +{ + if( bComplete ) + { + ;// (Optional) add code here for completion processing + } +} + +BOOL CVOImage::IsLoaded() +{ + return (m_hbitmap != 0); +} + +CVOResource::CVOResource(HMODULE hModule, DWORD dwResourceID, LPCTSTR pcszClass) +{ + m_dwSize = 0; + m_hGlobal = 0; + m_pData = 0; + + m_hrsrc = FindResource(hModule, (LPCWSTR)dwResourceID, pcszClass); + + if(m_hrsrc == 0) + return; + + m_dwSize = SizeofResource(hModule, m_hrsrc); + m_hGlobal = LoadResource(hModule, m_hrsrc); + m_pData = (PBYTE) LockResource(m_hGlobal); +} + +CVOResource::~CVOResource() +{ + if(m_hGlobal) + DeleteObject(m_hGlobal); +} + +BOOL CVOResource::IsLoaded() +{ + return (m_pData != NULL); +} diff --git a/src/VOIMAGE.H b/src/VOIMAGE.H new file mode 100644 index 0000000..2825b58 --- /dev/null +++ b/src/VOIMAGE.H @@ -0,0 +1,84 @@ +//------------------------------------------------------------------- +// VOImage Header File +//------------------------------------------------------------------- +// +// Copyright ©2000 Virtual Office Systems Incorporated +// All Rights Reserved +// +// This code may be used in compiled form in any way you desire. This +// file may be redistributed unmodified by any means PROVIDING it is +// not sold for profit without the authors written consent, and +// providing that this notice and the authors name is included. +// +// This code can be compiled, modified and distributed freely, providing +// that this copyright information remains intact in the distribution. +// +// This code may be compiled in original or modified form in any private +// or commercial application. +// +// This file is provided "as is" with no expressed or implied warranty. +// The author accepts no liability for any damage, in any form, caused +// by this code. Use it at your own risk. +//------------------------------------------------------------------- + +#if !defined(AFX_VOIMAGE_H__B83C4202_DB1E_48BE_92A5_21019F9EE6FC__INCLUDED_) +#define AFX_VOIMAGE_H__B83C4202_DB1E_48BE_92A5_21019F9EE6FC__INCLUDED_ + +#if _MSC_VER > 1000 +#pragma once +#endif // _MSC_VER > 1000 + +#include "imgdecmp.h" + +class CVOResource +{ +public: + CVOResource(HMODULE hModule, DWORD dwResourceID, LPCTSTR pcszClass); + ~CVOResource(); + + BOOL IsLoaded(); + + DWORD GetSize() { return m_dwSize; } + PBYTE GetData() { return m_pData; } + + void SetUserData(DWORD dwValue) { m_dwUser = dwValue; } + DWORD GetUserData() { return m_dwUser; } + +protected: + DWORD m_dwUser; + + DWORD m_dwSize; + PBYTE m_pData; + HGLOBAL m_hGlobal; + HRSRC m_hrsrc; +}; + +class CVOImage +{ +public: + HBITMAP Copy(); + static DWORD CALLBACK GetImageResourceData(LPSTR szBuffer, DWORD dwBufferMax, LPARAM lParam); + BOOL IsLoaded(); + static void CALLBACK ImageProgress( IImageRender *, BOOL, LPARAM); + static DWORD CALLBACK GetImageData( LPSTR, DWORD, LPARAM); + BOOL SetBitmap(HDC hdc, DWORD dwResourceID, LPCTSTR pcszClass = TEXT("IMAGE"), HMODULE hModule = 0 ); + DWORD GetWidth(); + DWORD GetHeight(); + BOOL Draw(HDC hdc, int x, int y, int cx = -1, int cy = -1); + BOOL Load(HDC hdc, LPCTSTR pcszFileName); + CVOImage(); + virtual ~CVOImage(); + operator HBITMAP() { return m_hbitmap; } + +protected: + DWORD m_dwHeight; + DWORD m_dwWidth; + HBITMAP m_hbitmap; + static BOOL g_bStretchBlt; + static int g_iMaxHeight; + static int g_iMaxWidth; + static int g_iScale; + static HDC g_hdc; +}; + +#endif // !defined(AFX_VOIMAGE_H__B83C4202_DB1E_48BE_92A5_21019F9EE6FC__INCLUDED_) diff --git a/src/apu.cpp b/src/apu.cpp new file mode 100644 index 0000000..2e83a00 --- /dev/null +++ b/src/apu.cpp @@ -0,0 +1,1181 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#include "snes9x.h" +#include "spc700.h" +#include "apu.h" +#include "soundux.h" +#include "cpuexec.h" + +/* For note-triggered SPC dump support */ +//#include "snapshot.h" + +//extern int NoiseFreq [32]; +#ifdef DEBUGGER +void S9xTraceSoundDSP (const char *s, int i1 = 0, int i2 = 0, int i3 = 0, + int i4 = 0, int i5 = 0, int i6 = 0, int i7 = 0); +#endif + +#undef ABS +#define ABS(a) ((a) < 0 ? -(a) : (a)) +#define ENVX_SHIFT 24 + + +unsigned long AttackRate [16] = { + 4100, 2600, 1500, 1000, 640, 380, 260, 160, + 96, 64, 40, 24, 16, 10, 6, 1 +}; + +unsigned long DecayRate [8] = { + 1200, 740, 440, 290, 180, 110, 74, 37 +}; + +unsigned long SustainRate [32] = { + /*~0*/0xFFFFFFFF, 38000, 28000, 24000, 19000, 14000, 12000, 9400, + 7100, 5900, 4700, 3500, 2900, 2400, 1800, 1500, + 1200, 880, 740, 590, 440, 370, 290, 220, + 180, 150, 110, 92, 74, 55, 37, 18 +}; + +unsigned long IncreaseRate [32] = { + /*~0*/0xFFFFFFFF, 4100, 3100, 2600, 2000, 1500, 1300, 1000, + 770, 640, 510, 380, 320, 260, 190, 160, + 130, 96, 80, 64, 48, 40, 32, 24, + 20, 16, 12, 10, 8, 6, 4, 2 +}; + +unsigned long DecreaseRateExp [32] = { + /*~0*/0xFFFFFFFF, 38000, 28000, 24000, 19000, 14000, 12000, 9400, + 7100, 5900, 4700, 3500, 2900, 2400, 1800, 1500, + 1200, 880, 740, 590, 440, 370, 290, 220, + 180, 150, 110, 92, 74, 55, 37, 18 +}; + +// precalculated env rates for S9xSetEnvRate +unsigned long AttackERate [16][10]; +unsigned long DecayERate [8][10]; +unsigned long SustainERate [32][10]; +unsigned long IncreaseERate [32][10]; +unsigned long DecreaseERateExp[32][10]; +unsigned long KeyOffERate[10]; + + +static inline void S9xSetEnvelopeRate (int channel, unsigned long rate, int direction, int target, unsigned int mode) +{ + S9xSetEnvRate (&SoundData.channels [channel], rate, direction, target, mode); +} + +static inline void S9xSetSoundADSR (int channel, int attack_ind, int decay_ind, + int sustain_ind, int sustain_level, int release_rate) +{ + int attack_rate = AttackRate [attack_ind]; + int decay_rate = DecayRate [decay_ind]; + int sustain_rate = SustainRate [sustain_ind]; + + // Hack for ROMs that use a very short attack rate, key on a + // channel, then switch to decay mode. e.g. Final Fantasy II. + if (attack_rate == 1) + attack_rate = 0; + + SoundData.channels[channel].env_ind_attack = attack_ind; + SoundData.channels[channel].env_ind_decay = decay_ind; + SoundData.channels[channel].env_ind_sustain = sustain_ind; + + SoundData.channels[channel].attack_rate = attack_rate; + SoundData.channels[channel].decay_rate = decay_rate; + SoundData.channels[channel].sustain_rate = sustain_rate; + SoundData.channels[channel].release_rate = release_rate; + SoundData.channels[channel].sustain_level = sustain_level + 1; + + switch (SoundData.channels[channel].state) + { + case SOUND_ATTACK: + S9xSetEnvelopeRate (channel, attack_rate, 1, 127, 0); + break; + + case SOUND_DECAY: + S9xSetEnvelopeRate (channel, decay_rate, -1, + (MAX_ENVELOPE_HEIGHT * (sustain_level + 1)) >> 3, 1<<28); + break; + case SOUND_SUSTAIN: + S9xSetEnvelopeRate (channel, sustain_rate, -1, 0, 2<<28); + break; + } +} + +static inline void S9xSetSoundVolume (int channel, short volume_left, short volume_right) +{ + Channel *ch = &SoundData.channels[channel]; + if (!so.stereo) + volume_left = (ABS(volume_right) + ABS(volume_left)) / 2; + + ch->volume_left = volume_left; + ch->volume_right = volume_right; + ch-> left_vol_level = (ch->envx * volume_left) / 128; + ch->right_vol_level = (ch->envx * volume_right) / 128; +} + +static inline void S9xSetMasterVolume (short volume_left, short volume_right) +{ + if (Settings.DisableMasterVolume) + { + SoundData.master_volume_left = 127; + SoundData.master_volume_right = 127; + SoundData.master_volume [0] = SoundData.master_volume [1] = 127; + } + else + { + if (!so.stereo) + volume_left = (ABS (volume_right) + ABS (volume_left)) / 2; + SoundData.master_volume_left = volume_left; + SoundData.master_volume_right = volume_right; + SoundData.master_volume [0] = volume_left; + SoundData.master_volume [1] = volume_right; + } +} + +static inline void S9xSetEchoVolume (short volume_left, short volume_right) +{ + if (!so.stereo) + volume_left = (ABS (volume_right) + ABS (volume_left)) / 2; + SoundData.echo_volume_left = volume_left; + SoundData.echo_volume_right = volume_right; + SoundData.echo_volume [0] = volume_left; + SoundData.echo_volume [1] = volume_right; +} + +static inline void S9xSetEchoWriteEnable (uint8 byte) +{ + SoundData.echo_write_enabled = byte; + S9xSetEchoDelay (APU.DSP [APU_EDL] & 15); +} + +static inline void S9xSetFrequencyModulationEnable (uint8 byte) +{ + SoundData.pitch_mod = byte & (0xFE);//~1; +} + +static inline int S9xGetEnvelopeHeight (int channel) +{ + if ((Settings.SoundEnvelopeHeightReading || + SNESGameFixes.SoundEnvelopeHeightReading2) && + SoundData.channels[channel].state != SOUND_SILENT && + SoundData.channels[channel].state != SOUND_GAIN) + { + return (SoundData.channels[channel].envx); + } + + //siren fix from XPP + if (SNESGameFixes.SoundEnvelopeHeightReading2 && + SoundData.channels[channel].state != SOUND_SILENT) + { + return (SoundData.channels[channel].envx); + } + + return (0); +} + +static inline void S9xSetSoundHertz (int channel, int hertz) +{ + SoundData.channels[channel].hertz = hertz; + S9xSetSoundFrequency (channel, hertz); +} + +static inline void S9xSetSoundType (int channel, int type_of_sound) +{ + SoundData.channels[channel].type = type_of_sound; +} + +static inline bool8 S9xSetSoundMode (int channel, int mode) +{ + Channel *ch = &SoundData.channels[channel]; + + switch (mode) + { + case MODE_RELEASE: + if (ch->mode != MODE_NONE) + { + ch->mode = MODE_RELEASE; + return (TRUE); + } + break; + + case MODE_DECREASE_LINEAR: + case MODE_DECREASE_EXPONENTIAL: + case MODE_GAIN: + if (ch->mode != MODE_RELEASE) + { + ch->mode = mode; + if (ch->state != SOUND_SILENT) + ch->state = mode; + + return (TRUE); + } + break; + + case MODE_INCREASE_LINEAR: + case MODE_INCREASE_BENT_LINE: + if (ch->mode != MODE_RELEASE) + { + ch->mode = mode; + if (ch->state != SOUND_SILENT) + ch->state = mode; + + + + + return (TRUE); + } + break; + + case MODE_ADSR: + if (ch->mode == MODE_NONE || ch->mode == MODE_ADSR) + { + ch->mode = mode; + return (TRUE); + } + } + + return (FALSE); +} + +static inline void S9xPlaySample (int channel) +{ + Channel *ch = &SoundData.channels[channel]; + + ch->state = SOUND_SILENT; + ch->mode = MODE_NONE; + ch->envx = 0; + ch->envxx = 0; + + ch->g_index=0; + ch->gaussian[0]=ch->gaussian[1]=ch->gaussian[2]=ch->gaussian[3]=0; + + S9xFixEnvelope (channel, + APU.DSP [APU_GAIN + (channel << 4)], + APU.DSP [APU_ADSR1 + (channel << 4)], + APU.DSP [APU_ADSR2 + (channel << 4)]); + + ch->sample_number = APU.DSP [APU_SRCN + channel * 0x10]; + if (APU.DSP [APU_NON] & (1 << channel)) + ch->type = SOUND_NOISE; + else + ch->type = SOUND_SAMPLE; + + S9xSetSoundFrequency (channel, ch->hertz); + ch->loop = FALSE; + ch->needs_decode = TRUE; + ch->last_block = FALSE; + ch->previous [0] = ch->previous[1] = 0; + ch->block_pointer = *S9xGetSampleAddress(ch->sample_number); + ch->sample_pointer = 0; + ch->env_error = 0; + ch->next_sample = 0; + ch->interpolate = 0; + ch->last_valid_header=0; + switch (ch->mode) + { + case MODE_ADSR: + if (ch->attack_rate == 0) + { + if (ch->decay_rate == 0 || ch->sustain_level == 8) + { + ch->state = SOUND_SUSTAIN; + ch->envx = (MAX_ENVELOPE_HEIGHT * ch->sustain_level) >> 3; + S9xSetEnvRate (ch, ch->sustain_rate, -1, 0, 2<<28); + } + else + { + ch->state = SOUND_DECAY; + ch->envx = MAX_ENVELOPE_HEIGHT; + S9xSetEnvRate (ch, ch->decay_rate, -1, + (MAX_ENVELOPE_HEIGHT * ch->sustain_level) >> 3, 1<<28); + } + ch-> left_vol_level = (ch->envx * ch->volume_left) / 128; + ch->right_vol_level = (ch->envx * ch->volume_right) / 128; + } + else + { + ch->state = SOUND_ATTACK; + ch->envx = 0; + ch->left_vol_level = 0; + ch->right_vol_level = 0; + S9xSetEnvRate (ch, ch->attack_rate, 1, MAX_ENVELOPE_HEIGHT, 0); + } + ch->envxx = ch->envx << ENVX_SHIFT; + break; + + case MODE_GAIN: + ch->state = SOUND_GAIN; + break; + + case MODE_INCREASE_LINEAR: + ch->state = SOUND_INCREASE_LINEAR; + break; + + case MODE_INCREASE_BENT_LINE: + ch->state = SOUND_INCREASE_BENT_LINE; + break; + + case MODE_DECREASE_LINEAR: + ch->state = SOUND_DECREASE_LINEAR; + break; + + case MODE_DECREASE_EXPONENTIAL: + ch->state = SOUND_DECREASE_EXPONENTIAL; + break; + + default: + break; + } + + S9xFixEnvelope (channel, + APU.DSP [APU_GAIN + (channel << 4)], + APU.DSP [APU_ADSR1 + (channel << 4)], + APU.DSP [APU_ADSR2 + (channel << 4)]); +} + +extern "C" uint32 Spc700JumpTab_15; + +bool8 S9xInitAPU () +{ + // notaz + memset(&IAPU, 0, sizeof(IAPU)); + IAPU.ExtraRAM = APU.ExtraRAM; + IAPU.asmJumpTab = &Spc700JumpTab_15; // Normal case: ONE_APU_CYCLE = 15 + + IAPU.RAM = (uint8 *) malloc (0x10000); + IAPU.ShadowRAM = NULL;//(uint8 *) malloc (0x10000); + IAPU.CachedSamples = NULL;//(uint8 *) malloc (0x40000); + + if (!IAPU.RAM /*|| !IAPU.ShadowRAM || !IAPU.CachedSamples*/) + { + S9xDeinitAPU (); + return (FALSE); + } + + return (TRUE); +} + +void S9xDeinitAPU () +{ + if (IAPU.RAM) + { + free ((char *) IAPU.RAM); + IAPU.RAM = NULL; + } + if (IAPU.ShadowRAM) + { + free ((char *) IAPU.ShadowRAM); + IAPU.ShadowRAM = NULL; + } + if (IAPU.CachedSamples) + { + free ((char *) IAPU.CachedSamples); + IAPU.CachedSamples = NULL; + } +} + +EXTERN_C uint8 APUROM [64]; + +void S9xResetAPU () +{ +// Settings.APUEnabled = Settings.NextAPUEnabled; + + ZeroMemory(IAPU.RAM, 0x100); + memset(IAPU.RAM+0x20, 0xFF, 0x20); + memset(IAPU.RAM+0x60, 0xFF, 0x20); + memset(IAPU.RAM+0xA0, 0xFF, 0x20); + memset(IAPU.RAM+0xE0, 0xFF, 0x20); + + for(int i=1;i<256;i++) + { + memcpy(IAPU.RAM+(i<<8), IAPU.RAM, 0x100); + } + //ZeroMemory (IAPU.CachedSamples, 0x40000); + ZeroMemory (APU.OutPorts, 4); + IAPU.DirectPage = IAPU.RAM; + memmove (&IAPU.RAM [0xffc0], APUROM, sizeof (APUROM)); + memmove (APU.ExtraRAM, APUROM, sizeof (APUROM)); + IAPU.PC = IAPU.RAM + IAPU.RAM [0xfffe] + (IAPU.RAM [0xffff] << 8); + CPU.APU_Cycles = 0; + IAPU.YA.W = 0; + IAPU.X = 0; + IAPU.S = 0xff; + IAPU.P = 0; + S9xAPUUnpackStatus (); + CPU.APU_APUExecuting = Settings.APUEnabled; +#ifdef SPC700_SHUTDOWN + IAPU.WaitAddress1 = NULL; + IAPU.WaitAddress2 = NULL; + IAPU.WaitCounter = 0; +#endif + APU.ShowROM = TRUE; + IAPU.RAM [0xf1] = 0x80; + + int i; + + for (i = 0; i < 3; i++) + { + APU.TimerEnabled [i] = FALSE; + APU.TimerValueWritten [i] = 0; + APU.TimerTarget [i] = 0; + APU.Timer [i] = 0; + } + for (int j = 0; j < 0x80; j++) + APU.DSP [j] = 0; + + IAPU.TwoCycles = IAPU.OneCycle * 2; + + for (i = 0; i < 256; i++) + S9xAPUCycles [i] = S9xAPUCycleLengths [i] * IAPU.OneCycle; + + APU.DSP [APU_ENDX] = 0; + APU.DSP [APU_KOFF] = 0; + APU.DSP [APU_KON] = 0; + APU.DSP [APU_FLG] = APU_MUTE | APU_ECHO_DISABLED; + APU.KeyedChannels = 0; + + S9xResetSound (TRUE); + S9xSetEchoEnable (0); +} + +extern int framecpto; +void S9xSetAPUDSP (uint8 byte) +{ + uint8 reg = IAPU.RAM [0xf2]; + static uint8 KeyOn; + static uint8 KeyOnPrev; + int i; + +/* char str[64]; + if (byte!=0) + { + sprintf(str,"fr : %d\nwrite dsp %d\ncpu cycle=%d pc=%04X",framecpto,byte,CPU.Cycles,CPU.PC-CPU.PCBase); + S9xMessage(0,0,str); + gp32_pause(); + }*/ + + //extern uint8 spc_dump_dsp[0x100]; + + //spc_dump_dsp[reg] = byte; + + switch (reg) + { + case APU_FLG: + if (byte & APU_SOFT_RESET) + { + APU.DSP [reg] = APU_MUTE | APU_ECHO_DISABLED | (byte & 0x1f); + APU.DSP [APU_ENDX] = 0; + APU.DSP [APU_KOFF] = 0; + APU.DSP [APU_KON] = 0; + S9xSetEchoWriteEnable (FALSE); +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] DSP reset\n", ICPU.Scanline); +#endif + // Kill sound + S9xResetSound (FALSE); + } + else + { + S9xSetEchoWriteEnable (!(byte & APU_ECHO_DISABLED)); + if (byte & APU_MUTE) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Mute sound\n", ICPU.Scanline); +#endif + S9xSetSoundMute (TRUE); + } + else + S9xSetSoundMute (FALSE); + + SoundData.noise_hertz = NoiseFreq [byte & 0x1f]; + for (i = 0; i < 8; i++) + { + if (SoundData.channels [i].type == SOUND_NOISE) + S9xSetSoundFrequency (i, SoundData.noise_hertz); + } + } + break; + case APU_NON: + if (byte != APU.DSP [APU_NON]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Noise:", ICPU.Scanline); +#endif + uint8 mask = 1; + for (int c = 0; c < 8; c++, mask <<= 1) + { + int type; + if (byte & mask) + { + type = SOUND_NOISE; +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + { + if (APU.DSP [reg] & mask) + S9xTraceSoundDSP ("%d,", c); + else + S9xTraceSoundDSP ("%d(on),", c); + } +#endif + } + else + { + type = SOUND_SAMPLE; +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + { + if (APU.DSP [reg] & mask) + S9xTraceSoundDSP ("%d(off),", c); + } +#endif + } + S9xSetSoundType (c, type); + } +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("\n"); +#endif + } + break; + case APU_MVOL_LEFT: + if (byte != APU.DSP [APU_MVOL_LEFT]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Master volume left:%d\n", + ICPU.Scanline, (signed char) byte); +#endif + S9xSetMasterVolume ((signed char) byte, + (signed char) APU.DSP [APU_MVOL_RIGHT]); + } + break; + case APU_MVOL_RIGHT: + if (byte != APU.DSP [APU_MVOL_RIGHT]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Master volume right:%d\n", + ICPU.Scanline, (signed char) byte); +#endif + S9xSetMasterVolume ((signed char) APU.DSP [APU_MVOL_LEFT], + (signed char) byte); + } + break; + case APU_EVOL_LEFT: + if (byte != APU.DSP [APU_EVOL_LEFT]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Echo volume left:%d\n", + ICPU.Scanline, (signed char) byte); +#endif + S9xSetEchoVolume ((signed char) byte, + (signed char) APU.DSP [APU_EVOL_RIGHT]); + } + break; + case APU_EVOL_RIGHT: + if (byte != APU.DSP [APU_EVOL_RIGHT]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Echo volume right:%d\n", + ICPU.Scanline, (signed char) byte); +#endif + S9xSetEchoVolume ((signed char) APU.DSP [APU_EVOL_LEFT], + (signed char) byte); + } + break; + case APU_ENDX: +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Reset ENDX\n", ICPU.Scanline); +#endif + byte = 0; + break; + + case APU_KOFF: + // if (byte) + { + uint8 mask = 1; +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Key off:", ICPU.Scanline); +#endif + for (int c = 0; c < 8; c++, mask <<= 1) + { + if ((byte & mask) != 0) + { +#ifdef DEBUGGER + + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("%d,", c); +#endif + if (APU.KeyedChannels & mask) + { + { + KeyOnPrev&=~mask; + APU.KeyedChannels &= ~mask; + APU.DSP [APU_KON] &= ~mask; + //APU.DSP [APU_KOFF] |= mask; + S9xSetSoundKeyOff (c); + } + } + } + else if((KeyOnPrev&mask)!=0) + { + KeyOnPrev&=~mask; + APU.KeyedChannels |= mask; + //APU.DSP [APU_KON] |= mask; + APU.DSP [APU_KOFF] &= ~mask; + APU.DSP [APU_ENDX] &= ~mask; + S9xPlaySample (c); + } + } +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("\n"); +#endif + } + //KeyOnPrev=0; + APU.DSP [APU_KOFF] = byte; + return; + case APU_KON: + + if (byte) + { + uint8 mask = 1; +#ifdef DEBUGGER + + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Key on:", ICPU.Scanline); +#endif + for (int c = 0; c < 8; c++, mask <<= 1) + { + if ((byte & mask) != 0) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("%d,", c); +#endif + // Pac-In-Time requires that channels can be key-on + // regardeless of their current state. + if((APU.DSP [APU_KOFF] & mask) ==0) + { + KeyOnPrev&=~mask; + APU.KeyedChannels |= mask; + //APU.DSP [APU_KON] |= mask; + //APU.DSP [APU_KOFF] &= ~mask; + APU.DSP [APU_ENDX] &= ~mask; + S9xPlaySample (c); + } + else KeyOn|=mask; + } + } +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("\n"); +#endif + } + //spc_is_dumping_temp = byte; + return; + + case APU_VOL_LEFT + 0x00: + case APU_VOL_LEFT + 0x10: + case APU_VOL_LEFT + 0x20: + case APU_VOL_LEFT + 0x30: + case APU_VOL_LEFT + 0x40: + case APU_VOL_LEFT + 0x50: + case APU_VOL_LEFT + 0x60: + case APU_VOL_LEFT + 0x70: +// At Shin Megami Tensei suggestion 6/11/00 +// if (byte != APU.DSP [reg]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] %d volume left: %d\n", + ICPU.Scanline, reg>>4, (signed char) byte); +#endif + S9xSetSoundVolume (reg >> 4, (signed char) byte, + (signed char) APU.DSP [reg + 1]); + } + break; + case APU_VOL_RIGHT + 0x00: + case APU_VOL_RIGHT + 0x10: + case APU_VOL_RIGHT + 0x20: + case APU_VOL_RIGHT + 0x30: + case APU_VOL_RIGHT + 0x40: + case APU_VOL_RIGHT + 0x50: + case APU_VOL_RIGHT + 0x60: + case APU_VOL_RIGHT + 0x70: +// At Shin Megami Tensei suggestion 6/11/00 +// if (byte != APU.DSP [reg]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] %d volume right: %d\n", + ICPU.Scanline, reg >>4, (signed char) byte); +#endif + S9xSetSoundVolume (reg >> 4, (signed char) APU.DSP [reg - 1], + (signed char) byte); + } + break; + + case APU_P_LOW + 0x00: + case APU_P_LOW + 0x10: + case APU_P_LOW + 0x20: + case APU_P_LOW + 0x30: + case APU_P_LOW + 0x40: + case APU_P_LOW + 0x50: + case APU_P_LOW + 0x60: + case APU_P_LOW + 0x70: +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] %d freq low: %d\n", + ICPU.Scanline, reg>>4, byte); +#endif + S9xSetSoundHertz (reg >> 4, (((byte + (APU.DSP [reg + 1] << 8)) & FREQUENCY_MASK) * 32000) >> 12); + break; + + case APU_P_HIGH + 0x00: + case APU_P_HIGH + 0x10: + case APU_P_HIGH + 0x20: + case APU_P_HIGH + 0x30: + case APU_P_HIGH + 0x40: + case APU_P_HIGH + 0x50: + case APU_P_HIGH + 0x60: + case APU_P_HIGH + 0x70: +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] %d freq high: %d\n", + ICPU.Scanline, reg>>4, byte); +#endif + S9xSetSoundHertz (reg >> 4, + (((byte << 8) + APU.DSP [reg - 1]) & FREQUENCY_MASK) * 8); + break; + + case APU_SRCN + 0x00: + case APU_SRCN + 0x10: + case APU_SRCN + 0x20: + case APU_SRCN + 0x30: + case APU_SRCN + 0x40: + case APU_SRCN + 0x50: + case APU_SRCN + 0x60: + case APU_SRCN + 0x70: + if (byte != APU.DSP [reg]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] %d sample number: %d\n", + ICPU.Scanline, reg>>4, byte); +#endif + //S9xSetSoundSample (reg >> 4, byte); // notaz: seems to be unused? + } + break; + + case APU_ADSR1 + 0x00: + case APU_ADSR1 + 0x10: + case APU_ADSR1 + 0x20: + case APU_ADSR1 + 0x30: + case APU_ADSR1 + 0x40: + case APU_ADSR1 + 0x50: + case APU_ADSR1 + 0x60: + case APU_ADSR1 + 0x70: + if (byte != APU.DSP [reg]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] %d adsr1: %02x\n", + ICPU.Scanline, reg>>4, byte); +#endif + { + S9xFixEnvelope (reg >> 4, APU.DSP [reg + 2], byte, + APU.DSP [reg + 1]); + } + } + break; + + case APU_ADSR2 + 0x00: + case APU_ADSR2 + 0x10: + case APU_ADSR2 + 0x20: + case APU_ADSR2 + 0x30: + case APU_ADSR2 + 0x40: + case APU_ADSR2 + 0x50: + case APU_ADSR2 + 0x60: + case APU_ADSR2 + 0x70: + if (byte != APU.DSP [reg]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] %d adsr2: %02x\n", + ICPU.Scanline, reg>>4, byte); +#endif + { + S9xFixEnvelope (reg >> 4, APU.DSP [reg + 1], APU.DSP [reg - 1], + byte); + } + } + break; + + case APU_GAIN + 0x00: + case APU_GAIN + 0x10: + case APU_GAIN + 0x20: + case APU_GAIN + 0x30: + case APU_GAIN + 0x40: + case APU_GAIN + 0x50: + case APU_GAIN + 0x60: + case APU_GAIN + 0x70: + if (byte != APU.DSP [reg]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] %d gain: %02x\n", + ICPU.Scanline, reg>>4, byte); +#endif + { + S9xFixEnvelope (reg >> 4, byte, APU.DSP [reg - 2], + APU.DSP [reg - 1]); + } + } + break; + + case APU_ENVX + 0x00: + case APU_ENVX + 0x10: + case APU_ENVX + 0x20: + case APU_ENVX + 0x30: + case APU_ENVX + 0x40: + case APU_ENVX + 0x50: + case APU_ENVX + 0x60: + case APU_ENVX + 0x70: + break; + + case APU_OUTX + 0x00: + case APU_OUTX + 0x10: + case APU_OUTX + 0x20: + case APU_OUTX + 0x30: + case APU_OUTX + 0x40: + case APU_OUTX + 0x50: + case APU_OUTX + 0x60: + case APU_OUTX + 0x70: + break; + + case APU_DIR: +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + S9xTraceSoundDSP ("[%d] Sample directory to: %02x\n", + ICPU.Scanline, byte); +#endif + break; + + case APU_PMON: + if (byte != APU.DSP [APU_PMON]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + { + S9xTraceSoundDSP ("[%d] FreqMod:", ICPU.Scanline); + uint8 mask = 1; + for (int c = 0; c < 8; c++, mask <<= 1) + { + if (byte & mask) + { + if (APU.DSP [reg] & mask) + S9xTraceSoundDSP ("%d", c); + else + S9xTraceSoundDSP ("%d(on),", c); + } + else + { + if (APU.DSP [reg] & mask) + S9xTraceSoundDSP ("%d(off),", c); + } + } + S9xTraceSoundDSP ("\n"); + } +#endif + S9xSetFrequencyModulationEnable (byte); + } + break; + + case APU_EON: + if (byte != APU.DSP [APU_EON]) + { +#ifdef DEBUGGER + if (Settings.TraceSoundDSP) + { + S9xTraceSoundDSP ("[%d] Echo:", ICPU.Scanline); + uint8 mask = 1; + + for (int c = 0; c < 8; c++, mask <<= 1) + { + if (byte & mask) + + { + if (APU.DSP [reg] & mask) + S9xTraceSoundDSP ("%d", c); + else + S9xTraceSoundDSP ("%d(on),", c); + } + else + { + if (APU.DSP [reg] & mask) + S9xTraceSoundDSP ("%d(off),", c); + } + } + S9xTraceSoundDSP ("\n"); + } +#endif + S9xSetEchoEnable (byte); + } + break; + + case APU_EFB: + S9xSetEchoFeedback ((signed char) byte); + break; + + case APU_ESA: + break; + + case APU_EDL: + S9xSetEchoDelay (byte & 0xf); + break; + + case APU_C0: + case APU_C1: + case APU_C2: + case APU_C3: + case APU_C4: + case APU_C5: + case APU_C6: + case APU_C7: + S9xSetFilterCoefficient (reg >> 4, (signed char) byte); + break; + default: +// XXX +//printf ("Write %02x to unknown APU register %02x\n", byte, reg); + break; + } + + KeyOnPrev|=KeyOn; + KeyOn=0; + + if (reg < 0x80) + APU.DSP [reg] = byte; +} + +void S9xFixEnvelope (int channel, uint8 gain, uint8 adsr1, uint8 adsr2) +{ + if (adsr1 & 0x80) + { + // ADSR mode + + // XXX: can DSP be switched to ADSR mode directly from GAIN/INCREASE/ + // DECREASE mode? And if so, what stage of the sequence does it start + // at? + if (S9xSetSoundMode (channel, MODE_ADSR)) + { + S9xSetSoundADSR (channel, adsr1 & 0xf, (adsr1 >> 4) & 7, adsr2 & 0x1f, (adsr2 >> 5) & 7, 8); + } + } + else + { + // Gain mode + if ((gain & 0x80) == 0) + { + if (S9xSetSoundMode (channel, MODE_GAIN)) + { + S9xSetEnvelopeRate (channel, 0, 0, gain & 0x7f, 0); + S9xSetEnvelopeHeight (channel, gain & 0x7f); + } + } + else + { + + if (gain & 0x40) + { + // Increase mode + if (S9xSetSoundMode (channel, (gain & 0x20) ? + MODE_INCREASE_BENT_LINE : + MODE_INCREASE_LINEAR)) + { + S9xSetEnvelopeRate (channel, IncreaseRate [gain & 0x1f], 1, 127, (3<<28)|gain); + } + } + else + { + if(gain & 0x20) { + if (S9xSetSoundMode (channel, MODE_DECREASE_EXPONENTIAL)) + S9xSetEnvelopeRate (channel, DecreaseRateExp [gain & 0x1f] / 2, -1, 0, (4<<28)|gain); + } else { + if (S9xSetSoundMode (channel, MODE_DECREASE_LINEAR)) + S9xSetEnvelopeRate (channel, IncreaseRate [gain & 0x1f], -1, 0, (3<<28)|gain); + } + } + } + } +} + +void S9xSetAPUControl (uint8 byte) +{ +//if (byte & 0x40) +//printf ("*** Special SPC700 timing enabled\n"); + if ((byte & 1) != 0 && !APU.TimerEnabled [0]) + { + APU.Timer [0] = 0; + IAPU.RAM [0xfd] = 0; + if ((APU.TimerTarget [0] = IAPU.RAM [0xfa]) == 0) + APU.TimerTarget [0] = 0x100; + } + if ((byte & 2) != 0 && !APU.TimerEnabled [1]) + { + APU.Timer [1] = 0; + IAPU.RAM [0xfe] = 0; + if ((APU.TimerTarget [1] = IAPU.RAM [0xfb]) == 0) + APU.TimerTarget [1] = 0x100; + } + if ((byte & 4) != 0 && !APU.TimerEnabled [2]) + { + APU.Timer [2] = 0; + IAPU.RAM [0xff] = 0; + if ((APU.TimerTarget [2] = IAPU.RAM [0xfc]) == 0) + APU.TimerTarget [2] = 0x100; + } + APU.TimerEnabled [0] = byte & 1; + APU.TimerEnabled [1] = (byte & 2) >> 1; + APU.TimerEnabled [2] = (byte & 4) >> 2; + + if (byte & 0x10) + IAPU.RAM [0xF4] = IAPU.RAM [0xF5] = 0; + + if (byte & 0x20) + IAPU.RAM [0xF6] = IAPU.RAM [0xF7] = 0; + + if (byte & 0x80) + { + if (!APU.ShowROM) + { + memmove (&IAPU.RAM [0xffc0], APUROM, sizeof (APUROM)); + APU.ShowROM = TRUE; + } + } + else + { + if (APU.ShowROM) + { + APU.ShowROM = FALSE; + memmove (&IAPU.RAM [0xffc0], APU.ExtraRAM, sizeof (APUROM)); + } + } + IAPU.RAM [0xf1] = byte; +} + +void S9xSetAPUTimer (uint16 Address, uint8 byte) +{ + IAPU.RAM [Address] = byte; + + switch (Address) + { + case 0xfa: + if ((APU.TimerTarget [0] = IAPU.RAM [0xfa]) == 0) + APU.TimerTarget [0] = 0x100; + APU.TimerValueWritten [0] = TRUE; + break; + case 0xfb: + if ((APU.TimerTarget [1] = IAPU.RAM [0xfb]) == 0) + APU.TimerTarget [1] = 0x100; + APU.TimerValueWritten [1] = TRUE; + break; + case 0xfc: + if ((APU.TimerTarget [2] = IAPU.RAM [0xfc]) == 0) + APU.TimerTarget [2] = 0x100; + APU.TimerValueWritten [2] = TRUE; + break; + } +} + +uint8 S9xGetAPUDSP () +{ + uint8 reg = IAPU.RAM [0xf2] & 0x7f; + uint8 byte = APU.DSP [reg]; + + switch (reg) + { + case APU_KON: + break; + case APU_KOFF: + break; + case APU_OUTX + 0x00: + case APU_OUTX + 0x10: + case APU_OUTX + 0x20: + case APU_OUTX + 0x30: + case APU_OUTX + 0x40: + case APU_OUTX + 0x50: + case APU_OUTX + 0x60: + case APU_OUTX + 0x70: + if (SoundData.channels [reg >> 4].state == SOUND_SILENT) + return (0); + return ((SoundData.channels [reg >> 4].sample >> 8) | + (SoundData.channels [reg >> 4].sample & 0xff)); + + case APU_ENVX + 0x00: + case APU_ENVX + 0x10: + case APU_ENVX + 0x20: + case APU_ENVX + 0x30: + case APU_ENVX + 0x40: + case APU_ENVX + 0x50: + case APU_ENVX + 0x60: + case APU_ENVX + 0x70: + return 0; +// return ((uint8) S9xGetEnvelopeHeight (reg >> 4)); + + case APU_ENDX: +// To fix speech in Magical Drop 2 6/11/00 +// APU.DSP [APU_ENDX] = 0; + break; + default: + break; + } + return (byte); +} diff --git a/src/apu.h b/src/apu.h new file mode 100644 index 0000000..0f13bb2 --- /dev/null +++ b/src/apu.h @@ -0,0 +1,200 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _apu_h_ +#define _apu_h_ + +#include "spc700.h" + +/* +typedef union +{ + struct { uint8 A, Y; } B; + uint16 W; +} YAndA; +*/ + +struct SAPU +{ + int32 Cycles; // 0x00 + bool8 ShowROM; // 0x04 + uint8 Flags; // 0x05 + uint8 KeyedChannels; // 0x06 + uint8 OutPorts [4]; // 0x07 + uint8 DSP [0x80]; // 0x0B + uint8 ExtraRAM [64]; + uint16 Timer [3]; + uint16 TimerTarget [3]; + bool8 TimerEnabled [3]; + bool8 TimerValueWritten [3]; +}; + +struct SIAPU +{ + uint8 *DirectPage; // 0x00 + uint32 Address; // 0x04 c core only + uint8 *WaitAddress1; // 0x08 + uint8 *WaitAddress2; // 0x0C + uint32 WaitCounter; // 0x10 + uint8 *ShadowRAM; // 0x14 + uint8 *CachedSamples; // 0x18 + uint8 _Carry; // 0x1C c core only + uint8 _Overflow; // 0x1D c core only + uint8 Bit; // 0x1E c core only + uint8 pad0; + uint32 TimerErrorCounter; // 0x20 + uint32 Scanline; // 0x24 + int32 OneCycle; // 0x28 + int32 TwoCycles; // 0x2C + // notaz: reordered and moved everything here, for faster context load/save + uint32 *asmJumpTab; // 0x30 + uint8 *PC; // 0x34 + YAndA YA; // 0x38 0x0000YYAA + uint8 P; // 0x3C flags: NODBHIZC + uint8 pad1; + uint8 pad2; + uint8 _Zero; // 0x3F Z=0, when this!=0; also stores neg flag in &0x80 + uint8 X; // 0x40 + uint8 S; // 0x41 stack pointer, default: 0xff + uint16 pad3; + uint8 *RAM; // 0x44 + + uint8 *ExtraRAM; // 0x48 shortcut to APU.ExtraRAM +}; + + +EXTERN_C struct SAPU APU; +EXTERN_C struct SIAPU IAPU; + +STATIC inline void S9xAPUUnpackStatus() +{ + + IAPU._Zero =((IAPU.P & Zero) == 0) | (IAPU.P & Negative); + + if (!Settings.asmspc700) + { + IAPU._Carry = (IAPU.P & Carry); + IAPU._Overflow = (IAPU.P & Overflow); + } +} + +STATIC inline void S9xAPUPackStatus() +{ + if (Settings.asmspc700) + { + IAPU.P &= ~(Zero | Negative); + if(!IAPU._Zero) IAPU.P |= Zero; + if(IAPU._Zero & 0x80) IAPU.P |= Negative; + + } + else + { + IAPU.P &= ~(Zero | Negative | Carry | Overflow); + if(IAPU._Carry) IAPU.P |= Carry; + if(!IAPU._Zero) IAPU.P |= Zero; + if(IAPU._Overflow) IAPU.P |= Overflow; + if(IAPU._Zero & 0x80) IAPU.P |= Negative; + } +} + +START_EXTERN_C +void S9xResetAPU (void); +bool8 S9xInitAPU (); +void S9xDeinitAPU (); +void S9xDecacheSamples (); +int S9xTraceAPU (); +int S9xAPUOPrint (char *buffer, uint16 Address); +void S9xSetAPUControl (uint8 byte); +void S9xSetAPUDSP (uint8 byte); +uint8 S9xGetAPUDSP (); +void S9xSetAPUTimer (uint16 Address, uint8 byte); +void S9xOpenCloseSoundTracingFile (bool8); +void S9xPrintAPUState (); +extern int32 S9xAPUCycles [256]; // Scaled cycle lengths +extern int32 S9xAPUCycleLengths [256]; // Raw data. +extern void (*S9xApuOpcodes [256]) (void); +extern void (*S9xApuOpcodesReal [256]) (void); +END_EXTERN_C + + +#define APU_VOL_LEFT 0x00 +#define APU_VOL_RIGHT 0x01 +#define APU_P_LOW 0x02 +#define APU_P_HIGH 0x03 +#define APU_SRCN 0x04 +#define APU_ADSR1 0x05 +#define APU_ADSR2 0x06 +#define APU_GAIN 0x07 +#define APU_ENVX 0x08 +#define APU_OUTX 0x09 + +#define APU_MVOL_LEFT 0x0c +#define APU_MVOL_RIGHT 0x1c +#define APU_EVOL_LEFT 0x2c +#define APU_EVOL_RIGHT 0x3c +#define APU_KON 0x4c +#define APU_KOFF 0x5c +#define APU_FLG 0x6c +#define APU_ENDX 0x7c + +#define APU_EFB 0x0d +#define APU_PMON 0x2d +#define APU_NON 0x3d +#define APU_EON 0x4d +#define APU_DIR 0x5d +#define APU_ESA 0x6d +#define APU_EDL 0x7d + +#define APU_CX 0x0f +#define APU_C0 0x0f +#define APU_C1 0x1f +#define APU_C2 0x2f +#define APU_C3 0x3f +#define APU_C4 0x4f +#define APU_C5 0x5f +#define APU_C6 0x6f +#define APU_C7 0x7f + +#define APU_SOFT_RESET 0x80 +#define APU_MUTE 0x40 +#define APU_ECHO_DISABLED 0x20 + +#define FREQUENCY_MASK 0x3fff +#endif diff --git a/src/apuaux.cpp b/src/apuaux.cpp new file mode 100644 index 0000000..e10ac6e --- /dev/null +++ b/src/apuaux.cpp @@ -0,0 +1,32 @@ +#include "snes9x.h" +#include "spc700.h" +#include "apu.h" + +extern "C" { + +void S9xAPUSetByteFFtoF0 (uint8 val, uint32 Address) +{ + if (Address >= 0xf4 && Address <= 0xf7) + APU.OutPorts [Address - 0xf4] = val; + else + if (Address < 0xfd) + { + IAPU.RAM [Address] = val; + if (Address >= 0xfa) + { + if (val == 0) + APU.TimerTarget [Address - 0xfa] = 0x100; + else + APU.TimerTarget [Address - 0xfa] = val; + } + } +} + +void S9xAPUSetByteFFC0 (uint8 val, uint32 Address) +{ + APU.ExtraRAM [Address - 0xffc0] = val; + if (!APU.ShowROM) IAPU.RAM [Address] = val; +} + + +} diff --git a/src/apumem.h b/src/apumem.h new file mode 100644 index 0000000..5288941 --- /dev/null +++ b/src/apumem.h @@ -0,0 +1,151 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#ifndef _apumemory_h_ +#define _apumemory_h_ + +START_EXTERN_C +extern uint8 W4; +extern uint8 APUROM[64]; +END_EXTERN_C + +INLINE uint8 S9xAPUGetByteZ (uint8 Address) +{ + if (Address >= 0xf0 && IAPU.DirectPage == IAPU.RAM) + { + if (Address >= 0xfd) { + uint8 t = IAPU.RAM [Address]; + IAPU.RAM [Address] = 0; + return (t); + } else if (Address == 0xf3) return (S9xGetAPUDSP ()); + + return (IAPU.RAM [Address]); + } + else + return (IAPU.DirectPage [Address]); +} + +INLINE void S9xAPUSetByteZ (uint8 val, uint8 Address) +{ + if (Address >= 0xf0 && IAPU.DirectPage == IAPU.RAM) + { + if (Address == 0xf3) + S9xSetAPUDSP (val); + else + if (Address >= 0xf4 && Address <= 0xf7) + APU.OutPorts [Address - 0xf4] = val; + else + if (Address == 0xf1) + S9xSetAPUControl (val); + else + if (Address < 0xfd) + { + IAPU.RAM [Address] = val; + if (Address >= 0xfa) + { + if (val == 0) + APU.TimerTarget [Address - 0xfa] = 0x100; + else + APU.TimerTarget [Address - 0xfa] = val; + } + } + } + else + IAPU.DirectPage [Address] = val; +} + +INLINE uint8 S9xAPUGetByte (uint32 Address) +{ + Address &= 0xffff; + + if (Address <= 0xff && Address >= 0xf3) + { + if (Address == 0xf3) return (S9xGetAPUDSP ()); + if (Address >= 0xfd) { + uint8 t = IAPU.RAM [Address]; + IAPU.RAM [Address] = 0; + return (t); + } + return (IAPU.RAM [Address]); + } + return (IAPU.RAM [Address]); +} + +INLINE void S9xAPUSetByte (uint8 val, uint32 Address) +{ + Address &= 0xffff; + + if (Address <= 0xff && Address >= 0xf0) + { + if (Address == 0xf3) + S9xSetAPUDSP (val); + else + if (Address >= 0xf4 && Address <= 0xf7) + APU.OutPorts [Address - 0xf4] = val; + else + if (Address == 0xf1) + S9xSetAPUControl (val); + else + if (Address < 0xfd) + { + IAPU.RAM [Address] = val; + if (Address >= 0xfa) + { + if (val == 0) + APU.TimerTarget [Address - 0xfa] = 0x100; + else + APU.TimerTarget [Address - 0xfa] = val; + } + } + } + else + { + if (Address < 0xffc0) + IAPU.RAM [Address] = val; + else + { + APU.ExtraRAM [Address - 0xffc0] = val; + if (!APU.ShowROM) + IAPU.RAM [Address] = val; + } + } +} +#endif diff --git a/src/asm_util.S b/src/asm_util.S new file mode 100644 index 0000000..cc9a887 --- /dev/null +++ b/src/asm_util.S @@ -0,0 +1,85 @@ +.global invalidate_cache_region +.global invoke_kernel_custom_code +.global invalidate_icache_all +.global invalidate_dcache_all + +.equ CACHE_SIZE, (16 * 1024) +.equ CACHE_LINE_SIZE, 32 +.equ CACHE_LINES, (CACHE_SIZE / CACHE_LINE_SIZE) +.equ CACHE_WAYS, 4 + +#define nop16b() \ + nop; \ + nop; \ + nop; \ + nop \ + +#define nop64b() \ + nop16b(); \ + nop16b(); \ + nop16b(); \ + nop16b() \ + +#define nop256b() \ + nop64b(); \ + nop64b(); \ + nop64b(); \ + nop64b() \ + +#define nop1kb() \ + nop256b(); \ + nop256b(); \ + nop256b(); \ + nop256b() \ + +#define nop4kb() \ + nop1kb(); \ + nop1kb(); \ + nop1kb(); \ + nop1kb() \ + +#define nop16kb() \ + nop4kb(); \ + nop4kb(); \ + nop4kb(); \ + nop4kb() \ + +invalidate_cache_region: + mov r2, #0x0 + swi 0x9f0002 + + bx lr + +invoke_kernel_custom_code: + swi 0x90007a + + bx lr + + +invalidate_dcache_all: + ldr r0, dcache_buffer + mov r1, #(CACHE_SIZE / 2) + +1: + ldr r2, [r0], #4 + subs r1, r1, #1 + bne 1b + + bx lr + +dcache_buffer: + .word _dcache_buffer + +.balign 16384 + +invalidate_icache_all: + nop16kb() + bx lr + + +.section bss + +.balign 32768 + +.comm _dcache_buffer (CACHE_SIZE * 2) + diff --git a/src/asmmemfuncs.h b/src/asmmemfuncs.h new file mode 100644 index 0000000..d6f508c --- /dev/null +++ b/src/asmmemfuncs.h @@ -0,0 +1,206 @@ +#ifndef _ASMMEMFUNCS_H_ +#define _ASMMEMFUNCS_H_ + +#define memset32(_dst, _c, _count) \ +({ uint32_t *dst = (_dst); uint32_t c = (_c); int count = (_count); uint32_t dummy0, dummy1, dummy2; \ + __asm__ __volatile__ ( \ + " cmp %[count], #4\n" \ + " blt 2f\n" \ + " mov %[dummy0], %[c]\n" \ + " tst %[dst], #4\n" \ + " strne %[c], [%[dst]], #4\n" \ + " subne %[count], %[count], #1\n" \ + " tst %[dst], #8\n" \ + " stmneia %[dst]!, {%[dummy0], %[c]}\n" \ + " subne %[count], %[count], #2\n" \ + " mov %[dummy1], %[c]\n" \ + " mov %[dummy2], %[c]\n" \ + "1:\n"\ + " subs %[count], %[count], #4\n" \ + " stmgeia %[dst]!, {%[dummy0], %[dummy1], %[dummy2], %[c]}\n" \ + " bge 1b\n" \ + " add %[count], %[count], #4\n" \ + "2:\n"\ + " subs %[count], %[count], #1\n" \ + " strge %[c], [%[dst]], #4\n" \ + " subs %[count], %[count], #1\n" \ + " strge %[c], [%[dst]], #4\n" \ + " subs %[count], %[count], #1\n" \ + " strge %[c], [%[dst]], #4\n" \ + "\n" \ + : [dst] "+&r" (dst), [count] "+&r" (count), [dummy0] "=&r" (dummy0), [dummy1] "=&r" (dummy1), [dummy2] "=&r" (dummy2), [c] "+&r" (c) \ + : \ + : "cc", "memory" \ + ); _dst; \ +}) + +#define memset16(_dst, _c, _count) \ +({ uint16_t *dst = (_dst); uint16_t c = (_c); int count = (_count); uint32_t dummy0, dummy1, dummy2; \ + __asm__ __volatile__ ( \ + " cmp %[count], #2\n" \ + " blt 3f\n" \ + /* Alignment is known to be at least 16-bit */ \ + " tst %[dst], #2\n" \ + " strneh %[c], [%[dst]], #2\n" \ + " subne %[count], %[count], #1\n" \ + /* Now we are 32-bit aligned (need to upgrade 'c' to 32-bit )*/ \ + " orr %[c], %[c], %[c], asl #16\n" \ + " mov %[dummy0], %[c]\n" \ + " cmp %[count], #8\n" \ + " blt 2f\n" \ + " tst %[dst], #4\n" \ + " strne %[c], [%[dst]], #4\n" \ + " subne %[count], %[count], #2\n" \ + " tst %[dst], #8\n" \ + " stmneia %[dst]!, {%[dummy0], %[c]}\n" \ + " subne %[count], %[count], #4\n" \ + /* Now we are 128-bit aligned */ \ + " mov %[dummy1], %[c]\n" \ + " mov %[dummy2], %[c]\n" \ + "1:\n" /* Copy 4 32-bit values per loop iteration */ \ + " subs %[count], %[count], #8\n" \ + " stmgeia %[dst]!, {%[dummy0], %[dummy1], %[dummy2], %[c]}\n" \ + " bge 1b\n" \ + " add %[count], %[count], #8\n" \ + "2:\n" /* Copy up to 3 remaining 32-bit values */ \ + " tst %[count], #4\n" \ + " stmneia %[dst]!, {%[dummy0], %[c]}\n" \ + " tst %[count], #2\n" \ + " strne %[c], [%[dst]], #4\n" \ + " and %[count], %[count], #1\n" \ + "3:\n" /* Copy up to 1 remaining 16-bit value */ \ + " subs %[count], %[count], #1\n" \ + " strgeh %[c], [%[dst]], #2\n" \ + "\n" \ + : [dst] "+&r" (dst), [count] "+&r" (count), [dummy0] "=&r" (dummy0), [dummy1] "=&r" (dummy1), [dummy2] "=&r" (dummy2), [c] "+&r" (c) \ + : \ + : "cc", "memory" \ + ); _dst;\ +}) + +#define memcpy32(_dst, _src, _count) \ +({ uint32_t *dst = (_dst); uint32_t *src = (_src); int count = (_count); \ + __asm__ __volatile__ ( \ + " cmp %[count], #4\n" \ + " blt 2f\n" \ + " tst %[dst], #4\n" \ + " ldrne r4, [%[src]], #4\n" \ + " strne r4, [%[dst]], #4\n" \ + " subne %[count], %[count], #1\n" \ + " tst %[dst], #8\n" \ + " ldmneia %[src]!, {r4-r5}\n" \ + " stmneia %[dst]!, {r4-r5}\n" \ + " subne %[count], %[count], #2\n" \ + "1:\n" \ + " subs %[count], %[count], #4\n" \ + " ldmgeia %[src]!, {r4-r7}\n" \ + " stmgeia %[dst]!, {r4-r7}\n" \ + " bge 1b\n" \ + " add %[count], %[count], #4\n" \ + "2:\n" \ + " tst %[count], #2\n" \ + " ldmneia %[src]!, {r4-r5}\n" \ + " stmneia %[dst]!, {r4-r5}\n" \ + " tst %[count], #1\n" \ + " ldrne r4, [%[src]], #4\n" \ + " strne r4, [%[dst]], #4\n" \ + "\n" \ + : [dst] "+&r" (dst), [src] "+&r" (src), [count] "+&r" (count) \ + : \ + : "r4", "r5", "r6", "r7", "cc", "memory" \ + ); _dst; \ +}) + +#define memcpy16(_dst, _src, _count) \ +({ uint16_t *dst = (_dst); uint16_t *src = (_src); int count = (_count); uint32_t dummy0; \ + __asm__ __volatile__ ( \ + " cmp %[count], #2\n" \ + " blt 6f\n" \ + /* Alignment is known to be at least 16-bit */ \ + " tst %[dst], #2\n" \ + " ldrneh r4, [%[src]], #2\n" \ + " strneh r4, [%[dst]], #2\n" \ + " subne %[count], %[count], #1\n" \ + /* Now destination address is 32-bit aligned, still need to check whether */ \ + /* source is 32-bit aligned or not */ \ + " tst %[src], #2\n" \ + " bne 3f\n" \ + /* Both destination and source are 32-bit aligned */ \ + " cmp %[count], #8\n" \ + " blt 2f\n" \ + " tst %[dst], #4\n" \ + " ldrne r4, [%[src]], #4\n" \ + " strne r4, [%[dst]], #4\n" \ + " subne %[count], %[count], #2\n" \ + " tst %[dst], #8\n" \ + " ldmneia %[src]!, {r4-r5}\n" \ + " stmneia %[dst]!, {r4-r5}\n" \ + " subne %[count], %[count], #4\n" \ + /* Destination address is 128-bit aligned, source address is 32-bit aligned */ \ + "1: subs %[count], %[count], #8\n" \ + " ldmgeia %[src]!, {r4-r7}\n" \ + " stmgeia %[dst]!, {r4-r7}\n" \ + " bge 1b\n" \ + " add %[count], %[count], #8\n" \ + /* Copy up to 3 remaining aligned 32-bit values */ \ + "2: tst %[count], #4\n" \ + " ldmneia %[src]!, {r4-r5}\n" \ + " stmneia %[dst]!, {r4-r5}\n" \ + " tst %[count], #2\n" \ + " ldrne r4, [%[src]], #4\n" \ + " strne r4, [%[dst]], #4\n" \ + " and %[count], %[count], #1\n" \ + " b 6f\n" \ + /* Destination is 32-bit aligned, but source is only 16-bit aligned */ \ + "3: cmp %[count], #8\n" \ + " blt 5f\n" \ + " tst %[dst], #4\n" \ + " ldrneh r4, [%[src]], #2\n" \ + " ldrneh r5, [%[src]], #2\n" \ + " orrne r4, r4, r5, asl #16\n" \ + " strne r4, [%[dst]], #4\n" \ + " subne %[count], %[count], #2\n" \ + " tst %[dst], #8\n" \ + " ldrneh r4, [%[src]], #2\n" \ + " ldrne r5, [%[src]], #4\n" \ + " ldrneh r6, [%[src]], #2\n" \ + " orrne r4, r4, r5, asl #16\n" \ + " movne r5, r5, lsr #16\n" \ + " orrne r5, r5, r6, asl #16\n" \ + " stmneia %[dst]!, {r4-r5}\n" \ + " subne %[count], %[count], #4\n" \ + /* Destination is 128-bit aligned, but source is only 16-bit aligned */ \ + "4: subs %[count], %[count], #8\n" \ + " ldrgeh r4, [%[src]], #2\n" \ + " ldmgeia %[src]!, {r5-r7}\n" \ + " ldrgeh %[dummy0], [%[src]], #2\n" \ + " orrge r4, r4, r5, asl #16\n" \ + " movge r5, r5, lsr #16\n" \ + " orrge r5, r5, r6, asl #16\n" \ + " movge r6, r6, lsr #16\n" \ + " orrge r6, r6, r7, asl #16\n" \ + " movge r7, r7, lsr #16\n" \ + " orrge r7, r7, %[dummy0], asl #16\n" \ + " stmgeia %[dst]!, {r4-r7}\n" \ + " bge 4b\n" \ + " add %[count], %[count], #8\n" \ + /* Copy up to 6 remaining 16-bit values (to 32-bit aligned destination) */ \ + "5: subs %[count], %[count], #2\n" \ + " ldrgeh r4, [%[src]], #2\n" \ + " ldrgeh r5, [%[src]], #2\n" \ + " orrge r4, r4, r5, asl #16\n" \ + " strge r4, [%[dst]], #4\n" \ + " bge 5b\n" \ + " add %[count], %[count], #2\n" \ + /* Copy the last remaining 16-bit value if any */ \ + "6: subs %[count], %[count], #1\n" \ + " ldrgeh r4, [%[src]], #2\n" \ + " strgeh r4, [%[dst]], #2\n" \ + "\n" \ + : [dst] "+&r" (dst), [src] "+&r" (src), [count] "+&r" (count), [dummy0] "=&r" (dummy0) \ + : \ + : "r4", "r5", "r6", "r7", "cc", "memory" \ + ); _dst; \ +}) + +#endif diff --git a/src/asmout.sh b/src/asmout.sh new file mode 100644 index 0000000..f8603ed --- /dev/null +++ b/src/asmout.sh @@ -0,0 +1,37 @@ +#!/bin/bash + +if [ "$2" == "caanoo" ]; then + echo Using Caanoo toolkit + ARCH="arm-gph-linux-gnueabi" + SDK="/opt/caanoo_sdk/tools/gcc-4.2.4-glibc-2.7-eabi/" + MACHINE="caanoo" +else + echo Using Wiz toolkit + ARCH="arm-open2x-linux" + SDK="/opt/open2x/gcc-4.1.1-glibc-2.3.6/" + MACHINE="wiz" +fi + +GCC="$SDK/bin/$ARCH-gcc" + +COPT="-mcpu=arm926ej-s -mtune=arm926ej-s -g -D__WIZ__" +COPT="$COPT -DASMCPU -DARM" +COPT="$COPT -Os" +COPT="$COPT -ffast-math -msoft-float" +COPT="$COPT -finline -finline-functions -fexpensive-optimizations" +COPT="$COPT -falign-functions=32 -falign-loops -falign-labels -falign-jumps" +COPT="$COPT -fomit-frame-pointer" +COPT="$COPT -fno-common -fno-builtin -fstrict-aliasing -mstructure-size-boundary=32" +#COPT="$COPT -O3" +#COPT="$COPT -ffast-math -msoft-float" +#COPT="$COPT -finline-functions" +#COPT="$COPT -finline -fexpensive-optimizations" +#COPT="$COPT -falign-functions=32 -falign-loops -falign-labels -falign-jumps" +#COPT="$COPT -fomit-frame-pointer" +COPT="$COPT -I$SDK/include" +COPT="$COPT -L$SDK/lib" + + +# -c -g -Wa,-a,-ad +$GCC -c -Wa,-ahl=$1.commented.$MACHINE.s $1.cpp $COPT +$GCC -S -c -o $1.generated.$MACHINE.s $1.cpp $COPT diff --git a/src/bsd_mem.h b/src/bsd_mem.h new file mode 100644 index 0000000..66f25d3 --- /dev/null +++ b/src/bsd_mem.h @@ -0,0 +1,2 @@ +extern "C" void *bsd_memmove(void *destination, const void *source, size_t num ); + diff --git a/src/c4.cpp b/src/c4.cpp new file mode 100644 index 0000000..511e414 --- /dev/null +++ b/src/c4.cpp @@ -0,0 +1,432 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2003 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2002 - 2003 Matthew Kendora and + Brad Jorsch (anomie@users.sourceforge.net) + + + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and + Nach (n-a-c-h@users.sourceforge.net) + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2003 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman (jweidman@slip.net), + neviksti (neviksti@hotmail.com), and + Kris Bleakley (stinkfish@bigpond.com) + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2003 zsKnight, pagefault (pagefault@zsnes.com) + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar and Gary Henderson. + + + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ + +#ifndef __GP32__ +#include +#endif + +#include +#include "c4.h" +#include "bsd_mem.h" +//#include "memmap.h" + +extern "C" { + +short C4WFXVal; +short C4WFYVal; +short C4WFZVal; +short C4WFX2Val; +short C4WFY2Val; +short C4WFDist; +short C4WFScale; + +static long tanval; +static long c4x, c4y, c4z; +static long c4x2, c4y2, c4z2; + +const short C4_MulTable[256] = { + 0x0000, 0x0003, 0x0006, 0x0009, 0x000c, 0x000f, 0x0012, 0x0015, + 0x0019, 0x001c, 0x001f, 0x0022, 0x0025, 0x0028, 0x002b, 0x002f, + 0x0032, 0x0035, 0x0038, 0x003b, 0x003e, 0x0041, 0x0045, 0x0048, + 0x004b, 0x004e, 0x0051, 0x0054, 0x0057, 0x005b, 0x005e, 0x0061, + 0x0064, 0x0067, 0x006a, 0x006d, 0x0071, 0x0074, 0x0077, 0x007a, + 0x007d, 0x0080, 0x0083, 0x0087, 0x008a, 0x008d, 0x0090, 0x0093, + 0x0096, 0x0099, 0x009d, 0x00a0, 0x00a3, 0x00a6, 0x00a9, 0x00ac, + 0x00af, 0x00b3, 0x00b6, 0x00b9, 0x00bc, 0x00bf, 0x00c2, 0x00c5, + 0x00c9, 0x00cc, 0x00cf, 0x00d2, 0x00d5, 0x00d8, 0x00db, 0x00df, + 0x00e2, 0x00e5, 0x00e8, 0x00eb, 0x00ee, 0x00f1, 0x00f5, 0x00f8, + 0x00fb, 0x00fe, 0x0101, 0x0104, 0x0107, 0x010b, 0x010e, 0x0111, + 0x0114, 0x0117, 0x011a, 0x011d, 0x0121, 0x0124, 0x0127, 0x012a, + 0x012d, 0x0130, 0x0133, 0x0137, 0x013a, 0x013d, 0x0140, 0x0143, + 0x0146, 0x0149, 0x014d, 0x0150, 0x0153, 0x0156, 0x0159, 0x015c, + 0x015f, 0x0163, 0x0166, 0x0169, 0x016c, 0x016f, 0x0172, 0x0175, + 0x0178, 0x017c, 0x017f, 0x0182, 0x0185, 0x0188, 0x018b, 0x018e, + 0x0192, 0x0195, 0x0198, 0x019b, 0x019e, 0x01a1, 0x01a4, 0x01a8, + 0x01ab, 0x01ae, 0x01b1, 0x01b4, 0x01b7, 0x01ba, 0x01be, 0x01c1, + 0x01c4, 0x01c7, 0x01ca, 0x01cd, 0x01d0, 0x01d4, 0x01d7, 0x01da, + 0x01dd, 0x01e0, 0x01e3, 0x01e6, 0x01ea, 0x01ed, 0x01f0, 0x01f3, + 0x01f6, 0x01f9, 0x01fc, 0x0200, 0x0203, 0x0206, 0x0209, 0x020c, + 0x020f, 0x0212, 0x0216, 0x0219, 0x021c, 0x021f, 0x0222, 0x0225, + 0x0228, 0x022c, 0x022f, 0x0232, 0x0235, 0x0238, 0x023b, 0x023e, + 0x0242, 0x0245, 0x0248, 0x024b, 0x024e, 0x0251, 0x0254, 0x0258, + 0x025b, 0x025e, 0x0261, 0x0264, 0x0267, 0x026a, 0x026e, 0x0271, + 0x0274, 0x0277, 0x027a, 0x027d, 0x0280, 0x0284, 0x0287, 0x028a, + 0x028d, 0x0290, 0x0293, 0x0296, 0x029a, 0x029d, 0x02a0, 0x02a3, + 0x02a6, 0x02a9, 0x02ac, 0x02b0, 0x02b3, 0x02b6, 0x02b9, 0x02bc, + 0x02bf, 0x02c2, 0x02c6, 0x02c9, 0x02cc, 0x02cf, 0x02d2, 0x02d5, + 0x02d8, 0x02db, 0x02df, 0x02e2, 0x02e5, 0x02e8, 0x02eb, 0x02ee, + 0x02f1, 0x02f5, 0x02f8, 0x02fb, 0x02fe, 0x0301, 0x0304, 0x0307, + 0x030b, 0x030e, 0x0311, 0x0314, 0x0317, 0x031a, 0x031d, 0x0321}; + +const short C4_SinTable[256] = { + 0x0000, 0x0324, 0x0647, 0x096a, 0x0c8b, 0x0fab, 0x12c8, 0x15e2, + 0x18f8, 0x1c0b, 0x1f19, 0x2223, 0x2528, 0x2826, 0x2b1f, 0x2e11, + 0x30fb, 0x33de, 0x36ba, 0x398c, 0x3c56, 0x3f17, 0x41ce, 0x447a, + 0x471c, 0x49b4, 0x4c3f, 0x4ebf, 0x5133, 0x539b, 0x55f5, 0x5842, + 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e8, 0x66cf, 0x68a6, + 0x6a6d, 0x6c24, 0x6dca, 0x6f5f, 0x70e2, 0x7255, 0x73b5, 0x7504, + 0x7641, 0x776c, 0x7884, 0x798a, 0x7a7d, 0x7b5d, 0x7c29, 0x7ce3, + 0x7d8a, 0x7e1d, 0x7e9d, 0x7f09, 0x7f62, 0x7fa7, 0x7fd8, 0x7ff6, + 0x7fff, 0x7ff6, 0x7fd8, 0x7fa7, 0x7f62, 0x7f09, 0x7e9d, 0x7e1d, + 0x7d8a, 0x7ce3, 0x7c29, 0x7b5d, 0x7a7d, 0x798a, 0x7884, 0x776c, + 0x7641, 0x7504, 0x73b5, 0x7255, 0x70e2, 0x6f5f, 0x6dca, 0x6c24, + 0x6a6d, 0x68a6, 0x66cf, 0x64e8, 0x62f2, 0x60ec, 0x5ed7, 0x5cb4, + 0x5a82, 0x5842, 0x55f5, 0x539b, 0x5133, 0x4ebf, 0x4c3f, 0x49b4, + 0x471c, 0x447a, 0x41ce, 0x3f17, 0x3c56, 0x398c, 0x36ba, 0x33de, + 0x30fb, 0x2e11, 0x2b1f, 0x2826, 0x2528, 0x2223, 0x1f19, 0x1c0b, + 0x18f8, 0x15e2, 0x12c8, 0x0fab, 0x0c8b, 0x096a, 0x0647, 0x0324, + -0x0000, -0x0324, -0x0647, -0x096a, -0x0c8b, -0x0fab, -0x12c8, -0x15e2, + -0x18f8, -0x1c0b, -0x1f19, -0x2223, -0x2528, -0x2826, -0x2b1f, -0x2e11, + -0x30fb, -0x33de, -0x36ba, -0x398c, -0x3c56, -0x3f17, -0x41ce, -0x447a, + -0x471c, -0x49b4, -0x4c3f, -0x4ebf, -0x5133, -0x539b, -0x55f5, -0x5842, + -0x5a82, -0x5cb4, -0x5ed7, -0x60ec, -0x62f2, -0x64e8, -0x66cf, -0x68a6, + -0x6a6d, -0x6c24, -0x6dca, -0x6f5f, -0x70e2, -0x7255, -0x73b5, -0x7504, + -0x7641, -0x776c, -0x7884, -0x798a, -0x7a7d, -0x7b5d, -0x7c29, -0x7ce3, + -0x7d8a, -0x7e1d, -0x7e9d, -0x7f09, -0x7f62, -0x7fa7, -0x7fd8, -0x7ff6, + -0x7fff, -0x7ff6, -0x7fd8, -0x7fa7, -0x7f62, -0x7f09, -0x7e9d, -0x7e1d, + -0x7d8a, -0x7ce3, -0x7c29, -0x7b5d, -0x7a7d, -0x798a, -0x7884, -0x776c, + -0x7641, -0x7504, -0x73b5, -0x7255, -0x70e2, -0x6f5f, -0x6dca, -0x6c24, + -0x6a6d, -0x68a6, -0x66cf, -0x64e8, -0x62f2, -0x60ec, -0x5ed7, -0x5cb4, + -0x5a82, -0x5842, -0x55f5, -0x539b, -0x5133, -0x4ebf, -0x4c3f, -0x49b4, + -0x471c, -0x447a, -0x41ce, -0x3f17, -0x3c56, -0x398c, -0x36ba, -0x33de, + -0x30fb, -0x2e11, -0x2b1f, -0x2826, -0x2528, -0x2223, -0x1f19, -0x1c0b, + -0x18f8, -0x15e2, -0x12c8, -0x0fab, -0x0c8b, -0x096a, -0x0647, -0x0324}; + +short C4_Sin(short Angle) +{ + if (Angle < 0) { + if (Angle == -32768) return 0; + return -C4_Sin(-Angle); + } + int S = C4_SinTable[Angle >> 8] + (C4_MulTable[Angle & 0xff] * C4_SinTable[0x40 + (Angle >> 8)] >> 15); + if (S > 32767) S = 32767; + return (short) S; +} + +short C4_Cos(short Angle) +{ + if (Angle < 0) { + if (Angle == -32768) return -32768; + Angle = -Angle; + } + int S = C4_SinTable[0x40 + (Angle >> 8)] - (C4_MulTable[Angle & 0xff] * C4_SinTable[Angle >> 8] >> 15); + if (S < -32768) S = -32767; + return (short) S; +} +const short atantbl[] = { 0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 14, 15, 15, 16, 16, 17, 18, 18, 19, 20, 20, 21, 21, 22, 23, 23, 24, 25, 25, 26, 26, 27, 28, 28, 29, 29, 30, 31, 31, 32, 33, 33, 34, 34, 35, 36, 36, 37, 37, 38, 39, 39, 40, 40, 41, 42, 42, 43, 43, 44, 44, 45, 46, 46, 47, 47, 48, 49, 49, 50, 50, 51, 51, 52, 53, 53, 54, 54, 55, 55, 56, 57, 57, 58, 58, 59, 59, 60, 60, 61, 62, 62, 63, 63, 64, 64, 65, 65, 66, 66, 67, 67, 68, 69, 69, 70, 70, 71, 71, 72, 72, 73, 73, 74, 74, 75, 75, 76, 76, 77, 77, 78, 78, 79, 79, 80, 80, 81, 81, 82, 82, 83, 83, 84, 84, 85, 85, 86, 86, 86, 87, 87, 88, 88, 89, 89, 90, 90, 91, 91, 92, 92, 92, 93, 93, 94, 94, 95, 95, 96, 96, 96, 97, 97, 98, 98, 99, 99, 99, 100, 100, 101, 101, 101, 102, 102, 103, 103, 104, 104, 104, 105, 105, 106, 106, 106, 107, 107, 108, 108, 108, 109, 109, 109, 110, 110, 111, 111, 111, 112, 112, 113, 113, 113, 114, 114, 114, 115, 115, 115, 116, 116, 117, 117, 117, 118, 118, 118, 119, 119, 119, 120, 120, 120, 121, 121, 121, 122, 122, 122, 123, 123, 123, 124, 124, 124, 125, 125, 125, 126, 126, 126, 127, 127 }; + +short _abs (short val) +{ + return ((val >= 0) ? val : -val); +} + +short _atan2 (short x, short y) +{ + int x1,y1; + x1 = _abs (x); + y1 = _abs (y); + + if (x == 0) return 0; + + if ( ((x >= 0) && (y >= 0)) || ( (x < 0) && (y < 0)) ) { + if (x1 > y1) { + return atantbl[(unsigned char)((y1 << 8) / x1)]; + } else { + return atantbl[(unsigned char)((x1 << 8) / y1)]; + } + } else { + if (x1 > y1) { + return -atantbl[(unsigned char)((y1 << 8) / x1)]; + } else { + return -atantbl[(unsigned char)((x1 << 8) / y1)]; + } + } +} + +/*long _isqrt(long x) +{ + long s, t; + + if (x <= 0) return 0; + + s = 1; t = x; + while (s < t) { s <<= 1; t >>= 1; } + do { + t = s; + s = (x / s + s) >> 1; + } while (s < t); + + return t; +} +*/ + +static unsigned int _isqrt (unsigned long val) +{ + unsigned int temp, g=0; + + if (val >= 0x40000000) { + g = 0x8000; + val -= 0x40000000; + } + + #define INNER_ISQRT(s) \ + temp = (g << (s)) + (1 << ((s) * 2 - 2)); \ + if (val >= temp) { \ + g += 1 << ((s)-1); \ + val -= temp; \ + } + + INNER_ISQRT (15) + INNER_ISQRT (14) + INNER_ISQRT (13) + INNER_ISQRT (12) + INNER_ISQRT (11) + INNER_ISQRT (10) + INNER_ISQRT ( 9) + INNER_ISQRT ( 8) + INNER_ISQRT ( 7) + INNER_ISQRT ( 6) + INNER_ISQRT ( 5) + INNER_ISQRT ( 4) + INNER_ISQRT ( 3) + INNER_ISQRT ( 2) + + #undef INNER_ISQRT + + temp = g+g+1; + if (val >= temp) g++; + return g; +} + +void C4TransfWireFrame () +{ + c4x = C4WFXVal; + c4y = C4WFYVal; + c4z = C4WFZVal - 0x95; + + // Rotate X + tanval = -C4WFX2Val << 9; + c4y2 = (c4y * C4_Cos(tanval) - c4z * C4_Sin(tanval)) >> 15; + c4z2 = (c4y * C4_Sin(tanval) + c4z * C4_Cos(tanval)) >> 15; + + // Rotate Y + tanval = -C4WFY2Val << 9; + c4x2 = (c4x * C4_Cos(tanval) + c4z2 * C4_Sin(tanval)) >> 15; + c4z = (c4x * -C4_Sin(tanval) + c4z2 * C4_Cos(tanval)) >> 15; + + // Rotate Z + tanval = -C4WFDist << 9; + c4x = (c4x2 * C4_Cos(tanval) - c4y2 * C4_Sin(tanval)) >> 15; + c4y = (c4x2 * C4_Sin(tanval) + c4y2 * C4_Cos(tanval)) >> 15; + + // Scale + C4WFXVal = (short)(((long)c4x*C4WFScale*0x95)/(0x90*(c4z+0x95))); + C4WFYVal = (short)(((long)c4y*C4WFScale*0x95)/(0x90*(c4z+0x95))); + +} + +void C4TransfWireFrame2 () +{ + c4x = C4WFXVal; + c4y = C4WFYVal; + c4z = C4WFZVal; + + // Rotate X + tanval = -C4WFX2Val << 9; + c4y2 = (c4y * C4_Cos(tanval) - c4z * C4_Sin(tanval)) >> 15; + c4z2 = (c4y * C4_Sin(tanval) + c4z * C4_Cos(tanval)) >> 15; + + // Rotate Y + tanval = -C4WFY2Val << 9; + c4x2 = (c4x * C4_Cos(tanval) + c4z2 * C4_Sin(tanval)) >> 15; + c4z = (c4x * -C4_Sin(tanval) + c4z2 * C4_Cos(tanval)) >> 15; + + // Rotate Z + tanval = -C4WFDist << 9; + c4x = (c4x2 * C4_Cos(tanval) - c4y2 * C4_Sin(tanval)) >> 15; + c4y = (c4x2 * C4_Sin(tanval) + c4y2 * C4_Cos(tanval)) >> 15; + + // Scale + C4WFXVal =(short)(((long)c4x * C4WFScale) / 0x100); + C4WFYVal =(short)(((long)c4y * C4WFScale) / 0x100); + +} + +void C4CalcWireFrame () +{ + C4WFXVal = C4WFX2Val - C4WFXVal; + C4WFYVal = C4WFY2Val - C4WFYVal; + if (_abs (C4WFXVal) > _abs (C4WFYVal)) + { + C4WFDist = _abs (C4WFXVal) + 1; + C4WFYVal = (short) ( ((long)C4WFYVal << 8) / _abs (C4WFXVal) ); + if (C4WFXVal < 0) + C4WFXVal = -256; + else + C4WFXVal = 256; + } + else + { + if (C4WFYVal != 0) + { + C4WFDist = _abs(C4WFYVal)+1; + C4WFXVal = (short) ( ((long)C4WFXVal << 8) / _abs (C4WFYVal) ); + if (C4WFYVal < 0) + C4WFYVal = -256; + else + C4WFYVal = 256; + } + else + C4WFDist = 0; + } +} + +short C41FXVal; +short C41FYVal; +short C41FAngleRes; +short C41FDist; +short C41FDistVal; + +void C4Op1F () +{ + if (C41FXVal == 0) + { + if (C41FYVal > 0) + C41FAngleRes = 0x80; + else + C41FAngleRes = 0x180; + } + else + { + C41FAngleRes = (short)(_atan2(C41FYVal, C41FXVal) / 2); + C41FAngleRes = C41FAngleRes; + if (C41FXVal< 0) + C41FAngleRes += 0x100; + C41FAngleRes &= 0x1FF; + } +/* + if (C41FXVal == 0) + { + if (C41FYVal > 0) + C41FAngleRes = 0x80; + else + C41FAngleRes = 0x180; + } + else + { + tanval = (double) C41FYVal / C41FXVal; + C41FAngleRes = (short) (atan (tanval) / (3.141592675 * 2) * 512); + C41FAngleRes = C41FAngleRes; + if (C41FXVal< 0) + C41FAngleRes += 0x100; + C41FAngleRes &= 0x1FF; + } +*/ +} + +void C4Op15() +{ + tanval = (short)_isqrt ((long) C41FYVal * C41FYVal + (long) C41FXVal * C41FXVal); + C41FDist = tanval; +/* + tanval = sqrt ((double) C41FYVal * C41FYVal + (double) C41FXVal * C41FXVal); + C41FDist = (short) tanval; +*/ +} + +void C4Op0D() +{ + tanval = (short)_isqrt ((long) C41FYVal * C41FYVal + (long) C41FXVal * C41FXVal); + tanval = C41FDistVal / tanval; + C41FYVal = (short) (((long)C41FYVal * tanval * 99) / 100); + C41FXVal = (short) (((long)C41FXVal * tanval * 98) / 100); +/* + tanval = sqrt ((double) C41FYVal * C41FYVal + (double) C41FXVal * C41FXVal); + tanval = C41FDistVal / tanval; + C41FYVal = (short) (C41FYVal * tanval * 0.99); + C41FXVal = (short) (C41FXVal * tanval * 0.98); +*/ +} + +#ifdef ZSNES_C4 +void C4LoaDMem(char *C4RAM) +{ + bsd_memmove(C4RAM+(READ_WORD(C4RAM+0x1f45)&0x1fff), + C4GetMemPointer(READ_3WORD(C4RAM+0x1f40)), + READ_WORD(C4RAM+0x1f43)); +} +#endif +}//end extern C + diff --git a/src/c4.h b/src/c4.h new file mode 100644 index 0000000..9efe17d --- /dev/null +++ b/src/c4.h @@ -0,0 +1,114 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2003 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2002 - 2003 Matthew Kendora and + Brad Jorsch (anomie@users.sourceforge.net) + + + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and + Nach (n-a-c-h@users.sourceforge.net) + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2003 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman (jweidman@slip.net), + neviksti (neviksti@hotmail.com), and + Kris Bleakley (stinkfish@bigpond.com) + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2003 zsKnight, pagefault (pagefault@zsnes.com) + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar and Gary Henderson. + + + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#ifndef _C4_H_ +#define _C4_H_ + +#include "port.h" +#include "memmap.h" + +extern "C" { + +extern int16 C4WFXVal; +extern int16 C4WFYVal; +extern int16 C4WFZVal; +extern int16 C4WFX2Val; +extern int16 C4WFY2Val; +extern int16 C4WFDist; +extern int16 C4WFScale; + +void C4TransfWireFrame(); +void C4TransfWireFrame2(); +void C4CalcWireFrame(); + +extern int16 C41FXVal; +extern int16 C41FYVal; +extern int16 C41FAngleRes; +extern int16 C41FDist; +extern int16 C41FDistVal; + +void C4Op1F(); +void C4Op15(); +void C4Op0D(); + +extern int16 C4CosTable[]; +extern int16 C4SinTable[]; + +} + +static inline uint8 *C4GetMemPointer(uint32 Address){ + return (Memory.ROM + ((Address&0xff0000)>>1) + (Address&0x7fff)); +} + +#endif diff --git a/src/c4emu.cpp b/src/c4emu.cpp new file mode 100644 index 0000000..5e82222 --- /dev/null +++ b/src/c4emu.cpp @@ -0,0 +1,1007 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2003 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2002 - 2003 Matthew Kendora and + Brad Jorsch (anomie@users.sourceforge.net) + + + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and + Nach (n-a-c-h@users.sourceforge.net) + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2003 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman (jweidman@slip.net), + neviksti (neviksti@hotmail.com), and + Kris Bleakley (stinkfish@bigpond.com) + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2003 zsKnight, pagefault (pagefault@zsnes.com) + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar and Gary Henderson. + + + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ + +#ifndef __GP32__ +#ifdef HAVE_CONFIG_H + #include +#endif +#endif + +#include +#include "snes9x.h" +#include "sar.h" +#include "memmap.h" +#include "ppu.h" +#include "c4.h" + +void S9xInitC4 () +{ + // Stupid zsnes code, we can't do the logical thing without breaking + // savestates +// Memory.C4RAM = &Memory.FillRAM [0x6000]; + memset(Memory.C4RAM, 0, 0x2000); +} + +uint8 S9xGetC4 (uint16 Address) +{ +#ifdef DEBUGGER + if(Settings.BGLayering) printf("%02x from %04x\n", Memory.C4RAM[Address-0x6000], Address); +#endif + if(Address==0x7f5e) return 0; + return (Memory.C4RAM [Address-0x6000]); +} + +static uint8 C4TestPattern [12 * 4] = +{ + 0x00, 0x00, 0x00, 0xff, + 0xff, 0xff, 0x00, 0xff, + 0x00, 0x00, 0x00, 0xff, + 0xff, 0xff, 0x00, 0x00, + 0xff, 0xff, 0x00, 0x00, + 0x80, 0xff, 0xff, 0x7f, + 0x00, 0x80, 0x00, 0xff, + 0x7f, 0x00, 0xff, 0x7f, + 0xff, 0x7f, 0xff, 0xff, + 0x00, 0x00, 0x01, 0xff, + 0xff, 0xfe, 0x00, 0x01, + 0x00, 0xff, 0xfe, 0x00 +}; + + +static void C4ConvOAM(void){ + uint8 *OAMptr=Memory.C4RAM+(Memory.C4RAM[0x626]<<2); + for(uint8 *i=Memory.C4RAM+0x1fd; i>OAMptr; i-=4){ + // Clear OAM-to-be + *i=0xe0; + } + + uint16 globalX, globalY; + uint8 *OAMptr2; + int16 SprX, SprY; + uint8 SprName, SprAttr; + uint8 SprCount; + + globalX=READ_WORD(Memory.C4RAM+0x0621); + globalY=READ_WORD(Memory.C4RAM+0x0623); + OAMptr2=Memory.C4RAM+0x200+(Memory.C4RAM[0x626]>>2); + +#ifdef DEBUGGER + if(Memory.C4RAM[0x625]!=0) printf("$6625=%02x, expected 00\n", Memory.C4RAM[0x625]); + if((Memory.C4RAM[0x626]>>2)!=Memory.C4RAM[0x629]) printf("$6629=%02x, expected %02x\n", Memory.C4RAM[0x629], (Memory.C4RAM[0x626]>>2)); + if(((uint16)Memory.C4RAM[0x626]<<2)!=READ_WORD(Memory.C4RAM+0x627)) printf("$6627=%04x, expected %04x\n", READ_WORD(Memory.C4RAM+0x627), ((uint16)Memory.C4RAM[0x626]<<2)); +#endif + + if(Memory.C4RAM[0x0620]!=0){ + SprCount=128-Memory.C4RAM[0x626]; + uint8 offset=(Memory.C4RAM[0x626]&3)*2; + uint8 *srcptr=Memory.C4RAM+0x220; + for(int i=Memory.C4RAM[0x0620]; i>0 && SprCount>0; i--, srcptr+=16){ + SprX=READ_WORD(srcptr)-globalX; + SprY=READ_WORD(srcptr+2)-globalY; + SprName=srcptr[5]; + SprAttr=srcptr[4] | srcptr[0x06]; // XXX: mask bits? + + uint8 *sprptr=C4GetMemPointer(READ_3WORD(srcptr+7)); + if(*sprptr!=0){ + int16 X, Y; + for(int SprCnt=*sprptr++; SprCnt>0 && SprCount>0; SprCnt--, sprptr+=4){ + X=(int8)sprptr[1]; + if(SprAttr&0x40){ // flip X + X=-X-((sprptr[0]&0x20)?16:8); + } + X+=SprX; + if(X>=-16 && X<=272){ + Y=(int8)sprptr[2]; + if(SprAttr&0x80){ + Y=-Y-((sprptr[0]&0x20)?16:8); + } + Y+=SprY; + if(Y>=-16 && Y<=224){ + OAMptr[0]=X&0xff; + OAMptr[1]=(uint8)Y; + OAMptr[2]=SprName+sprptr[3]; + OAMptr[3]=SprAttr^(sprptr[0]&0xc0); // XXX: Carry from SprName addition? + *OAMptr2 &= ~(3<0){ + OAMptr[0]=(uint8)SprX; + OAMptr[1]=(uint8)SprY; + OAMptr[2]=SprName; + OAMptr[3]=SprAttr; + *OAMptr2 &= ~(3<>12)>=w || (Y>>12)>=h){ + byte=0; + } else { + uint32 addr=(Y>>12)*w+(X>>12); + byte=Memory.C4RAM[0x600+(addr>>1)]; + if(addr&1) byte>>=4; + } + + // De-bitplanify + if(byte&1) Memory.C4RAM[outidx]|=bit; + if(byte&2) Memory.C4RAM[outidx+1]|=bit; + if(byte&4) Memory.C4RAM[outidx+16]|=bit; + if(byte&8) Memory.C4RAM[outidx+17]|=bit; + + bit>>=1; + if(bit==0){ + bit=0x80; + outidx+=32; + } + + X+=A; // Add 1 to output x => add an A and a C + Y+=C; + } + outidx+=2+row_padding; + if(outidx&0x10){ + outidx&=~0x10; + } else { + outidx-=w*4+row_padding; + } + LineX+=B; // Add 1 to output y => add a B and a D + LineY+=D; + } +} + +static void C4DrawLine(int32 X1, int32 Y1, int16 Z1, + int32 X2, int32 Y2, int16 Z2, uint8 Color){ + // Transform coordinates + C4WFXVal=(short)X1; + C4WFYVal=(short)Y1; + C4WFZVal=Z1; + C4WFScale=Memory.C4RAM[0x1f90]; + C4WFX2Val=Memory.C4RAM[0x1f86]; + C4WFY2Val=Memory.C4RAM[0x1f87]; + C4WFDist=Memory.C4RAM[0x1f88]; + C4TransfWireFrame2(); + X1=(C4WFXVal+48)<<8; + Y1=(C4WFYVal+48)<<8; + + C4WFXVal=(short)X2; + C4WFYVal=(short)Y2; + C4WFZVal=Z2; + C4TransfWireFrame2(); + X2=(C4WFXVal+48)<<8; + Y2=(C4WFYVal+48)<<8; + + // get line info + C4WFXVal=(short)(X1>>8); + C4WFYVal=(short)(Y1>>8); + C4WFX2Val=(short)(X2>>8); + C4WFY2Val=(short)(Y2>>8); + C4CalcWireFrame(); + X2=(int16)C4WFXVal; + Y2=(int16)C4WFYVal; + + // render line + for(int i=C4WFDist?C4WFDist:1; i>0; i--) + { //.loop + if(X1>0xff && Y1>0xff && X1<0x6000 && Y1<0x6000) + { + uint16 addr=((X1&~0x7ff) + (Y1&~0x7ff)*12 + (Y1&0x700))>>7; + addr=(((Y1>>8)>>3)<<8)-(((Y1>>8)>>3)<<6)+(((X1>>8)>>3)<<4)+((Y1>>8)&7)*2; + uint8 bit=0x80>>((X1>>8)&7); + Memory.C4RAM[addr+0x300]&=~bit; + Memory.C4RAM[addr+0x301]&=~bit; + if(Color&1) Memory.C4RAM[addr+0x300]|=bit; + if(Color&2) Memory.C4RAM[addr+0x301]|=bit; + } + X1+=X2; + Y1+=Y2; + } +} + +static void C4DrawWireFrame(void) +{ + uint8 *line=C4GetMemPointer(READ_3WORD(Memory.C4RAM+0x1f80)); + uint8 *point1, *point2; + int16 X1, Y1, Z1; + int16 X2, Y2, Z2; + uint8 Color; + +#ifdef DEBUGGER + if(READ_3WORD(Memory.C4RAM+0x1f8f)&0xff00ff) printf("wireframe: Unexpected value in $7f8f: %06x\n", READ_3WORD(Memory.C4RAM+0x1f8f)); + if(READ_3WORD(Memory.C4RAM+0x1fa4)!=0x001000) printf("wireframe: Unexpected value in $7fa4: %06x\n", READ_3WORD(Memory.C4RAM+0x1fa4)); +#endif + + for(int i=Memory.C4RAM[0x0295]; i>0; i--, line+=5){ + if(line[0]==0xff && line[1]==0xff){ + uint8 *tmp=line-5; + while(tmp[2]==0xff && tmp[3]==0xff) tmp-=5; + point1=C4GetMemPointer((Memory.C4RAM[0x1f82]<<16) | (tmp[2]<<8) | tmp[3]); + } else { + point1=C4GetMemPointer((Memory.C4RAM[0x1f82]<<16) | (line[0]<<8) | line[1]); + } + point2=C4GetMemPointer((Memory.C4RAM[0x1f82]<<16) | (line[2]<<8) | line[3]); + + X1=(point1[0]<<8) | point1[1]; + Y1=(point1[2]<<8) | point1[3]; + Z1=(point1[4]<<8) | point1[5]; + X2=(point2[0]<<8) | point2[1]; + Y2=(point2[2]<<8) | point2[3]; + Z2=(point2[4]<<8) | point2[5]; + Color=line[4]; + C4DrawLine(X1, Y1, Z1, X2, Y2, Z2, Color); + } +} + +static void C4TransformLines(void){ + C4WFX2Val=Memory.C4RAM[0x1f83]; + C4WFY2Val=Memory.C4RAM[0x1f86]; + C4WFDist=Memory.C4RAM[0x1f89]; + C4WFScale=Memory.C4RAM[0x1f8c]; + +#ifdef DEBUGGER + if(Memory.C4RAM[0x1f8a]!=0x90) printf("lines: $7f8a = %02x, expected 90\n", READ_WORD(Memory.C4RAM+0x1f8a)); +#endif + + // transform vertices + uint8 *ptr=Memory.C4RAM; + { + for(int i=READ_WORD(Memory.C4RAM+0x1f80); i>0; i--, ptr+=0x10) + { + C4WFXVal=READ_WORD(ptr+1); + C4WFYVal=READ_WORD(ptr+5); + C4WFZVal=READ_WORD(ptr+9); + C4TransfWireFrame(); + + // displace + WRITE_WORD(ptr+1, C4WFXVal+0x80); + WRITE_WORD(ptr+5, C4WFYVal+0x50); + } + } + WRITE_WORD(Memory.C4RAM+0x600, 23); + WRITE_WORD(Memory.C4RAM+0x602, 0x60); + WRITE_WORD(Memory.C4RAM+0x605, 0x40); + WRITE_WORD(Memory.C4RAM+0x600+8, 23); + WRITE_WORD(Memory.C4RAM+0x602+8, 0x60); + WRITE_WORD(Memory.C4RAM+0x605+8, 0x40); + + ptr=Memory.C4RAM+0xb02; + uint8 *ptr2=Memory.C4RAM; + { + for(int i=READ_WORD(Memory.C4RAM+0xb00); i>0; i--, ptr+=2, ptr2+=8) + { + C4WFXVal=READ_WORD(Memory.C4RAM+(ptr[0]<<4)+1); + C4WFYVal=READ_WORD(Memory.C4RAM+(ptr[0]<<4)+5); + C4WFX2Val=READ_WORD(Memory.C4RAM+(ptr[1]<<4)+1); + C4WFY2Val=READ_WORD(Memory.C4RAM+(ptr[1]<<4)+5); + C4CalcWireFrame(); + WRITE_WORD(ptr2+0x600, C4WFDist?C4WFDist:1); + WRITE_WORD(ptr2+0x602, C4WFXVal); + WRITE_WORD(ptr2+0x605, C4WFYVal); + } + } +} +static void C4BitPlaneWave(){ + static uint16 bmpdata[]={ + 0x0000, 0x0002, 0x0004, 0x0006, 0x0008, 0x000A, 0x000C, 0x000E, + 0x0200, 0x0202, 0x0204, 0x0206, 0x0208, 0x020A, 0x020C, 0x020E, + 0x0400, 0x0402, 0x0404, 0x0406, 0x0408, 0x040A, 0x040C, 0x040E, + 0x0600, 0x0602, 0x0604, 0x0606, 0x0608, 0x060A, 0x060C, 0x060E, + 0x0800, 0x0802, 0x0804, 0x0806, 0x0808, 0x080A, 0x080C, 0x080E + }; + + uint8 *dst=Memory.C4RAM; + uint32 waveptr=Memory.C4RAM[0x1f83]; + uint16 mask1=0xc0c0; + uint16 mask2=0x3f3f; + +#ifdef DEBUGGER + if(READ_3WORD(Memory.C4RAM+0x1f80) != Memory.C4RAM[waveptr+0xb00]) printf("$7f80=%06x, expected %02x\n", READ_3WORD(Memory.C4RAM+0x1f80), Memory.C4RAM[waveptr+0xb00]); +#endif + + for(int j=0; j<0x10; j++){ + do { + int16 height=-((int8)Memory.C4RAM[waveptr+0xb00])-16; + for(int i=0; i<40; i++){ + uint16 tmp=READ_WORD(dst+bmpdata[i]) & mask2; + if(height>=0){ + if(height<8){ + tmp|=mask1&READ_WORD(Memory.C4RAM+0xa00+height*2); + } else { + tmp|=mask1&0xff00; + } + } + WRITE_WORD(dst+bmpdata[i], tmp); + height++; + } + waveptr=(waveptr+1)&0x7f; + mask1=(mask1>>2)|(mask1<<6); + mask2=(mask2>>2)|(mask2<<6); + } while(mask1!=0xc0c0); + dst+=16; + + do { + int16 height=-((int8)Memory.C4RAM[waveptr+0xb00])-16; + for(int i=0; i<40; i++){ + uint16 tmp=READ_WORD(dst+bmpdata[i]) & mask2; + if(height>=0){ + if(height<8){ + tmp|=mask1&READ_WORD(Memory.C4RAM+0xa10+height*2); + } else { + tmp|=mask1&0xff00; + } + } + WRITE_WORD(dst+bmpdata[i], tmp); + height++; + } + waveptr=(waveptr+1)&0x7f; + mask1=(mask1>>2)|(mask1<<6); + mask2=(mask2>>2)|(mask2<<6); + } while(mask1!=0xc0c0); + dst+=16; + } +} + +static void C4SprDisintegrate() +{ + uint8 width, height; + uint32 StartX, StartY; + uint8 *src; + int32 scaleX, scaleY; + int32 Cx, Cy; + + width=Memory.C4RAM[0x1f89]; + height=Memory.C4RAM[0x1f8c]; + Cx=(int16)READ_WORD(Memory.C4RAM+0x1f80); + Cy=(int16)READ_WORD(Memory.C4RAM+0x1f83); + +#ifdef DEBUGGER + if((Cx&~1)!=width/2 || (Cy&~1)!=height/2) printf("Center is not middle of image for disintegrate! (%d, %d) != (%d, %d)\n", Cx, Cy, width/2, height/2); +#endif + + scaleX=(int16)READ_WORD(Memory.C4RAM+0x1f86); + scaleY=(int16)READ_WORD(Memory.C4RAM+0x1f8f); + StartX=-Cx*scaleX+(Cx<<8); + StartY=-Cy*scaleY+(Cy<<8); + src=Memory.C4RAM+0x600; + + memset(Memory.C4RAM, 0, width*height/2); + + for(uint32 y=StartY, i=0; i>8)>8)>8)*width+(x>>8)<0x2000) + { + uint8 pixel=(j&1)?(*src>>4):*src; + int idx=(y>>11)*width*4+(x>>11)*32+((y>>8)&7)*2; + uint8 mask=0x80>>((x>>8)&7); + if(pixel&1) Memory.C4RAM[idx]|=mask; + if(pixel&2) Memory.C4RAM[idx+1]|=mask; + if(pixel&4) Memory.C4RAM[idx+16]|=mask; + if(pixel&8) Memory.C4RAM[idx+17]|=mask; + } + if(j&1) src++; + } + } +} + +static void S9xC4ProcessSprites() +{ + switch(Memory.C4RAM[0x1f4d]) + { + case 0x00: // Build OAM +#ifdef DEBUGGER +// printf("00 00 Build OAM!\n"); +#endif + C4ConvOAM(); + break; + + case 0x03: // Scale/Rotate +#ifdef DEBUGGER +// printf("00 03 Scale/Rotate!\n"); +#endif + C4DoScaleRotate(0); + break; + + case 0x05: // Transform Lines +#ifdef DEBUGGER +// printf("00 05 Transform Lines!\n"); +#endif + C4TransformLines(); + break; + + case 0x07: // Scale/Rotate +#ifdef DEBUGGER +// printf("00 07 Scale/Rotate!\n"); +#endif + C4DoScaleRotate(64); + break; + + case 0x08: // Draw wireframe +#ifdef DEBUGGER +// printf("00 08 Draw wireframe!\n"); +#endif + C4DrawWireFrame(); + break; + + case 0x0b: // Disintegrate +#ifdef DEBUGGER + printf("00 0b Disintegrate!\n"); +#endif + C4SprDisintegrate(); + break; + + case 0x0c: // Wave +#ifdef DEBUGGER +// printf("00 0b Wave!\n"); +#endif + C4BitPlaneWave(); + break; + + default: +#ifdef DEBUGGER + printf ("Unknown C4 sprite command (%02x)\n", Memory.C4RAM [0x1f4d]); +#endif + break; + } +} + +void S9xSetC4 (uint8 byte, uint16 Address) +{ + int i; + +#ifdef DEBUGGER + if(Settings.BGLayering) printf("%02x to %04x\n", byte, Address); +#endif + Memory.C4RAM [Address-0x6000] = byte; + if (Address == 0x7f4f) + { + if(Memory.C4RAM[0x1f4d]==0x0e && byte<0x40 && (byte&3)==0) + { +#ifdef DEBUGGER + printf("Test command %02x 0e used!\n", byte); +#endif + Memory.C4RAM[0x1f80]=byte>>2; + } + else + { + switch (byte) + { + case 0x00: // Sprite + S9xC4ProcessSprites(); + break; + + case 0x01: // Draw wireframe +#ifdef DEBUGGER + //printf("01 Draw wireframe used!\n"); + if(Memory.C4RAM[0x1f4d]!=8) printf("$7f4d=%02x, expected 08 for command 01 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + memset(Memory.C4RAM+0x300, 0, 16*12*3*4); + C4DrawWireFrame(); + break; + + case 0x05: // Propulsion (?) +#ifdef DEBUGGER + printf("05 Propulsion (?)!\n"); + if(Memory.C4RAM[0x1f4d]!=2) printf("$7f4d=%02x, expected 02 for command 05 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + { + int32 tmp=0x10000; + if(READ_WORD(Memory.C4RAM+0x1f83)){ + tmp=SAR((tmp/READ_WORD(Memory.C4RAM+0x1f83))*READ_WORD(Memory.C4RAM+0x1f81), 8); + } + WRITE_WORD(Memory.C4RAM+0x1f80, (uint16)tmp); + } + break; + + case 0x0d: // Set vector length +#ifdef DEBUGGER + printf("0d Set vector length!\n"); + if(Memory.C4RAM[0x1f4d]!=2) printf("$7f4d=%02x, expected 02 for command 0d %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + C41FXVal=READ_WORD(Memory.C4RAM+0x1f80); + C41FYVal=READ_WORD(Memory.C4RAM+0x1f83); + C41FDistVal=READ_WORD(Memory.C4RAM+0x1f86); + C4Op0D(); + WRITE_WORD(Memory.C4RAM+0x1f89, C41FXVal); + WRITE_WORD(Memory.C4RAM+0x1f8c, C41FYVal); + break; + + case 0x10: // Polar to rectangluar +#ifdef DEBUGGER +// printf("10 Polar->Rect!\n"); + if(Memory.C4RAM[0x1f4d]!=2) printf("$7f4d=%02x, expected 02 for command 10 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + { + int32 tmp=SAR((int32)READ_WORD(Memory.C4RAM+0x1f83)*C4CosTable[READ_WORD(Memory.C4RAM+0x1f80)&0x1ff]*2, 16); + WRITE_3WORD(Memory.C4RAM+0x1f86, tmp); + tmp=SAR((int32)READ_WORD(Memory.C4RAM+0x1f83)*C4SinTable[READ_WORD(Memory.C4RAM+0x1f80)&0x1ff]*2, 16); + WRITE_3WORD(Memory.C4RAM+0x1f89, (tmp-SAR(tmp, 6))); + } + break; + + case 0x13: // Polar to rectangluar +#ifdef DEBUGGER +// printf("13 Polar->Rect!\n"); + if(Memory.C4RAM[0x1f4d]!=2) printf("$7f4d=%02x, expected 02 for command 13 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + { + int32 tmp=SAR((int32)READ_WORD(Memory.C4RAM+0x1f83)*C4CosTable[READ_WORD(Memory.C4RAM+0x1f80)&0x1ff]*2, 8); + WRITE_3WORD(Memory.C4RAM+0x1f86, tmp); + tmp=SAR((int32)READ_WORD(Memory.C4RAM+0x1f83)*C4SinTable[READ_WORD(Memory.C4RAM+0x1f80)&0x1ff]*2, 8); + WRITE_3WORD(Memory.C4RAM+0x1f89, tmp); + } + break; + + case 0x15: // Pythagorean +#ifdef DEBUGGER + printf("15 Pythagorean!\n"); + if(Memory.C4RAM[0x1f4d]!=2) printf("$7f4d=%02x, expected 02 for command 15 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + C41FXVal=READ_WORD(Memory.C4RAM+0x1f80); + C41FYVal=READ_WORD(Memory.C4RAM+0x1f83); + C41FDist=(int16)sqrtf((float)C41FXVal*C41FXVal + (float)C41FYVal*C41FYVal); + WRITE_WORD(Memory.C4RAM+0x1f80, C41FDist); + break; + + case 0x1f: // atan +#ifdef DEBUGGER +// printf("1f atan!\n"); + if(Memory.C4RAM[0x1f4d]!=2) printf("$7f4d=%02x, expected 02 for command 1f %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + C41FXVal=READ_WORD(Memory.C4RAM+0x1f80); + C41FYVal=READ_WORD(Memory.C4RAM+0x1f83); + C4Op1F(); + WRITE_WORD(Memory.C4RAM+0x1f86, C41FAngleRes); + break; + + case 0x22: // Trapezoid + { +#ifdef DEBUGGER +// printf("22 Trapezoid!\n"); + if(Memory.C4RAM[0x1f4d]!=2) printf("$7f4d=%02x, expected 02 for command 22 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + int16 angle1=READ_WORD(Memory.C4RAM+0x1f8c)&0x1ff; + int16 angle2=READ_WORD(Memory.C4RAM+0x1f8f)&0x1ff; +#ifdef DEBUGGER + if(C4CosTable[angle1]==0) fprintf(stderr, "22 Trapezoid: Invalid tangent! angle1=%d\n", angle1); + if(C4CosTable[angle2]==0) fprintf(stderr, "22 Trapezoid: Invalid tangent! angle2=%d\n", angle2); +#endif + int32 tan1=(C4CosTable[angle1]!=0)?((((int32)C4SinTable[angle1])<<16)/C4CosTable[angle1]):0x80000000; + int32 tan2=(C4CosTable[angle2]!=0)?((((int32)C4SinTable[angle2])<<16)/C4CosTable[angle2]):0x80000000; + int16 y = READ_WORD(Memory.C4RAM+0x1f83) - READ_WORD(Memory.C4RAM+0x1f89); + int16 left, right; + for(int j=0; j<225; j++) + { + if(y>=0) + { + left = SAR((int32)tan1*y, 16) - + READ_WORD(Memory.C4RAM+0x1f80) + + READ_WORD(Memory.C4RAM+0x1f86); + right = SAR((int32)tan2*y, 16) - + READ_WORD(Memory.C4RAM+0x1f80) + + READ_WORD(Memory.C4RAM+0x1f86) + + READ_WORD(Memory.C4RAM+0x1f93); + + if(left<0 && right<0){ + left=1; + right=0; + } else if(left<0){ + left=0; + } else if(right<0){ + right=0; + } + if(left>255 && right>255){ + left=255; + right=254; + } else if(left>255){ + left=255; + } else if(right>255){ + right=255; + } + } + else + { + left=1; + right=0; + } + Memory.C4RAM[j+0x800] = (uint8)left; + Memory.C4RAM[j+0x900] = (uint8)right; + y++; + } + } + break; + + case 0x25: // Multiply +#ifdef DEBUGGER + printf("25 Multiply!\n"); + if(Memory.C4RAM[0x1f4d]!=2) printf("$7f4d=%02x, expected 02 for command 25 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + { + int32 foo=READ_3WORD(Memory.C4RAM+0x1f80); + int32 bar=READ_3WORD(Memory.C4RAM+0x1f83); + foo*=bar; + WRITE_3WORD(Memory.C4RAM+0x1f80, foo); + } + break; + + case 0x2d: // Transform Coords +#ifdef DEBUGGER +// printf("2d Transform Coords!\n"); + if(Memory.C4RAM[0x1f4d]!=2) printf("$7f4d=%02x, expected 02 for command 2d %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); + if(READ_3WORD(Memory.C4RAM+0x1f8f)&0xff00ff) printf("2d transform coords: Unexpected value in $7f8f: %06x\n", READ_3WORD(Memory.C4RAM+0x1f8f)); + if(READ_3WORD(Memory.C4RAM+0x1f8c)!=0x001000) printf("0d transform coords: Unexpected value in $7f8c: %06x\n", READ_3WORD(Memory.C4RAM+0x1f8c)); +#endif + C4WFXVal=READ_WORD(Memory.C4RAM+0x1f81); + C4WFYVal=READ_WORD(Memory.C4RAM+0x1f84); + C4WFZVal=READ_WORD(Memory.C4RAM+0x1f87); + C4WFX2Val=Memory.C4RAM[0x1f89]; + C4WFY2Val=Memory.C4RAM[0x1f8a]; + C4WFDist=Memory.C4RAM[0x1f8b]; + C4WFScale=READ_WORD(Memory.C4RAM+0x1f90); + C4TransfWireFrame2(); + WRITE_WORD(Memory.C4RAM+0x1f80, C4WFXVal); + WRITE_WORD(Memory.C4RAM+0x1f83, C4WFYVal); + break; + + case 0x40: // Sum +#ifdef DEBUGGER + printf("40 Sum!\n"); + if(Memory.C4RAM[0x1f4d]!=0x0e) printf("$7f4d=%02x, expected 0e for command 40 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + { + uint16 sum=0; + for(int i=0; i<0x800; sum+=Memory.C4RAM[i++]); + WRITE_WORD(Memory.C4RAM+0x1f80, sum); + } + break; + + case 0x54: // Square +#ifdef DEBUGGER + printf("54 Square!\n"); + if(Memory.C4RAM[0x1f4d]!=0x0e) printf("$7f4d=%02x, expected 0e for command 54 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + { + int64 a=SAR((int64)READ_3WORD(Memory.C4RAM+0x1f80)<<40, 40); + // printf("%08X%08X\n", (uint32)(a>>32), (uint32)(a&0xFFFFFFFF)); + a*=a; + // printf("%08X%08X\n", (uint32)(a>>32), (uint32)(a&0xFFFFFFFF)); + WRITE_3WORD(Memory.C4RAM+0x1f83, a); + WRITE_3WORD(Memory.C4RAM+0x1f86, (a>>24)); + } + break; + + case 0x5c: // Immediate Reg +#ifdef DEBUGGER + printf("5c Immediate Reg!\n"); + if(Memory.C4RAM[0x1f4d]!=0x0e) printf("$7f4d=%02x, expected 0e for command 5c %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + for (i = 0; i < 12 * 4; i++) + Memory.C4RAM [i] = C4TestPattern [i]; + break; + + case 0x89: // Immediate ROM +#ifdef DEBUGGER + printf("89 Immediate ROM!\n"); + if(Memory.C4RAM[0x1f4d]!=0x0e) printf("$7f4d=%02x, expected 0e for command 89 %02x\n", Memory.C4RAM[0x1f4d], Memory.C4RAM[0x1f4d]); +#endif + Memory.C4RAM [0x1f80] = 0x36; + Memory.C4RAM [0x1f81] = 0x43; + Memory.C4RAM [0x1f82] = 0x05; + break; + + default: +#ifdef DEBUGGER + printf ("Unknown C4 command (%02x)\n", byte); +#endif + break; + } + } + } else if (Address == 0x7f47) { +#ifdef DEBUGGER +// printf("C4 load memory %06x => %04x, %04x bytes\n", READ_3WORD(Memory.C4RAM+0x1f40), READ_WORD(Memory.C4RAM+0x1f45), READ_WORD(Memory.C4RAM+0x1f43)); + if(byte != 0) printf("C4 load: non-0 written to $7f47! Wrote %02x\n", byte); + if(READ_WORD(Memory.C4RAM+0x1f45) < 0x6000 || (READ_WORD(Memory.C4RAM+0x1f45) + READ_WORD(Memory.C4RAM+0x1f43)) > 0x6c00) printf("C4 load: Dest unusual! It's %04x\n", READ_WORD(Memory.C4RAM+0x1f45)); +#endif + memmove(Memory.C4RAM+(READ_WORD(Memory.C4RAM+0x1f45)&0x1fff), + C4GetMemPointer(READ_3WORD(Memory.C4RAM+0x1f40)), + READ_WORD(Memory.C4RAM+0x1f43)); + } +} + +int16 C4SinTable[512] = { + 0, 402, 804, 1206, 1607, 2009, 2410, 2811, + 3211, 3611, 4011, 4409, 4808, 5205, 5602, 5997, + 6392, 6786, 7179, 7571, 7961, 8351, 8739, 9126, + 9512, 9896, 10278, 10659, 11039, 11416, 11793, 12167, + 12539, 12910, 13278, 13645, 14010, 14372, 14732, 15090, + 15446, 15800, 16151, 16499, 16846, 17189, 17530, 17869, + 18204, 18537, 18868, 19195, 19519, 19841, 20159, 20475, + 20787, 21097, 21403, 21706, 22005, 22301, 22594, 22884, + 23170, 23453, 23732, 24007, 24279, 24547, 24812, 25073, + 25330, 25583, 25832, 26077, 26319, 26557, 26790, 27020, + 27245, 27466, 27684, 27897, 28106, 28310, 28511, 28707, + 28898, 29086, 29269, 29447, 29621, 29791, 29956, 30117, + 30273, 30425, 30572, 30714, 30852, 30985, 31114, 31237, + 31357, 31471, 31581, 31685, 31785, 31881, 31971, 32057, + 32138, 32214, 32285, 32351, 32413, 32469, 32521, 32568, + 32610, 32647, 32679, 32706, 32728, 32745, 32758, 32765, + 32767, 32765, 32758, 32745, 32728, 32706, 32679, 32647, + 32610, 32568, 32521, 32469, 32413, 32351, 32285, 32214, + 32138, 32057, 31971, 31881, 31785, 31685, 31581, 31471, + 31357, 31237, 31114, 30985, 30852, 30714, 30572, 30425, + 30273, 30117, 29956, 29791, 29621, 29447, 29269, 29086, + 28898, 28707, 28511, 28310, 28106, 27897, 27684, 27466, + 27245, 27020, 26790, 26557, 26319, 26077, 25832, 25583, + 25330, 25073, 24812, 24547, 24279, 24007, 23732, 23453, + 23170, 22884, 22594, 22301, 22005, 21706, 21403, 21097, + 20787, 20475, 20159, 19841, 19519, 19195, 18868, 18537, + 18204, 17869, 17530, 17189, 16846, 16499, 16151, 15800, + 15446, 15090, 14732, 14372, 14010, 13645, 13278, 12910, + 12539, 12167, 11793, 11416, 11039, 10659, 10278, 9896, + 9512, 9126, 8739, 8351, 7961, 7571, 7179, 6786, + 6392, 5997, 5602, 5205, 4808, 4409, 4011, 3611, + 3211, 2811, 2410, 2009, 1607, 1206, 804, 402, + 0, -402, -804, -1206, -1607, -2009, -2410, -2811, + -3211, -3611, -4011, -4409, -4808, -5205, -5602, -5997, + -6392, -6786, -7179, -7571, -7961, -8351, -8739, -9126, + -9512, -9896, -10278, -10659, -11039, -11416, -11793, -12167, + -12539, -12910, -13278, -13645, -14010, -14372, -14732, -15090, + -15446, -15800, -16151, -16499, -16846, -17189, -17530, -17869, + -18204, -18537, -18868, -19195, -19519, -19841, -20159, -20475, + -20787, -21097, -21403, -21706, -22005, -22301, -22594, -22884, + -23170, -23453, -23732, -24007, -24279, -24547, -24812, -25073, + -25330, -25583, -25832, -26077, -26319, -26557, -26790, -27020, + -27245, -27466, -27684, -27897, -28106, -28310, -28511, -28707, + -28898, -29086, -29269, -29447, -29621, -29791, -29956, -30117, + -30273, -30425, -30572, -30714, -30852, -30985, -31114, -31237, + -31357, -31471, -31581, -31685, -31785, -31881, -31971, -32057, + -32138, -32214, -32285, -32351, -32413, -32469, -32521, -32568, + -32610, -32647, -32679, -32706, -32728, -32745, -32758, -32765, + -32767, -32765, -32758, -32745, -32728, -32706, -32679, -32647, + -32610, -32568, -32521, -32469, -32413, -32351, -32285, -32214, + -32138, -32057, -31971, -31881, -31785, -31685, -31581, -31471, + -31357, -31237, -31114, -30985, -30852, -30714, -30572, -30425, + -30273, -30117, -29956, -29791, -29621, -29447, -29269, -29086, + -28898, -28707, -28511, -28310, -28106, -27897, -27684, -27466, + -27245, -27020, -26790, -26557, -26319, -26077, -25832, -25583, + -25330, -25073, -24812, -24547, -24279, -24007, -23732, -23453, + -23170, -22884, -22594, -22301, -22005, -21706, -21403, -21097, + -20787, -20475, -20159, -19841, -19519, -19195, -18868, -18537, + -18204, -17869, -17530, -17189, -16846, -16499, -16151, -15800, + -15446, -15090, -14732, -14372, -14010, -13645, -13278, -12910, + -12539, -12167, -11793, -11416, -11039, -10659, -10278, -9896, + -9512, -9126, -8739, -8351, -7961, -7571, -7179, -6786, + -6392, -5997, -5602, -5205, -4808, -4409, -4011, -3611, + -3211, -2811, -2410, -2009, -1607, -1206, -804, -402 +}; + +int16 C4CosTable[512] = { + 32767, 32765, 32758, 32745, 32728, 32706, 32679, 32647, + 32610, 32568, 32521, 32469, 32413, 32351, 32285, 32214, + 32138, 32057, 31971, 31881, 31785, 31685, 31581, 31471, + 31357, 31237, 31114, 30985, 30852, 30714, 30572, 30425, + 30273, 30117, 29956, 29791, 29621, 29447, 29269, 29086, + 28898, 28707, 28511, 28310, 28106, 27897, 27684, 27466, + 27245, 27020, 26790, 26557, 26319, 26077, 25832, 25583, + 25330, 25073, 24812, 24547, 24279, 24007, 23732, 23453, + 23170, 22884, 22594, 22301, 22005, 21706, 21403, 21097, + 20787, 20475, 20159, 19841, 19519, 19195, 18868, 18537, + 18204, 17869, 17530, 17189, 16846, 16499, 16151, 15800, + 15446, 15090, 14732, 14372, 14010, 13645, 13278, 12910, + 12539, 12167, 11793, 11416, 11039, 10659, 10278, 9896, + 9512, 9126, 8739, 8351, 7961, 7571, 7179, 6786, + 6392, 5997, 5602, 5205, 4808, 4409, 4011, 3611, + 3211, 2811, 2410, 2009, 1607, 1206, 804, 402, + 0, -402, -804, -1206, -1607, -2009, -2410, -2811, + -3211, -3611, -4011, -4409, -4808, -5205, -5602, -5997, + -6392, -6786, -7179, -7571, -7961, -8351, -8739, -9126, + -9512, -9896, -10278, -10659, -11039, -11416, -11793, -12167, + -12539, -12910, -13278, -13645, -14010, -14372, -14732, -15090, + -15446, -15800, -16151, -16499, -16846, -17189, -17530, -17869, + -18204, -18537, -18868, -19195, -19519, -19841, -20159, -20475, + -20787, -21097, -21403, -21706, -22005, -22301, -22594, -22884, + -23170, -23453, -23732, -24007, -24279, -24547, -24812, -25073, + -25330, -25583, -25832, -26077, -26319, -26557, -26790, -27020, + -27245, -27466, -27684, -27897, -28106, -28310, -28511, -28707, + -28898, -29086, -29269, -29447, -29621, -29791, -29956, -30117, + -30273, -30425, -30572, -30714, -30852, -30985, -31114, -31237, + -31357, -31471, -31581, -31685, -31785, -31881, -31971, -32057, + -32138, -32214, -32285, -32351, -32413, -32469, -32521, -32568, + -32610, -32647, -32679, -32706, -32728, -32745, -32758, -32765, + -32767, -32765, -32758, -32745, -32728, -32706, -32679, -32647, + -32610, -32568, -32521, -32469, -32413, -32351, -32285, -32214, + -32138, -32057, -31971, -31881, -31785, -31685, -31581, -31471, + -31357, -31237, -31114, -30985, -30852, -30714, -30572, -30425, + -30273, -30117, -29956, -29791, -29621, -29447, -29269, -29086, + -28898, -28707, -28511, -28310, -28106, -27897, -27684, -27466, + -27245, -27020, -26790, -26557, -26319, -26077, -25832, -25583, + -25330, -25073, -24812, -24547, -24279, -24007, -23732, -23453, + -23170, -22884, -22594, -22301, -22005, -21706, -21403, -21097, + -20787, -20475, -20159, -19841, -19519, -19195, -18868, -18537, + -18204, -17869, -17530, -17189, -16846, -16499, -16151, -15800, + -15446, -15090, -14732, -14372, -14010, -13645, -13278, -12910, + -12539, -12167, -11793, -11416, -11039, -10659, -10278, -9896, + -9512, -9126, -8739, -8351, -7961, -7571, -7179, -6786, + -6392, -5997, -5602, -5205, -4808, -4409, -4011, -3611, + -3211, -2811, -2410, -2009, -1607, -1206, -804, -402, + 0, 402, 804, 1206, 1607, 2009, 2410, 2811, + 3211, 3611, 4011, 4409, 4808, 5205, 5602, 5997, + 6392, 6786, 7179, 7571, 7961, 8351, 8739, 9126, + 9512, 9896, 10278, 10659, 11039, 11416, 11793, 12167, + 12539, 12910, 13278, 13645, 14010, 14372, 14732, 15090, + 15446, 15800, 16151, 16499, 16846, 17189, 17530, 17869, + 18204, 18537, 18868, 19195, 19519, 19841, 20159, 20475, + 20787, 21097, 21403, 21706, 22005, 22301, 22594, 22884, + 23170, 23453, 23732, 24007, 24279, 24547, 24812, 25073, + 25330, 25583, 25832, 26077, 26319, 26557, 26790, 27020, + 27245, 27466, 27684, 27897, 28106, 28310, 28511, 28707, + 28898, 29086, 29269, 29447, 29621, 29791, 29956, 30117, + 30273, 30425, 30572, 30714, 30852, 30985, 31114, 31237, + 31357, 31471, 31581, 31685, 31785, 31881, 31971, 32057, + 32138, 32214, 32285, 32351, 32413, 32469, 32521, 32568, + 32610, 32647, 32679, 32706, 32728, 32745, 32758, 32765 +}; diff --git a/src/caanoo_sdk.c b/src/caanoo_sdk.c new file mode 100644 index 0000000..5ce36a0 --- /dev/null +++ b/src/caanoo_sdk.c @@ -0,0 +1,806 @@ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "menu.h" +#include "wiz_sdk.h" +#include +#include "polluxregs.h" +#include +#include "asmmemfuncs.h" +#include "pollux_set.h" +#include "warm.h" +#include + +#define SYS_CLK_FREQ 27 +#define BUFFERS 4 + +static int fb_size=(320*240*2); //+(16*2); + +//unsigned long gp2x_ticks_per_second=7372800/1000; +unsigned long wiz_dev[3]={0,0,0}; +unsigned long wiz_physvram[BUFFERS]={0,0,0,0}; + +unsigned short *framebuffer16[BUFFERS]={0,0,0,0}; +static unsigned short *framebuffer_mmap[BUFFERS]={0,0,0,0}; +unsigned short gp2x_sound_buffer[4+((44100*2)*8)]; //*2=stereo, *4=max buffers + +volatile short *pOutput[8]; +int InitFramebuffer=0; +int Timer=0; +volatile int SoundThreadFlag=0; +volatile int CurrentSoundBank=0; +int CurrentFrameBuffer=0; +int CurrentFrag=0; + +// 1024x8 8x8 font, i love it :) +const unsigned int font8x8[]= {0x0,0x0,0xc3663c18,0x3c2424e7,0xe724243c,0x183c66c3,0xc16f3818,0x18386fc1,0x83f61c18,0x181cf683,0xe7c3993c,0x3c99c3,0x3f7fffff,0xe7cf9f,0x3c99c3e7,0xe7c399,0x3160c080,0x40e1b,0xcbcbc37e,0x7ec3c3db,0x3c3c3c18,0x81c087e,0x8683818,0x60f0e08,0x81422418,0x18244281,0xbd5a2418,0x18245abd,0x818181ff,0xff8181,0xa1c181ff,0xff8995,0x63633e,0x3e6363,0x606060,0x606060,0x3e60603e,0x3e0303,0x3e60603e,0x3e6060,0x3e636363,0x606060,0x3e03033e,0x3e6060,0x3e03033e,0x3e6363,0x60603e,0x606060,0x3e63633e,0x3e6363,0x3e63633e,0x3e6060,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x18181818,0x180018,0x666666,0x0,0x367f3600,0x367f36,0x3c067c18,0x183e60,0x18366600,0x62660c,0xe1c361c,0x6e337b,0x181818,0x0,0x18183870,0x703818,0x18181c0e,0xe1c18,0xff3c6600,0x663c,0x7e181800,0x1818,0x0,0x60c0c00,0x7e000000,0x0,0x0,0x181800,0x18306040,0x2060c,0x6e76663c,0x3c6666,0x18181c18,0x7e1818,0x3060663c,0x7e0c18,0x3018307e,0x3c6660,0x363c3830,0x30307e,0x603e067e,0x3c6660,0x3e06063c,0x3c6666,0x1830607e,0xc0c0c,0x3c66663c,0x3c6666,0x7c66663c,0x1c3060,0x181800,0x1818,0x181800,0xc1818,0xc183060,0x603018,0x7e0000,0x7e00,0x30180c06,0x60c18,0x3060663c,0x180018,0x5676663c,0x7c0676,0x66663c18,0x66667e,0x3e66663e,0x3e6666,0x606663c,0x3c6606,0x6666361e,0x1e3666,0x3e06067e,0x7e0606,0x3e06067e,0x60606,0x7606067c,0x7c6666,0x7e666666,0x666666,0x1818183c,0x3c1818,0x60606060,0x3c6660,0xe1e3666,0x66361e,0x6060606,0x7e0606,0x6b7f7763,0x636363,0x7e7e6e66,0x666676,0x6666663c,0x3c6666,0x3e66663e,0x60606,0x6666663c,0x6c366e,0x3e66663e,0x666636,0x3c06663c,0x3c6660,0x1818187e,0x181818,0x66666666,0x7c6666,0x66666666,0x183c66,0x6b636363,0x63777f,0x183c6666,0x66663c,0x3c666666,0x181818,0x1830607e,0x7e060c,0x18181878,0x781818,0x180c0602,0x406030,0x1818181e,0x1e1818,0x63361c08,0x0,0x0,0x7f0000,0xc060300,0x0,0x603c0000,0x7c667c,0x663e0606,0x3e6666,0x63c0000,0x3c0606,0x667c6060,0x7c6666,0x663c0000,0x3c067e,0xc3e0c38,0xc0c0c,0x667c0000,0x3e607c66,0x663e0606,0x666666,0x181c0018,0x3c1818,0x18180018,0xe181818,0x36660606,0x66361e,0x1818181c,0x3c1818,0x7f370000,0x63636b,0x663e0000,0x666666,0x663c0000,0x3c6666,0x663e0000,0x63e6666,0x667c0000,0x607c6666,0x663e0000,0x60606,0x67c0000,0x3e603c,0x187e1800,0x701818,0x66660000,0x7c6666,0x66660000,0x183c66,0x63630000,0x363e6b,0x3c660000,0x663c18,0x66660000,0x3e607c66,0x307e0000,0x7e0c18,0xc181870,0x701818,0x18181818,0x18181818,0x3018180e,0xe1818,0x794f0600,0x30}; + +pthread_t gp2x_sound_thread=0, gp2x_sound_thread_exit=0; + +uint32_t bkregs32[15]; /* backing up values */ +int layer_width[2]; +volatile uint32_t *memregs32; +volatile uint16_t *memregs16; +volatile uint8_t *memregs8; + +extern unsigned short * pOutputScreen; + +/* Sets the dirty flag for the MLC */ +static void lc_dirtymlc(void) +{ + MLCCONTROLT |= BIT(3); +} + +#define FBIO_MAGIC 'D' +#define FBIO_LCD_CHANGE_CONTROL _IOW(FBIO_MAGIC, 90, unsigned int[2]) +#define LCD_DIRECTION_ON_CMD 5 /* 320x240 */ +#define LCD_DIRECTION_OFF_CMD 6 /* 240x320 */ + +void lc_screensize(int w, int h) { + unsigned int send[2]; + int fb_fd = open("/dev/fb0", O_RDWR); + send[1] = 0; + /* alter MLC to rotate the display */ + if(w == 320 && h == 240) { + send[0] = LCD_DIRECTION_ON_CMD; + } else if(w == 240 && h == 320) { + send[0] = LCD_DIRECTION_OFF_CMD; + } + + /* send command to display controller */ + ioctl(fb_fd, FBIO_LCD_CHANGE_CONTROL, &send); + close(fb_fd); + /* apply the MLC changes */ + MLCSCREENSIZE = ((h-1)<<16) | (w-1); + lc_dirtymlc(); +} + +/* Sets the dirty flag for the layer */ +static void lc_dirtylayer(int layer) +{ + if(layer == 0) { + MLCCONTROL0 |= BIT(4); + } else { + MLCCONTROL1 |= BIT(4); + } +} + +/* Sets layer position */ +static void lc_layerpos(int layer, int x1, int y1, int x2, int y2) +{ + unsigned int temp_lr, temp_tb; + temp_lr = (x1 << 16) | x2; + temp_tb = (y1 << 16) | y2; + + if(layer == 0) { + MLCLEFTRIGHT0 = temp_lr; + MLCTOPBOTTOM0 = temp_tb; + } else { + MLCLEFTRIGHT1 = temp_lr; + MLCTOPBOTTOM1 = temp_tb; + } + lc_dirtylayer(layer); + + layer_width[layer] = (x2-x1)+1; +} + +/* Sets stride registers */ +static void lc_setstride(int layer, int hs, int vs) +{ + /* set how many bytes the MLC is supposed to read */ + if(layer == 0) { + MLCHSTRIDE0 = hs; + MLCVSTRIDE0 = vs; + } else { + MLCHSTRIDE1 = hs; + MLCVSTRIDE1 = vs; + } + lc_dirtylayer(layer); +} + +/* Sets layer properties */ +static void lc_setlayer(int layer, unsigned int onoff, unsigned int alpha, unsigned int invert, unsigned int trans, unsigned int mode) +{ + /* set layer properties register */ + unsigned int temp; + temp = 0; + if(onoff) temp |= BIT(5); + if(alpha) temp |= BIT(2); + if(invert) temp |= BIT(1); + if(trans) temp |= BIT(0); + temp |= BIT(12); + temp |= BIT(14); + temp |= BIT(15); + temp |= (mode<<16); + + if(layer == 0) { + MLCCONTROL0 = temp; + } else { + MLCCONTROL1= temp; + } + lc_dirtylayer(layer); + + int pixel_width = 0; + /* set stride based on pixel width*/ + switch(mode) { + case RGB565: + case BGR565: + case XRGB1555: + case XBGR1555: + case XRGB4444: + case XBGR4444: + case XRGB8332: + case XBGR8332: + case ARGB1555: + case ABGR1555: + case ARGB4444: + case ABGR4444: + case ARGB8332: + case ABGR8332: + pixel_width = 2; + break; + case RGB888: + case BGR888: + pixel_width = 3; + break; + case ARGB8888: + case ABGR8888: + pixel_width = 4; + break; + case PTRGB565: + pixel_width = 1; + break; + default: + break; + } + lc_setstride(layer, pixel_width, pixel_width*layer_width[layer]); +} + +/* Sets the background colour */ +static void lc_setbgcol(unsigned int colour) +{ + /* colour to be displayed where no layers cover */ + MLCBGCOLOR = colour; + lc_dirtymlc(); +} + +/* +######################## +Graphics functions +######################## + */ + +static void debug(char *text, int pause) +{ + gp_clearFramebuffer16(framebuffer16[currFB],0); + gp_drawString(0,0,strlen(text),text,(unsigned short)MENU_RGB(31,31,31),framebuffer16[currFB]); + MenuFlip(); + if(pause) MenuPause(); + +} + +static int clipping_x1 = 0; +static int clipping_x2 = 319; +static int clipping_y1 = 0; +static int clipping_y2 = 239; + + +void gp_setClipping(int x1, int y1, int x2, int y2) { + if (x1 < 0) x1 = 0; + if (x1 > 319) x1 = 319; + if (x2 < 0) x2 = 0; + if (x2 > 319) x2 = 319; + if (y1 < 0) y1 = 0; + if (y1 > 239) y1 = 239; + if (y2 < 0) y2 = 0; + if (y2 > 239) y2 = 239; + + if (x1 < x2) { + clipping_x1 = x1; + clipping_x2 = x2; + } else { + clipping_x2 = x1; + clipping_x1 = x2; + } + + if (y1 < y2) { + clipping_y1 = y1; + clipping_y2 = y2; + } else { + clipping_y2 = y1; + clipping_y1 = y2; + } +} + +static __inline__ +void gp_drawPixel16 ( int x, int y, unsigned short c, unsigned short *framebuffer ) +{ + if ((x < clipping_x1) || (x > clipping_x2) || (y < clipping_y1) || (y > clipping_y2)) return; + *(framebuffer +(320*y)+x ) = c; +} + +static +void set_char8x8_16bpp (int xx,int yy,int offset,unsigned short mode,unsigned short *framebuffer) +{ + unsigned int y, pixel; + offset *= 2; + pixel = font8x8[0 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y, mode, framebuffer); + } + pixel = font8x8[1 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y+4, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y+4, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y+4, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y+4, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y+4, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y+4, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y+4, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y+4, mode, framebuffer); + + } +} + +void gp_drawString (int x,int y,int len,char *buffer,unsigned short color,void *framebuffer) +{ + int l,base=0; + + for (l=0;l 0) { + for (i=0; i < bytes/sizeof(struct input_event); i++) { + if (event[i].type == EV_ABS) { + switch (event[i].code) { + case ABS_X: abs_x = event[i].value - 128; break; + case ABS_Y: abs_y = event[i].value - 128; break; + } + } + } + } + + if (abs_x < -32) key |= (1< 32) key |= (1< 32) key |= (1<= 8) CurrentSoundBank = 0; + + //if (SoundThreadFlag==SOUND_THREAD_SOUND_ON) + //{ + write(wiz_dev[1], (void *)pOutput[CurrentSoundBank], gp2x_sound_buffer[1]); + CurrentSoundBank = (CurrentSoundBank + 1) & 7; + ioctl(wiz_dev[1], SOUND_PCM_SYNC, 0); + //ts.tv_sec=0, ts.tv_nsec=(gp2x_sound_buffer[3]<<16)|gp2x_sound_buffer[2]; + //nanosleep(&ts, NULL); +/* + } + else + { + write(wiz_dev[1], (void *)&gp2x_sound_buffer[4], gp2x_sound_buffer[1]); + //ioctl(wiz_dev[1], SOUND_PCM_SYNC, 0); + //ts.tv_sec=0, ts.tv_nsec=(gp2x_sound_buffer[3]<<16)|gp2x_sound_buffer[2]; + //nanosleep(&ts, NULL); + } +*/ + } + + return NULL; +} + +void gp_sound_volume(int l, int r) +{ + if(!wiz_dev[2]) + { + wiz_dev[2] = open("/dev/mixer", O_WRONLY); + } + + l=((l<<8)|r); + ioctl(wiz_dev[2], SOUND_MIXER_WRITE_PCM, &l); +} + +/* +unsigned long gp_timer_read(void) +{ + // Once again another peice of direct hardware access bites the dust + // the code below is broken in firmware 2.1.1 so I've replaced it with a + // to a linux function which seems to work + //return gp2x_memregl[0x0A00>>2]/gp2x_ticks_per_second; + struct timeval tval; // timing + + gettimeofday(&tval, 0); + //tval.tv_usec + //tval.tv_sec + return (tval.tv_sec*1000000)+tval.tv_usec; +} +*/ + +static int _rate = -1; +static int _bits = -1; +static int _stereo = -1; +static int _Hz = -1; +static int _frag = -1; +int gp_initSound(int rate, int bits, int stereo, int Hz, int frag) +{ + int status; + int i=0; + int nonblocking=1; + unsigned int bufferStart=0; + int result; + char text[256]; + + //int frag=0x00020010; // double buffer - frag size = 1<<0xf = 32768 + + //8 = 256 = 2 fps loss = good sound + //9 = 512 = 1 fps loss = good sound + //A = 1024 = + //f = 32768 = 0 fps loss = bad sound + //if ((frag!= CurrentFrag)&&(wiz_dev[1]!=0)) + /* + if (wiz_dev[1] != 0) + { + // Different frag config required + // close device in order to re-adjust + close(wiz_dev[1]); + wiz_dev[1]=0; + } + */ + + if (wiz_dev[1]==0) + { + wiz_dev[1] = open("/dev/dsp", O_WRONLY); + printf("Opening sound device: %x\r\n",wiz_dev[1]); + //ioctl(wiz_dev[1], SNDCTL_DSP_SETFRAGMENT, &frag); + //CurrentFrag=frag; // save frag config + } + + ioctl(wiz_dev[1], SNDCTL_DSP_RESET, 0); + + result=ioctl(wiz_dev[1], SNDCTL_DSP_SPEED, &rate); + if(result==-1) + { + debug("Error setting DSP Speed",1); + return(-1); + } + + result=ioctl(wiz_dev[1], SNDCTL_DSP_SETFMT, &bits); + if(result==-1) + { + debug("Error setting DSP format",1); + return(-1); + } + + result=ioctl(wiz_dev[1], SNDCTL_DSP_STEREO, &stereo); + if(result==-1) + { + debug("Error setting DSP format",1); + return(-1); + } + + //printf("Disable Blocking: %x\r\n",ioctl(wiz_dev[3], 0x5421, &nonblocking)); + + gp2x_sound_buffer[1]=(gp2x_sound_buffer[0]=(rate/Hz)) << (stereo + (bits==16)); + gp2x_sound_buffer[2]=(1000000000/Hz)&0xFFFF; + gp2x_sound_buffer[3]=(1000000000/Hz)>>16; + + bufferStart= (unsigned int)&gp2x_sound_buffer[4]; + pOutput[0] = (short*)bufferStart+(0*gp2x_sound_buffer[1]); + pOutput[1] = (short*)bufferStart+(1*gp2x_sound_buffer[1]); + pOutput[2] = (short*)bufferStart+(2*gp2x_sound_buffer[1]); + pOutput[3] = (short*)bufferStart+(3*gp2x_sound_buffer[1]); + pOutput[4] = (short*)bufferStart+(4*gp2x_sound_buffer[1]); + pOutput[5] = (short*)bufferStart+(5*gp2x_sound_buffer[1]); + pOutput[6] = (short*)bufferStart+(6*gp2x_sound_buffer[1]); + pOutput[7] = (short*)bufferStart+(7*gp2x_sound_buffer[1]); + + if(!gp2x_sound_thread) + { + pthread_create( &gp2x_sound_thread, NULL, gp2x_sound_play, NULL); + //atexit(gp_Reset); + } + + for(i=0;i<(gp2x_sound_buffer[1]*8);i++) + { + gp2x_sound_buffer[4+i] = 0; + } + + // save function's args + _rate = rate; + _bits = bits; + _stereo = stereo; + _Hz = Hz; + _frag = frag; + + return(0); +} + +void gp_stopSound(void) +{ + unsigned int i=0; + gp2x_sound_thread_exit=1; + printf("Killing Thread\r\n"); + for(i=0;i<(gp2x_sound_buffer[1]*8);i++) + { + gp2x_sound_buffer[4+i] = 0; + } + usleep(100000); + printf("Thread is dead\r\n"); + gp2x_sound_thread=0; + gp2x_sound_thread_exit=0; + CurrentSoundBank=0; +} + + +/* +######################## +System functions +######################## + */ +void gp_Reset(void) +{ + unsigned int i=0; + + gp_setCpuspeed(533); + + if( gp2x_sound_thread) + { + gp2x_sound_thread_exit=1; + usleep(500); + } + + MLCADDRESS0 = bkregs32[0]; MLCADDRESS1 = bkregs32[1]; MLCCONTROL0 = bkregs32[2]; MLCCONTROL1 = bkregs32[3]; MLCLEFTRIGHT0 = bkregs32[4]; + MLCTOPBOTTOM0 = bkregs32[5]; MLCLEFTRIGHT1 = bkregs32[6]; MLCTOPBOTTOM1 = bkregs32[7]; MLCBGCOLOR = bkregs32[8]; MLCHSTRIDE0 = bkregs32[9]; + MLCVSTRIDE0 = bkregs32[10]; MLCHSTRIDE1 = bkregs32[11]; MLCVSTRIDE1 = bkregs32[12]; DPCCTRL1 = bkregs32[13]; MLCSCREENSIZE = bkregs32[14]; + + lc_dirtylayer(0); + lc_dirtylayer(1); + lc_dirtymlc(); + + munmap((void *)memregs32, 0x20000); + + munmap(framebuffer_mmap[0], fb_size * BUFFERS); + + if (wiz_dev[0]) close(wiz_dev[0]); + if (wiz_dev[1]) close(wiz_dev[1]); + if (wiz_dev[2]) close(wiz_dev[2]); + + fcloseall(); + + chdir("/usr/gp2x"); + execl("gp2xmenu",NULL); +} + +void gp_video_RGB_setscaling(int W, int H) +{ + uint16_t * pSource = (uint16_t *)pOutputScreen; + uint16_t * pTarget = (uint16_t *)framebuffer16[currFB]; + unsigned short y; + unsigned short x; + if (H == 239) + { + for (y = 240; y != 0; y--) + { + pSource+=32; + for (x = 64; x != 0; x--) + { + pTarget[0] = pSource[0]; + pTarget[1] = pSource[1]; + pTarget[2] = pSource[2]; + pTarget[3] = pSource[3]; + pTarget[4] = pSource[3]; + pTarget+=5; + pSource+=4; + } + pSource+=32; + } + } + else // 224 + { + pSource += 2560; + unsigned short pos = 2; + for (y = 240; y != 0; y--) + { + pSource+=32; + for (x = 64; x != 0; x--) + { + pTarget[0] = pSource[0]; + pTarget[1] = pSource[1]; + pTarget[2] = pSource[2]; + pTarget[3] = pSource[3]; + pTarget[4] = pSource[3]; + pTarget+=5; + pSource+=4; + } + pSource+=32; + pos--; + + if (pos == 0) + { + pSource -= 320; + pos = 14; + } + } + } +} + +#define COLORMIX(a, b) ( ((((a & 0xF81F) + (b & 0xF81F)) >> 1) & 0xF81F) | ((((a & 0x07E0) + (b & 0x07E0)) >> 1) & 0x07E0) ) +void gp_video_RGB_setHZscaling(int W, int H) +{ + uint16_t * pSource = (uint16_t *)pOutputScreen; + uint16_t * pTarget = (uint16_t *)framebuffer16[currFB]; + unsigned short y; + unsigned short x; + + if (H == 224) + { + pSource += 2560; + pTarget += 2560; + } + for (y = H; y != 0; y--) + { + pSource+=32; + for (x = 64; x != 0; x--) + { + pTarget[0] = pSource[0]; + pTarget[1] = pSource[1]; + pTarget[2] = pSource[2]; + pTarget[3] = COLORMIX(pSource[2],pSource[3]); + pTarget[4] = pSource[3]; + pTarget+=5; + pSource+=4; + } + pSource+=32; + } +} + +void gp_setCpuspeed(unsigned int MHZ) +{ + unsigned long v; + //unsigned mdiv, pdiv=9, sdiv=0; + unsigned mdiv, pdiv=20, sdiv=0; + + mdiv= (MHZ * pdiv) / SYS_CLK_FREQ; + mdiv &= 0x3FF; + v= pdiv<<18 | mdiv<<8 | sdiv; + + PLLSETREG0 = v; + PWRMODE |= 0x8000; + + while (PWRMODE & 0x8000); + + // Ok, let's reset sound since it depends on CPU speed + if (_rate > 0) { + gp_initSound(_rate, _bits, _stereo, _Hz, _frag); + } +} + +// craigix: --trc 6 --tras 4 --twr 1 --tmrd 1 --trfc 1 --trp 2 --trcd 2 +// set_RAM_Timings(6, 4, 1, 1, 1, 2, 2); +void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD) +{ +} + +void set_gamma(int g100) +{ +} + + + + + diff --git a/src/caanoo_sdk.h b/src/caanoo_sdk.h new file mode 100644 index 0000000..fb642e5 --- /dev/null +++ b/src/caanoo_sdk.h @@ -0,0 +1,64 @@ +#ifndef _WIZ_SDK_H_ +#define _WIZ_SDK_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define UPPERMEM_START 0x3000000 +//0x2A00000 +#define UPPERMEM_SIZE (0x4000000-UPPERMEM_START) + +#define SOUND_THREAD_SOUND_ON 1 +#define SOUND_THREAD_SOUND_OFF 2 +#define SOUND_THREAD_PAUSE 3 + +#define INP_BUTTON_A (20) +#define INP_BUTTON_B (21) +#define INP_BUTTON_X (22) +#define INP_BUTTON_Y (23) +#define INP_BUTTON_L (18) +#define INP_BUTTON_R (19) +#define INP_BUTTON_START (17) +#define INP_BUTTON_SELECT (16) +#define INP_BUTTON_VOL_UP ( 4) +#define INP_BUTTON_VOL_DOWN ( 5) +#define INP_BUTTON_HOME (11) +#define INP_BUTTON_LEFT (12) +#define INP_BUTTON_RIGHT (13) +#define INP_BUTTON_UP (14) +#define INP_BUTTON_DOWN (15) + +void gp_setClipping(int x1, int y1, int x2, int y2); +void gp_drawString (int x,int y,int len,char *buffer,unsigned short color,void *framebuffer); +void gp_clearFramebuffer16(unsigned short *framebuffer, unsigned short pal); +void gp_setCpuspeed(unsigned int cpuspeed); +void gp_initGraphics(unsigned short bpp, int flip, int applyMmuHack); +void gp_setFramebuffer(int flip, int sync); +int gp_initSound(int rate, int bits, int stereo, int Hz, int frag); +void gp_stopSound(void); +void gp_Reset(void); +void gp_sound_volume(int l, int r); +//unsigned long gp_timer_read(void); +#define gp_timer_read clock +unsigned int gp_getButton(unsigned char enable_diagnals); +void gp_video_RGB_setscaling(int W, int H); +void gp_video_RGB_setHZscaling(int W, int H); +void set_gamma(int g100); +void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD); + +extern volatile int SoundThreadFlag; +extern volatile int CurrentSoundBank; +extern int CurrentFrameBuffer; +extern volatile short *pOutput[]; +extern unsigned short *framebuffer16[]; +extern unsigned long wiz_physvram[]; +extern volatile unsigned short *wiz_memregs; +extern void *uppermem; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/cheats.cpp b/src/cheats.cpp new file mode 100644 index 0000000..966e0b9 --- /dev/null +++ b/src/cheats.cpp @@ -0,0 +1,391 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include +#include +#include +#include "snes9x.h" +#include "cheats.h" +#include "memmap.h" + +static bool8 S9xAllHex (const char *code, int len) +{ + for (int i = 0; i < len; i++) + if ((code [i] < '0' || code [i] > '9') && + (code [i] < 'a' || code [i] > 'f') && + (code [i] < 'A' || code [i] > 'F')) + return (FALSE); + + return (TRUE); +} + +const char *S9xProActionReplayToRaw (const char *code, uint32 &address, uint8 &byte) +{ + uint32 data = 0; + if (strlen (code) != 8 || !S9xAllHex (code, 8) || + sscanf (code, "%x", &data) != 1) + return ("Invalid Pro Action Replay code - should be 8 hex digits in length."); + + address = data >> 8; + byte = (uint8) data; + return (NULL); +} + +const char *S9xGoldFingerToRaw (const char *code, uint32 &address, bool8 &sram, + uint8 &num_bytes, uint8 bytes[3]) +{ + char tmp [15]; + if (strlen (code) != 14) + return ("Invalid Gold Finger code should be 14 hex digits in length."); + + strncpy (tmp, code, 5); + tmp [5] = 0; + if (sscanf (tmp, "%x", &address) != 1) + return ("Invalid Gold Finger code."); + + int i; + for (i = 0; i < 3; i++) + { + strncpy (tmp, code + 5 + i * 2, 2); + tmp [2] = 0; + int byte; + if (sscanf (tmp, "%x", &byte) != 1) + break; + bytes [i] = (uint8) byte; + } + num_bytes = i; + sram = code [13] == '1'; + return (NULL); +} + +const char *S9xGameGenieToRaw (const char *code, uint32 &address, uint8 &byte) +{ + char new_code [12]; + + if (strlen (code) != 9 || *(code + 4) != '-' || !S9xAllHex (code, 4) || + !S9xAllHex (code + 5, 4)) + return ("Invalid Game Genie(tm) code - should be 'xxxx-xxxx'."); + + strcpy (new_code, "0x"); + strncpy (new_code + 2, code, 4); + strcpy (new_code + 6, code + 5); + + static char *real_hex = "0123456789ABCDEF"; + static char *genie_hex = "DF4709156BC8A23E"; + + for (int i = 2; i < 10; i++) + { + if (islower (new_code [i])) + new_code [i] = toupper (new_code [i]); + int j; + for (j = 0; j < 16; j++) + { + if (new_code [i] == genie_hex [j]) + { + new_code [i] = real_hex [j]; + break; + } + } + if (j == 16) + return ("Invalid hex-character in Game Genie(tm) code"); + } + uint32 data = 0; + sscanf (new_code, "%x", &data); + byte = (uint8)(data >> 24); + address = data & 0xffffff; + address = ((address & 0x003c00) << 10) + + ((address & 0x00003c) << 14) + + ((address & 0xf00000) >> 8) + + ((address & 0x000003) << 10) + + ((address & 0x00c000) >> 6) + + ((address & 0x0f0000) >> 12) + + ((address & 0x0003c0) >> 6); + + return (NULL); +} + +void S9xStartCheatSearch (SCheatData *d) +{ + memmove (d->CWRAM, d->RAM, 0x20000); + memmove (d->CSRAM, d->SRAM, 0x10000); + memmove (d->CIRAM, &d->FillRAM [0x3000], 0x2000); + memset ((char *) d->WRAM_BITS, 0xff, 0x20000 >> 3); + memset ((char *) d->SRAM_BITS, 0xff, 0x10000 >> 3); + memset ((char *) d->IRAM_BITS, 0xff, 0x2000 >> 3); +} + +#define BIT_CLEAR(a,v) \ +(a)[(v) >> 5] &= ~(1 << ((v) & 31)) + +#define BIT_SET(a,v) \ +(a)[(v) >> 5] |= 1 << ((v) & 31) + +#define TEST_BIT(a,v) \ +((a)[(v) >> 5] & (1 << ((v) & 31))) + +#define _C(c,a,b) \ +((c) == S9X_LESS_THAN ? (a) < (b) : \ + (c) == S9X_GREATER_THAN ? (a) > (b) : \ + (c) == S9X_LESS_THAN_OR_EQUAL ? (a) <= (b) : \ + (c) == S9X_GREATER_THAN_OR_EQUAL ? (a) >= (b) : \ + (c) == S9X_EQUAL ? (a) == (b) : \ + (a) != (b)) + +#define _D(s,m,o) \ +((s) == S9X_8_BITS ? (uint8) (*((m) + (o))) : \ + (s) == S9X_16_BITS ? ((uint16) (*((m) + (o)) + (*((m) + (o) + 1) << 8))) : \ + (s) == S9X_24_BITS ? ((uint32) (*((m) + (o)) + (*((m) + (o) + 1) << 8) + (*((m) + (o) + 2) << 16))) : \ +((uint32) (*((m) + (o)) + (*((m) + (o) + 1) << 8) + (*((m) + (o) + 2) << 16) + (*((m) + (o) + 3) << 24)))) + +#define _DS(s,m,o) \ +((s) == S9X_8_BITS ? ((int8) *((m) + (o))) : \ + (s) == S9X_16_BITS ? ((int16) (*((m) + (o)) + (*((m) + (o) + 1) << 8))) : \ + (s) == S9X_24_BITS ? (((int32) ((*((m) + (o)) + (*((m) + (o) + 1) << 8) + (*((m) + (o) + 2) << 16)) << 8)) >> 8): \ + ((int32) (*((m) + (o)) + (*((m) + (o) + 1) << 8) + (*((m) + (o) + 2) << 16) + (*((m) + (o) + 3) << 24)))) + +void S9xSearchForChange (SCheatData *d, S9xCheatComparisonType cmp, + S9xCheatDataSize size, bool8 is_signed, bool8 update) +{ + int l; + + switch (size) + { + case S9X_8_BITS: l = 0; break; + case S9X_16_BITS: l = 1; break; + case S9X_24_BITS: l = 2; break; + default: + case S9X_32_BITS: l = 3; break; + } + + int i; + if (is_signed) + { + for (i = 0; i < 0x20000 - l; i++) + { + if (TEST_BIT (d->WRAM_BITS, i) && + _C(cmp, _DS(size, d->RAM, i), _DS(size, d->CWRAM, i))) + { + if (update) + d->CWRAM [i] = d->RAM [i]; + } + else + BIT_CLEAR (d->WRAM_BITS, i); + } + + for (i = 0; i < 0x10000 - l; i++) + { + if (TEST_BIT (d->SRAM_BITS, i) && + _C(cmp, _DS(size, d->SRAM, i), _DS(size, d->CSRAM, i))) + { + if (update) + d->CSRAM [i] = d->SRAM [i]; + } + else + BIT_CLEAR (d->SRAM_BITS, i); + } + + for (i = 0; i < 0x2000 - l; i++) + { + if (TEST_BIT (d->IRAM_BITS, i) && + _C(cmp, _DS(size, d->FillRAM + 0x3000, i), _DS(size, d->CIRAM, i))) + { + if (update) + d->CIRAM [i] = d->FillRAM [i + 0x3000]; + } + else + BIT_CLEAR (d->IRAM_BITS, i); + } + } + else + { + for (i = 0; i < 0x20000 - l; i++) + { + if (TEST_BIT (d->WRAM_BITS, i) && + _C(cmp, _D(size, d->RAM, i), _D(size, d->CWRAM, i))) + { + if (update) + d->CWRAM [i] = d->RAM [i]; + } + else + BIT_CLEAR (d->WRAM_BITS, i); + } + + for (i = 0; i < 0x10000 - l; i++) + { + if (TEST_BIT (d->SRAM_BITS, i) && + _C(cmp, _D(size, d->SRAM, i), _D(size, d->CSRAM, i))) + { + if (update) + d->CSRAM [i] = d->SRAM [i]; + } + else + BIT_CLEAR (d->SRAM_BITS, i); + } + + for (i = 0; i < 0x2000 - l; i++) + { + if (TEST_BIT (d->IRAM_BITS, i) && + _C(cmp, _D(size, d->FillRAM + 0x3000, i), _D(size, d->CIRAM, i))) + { + if (update) + d->CIRAM [i] = d->FillRAM [i + 0x3000]; + } + else + BIT_CLEAR (d->IRAM_BITS, i); + } + } +} + +void S9xSearchForValue (SCheatData *d, S9xCheatComparisonType cmp, + S9xCheatDataSize size, uint32 value, + bool8 is_signed, bool8 update) +{ + int l; + + switch (size) + { + case S9X_8_BITS: l = 0; break; + case S9X_16_BITS: l = 1; break; + case S9X_24_BITS: l = 2; break; + default: + case S9X_32_BITS: l = 3; break; + } + + int i; + + if (is_signed) + { + for (i = 0; i < 0x20000 - l; i++) + { + if (TEST_BIT (d->WRAM_BITS, i) && + _C(cmp, _DS(size, d->RAM, i), (int32) value)) + { + if (update) + d->CWRAM [i] = d->RAM [i]; + } + else + BIT_CLEAR (d->WRAM_BITS, i); + } + + for (i = 0; i < 0x10000 - l; i++) + { + if (TEST_BIT (d->SRAM_BITS, i) && + _C(cmp, _DS(size, d->SRAM, i), (int32) value)) + { + if (update) + d->CSRAM [i] = d->SRAM [i]; + } + else + BIT_CLEAR (d->SRAM_BITS, i); + } + + for (i = 0; i < 0x2000 - l; i++) + { + if (TEST_BIT (d->IRAM_BITS, i) && + _C(cmp, _DS(size, d->FillRAM + 0x3000, i), (int32) value)) + { + if (update) + d->CIRAM [i] = d->FillRAM [i + 0x3000]; + } + else + BIT_CLEAR (d->IRAM_BITS, i); + } + } + else + { + for (i = 0; i < 0x20000 - l; i++) + { + if (TEST_BIT (d->WRAM_BITS, i) && + _C(cmp, _D(size, d->RAM, i), value)) + { + if (update) + d->CWRAM [i] = d->RAM [i]; + } + else + BIT_CLEAR (d->WRAM_BITS, i); + } + + for (i = 0; i < 0x10000 - l; i++) + { + if (TEST_BIT (d->SRAM_BITS, i) && + _C(cmp, _D(size, d->SRAM, i), value)) + { + if (update) + d->CSRAM [i] = d->SRAM [i]; + } + else + BIT_CLEAR (d->SRAM_BITS, i); + } + + for (i = 0; i < 0x2000 - l; i++) + { + if (TEST_BIT (d->IRAM_BITS, i) && + _C(cmp, _D(size, d->FillRAM + 0x3000, i), value)) + { + if (update) + d->CIRAM [i] = d->FillRAM [i + 0x3000]; + } + else + BIT_CLEAR (d->IRAM_BITS, i); + } + } +} + +void S9xOutputCheatSearchResults (SCheatData *d) +{ + int i; + for (i = 0; i < 0x20000; i++) + { + if (TEST_BIT (d->WRAM_BITS, i)) + printf ("WRAM: %05x: %02x\n", i, d->RAM [i]); + } + + for (i = 0; i < 0x10000; i++) + { + if (TEST_BIT (d->SRAM_BITS, i)) + printf ("SRAM: %04x: %02x\n", i, d->SRAM [i]); + } + + for (i = 0; i < 0x2000; i++) + { + if (TEST_BIT (d->IRAM_BITS, i)) + printf ("IRAM: %05x: %02x\n", i, d->FillRAM [i + 0x3000]); + } +} diff --git a/src/cheats.h b/src/cheats.h new file mode 100644 index 0000000..0ac09ec --- /dev/null +++ b/src/cheats.h @@ -0,0 +1,109 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _CHEATS_H_ +#define _CHEATS_H_ + +struct SCheat +{ + uint32 address; + uint8 byte; + uint8 saved_byte; + bool8 enabled; + bool8 saved; + char name [22]; +}; + +#define MAX_CHEATS 75 + +struct SCheatData +{ + struct SCheat c [MAX_CHEATS]; + uint32 num_cheats; + uint8 CWRAM [0x20000]; + uint8 CSRAM [0x10000]; + uint8 CIRAM [0x2000]; + uint8 *RAM; + uint8 *FillRAM; + uint8 *SRAM; + uint32 WRAM_BITS [0x20000 >> 3]; + uint32 SRAM_BITS [0x10000 >> 3]; + uint32 IRAM_BITS [0x2000 >> 3]; +}; + +typedef enum +{ + S9X_LESS_THAN, S9X_GREATER_THAN, S9X_LESS_THAN_OR_EQUAL, + S9X_GREATER_THAN_OR_EQUAL, S9X_EQUAL, S9X_NOT_EQUAL +} S9xCheatComparisonType; + +typedef enum +{ + S9X_8_BITS, S9X_16_BITS, S9X_24_BITS, S9X_32_BITS +} S9xCheatDataSize; + +void S9xInitCheatData (); + +const char *S9xGameGenieToRaw (const char *code, uint32 &address, uint8 &byte); +const char *S9xProActionReplayToRaw (const char *code, uint32 &address, uint8 &byte); +const char *S9xGoldFingerToRaw (const char *code, uint32 &address, bool8 &sram, + uint8 &num_bytes, uint8 bytes[3]); +void S9xApplyCheats (); +void S9xApplyCheat (uint32 which1); +void S9xRemoveCheats (); +void S9xRemoveCheat (uint32 which1); +void S9xEnableCheat (uint32 which1); +void S9xDisableCheat (uint32 which1); +void S9xAddCheat (bool8 enable, bool8 save_current_value, uint32 address, + uint8 byte); +void S9xDeleteCheats (); +void S9xDeleteCheat (uint32 which1); +bool8 S9xLoadCheatFile (const char *filename); +bool8 S9xSaveCheatFile (const char *filename); + +void S9xStartCheatSearch (SCheatData *); +void S9xSearchForChange (SCheatData *, S9xCheatComparisonType cmp, + S9xCheatDataSize size, bool8 is_signed, bool8 update); +void S9xSearchForValue (SCheatData *, S9xCheatComparisonType cmp, + S9xCheatDataSize size, uint32 value, + bool8 is_signed, bool8 update); +void S9xOutputCheatSearchResults (SCheatData *); + +#endif diff --git a/src/cheats2.cpp b/src/cheats2.cpp new file mode 100644 index 0000000..1805a34 --- /dev/null +++ b/src/cheats2.cpp @@ -0,0 +1,232 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include +#include +#include +#include "snes9x.h" +#include "cheats.h" +#include "memmap.h" + +extern SCheatData Cheat; + +void S9xInitCheatData () +{ + Cheat.RAM = Memory.RAM; + Cheat.SRAM = ::SRAM; + Cheat.FillRAM = Memory.FillRAM; +} + +void S9xAddCheat (bool8 enable, bool8 save_current_value, + uint32 address, uint8 byte) +{ + if (Cheat.num_cheats < sizeof (Cheat.c) / sizeof (Cheat. c [0])) + { + Cheat.c [Cheat.num_cheats].address = address; + Cheat.c [Cheat.num_cheats].byte = byte; + Cheat.c [Cheat.num_cheats].enabled = TRUE; + if (save_current_value) + { + Cheat.c [Cheat.num_cheats].saved_byte = S9xGetByte (address); + Cheat.c [Cheat.num_cheats].saved = TRUE; + } + Cheat.num_cheats++; + } +} + +void S9xDeleteCheat (uint32 which1) +{ + if (which1 < Cheat.num_cheats) + { + if (Cheat.c [which1].enabled) + S9xRemoveCheat (which1); + + memmove (&Cheat.c [which1], &Cheat.c [which1 + 1], + sizeof (Cheat.c [0]) * (Cheat.num_cheats - which1 - 1)); + Cheat.num_cheats = 0; + } +} + +void S9xDeleteCheats () +{ + S9xRemoveCheats (); + Cheat.num_cheats = 0; +} + +void S9xEnableCheat (uint32 which1) +{ + if (which1 < Cheat.num_cheats && !Cheat.c [which1].enabled) + { + Cheat.c [which1].enabled = TRUE; + S9xApplyCheat (which1); + } +} + +void S9xDisableCheat (uint32 which1) +{ + if (which1 < Cheat.num_cheats && Cheat.c [which1].enabled) + { + S9xRemoveCheat (which1); + Cheat.c [which1].enabled = FALSE; + } +} + +void S9xRemoveCheat (uint32 which1) +{ + if (Cheat.c [which1].saved) + { + uint32 address = Cheat.c [which1].address; + + int block = (address >> MEMMAP_SHIFT) & MEMMAP_MASK; + uint8 *ptr = Memory.Map [block]; + + if (ptr >= (uint8 *) CMemory::MAP_LAST) + *(ptr + (address & 0xffff)) = Cheat.c [which1].saved_byte; + else + S9xSetByte (address, Cheat.c [which1].saved_byte); + } +} + +void S9xApplyCheat (uint32 which1) +{ + uint32 address = Cheat.c [which1].address; + + if (!Cheat.c [which1].saved) + Cheat.c [which1].saved_byte = S9xGetByte (address); + + int block = (address >> MEMMAP_SHIFT) & MEMMAP_MASK; + uint8 *ptr = Memory.Map [block]; + + if (ptr >= (uint8 *) CMemory::MAP_LAST) + *(ptr + (address & 0xffff)) = Cheat.c [which1].byte; + else + S9xSetByte (address, Cheat.c [which1].byte); + Cheat.c [which1].saved = TRUE; +} + +void S9xApplyCheats () +{ + if (Settings.ApplyCheats) + { + for (uint32 i = 0; i < Cheat.num_cheats; i++) + if (Cheat.c [i].enabled) + S9xApplyCheat (i); + } +} + +void S9xRemoveCheats () +{ + for (uint32 i = 0; i < Cheat.num_cheats; i++) + if (Cheat.c [i].enabled) + S9xRemoveCheat (i); +} + +bool8 S9xLoadCheatFile (const char *filename) +{ + Cheat.num_cheats = 0; + + FILE *fs = fopen (filename, "rb"); + uint8 data [28]; + + if (!fs) + return (FALSE); + + while (fread ((void *) data, 1, 28, fs) == 28) + { + Cheat.c [Cheat.num_cheats].enabled = (data [0] & 4) == 0; + Cheat.c [Cheat.num_cheats].byte = data [1]; + Cheat.c [Cheat.num_cheats].address = data [2] | (data [3] << 8) | (data [4] << 16); + Cheat.c [Cheat.num_cheats].saved_byte = data [5]; + Cheat.c [Cheat.num_cheats].saved = (data [0] & 8) != 0; + memmove (Cheat.c [Cheat.num_cheats].name, &data [8], 20); + Cheat.c [Cheat.num_cheats++].name [20] = 0; + } + fclose (fs); + + return (TRUE); +} + +bool8 S9xSaveCheatFile (const char *filename) +{ + if (Cheat.num_cheats == 0) + { +#ifndef _SNESPPC + (void) remove (filename); +#endif + return (TRUE); + } + + FILE *fs = fopen (filename, "wb"); + uint8 data [28]; + + if (!fs) + return (FALSE); + + uint32 i; + for (i = 0; i < Cheat.num_cheats; i++) + { + memset (data, 0, 28); + if (i == 0) + { + data [6] = 254; + data [7] = 252; + } + if (!Cheat.c [i].enabled) + data [0] |= 4; + + if (Cheat.c [i].saved) + data [0] |= 8; + + data [1] = Cheat.c [i].byte; + data [2] = (uint8) Cheat.c [i].address; + data [3] = (uint8) (Cheat.c [i].address >> 8); + data [4] = (uint8) (Cheat.c [i].address >> 16); + data [5] = Cheat.c [i].saved_byte; + + memmove (&data [8], Cheat.c [i].name, 19); + if (fwrite (data, 28, 1, fs) != 1) + { + fclose (fs); + return (FALSE); + } + } + return (fclose (fs) == 0); +} + diff --git a/src/clip.cpp b/src/clip.cpp new file mode 100644 index 0000000..faeb641 --- /dev/null +++ b/src/clip.cpp @@ -0,0 +1,739 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include + +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" + +struct Band +{ + uint32 Left; + uint32 Right; +}; + +#undef MIN +#undef MAX +#define MIN(A,B) ((A) < (B) ? (A) : (B)) +#define MAX(A,B) ((A) > (B) ? (A) : (B)) +#define BAND_EMPTY(B) (B.Left >= B.Right) +#define BANDS_INTERSECT(A,B) ((A.Left >= B.Left && A.Left < B.Right) || \ + (A.Right > B.Left && A.Right <= B.Right)) +#define OR_BANDS(R,A,B) {\ + R.Left = MIN(A.Left, B.Left); \ + R.Right = MAX(A.Right, B.Right);} + +#define AND_BANDS(R,A,B) {\ + R.Left = MAX(A.Left, B.Left); \ + R.Right = MIN(A.Right, B.Right);} + +#ifndef _SNESPPC +static int IntCompare (const void *d1, const void *d2) +#else +static int _cdecl IntCompare (const void *d1, const void *d2) +#endif +{ +/* + if (*(uint32 *) d1 > *(uint32 *) d2) + return (1); + else + if (*(uint32 *) d1 < *(uint32 *) d2) + return (-1); + return (0); +*/ + return (*(uint32 *) d1 - *(uint32 *) d2); +} + +#ifndef _SNESPPC +static int BandCompare (const void *d1, const void *d2) +#else +static int _cdecl BandCompare (const void *d1, const void *d2) +#endif +{ +/* + if (((struct Band *) d1)->Left > ((struct Band *) d2)->Left) + return (1); + else + if (((struct Band *) d1)->Left < ((struct Band *) d2)->Left) + return (-1); + return (0); +*/ + return (((struct Band *) d1)->Left - ((struct Band *) d2)->Left); +} + +void ComputeClipWindow(bool8_32 invert, int w, int wok, struct ClipData *pClip) { + pClip->Count[w] = 0; + + if (!Settings.DisableGraphicWindows) + { + if (pClip->Count [5] || wok) + { + struct Band Win1[3]; + struct Band Win2[3]; + uint32 Window1Enabled = 0; + uint32 Window2Enabled = 0; + if (wok) + { + if (PPU.ClipWindow1Enable [w]) + { + if (!PPU.ClipWindow1Inside [w]) + { + Win1[0].Left = PPU.Window1Left; + Win1[0].Right = PPU.Window1Right + 1; + Window1Enabled = 1; + } + else + { + if (PPU.Window1Left <= PPU.Window1Right) + { + if (PPU.Window1Left > 0) + { + Win1[0].Left = 0; + Win1[0].Right = PPU.Window1Left; + Window1Enabled = 1; + } + if (PPU.Window1Right < 255) + { + Win1[Window1Enabled].Left = PPU.Window1Right + 1; + Win1[Window1Enabled++].Right = 256; + } + if (Window1Enabled == 0) + { + Win1[0].Left = 1; + Win1[0].Right = 0; + Window1Enabled = 1; + } + } + else + { + // 'outside' a window with no range - + // appears to be the whole screen. + Win1[0].Left = 0; + Win1[0].Right = 256; + Window1Enabled = 1; + } + } + } + if (PPU.ClipWindow2Enable [w]) + { + if (!PPU.ClipWindow2Inside [w]) + { + Win2[0].Left = PPU.Window2Left; + Win2[0].Right = PPU.Window2Right + 1; + Window2Enabled = 1; + } + else + { + if (PPU.Window2Left <= PPU.Window2Right) + { + if (PPU.Window2Left > 0) + { + Win2[0].Left = 0; + Win2[0].Right = PPU.Window2Left; + Window2Enabled = 1; + } + if (PPU.Window2Right < 255) + { + Win2[Window2Enabled].Left = PPU.Window2Right + 1; + Win2[Window2Enabled++].Right = 256; + } + if (Window2Enabled == 0) + { + Win2[0].Left = 1; + Win2[0].Right = 0; + Window2Enabled = 1; + } + } + else + { + Win2[0].Left = 0; + Win2[0].Right = 256; + Window2Enabled = 1; + } + } + } + } + if (Window1Enabled && Window2Enabled) + { + // Overlap logic + // + // Each window will be in one of three states: + // 1. (Left > Right. One band) + // 2. | ---------------- | (Left >= 0, Right <= 255, Left <= Right. One band) + // 3. |------------ ----------| (Left1 == 0, Right1 < Left2; Left2 > Right1, Right2 == 255. Two bands) + + struct Band Bands [6]; + int B = 0; + switch (PPU.ClipWindowOverlapLogic [w] ^ 1) + { + case CLIP_OR: + if (Window1Enabled == 1) + { + if (BAND_EMPTY(Win1[0])) + { + B = Window2Enabled; + memmove (Bands, Win2, + sizeof(Win2[0]) * Window2Enabled); + } + else + { + if (Window2Enabled == 1) + { + if (BAND_EMPTY (Win2[0])) + Bands[B++] = Win1[0]; + else + { + if (BANDS_INTERSECT (Win1[0], Win2[0])) + { + OR_BANDS(Bands[0],Win1[0], Win2[0]) + B = 1; + } + else + { + Bands[B++] = Win1[0]; + Bands[B++] = Win2[0]; + } + } + } + else + { + if (BANDS_INTERSECT(Win1[0], Win2[0])) + { + OR_BANDS(Bands[0], Win1[0], Win2[0]) + if (BANDS_INTERSECT(Win1[0], Win2[1])) + OR_BANDS(Bands[1], Win1[0], Win2[1]) + else + Bands[1] = Win2[1]; + B = 1; + if (BANDS_INTERSECT(Bands[0], Bands[1])) + OR_BANDS(Bands[0], Bands[0], Bands[1]) + else + B = 2; + } + else + if (BANDS_INTERSECT(Win1[0], Win2[1])) + { + Bands[B++] = Win2[0]; + OR_BANDS(Bands[B], Win1[0], Win2[1]); + B++; + } + else + { + Bands[0] = Win2[0]; + Bands[1] = Win1[0]; + Bands[2] = Win2[1]; + B = 3; + } + } + } + } + else + if (Window2Enabled == 1) + { + if (BAND_EMPTY(Win2[0])) + { + // Window 2 defines an empty range - just + // use window 1 as the clipping (which + // could also be empty). + B = Window1Enabled; + memmove (Bands, Win1, + sizeof(Win1[0]) * Window1Enabled); + } + else + { + // Window 1 has two bands and Window 2 has one. + // Neither is an empty region. + if (BANDS_INTERSECT(Win2[0], Win1[0])) + { + OR_BANDS(Bands[0], Win2[0], Win1[0]) + if (BANDS_INTERSECT(Win2[0], Win1[1])) + OR_BANDS(Bands[1], Win2[0], Win1[1]) + else + Bands[1] = Win1[1]; + B = 1; + if (BANDS_INTERSECT(Bands[0], Bands[1])) + OR_BANDS(Bands[0], Bands[0], Bands[1]) + else + B = 2; + } + else + if (BANDS_INTERSECT(Win2[0], Win1[1])) + { + Bands[B++] = Win1[0]; + OR_BANDS(Bands[B], Win2[0], Win1[1]); + B++; + } + else + { + Bands[0] = Win1[0]; + Bands[1] = Win2[0]; + Bands[2] = Win1[1]; + B = 3; + } + } + } + else + { + // Both windows have two bands + OR_BANDS(Bands[0], Win1[0], Win2[0]); + OR_BANDS(Bands[1], Win1[1], Win2[1]); + B = 1; + if (BANDS_INTERSECT(Bands[0], Bands[1])) + OR_BANDS(Bands[0], Bands[0], Bands[1]) + else + B = 2; + } + break; + + case CLIP_AND: + if (Window1Enabled == 1) + { + // Window 1 has one band + if (BAND_EMPTY(Win1[0])) + Bands [B++] = Win1[0]; + else + if (Window2Enabled == 1) + { + if (BAND_EMPTY (Win2[0])) + Bands [B++] = Win2[0]; + else + { + AND_BANDS(Bands[0], Win1[0], Win2[0]); + B = 1; + } + } + else + { + AND_BANDS(Bands[0], Win1[0], Win2[0]); + AND_BANDS(Bands[1], Win1[0], Win2[1]); + B = 2; + } + } + else + if (Window2Enabled == 1) + { + if (BAND_EMPTY(Win2[0])) + Bands[B++] = Win2[0]; + else + { + // Window 1 has two bands. + AND_BANDS(Bands[0], Win1[0], Win2[0]); + AND_BANDS(Bands[1], Win1[1], Win2[0]); + B = 2; + } + } + else + { + // Both windows have two bands. + AND_BANDS(Bands[0], Win1[0], Win2[0]); + AND_BANDS(Bands[1], Win1[1], Win2[1]); + B = 2; + if (BANDS_INTERSECT(Win1[0], Win2[1])) + { + AND_BANDS(Bands[2], Win1[0], Win2[1]); + B = 3; + } + else + if (BANDS_INTERSECT(Win1[1], Win2[0])) + { + AND_BANDS(Bands[2], Win1[1], Win2[0]); + B = 3; + } + } + break; + case CLIP_XNOR: + invert = !invert; + // Fall... + + case CLIP_XOR: + if (Window1Enabled == 1 && BAND_EMPTY(Win1[0])) + { + B = Window2Enabled; + memmove (Bands, Win2, + sizeof(Win2[0]) * Window2Enabled); + } + else + if (Window2Enabled == 1 && BAND_EMPTY(Win2[0])) + { + B = Window1Enabled; + memmove (Bands, Win1, + sizeof(Win1[0]) * Window1Enabled); + } + else + { + uint32 p = 0; + uint32 points [10]; + uint32 i; + + invert = !invert; + // Build an array of points (window edges) + points [p++] = 0; + for (i = 0; i < Window1Enabled; i++) + { + points [p++] = Win1[i].Left; + points [p++] = Win1[i].Right; + } + for (i = 0; i < Window2Enabled; i++) + { + points [p++] = Win2[i].Left; + points [p++] = Win2[i].Right; + } + points [p++] = 256; + // Sort them + qsort ((void *) points, p, sizeof (points [0]), + IntCompare); + for (i = 0; i < p; i += 2) + { + if (points [i] == points [i + 1]) + continue; + Bands [B].Left = points [i]; + while (i + 2 < p && + points [i + 1] == points [i + 2]) + { + i += 2; + } + Bands [B++].Right = points [i + 1]; + } + } + break; + } + if (invert) + { + int b; + int j = 0; + int empty_band_count = 0; + + // First remove all empty bands from the list. + for (b = 0; b < B; b++) + { + if (!BAND_EMPTY(Bands[b])) + { + if (b != j) + Bands[j] = Bands[b]; + j++; + } + else + empty_band_count++; + } + + if (j > 0) + { + if (j == 1) + { + j = 0; + // Easy case to deal with, so special case it. + + if (Bands[0].Left > 0) + { + pClip->Left[j][w] = 0; + pClip->Right[j++][w] = Bands[0].Left + 1; + } + if (Bands[0].Right < 256) + { + pClip->Left[j][w] = Bands[0].Right; + pClip->Right[j++][w] = 256; + } + if (j == 0) + { + pClip->Left[j][w] = 1; + pClip->Right[j++][w] = 0; + } + } + else + { + // Now sort the bands into order + B = j; + qsort ((void *) Bands, B, + sizeof (Bands [0]), BandCompare); + + // Now invert the area the bands cover + j = 0; + for (b = 0; b < B; b++) + { + if (b == 0 && Bands[b].Left > 0) + { + pClip->Left[j][w] = 0; + pClip->Right[j++][w] = Bands[b].Left + 1; + } + else + if (b == B - 1 && Bands[b].Right < 256) + { + pClip->Left[j][w] = Bands[b].Right; + pClip->Right[j++][w] = 256; + } + if (b < B - 1) + { + pClip->Left[j][w] = Bands[b].Right; + pClip->Right[j++][w] = Bands[b + 1].Left + 1; + } + } + } + } + else + { + // Inverting a window that consisted of only + // empty bands is the whole width of the screen. + // Needed for Mario Kart's rear-view mirror display. + if (empty_band_count) + { + pClip->Left[j][w] = 0; + pClip->Right[j][w] = 256; + j++; + } + } + pClip->Count[w] = j; + } + else + { + for (int j = 0; j < B; j++) + { + pClip->Left[j][w] = Bands[j].Left; + pClip->Right[j][w] = Bands[j].Right; + } + pClip->Count [w] = B; + } + } + else + { + // Only one window enabled so no need to perform + // complex overlap logic... + + if (Window1Enabled) + { + if (invert) + { + int j = 0; + + if (Window1Enabled == 1) + { + if (Win1[0].Left <= Win1[0].Right) + { + if (Win1[0].Left > 0) + { + pClip->Left[0][w] = 0; + pClip->Right[0][w] = Win1[0].Left; + j = 1; + } + if (Win1[0].Right < 256) + { + pClip->Left[j][w] = Win1[0].Right; + pClip->Right[j++][w] = 256; + } + if (j == 0) + { + pClip->Left[0][w] = 1; + pClip->Right[0][w] = 0; + j = 1; + } + } + else + { + pClip->Left[0][w] = 0; + pClip->Right[0][w] = 256; + j = 1; + } + } + else + { + pClip->Left [0][w] = Win1[0].Right; + pClip->Right[0][w] = Win1[1].Left; + j = 1; + } + pClip->Count [w] = j; + } + else + { + for (uint32 j = 0; j < Window1Enabled; j++) + { + pClip->Left [j][w] = Win1[j].Left; + pClip->Right [j][w] = Win1[j].Right; + } + pClip->Count [w] = Window1Enabled; + } + } + else + if (Window2Enabled) + { + if (invert) + { + int j = 0; + if (Window2Enabled == 1) + { + if (Win2[0].Left <= Win2[0].Right) + { + if (Win2[0].Left > 0) + { + pClip->Left[0][w] = 0; + pClip->Right[0][w] = Win2[0].Left; + j = 1; + } + if (Win2[0].Right < 256) + { + pClip->Left[j][w] = Win2[0].Right; + pClip->Right[j++][w] = 256; + } + if (j == 0) + { + pClip->Left[0][w] = 1; + pClip->Right[0][w] = 0; + j = 1; + } + } + else + { + pClip->Left[0][w] = 0; + pClip->Right[0][w] = 256; + j = 1; + } + } + else + { + pClip->Left [0][w] = Win2[0].Right; + pClip->Right[0][w] = Win2[1].Left + 1; + j = 1; + } + pClip->Count [w] = j; + } + else + { + for (uint32 j = 0; j < Window2Enabled; j++) + { + pClip->Left [j][w] = Win2[j].Left; + pClip->Right [j][w] = Win2[j].Right; + } + pClip->Count [w] = Window2Enabled; + } + } + } + + if ((w != 5) && (pClip->Count [5])) + { + //if + //{ + // Colour window enabled. Set the + // clip windows for all remaining backgrounds to be + // the same as the colour window. + if (pClip->Count [w] == 0) + { + pClip->Count [w] = pClip->Count [5]; + for (int i = pClip->Count[w]-1; i >= 0 ; i--) + { + pClip->Left [i][w] = pClip->Left [i][5]; + pClip->Right [i][w] = pClip->Right [i][5]; + } + } + else + { + // Intersect the colour window with the bg's + // own clip window. + int i, j; + //for (i = 0; i < pClip->Count [w]; i++) + for (i = pClip->Count [w] - 1; i >= 0 ; i--) + { + //for (j = 0; j < pClip->Count [5]; j++) + for (j = pClip->Count [5] - 1; j >= 0 ; j--) + { + if((pClip->Left[i][w] >= pClip->Left[j][5] && pClip->Left[i][w] < pClip->Right[j][5]) || (pClip->Left[j][5] >= pClip->Left[i][w] && pClip->Left[j][5] < pClip->Right[i][w])){ + // Found an intersection! + pClip->Left[i][w]=MAX(pClip->Left[i][w], pClip->Left[j][5]); + pClip->Right[i][w]=MIN(pClip->Right[i][w], pClip->Right[j][5]); + goto Clip_ok; + } + } + // no intersection, nullify it + pClip->Left[i][w]=1; + pClip->Right[i][w]=0; +Clip_ok: + j=0; // dummy statement + } + } + //} + } + } // if (w == 5 | ... + } // if (!Settings.DisableGraphicWindows) +} + +void ComputeClipWindows () +{ + // Main screen + // - Colour window + if ((GFX.r2130_s & 0xc0) == 0xc0) { + // The whole of the main screen is switched off, + // completely clip everything. + for (int i = 0; i < 6; i++) { + IPPU.Clip [0].Count [i] = 1; + IPPU.Clip [0].Left [0][i] = 1; + IPPU.Clip [0].Right [0][i] = 0; + } + } + else if (GFX.r2130_s & 0xc0) ComputeClipWindow(((GFX.r2130_s & 0xc0) == 0x40), 5, 1, &IPPU.Clip [0]); + else IPPU.Clip[0].Count[5] = 0; + // - Objs + ComputeClipWindow(FALSE, 4, (GFX.r212c_s & GFX.r212e_s & (1 << 4)), &IPPU.Clip [0]); + // - Backgrounds + ComputeClipWindow(FALSE, 3, (GFX.r212c_s & GFX.r212e_s & (1 << 3)), &IPPU.Clip [0]); + ComputeClipWindow(FALSE, 2, (GFX.r212c_s & GFX.r212e_s & (1 << 2)), &IPPU.Clip [0]); + ComputeClipWindow(FALSE, 1, (GFX.r212c_s & GFX.r212e_s & (1 << 1)), &IPPU.Clip [0]); + ComputeClipWindow(FALSE, 0, (GFX.r212c_s & GFX.r212e_s & (1 << 0)), &IPPU.Clip [0]); + + // Sub screen + // - Colour window + if ((GFX.r2130_s & 0x30) == 0x30) { + // The sub-screen is switched off, completely + // clip everything. + for (int i = 0; i < 6; i++) { + IPPU.Clip [1].Count [i] = 1; + IPPU.Clip [1].Left [0][i] = 1; + IPPU.Clip [1].Right [0][i] = 0; + } + } + else if (GFX.r2130_s & 0x30) ComputeClipWindow(((GFX.r2130_s & 0x30) == 0x10), 5, 1, &IPPU.Clip [1]); + else IPPU.Clip[1].Count[5] = 0; + // - Objs + ComputeClipWindow(FALSE, 4, (GFX.r212d_s & GFX.r212f_s & (1 << 4)), &IPPU.Clip [1]); + // - Backgrounds + ComputeClipWindow(FALSE, 3, (GFX.r212d_s & GFX.r212f_s & (1 << 3)), &IPPU.Clip [1]); + ComputeClipWindow(FALSE, 2, (GFX.r212d_s & GFX.r212f_s & (1 << 2)), &IPPU.Clip [1]); + ComputeClipWindow(FALSE, 1, (GFX.r212d_s & GFX.r212f_s & (1 << 1)), &IPPU.Clip [1]); + ComputeClipWindow(FALSE, 0, (GFX.r212d_s & GFX.r212f_s & (1 << 0)), &IPPU.Clip [1]); + + PPU.RecomputeClipWindows = FALSE; +} diff --git a/src/clip.cpp.new b/src/clip.cpp.new new file mode 100644 index 0000000..8e6baa3 --- /dev/null +++ b/src/clip.cpp.new @@ -0,0 +1,405 @@ +/*********************************************************************************** + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com), + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2002 - 2004 Matthew Kendora + + (c) Copyright 2002 - 2005 Peter Bortas (peter@bortas.org) + + (c) Copyright 2004 - 2005 Joel Yliluoma (http://iki.fi/bisqwit/) + + (c) Copyright 2001 - 2006 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2006 funkyass (funkyass@spam.shaw.ca), + Kris Bleakley (codeviolation@hotmail.com) + + (c) Copyright 2002 - 2010 Brad Jorsch (anomie@users.sourceforge.net), + Nach (n-a-c-h@users.sourceforge.net), + zones (kasumitokoduck@yahoo.com) + + (c) Copyright 2006 - 2007 nitsuja + + (c) Copyright 2009 - 2010 BearOso, + OV2 + + + BS-X C emulator code + (c) Copyright 2005 - 2006 Dreamer Nom, + zones + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 _Demo_ (_demo_@zsnes.com), + Nach, + zsKnight (zsknight@zsnes.com) + + C4 C++ code + (c) Copyright 2003 - 2006 Brad Jorsch, + Nach + + DSP-1 emulator code + (c) Copyright 1998 - 2006 _Demo_, + Andreas Naive (andreasnaive@gmail.com), + Gary Henderson, + Ivar (ivar@snes9x.com), + John Weidman, + Kris Bleakley, + Matthew Kendora, + Nach, + neviksti (neviksti@hotmail.com) + + DSP-2 emulator code + (c) Copyright 2003 John Weidman, + Kris Bleakley, + Lord Nightmare (lord_nightmare@users.sourceforge.net), + Matthew Kendora, + neviksti + + DSP-3 emulator code + (c) Copyright 2003 - 2006 John Weidman, + Kris Bleakley, + Lancer, + z80 gaiden + + DSP-4 emulator code + (c) Copyright 2004 - 2006 Dreamer Nom, + John Weidman, + Kris Bleakley, + Nach, + z80 gaiden + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, + pagefault (pagefault@zsnes.com), + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code used in 1.39-1.51 + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, + John Weidman, + Dark Force + + SPC7110 and RTC C++ emulator code used in 1.52+ + (c) Copyright 2009 byuu, + neviksti + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive, + John Weidman + + S-RTC C emulator code + (c) Copyright 2001 - 2006 byuu, + John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, + John Weidman, + Kris Bleakley, + Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 _Demo_, + pagefault, + zsKnight + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, + Gary Henderson, + John Weidman + + Sound emulator code used in 1.5-1.51 + (c) Copyright 1998 - 2003 Brad Martin + (c) Copyright 1998 - 2006 Charles Bilyue' + + Sound emulator code used in 1.52+ + (c) Copyright 2004 - 2007 Shay Green (gblargg@gmail.com) + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + 2xSaI filter + (c) Copyright 1999 - 2001 Derek Liauw Kie Fa + + HQ2x, HQ3x, HQ4x filters + (c) Copyright 2003 Maxim Stepin (maxim@hiend3d.com) + + NTSC filter + (c) Copyright 2006 - 2007 Shay Green + + GTK+ GUI code + (c) Copyright 2004 - 2010 BearOso + + Win32 GUI code + (c) Copyright 2003 - 2006 blip, + funkyass, + Matthew Kendora, + Nach, + nitsuja + (c) Copyright 2009 - 2010 OV2 + + Mac OS GUI code + (c) Copyright 1998 - 2001 John Stiles + (c) Copyright 2001 - 2010 zones + + + Specific ports contains the works of other authors. See headers in + individual files. + + + Snes9x homepage: http://www.snes9x.com/ + + Permission to use, copy, modify and/or distribute Snes9x in both binary + and source form, for non-commercial purposes, is hereby granted without + fee, providing that this license information and copyright notice appear + with all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software or it's derivatives. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes, + but is not limited to, charging money for Snes9x or software derived from + Snes9x, including Snes9x or derivatives in commercial game bundles, and/or + using Snes9x as a promotion for your commercial product. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. + ***********************************************************************************/ + + +#include "snes9x.h" +#include "memmap.h" + +static uint8 region_map[6][6] = +{ + { 0, 0x01, 0x03, 0x07, 0x0f, 0x1f }, + { 0, 0, 0x02, 0x06, 0x0e, 0x1e }, + { 0, 0, 0, 0x04, 0x0c, 0x1c }, + { 0, 0, 0, 0, 0x08, 0x18 }, + { 0, 0, 0, 0, 0, 0x10 } +}; + +static inline uint8 CalcWindowMask (int, uint8, uint8); +static inline void StoreWindowRegions (uint8, struct ClipData *, int, int16 *, uint8 *, bool8, bool8 s = FALSE); + + +static inline uint8 CalcWindowMask (int i, uint8 W1, uint8 W2) +{ + if (!PPU.ClipWindow1Enable[i]) + { + if (!PPU.ClipWindow2Enable[i]) + return (0); + else + { + if (!PPU.ClipWindow2Inside[i]) + return (~W2); + return (W2); + } + } + else + { + if (!PPU.ClipWindow2Enable[i]) + { + if (!PPU.ClipWindow1Inside[i]) + return (~W1); + return (W1); + } + else + { + if (!PPU.ClipWindow1Inside[i]) + W1 = ~W1; + if (!PPU.ClipWindow2Inside[i]) + W2 = ~W2; + + switch (PPU.ClipWindowOverlapLogic[i]) + { + case 0: // OR + return (W1 | W2); + + case 1: // AND + return (W1 & W2); + + case 2: // XOR + return (W1 ^ W2); + + case 3: // XNOR + return (~(W1 ^ W2)); + } + } + } + + // Never get here + return (0); +} + +static inline void StoreWindowRegions (uint8 Mask, struct ClipData *Clip, int n_regions, int16 *windows, uint8 *drawing_modes, bool8 sub, bool8 StoreMode0) +{ + int ct = 0; + + for (int j = 0; j < n_regions; j++) + { + int DrawMode = drawing_modes[j]; + if (sub) + DrawMode |= 1; + if (Mask & (1 << j)) + DrawMode = 0; + + if (!StoreMode0 && !DrawMode) + continue; + + if (ct > 0 && Clip->Right[ct - 1] == windows[j] && Clip->DrawMode[ct - 1] == DrawMode) + Clip->Right[ct - 1] = windows[j + 1]; // This region borders with and has the same drawing mode as the previous region: merge them. + else + { + // Add a new region to the BG + Clip->Left[ct] = windows[j]; + Clip->Right[ct] = windows[j + 1]; + Clip->DrawMode[ct] = DrawMode; + ct++; + } + } + + Clip->Count = ct; +} + +void S9xComputeClipWindows (void) +{ + int16 windows[6] = { 0, 256, 256, 256, 256, 256 }; + uint8 drawing_modes[5] = { 0, 0, 0, 0, 0 }; + int n_regions = 1; + int i, j; + + // Calculate window regions. We have at most 5 regions, because we have 6 control points + // (screen edges, window 1 left & right, and window 2 left & right). + + if (PPU.Window1Left <= PPU.Window1Right) + { + if (PPU.Window1Left > 0) + { + windows[2] = 256; + windows[1] = PPU.Window1Left; + n_regions = 2; + } + + if (PPU.Window1Right < 255) + { + windows[n_regions + 1] = 256; + windows[n_regions] = PPU.Window1Right + 1; + n_regions++; + } + } + + if (PPU.Window2Left <= PPU.Window2Right) + { + for (i = 0; i <= n_regions; i++) + { + if (PPU.Window2Left == windows[i]) + break; + + if (PPU.Window2Left < windows[i]) + { + for (j = n_regions; j >= i; j--) + windows[j + 1] = windows[j]; + + windows[i] = PPU.Window2Left; + n_regions++; + break; + } + } + + for (; i <= n_regions; i++) + { + if (PPU.Window2Right + 1 == windows[i]) + break; + + if (PPU.Window2Right + 1 < windows[i]) + { + for (j = n_regions; j >= i; j--) + windows[j + 1] = windows[j]; + + windows[i] = PPU.Window2Right + 1; + n_regions++; + break; + } + } + } + + // Get a bitmap of which regions correspond to each window. + + uint8 W1, W2; + + if (PPU.Window1Left <= PPU.Window1Right) + { + for (i = 0; windows[i] != PPU.Window1Left; i++) ; + for (j = i; windows[j] != PPU.Window1Right + 1; j++) ; + W1 = region_map[i][j]; + } + else + W1 = 0; + + if (PPU.Window2Left <= PPU.Window2Right) + { + for (i = 0; windows[i] != PPU.Window2Left; i++) ; + for (j = i; windows[j] != PPU.Window2Right + 1; j++) ; + W2 = region_map[i][j]; + } + else + W2 = 0; + + // Color Window affects the drawing mode for each region. + // Modes are: 3=Draw as normal, 2=clip color (math only), 1=no math (draw only), 0=nothing. + + uint8 CW_color = 0, CW_math = 0; + uint8 CW = CalcWindowMask(5, W1, W2); + + switch (Memory.FillRAM[0x2130] & 0xc0) + { + case 0x00: CW_color = 0; break; + case 0x40: CW_color = ~CW; break; + case 0x80: CW_color = CW; break; + case 0xc0: CW_color = 0xff; break; + } + + switch (Memory.FillRAM[0x2130] & 0x30) + { + case 0x00: CW_math = 0; break; + case 0x10: CW_math = ~CW; break; + case 0x20: CW_math = CW; break; + case 0x30: CW_math = 0xff; break; + } + + for (i = 0; i < n_regions; i++) + { + if (!(CW_color & (1 << i))) + drawing_modes[i] |= 1; + if (!(CW_math & (1 << i))) + drawing_modes[i] |= 2; + } + + // Store backdrop clip window (draw everywhere color window allows) + + StoreWindowRegions(0, &IPPU.Clip[0][5], n_regions, windows, drawing_modes, FALSE, TRUE); + StoreWindowRegions(0, &IPPU.Clip[1][5], n_regions, windows, drawing_modes, TRUE, TRUE); + + // Store per-BG and OBJ clip windows + + for (j = 0; j < 5; j++) + { + uint8 W = Settings.DisableGraphicWindows ? 0 : CalcWindowMask(j, W1, W2); + for (int sub = 0; sub < 2; sub++) + { + if (Memory.FillRAM[sub + 0x212e] & (1 << j)) + StoreWindowRegions(W, &IPPU.Clip[sub][j], n_regions, windows, drawing_modes, sub); + else + StoreWindowRegions(0, &IPPU.Clip[sub][j], n_regions, windows, drawing_modes, sub); + } + } +} diff --git a/src/compile.txt b/src/compile.txt new file mode 100644 index 0000000..b71265f --- /dev/null +++ b/src/compile.txt @@ -0,0 +1,27 @@ +To compile just do: +------------------ + +make + +will compile for Gp2x, Wiz and Caanoo + +To compile just for a platform: +------------------------------ + +make target + +where target can be: gp2x, wiz or caanoo this will compile both fast and compatible binaries + +To compile just a binary (fast or compatible) for just a platform: +----------------------------------------------------------------- + +make target(c|f) + +c for Compatible binary +f for Fast binary + +for example: + +make wizf + + diff --git a/src/config.c b/src/config.c new file mode 100644 index 0000000..174ef58 --- /dev/null +++ b/src/config.c @@ -0,0 +1,39 @@ +#include +#include "minIni.h" +#include "menu.h" +#include "port.h" +#include "config.h" + +static char *cfgEntry_lastLoaded = "last_loaded"; +static char *cfgEntry_theme = "theme"; +static char *cfgFile = "config.ini"; +static char *cfgSection_general = "general"; + +void getConfigValue(unsigned int value, char *buffer, int bfsz) { + char fp_cfgFile[_MAX_PATH]; + sprintf(fp_cfgFile, "%s/%s", snesOptionsDir, cfgFile); + + switch(value) { + case CONFIG_LASTLOADED: + ini_gets(cfgSection_general, cfgEntry_lastLoaded, "\0", buffer, bfsz, fp_cfgFile); + break; + case CONFIG_THEME: + ini_gets(cfgSection_general, cfgEntry_theme, "default", buffer, bfsz, fp_cfgFile); + break; + } +} + +void setConfigValue(unsigned int value, char *ll) { + char fp_cfgFile[_MAX_PATH]; + sprintf(fp_cfgFile, "%s/%s", snesOptionsDir, cfgFile); + + switch(value) { + case CONFIG_LASTLOADED: + ini_puts(cfgSection_general, cfgEntry_lastLoaded, ll, fp_cfgFile); + break; + case CONFIG_THEME: + ini_puts(cfgSection_general, cfgEntry_theme, ll, fp_cfgFile); + break; + } +} + diff --git a/src/config.h b/src/config.h new file mode 100644 index 0000000..e41a308 --- /dev/null +++ b/src/config.h @@ -0,0 +1,18 @@ +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define CONFIG_LASTLOADED 0 +#define CONFIG_THEME 1 + +void getConfigValue(unsigned int value, char *buffer, int bfsz); +void setConfigValue(unsigned int value, char *ll); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/copyright.h b/src/copyright.h new file mode 100644 index 0000000..7e02c4c --- /dev/null +++ b/src/copyright.h @@ -0,0 +1,70 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996, 1997, 1998, 1999 Gary Henderson (gary@daniver.demon.co.uk) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code (c) Copyright 1997, 1998 Ivar and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ diff --git a/src/cpu.cpp b/src/cpu.cpp new file mode 100644 index 0000000..621b6f0 --- /dev/null +++ b/src/cpu.cpp @@ -0,0 +1,170 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "dsp1.h" +#include "cpuexec.h" +#include "debug.h" +#include "apu.h" +#include "dma.h" +#ifdef USE_SA1 +#include "sa1.h" +#endif +//#include "cheats.h" +#include "srtc.h" +#include "sdd1.h" +//#include "spc7110.h" + +#include "soundux.h" + +#ifdef SUPER_FX +#include "fxemu.h" + +extern struct FxInit_s SuperFX; + +void S9xResetSuperFX () +{ + SuperFX.vFlags = 0; //FX_FLAG_ROM_BUFFER;// | FX_FLAG_ADDRESS_CHECKING; + FxReset (&SuperFX); +} +#endif + +void S9xResetCPU () +{ + Registers.PB = 0; + Registers.PC = S9xGetWord (0xFFFC); + Registers.D.W = 0; + Registers.DB = 0; + Registers.SH = 1; + Registers.SL = 0xFF; + Registers.XH = 0; + Registers.YH = 0; + Registers.P.W = 0; + + ICPU.ShiftedPB = 0; + ICPU.ShiftedDB = 0; + SetFlags (MemoryFlag | IndexFlag | IRQ | Emulation); + ClearFlags (Decimal); + + CPU.Flags = CPU.Flags & (DEBUG_MODE_FLAG | TRACE_FLAG); + CPU.BranchSkip = FALSE; + CPU.NMIActive = FALSE; + CPU.IRQActive = FALSE; + CPU.WaitingForInterrupt = FALSE; + CPU.InDMA = FALSE; + CPU.WhichEvent = HBLANK_START_EVENT; + + CPU.PC = NULL; + CPU.PCBase = NULL; + CPU.PCAtOpcodeStart = NULL; + CPU.WaitAddress = NULL; + CPU.WaitCounter = 0; + CPU.Cycles = 0; + CPU.NextEvent = Settings.HBlankStart; + CPU.V_Counter = 0; + CPU.MemSpeed = SLOW_ONE_CYCLE; + CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; + CPU.FastROMSpeed = SLOW_ONE_CYCLE; + CPU.AutoSaveTimer = 0; + CPU.SRAMModified = FALSE; + // CPU.NMITriggerPoint = 4; // Set when ROM image loaded + CPU.BRKTriggered = FALSE; + //CPU.TriedInterleavedMode2 = FALSE; // Reset when ROM image loaded + CPU.NMICycleCount = 0; + CPU.IRQCycleCount = 0; + S9xSetPCBase (Registers.PC); + +#ifndef ASMCPU +#ifndef VAR_CYCLES + ICPU.Speed = S9xE1M1X1; +#endif + ICPU.S9xOpcodes = S9xOpcodesM1X1; + S9xUnpackStatus(); +#endif + + ICPU.CPUExecuting = TRUE; +} + + +void S9xReset (void) +{ +#ifdef SUPER_FX + if (Settings.SuperFX) + S9xResetSuperFX (); +#endif + + ZeroMemory (Memory.FillRAM, 0x8000); + memset (Memory.VRAM, 0x00, 0x10000); + memset (Memory.RAM, 0x55, 0x20000); + +/* if(Settings.SPC7110) + S9xSpc7110Reset();*/ + S9xResetCPU (); + S9xResetPPU (); + S9xResetSRTC (); + if (Settings.SDD1) + S9xResetSDD1 (); + + S9xResetDMA (); + S9xResetAPU (); + S9xResetDSP1 (); +#ifdef USE_SA1 + S9xSA1Init (); +#endif + + if (Settings.C4) + S9xInitC4 (); + + S9xResetSound(1); + + Settings.Paused = FALSE; + + //Init CPU Map & co + CPU.Memory_Map=(uint8*)&(Memory.Map); + CPU.Memory_WriteMap=(uint8*)&(Memory.WriteMap); + CPU.Memory_MemorySpeed=Memory.MemorySpeed; + CPU.Memory_BlockIsRAM=(uint8*)&(Memory.BlockIsRAM); + CPU.Memory_SRAM=Memory.SRAM; + CPU.Memory_BWRAM=Memory.BWRAM; +// CPU.Memory_SRAMMask=Memory.SRAMMask; + +} diff --git a/src/cpuaddr.h b/src/cpuaddr.h new file mode 100644 index 0000000..1fc5640 --- /dev/null +++ b/src/cpuaddr.h @@ -0,0 +1,325 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#ifdef CPUASM +#define _CPUADDR_H_ +#endif + +#ifndef _CPUADDR_H_ +#define _CPUADDR_H_ + +EXTERN_C long OpAddress; + +STATIC inline void Immediate8 () +{ + OpAddress = ICPU.ShiftedPB + CPU.PC - CPU.PCBase; + CPU.PC++; +} + +STATIC inline void Immediate16 () +{ + OpAddress = ICPU.ShiftedPB + CPU.PC - CPU.PCBase; + CPU.PC += 2; +} + +STATIC inline void Relative () +{ + signed char s9xInt8 = *CPU.PC++; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + OpAddress = ((int) (CPU.PC - CPU.PCBase) + s9xInt8) & 0xffff; +} + +STATIC inline void RelativeLong () +{ +#ifdef FAST_LSB_WORD_ACCESS + OpAddress = *(uint16 *) CPU.PC; +#else + OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8); +#endif +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2 + ONE_CYCLE; +#endif + CPU.PC += 2; + OpAddress += (CPU.PC - CPU.PCBase); + OpAddress &= 0xffff; +} + +STATIC inline void AbsoluteIndexedIndirect () +{ +#ifdef FAST_LSB_WORD_ACCESS + OpAddress = (Registers.X.W + *(uint16 *) CPU.PC) & 0xffff; +#else + OpAddress = (Registers.X.W + *CPU.PC + (*(CPU.PC + 1) << 8)) & 0xffff; +#endif +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + CPU.PC += 2; + OpAddress = S9xGetWord (ICPU.ShiftedPB + OpAddress); +} + +STATIC inline void AbsoluteIndirectLong () +{ +#ifdef FAST_LSB_WORD_ACCESS + OpAddress = *(uint16 *) CPU.PC; +#else + OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8); +#endif + +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + CPU.PC += 2; + OpAddress = S9xGetWord (OpAddress) | (S9xGetByte (OpAddress + 2) << 16); +} + +STATIC inline void AbsoluteIndirect () +{ +#ifdef FAST_LSB_WORD_ACCESS + OpAddress = *(uint16 *) CPU.PC; +#else + OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8); +#endif + +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + CPU.PC += 2; + OpAddress = S9xGetWord (OpAddress) + ICPU.ShiftedPB; +} + +STATIC inline void Absolute () +{ +#ifdef FAST_LSB_WORD_ACCESS + OpAddress = *(uint16 *) CPU.PC + ICPU.ShiftedDB; +#else + OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8) + ICPU.ShiftedDB; +#endif + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif +} + +STATIC inline void AbsoluteLong () +{ +#ifdef FAST_LSB_WORD_ACCESS + OpAddress = (*(uint32 *) CPU.PC) & 0xffffff; +#else + OpAddress = *CPU.PC + (*(CPU.PC + 1) << 8) + (*(CPU.PC + 2) << 16); +#endif + CPU.PC += 3; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2 + CPU.MemSpeed; +#endif +} + +STATIC inline void Direct( void) +{ + OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif +// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE; +} + +STATIC inline void DirectIndirectIndexed () +{ + OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + + OpAddress = ICPU.ShiftedDB + S9xGetWord (OpAddress) + Registers.Y.W; + +// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE; + // XXX: always add one if STA + // XXX: else Add one cycle if crosses page boundary +} + +STATIC inline void DirectIndirectIndexedLong () +{ + OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + + OpAddress = S9xGetWord (OpAddress) + (S9xGetByte (OpAddress + 2) << 16) + + Registers.Y.W; +// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE; +} + +STATIC inline void DirectIndexedIndirect( void) +{ + OpAddress = (*CPU.PC++ + Registers.D.W + Registers.X.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + + OpAddress = S9xGetWord (OpAddress) + ICPU.ShiftedDB; + +#ifdef VAR_CYCLES +// if (Registers.DL != 0) +// CPU.Cycles += TWO_CYCLES; +// else + CPU.Cycles += ONE_CYCLE; +#endif +} + +STATIC inline void DirectIndexedX () +{ + OpAddress = (*CPU.PC++ + Registers.D.W + Registers.X.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + +#ifdef VAR_CYCLES +// if (Registers.DL != 0) +// CPU.Cycles += TWO_CYCLES; +// else + CPU.Cycles += ONE_CYCLE; +#endif +} + +STATIC inline void DirectIndexedY () +{ + OpAddress = (*CPU.PC++ + Registers.D.W + Registers.Y.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + +#ifdef VAR_CYCLES +// if (Registers.DL != 0) +// CPU.Cycles += TWO_CYCLES; +// else + CPU.Cycles += ONE_CYCLE; +#endif +} + +STATIC inline void AbsoluteIndexedX () +{ +#ifdef FAST_LSB_WORD_ACCESS + OpAddress = ICPU.ShiftedDB + *(uint16 *) CPU.PC + Registers.X.W; +#else + OpAddress = ICPU.ShiftedDB + *CPU.PC + (*(CPU.PC + 1) << 8) + + Registers.X.W; +#endif + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + // XXX: always add one cycle for ROL, LSR, etc + // XXX: else is cross page boundary add one cycle +} + +STATIC inline void AbsoluteIndexedY () +{ +#ifdef FAST_LSB_WORD_ACCESS + OpAddress = ICPU.ShiftedDB + *(uint16 *) CPU.PC + Registers.Y.W; +#else + OpAddress = ICPU.ShiftedDB + *CPU.PC + (*(CPU.PC + 1) << 8) + + Registers.Y.W; +#endif + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + // XXX: always add cycle for STA + // XXX: else is cross page boundary add one cycle +} + +STATIC inline void AbsoluteLongIndexedX () +{ +#ifdef FAST_LSB_WORD_ACCESS + OpAddress = (*(uint32 *) CPU.PC + Registers.X.W) & 0xffffff; +#else + OpAddress = (*CPU.PC + (*(CPU.PC + 1) << 8) + (*(CPU.PC + 2) << 16) + Registers.X.W) & 0xffffff; +#endif + CPU.PC += 3; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2 + CPU.MemSpeed; +#endif +} + +STATIC inline void DirectIndirect () +{ + OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + OpAddress = S9xGetWord (OpAddress) + ICPU.ShiftedDB; + +// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE; +} + +STATIC inline void DirectIndirectLong () +{ + OpAddress = (*CPU.PC++ + Registers.D.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + OpAddress = S9xGetWord (OpAddress) + + (S9xGetByte (OpAddress + 2) << 16); +// if (Registers.DL != 0) CPU.Cycles += ONE_CYCLE; +} + +STATIC inline void StackRelative () +{ + OpAddress = (*CPU.PC++ + Registers.S.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; + CPU.Cycles += ONE_CYCLE; +#endif +} + +STATIC inline void StackRelativeIndirectIndexed () +{ + OpAddress = (*CPU.PC++ + Registers.S.W) & 0xffff; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; + CPU.Cycles += TWO_CYCLES; +#endif + OpAddress = (S9xGetWord (OpAddress) + ICPU.ShiftedDB + + Registers.Y.W) & 0xffffff; +} +#endif diff --git a/src/cpuexec.cpp b/src/cpuexec.cpp new file mode 100644 index 0000000..7865e18 --- /dev/null +++ b/src/cpuexec.cpp @@ -0,0 +1,542 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + + + +#include "snes9x.h" + +#include "memmap.h" +#include "cpuops.h" +#include "ppu.h" +#include "cpuexec.h" +#include "debug.h" +#include "snapshot.h" +#include "gfx.h" +#include "missing.h" +#include "apu.h" +#include "dma.h" +#include "fxemu.h" +#ifdef USE_SA1 +#include "sa1.h" +#endif + +#include "os9x_asm_cpu.h" + + +void (*S9x_Current_HBlank_Event)(); + + +#ifndef ASMCPU + #ifdef USE_SA1 +void S9xMainLoop_SA1_APU (void) +{ + for (;;) + { + asm_APU_EXECUTE(1); + if (CPU.Flags) + { + if (CPU.Flags & NMI_FLAG) + { + if (--CPU.NMICycleCount == 0) + { + CPU.Flags &= ~NMI_FLAG; + if (CPU.WaitingForInterrupt) + { + CPU.WaitingForInterrupt = FALSE; + ++CPU.PC; + } + S9xOpcode_NMI (); + } + } + + if (CPU.Flags & IRQ_PENDING_FLAG) + { + if (CPU.IRQCycleCount == 0) + { + if (CPU.WaitingForInterrupt) + { + CPU.WaitingForInterrupt = FALSE; + CPU.PC++; + } + if (CPU.IRQActive && !Settings.DisableIRQ) + { + if (!CheckFlag (IRQ)) + S9xOpcode_IRQ (); + } + else + CPU.Flags &= ~IRQ_PENDING_FLAG; + } + else + CPU.IRQCycleCount--; + } + if (CPU.Flags & SCAN_KEYS_FLAG) + break; + } + +#ifdef CPU_SHUTDOWN + CPU.PCAtOpcodeStart = CPU.PC; +#endif +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#else + CPU.Cycles += ICPU.Speed [*CPU.PC]; +#endif + (*ICPU.S9xOpcodes[*CPU.PC++].S9xOpcode) (); + + + //S9xUpdateAPUTimer (); + + + if (SA1.Executing) + S9xSA1MainLoop (); + DO_HBLANK_CHECK (); + + } +} + +void S9xMainLoop_SA1_NoAPU (void) +{ + for (;;) + { + if (CPU.Flags) + { + if (CPU.Flags & NMI_FLAG) + { + if (--CPU.NMICycleCount == 0) + { + CPU.Flags &= ~NMI_FLAG; + if (CPU.WaitingForInterrupt) + { + CPU.WaitingForInterrupt = FALSE; + ++CPU.PC; + } + S9xOpcode_NMI (); + } + } + + if (CPU.Flags & IRQ_PENDING_FLAG) + { + if (CPU.IRQCycleCount == 0) + { + if (CPU.WaitingForInterrupt) + { + CPU.WaitingForInterrupt = FALSE; + CPU.PC++; + } + if (CPU.IRQActive && !Settings.DisableIRQ) + { + if (!CheckFlag (IRQ)) + S9xOpcode_IRQ (); + } + else + CPU.Flags &= ~IRQ_PENDING_FLAG; + } + else + CPU.IRQCycleCount--; + } + if (CPU.Flags & SCAN_KEYS_FLAG) + break; + } + +#ifdef CPU_SHUTDOWN + CPU.PCAtOpcodeStart = CPU.PC; +#endif +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#else + CPU.Cycles += ICPU.Speed [*CPU.PC]; +#endif + (*ICPU.S9xOpcodes[*CPU.PC++].S9xOpcode) (); + + + //S9xUpdateAPUTimer (); + + + if (SA1.Executing) + S9xSA1MainLoop (); + DO_HBLANK_CHECK (); + + } +} + // USE_SA1 + #endif + +void S9xMainLoop_NoSA1_APU (void) +{ + for (;;) + { + asm_APU_EXECUTE(1); + if (CPU.Flags) + { + if (CPU.Flags & NMI_FLAG) + { + if (--CPU.NMICycleCount == 0) + { + CPU.Flags &= ~NMI_FLAG; + if (CPU.WaitingForInterrupt) + { + CPU.WaitingForInterrupt = FALSE; + ++CPU.PC; + } + S9xOpcode_NMI (); + } + } + + if (CPU.Flags & IRQ_PENDING_FLAG) + { + if (CPU.IRQCycleCount == 0) + { + if (CPU.WaitingForInterrupt) + { + CPU.WaitingForInterrupt = FALSE; + CPU.PC++; + } + if (CPU.IRQActive && !Settings.DisableIRQ) + { + if (!CheckFlag (IRQ)) + S9xOpcode_IRQ (); + } + else + CPU.Flags &= ~IRQ_PENDING_FLAG; + } + else + CPU.IRQCycleCount--; + } + if (CPU.Flags & SCAN_KEYS_FLAG) + break; + } + +#ifdef CPU_SHUTDOWN + CPU.PCAtOpcodeStart = CPU.PC; +#endif +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#else + CPU.Cycles += ICPU.Speed [*CPU.PC]; +#endif + (*ICPU.S9xOpcodes[*CPU.PC++].S9xOpcode) (); + + + //S9xUpdateAPUTimer (); + + DO_HBLANK_CHECK (); + } +} + +void S9xMainLoop_NoSA1_NoAPU (void) +{ + for (;;) + { + if (CPU.Flags) + { + if (CPU.Flags & NMI_FLAG) + { + if (--CPU.NMICycleCount == 0) + { + CPU.Flags &= ~NMI_FLAG; + if (CPU.WaitingForInterrupt) + { + CPU.WaitingForInterrupt = FALSE; + ++CPU.PC; + } + S9xOpcode_NMI (); + } + } + + if (CPU.Flags & IRQ_PENDING_FLAG) + { + if (CPU.IRQCycleCount == 0) + { + if (CPU.WaitingForInterrupt) + { + CPU.WaitingForInterrupt = FALSE; + CPU.PC++; + } + if (CPU.IRQActive && !Settings.DisableIRQ) + { + if (!CheckFlag (IRQ)) + S9xOpcode_IRQ (); + } + else + CPU.Flags &= ~IRQ_PENDING_FLAG; + } + else + CPU.IRQCycleCount--; + } + if (CPU.Flags & SCAN_KEYS_FLAG) + break; + } + +#ifdef CPU_SHUTDOWN + CPU.PCAtOpcodeStart = CPU.PC; +#endif +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#else + CPU.Cycles += ICPU.Speed [*CPU.PC]; +#endif + (*ICPU.S9xOpcodes[*CPU.PC++].S9xOpcode) (); + + + //S9xUpdateAPUTimer (); + + + DO_HBLANK_CHECK (); + + } +} +#endif + + +void +S9xMainLoop (void) +{ +#ifndef ASMCPU + if (Settings.APUEnabled == 1) { + #ifdef USE_SA1 + if (Settings.SA1) S9xMainLoop_SA1_APU(); + else + #endif + S9xMainLoop_NoSA1_APU(); + } else { + #ifdef USE_SA1 + if (Settings.SA1) S9xMainLoop_SA1_NoAPU(); + else S9xMainLoop_NoSA1_NoAPU(); + #endif + + } +#else + if (Settings.asmspc700) asmMainLoop_spcAsm(&CPU); + else asmMainLoop_spcC(&CPU); +#endif + Registers.PC = CPU.PC - CPU.PCBase; + +#ifndef ASMCPU + S9xPackStatus (); +#endif + + S9xAPUPackStatus (); + + + //if (CPU.Flags & SCAN_KEYS_FLAG) + // { + CPU.Flags &= ~SCAN_KEYS_FLAG; + //} + + if (CPU.BRKTriggered && Settings.SuperFX && !CPU.TriedInterleavedMode2) + { + CPU.TriedInterleavedMode2 = TRUE; + CPU.BRKTriggered = FALSE; + S9xDeinterleaveMode2 (); + } +} + +void S9xSetIRQ (uint32 source) +{ + CPU.IRQActive |= source; + CPU.Flags |= IRQ_PENDING_FLAG; + CPU.IRQCycleCount = 3; + if (CPU.WaitingForInterrupt) + { + // Force IRQ to trigger immediately after WAI - + // Final Fantasy Mystic Quest crashes without this. + CPU.IRQCycleCount = 0; + CPU.WaitingForInterrupt = FALSE; + CPU.PC++; + } +} + +void S9xClearIRQ (uint32 source) +{ + CLEAR_IRQ_SOURCE (source); +} + +void S9xDoHBlankProcessing () +{ +#ifdef CPU_SHUTDOWN + CPU.WaitCounter++; +#endif + + switch (CPU.WhichEvent) + { + case HBLANK_START_EVENT: + if (IPPU.HDMA && CPU.V_Counter <= PPU.ScreenHeight) + IPPU.HDMA = S9xDoHDMA (IPPU.HDMA); + break; + + case HBLANK_END_EVENT: + asm_APU_EXECUTE(3); // notaz: run spc700 in sound 'speed hack' mode + if(Settings.SuperFX) + S9xSuperFXExec (); + + CPU.Cycles -= Settings.H_Max; + if (/*IAPU.APUExecuting*/CPU.APU_APUExecuting) + CPU.APU_Cycles -= Settings.H_Max; + else + CPU.APU_Cycles = 0; + + CPU.NextEvent = -1; + ICPU.Scanline++; + + if (++CPU.V_Counter >= (Settings.PAL ? SNES_MAX_PAL_VCOUNTER : SNES_MAX_NTSC_VCOUNTER)) + { + CPU.V_Counter = 0; + CPU.NMIActive = FALSE; + ICPU.Frame++; + PPU.HVBeamCounterLatched = 0; + CPU.Flags |= SCAN_KEYS_FLAG; + S9xStartHDMA (); + } + + if (PPU.VTimerEnabled && !PPU.HTimerEnabled && + CPU.V_Counter == PPU.IRQVBeamPos) + { + S9xSetIRQ (PPU_V_BEAM_IRQ_SOURCE); + } + + if (CPU.V_Counter == PPU.ScreenHeight + FIRST_VISIBLE_LINE) + { + // Start of V-blank + S9xEndScreenRefresh (); + IPPU.HDMA = 0; + // Bits 7 and 6 of $4212 are computed when read in S9xGetPPU. + missing.dma_this_frame = 0; + IPPU.MaxBrightness = PPU.Brightness; + PPU.ForcedBlanking = (Memory.FillRAM [0x2100] >> 7) & 1; + + if(!PPU.ForcedBlanking){ + PPU.OAMAddr = PPU.SavedOAMAddr; + PPU.OAMFlip = 0; + PPU.FirstSprite = 0; + if(PPU.OAMPriorityRotation) + PPU.FirstSprite = PPU.OAMAddr>>1; + } + + Memory.FillRAM[0x4210] = 0x80; + if (Memory.FillRAM[0x4200] & 0x80) + { + CPU.NMIActive = TRUE; + CPU.Flags |= NMI_FLAG; + CPU.NMICycleCount = CPU.NMITriggerPoint; + } + + } + + if (CPU.V_Counter == PPU.ScreenHeight + 3) + S9xUpdateJoypads (); + + if (CPU.V_Counter == FIRST_VISIBLE_LINE) + { + Memory.FillRAM[0x4210] = 0; + CPU.Flags &= ~NMI_FLAG; + S9xStartScreenRefresh (); + } + if (CPU.V_Counter >= FIRST_VISIBLE_LINE && + CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) + { + RenderLine (CPU.V_Counter - FIRST_VISIBLE_LINE); + } + // Use TimerErrorCounter to skip update of SPC700 timers once + // every 128 updates. Needed because this section of code is called + // once every emulated 63.5 microseconds, which coresponds to + // 15.750KHz, but the SPC700 timers need to be updated at multiples + // of 8KHz, hence the error correction. + // IAPU.TimerErrorCounter++; + // if (IAPU.TimerErrorCounter >= ) + // IAPU.TimerErrorCounter = 0; + // else + { + if (APU.TimerEnabled [2]) + { + APU.Timer [2] += 4; + while (APU.Timer [2] >= APU.TimerTarget [2]) + { + IAPU.RAM [0xff] = (IAPU.RAM [0xff] + 1) & 0xf; + APU.Timer [2] -= APU.TimerTarget [2]; +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; + /*IAPU.APUExecuting*/CPU.APU_APUExecuting= TRUE; +#endif + } + } + if (CPU.V_Counter & 1) + { + if (APU.TimerEnabled [0]) + { + APU.Timer [0]++; + if (APU.Timer [0] >= APU.TimerTarget [0]) + { + IAPU.RAM [0xfd] = (IAPU.RAM [0xfd] + 1) & 0xf; + APU.Timer [0] = 0; +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; + /*IAPU.APUExecuting*/CPU.APU_APUExecuting = TRUE; +#endif + } + } + if (APU.TimerEnabled [1]) + { + APU.Timer [1]++; + if (APU.Timer [1] >= APU.TimerTarget [1]) + { + IAPU.RAM [0xfe] = (IAPU.RAM [0xfe] + 1) & 0xf; + APU.Timer [1] = 0; +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; + /*IAPU.APUExecuting*/CPU.APU_APUExecuting = TRUE; +#endif + } + } + } + } + break; + case HTIMER_BEFORE_EVENT: + case HTIMER_AFTER_EVENT: + if (PPU.HTimerEnabled && + (!PPU.VTimerEnabled || CPU.V_Counter == PPU.IRQVBeamPos)) + { + S9xSetIRQ (PPU_H_BEAM_IRQ_SOURCE); + } + break; + } + S9xReschedule (); +} + diff --git a/src/cpuexec.h b/src/cpuexec.h new file mode 100644 index 0000000..649d0ec --- /dev/null +++ b/src/cpuexec.h @@ -0,0 +1,235 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _CPUEXEC_H_ +#define _CPUEXEC_H_ +#include "ppu.h" +#include "memmap.h" +#include "65c816.h" + +#define DO_HBLANK_CHECK() \ + if (CPU.Cycles >= CPU.NextEvent) \ + S9xDoHBlankProcessing (); + +struct SOpcodes { +#ifdef __WIN32__ + void (__cdecl *S9xOpcode)( void); +#else + void (*S9xOpcode)( void); +#endif +}; + +struct SICPU +{ + uint8 *Speed; + struct SOpcodes *S9xOpcodes; + uint8 _Carry; + uint8 _Zero; + uint8 _Negative; + uint8 _Overflow; + bool8 CPUExecuting; + uint32 ShiftedPB; + uint32 ShiftedDB; + uint32 Frame; + uint32 Scanline; + uint32 FrameAdvanceCount; +}; + +START_EXTERN_C +void S9xMainLoop (void); +void S9xReset (void); +void S9xDoHBlankProcessing (); +void S9xClearIRQ (uint32); +void S9xSetIRQ (uint32); + +extern struct SOpcodes S9xOpcodesM1X1 [256]; +extern struct SOpcodes S9xOpcodesM1X0 [256]; +extern struct SOpcodes S9xOpcodesM0X1 [256]; +extern struct SOpcodes S9xOpcodesM0X0 [256]; + +#ifndef VAR_CYCLES +extern uint8 S9xE1M1X1 [256]; +extern uint8 S9xE0M1X0 [256]; +extern uint8 S9xE0M1X1 [256]; +extern uint8 S9xE0M0X0 [256]; +extern uint8 S9xE0M0X1 [256]; +#endif + +extern struct SICPU ICPU; +END_EXTERN_C + +STATIC inline void CLEAR_IRQ_SOURCE (uint32 M) +{ + CPU.IRQActive &= ~M; + if (!CPU.IRQActive) + CPU.Flags &= ~IRQ_PENDING_FLAG; +} + +STATIC inline void S9xUnpackStatus() +{ + ICPU._Zero = (Registers.PL & Zero) == 0; + ICPU._Negative = (Registers.PL & Negative); + ICPU._Carry = (Registers.PL & Carry); + ICPU._Overflow = (Registers.PL & Overflow) >> 6; +} + +STATIC inline void S9xPackStatus() +{ + Registers.PL &= ~(Zero | Negative | Carry | Overflow); + Registers.PL |= ICPU._Carry | ((ICPU._Zero == 0) << 1) | + (ICPU._Negative & 0x80) | (ICPU._Overflow << 6); +} + +STATIC inline void S9xFixCycles () +{ + if (CheckEmulation ()) + { +#ifndef VAR_CYCLES + ICPU.Speed = S9xE1M1X1; +#endif + ICPU.S9xOpcodes = S9xOpcodesM1X1; + } + else + if (CheckMemory ()) + { + if (CheckIndex ()) + { +#ifndef VAR_CYCLES + ICPU.Speed = S9xE0M1X1; +#endif + ICPU.S9xOpcodes = S9xOpcodesM1X1; + } + else + { +#ifndef VAR_CYCLES + ICPU.Speed = S9xE0M1X0; +#endif + ICPU.S9xOpcodes = S9xOpcodesM1X0; + } + } + else + { + if (CheckIndex ()) + { +#ifndef VAR_CYCLES + ICPU.Speed = S9xE0M0X1; +#endif + ICPU.S9xOpcodes = S9xOpcodesM0X1; + } + else + { +#ifndef VAR_CYCLES + ICPU.Speed = S9xE0M0X0; +#endif + ICPU.S9xOpcodes = S9xOpcodesM0X0; + } + } +} + + +#define S9xReschedule() { \ + uint8 which; \ + long max; \ + if (CPU.WhichEvent == HBLANK_START_EVENT || CPU.WhichEvent == HTIMER_AFTER_EVENT) { \ + which = HBLANK_END_EVENT; \ + max = Settings.H_Max; \ + } else { \ + which = HBLANK_START_EVENT; \ + max = Settings.HBlankStart; \ + } \ + \ + if (PPU.HTimerEnabled && (long) PPU.HTimerPosition < max && (long) PPU.HTimerPosition > CPU.NextEvent && \ + (!PPU.VTimerEnabled || (PPU.VTimerEnabled && CPU.V_Counter == PPU.IRQVBeamPos))) { \ + which = (long) PPU.HTimerPosition < Settings.HBlankStart ? HTIMER_BEFORE_EVENT : HTIMER_AFTER_EVENT; \ + max = PPU.HTimerPosition; \ + } \ + CPU.NextEvent = max; \ + CPU.WhichEvent = which; \ +} + +/* +extern "C" { +void asm_APU_EXECUTE(int Mode); +void asm_APU_EXECUTE2(void); +}*/ + +#define asm_APU_EXECUTE(MODE)\ +{\ + if (CPU.APU_APUExecuting == MODE) {\ + if (Settings.asmspc700) {\ + if(CPU.APU_Cycles < CPU.Cycles) {\ + int cycles = CPU.Cycles - CPU.APU_Cycles;\ + CPU.APU_Cycles += cycles - spc700_execute(cycles);\ + }\ + }\ + else\ + {\ + while (CPU.APU_Cycles <= CPU.Cycles)\ + {\ + CPU.APU_Cycles += S9xAPUCycles [*IAPU.PC];\ + (*S9xApuOpcodes[*IAPU.PC]) ();\ + }\ + }\ + }\ +} + + +#define asm_APU_EXECUTE2() \ +{\ + if (CPU.APU_APUExecuting == 1) {\ + if (Settings.asmspc700) {\ + if (CPU.APU_Cycles < CPU.NextEvent) {\ + int cycles = CPU.NextEvent - CPU.APU_Cycles;\ + CPU.APU_Cycles += cycles - spc700_execute(cycles);\ + }\ + }\ + else\ + {\ + do\ + {\ + CPU.APU_Cycles += S9xAPUCycles [*IAPU.PC];\ + (*S9xApuOpcodes[*IAPU.PC]) ();\ + } while (CPU.APU_Cycles < CPU.NextEvent);\ + }\ + }\ +} + + +#endif diff --git a/src/cpumacro.h b/src/cpumacro.h new file mode 100644 index 0000000..d4866f1 --- /dev/null +++ b/src/cpumacro.h @@ -0,0 +1,820 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _CPUMACRO_H_ +#define _CPUMACRO_H_ + +STATIC inline void SetZN16 (uint16 Work) +{ + ICPU._Zero = Work != 0; + ICPU._Negative = (uint8) (Work >> 8); +} + +STATIC inline void SetZN8 (uint8 Work) +{ + ICPU._Zero = Work; + ICPU._Negative = Work; +} + +STATIC inline void ADC8 () +{ + uint8 Work8 = S9xGetByte (OpAddress); + + if (CheckDecimal ()) + { + uint8 A1 = (Registers.A.W) & 0xF; + uint8 A2 = (Registers.A.W >> 4) & 0xF; + uint8 W1 = Work8 & 0xF; + uint8 W2 = (Work8 >> 4) & 0xF; + + A1 += W1 + CheckCarry(); + if (A1 > 9) + { + A1 -= 10; + A2++; + } + + A2 += W2; + if (A2 > 9) + { + A2 -= 10; + SetCarry (); + } + else + { + ClearCarry (); + } + + uint8 Ans8 = (A2 << 4) | A1; + if (~(Registers.AL ^ Work8) & + (Work8 ^ Ans8) & 0x80) + SetOverflow(); + else + ClearOverflow(); + Registers.AL = Ans8; + SetZN8 (Registers.AL); + } + else + { + uint16 Ans16 = Registers.AL + Work8 + CheckCarry(); + + ICPU._Carry = Ans16 >= 0x100; + + if (~(Registers.AL ^ Work8) & + (Work8 ^ (uint8) Ans16) & 0x80) + SetOverflow(); + else + ClearOverflow(); + Registers.AL = (uint8) Ans16; + SetZN8 (Registers.AL); + + } +} + +STATIC inline void ADC16 () +{ + uint16 Work16 = S9xGetWord (OpAddress); + + if (CheckDecimal ()) + { + uint8 A1 = (Registers.A.W) & 0xF; + uint8 A2 = (Registers.A.W >> 4) & 0xF; + uint8 A3 = (Registers.A.W >> 8) & 0xF; + uint8 A4 = (Registers.A.W >> 12) & 0xF; + uint8 W1 = Work16 & 0xF; + uint8 W2 = (Work16 >> 4) & 0xF; + uint8 W3 = (Work16 >> 8) & 0xF; + uint8 W4 = (Work16 >> 12) & 0xF; + + A1 += W1 + CheckCarry (); + if (A1 > 9) + { + A1 -= 10; + A2++; + } + + A2 += W2; + if (A2 > 9) + { + A2 -= 10; + A3++; + } + + A3 += W3; + if (A3 > 9) + { + A3 -= 10; + A4++; + } + + A4 += W4; + if (A4 > 9) + { + A4 -= 10; + SetCarry (); + } + else + { + ClearCarry (); + } + + uint16 Ans16 = (A4 << 12) | (A3 << 8) | (A2 << 4) | (A1); + if (~(Registers.A.W ^ Work16) & + (Work16 ^ Ans16) & 0x8000) + SetOverflow(); + else + ClearOverflow(); + Registers.A.W = Ans16; + SetZN16 (Registers.A.W); + } + else + { + uint32 Ans32 = Registers.A.W + Work16 + CheckCarry(); + + ICPU._Carry = Ans32 >= 0x10000; + + if (~(Registers.A.W ^ Work16) & + (Work16 ^ (uint16) Ans32) & 0x8000) + SetOverflow(); + else + ClearOverflow(); + Registers.A.W = (uint16) Ans32; + SetZN16 (Registers.A.W); + } +} + +STATIC inline void AND16 () +{ + Registers.A.W &= S9xGetWord (OpAddress); + SetZN16 (Registers.A.W); +} + +STATIC inline void AND8 () +{ + Registers.AL &= S9xGetByte (OpAddress); + SetZN8 (Registers.AL); +} + +STATIC inline void A_ASL16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + ICPU._Carry = (Registers.AH & 0x80) != 0; + Registers.A.W <<= 1; + SetZN16 (Registers.A.W); +} + +STATIC inline void A_ASL8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + ICPU._Carry = (Registers.AL & 0x80) != 0; + Registers.AL <<= 1; + SetZN8 (Registers.AL); +} + +STATIC inline void ASL16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint16 Work16 = S9xGetWord (OpAddress); + ICPU._Carry = (Work16 & 0x8000) != 0; + Work16 <<= 1; + S9xSetWord (Work16, OpAddress); + SetZN16 (Work16); +} + +STATIC inline void ASL8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint8 Work8 = S9xGetByte (OpAddress); + ICPU._Carry = (Work8 & 0x80) != 0; + Work8 <<= 1; + S9xSetByte (Work8, OpAddress); + SetZN8 (Work8); +} + +STATIC inline void BIT16 () +{ + uint16 Work16 = S9xGetWord (OpAddress); + ICPU._Overflow = (Work16 & 0x4000) != 0; + ICPU._Negative = (uint8) (Work16 >> 8); + ICPU._Zero = (Work16 & Registers.A.W) != 0; +} + +STATIC inline void BIT8 () +{ + uint8 Work8 = S9xGetByte (OpAddress); + ICPU._Overflow = (Work8 & 0x40) != 0; + ICPU._Negative = Work8; + ICPU._Zero = Work8 & Registers.AL; +} + +STATIC inline void CMP16 () +{ + long s9xInt32 = (long) Registers.A.W - + (long) S9xGetWord (OpAddress); + ICPU._Carry = s9xInt32 >= 0; + SetZN16 ((uint16) s9xInt32); +} + +STATIC inline void CMP8 () +{ + short s9xInt16 = (short) Registers.AL - + (short) S9xGetByte (OpAddress); + ICPU._Carry = s9xInt16 >= 0; + SetZN8 ((uint8) s9xInt16); +} + +STATIC inline void CMX16 () +{ + long s9xInt32 = (long) Registers.X.W - + (long) S9xGetWord (OpAddress); + ICPU._Carry = s9xInt32 >= 0; + SetZN16 ((uint16) s9xInt32); +} + +STATIC inline void CMX8 () +{ + short s9xInt16 = (short) Registers.XL - + (short) S9xGetByte (OpAddress); + ICPU._Carry = s9xInt16 >= 0; + SetZN8 ((uint8) s9xInt16); +} + +STATIC inline void CMY16 () +{ + long s9xInt32 = (long) Registers.Y.W - + (long) S9xGetWord (OpAddress); + ICPU._Carry = s9xInt32 >= 0; + SetZN16 ((uint16) s9xInt32); +} + +STATIC inline void CMY8 () +{ + short s9xInt16 = (short) Registers.YL - + (short) S9xGetByte (OpAddress); + ICPU._Carry = s9xInt16 >= 0; + SetZN8 ((uint8) s9xInt16); +} + +STATIC inline void A_DEC16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.A.W--; + SetZN16 (Registers.A.W); +} + +STATIC inline void A_DEC8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.AL--; + SetZN8 (Registers.AL); +} + +STATIC inline void DEC16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + uint16 Work16 = S9xGetWord (OpAddress) - 1; + S9xSetWord (Work16, OpAddress); + SetZN16 (Work16); +} + +STATIC inline void DEC8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + uint8 Work8 = S9xGetByte (OpAddress) - 1; + S9xSetByte (Work8, OpAddress); + SetZN8 (Work8); +} + +STATIC inline void EOR16 () +{ + Registers.A.W ^= S9xGetWord (OpAddress); + SetZN16 (Registers.A.W); +} + +STATIC inline void EOR8 () +{ + Registers.AL ^= S9xGetByte (OpAddress); + SetZN8 (Registers.AL); +} + +STATIC inline void A_INC16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.A.W++; + SetZN16 (Registers.A.W); +} + +STATIC inline void A_INC8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.AL++; + SetZN8 (Registers.AL); +} + +STATIC inline void INC16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + uint16 Work16 = S9xGetWord (OpAddress) + 1; + S9xSetWord (Work16, OpAddress); + SetZN16 (Work16); +} + +STATIC inline void INC8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + uint8 Work8 = S9xGetByte (OpAddress) + 1; + S9xSetByte (Work8, OpAddress); + SetZN8 (Work8); +} + +STATIC inline void LDA16 () +{ + Registers.A.W = S9xGetWord (OpAddress); + SetZN16 (Registers.A.W); +} + +STATIC inline void LDA8 () +{ + Registers.AL = S9xGetByte (OpAddress); + SetZN8 (Registers.AL); +} + +STATIC inline void LDX16 () +{ + Registers.X.W = S9xGetWord (OpAddress); + SetZN16 (Registers.X.W); +} + +STATIC inline void LDX8 () +{ + Registers.XL = S9xGetByte (OpAddress); + SetZN8 (Registers.XL); +} + +STATIC inline void LDY16 () +{ + Registers.Y.W = S9xGetWord (OpAddress); + SetZN16 (Registers.Y.W); +} + +STATIC inline void LDY8 () +{ + Registers.YL = S9xGetByte (OpAddress); + SetZN8 (Registers.YL); +} + +STATIC inline void A_LSR16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + ICPU._Carry = Registers.AL & 1; + Registers.A.W >>= 1; + SetZN16 (Registers.A.W); +} + +STATIC inline void A_LSR8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + ICPU._Carry = Registers.AL & 1; + Registers.AL >>= 1; + SetZN8 (Registers.AL); +} + +STATIC inline void LSR16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint16 Work16 = S9xGetWord (OpAddress); + ICPU._Carry = Work16 & 1; + Work16 >>= 1; + S9xSetWord (Work16, OpAddress); + SetZN16 (Work16); +} + +STATIC inline void LSR8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint8 Work8 = S9xGetByte (OpAddress); + ICPU._Carry = Work8 & 1; + Work8 >>= 1; + S9xSetByte (Work8, OpAddress); + SetZN8 (Work8); +} + +STATIC inline void ORA16 () +{ + Registers.A.W |= S9xGetWord (OpAddress); + SetZN16 (Registers.A.W); +} + +STATIC inline void ORA8 () +{ + Registers.AL |= S9xGetByte (OpAddress); + SetZN8 (Registers.AL); +} + +STATIC inline void A_ROL16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint32 Work32 = (Registers.A.W << 1) | CheckCarry(); + ICPU._Carry = Work32 >= 0x10000; + Registers.A.W = (uint16) Work32; + SetZN16 ((uint16) Work32); +} + +STATIC inline void A_ROL8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint16 Work16 = Registers.AL; + Work16 <<= 1; + Work16 |= CheckCarry(); + ICPU._Carry = Work16 >= 0x100; + Registers.AL = (uint8) Work16; + SetZN8 ((uint8) Work16); +} + +STATIC inline void ROL16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint32 Work32 = S9xGetWord (OpAddress); + Work32 <<= 1; + Work32 |= CheckCarry(); + ICPU._Carry = Work32 >= 0x10000; + S9xSetWord ((uint16) Work32, OpAddress); + SetZN16 ((uint16) Work32); +} + +STATIC inline void ROL8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint16 Work16 = S9xGetByte (OpAddress); + Work16 <<= 1; + Work16 |= CheckCarry (); + ICPU._Carry = Work16 >= 0x100; + S9xSetByte ((uint8) Work16, OpAddress); + SetZN8 ((uint8) Work16); +} + +STATIC inline void A_ROR16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint32 Work32 = Registers.A.W; + Work32 |= (int) CheckCarry() << 16; + ICPU._Carry = (uint8) (Work32 & 1); + Work32 >>= 1; + Registers.A.W = (uint16) Work32; + SetZN16 ((uint16) Work32); +} + +STATIC inline void A_ROR8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint16 Work16 = Registers.AL | ((uint16) CheckCarry() << 8); + ICPU._Carry = (uint8) Work16 & 1; + Work16 >>= 1; + Registers.AL = (uint8) Work16; + SetZN8 ((uint8) Work16); +} + +STATIC inline void ROR16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint32 Work32 = S9xGetWord (OpAddress); + Work32 |= (int) CheckCarry() << 16; + ICPU._Carry = (uint8) (Work32 & 1); + Work32 >>= 1; + S9xSetWord ((uint16) Work32, OpAddress); + SetZN16 ((uint16) Work32); +} + +STATIC inline void ROR8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint16 Work16 = S9xGetByte (OpAddress); + Work16 |= (int) CheckCarry () << 8; + ICPU._Carry = (uint8) (Work16 & 1); + Work16 >>= 1; + S9xSetByte ((uint8) Work16, OpAddress); + SetZN8 ((uint8) Work16); +} + +STATIC inline void SBC16 () +{ + uint16 Work16 = S9xGetWord (OpAddress); + + if (CheckDecimal ()) + { + uint8 A1 = (Registers.A.W) & 0xF; + uint8 A2 = (Registers.A.W >> 4) & 0xF; + uint8 A3 = (Registers.A.W >> 8) & 0xF; + uint8 A4 = (Registers.A.W >> 12) & 0xF; + uint8 W1 = Work16 & 0xF; + uint8 W2 = (Work16 >> 4) & 0xF; + uint8 W3 = (Work16 >> 8) & 0xF; + uint8 W4 = (Work16 >> 12) & 0xF; + + A1 -= W1 + !CheckCarry (); + A2 -= W2; + A3 -= W3; + A4 -= W4; + if (A1 > 9) + { + A1 += 10; + A2--; + } + if (A2 > 9) + { + A2 += 10; + A3--; + } + if (A3 > 9) + { + A3 += 10; + A4--; + } + if (A4 > 9) + { + A4 += 10; + ClearCarry (); + } + else + { + SetCarry (); + } + + uint16 Ans16 = (A4 << 12) | (A3 << 8) | (A2 << 4) | (A1); + if ((Registers.A.W ^ Work16) & + (Registers.A.W ^ Ans16) & 0x8000) + SetOverflow(); + else + ClearOverflow(); + Registers.A.W = Ans16; + SetZN16 (Registers.A.W); + } + else + { + + long s9xInt32 = (long) Registers.A.W - (long) Work16 + (long) CheckCarry() - 1; + + ICPU._Carry = s9xInt32 >= 0; + + if ((Registers.A.W ^ Work16) & + (Registers.A.W ^ (uint16) s9xInt32) & 0x8000) + SetOverflow(); + else + ClearOverflow (); + Registers.A.W = (uint16) s9xInt32; + SetZN16 (Registers.A.W); + } +} + +STATIC inline void SBC8 () +{ + uint8 Work8 = S9xGetByte (OpAddress); + if (CheckDecimal ()) + { + uint8 A1 = (Registers.A.W) & 0xF; + uint8 A2 = (Registers.A.W >> 4) & 0xF; + uint8 W1 = Work8 & 0xF; + uint8 W2 = (Work8 >> 4) & 0xF; + + A1 -= W1 + !CheckCarry (); + A2 -= W2; + if (A1 > 9) + { + A1 += 10; + A2--; + } + if (A2 > 9) + { + A2 += 10; + ClearCarry (); + } + else + { + SetCarry (); + } + + uint8 Ans8 = (A2 << 4) | A1; + if ((Registers.AL ^ Work8) & + (Registers.AL ^ Ans8) & 0x80) + SetOverflow (); + else + ClearOverflow (); + Registers.AL = Ans8; + SetZN8 (Registers.AL); + } + else + { + short s9xInt16 = (short) Registers.AL - (short) Work8 + (short) CheckCarry() - 1; + + ICPU._Carry = s9xInt16 >= 0; + if ((Registers.AL ^ Work8) & + (Registers.AL ^ (uint8) s9xInt16) & 0x80) + SetOverflow (); + else + ClearOverflow (); + Registers.AL = (uint8) s9xInt16; + SetZN8 (Registers.AL); + } +} + +STATIC inline void STA16 () +{ + S9xSetWord (Registers.A.W, OpAddress); +} + +STATIC inline void STA8 () +{ + S9xSetByte (Registers.AL, OpAddress); +} + +STATIC inline void STX16 () +{ + S9xSetWord (Registers.X.W, OpAddress); +} + +STATIC inline void STX8 () +{ + S9xSetByte (Registers.XL, OpAddress); +} + +STATIC inline void STY16 () +{ + S9xSetWord (Registers.Y.W, OpAddress); +} + +STATIC inline void STY8 () +{ + S9xSetByte (Registers.YL, OpAddress); +} + +STATIC inline void STZ16 () +{ + S9xSetWord (0, OpAddress); +} + +STATIC inline void STZ8 () +{ + S9xSetByte (0, OpAddress); +} + +STATIC inline void TSB16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint16 Work16 = S9xGetWord (OpAddress); + ICPU._Zero = (Work16 & Registers.A.W) != 0; + Work16 |= Registers.A.W; + S9xSetWord (Work16, OpAddress); +} + +STATIC inline void TSB8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint8 Work8 = S9xGetByte (OpAddress); + ICPU._Zero = Work8 & Registers.AL; + Work8 |= Registers.AL; + S9xSetByte (Work8, OpAddress); +} + +STATIC inline void TRB16 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint16 Work16 = S9xGetWord (OpAddress); + ICPU._Zero = (Work16 & Registers.A.W) != 0; + Work16 &= ~Registers.A.W; + S9xSetWord (Work16, OpAddress); +} + +STATIC inline void TRB8 () +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + uint8 Work8 = S9xGetByte (OpAddress); + ICPU._Zero = Work8 & Registers.AL; + Work8 &= ~Registers.AL; + S9xSetByte (Work8, OpAddress); +} +#endif diff --git a/src/cpuops.cpp b/src/cpuops.cpp new file mode 100644 index 0000000..993087e --- /dev/null +++ b/src/cpuops.cpp @@ -0,0 +1,4265 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +/**********************************************************************************************/ +/* CPU-S9xOpcodes.CPP */ +/* This file contains all the opcodes */ +/**********************************************************************************************/ + +#include "snes9x.h" +#include "memmap.h" +#include "debug.h" +#include "missing.h" +#include "apu.h" +#include "sa1.h" +//#include "spc7110.h" + +#include "cpuexec.h" +#include "cpuaddr.h" +#include "cpuops.h" +#include "cpumacro.h" +#include "apu.h" + +/* ADC *************************************************************************************** */ +static void Op69M1 (void) +{ + Immediate8 (); + ADC8 (); +} + +static void Op69M0 (void) +{ + Immediate16 (); + ADC16 (); +} + +static void Op65M1 (void) +{ + Direct (); + ADC8 (); +} + +static void Op65M0 (void) +{ + Direct (); + ADC16 (); +} + +static void Op75M1 (void) +{ + DirectIndexedX (); + ADC8 (); +} + +static void Op75M0 (void) +{ + DirectIndexedX (); + ADC16 (); +} + +static void Op72M1 (void) +{ + DirectIndirect (); + ADC8 (); +} + +static void Op72M0 (void) +{ + DirectIndirect (); + ADC16 (); +} + +static void Op61M1 (void) +{ + DirectIndexedIndirect (); + ADC8 (); +} + +static void Op61M0 (void) +{ + DirectIndexedIndirect (); + ADC16 (); +} + +static void Op71M1 (void) +{ + DirectIndirectIndexed (); + ADC8 (); +} + +static void Op71M0 (void) +{ + DirectIndirectIndexed (); + ADC16 (); +} + +static void Op67M1 (void) +{ + DirectIndirectLong (); + ADC8 (); +} + +static void Op67M0 (void) +{ + DirectIndirectLong (); + ADC16 (); +} + +static void Op77M1 (void) +{ + DirectIndirectIndexedLong (); + ADC8 (); +} + +static void Op77M0 (void) +{ + DirectIndirectIndexedLong (); + ADC16 (); +} + +static void Op6DM1 (void) +{ + Absolute (); + ADC8 (); +} + +static void Op6DM0 (void) +{ + Absolute (); + ADC16 (); +} + +static void Op7DM1 (void) +{ + AbsoluteIndexedX (); + ADC8 (); +} + +static void Op7DM0 (void) +{ + AbsoluteIndexedX (); + ADC16 (); +} + +static void Op79M1 (void) +{ + AbsoluteIndexedY (); + ADC8 (); +} + +static void Op79M0 (void) +{ + AbsoluteIndexedY (); + ADC16 (); +} + +static void Op6FM1 (void) +{ + AbsoluteLong (); + ADC8 (); +} + +static void Op6FM0 (void) +{ + AbsoluteLong (); + ADC16 (); +} + +static void Op7FM1 (void) +{ + AbsoluteLongIndexedX (); + ADC8 (); +} + +static void Op7FM0 (void) +{ + AbsoluteLongIndexedX (); + ADC16 (); +} + +static void Op63M1 (void) +{ + StackRelative (); + ADC8 (); +} + +static void Op63M0 (void) +{ + StackRelative (); + ADC16 (); +} + +static void Op73M1 (void) +{ + StackRelativeIndirectIndexed (); + ADC8 (); +} + +static void Op73M0 (void) +{ + StackRelativeIndirectIndexed (); + ADC16 (); +} + +/**********************************************************************************************/ + +/* AND *************************************************************************************** */ +static void Op29M1 (void) +{ + Registers.AL &= *CPU.PC++; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + SetZN8 (Registers.AL); +} + +static void Op29M0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + Registers.A.W &= *(uint16 *) CPU.PC; +#else + Registers.A.W &= *CPU.PC + (*(CPU.PC + 1) << 8); +#endif + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + SetZN16 (Registers.A.W); +} + +static void Op25M1 (void) +{ + Direct (); + AND8 (); +} + +static void Op25M0 (void) +{ + Direct (); + AND16 (); +} + +static void Op35M1 (void) +{ + DirectIndexedX (); + AND8 (); +} + +static void Op35M0 (void) +{ + DirectIndexedX (); + AND16 (); +} + +static void Op32M1 (void) +{ + DirectIndirect (); + AND8 (); +} + +static void Op32M0 (void) +{ + DirectIndirect (); + AND16 (); +} + +static void Op21M1 (void) +{ + DirectIndexedIndirect (); + AND8 (); +} + +static void Op21M0 (void) +{ + DirectIndexedIndirect (); + AND16 (); +} + +static void Op31M1 (void) +{ + DirectIndirectIndexed (); + AND8 (); +} + +static void Op31M0 (void) +{ + DirectIndirectIndexed (); + AND16 (); +} + +static void Op27M1 (void) +{ + DirectIndirectLong (); + AND8 (); +} + +static void Op27M0 (void) +{ + DirectIndirectLong (); + AND16 (); +} + +static void Op37M1 (void) +{ + DirectIndirectIndexedLong (); + AND8 (); +} + +static void Op37M0 (void) +{ + DirectIndirectIndexedLong (); + AND16 (); +} + +static void Op2DM1 (void) +{ + Absolute (); + AND8 (); +} + +static void Op2DM0 (void) +{ + Absolute (); + AND16 (); +} + +static void Op3DM1 (void) +{ + AbsoluteIndexedX (); + AND8 (); +} + +static void Op3DM0 (void) +{ + AbsoluteIndexedX (); + AND16 (); +} + +static void Op39M1 (void) +{ + AbsoluteIndexedY (); + AND8 (); +} + +static void Op39M0 (void) +{ + AbsoluteIndexedY (); + AND16 (); +} + +static void Op2FM1 (void) +{ + AbsoluteLong (); + AND8 (); +} + +static void Op2FM0 (void) +{ + AbsoluteLong (); + AND16 (); +} + +static void Op3FM1 (void) +{ + AbsoluteLongIndexedX (); + AND8 (); +} + +static void Op3FM0 (void) +{ + AbsoluteLongIndexedX (); + AND16 (); +} + +static void Op23M1 (void) +{ + StackRelative (); + AND8 (); +} + +static void Op23M0 (void) +{ + StackRelative (); + AND16 (); +} + +static void Op33M1 (void) +{ + StackRelativeIndirectIndexed (); + AND8 (); +} + +static void Op33M0 (void) +{ + StackRelativeIndirectIndexed (); + AND16 (); +} +/**********************************************************************************************/ + +/* ASL *************************************************************************************** */ +static void Op0AM1 (void) +{ + A_ASL8 (); +} + +static void Op0AM0 (void) +{ + A_ASL16 (); +} + +static void Op06M1 (void) +{ + Direct (); + ASL8 (); +} + +static void Op06M0 (void) +{ + Direct (); + ASL16 (); +} + +static void Op16M1 (void) +{ + DirectIndexedX (); + ASL8 (); +} + +static void Op16M0 (void) +{ + DirectIndexedX (); + ASL16 (); + +} + +static void Op0EM1 (void) +{ + Absolute (); + ASL8 (); +} + +static void Op0EM0 (void) +{ + Absolute (); + ASL16 (); +} + +static void Op1EM1 (void) +{ + AbsoluteIndexedX (); + ASL8 (); +} + +static void Op1EM0 (void) +{ + AbsoluteIndexedX (); + ASL16 (); +} +/**********************************************************************************************/ + +/* BIT *************************************************************************************** */ +static void Op89M1 (void) +{ + ICPU._Zero = Registers.AL & *CPU.PC++; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif +} + +static void Op89M0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + ICPU._Zero = (Registers.A.W & *(uint16 *) CPU.PC) != 0; +#else + ICPU._Zero = (Registers.A.W & (*CPU.PC + (*(CPU.PC + 1) << 8))) != 0; +#endif +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + CPU.PC += 2; +} + +static void Op24M1 (void) +{ + Direct (); + BIT8 (); +} + +static void Op24M0 (void) +{ + Direct (); + BIT16 (); +} + +static void Op34M1 (void) +{ + DirectIndexedX (); + BIT8 (); +} + +static void Op34M0 (void) +{ + DirectIndexedX (); + BIT16 (); +} + +static void Op2CM1 (void) +{ + Absolute (); + BIT8 (); +} + +static void Op2CM0 (void) +{ + Absolute (); + BIT16 (); +} + +static void Op3CM1 (void) +{ + AbsoluteIndexedX (); + BIT8 (); +} + +static void Op3CM0 (void) +{ + AbsoluteIndexedX (); + BIT16 (); +} +/**********************************************************************************************/ + +/* CMP *************************************************************************************** */ +static void OpC9M1 (void) +{ + long s9xInt32 = (int) Registers.AL - (int) *CPU.PC++; + ICPU._Carry = s9xInt32 >= 0; + SetZN8 ((uint8) s9xInt32); +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif +} + +static void OpC9M0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + long s9xInt32 = (long) Registers.A.W - (long) *(uint16 *) CPU.PC; +#else + long s9xInt32 = (long) Registers.A.W - + (long) (*CPU.PC + (*(CPU.PC + 1) << 8)); +#endif + ICPU._Carry = s9xInt32 >= 0; + SetZN16 ((uint16) s9xInt32); + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif +} + +static void OpC5M1 (void) +{ + Direct (); + CMP8 (); +} + +static void OpC5M0 (void) +{ + Direct (); + CMP16 (); +} + +static void OpD5M1 (void) +{ + DirectIndexedX (); + CMP8 (); +} + +static void OpD5M0 (void) +{ + DirectIndexedX (); + CMP16 (); +} + +static void OpD2M1 (void) +{ + DirectIndirect (); + CMP8 (); +} + +static void OpD2M0 (void) +{ + DirectIndirect (); + CMP16 (); +} + +static void OpC1M1 (void) +{ + DirectIndexedIndirect (); + CMP8 (); +} + +static void OpC1M0 (void) +{ + DirectIndexedIndirect (); + CMP16 (); +} + +static void OpD1M1 (void) +{ + DirectIndirectIndexed (); + CMP8 (); +} + +static void OpD1M0 (void) +{ + DirectIndirectIndexed (); + CMP16 (); +} + +static void OpC7M1 (void) +{ + DirectIndirectLong (); + CMP8 (); +} + +static void OpC7M0 (void) +{ + DirectIndirectLong (); + CMP16 (); +} + +static void OpD7M1 (void) +{ + DirectIndirectIndexedLong (); + CMP8 (); +} + +static void OpD7M0 (void) +{ + DirectIndirectIndexedLong (); + CMP16 (); +} + +static void OpCDM1 (void) +{ + Absolute (); + CMP8 (); +} + +static void OpCDM0 (void) +{ + Absolute (); + CMP16 (); +} + +static void OpDDM1 (void) +{ + AbsoluteIndexedX (); + CMP8 (); +} + +static void OpDDM0 (void) +{ + AbsoluteIndexedX (); + CMP16 (); +} + +static void OpD9M1 (void) +{ + AbsoluteIndexedY (); + CMP8 (); +} + +static void OpD9M0 (void) +{ + AbsoluteIndexedY (); + CMP16 (); +} + +static void OpCFM1 (void) +{ + AbsoluteLong (); + CMP8 (); +} + +static void OpCFM0 (void) +{ + AbsoluteLong (); + CMP16 (); +} + +static void OpDFM1 (void) +{ + AbsoluteLongIndexedX (); + CMP8 (); +} + +static void OpDFM0 (void) +{ + AbsoluteLongIndexedX (); + CMP16 (); +} + +static void OpC3M1 (void) +{ + StackRelative (); + CMP8 (); +} + +static void OpC3M0 (void) +{ + StackRelative (); + CMP16 (); +} + +static void OpD3M1 (void) +{ + StackRelativeIndirectIndexed (); + CMP8 (); +} + +static void OpD3M0 (void) +{ + StackRelativeIndirectIndexed (); + CMP16 (); +} + +/**********************************************************************************************/ + +/* CMX *************************************************************************************** */ +static void OpE0X1 (void) +{ + long s9xInt32 = (int) Registers.XL - (int) *CPU.PC++; + ICPU._Carry = s9xInt32 >= 0; + SetZN8 ((uint8) s9xInt32); +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif +} + +static void OpE0X0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + long s9xInt32 = (long) Registers.X.W - (long) *(uint16 *) CPU.PC; +#else + long s9xInt32 = (long) Registers.X.W - + (long) (*CPU.PC + (*(CPU.PC + 1) << 8)); +#endif + ICPU._Carry = s9xInt32 >= 0; + SetZN16 ((uint16) s9xInt32); + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif +} + +static void OpE4X1 (void) +{ + Direct (); + CMX8 (); +} + +static void OpE4X0 (void) +{ + Direct (); + CMX16 (); +} + +static void OpECX1 (void) +{ + Absolute (); + CMX8 (); +} + +static void OpECX0 (void) +{ + Absolute (); + CMX16 (); +} + +/**********************************************************************************************/ + +/* CMY *************************************************************************************** */ +static void OpC0X1 (void) +{ + long s9xInt32 = (int) Registers.YL - (int) *CPU.PC++; + ICPU._Carry = s9xInt32 >= 0; + SetZN8 ((uint8) s9xInt32); +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif +} + +static void OpC0X0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + long s9xInt32 = (long) Registers.Y.W - (long) *(uint16 *) CPU.PC; +#else + long s9xInt32 = (long) Registers.Y.W - + (long) (*CPU.PC + (*(CPU.PC + 1) << 8)); +#endif + ICPU._Carry = s9xInt32 >= 0; + SetZN16 ((uint16) s9xInt32); + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif +} + +static void OpC4X1 (void) +{ + Direct (); + CMY8 (); +} + +static void OpC4X0 (void) +{ + Direct (); + CMY16 (); +} + +static void OpCCX1 (void) +{ + Absolute (); + CMY8 (); +} + +static void OpCCX0 (void) +{ + Absolute (); + CMY16 (); +} + +/**********************************************************************************************/ + +/* DEC *************************************************************************************** */ +static void Op3AM1 (void) +{ + A_DEC8 (); +} + +static void Op3AM0 (void) +{ + A_DEC16 (); +} + +static void OpC6M1 (void) +{ + Direct (); + DEC8 (); +} + +static void OpC6M0 (void) +{ + Direct (); + DEC16 (); +} + +static void OpD6M1 (void) +{ + DirectIndexedX (); + DEC8 (); +} + +static void OpD6M0 (void) +{ + DirectIndexedX (); + DEC16 (); +} + +static void OpCEM1 (void) +{ + Absolute (); + DEC8 (); +} + +static void OpCEM0 (void) +{ + Absolute (); + DEC16 (); +} + +static void OpDEM1 (void) +{ + AbsoluteIndexedX (); + DEC8 (); +} + +static void OpDEM0 (void) +{ + AbsoluteIndexedX (); + DEC16 (); +} + +/**********************************************************************************************/ + +/* EOR *************************************************************************************** */ +static void Op49M1 (void) +{ + Registers.AL ^= *CPU.PC++; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + SetZN8 (Registers.AL); +} + +static void Op49M0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + Registers.A.W ^= *(uint16 *) CPU.PC; +#else + Registers.A.W ^= *CPU.PC + (*(CPU.PC + 1) << 8); +#endif + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + SetZN16 (Registers.A.W); +} + +static void Op45M1 (void) +{ + Direct (); + EOR8 (); +} + +static void Op45M0 (void) +{ + Direct (); + EOR16 (); +} + +static void Op55M1 (void) +{ + DirectIndexedX (); + EOR8 (); +} + +static void Op55M0 (void) +{ + DirectIndexedX (); + EOR16 (); +} + +static void Op52M1 (void) +{ + DirectIndirect (); + EOR8 (); +} + +static void Op52M0 (void) +{ + DirectIndirect (); + EOR16 (); +} + +static void Op41M1 (void) +{ + DirectIndexedIndirect (); + EOR8 (); +} + +static void Op41M0 (void) +{ + DirectIndexedIndirect (); + EOR16 (); +} + +static void Op51M1 (void) +{ + DirectIndirectIndexed (); + EOR8 (); +} + +static void Op51M0 (void) +{ + DirectIndirectIndexed (); + EOR16 (); +} + +static void Op47M1 (void) +{ + DirectIndirectLong (); + EOR8 (); +} + +static void Op47M0 (void) +{ + DirectIndirectLong (); + EOR16 (); +} + +static void Op57M1 (void) +{ + DirectIndirectIndexedLong (); + EOR8 (); +} + +static void Op57M0 (void) +{ + DirectIndirectIndexedLong (); + EOR16 (); +} + +static void Op4DM1 (void) +{ + Absolute (); + EOR8 (); +} + +static void Op4DM0 (void) +{ + Absolute (); + EOR16 (); +} + +static void Op5DM1 (void) +{ + AbsoluteIndexedX (); + EOR8 (); +} + +static void Op5DM0 (void) +{ + AbsoluteIndexedX (); + EOR16 (); +} + +static void Op59M1 (void) +{ + AbsoluteIndexedY (); + EOR8 (); +} + +static void Op59M0 (void) +{ + AbsoluteIndexedY (); + EOR16 (); +} + +static void Op4FM1 (void) +{ + AbsoluteLong (); + EOR8 (); +} + +static void Op4FM0 (void) +{ + AbsoluteLong (); + EOR16 (); +} + +static void Op5FM1 (void) +{ + AbsoluteLongIndexedX (); + EOR8 (); +} + +static void Op5FM0 (void) +{ + AbsoluteLongIndexedX (); + EOR16 (); +} + +static void Op43M1 (void) +{ + StackRelative (); + EOR8 (); +} + +static void Op43M0 (void) +{ + StackRelative (); + EOR16 (); +} + +static void Op53M1 (void) +{ + StackRelativeIndirectIndexed (); + EOR8 (); +} + +static void Op53M0 (void) +{ + StackRelativeIndirectIndexed (); + EOR16 (); +} + +/**********************************************************************************************/ + +/* INC *************************************************************************************** */ +static void Op1AM1 (void) +{ + A_INC8 (); +} + +static void Op1AM0 (void) +{ + A_INC16 (); +} + +static void OpE6M1 (void) +{ + Direct (); + INC8 (); +} + +static void OpE6M0 (void) +{ + Direct (); + INC16 (); +} + +static void OpF6M1 (void) +{ + DirectIndexedX (); + INC8 (); +} + +static void OpF6M0 (void) +{ + DirectIndexedX (); + INC16 (); +} + +static void OpEEM1 (void) +{ + Absolute (); + INC8 (); +} + +static void OpEEM0 (void) +{ + Absolute (); + INC16 (); +} + +static void OpFEM1 (void) +{ + AbsoluteIndexedX (); + INC8 (); +} + +static void OpFEM0 (void) +{ + AbsoluteIndexedX (); + INC16 (); +} + +/**********************************************************************************************/ +/* LDA *************************************************************************************** */ +static void OpA9M1 (void) +{ + Registers.AL = *CPU.PC++; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + SetZN8 (Registers.AL); +} + +static void OpA9M0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + Registers.A.W = *(uint16 *) CPU.PC; +#else + Registers.A.W = *CPU.PC + (*(CPU.PC + 1) << 8); +#endif + + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + SetZN16 (Registers.A.W); +} + +static void OpA5M1 (void) +{ + Direct (); + LDA8 (); +} + +static void OpA5M0 (void) +{ + Direct (); + LDA16 (); +} + +static void OpB5M1 (void) +{ + DirectIndexedX (); + LDA8 (); +} + +static void OpB5M0 (void) +{ + DirectIndexedX (); + LDA16 (); +} + +static void OpB2M1 (void) +{ + DirectIndirect (); + LDA8 (); +} + +static void OpB2M0 (void) +{ + DirectIndirect (); + LDA16 (); +} + +static void OpA1M1 (void) +{ + DirectIndexedIndirect (); + LDA8 (); +} + +static void OpA1M0 (void) +{ + DirectIndexedIndirect (); + LDA16 (); +} + +static void OpB1M1 (void) +{ + DirectIndirectIndexed (); + LDA8 (); +} + +static void OpB1M0 (void) +{ + DirectIndirectIndexed (); + LDA16 (); +} + +static void OpA7M1 (void) +{ + DirectIndirectLong (); + LDA8 (); +} + +static void OpA7M0 (void) +{ + DirectIndirectLong (); + LDA16 (); +} + +static void OpB7M1 (void) +{ + DirectIndirectIndexedLong (); + LDA8 (); +} + +static void OpB7M0 (void) +{ + DirectIndirectIndexedLong (); + LDA16 (); +} + +static void OpADM1 (void) +{ + Absolute (); + LDA8 (); +} + +static void OpADM0 (void) +{ + Absolute (); + LDA16 (); +} + +static void OpBDM1 (void) +{ + AbsoluteIndexedX (); + LDA8 (); +} + +static void OpBDM0 (void) +{ + AbsoluteIndexedX (); + LDA16 (); +} + +static void OpB9M1 (void) +{ + AbsoluteIndexedY (); + LDA8 (); +} + +static void OpB9M0 (void) +{ + AbsoluteIndexedY (); + LDA16 (); +} + +static void OpAFM1 (void) +{ + AbsoluteLong (); + LDA8 (); +} + +static void OpAFM0 (void) +{ + AbsoluteLong (); + LDA16 (); +} + +static void OpBFM1 (void) +{ + AbsoluteLongIndexedX (); + LDA8 (); +} + +static void OpBFM0 (void) +{ + AbsoluteLongIndexedX (); + LDA16 (); +} + +static void OpA3M1 (void) +{ + StackRelative (); + LDA8 (); +} + +static void OpA3M0 (void) +{ + StackRelative (); + LDA16 (); +} + +static void OpB3M1 (void) +{ + StackRelativeIndirectIndexed (); + LDA8 (); +} + +static void OpB3M0 (void) +{ + StackRelativeIndirectIndexed (); + LDA16 (); +} + +/**********************************************************************************************/ + +/* LDX *************************************************************************************** */ +static void OpA2X1 (void) +{ + Registers.XL = *CPU.PC++; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + SetZN8 (Registers.XL); +} + +static void OpA2X0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + Registers.X.W = *(uint16 *) CPU.PC; +#else + Registers.X.W = *CPU.PC + (*(CPU.PC + 1) << 8); +#endif + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + SetZN16 (Registers.X.W); +} + +static void OpA6X1 (void) +{ + Direct (); + LDX8 (); +} + +static void OpA6X0 (void) +{ + Direct (); + LDX16 (); +} + +static void OpB6X1 (void) +{ + DirectIndexedY (); + LDX8 (); +} + +static void OpB6X0 (void) +{ + DirectIndexedY (); + LDX16 (); +} + +static void OpAEX1 (void) +{ + Absolute (); + LDX8 (); +} + +static void OpAEX0 (void) +{ + Absolute (); + LDX16 (); +} + +static void OpBEX1 (void) +{ + AbsoluteIndexedY (); + LDX8 (); +} + +static void OpBEX0 (void) +{ + AbsoluteIndexedY (); + LDX16 (); +} +/**********************************************************************************************/ + +/* LDY *************************************************************************************** */ +static void OpA0X1 (void) +{ + Registers.YL = *CPU.PC++; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + SetZN8 (Registers.YL); +} + +static void OpA0X0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + Registers.Y.W = *(uint16 *) CPU.PC; +#else + Registers.Y.W = *CPU.PC + (*(CPU.PC + 1) << 8); +#endif + + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + SetZN16 (Registers.Y.W); +} + +static void OpA4X1 (void) +{ + Direct (); + LDY8 (); +} + +static void OpA4X0 (void) +{ + Direct (); + LDY16 (); +} + +static void OpB4X1 (void) +{ + DirectIndexedX (); + LDY8 (); +} + +static void OpB4X0 (void) +{ + DirectIndexedX (); + LDY16 (); +} + +static void OpACX1 (void) +{ + Absolute (); + LDY8 (); +} + +static void OpACX0 (void) +{ + Absolute (); + LDY16 (); +} + +static void OpBCX1 (void) +{ + AbsoluteIndexedX (); + LDY8 (); +} + +static void OpBCX0 (void) +{ + AbsoluteIndexedX (); + LDY16 (); +} +/**********************************************************************************************/ + +/* LSR *************************************************************************************** */ +static void Op4AM1 (void) +{ + A_LSR8 (); +} + +static void Op4AM0 (void) +{ + A_LSR16 (); +} + +static void Op46M1 (void) +{ + Direct (); + LSR8 (); +} + +static void Op46M0 (void) +{ + Direct (); + LSR16 (); +} + +static void Op56M1 (void) +{ + DirectIndexedX (); + LSR8 (); +} + +static void Op56M0 (void) +{ + DirectIndexedX (); + LSR16 (); +} + +static void Op4EM1 (void) +{ + Absolute (); + LSR8 (); +} + +static void Op4EM0 (void) +{ + Absolute (); + LSR16 (); +} + +static void Op5EM1 (void) +{ + AbsoluteIndexedX (); + LSR8 (); +} + +static void Op5EM0 (void) +{ + AbsoluteIndexedX (); + LSR16 (); +} + +/**********************************************************************************************/ + +/* ORA *************************************************************************************** */ +static void Op09M1 (void) +{ + Registers.AL |= *CPU.PC++; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; +#endif + SetZN8 (Registers.AL); +} + +static void Op09M0 (void) +{ +#ifdef FAST_LSB_WORD_ACCESS + Registers.A.W |= *(uint16 *) CPU.PC; +#else + Registers.A.W |= *CPU.PC + (*(CPU.PC + 1) << 8); +#endif + CPU.PC += 2; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2; +#endif + SetZN16 (Registers.A.W); +} + +static void Op05M1 (void) +{ + Direct (); + ORA8 (); +} + +static void Op05M0 (void) +{ + Direct (); + ORA16 (); +} + +static void Op15M1 (void) +{ + DirectIndexedX (); + ORA8 (); +} + +static void Op15M0 (void) +{ + DirectIndexedX (); + ORA16 (); +} + +static void Op12M1 (void) +{ + DirectIndirect (); + ORA8 (); +} + +static void Op12M0 (void) +{ + DirectIndirect (); + ORA16 (); +} + +static void Op01M1 (void) +{ + DirectIndexedIndirect (); + ORA8 (); +} + +static void Op01M0 (void) +{ + DirectIndexedIndirect (); + ORA16 (); +} + +static void Op11M1 (void) +{ + DirectIndirectIndexed (); + ORA8 (); +} + +static void Op11M0 (void) +{ + DirectIndirectIndexed (); + ORA16 (); +} + +static void Op07M1 (void) +{ + DirectIndirectLong (); + ORA8 (); +} + +static void Op07M0 (void) +{ + DirectIndirectLong (); + ORA16 (); +} + +static void Op17M1 (void) +{ + DirectIndirectIndexedLong (); + ORA8 (); +} + +static void Op17M0 (void) +{ + DirectIndirectIndexedLong (); + ORA16 (); +} + +static void Op0DM1 (void) +{ + Absolute (); + ORA8 (); +} + +static void Op0DM0 (void) +{ + Absolute (); + ORA16 (); +} + +static void Op1DM1 (void) +{ + AbsoluteIndexedX (); + ORA8 (); +} + +static void Op1DM0 (void) +{ + AbsoluteIndexedX (); + ORA16 (); +} + +static void Op19M1 (void) +{ + AbsoluteIndexedY (); + ORA8 (); +} + +static void Op19M0 (void) +{ + AbsoluteIndexedY (); + ORA16 (); +} + +static void Op0FM1 (void) +{ + AbsoluteLong (); + ORA8 (); +} + +static void Op0FM0 (void) +{ + AbsoluteLong (); + ORA16 (); +} + +static void Op1FM1 (void) +{ + AbsoluteLongIndexedX (); + ORA8 (); +} + +static void Op1FM0 (void) +{ + AbsoluteLongIndexedX (); + ORA16 (); +} + +static void Op03M1 (void) +{ + StackRelative (); + ORA8 (); +} + +static void Op03M0 (void) +{ + StackRelative (); + ORA16 (); +} + +static void Op13M1 (void) +{ + StackRelativeIndirectIndexed (); + ORA8 (); +} + +static void Op13M0 (void) +{ + StackRelativeIndirectIndexed (); + ORA16 (); +} + +/**********************************************************************************************/ + +/* ROL *************************************************************************************** */ +static void Op2AM1 (void) +{ + A_ROL8 (); +} + +static void Op2AM0 (void) +{ + A_ROL16 (); +} + +static void Op26M1 (void) +{ + Direct (); + ROL8 (); +} + +static void Op26M0 (void) +{ + Direct (); + ROL16 (); +} + +static void Op36M1 (void) +{ + DirectIndexedX (); + ROL8 (); +} + +static void Op36M0 (void) +{ + DirectIndexedX (); + ROL16 (); +} + +static void Op2EM1 (void) +{ + Absolute (); + ROL8 (); +} + +static void Op2EM0 (void) +{ + Absolute (); + ROL16 (); +} + +static void Op3EM1 (void) +{ + AbsoluteIndexedX (); + ROL8 (); +} + +static void Op3EM0 (void) +{ + AbsoluteIndexedX (); + ROL16 (); +} +/**********************************************************************************************/ + +/* ROR *************************************************************************************** */ +static void Op6AM1 (void) +{ + A_ROR8 (); +} + +static void Op6AM0 (void) +{ + A_ROR16 (); +} + +static void Op66M1 (void) +{ + Direct (); + ROR8 (); +} + +static void Op66M0 (void) +{ + Direct (); + ROR16 (); +} + +static void Op76M1 (void) +{ + DirectIndexedX (); + ROR8 (); +} + +static void Op76M0 (void) +{ + DirectIndexedX (); + ROR16 (); +} + +static void Op6EM1 (void) +{ + Absolute (); + ROR8 (); +} + +static void Op6EM0 (void) +{ + Absolute (); + ROR16 (); +} + +static void Op7EM1 (void) +{ + AbsoluteIndexedX (); + ROR8 (); +} + +static void Op7EM0 (void) +{ + AbsoluteIndexedX (); + ROR16 (); +} +/**********************************************************************************************/ + +/* SBC *************************************************************************************** */ +static void OpE9M1 (void) +{ + Immediate8 (); + SBC8 (); +} + +static void OpE9M0 (void) +{ + Immediate16 (); + SBC16 (); +} + +static void OpE5M1 (void) +{ + Direct (); + SBC8 (); +} + +static void OpE5M0 (void) +{ + Direct (); + SBC16 (); +} + +static void OpF5M1 (void) +{ + DirectIndexedX (); + SBC8 (); +} + +static void OpF5M0 (void) +{ + DirectIndexedX (); + SBC16 (); +} + +static void OpF2M1 (void) +{ + DirectIndirect (); + SBC8 (); +} + +static void OpF2M0 (void) +{ + DirectIndirect (); + SBC16 (); +} + +static void OpE1M1 (void) +{ + DirectIndexedIndirect (); + SBC8 (); +} + +static void OpE1M0 (void) +{ + DirectIndexedIndirect (); + SBC16 (); +} + +static void OpF1M1 (void) +{ + DirectIndirectIndexed (); + SBC8 (); +} + +static void OpF1M0 (void) +{ + DirectIndirectIndexed (); + SBC16 (); +} + +static void OpE7M1 (void) +{ + DirectIndirectLong (); + SBC8 (); +} + +static void OpE7M0 (void) +{ + DirectIndirectLong (); + SBC16 (); +} + +static void OpF7M1 (void) +{ + DirectIndirectIndexedLong (); + SBC8 (); +} + +static void OpF7M0 (void) +{ + DirectIndirectIndexedLong (); + SBC16 (); +} + +static void OpEDM1 (void) +{ + Absolute (); + SBC8 (); +} + +static void OpEDM0 (void) +{ + Absolute (); + SBC16 (); +} + +static void OpFDM1 (void) +{ + AbsoluteIndexedX (); + SBC8 (); +} + +static void OpFDM0 (void) +{ + AbsoluteIndexedX (); + SBC16 (); +} + +static void OpF9M1 (void) +{ + AbsoluteIndexedY (); + SBC8 (); +} + +static void OpF9M0 (void) +{ + AbsoluteIndexedY (); + SBC16 (); +} + +static void OpEFM1 (void) +{ + AbsoluteLong (); + SBC8 (); +} + +static void OpEFM0 (void) +{ + AbsoluteLong (); + SBC16 (); +} + +static void OpFFM1 (void) +{ + AbsoluteLongIndexedX (); + SBC8 (); +} + +static void OpFFM0 (void) +{ + AbsoluteLongIndexedX (); + SBC16 (); +} + +static void OpE3M1 (void) +{ + StackRelative (); + SBC8 (); +} + +static void OpE3M0 (void) +{ + StackRelative (); + SBC16 (); +} + +static void OpF3M1 (void) +{ + StackRelativeIndirectIndexed (); + SBC8 (); +} + +static void OpF3M0 (void) +{ + StackRelativeIndirectIndexed (); + SBC16 (); +} +/**********************************************************************************************/ + +/* STA *************************************************************************************** */ +static void Op85M1 (void) +{ + Direct (); + STA8 (); +} + +static void Op85M0 (void) +{ + Direct (); + STA16 (); +} + +static void Op95M1 (void) +{ + DirectIndexedX (); + STA8 (); +} + +static void Op95M0 (void) +{ + DirectIndexedX (); + STA16 (); +} + +static void Op92M1 (void) +{ + DirectIndirect (); + STA8 (); +} + +static void Op92M0 (void) +{ + DirectIndirect (); + STA16 (); +} + +static void Op81M1 (void) +{ + DirectIndexedIndirect (); + STA8 (); +#ifdef VAR_CYCLES + if (CheckIndex ()) + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op81M0 (void) +{ + DirectIndexedIndirect (); + STA16 (); +#ifdef VAR_CYCLES + if (CheckIndex ()) + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op91M1 (void) +{ + DirectIndirectIndexed (); + STA8 (); +} + +static void Op91M0 (void) +{ + DirectIndirectIndexed (); + STA16 (); +} + +static void Op87M1 (void) +{ + DirectIndirectLong (); + STA8 (); +} + +static void Op87M0 (void) +{ + DirectIndirectLong (); + STA16 (); +} + +static void Op97M1 (void) +{ + DirectIndirectIndexedLong (); + STA8 (); +} + +static void Op97M0 (void) +{ + DirectIndirectIndexedLong (); + STA16 (); +} + +static void Op8DM1 (void) +{ + Absolute (); + STA8 (); +} + +static void Op8DM0 (void) +{ + Absolute (); + STA16 (); +} + +static void Op9DM1 (void) +{ + AbsoluteIndexedX (); + STA8 (); +} + +static void Op9DM0 (void) +{ + AbsoluteIndexedX (); + STA16 (); +} + +static void Op99M1 (void) +{ + AbsoluteIndexedY (); + STA8 (); +} + +static void Op99M0 (void) +{ + AbsoluteIndexedY (); + STA16 (); +} + +static void Op8FM1 (void) +{ + AbsoluteLong (); + STA8 (); +} + +static void Op8FM0 (void) +{ + AbsoluteLong (); + STA16 (); +} + +static void Op9FM1 (void) +{ + AbsoluteLongIndexedX (); + STA8 (); +} + +static void Op9FM0 (void) +{ + AbsoluteLongIndexedX (); + STA16 (); +} + +static void Op83M1 (void) +{ + StackRelative (); + STA8 (); +} + +static void Op83M0 (void) +{ + StackRelative (); + STA16 (); +} + +static void Op93M1 (void) +{ + StackRelativeIndirectIndexed (); + STA8 (); +} + +static void Op93M0 (void) +{ + StackRelativeIndirectIndexed (); + STA16 (); +} +/**********************************************************************************************/ + +/* STX *************************************************************************************** */ +static void Op86X1 (void) +{ + Direct (); + STX8 (); +} + +static void Op86X0 (void) +{ + Direct (); + STX16 (); +} + +static void Op96X1 (void) +{ + DirectIndexedY (); + STX8 (); +} + +static void Op96X0 (void) +{ + DirectIndexedY (); + STX16 (); +} + +static void Op8EX1 (void) +{ + Absolute (); + STX8 (); +} + +static void Op8EX0 (void) +{ + Absolute (); + STX16 (); +} +/**********************************************************************************************/ + +/* STY *************************************************************************************** */ +static void Op84X1 (void) +{ + Direct (); + STY8 (); +} + +static void Op84X0 (void) +{ + Direct (); + STY16 (); +} + +static void Op94X1 (void) +{ + DirectIndexedX (); + STY8 (); +} + +static void Op94X0 (void) +{ + DirectIndexedX (); + STY16 (); +} + +static void Op8CX1 (void) +{ + Absolute (); + STY8 (); +} + +static void Op8CX0 (void) +{ + Absolute (); + STY16 (); +} +/**********************************************************************************************/ + +/* STZ *************************************************************************************** */ +static void Op64M1 (void) +{ + Direct (); + STZ8 (); +} + +static void Op64M0 (void) +{ + Direct (); + STZ16 (); +} + +static void Op74M1 (void) +{ + DirectIndexedX (); + STZ8 (); +} + +static void Op74M0 (void) +{ + DirectIndexedX (); + STZ16 (); +} + +static void Op9CM1 (void) +{ + Absolute (); + STZ8 (); +} + +static void Op9CM0 (void) +{ + Absolute (); + STZ16 (); +} + +static void Op9EM1 (void) +{ + AbsoluteIndexedX (); + STZ8 (); +} + +static void Op9EM0 (void) +{ + AbsoluteIndexedX (); + STZ16 (); +} + +/**********************************************************************************************/ + +/* TRB *************************************************************************************** */ +static void Op14M1 (void) +{ + Direct (); + TRB8 (); +} + +static void Op14M0 (void) +{ + Direct (); + TRB16 (); +} + +static void Op1CM1 (void) +{ + Absolute (); + TRB8 (); +} + +static void Op1CM0 (void) +{ + Absolute (); + TRB16 (); +} +/**********************************************************************************************/ + +/* TSB *************************************************************************************** */ +static void Op04M1 (void) +{ + Direct (); + TSB8 (); +} + +static void Op04M0 (void) +{ + Direct (); + TSB16 (); +} + +static void Op0CM1 (void) +{ + Absolute (); + TSB8 (); +} + +static void Op0CM0 (void) +{ + Absolute (); + TSB16 (); +} + +/**********************************************************************************************/ + +/* Branch Instructions *********************************************************************** */ +#ifndef SA1_OPCODES +#define BranchCheck0()\ + if( CPU.BranchSkip)\ + {\ + CPU.BranchSkip = FALSE;\ + if (!Settings.SoundSkipMethod)\ + if( CPU.PC - CPU.PCBase > OpAddress)\ + return;\ + } + +#define BranchCheck1()\ + if( CPU.BranchSkip)\ + {\ + CPU.BranchSkip = FALSE;\ + if (!Settings.SoundSkipMethod) {\ + if( CPU.PC - CPU.PCBase > OpAddress)\ + return;\ + } else \ + if (Settings.SoundSkipMethod == 1)\ + return;\ + if (Settings.SoundSkipMethod == 3)\ + if( CPU.PC - CPU.PCBase > OpAddress)\ + return;\ + else\ + CPU.PC = CPU.PCBase + OpAddress;\ + } + +#define BranchCheck2()\ + if( CPU.BranchSkip)\ + {\ + CPU.BranchSkip = FALSE;\ + if (!Settings.SoundSkipMethod) {\ + if( CPU.PC - CPU.PCBase > OpAddress)\ + return;\ + } else \ + if (Settings.SoundSkipMethod == 1)\ + CPU.PC = CPU.PCBase + OpAddress;\ + if (Settings.SoundSkipMethod == 3)\ + if (CPU.PC - CPU.PCBase > OpAddress)\ + return;\ + else\ + CPU.PC = CPU.PCBase + OpAddress;\ + } +#else +#define BranchCheck0() +#define BranchCheck1() +#define BranchCheck2() +#endif + +#ifdef CPU_SHUTDOWN +#ifndef SA1_OPCODES +inline void CPUShutdown() { + if (Settings.Shutdown && CPU.PC == CPU.WaitAddress) { + // Don't skip cycles with a pending NMI or IRQ - could cause delayed + // interrupt. Interrupts are delayed for a few cycles already, but + // the delay could allow the shutdown code to cycle skip again. + // Was causing screen flashing on Top Gear 3000. + + if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG))) { + CPU.WaitAddress = NULL; +#ifdef USE_SA1 + if (Settings.SA1) S9xSA1ExecuteDuringSleep (); + CPU.Cycles = CPU.NextEvent; +#endif + //S9xUpdateAPUTimer(); + asm_APU_EXECUTE2(); + } else { + if (CPU.WaitCounter >= 2) CPU.WaitCounter = 1; + else CPU.WaitCounter--; + } + } +} +#else +inline void CPUShutdown() +{ + if (Settings.Shutdown && CPU.PC == CPU.WaitAddress) + { + if (CPU.WaitCounter >= 1) + { + SA1.Executing = FALSE; + SA1.CPUExecuting = FALSE; + } + else + CPU.WaitCounter++; + } +} +#endif +#else +#define CPUShutdown() +#endif + +/* BCC */ +static void Op90 (void) +{ + Relative (); + BranchCheck0 (); + if (!CheckCarry ()) + { + CPU.PC = CPU.PCBase + OpAddress; +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles++; +#endif +#endif + CPUShutdown (); + } +} + +/* BCS */ +static void OpB0 (void) +{ + Relative (); + BranchCheck0 (); + if (CheckCarry ()) + { + CPU.PC = CPU.PCBase + OpAddress; +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles++; +#endif +#endif + CPUShutdown (); + } +} + +/* BEQ */ +static void OpF0 (void) +{ + Relative (); + BranchCheck2 (); + if (CheckZero ()) + { + CPU.PC = CPU.PCBase + OpAddress; +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles++; +#endif +#endif + CPUShutdown (); + } +} + +/* BMI */ +static void Op30 (void) +{ + Relative (); + + + BranchCheck1 (); + if (CheckNegative ()) + { + CPU.PC = CPU.PCBase + OpAddress; +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles++; +#endif +#endif + CPUShutdown (); + } +} + +/* BNE */ +static void OpD0 (void) +{ + Relative (); + BranchCheck1 (); + if (!CheckZero ()) + { + CPU.PC = CPU.PCBase + OpAddress; + +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles++; +#endif +#endif + CPUShutdown (); + } +} + +/* BPL */ +static void Op10 (void) +{ + Relative (); + BranchCheck1 (); + if (!CheckNegative ()) + { + CPU.PC = CPU.PCBase + OpAddress; +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles++; +#endif +#endif + CPUShutdown (); + } +} + +/* BRA */ +static void Op80 (void) +{ + Relative (); + CPU.PC = CPU.PCBase + OpAddress; +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles++; +#endif +#endif + CPUShutdown (); +} + +/* BVC */ +static void Op50 (void) +{ + Relative (); + BranchCheck0 (); + if (!CheckOverflow ()) + { + CPU.PC = CPU.PCBase + OpAddress; +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles++; +#endif +#endif + CPUShutdown (); + } +} + +/* BVS */ +static void Op70 (void) +{ + Relative (); + BranchCheck0 (); + if (CheckOverflow ()) + { + CPU.PC = CPU.PCBase + OpAddress; +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles++; +#endif +#endif + CPUShutdown (); + } +} +/**********************************************************************************************/ + +/* ClearFlag Instructions ******************************************************************** */ +/* CLC */ +static void Op18 (void) +{ + ClearCarry (); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +/* CLD */ +static void OpD8 (void) +{ + ClearDecimal (); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +/* CLI */ +static void Op58 (void) +{ + ClearIRQ (); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +/* CHECK_FOR_IRQ(); */ +} + +/* CLV */ +static void OpB8 (void) +{ + ClearOverflow (); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} +/**********************************************************************************************/ + +/* DEX/DEY *********************************************************************************** */ +static void OpCAX1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.XL--; + SetZN8 (Registers.XL); +} + +static void OpCAX0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.X.W--; + SetZN16 (Registers.X.W); +} + +static void Op88X1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.YL--; + SetZN8 (Registers.YL); +} + +static void Op88X0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.Y.W--; + SetZN16 (Registers.Y.W); +} +/**********************************************************************************************/ + +/* INX/INY *********************************************************************************** */ +static void OpE8X1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.XL++; + SetZN8 (Registers.XL); +} + +static void OpE8X0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.X.W++; + SetZN16 (Registers.X.W); +} + +static void OpC8X1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.YL++; + SetZN8 (Registers.YL); +} + +static void OpC8X0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = NULL; +#endif + + Registers.Y.W++; + SetZN16 (Registers.Y.W); +} + +/**********************************************************************************************/ + +/* NOP *************************************************************************************** */ +static void OpEA (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + +} +/**********************************************************************************************/ + +/* PUSH Instructions ************************************************************************* */ +#define PushW(w) \ + S9xSetWord (w, Registers.S.W - 1);\ + Registers.S.W -= 2; +#define PushB(b)\ + S9xSetByte (b, Registers.S.W--); + +static void OpF4 (void) +{ + Absolute (); + PushW ((unsigned short)OpAddress); +} + +static void OpD4 (void) +{ + DirectIndirect (); + PushW ((unsigned short)OpAddress); +} + +static void Op62 (void) +{ + RelativeLong (); + PushW ((unsigned short)OpAddress); +} + +static void Op48M1 (void) +{ + PushB (Registers.AL); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op48M0 (void) +{ + PushW (Registers.A.W); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op8B (void) +{ + PushB (Registers.DB); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op0B (void) +{ + PushW (Registers.D.W); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op4B (void) +{ + PushB (Registers.PB); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op08 (void) +{ + S9xPackStatus (); + PushB (Registers.PL); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void OpDAX1 (void) +{ + PushB (Registers.XL); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void OpDAX0 (void) +{ + PushW (Registers.X.W); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op5AX1 (void) +{ + PushB (Registers.YL); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op5AX0 (void) +{ + PushW (Registers.Y.W); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} +/**********************************************************************************************/ + +/* PULL Instructions ************************************************************************* */ +#define PullW(w) \ + w = S9xGetWord (Registers.S.W + 1); \ + Registers.S.W += 2; + +#define PullB(b)\ + b = S9xGetByte (++Registers.S.W); + +static void Op68M1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + PullB (Registers.AL); + SetZN8 (Registers.AL); +} + +static void Op68M0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + PullW (Registers.A.W); + SetZN16 (Registers.A.W); +} + +static void OpAB (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + PullB (Registers.DB); + SetZN8 (Registers.DB); + ICPU.ShiftedDB = Registers.DB << 16; +} + +/* PHP */ +static void Op2B (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + PullW (Registers.D.W); + SetZN16 (Registers.D.W); +} + +/* PLP */ +static void Op28 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + PullB (Registers.PL); + S9xUnpackStatus (); + + if (CheckIndex ()) + { + Registers.XH = 0; + Registers.YH = 0; + } + S9xFixCycles(); +/* CHECK_FOR_IRQ();*/ +} + +static void OpFAX1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + PullB (Registers.XL); + SetZN8 (Registers.XL); +} + +static void OpFAX0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + PullW (Registers.X.W); + SetZN16 (Registers.X.W); +} + +static void Op7AX1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + PullB (Registers.YL); + SetZN8 (Registers.YL); +} + +static void Op7AX0 (void) +{ +#ifdef VAR_CYCLES + + CPU.Cycles += TWO_CYCLES; +#endif + PullW (Registers.Y.W); + SetZN16 (Registers.Y.W); +} + +/**********************************************************************************************/ + +/* SetFlag Instructions ********************************************************************** */ +/* SEC */ +static void Op38 (void) +{ + SetCarry (); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +/* SED */ +static void OpF8 (void) +{ + SetDecimal (); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + missing.decimal_mode = 1; +} + +/* SEI */ +static void Op78 (void) +{ + SetIRQ (); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} +/**********************************************************************************************/ + +/* Transfer Instructions ********************************************************************* */ +/* TAX8 */ +static void OpAAX1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.XL = Registers.AL; + SetZN8 (Registers.XL); +} + +/* TAX16 */ +static void OpAAX0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.X.W = Registers.A.W; + SetZN16 (Registers.X.W); +} + +/* TAY8 */ +static void OpA8X1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.YL = Registers.AL; + SetZN8 (Registers.YL); +} + +/* TAY16 */ +static void OpA8X0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.Y.W = Registers.A.W; + SetZN16 (Registers.Y.W); +} + +static void Op5B (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.D.W = Registers.A.W; + SetZN16 (Registers.D.W); +} + +static void Op1B (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.S.W = Registers.A.W; + if (CheckEmulation()) + Registers.SH = 1; +} + +static void Op7B (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.A.W = Registers.D.W; + SetZN16 (Registers.A.W); +} + +static void Op3B (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.A.W = Registers.S.W; + SetZN16 (Registers.A.W); +} + +static void OpBAX1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.XL = Registers.SL; + SetZN8 (Registers.XL); +} + +static void OpBAX0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.X.W = Registers.S.W; + SetZN16 (Registers.X.W); +} + +static void Op8AM1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.AL = Registers.XL; + SetZN8 (Registers.AL); +} + +static void Op8AM0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.A.W = Registers.X.W; + SetZN16 (Registers.A.W); +} + +static void Op9A (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.S.W = Registers.X.W; + if (CheckEmulation()) + Registers.SH = 1; +} + +static void Op9BX1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.YL = Registers.XL; + SetZN8 (Registers.YL); +} + +static void Op9BX0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.Y.W = Registers.X.W; + SetZN16 (Registers.Y.W); +} + +static void Op98M1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.AL = Registers.YL; + SetZN8 (Registers.AL); +} + +static void Op98M0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.A.W = Registers.Y.W; + SetZN16 (Registers.A.W); +} + +static void OpBBX1 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.XL = Registers.YL; + SetZN8 (Registers.XL); +} + +static void OpBBX0 (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + Registers.X.W = Registers.Y.W; + SetZN16 (Registers.X.W); +} + +/**********************************************************************************************/ + +/* XCE *************************************************************************************** */ +static void OpFB (void) +{ +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + + uint8 A1 = ICPU._Carry; + uint8 A2 = Registers.PH; + ICPU._Carry = A2 & 1; + Registers.PH = A1; + + if (CheckEmulation()) + { + SetFlags (MemoryFlag | IndexFlag); + Registers.SH = 1; + missing.emulate6502 = 1; + } + if (CheckIndex ()) + { + Registers.XH = 0; + Registers.YH = 0; + } + S9xFixCycles(); +} +/**********************************************************************************************/ + +/* BRK *************************************************************************************** */ +static void Op00 (void) +{ +#ifdef DEBUGGER + if (CPU.Flags & TRACE_FLAG) + S9xTraceMessage ("*** BRK"); +#endif + +#ifndef SA1_OPCODES + CPU.BRKTriggered = TRUE; +#endif + + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase + 1); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; + S9xSetPCBase (S9xGetWord (0xFFE6)); +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#else +#ifndef SA1_OPCODES + CPU.Cycles += 8; +#endif +#endif + } + else + { + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; + S9xSetPCBase (S9xGetWord (0xFFFE)); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles += 6; +#endif +#endif + } +} +/**********************************************************************************************/ + +/* BRL ************************************************************************************** */ +static void Op82 (void) +{ + RelativeLong (); + S9xSetPCBase (ICPU.ShiftedPB + OpAddress); +} +/**********************************************************************************************/ + +/* IRQ *************************************************************************************** */ +void S9xOpcode_IRQ (void) +{ +#ifdef DEBUGGER + if (CPU.Flags & TRACE_FLAG) + S9xTraceMessage ("*** IRQ"); +#endif + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; +#ifdef SA1_OPCODES + S9xSA1SetPCBase (Memory.FillRAM [0x2207] | + (Memory.FillRAM [0x2208] << 8)); +#else + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40)) + S9xSetPCBase (Memory.FillRAM [0x220e] | + (Memory.FillRAM [0x220f] << 8)); + else + S9xSetPCBase (S9xGetWord (0xFFEE)); +#endif +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#else +#ifndef SA1_OPCODES + CPU.Cycles += 8; +#endif +#endif + } + else + { + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; +#ifdef SA1_OPCODES + S9xSA1SetPCBase (Memory.FillRAM [0x2207] | + (Memory.FillRAM [0x2208] << 8)); +#else + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40)) + S9xSetPCBase (Memory.FillRAM [0x220e] | + (Memory.FillRAM [0x220f] << 8)); + else + S9xSetPCBase (S9xGetWord (0xFFFE)); +#endif +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles += 6; +#endif +#endif + } +} + +/**********************************************************************************************/ + +/* NMI *************************************************************************************** */ +void S9xOpcode_NMI (void) +{ +#ifdef DEBUGGER + if (CPU.Flags & TRACE_FLAG) + S9xTraceMessage ("*** NMI"); +#endif + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; +#ifdef SA1_OPCODES + S9xSA1SetPCBase (Memory.FillRAM [0x2205] | + (Memory.FillRAM [0x2206] << 8)); +#else + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20)) + S9xSetPCBase (Memory.FillRAM [0x220c] | + (Memory.FillRAM [0x220d] << 8)); + else + S9xSetPCBase (S9xGetWord (0xFFEA)); +#endif +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#else +#ifndef SA1_OPCODES + CPU.Cycles += 8; +#endif +#endif + } + else + { + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; +#ifdef SA1_OPCODES + S9xSA1SetPCBase (Memory.FillRAM [0x2205] | + (Memory.FillRAM [0x2206] << 8)); +#else + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20)) + S9xSetPCBase (Memory.FillRAM [0x220c] | + (Memory.FillRAM [0x220d] << 8)); + else + S9xSetPCBase (S9xGetWord (0xFFFA)); +#endif +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles += 6; +#endif +#endif + } +} +/**********************************************************************************************/ + +/* COP *************************************************************************************** */ +static void Op02 (void) +{ +#ifdef DEBUGGER + if (CPU.Flags & TRACE_FLAG) + S9xTraceMessage ("*** COP"); +#endif + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase + 1); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; + S9xSetPCBase (S9xGetWord (0xFFE4)); +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#else +#ifndef SA1_OPCODES + CPU.Cycles += 8; +#endif +#endif + } + else + { + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; + S9xSetPCBase (S9xGetWord (0xFFF4)); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else +#ifndef SA1_OPCODES + CPU.Cycles += 6; +#endif +#endif + } +} +/**********************************************************************************************/ + +/* JML *************************************************************************************** */ +static void OpDC (void) +{ + AbsoluteIndirectLong (); + Registers.PB = (uint8) (OpAddress >> 16); + ICPU.ShiftedPB = OpAddress & 0xff0000; + S9xSetPCBase (OpAddress); +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif +} + +static void Op5C (void) +{ + AbsoluteLong (); + Registers.PB = (uint8) (OpAddress >> 16); + ICPU.ShiftedPB = OpAddress & 0xff0000; + S9xSetPCBase (OpAddress); +} +/**********************************************************************************************/ + +/* JMP *************************************************************************************** */ +static void Op4C (void) +{ + Absolute (); + S9xSetPCBase (ICPU.ShiftedPB + (OpAddress & 0xffff)); +#if defined(CPU_SHUTDOWN) && defined(SA1_OPCODES) + CPUShutdown (); +#endif +} + +static void Op6C (void) +{ + AbsoluteIndirect (); + S9xSetPCBase (ICPU.ShiftedPB + (OpAddress & 0xffff)); +} + +static void Op7C (void) +{ + AbsoluteIndexedIndirect (); + S9xSetPCBase (ICPU.ShiftedPB + OpAddress); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} +/**********************************************************************************************/ + +/* JSL/RTL *********************************************************************************** */ +static void Op22 (void) +{ + AbsoluteLong (); + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase - 1); + Registers.PB = (uint8) (OpAddress >> 16); + ICPU.ShiftedPB = OpAddress & 0xff0000; + S9xSetPCBase (OpAddress); +} + +static void Op6B (void) +{ + PullW (Registers.PC); + PullB (Registers.PB); + ICPU.ShiftedPB = Registers.PB << 16; + S9xSetPCBase (ICPU.ShiftedPB + ((Registers.PC + 1) & 0xffff)); +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif +} +/**********************************************************************************************/ + +/* JSR/RTS *********************************************************************************** */ +static void Op20 (void) +{ + Absolute (); + PushW (CPU.PC - CPU.PCBase - 1); + S9xSetPCBase (ICPU.ShiftedPB + (OpAddress & 0xffff)); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void OpFC (void) +{ + AbsoluteIndexedIndirect (); + PushW (CPU.PC - CPU.PCBase - 1); + S9xSetPCBase (ICPU.ShiftedPB + OpAddress); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif +} + +static void Op60 (void) +{ + PullW (Registers.PC); + S9xSetPCBase (ICPU.ShiftedPB + ((Registers.PC + 1) & 0xffff)); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE * 3; +#endif +} + +/**********************************************************************************************/ + +/* MVN/MVP *********************************************************************************** */ +static void Op54X1 (void) +{ + uint32 SrcBank; + +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2 + TWO_CYCLES; +#endif + + Registers.DB = *CPU.PC++; + ICPU.ShiftedDB = Registers.DB << 16; + SrcBank = *CPU.PC++; + + S9xSetByte (S9xGetByte ((SrcBank << 16) + Registers.X.W), + ICPU.ShiftedDB + Registers.Y.W); + + Registers.XL++; + Registers.YL++; + Registers.A.W--; + if (Registers.A.W != 0xffff) + CPU.PC -= 3; +} + +static void Op54X0 (void) +{ + uint32 SrcBank; + +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2 + TWO_CYCLES; +#endif + + Registers.DB = *CPU.PC++; + ICPU.ShiftedDB = Registers.DB << 16; + SrcBank = *CPU.PC++; + + S9xSetByte (S9xGetByte ((SrcBank << 16) + Registers.X.W), + ICPU.ShiftedDB + Registers.Y.W); + + Registers.X.W++; + Registers.Y.W++; + Registers.A.W--; + if (Registers.A.W != 0xffff) + CPU.PC -= 3; +} + +static void Op44X1 (void) +{ + uint32 SrcBank; + +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2 + TWO_CYCLES; +#endif + Registers.DB = *CPU.PC++; + ICPU.ShiftedDB = Registers.DB << 16; + SrcBank = *CPU.PC++; + S9xSetByte (S9xGetByte ((SrcBank << 16) + Registers.X.W), + ICPU.ShiftedDB + Registers.Y.W); + + Registers.XL--; + Registers.YL--; + Registers.A.W--; + if (Registers.A.W != 0xffff) + CPU.PC -= 3; +} + +static void Op44X0 (void) +{ + uint32 SrcBank; + +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeedx2 + TWO_CYCLES; +#endif + Registers.DB = *CPU.PC++; + ICPU.ShiftedDB = Registers.DB << 16; + SrcBank = *CPU.PC++; + S9xSetByte (S9xGetByte ((SrcBank << 16) + Registers.X.W), + ICPU.ShiftedDB + Registers.Y.W); + + Registers.X.W--; + Registers.Y.W--; + Registers.A.W--; + if (Registers.A.W != 0xffff) + CPU.PC -= 3; +} + +/**********************************************************************************************/ + +/* REP/SEP *********************************************************************************** */ +static void OpC2 (void) +{ + uint8 Work8 = ~*CPU.PC++; + Registers.PL &= Work8; + ICPU._Carry &= Work8; + ICPU._Overflow &= (Work8 >> 6); + ICPU._Negative &= Work8; + ICPU._Zero |= ~Work8 & Zero; + +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed + ONE_CYCLE; +#endif + if (CheckEmulation()) + { + SetFlags (MemoryFlag | IndexFlag); + missing.emulate6502 = 1; + } + if (CheckIndex ()) + { + Registers.XH = 0; + Registers.YH = 0; + } + S9xFixCycles(); +/* CHECK_FOR_IRQ(); */ +} + +static void OpE2 (void) +{ + uint8 Work8 = *CPU.PC++; + Registers.PL |= Work8; + ICPU._Carry |= Work8 & 1; + ICPU._Overflow |= (Work8 >> 6) & 1; + ICPU._Negative |= Work8; + if (Work8 & Zero) + ICPU._Zero = 0; +#ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed + ONE_CYCLE; +#endif + if (CheckEmulation()) + { + SetFlags (MemoryFlag | IndexFlag); + missing.emulate6502 = 1; + } + if (CheckIndex ()) + { + Registers.XH = 0; + Registers.YH = 0; + } + S9xFixCycles(); +} +/**********************************************************************************************/ + +/* XBA *************************************************************************************** */ +static void OpEB (void) +{ + uint8 Work8 = Registers.AL; + Registers.AL = Registers.AH; + Registers.AH = Work8; + + SetZN8 (Registers.AL); +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif +} +/**********************************************************************************************/ + +/* RTI *************************************************************************************** */ +static void Op40 (void) +{ + PullB (Registers.PL); + S9xUnpackStatus (); + PullW (Registers.PC); + if (!CheckEmulation()) + { + PullB (Registers.PB); + ICPU.ShiftedPB = Registers.PB << 16; + } + else + { + SetFlags (MemoryFlag | IndexFlag); + missing.emulate6502 = 1; + } + S9xSetPCBase (ICPU.ShiftedPB + Registers.PC); + + if (CheckIndex ()) + { + Registers.XH = 0; + Registers.YH = 0; + } +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + S9xFixCycles(); +/* CHECK_FOR_IRQ(); */ +} + +/**********************************************************************************************/ + +/* STP/WAI/DB ******************************************************************************** */ +// WAI +static void OpCB (void) +{ + if (CPU.IRQActive) + { +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#else +#ifndef SA1_OPCODES + CPU.Cycles += 2; +#endif +#endif + } + else + { + CPU.WaitingForInterrupt = TRUE; + CPU.PC--; +#ifdef CPU_SHUTDOWN +#ifndef SA1_OPCODES + if (Settings.Shutdown) + { + CPU.Cycles = CPU.NextEvent; + asm_APU_EXECUTE2(); + } +#else + if (Settings.Shutdown) + { + SA1.CPUExecuting = FALSE; + SA1.Executing = FALSE; + } +#endif +#endif + } +} + +// STP +static void OpDB (void) +{ + CPU.PC--; + CPU.Flags |= DEBUG_MODE_FLAG; +} + +// Reserved S9xOpcode +static void Op42 (void) { +#ifndef SA1_OPCODES + uint8 b; + + CPU.WaitAddress = NULL; + CPU.Cycles = CPU.NextEvent; + asm_APU_EXECUTE2(); + //debug_log("toto"); + b=*CPU.PC++; + + //relative + signed char s9xInt8=0xF0|(b&0xF); + #ifdef VAR_CYCLES + CPU.Cycles += CPU.MemSpeed; + #endif + OpAddress = ((int) (CPU.PC - CPU.PCBase) + s9xInt8) & 0xffff; + + switch (b&0xF0) { + case 0x10: //BPL + BranchCheck1 (); + if (!CheckNegative ()) { + CPU.PC = CPU.PCBase + OpAddress; + #ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; + #else + #ifndef SA1_OPCODES + CPU.Cycles++; + #endif + #endif + CPUShutdown (); + } + return; + case 0x30: //BMI + BranchCheck1 (); + if (CheckNegative ()) { + CPU.PC = CPU.PCBase + OpAddress; + #ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; + #else + #ifndef SA1_OPCODES + CPU.Cycles++; + #endif + #endif + CPUShutdown (); + } + return; + case 0x50: //BVC + BranchCheck0 (); + if (!CheckOverflow ()) { + CPU.PC = CPU.PCBase + OpAddress; + #ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; + #else + #ifndef SA1_OPCODES + CPU.Cycles++; + #endif + #endif + CPUShutdown (); + } + return; + case 0x70: //BVS + BranchCheck0 (); + if (CheckOverflow ()) { + CPU.PC = CPU.PCBase + OpAddress; + #ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; + #else + #ifndef SA1_OPCODES + CPU.Cycles++; + #endif + #endif + CPUShutdown (); + } + return; + case 0x80: //BRA + //op80 + CPU.PC = CPU.PCBase + OpAddress; + #ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; + #else + #ifndef SA1_OPCODES + CPU.Cycles++; + #endif + #endif + CPUShutdown (); + return; + case 0x90: //BCC + BranchCheck0 (); + if (!CheckCarry ()) { + CPU.PC = CPU.PCBase + OpAddress; + #ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; + #else + #ifndef SA1_OPCODES + CPU.Cycles++; + #endif + #endif + CPUShutdown (); + } + return; + case 0xB0: //BCS + BranchCheck0 (); + if (CheckCarry ()) { + CPU.PC = CPU.PCBase + OpAddress; + #ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; + #else + #ifndef SA1_OPCODES + CPU.Cycles++; + #endif + #endif + CPUShutdown (); + } + return; + case 0xD0: //BNE + BranchCheck1 (); + if (!CheckZero ()) { + CPU.PC = CPU.PCBase + OpAddress; + #ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; + #else + #ifndef SA1_OPCODES + CPU.Cycles++; + #endif + #endif + CPUShutdown (); + } + return; + case 0xF0: //BEQ + BranchCheck2 (); + if (CheckZero ()) { + CPU.PC = CPU.PCBase + OpAddress; + #ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; + #else + #ifndef SA1_OPCODES + CPU.Cycles++; + #endif + #endif + CPUShutdown (); + } + return; + } +#endif +} + +/**********************************************************************************************/ + +/**********************************************************************************************/ +/* CPU-S9xOpcodes Definitions */ +/**********************************************************************************************/ +struct SOpcodes S9xOpcodesM1X1[256] = +{ + {Op00}, {Op01M1}, {Op02}, {Op03M1}, {Op04M1}, + {Op05M1}, {Op06M1}, {Op07M1}, {Op08}, {Op09M1}, + {Op0AM1}, {Op0B}, {Op0CM1}, {Op0DM1}, {Op0EM1}, + {Op0FM1}, {Op10}, {Op11M1}, {Op12M1}, {Op13M1}, + {Op14M1}, {Op15M1}, {Op16M1}, {Op17M1}, {Op18}, + {Op19M1}, {Op1AM1}, {Op1B}, {Op1CM1}, {Op1DM1}, + {Op1EM1}, {Op1FM1}, {Op20}, {Op21M1}, {Op22}, + {Op23M1}, {Op24M1}, {Op25M1}, {Op26M1}, {Op27M1}, + {Op28}, {Op29M1}, {Op2AM1}, {Op2B}, {Op2CM1}, + {Op2DM1}, {Op2EM1}, {Op2FM1}, {Op30}, {Op31M1}, + {Op32M1}, {Op33M1}, {Op34M1}, {Op35M1}, {Op36M1}, + {Op37M1}, {Op38}, {Op39M1}, {Op3AM1}, {Op3B}, + {Op3CM1}, {Op3DM1}, {Op3EM1}, {Op3FM1}, {Op40}, + {Op41M1}, {Op42}, {Op43M1}, {Op44X1}, {Op45M1}, + {Op46M1}, {Op47M1}, {Op48M1}, {Op49M1}, {Op4AM1}, + {Op4B}, {Op4C}, {Op4DM1}, {Op4EM1}, {Op4FM1}, + {Op50}, {Op51M1}, {Op52M1}, {Op53M1}, {Op54X1}, + {Op55M1}, {Op56M1}, {Op57M1}, {Op58}, {Op59M1}, + {Op5AX1}, {Op5B}, {Op5C}, {Op5DM1}, {Op5EM1}, + {Op5FM1}, {Op60}, {Op61M1}, {Op62}, {Op63M1}, + {Op64M1}, {Op65M1}, {Op66M1}, {Op67M1}, {Op68M1}, + {Op69M1}, {Op6AM1}, {Op6B}, {Op6C}, {Op6DM1}, + {Op6EM1}, {Op6FM1}, {Op70}, {Op71M1}, {Op72M1}, + {Op73M1}, {Op74M1}, {Op75M1}, {Op76M1}, {Op77M1}, + {Op78}, {Op79M1}, {Op7AX1}, {Op7B}, {Op7C}, + {Op7DM1}, {Op7EM1}, {Op7FM1}, {Op80}, {Op81M1}, + {Op82}, {Op83M1}, {Op84X1}, {Op85M1}, {Op86X1}, + {Op87M1}, {Op88X1}, {Op89M1}, {Op8AM1}, {Op8B}, + {Op8CX1}, {Op8DM1}, {Op8EX1}, {Op8FM1}, {Op90}, + {Op91M1}, {Op92M1}, {Op93M1}, {Op94X1}, {Op95M1}, + {Op96X1}, {Op97M1}, {Op98M1}, {Op99M1}, {Op9A}, + {Op9BX1}, {Op9CM1}, {Op9DM1}, {Op9EM1}, {Op9FM1}, + {OpA0X1}, {OpA1M1}, {OpA2X1}, {OpA3M1}, {OpA4X1}, + {OpA5M1}, {OpA6X1}, {OpA7M1}, {OpA8X1}, {OpA9M1}, + {OpAAX1}, {OpAB}, {OpACX1}, {OpADM1}, {OpAEX1}, + {OpAFM1}, {OpB0}, {OpB1M1}, {OpB2M1}, {OpB3M1}, + {OpB4X1}, {OpB5M1}, {OpB6X1}, {OpB7M1}, {OpB8}, + {OpB9M1}, {OpBAX1}, {OpBBX1}, {OpBCX1}, {OpBDM1}, + {OpBEX1}, {OpBFM1}, {OpC0X1}, {OpC1M1}, {OpC2}, + {OpC3M1}, {OpC4X1}, {OpC5M1}, {OpC6M1}, {OpC7M1}, + {OpC8X1}, {OpC9M1}, {OpCAX1}, {OpCB}, {OpCCX1}, + {OpCDM1}, {OpCEM1}, {OpCFM1}, {OpD0}, {OpD1M1}, + {OpD2M1}, {OpD3M1}, {OpD4}, {OpD5M1}, {OpD6M1}, + {OpD7M1}, {OpD8}, {OpD9M1}, {OpDAX1}, {OpDB}, + {OpDC}, {OpDDM1}, {OpDEM1}, {OpDFM1}, {OpE0X1}, + {OpE1M1}, {OpE2}, {OpE3M1}, {OpE4X1}, {OpE5M1}, + {OpE6M1}, {OpE7M1}, {OpE8X1}, {OpE9M1}, {OpEA}, + + {OpEB}, {OpECX1}, {OpEDM1}, {OpEEM1}, {OpEFM1}, + {OpF0}, {OpF1M1}, {OpF2M1}, {OpF3M1}, {OpF4}, + {OpF5M1}, {OpF6M1}, {OpF7M1}, {OpF8}, {OpF9M1}, + {OpFAX1}, {OpFB}, {OpFC}, {OpFDM1}, {OpFEM1}, + {OpFFM1} +}; + +struct SOpcodes S9xOpcodesM1X0[256] = +{ + {Op00}, {Op01M1}, {Op02}, {Op03M1}, {Op04M1}, + {Op05M1}, {Op06M1}, {Op07M1}, {Op08}, {Op09M1}, + {Op0AM1}, {Op0B}, {Op0CM1}, {Op0DM1}, {Op0EM1}, + {Op0FM1}, {Op10}, {Op11M1}, {Op12M1}, {Op13M1}, + {Op14M1}, {Op15M1}, {Op16M1}, {Op17M1}, {Op18}, + {Op19M1}, {Op1AM1}, {Op1B}, {Op1CM1}, {Op1DM1}, + {Op1EM1}, {Op1FM1}, {Op20}, {Op21M1}, {Op22}, + {Op23M1}, {Op24M1}, {Op25M1}, {Op26M1}, {Op27M1}, + {Op28}, {Op29M1}, {Op2AM1}, {Op2B}, {Op2CM1}, + {Op2DM1}, {Op2EM1}, {Op2FM1}, {Op30}, {Op31M1}, + {Op32M1}, {Op33M1}, {Op34M1}, {Op35M1}, {Op36M1}, + {Op37M1}, {Op38}, {Op39M1}, {Op3AM1}, {Op3B}, + {Op3CM1}, {Op3DM1}, {Op3EM1}, {Op3FM1}, {Op40}, + {Op41M1}, {Op42}, {Op43M1}, {Op44X0}, {Op45M1}, + {Op46M1}, {Op47M1}, {Op48M1}, {Op49M1}, {Op4AM1}, + {Op4B}, {Op4C}, {Op4DM1}, {Op4EM1}, {Op4FM1}, + {Op50}, {Op51M1}, {Op52M1}, {Op53M1}, {Op54X0}, + {Op55M1}, {Op56M1}, {Op57M1}, {Op58}, {Op59M1}, + {Op5AX0}, {Op5B}, {Op5C}, {Op5DM1}, {Op5EM1}, + {Op5FM1}, {Op60}, {Op61M1}, {Op62}, {Op63M1}, + {Op64M1}, {Op65M1}, {Op66M1}, {Op67M1}, {Op68M1}, + {Op69M1}, {Op6AM1}, {Op6B}, {Op6C}, {Op6DM1}, + {Op6EM1}, {Op6FM1}, {Op70}, {Op71M1}, {Op72M1}, + {Op73M1}, {Op74M1}, {Op75M1}, {Op76M1}, {Op77M1}, + {Op78}, {Op79M1}, {Op7AX0}, {Op7B}, {Op7C}, + {Op7DM1}, {Op7EM1}, {Op7FM1}, {Op80}, {Op81M1}, + {Op82}, {Op83M1}, {Op84X0}, {Op85M1}, {Op86X0}, + {Op87M1}, {Op88X0}, {Op89M1}, {Op8AM1}, {Op8B}, + {Op8CX0}, {Op8DM1}, {Op8EX0}, {Op8FM1}, {Op90}, + {Op91M1}, {Op92M1}, {Op93M1}, {Op94X0}, {Op95M1}, + {Op96X0}, {Op97M1}, {Op98M1}, {Op99M1}, {Op9A}, + {Op9BX0}, {Op9CM1}, {Op9DM1}, {Op9EM1}, {Op9FM1}, + {OpA0X0}, {OpA1M1}, {OpA2X0}, {OpA3M1}, {OpA4X0}, + {OpA5M1}, {OpA6X0}, {OpA7M1}, {OpA8X0}, {OpA9M1}, + {OpAAX0}, {OpAB}, {OpACX0}, {OpADM1}, {OpAEX0}, + {OpAFM1}, {OpB0}, {OpB1M1}, {OpB2M1}, {OpB3M1}, + {OpB4X0}, {OpB5M1}, {OpB6X0}, {OpB7M1}, {OpB8}, + {OpB9M1}, {OpBAX0}, {OpBBX0}, {OpBCX0}, {OpBDM1}, + {OpBEX0}, {OpBFM1}, {OpC0X0}, {OpC1M1}, {OpC2}, + {OpC3M1}, {OpC4X0}, {OpC5M1}, {OpC6M1}, {OpC7M1}, + {OpC8X0}, {OpC9M1}, {OpCAX0}, {OpCB}, {OpCCX0}, + {OpCDM1}, {OpCEM1}, {OpCFM1}, {OpD0}, {OpD1M1}, + {OpD2M1}, {OpD3M1}, {OpD4}, {OpD5M1}, {OpD6M1}, + {OpD7M1}, {OpD8}, {OpD9M1}, {OpDAX0}, {OpDB}, + {OpDC}, {OpDDM1}, {OpDEM1}, {OpDFM1}, {OpE0X0}, + {OpE1M1}, {OpE2}, {OpE3M1}, {OpE4X0}, {OpE5M1}, + {OpE6M1}, {OpE7M1}, {OpE8X0}, {OpE9M1}, {OpEA}, + {OpEB}, {OpECX0}, {OpEDM1}, {OpEEM1}, {OpEFM1}, + {OpF0}, {OpF1M1}, {OpF2M1}, {OpF3M1}, {OpF4}, + {OpF5M1}, {OpF6M1}, {OpF7M1}, {OpF8}, {OpF9M1}, + {OpFAX0}, {OpFB}, {OpFC}, {OpFDM1}, {OpFEM1}, + {OpFFM1} +}; + +struct SOpcodes S9xOpcodesM0X0[256] = +{ + {Op00}, {Op01M0}, {Op02}, {Op03M0}, {Op04M0}, + {Op05M0}, {Op06M0}, {Op07M0}, {Op08}, {Op09M0}, + {Op0AM0}, {Op0B}, {Op0CM0}, {Op0DM0}, {Op0EM0}, + {Op0FM0}, {Op10}, {Op11M0}, {Op12M0}, {Op13M0}, + {Op14M0}, {Op15M0}, {Op16M0}, {Op17M0}, {Op18}, + {Op19M0}, {Op1AM0}, {Op1B}, {Op1CM0}, {Op1DM0}, + {Op1EM0}, {Op1FM0}, {Op20}, {Op21M0}, {Op22}, + {Op23M0}, {Op24M0}, {Op25M0}, {Op26M0}, {Op27M0}, + {Op28}, {Op29M0}, {Op2AM0}, {Op2B}, {Op2CM0}, + {Op2DM0}, {Op2EM0}, {Op2FM0}, {Op30}, {Op31M0}, + {Op32M0}, {Op33M0}, {Op34M0}, {Op35M0}, {Op36M0}, + {Op37M0}, {Op38}, {Op39M0}, {Op3AM0}, {Op3B}, + {Op3CM0}, {Op3DM0}, {Op3EM0}, {Op3FM0}, {Op40}, + {Op41M0}, {Op42}, {Op43M0}, {Op44X0}, {Op45M0}, + {Op46M0}, {Op47M0}, {Op48M0}, {Op49M0}, {Op4AM0}, + {Op4B}, {Op4C}, {Op4DM0}, {Op4EM0}, {Op4FM0}, + {Op50}, {Op51M0}, {Op52M0}, {Op53M0}, {Op54X0}, + {Op55M0}, {Op56M0}, {Op57M0}, {Op58}, {Op59M0}, + {Op5AX0}, {Op5B}, {Op5C}, {Op5DM0}, {Op5EM0}, + {Op5FM0}, {Op60}, {Op61M0}, {Op62}, {Op63M0}, + {Op64M0}, {Op65M0}, {Op66M0}, {Op67M0}, {Op68M0}, + {Op69M0}, {Op6AM0}, {Op6B}, {Op6C}, {Op6DM0}, + {Op6EM0}, {Op6FM0}, {Op70}, {Op71M0}, {Op72M0}, + {Op73M0}, {Op74M0}, {Op75M0}, {Op76M0}, {Op77M0}, + {Op78}, {Op79M0}, {Op7AX0}, {Op7B}, {Op7C}, + {Op7DM0}, {Op7EM0}, {Op7FM0}, {Op80}, {Op81M0}, + {Op82}, {Op83M0}, {Op84X0}, {Op85M0}, {Op86X0}, + {Op87M0}, {Op88X0}, {Op89M0}, {Op8AM0}, {Op8B}, + {Op8CX0}, {Op8DM0}, {Op8EX0}, {Op8FM0}, {Op90}, + {Op91M0}, {Op92M0}, {Op93M0}, {Op94X0}, {Op95M0}, + {Op96X0}, {Op97M0}, {Op98M0}, {Op99M0}, {Op9A}, + {Op9BX0}, {Op9CM0}, {Op9DM0}, {Op9EM0}, {Op9FM0}, + {OpA0X0}, {OpA1M0}, {OpA2X0}, {OpA3M0}, {OpA4X0}, + {OpA5M0}, {OpA6X0}, {OpA7M0}, {OpA8X0}, {OpA9M0}, + {OpAAX0}, {OpAB}, {OpACX0}, {OpADM0}, {OpAEX0}, + {OpAFM0}, {OpB0}, {OpB1M0}, {OpB2M0}, {OpB3M0}, + {OpB4X0}, {OpB5M0}, {OpB6X0}, {OpB7M0}, {OpB8}, + {OpB9M0}, {OpBAX0}, {OpBBX0}, {OpBCX0}, {OpBDM0}, + {OpBEX0}, {OpBFM0}, {OpC0X0}, {OpC1M0}, {OpC2}, + {OpC3M0}, {OpC4X0}, {OpC5M0}, {OpC6M0}, {OpC7M0}, + {OpC8X0}, {OpC9M0}, {OpCAX0}, {OpCB}, {OpCCX0}, + {OpCDM0}, {OpCEM0}, {OpCFM0}, {OpD0}, {OpD1M0}, + {OpD2M0}, {OpD3M0}, {OpD4}, {OpD5M0}, {OpD6M0}, + {OpD7M0}, {OpD8}, {OpD9M0}, {OpDAX0}, {OpDB}, + {OpDC}, {OpDDM0}, {OpDEM0}, {OpDFM0}, {OpE0X0}, + {OpE1M0}, {OpE2}, {OpE3M0}, {OpE4X0}, {OpE5M0}, + {OpE6M0}, {OpE7M0}, {OpE8X0}, {OpE9M0}, {OpEA}, + {OpEB}, {OpECX0}, {OpEDM0}, {OpEEM0}, {OpEFM0}, + {OpF0}, {OpF1M0}, {OpF2M0}, {OpF3M0}, {OpF4}, + {OpF5M0}, {OpF6M0}, {OpF7M0}, {OpF8}, {OpF9M0}, + {OpFAX0}, {OpFB}, {OpFC}, {OpFDM0}, {OpFEM0}, + {OpFFM0} +}; + +struct SOpcodes S9xOpcodesM0X1[256] = +{ + {Op00}, {Op01M0}, {Op02}, {Op03M0}, {Op04M0}, + {Op05M0}, {Op06M0}, {Op07M0}, {Op08}, {Op09M0}, + {Op0AM0}, {Op0B}, {Op0CM0}, {Op0DM0}, {Op0EM0}, + {Op0FM0}, {Op10}, {Op11M0}, {Op12M0}, {Op13M0}, + {Op14M0}, {Op15M0}, {Op16M0}, {Op17M0}, {Op18}, + {Op19M0}, {Op1AM0}, {Op1B}, {Op1CM0}, {Op1DM0}, + {Op1EM0}, {Op1FM0}, {Op20}, {Op21M0}, {Op22}, + {Op23M0}, {Op24M0}, {Op25M0}, {Op26M0}, {Op27M0}, + {Op28}, {Op29M0}, {Op2AM0}, {Op2B}, {Op2CM0}, + {Op2DM0}, {Op2EM0}, {Op2FM0}, {Op30}, {Op31M0}, + {Op32M0}, {Op33M0}, {Op34M0}, {Op35M0}, {Op36M0}, + {Op37M0}, {Op38}, {Op39M0}, {Op3AM0}, {Op3B}, + {Op3CM0}, {Op3DM0}, {Op3EM0}, {Op3FM0}, {Op40}, + {Op41M0}, {Op42}, {Op43M0}, {Op44X1}, {Op45M0}, + {Op46M0}, {Op47M0}, {Op48M0}, {Op49M0}, {Op4AM0}, + {Op4B}, {Op4C}, {Op4DM0}, {Op4EM0}, {Op4FM0}, + {Op50}, {Op51M0}, {Op52M0}, {Op53M0}, {Op54X1}, + {Op55M0}, {Op56M0}, {Op57M0}, {Op58}, {Op59M0}, + {Op5AX1}, {Op5B}, {Op5C}, {Op5DM0}, {Op5EM0}, + {Op5FM0}, {Op60}, {Op61M0}, {Op62}, {Op63M0}, + {Op64M0}, {Op65M0}, {Op66M0}, {Op67M0}, {Op68M0}, + {Op69M0}, {Op6AM0}, {Op6B}, {Op6C}, {Op6DM0}, + {Op6EM0}, {Op6FM0}, {Op70}, {Op71M0}, {Op72M0}, + {Op73M0}, {Op74M0}, {Op75M0}, {Op76M0}, {Op77M0}, + {Op78}, {Op79M0}, {Op7AX1}, {Op7B}, {Op7C}, + {Op7DM0}, {Op7EM0}, {Op7FM0}, {Op80}, {Op81M0}, + {Op82}, {Op83M0}, {Op84X1}, {Op85M0}, {Op86X1}, + {Op87M0}, {Op88X1}, {Op89M0}, {Op8AM0}, {Op8B}, + {Op8CX1}, {Op8DM0}, {Op8EX1}, {Op8FM0}, {Op90}, + {Op91M0}, {Op92M0}, {Op93M0}, {Op94X1}, {Op95M0}, + {Op96X1}, {Op97M0}, {Op98M0}, {Op99M0}, {Op9A}, + {Op9BX1}, {Op9CM0}, {Op9DM0}, {Op9EM0}, {Op9FM0}, + {OpA0X1}, {OpA1M0}, {OpA2X1}, {OpA3M0}, {OpA4X1}, + {OpA5M0}, {OpA6X1}, {OpA7M0}, {OpA8X1}, {OpA9M0}, + {OpAAX1}, {OpAB}, {OpACX1}, {OpADM0}, {OpAEX1}, + {OpAFM0}, {OpB0}, {OpB1M0}, {OpB2M0}, {OpB3M0}, + {OpB4X1}, {OpB5M0}, {OpB6X1}, {OpB7M0}, {OpB8}, + {OpB9M0}, {OpBAX1}, {OpBBX1}, {OpBCX1}, {OpBDM0}, + {OpBEX1}, {OpBFM0}, {OpC0X1}, {OpC1M0}, {OpC2}, + {OpC3M0}, {OpC4X1}, {OpC5M0}, {OpC6M0}, {OpC7M0}, + {OpC8X1}, {OpC9M0}, {OpCAX1}, {OpCB}, {OpCCX1}, + {OpCDM0}, {OpCEM0}, {OpCFM0}, {OpD0}, {OpD1M0}, + {OpD2M0}, {OpD3M0}, {OpD4}, {OpD5M0}, {OpD6M0}, + {OpD7M0}, {OpD8}, {OpD9M0}, {OpDAX1}, {OpDB}, + {OpDC}, {OpDDM0}, {OpDEM0}, {OpDFM0}, {OpE0X1}, + {OpE1M0}, {OpE2}, {OpE3M0}, {OpE4X1}, {OpE5M0}, + {OpE6M0}, {OpE7M0}, {OpE8X1}, {OpE9M0}, {OpEA}, + {OpEB}, {OpECX1}, {OpEDM0}, {OpEEM0}, {OpEFM0}, + {OpF0}, {OpF1M0}, {OpF2M0}, {OpF3M0}, {OpF4}, + {OpF5M0}, {OpF6M0}, {OpF7M0}, {OpF8}, {OpF9M0}, + {OpFAX1}, {OpFB}, {OpFC}, {OpFDM0}, {OpFEM0}, + {OpFFM0} +}; + diff --git a/src/cpuops.h b/src/cpuops.h new file mode 100644 index 0000000..542c9c7 --- /dev/null +++ b/src/cpuops.h @@ -0,0 +1,50 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _CPUOPS_H_ +#define _CPUOPS_H_ +void S9xOpcode_NMI (); +void S9xOpcode_IRQ (); + +#define CHECK_FOR_IRQ() \ +if (CPU.IRQActive && !CheckFlag (IRQ) && !Settings.DisableIRQ) \ + S9xOpcode_IRQ() + +#endif diff --git a/src/data.cpp b/src/data.cpp new file mode 100644 index 0000000..2a25eab --- /dev/null +++ b/src/data.cpp @@ -0,0 +1,489 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" +/* +uint8 add32_32 [32][32] = { +{ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e, + 0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f}, +{ 0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e, + 0x1f,0x1f}, +{ 0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10, + 0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f, + 0x1f,0x1f}, +{ 0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11, + 0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12, + 0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14, + 0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15, + 0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16, + 0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18, + 0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19, + 0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a, + 0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b, + 0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c, + 0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x1b,0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x1c,0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x1d,0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x1e,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f}, +{ 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f,0x1f, + 0x1f,0x1f} +}; + +uint8 add32_32_half [32][32] = { +{ 0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07, + 0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e, + 0x0f,0x0f}, +{ 0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07, + 0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f, + 0x0f,0x10}, +{ 0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08, + 0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f, + 0x10,0x10}, +{ 0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08, + 0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10, + 0x10,0x11}, +{ 0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09, + 0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10, + 0x11,0x11}, +{ 0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09, + 0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11, + 0x11,0x12}, +{ 0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a, + 0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11, + 0x12,0x12}, +{ 0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a, + 0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12, + 0x12,0x13}, +{ 0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b, + 0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12, + 0x13,0x13}, +{ 0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b, + 0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13, + 0x13,0x14}, +{ 0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c, + 0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13, + 0x14,0x14}, +{ 0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c, + 0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14, + 0x14,0x15}, +{ 0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d, + 0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14, + 0x15,0x15}, +{ 0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d, + 0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15, + 0x15,0x16}, +{ 0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e, + 0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15, + 0x16,0x16}, +{ 0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e, + 0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16, + 0x16,0x17}, +{ 0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f, + 0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16, + 0x17,0x17}, +{ 0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f, + 0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16,0x17, + 0x17,0x18}, +{ 0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10, + 0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16,0x17,0x17, + 0x18,0x18}, +{ 0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10, + 0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16,0x17,0x17,0x18, + 0x18,0x19}, +{ 0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11, + 0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18, + 0x19,0x19}, +{ 0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11, + 0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x19, + 0x19,0x1a}, +{ 0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12, + 0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x19,0x19, + 0x1a,0x1a}, +{ 0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12, + 0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1a, + 0x1a,0x1b}, +{ 0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13, + 0x13,0x14,0x14,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1a,0x1a, + 0x1b,0x1b}, +{ 0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13, + 0x14,0x14,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b, + 0x1b,0x1c}, +{ 0x0d,0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14, + 0x14,0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b,0x1b, + 0x1c,0x1c}, +{ 0x0d,0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14, + 0x15,0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b,0x1b,0x1c, + 0x1c,0x1d}, +{ 0x0e,0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15, + 0x15,0x16,0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c, + 0x1d,0x1d}, +{ 0x0e,0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15, + 0x16,0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d, + 0x1d,0x1e}, +{ 0x0f,0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16, + 0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d, + 0x1e,0x1e}, +{ 0x0f,0x10,0x10,0x11,0x11,0x12,0x12,0x13,0x13,0x14,0x14,0x15,0x15,0x16,0x16, + 0x17,0x17,0x18,0x18,0x19,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1e, + 0x1e,0x1f} +}; +uint8 sub32_32 [32][32] = { +{ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e, + 0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f}, +{ 0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d, + 0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c, + 0x1d,0x1e}, +{ 0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c, + 0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b, + 0x1c,0x1d}, +{ 0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b, + 0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a, + 0x1b,0x1c}, +{ 0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a, + 0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19, + 0x1a,0x1b}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18, + 0x19,0x1a}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08, + 0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + 0x18,0x19}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16, + 0x17,0x18}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06, + 0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15, + 0x16,0x17}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05, + 0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14, + 0x15,0x16}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04, + 0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03, + 0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12, + 0x13,0x14}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02, + 0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11, + 0x12,0x13}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, + 0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10, + 0x11,0x12}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, + 0x10,0x11}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e, + 0x0f,0x10}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d, + 0x0e,0x0f}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c, + 0x0d,0x0e}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b, + 0x0c,0x0d}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a, + 0x0b,0x0c}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08, + 0x09,0x0a}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0x08,0x09}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06, + 0x07,0x08}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05, + 0x06,0x07}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04, + 0x05,0x06}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03, + 0x04,0x05}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02, + 0x03,0x04}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, + 0x02,0x03}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x02}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x01}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00} +}; + +uint8 sub32_32_half [32][32] = { +{ 0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07, + 0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e, + 0x0f,0x0f}, +{ 0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06, + 0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e, + 0x0e,0x0f}, +{ 0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06, + 0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d, + 0x0e,0x0e}, +{ 0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05, + 0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d, + 0x0d,0x0e}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05, + 0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c, + 0x0d,0x0d}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04, + 0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c, + 0x0c,0x0d}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04, + 0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b, + 0x0c,0x0c}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03, + 0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b, + 0x0b,0x0c}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03, + 0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a, + 0x0b,0x0b}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02, + 0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09,0x0a, + 0x0a,0x0b}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02, + 0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09,0x09, + 0x0a,0x0a}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01, + 0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08,0x09, + 0x09,0x0a}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, + 0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08,0x08, + 0x09,0x09}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07,0x08, + 0x08,0x09}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07, + 0x08,0x08}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07, + 0x07,0x08}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06, + 0x07,0x07}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06, + 0x06,0x07}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05, + 0x06,0x06}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05, + 0x05,0x06}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04, + 0x05,0x05}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04, + 0x04,0x05}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03, + 0x04,0x04}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02,0x03, + 0x03,0x04}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x02, + 0x03,0x03}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02, + 0x02,0x03}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01, + 0x02,0x02}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, + 0x01,0x02}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x01}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x01}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00} +}; +*/ + +uint8 mul_brightness [16][32] = { +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00}, +{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02,0x02,0x02,0x02,0x02,0x02,0x02, + 0x02,0x02}, +{ 0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x02,0x02,0x02, + 0x02,0x02,0x02,0x02,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x04,0x04, + 0x04,0x04}, +{ 0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x02,0x02,0x02,0x02,0x02,0x03,0x03, + 0x03,0x03,0x03,0x04,0x04,0x04,0x04,0x04,0x05,0x05,0x05,0x05,0x05,0x06,0x06, + 0x06,0x06}, +{ 0x00,0x00,0x01,0x01,0x01,0x01,0x02,0x02,0x02,0x02,0x03,0x03,0x03,0x03,0x04, + 0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x06,0x06,0x06,0x07,0x07,0x07,0x07,0x08, + 0x08,0x08}, +{ 0x00,0x00,0x01,0x01,0x01,0x02,0x02,0x02,0x03,0x03,0x03,0x04,0x04,0x04,0x05, + 0x05,0x05,0x06,0x06,0x06,0x07,0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x09,0x0a, + 0x0a,0x0a}, +{ 0x00,0x00,0x01,0x01,0x02,0x02,0x02,0x03,0x03,0x04,0x04,0x04,0x05,0x05,0x06, + 0x06,0x06,0x07,0x07,0x08,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0a,0x0b,0x0b,0x0c, + 0x0c,0x0c}, +{ 0x00,0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07, + 0x07,0x07,0x08,0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e, + 0x0e,0x0e}, +{ 0x00,0x01,0x01,0x02,0x02,0x03,0x03,0x04,0x04,0x05,0x05,0x06,0x06,0x07,0x07, + 0x08,0x09,0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x0f, + 0x10,0x11}, +{ 0x00,0x01,0x01,0x02,0x02,0x03,0x04,0x04,0x05,0x05,0x06,0x07,0x07,0x08,0x08, + 0x09,0x0a,0x0a,0x0b,0x0b,0x0c,0x0d,0x0d,0x0e,0x0e,0x0f,0x10,0x10,0x11,0x11, + 0x12,0x13}, +{ 0x00,0x01,0x01,0x02,0x03,0x03,0x04,0x05,0x05,0x06,0x07,0x07,0x08,0x09,0x09, + 0x0a,0x0b,0x0b,0x0c,0x0d,0x0d,0x0e,0x0f,0x0f,0x10,0x11,0x11,0x12,0x13,0x13, + 0x14,0x15}, +{ 0x00,0x01,0x01,0x02,0x03,0x04,0x04,0x05,0x06,0x07,0x07,0x08,0x09,0x0a,0x0a, + 0x0b,0x0c,0x0c,0x0d,0x0e,0x0f,0x0f,0x10,0x11,0x12,0x12,0x13,0x14,0x15,0x15, + 0x16,0x17}, +{ 0x00,0x01,0x02,0x02,0x03,0x04,0x05,0x06,0x06,0x07,0x08,0x09,0x0a,0x0a,0x0b, + 0x0c,0x0d,0x0e,0x0e,0x0f,0x10,0x11,0x12,0x12,0x13,0x14,0x15,0x16,0x16,0x17, + 0x18,0x19}, +{ 0x00,0x01,0x02,0x03,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0a,0x0b,0x0c, + 0x0d,0x0e,0x0f,0x10,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x17,0x18,0x19, + 0x1a,0x1b}, +{ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d, + 0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b, + 0x1c,0x1d}, +{ 0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e, + 0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f} +}; + diff --git a/src/debug.h b/src/debug.h new file mode 100644 index 0000000..0b8cc79 --- /dev/null +++ b/src/debug.h @@ -0,0 +1,63 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _DEBUG_H_ +#define _DEBUG_H_ + +START_EXTERN_C +void S9xDoDebug (); +void S9xTrace (); +void S9xSA1Trace (); +void S9xTraceMessage (const char *); + +// Structures +struct SBreakPoint{ + bool8 Enabled; + uint8 Bank; + uint16 Address; +}; + +uint8 S9xOPrint( char *Line, uint8 Bank, uint16 Address); +uint8 S9xSA1OPrint( char *Line, uint8 Bank, uint16 Address); + +extern struct SBreakPoint S9xBreakpoint[ 6]; +extern char *S9xMnemonics[256]; +END_EXTERN_C +#endif diff --git a/src/disk_img.c b/src/disk_img.c new file mode 100644 index 0000000..a8495fd --- /dev/null +++ b/src/disk_img.c @@ -0,0 +1,103 @@ +#define DISK_IMG_WIDTH 16 +#define DISK_IMG_HEIGHT 16 + +unsigned short int disk_img[] = { +0x3357, 0x3357, 0x3357, 0x3357, 0x3357, 0x3357, 0x3357, 0x3357, 0x3357, 0x3b77, 0x3b77, +0x3b77, 0x3b57, 0x3b97, 0x3356, 0x0000, 0x3357, 0xd71e, 0xd71e, 0xffdf, 0xf7df, 0xf7df, +0xf7bf, 0xef9f, 0xef9f, 0xf7df, 0xf7df, 0xef9f, 0xdf5f, 0xbe9d, 0x5c59, 0x3356, 0x3357, +0xd6fe, 0x855d, 0xf7df, 0xf7df, 0x6479, 0xef9f, 0xef9f, 0xf7bf, 0xffdf, 0xf7bf, 0xe77f, +0xdf3f, 0xbe9d, 0xbe9d, 0x3b97, 0x3357, 0xd6fe, 0x7d5d, 0xf7bf, 0xf7bf, 0x6479, 0xef9f, +0xefbf, 0xf7df, 0xf7df, 0xef9f, 0xdf5f, 0xdf3e, 0x7d1c, 0xc6bd, 0x3356, 0x3357, 0xcefe, +0x7d5c, 0xef9f, 0xef9f, 0x6479, 0xef9f, 0xf7df, 0xffdf, 0xefbf, 0xdf5f, 0xdf3e, 0xdf3e, +0x7d1c, 0xae1c, 0x3356, 0x3357, 0xcefe, 0x7d3c, 0xe77f, 0xe77f, 0xe77f, 0xefbf, 0xf7df, +0xf7bf, 0xe77f, 0xdf3e, 0xdf3e, 0xdf3e, 0x751b, 0xa5fc, 0x3336, 0x3357, 0xc6de, 0x7d3c, +0x6479, 0x6479, 0x6479, 0x6c99, 0x6c99, 0x6c99, 0x6479, 0x6479, 0x6479, 0x6479, 0x74fb, +0x9ddc, 0x3336, 0x3357, 0xc6de, 0x7d3c, 0x7d1c, 0x7d3c, 0x7d3c, 0x7d1c, 0x7d1c, 0x7d1c, +0x751b, 0x74fb, 0x74fb, 0x74fb, 0x74fb, 0x9dbb, 0x3336, 0x3357, 0xc6be, 0x7d1c, 0x7d1c, +0x7d1c, 0x7d1c, 0x7d3c, 0x7d1c, 0x7d1c, 0x751b, 0x74fb, 0x74fb, 0x74db, 0x74db, 0x959b, +0x3335, 0x3357, 0xbe9e, 0x7d1c, 0x7d1c, 0x7d1c, 0x7d1c, 0x7d1c, 0x7d1c, 0x74fb, 0x74fb, +0x74fb, 0x74db, 0x74db, 0x74da, 0x8d5a, 0x3315, 0x3357, 0xbe9d, 0x7d1c, 0xffdf, 0xffdf, +0xffdf, 0xffdf, 0xffdf, 0xffdf, 0xffdf, 0xffdf, 0xffdf, 0xffdf, 0x6cba, 0x8d3a, 0x3315, +0x3b57, 0xbe7d, 0x7d1c, 0xf7df, 0x8e0c, 0x8e0c, 0x8e0c, 0x8e0c, 0x8e0c, 0x8e0c, 0x8e0c, +0x8e0c, 0xf7df, 0x6c99, 0x8519, 0x3315, 0x3b77, 0xb67d, 0x7d1c, 0xf7df, 0xc6f7, 0xc6f7, +0xc6f7, 0xc6f7, 0xc6f7, 0xc6f7, 0xc6f7, 0xc6f7, 0xf7df, 0x6c99, 0x84f9, 0x3315, 0x3357, +0xb65d, 0x7d1c, 0xf7df, 0x8e0c, 0x8e0c, 0x8e0c, 0x8e0c, 0x8e0c, 0x8e0c, 0x8e0c, 0x8e0c, +0xf7df, 0x6479, 0x7cd9, 0x3314, 0x3357, 0xae3d, 0xae3d, 0xffdf, 0xffdf, 0xffdf, 0xffdf, +0xffdf, 0xffdf, 0xffdf, 0xffdf, 0xffdf, 0xffdf, 0x7cd9, 0x7cd8, 0x3314, 0x3357, 0x3357, +0x3357, 0x3356, 0x3356, 0x3336, 0x3336, 0x3336, 0x3335, 0x3315, 0x3315, 0x3315, 0x3315, +0x3314, 0x3314, 0x3315}; + +void Draw16x16Image(unsigned short *Screen, int x, int y, unsigned short *Img) { + + Screen = &Screen[(320 * y) + x]; + + asm volatile ( + " mov r0, #16 \n" + "1: \n" + #define FN() \ + " ldr r1, [%[image]], #4 \n"\ + " str r1, [%[screen]], #4 \n" + + FN() + FN() + FN() + FN() + FN() + FN() + FN() + FN() + + // Loop + " add %[screen], %[screen], #(640 - (16 * 2)) \n" + " subs r0, r0, #1 \n" + " bne 1b" + // output + : // none + // input + : [screen] "r" (Screen), + [image] "r" (Img) + // clobbered + : "r0", "r1", "cc" // r8 & flags + ); +#undef FN + +} + +void Draw16x16Square(unsigned short *Screen, int x, int y, unsigned char r, unsigned char g, unsigned char b) { + + Screen = &Screen[(320 * y) + x]; + int color = (((((unsigned int )r) * 0x1f) >> 8) << 11) | + (((((unsigned int )g) * 0x3f) >> 8) << 5) | + ((((unsigned int )b) * 0x1f) >> 8); + color = color | (color << 16); + + asm volatile ( + " mov r0, #16 \n" + "1: \n" + #define FN() \ + " str %[color], [%[screen]], #4 \n" + + FN() + FN() + FN() + FN() + FN() + FN() + FN() + FN() + + // Loop + " add %[screen], %[screen], #(640 - (16 * 2)) \n" + " subs r0, r0, #1 \n" + " bne 1b" + // output + : // none + // input + : [screen] "r" (Screen), + [color] "r" (color) + // clobbered + : "r0", "cc" // r8 & flags + ); +#undef FN + +} diff --git a/src/disk_img.h b/src/disk_img.h new file mode 100644 index 0000000..3095af0 --- /dev/null +++ b/src/disk_img.h @@ -0,0 +1,12 @@ +#ifdef __cplusplus +extern "C" { +#endif + +extern unsigned short int disk_img[]; +void Draw16x16Image(unsigned short *Screen, int x, int y, unsigned short *Img); +void Draw16x16Square(unsigned short *Screen, int x, int y, unsigned char r, unsigned char g, unsigned char b); + + +#ifdef __cplusplus +} +#endif diff --git a/src/display.h b/src/display.h new file mode 100644 index 0000000..753652b --- /dev/null +++ b/src/display.h @@ -0,0 +1,86 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _DISPLAY_H_ +#define _DISPLAY_H_ + +START_EXTERN_C +// Routines the port specific code has to implement +void S9xSetPalette (); +void S9xTextMode (); +void S9xGraphicsMode (); +char *S9xParseArgs (char **argv, int argc); +void S9xParseArg (char **argv, int &index, int argc); +void S9xExtraUsage (); +uint32 S9xReadJoypad (int which1_0_to_4); +bool8_32 S9xReadMousePosition (int which1_0_to_1, int &x, int &y, uint32 &buttons); +bool8_32 S9xReadSuperScopePosition (int &x, int &y, uint32 &buttons); + +void S9xUsage (); +void S9xInitDisplay (int argc, char **argv); +void S9xDeinitDisplay (); +void S9xInitInputDevices (); +void S9xSetTitle (const char *title); +void S9xProcessEvents (bool8_32 block); +void S9xPutImage (int width, int height); +void S9xParseDisplayArg (char **argv, int &index, int argc); +void S9xToggleSoundChannel (int channel); +void S9xSetInfoString (const char *string); +int S9xMinCommandLineArgs (); +void S9xNextController (); +bool8_32 S9xLoadROMImage (const char *string); +const char *S9xSelectFilename (const char *def, const char *dir, + const char *ext, const char *title); + +const char *S9xChooseFilename (bool8_32 read_only); +bool8_32 S9xOpenSnapshotFile (const char *base, bool8_32 read_only, STREAM *file); +void S9xCloseSnapshotFile (STREAM file); + +const char *S9xBasename (const char *filename); + +int S9xFStrcmp (FILE *, const char *); +const char *S9xGetHomeDirectory (); +const char *S9xGetSnapshotDirectory (); +const char *S9xGetROMDirectory (); +const char *S9xGetSRAMFilename (); +const char *S9xGetFilename (const char *extension); +END_EXTERN_C + +#endif diff --git a/src/dma.cpp b/src/dma.cpp new file mode 100644 index 0000000..bf102ed --- /dev/null +++ b/src/dma.cpp @@ -0,0 +1,945 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" + +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "missing.h" +#include "dma.h" +#include "apu.h" +#include "gfx.h" +#ifdef USE_SA1 +#include "sa1.h" +#endif + +//SDD1 +#include "sdd1emu.h" +uint8 buffer[0x10000]; +//SDD1// + +extern int HDMA_ModeByteCounts [8]; +extern uint8 *HDMAMemPointers [8]; +extern uint8 *HDMABasePointers [8]; + +#if defined(__linux__) || defined(__WIN32__) || defined(__GP2X__) || defined(__GIZ__) || defined(__WIZ__) +static int S9xCompareSDD1IndexEntries (const void *p1, const void *p2) +{ + return (*(uint32 *) p1 - *(uint32 *) p2); +} +#endif + +/**********************************************************************************************/ +/* S9xDoDMA() */ +/* This function preforms the general dma transfer */ +/**********************************************************************************************/ +void S9xDoDMA (uint8 Channel) +{ + uint8 Work; + + if (Channel > 7 || CPU.InDMA) + return; + + CPU.InDMA = TRUE; + bool8 in_sa1_dma = FALSE; + uint8 *in_sdd1_dma = NULL; + SDMA *d = &DMA[Channel]; + + int count = d->TransferBytes; + + if (count == 0) + count = 0x10000; + + int inc = d->AAddressFixed ? 0 : (!d->AAddressDecrement ? 1 : -1); + + if((d->ABank==0x7E||d->ABank==0x7F)&&d->BAddress==0x80) + { + d->AAddress+= d->TransferBytes; + goto update_address; + } + switch (d->BAddress) + { + case 0x18: + case 0x19: + if (IPPU.RenderThisFrame) +#ifdef __DEBUG__ + printf("FLUSH_REDRAW by DMA BAddress %x", d->BAddress); +#endif + FLUSH_REDRAW (); + + break; + } + + if (Settings.SDD1) + { + if (d->AAddressFixed && Memory.FillRAM [0x4801] > 0) + { + // Hacky support for pre-decompressed S-DD1 data + inc = !d->AAddressDecrement ? 1 : -1; + uint32 address = (((d->ABank << 16) | d->AAddress) & 0xfffff) << 4; + + address |= Memory.FillRAM [0x4804 + ((d->ABank - 0xc0) >> 4)]; + if(Settings.SDD1Pack) + { + uint8* in_ptr=GetBasePointer(((d->ABank << 16) | d->AAddress)); + in_ptr+=d->AAddress; + + SDD1_decompress(buffer,in_ptr,d->TransferBytes); + in_sdd1_dma=buffer; + } + else + { + #if defined (__GP2X__) || defined (__GIZ__) || defined (__WIZ__) + void *ptr = bsearch (&address, Memory.SDD1Index, + Memory.SDD1Entries, 12, S9xCompareSDD1IndexEntries); + if (ptr) + in_sdd1_dma = *(uint32 *) ((uint8 *) ptr + 4) + Memory.SDD1Data; + #else + uint8 *ptr = Memory.SDD1Index; + + for (uint32 e = 0; e < Memory.SDD1Entries; e++, ptr += 12) + { + if (address == *(uint32 *) ptr) + { + in_sdd1_dma = *(uint32 *) (ptr + 4) + Memory.SDD1Data; + break; + } + } + #endif + +/* if (!in_sdd1_dma) + { + // No matching decompressed data found. Must be some new + // graphics not encountered before. Log it if it hasn't been + // already. + uint8 *p = Memory.SDD1LoggedData; + bool8 found = FALSE; + uint8 SDD1Bank = Memory.FillRAM [0x4804 + ((d->ABank - 0xc0) >> 4)] | 0xf0; + + for (uint32 i = 0; i < Memory.SDD1LoggedDataCount; i++, p += 8) + { + if (*p == d->ABank || + *(p + 1) == (d->AAddress >> 8) && + *(p + 2) == (d->AAddress & 0xff) && + *(p + 3) == (count >> 8) && + *(p + 4) == (count & 0xff) && + *(p + 7) == SDD1Bank) + { + found = TRUE; + break; + } + } + if (!found && Memory.SDD1LoggedDataCount < MEMMAP_MAX_SDD1_LOGGED_ENTRIES) + { + *p = d->ABank; + *(p + 1) = d->AAddress >> 8; + *(p + 2) = d->AAddress & 0xff; + *(p + 3) = count >> 8; + *(p + 4) = count & 0xff; + *(p + 7) = SDD1Bank; + Memory.SDD1LoggedDataCount += 1; + } + } +*/ } + } + + Memory.FillRAM [0x4801] = 0; + } + +#ifdef USE_SA1 + if (d->BAddress == 0x18 && SA1.in_char_dma && (d->ABank & 0xf0) == 0x40) +#else + if (d->BAddress == 0x18 && (d->ABank & 0xf0) == 0x40) +#endif + { + // Perform packed bitmap to PPU character format conversion on the + // data before transmitting it to V-RAM via-DMA. + int num_chars = 1 << ((Memory.FillRAM [0x2231] >> 2) & 7); + int depth = (Memory.FillRAM [0x2231] & 3) == 0 ? 8 : + (Memory.FillRAM [0x2231] & 3) == 1 ? 4 : 2; + + int bytes_per_char = 8 * depth; + int bytes_per_line = depth * num_chars; + int char_line_bytes = bytes_per_char * num_chars; + uint32 addr = (d->AAddress / char_line_bytes) * char_line_bytes; + uint8 *base = GetBasePointer ((d->ABank << 16) + addr) + addr; + uint8 *buffer = &Memory.ROM [CMemory::MAX_ROM_SIZE - 0x10000]; + uint8 *p = buffer; + uint32 inc = char_line_bytes - (d->AAddress % char_line_bytes); + uint32 char_count = inc / bytes_per_char; + + in_sa1_dma = TRUE; + +//printf ("%08x,", base); fflush (stdout); +//printf ("depth = %d, count = %d, bytes_per_char = %d, bytes_per_line = %d, num_chars = %d, char_line_bytes = %d\n", +//depth, count, bytes_per_char, bytes_per_line, num_chars, char_line_bytes); + int i; + + switch (depth) + { + case 2: + for (i = 0; i < count; i += inc, base += char_line_bytes, + inc = char_line_bytes, char_count = num_chars) + { + uint8 *line = base + (num_chars - char_count) * 2; + for (uint32 j = 0; j < char_count && p - buffer < count; + j++, line += 2) + { + uint8 *q = line; + for (int l = 0; l < 8; l++, q += bytes_per_line) + { + for (int b = 0; b < 2; b++) + { + uint8 r = *(q + b); + *(p + 0) = (*(p + 0) << 1) | ((r >> 0) & 1); + *(p + 1) = (*(p + 1) << 1) | ((r >> 1) & 1); + *(p + 0) = (*(p + 0) << 1) | ((r >> 2) & 1); + *(p + 1) = (*(p + 1) << 1) | ((r >> 3) & 1); + *(p + 0) = (*(p + 0) << 1) | ((r >> 4) & 1); + *(p + 1) = (*(p + 1) << 1) | ((r >> 5) & 1); + *(p + 0) = (*(p + 0) << 1) | ((r >> 6) & 1); + *(p + 1) = (*(p + 1) << 1) | ((r >> 7) & 1); + } + p += 2; + } + } + } + break; + case 4: + for (i = 0; i < count; i += inc, base += char_line_bytes, + inc = char_line_bytes, char_count = num_chars) + { + uint8 *line = base + (num_chars - char_count) * 4; + for (uint32 j = 0; j < char_count && p - buffer < count; + j++, line += 4) + { + uint8 *q = line; + for (int l = 0; l < 8; l++, q += bytes_per_line) + { + for (int b = 0; b < 4; b++) + { + uint8 r = *(q + b); + *(p + 0) = (*(p + 0) << 1) | ((r >> 0) & 1); + *(p + 1) = (*(p + 1) << 1) | ((r >> 1) & 1); + *(p + 16) = (*(p + 16) << 1) | ((r >> 2) & 1); + *(p + 17) = (*(p + 17) << 1) | ((r >> 3) & 1); + *(p + 0) = (*(p + 0) << 1) | ((r >> 4) & 1); + *(p + 1) = (*(p + 1) << 1) | ((r >> 5) & 1); + *(p + 16) = (*(p + 16) << 1) | ((r >> 6) & 1); + *(p + 17) = (*(p + 17) << 1) | ((r >> 7) & 1); + } + p += 2; + } + p += 32 - 16; + } + } + break; + case 8: + for (i = 0; i < count; i += inc, base += char_line_bytes, + inc = char_line_bytes, char_count = num_chars) + { + uint8 *line = base + (num_chars - char_count) * 8; + for (uint32 j = 0; j < char_count && p - buffer < count; + j++, line += 8) + { + uint8 *q = line; + for (int l = 0; l < 8; l++, q += bytes_per_line) + { + for (int b = 0; b < 8; b++) + { + uint8 r = *(q + b); + *(p + 0) = (*(p + 0) << 1) | ((r >> 0) & 1); + *(p + 1) = (*(p + 1) << 1) | ((r >> 1) & 1); + *(p + 16) = (*(p + 16) << 1) | ((r >> 2) & 1); + *(p + 17) = (*(p + 17) << 1) | ((r >> 3) & 1); + *(p + 32) = (*(p + 32) << 1) | ((r >> 4) & 1); + *(p + 33) = (*(p + 33) << 1) | ((r >> 5) & 1); + *(p + 48) = (*(p + 48) << 1) | ((r >> 6) & 1); + *(p + 49) = (*(p + 49) << 1) | ((r >> 7) & 1); + } + p += 2; + } + p += 64 - 16; + } + } + break; + } + + } + +#ifdef DEBUGGER + if (Settings.TraceDMA) + { + sprintf (String, "DMA[%d]: %s Mode: %d 0x%02X%04X->0x21%02X Bytes: %d (%s) V-Line:%ld", + Channel, d->TransferDirection ? "read" : "write", + d->TransferMode, d->ABank, d->AAddress, + d->BAddress, d->TransferBytes, + d->AAddressFixed ? "fixed" : + (d->AAddressDecrement ? "dec" : "inc"), + CPU.V_Counter); + if (d->BAddress == 0x18 || d->BAddress == 0x19) + sprintf (String, "%s VRAM: %04X (%d,%d) %s", String, + PPU.VMA.Address, + PPU.VMA.Increment, PPU.VMA.FullGraphicCount, + PPU.VMA.High ? "word" : "byte"); + else + if (d->BAddress == 0x22) + sprintf (String, "%s CGRAM: %02X (%x)", String, PPU.CGADD, + PPU.CGFLIP); + else + if (d->BAddress == 0x04) + sprintf (String, "%s OBJADDR: %04X", String, PPU.OAMAddr); + S9xMessage (S9X_TRACE, S9X_DMA_TRACE, String); + } +#endif + + if (!d->TransferDirection) + { +#ifdef VAR_CYCLES + //reflects extra cycle used by DMA + CPU.Cycles += 8 * (count+1); +#else + //needs fixing for the extra DMA cycle + CPU.Cycles += (1+count) + ((1+count) >> 2); +#endif + uint8 *base = GetBasePointer ((d->ABank << 16) + d->AAddress); + uint16 p = d->AAddress; + + if (!base) + base = Memory.ROM; + + if (in_sa1_dma) + { + base = &Memory.ROM [CMemory::MAX_ROM_SIZE - 0x10000]; + p = 0; + } + + if (in_sdd1_dma) + { + base = in_sdd1_dma; + p = 0; + } + + if (inc > 0) + d->AAddress += count; + else + if (inc < 0) + d->AAddress -= count; + + if (d->TransferMode == 0 || d->TransferMode == 2) + { + switch (d->BAddress) + { + case 0x04: + do + { + Work = *(base + p); + REGISTER_2104(Work); + p += inc; + CHECK_SOUND(); + } while (--count > 0); + break; + case 0x18: + IPPU.FirstVRAMRead = TRUE; + if (!PPU.VMA.FullGraphicCount) + { + do + { + Work = *(base + p); + REGISTER_2118_linear(Work); + p += inc; + CHECK_SOUND(); + } while (--count > 0); + } + else + { + do + { + Work = *(base + p); + REGISTER_2118_tile(Work); + p += inc; + CHECK_SOUND(); + } while (--count > 0); + } + break; + case 0x19: + IPPU.FirstVRAMRead = TRUE; + if (!PPU.VMA.FullGraphicCount) + { + do + { + Work = *(base + p); + REGISTER_2119_linear(Work); + p += inc; + CHECK_SOUND(); + } while (--count > 0); + } + else + { + do + { + Work = *(base + p); + REGISTER_2119_tile(Work); + p += inc; + CHECK_SOUND(); + } while (--count > 0); + } + break; + case 0x22: + do + { + Work = *(base + p); + REGISTER_2122(Work); + p += inc; + CHECK_SOUND(); + } while (--count > 0); + break; + case 0x80: + do + { + Work = *(base + p); + REGISTER_2180(Work); + p += inc; + CHECK_SOUND(); + } while (--count > 0); + break; + default: + do + { + Work = *(base + p); + S9xSetPPU (Work, 0x2100 + d->BAddress); + p += inc; + CHECK_SOUND(); + } while (--count > 0); + break; + } + } + else + if (d->TransferMode == 1 || d->TransferMode == 5) + { + if (d->BAddress == 0x18) + { + // Write to V-RAM + IPPU.FirstVRAMRead = TRUE; + if (!PPU.VMA.FullGraphicCount) + { + while (count > 1) + { + Work = *(base + p); + REGISTER_2118_linear(Work); + p += inc; + + Work = *(base + p); + REGISTER_2119_linear(Work); + p += inc; + CHECK_SOUND(); + count -= 2; + } + if (count == 1) + { + Work = *(base + p); + REGISTER_2118_linear(Work); + p += inc; + } + } + else + { + while (count > 1) + { + Work = *(base + p); + REGISTER_2118_tile(Work); + p += inc; + + Work = *(base + p); + REGISTER_2119_tile(Work); + p += inc; + CHECK_SOUND(); + count -= 2; + } + if (count == 1) + { + Work = *(base + p); + REGISTER_2118_tile(Work); + p += inc; + } + } + } + else + { + // DMA mode 1 general case + while (count > 1) + { + Work = *(base + p); + S9xSetPPU (Work, 0x2100 + d->BAddress); + p += inc; + + Work = *(base + p); + S9xSetPPU (Work, 0x2101 + d->BAddress); + p += inc; + CHECK_SOUND(); + count -= 2; + } + if (count == 1) + { + Work = *(base + p); + S9xSetPPU (Work, 0x2100 + d->BAddress); + p += inc; + } + } + } + else + if (d->TransferMode == 3) + { + do + { + Work = *(base + p); + S9xSetPPU (Work, 0x2100 + d->BAddress); + p += inc; + if (count <= 1) + break; + + Work = *(base + p); + S9xSetPPU (Work, 0x2100 + d->BAddress); + p += inc; + if (count <= 2) + break; + + Work = *(base + p); + S9xSetPPU (Work, 0x2101 + d->BAddress); + p += inc; + if (count <= 3) + break; + + Work = *(base + p); + S9xSetPPU (Work, 0x2101 + d->BAddress); + p += inc; + CHECK_SOUND(); + count -= 4; + } while (count > 0); + } + else + if (d->TransferMode == 4) + { + do + { + Work = *(base + p); + S9xSetPPU (Work, 0x2100 + d->BAddress); + p += inc; + if (count <= 1) + break; + + Work = *(base + p); + S9xSetPPU (Work, 0x2101 + d->BAddress); + p += inc; + if (count <= 2) + break; + + Work = *(base + p); + S9xSetPPU (Work, 0x2102 + d->BAddress); + p += inc; + if (count <= 3) + break; + + Work = *(base + p); + S9xSetPPU (Work, 0x2103 + d->BAddress); + p += inc; + CHECK_SOUND(); + count -= 4; + } while (count > 0); + } + else + { +#ifdef DEBUGGER +// if (Settings.TraceDMA) + { + sprintf (String, "Unknown DMA transfer mode: %d on channel %d\n", + d->TransferMode, Channel); + S9xMessage (S9X_TRACE, S9X_DMA_TRACE, String); + } +#endif + } + } + else + { + do + { + switch (d->TransferMode) + { + case 0: + case 2: +#ifndef VAR_CYCLES + CPU.Cycles += 1; +#endif + Work = S9xGetPPU (0x2100 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + --count; + break; + + case 1: + case 5: +#ifndef VAR_CYCLES + CPU.Cycles += 3; +#endif + Work = S9xGetPPU (0x2100 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + if (!--count) + break; + + Work = S9xGetPPU (0x2101 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + count--; + break; + + case 3: +#ifndef VAR_CYCLES + CPU.Cycles += 6; +#endif + Work = S9xGetPPU (0x2100 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + if (!--count) + break; + + Work = S9xGetPPU (0x2100 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + if (!--count) + break; + + Work = S9xGetPPU (0x2101 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + if (!--count) + break; + + Work = S9xGetPPU (0x2101 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + count--; + break; + + case 4: +#ifndef VAR_CYCLES + CPU.Cycles += 6; +#endif + Work = S9xGetPPU (0x2100 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + if (!--count) + break; + + Work = S9xGetPPU (0x2101 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + if (!--count) + break; + + Work = S9xGetPPU (0x2102 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + if (!--count) + break; + + Work = S9xGetPPU (0x2103 + d->BAddress); + S9xSetByte (Work, (d->ABank << 16) + d->AAddress); + d->AAddress += inc; + count--; + break; + + default: +#ifdef DEBUGGER + if (1) //Settings.TraceDMA) + { + sprintf (String, "Unknown DMA transfer mode: %d on channel %d\n", + d->TransferMode, Channel); + S9xMessage (S9X_TRACE, S9X_DMA_TRACE, String); + } +#endif + count = 0; + break; + } + CHECK_SOUND(); + } while (count); + } + +//#ifdef SPC700_C +#ifdef SPC700_SHUTDOWN + CPU.APU_APUExecuting = Settings.APUEnabled; +#endif + asm_APU_EXECUTE(1); // execute but only in normal mode +//#endif + while (CPU.Cycles > CPU.NextEvent) + S9xDoHBlankProcessing (); + +update_address: + // Super Punch-Out requires that the A-BUS address be updated after the + // DMA transfer. + Memory.FillRAM[0x4302 + (Channel << 4)] = (uint8) d->AAddress; + Memory.FillRAM[0x4303 + (Channel << 4)] = d->AAddress >> 8; + + // Secret of the Mana requires that the DMA bytes transfer count be set to + // zero when DMA has completed. + Memory.FillRAM [0x4305 + (Channel << 4)] = 0; + Memory.FillRAM [0x4306 + (Channel << 4)] = 0; + + DMA[Channel].IndirectAddress = 0; + d->TransferBytes = 0; + + CPU.InDMA = FALSE; +} + +void S9xStartHDMA () +{ + //if (Settings.DisableHDMA) + //IPPU.HDMA = 0; + //else + missing.hdma_this_frame = IPPU.HDMA = Memory.FillRAM [0x420c]; + + IPPU.HDMAStarted = TRUE; + + for (uint8 i = 0; i < 8; i++) + { + if (IPPU.HDMA & (1 << i)) + { + DMA [i].LineCount = 0; + DMA [i].FirstLine = TRUE; + DMA [i].Address = DMA [i].AAddress; + } + HDMAMemPointers [i] = NULL; + } +} + +#ifdef DEBUGGER +void S9xTraceSoundDSP (const char *s, int i1 = 0, int i2 = 0, int i3 = 0, + int i4 = 0, int i5 = 0, int i6 = 0, int i7 = 0); +#endif + + +uint8 S9xDoHDMA (uint8 byte) +{ + struct SDMA *p = &DMA [0]; + + int d = 0; + + for (uint8 mask = 1; mask; mask <<= 1, p++, d++) + { + if (byte & mask) + { + if (!p->LineCount) + { + uint8 line = S9xGetByte ((p->ABank << 16) + p->Address); + if (line == 0x80) + { + p->Repeat = TRUE; + p->LineCount = 128; + } + else + { + p->Repeat = !(line & 0x80); + p->LineCount = line & 0x7f; + } + + // Disable H-DMA'ing into V-RAM (register 2118) for Hook + if (!p->LineCount || p->BAddress == 0x18) + { + byte &= ~mask; + p->IndirectAddress += HDMAMemPointers [d] - HDMABasePointers [d]; + Memory.FillRAM [0x4305 + (d << 4)] = (uint8) p->IndirectAddress; + Memory.FillRAM [0x4306 + (d << 4)] = p->IndirectAddress >> 8; + continue; + } + + p->Address++; + p->FirstLine = 1; + if (p->HDMAIndirectAddressing) + { + p->IndirectBank = Memory.FillRAM [0x4307 + (d << 4)]; + p->IndirectAddress = S9xGetWord ((p->ABank << 16) + p->Address); + p->Address += 2; + } + else + { + p->IndirectBank = p->ABank; + p->IndirectAddress = p->Address; + } + HDMABasePointers [d] = HDMAMemPointers [d] = + S9xGetMemPointer ((p->IndirectBank << 16) + p->IndirectAddress); + } + else + { + + if (!HDMAMemPointers [d]) + { + if (!p->HDMAIndirectAddressing) + { + p->IndirectBank = p->ABank; + p->IndirectAddress = p->Address; + } + + if (!(HDMABasePointers [d] = HDMAMemPointers [d] = + S9xGetMemPointer ((p->IndirectBank << 16) + p->IndirectAddress))) + { + byte &= ~mask; + continue; + } + // Uncommenting the following line breaks Punchout - it starts + // H-DMA during the frame. + //p->FirstLine = TRUE; + } + } + if (p->Repeat && !p->FirstLine) + { + p->LineCount--; + continue; + } + +#ifdef DEBUGGER + if (Settings.TraceSoundDSP && p->FirstLine && + p->BAddress >= 0x40 && p->BAddress <= 0x43) + S9xTraceSoundDSP ("Spooling data!!!\n"); + + if (Settings.TraceHDMA && p->FirstLine) + { + sprintf (String, "H-DMA[%d] (%d) 0x%02X%04X->0x21%02X %s, Count: %3d, Rep: %s, V-LINE: %3ld %02X%04X", + p-DMA, p->TransferMode, p->IndirectBank, + p->IndirectAddress, + p->BAddress, + p->HDMAIndirectAddressing ? "ind" : "abs", + p->LineCount, + p->Repeat ? "yes" : "no ", CPU.V_Counter, + p->ABank, p->Address); + S9xMessage (S9X_TRACE, S9X_HDMA_TRACE, String); + } +#endif + switch (p->TransferMode) + { + case 0: +#ifndef VAR_CYCLES + CPU.Cycles += 1; +#else + CPU.Cycles += 8; +#endif + S9xSetPPU (*HDMAMemPointers [d]++, 0x2100 + p->BAddress); + break; + case 1: + case 5: +#ifndef VAR_CYCLES + CPU.Cycles += 3; +#else + CPU.Cycles += 16; +#endif + S9xSetPPU (*(HDMAMemPointers [d] + 0), 0x2100 + p->BAddress); + S9xSetPPU (*(HDMAMemPointers [d] + 1), 0x2101 + p->BAddress); + HDMAMemPointers [d] += 2; + break; + case 2: + case 6: +#ifndef VAR_CYCLES + CPU.Cycles += 3; +#else + CPU.Cycles += 16; +#endif + S9xSetPPU (*(HDMAMemPointers [d] + 0), 0x2100 + p->BAddress); + S9xSetPPU (*(HDMAMemPointers [d] + 1), 0x2100 + p->BAddress); + HDMAMemPointers [d] += 2; + break; + case 3: + case 7: +#ifndef VAR_CYCLES + CPU.Cycles += 6; +#else + CPU.Cycles += 32; +#endif + S9xSetPPU (*(HDMAMemPointers [d] + 0), 0x2100 + p->BAddress); + S9xSetPPU (*(HDMAMemPointers [d] + 1), 0x2100 + p->BAddress); + S9xSetPPU (*(HDMAMemPointers [d] + 2), 0x2101 + p->BAddress); + S9xSetPPU (*(HDMAMemPointers [d] + 3), 0x2101 + p->BAddress); + HDMAMemPointers [d] += 4; + break; + case 4: +#ifndef VAR_CYCLES + CPU.Cycles += 6; +#else + CPU.Cycles += 32; +#endif + S9xSetPPU (*(HDMAMemPointers [d] + 0), 0x2100 + p->BAddress); + S9xSetPPU (*(HDMAMemPointers [d] + 1), 0x2101 + p->BAddress); + S9xSetPPU (*(HDMAMemPointers [d] + 2), 0x2102 + p->BAddress); + S9xSetPPU (*(HDMAMemPointers [d] + 3), 0x2103 + p->BAddress); + HDMAMemPointers [d] += 4; + break; + } + if (!p->HDMAIndirectAddressing) + p->Address += HDMA_ModeByteCounts [p->TransferMode]; + p->FirstLine = FALSE; + p->LineCount--; + } + } + return (byte); +} + +void S9xResetDMA () +{ + int d; + for (d = 0; d < 8; d++) + { + DMA [d].TransferDirection = FALSE; + DMA [d].HDMAIndirectAddressing = FALSE; + DMA [d].AAddressFixed = TRUE; + DMA [d].AAddressDecrement = FALSE; + DMA [d].TransferMode = 0xff; + DMA [d].ABank = 0xff; + DMA [d].AAddress = 0xffff; + DMA [d].Address = 0xffff; + DMA [d].BAddress = 0xff; + DMA [d].TransferBytes = 0xffff; + } + for (int c = 0x4300; c < 0x4380; c += 0x10) + { + for (d = c; d < c + 12; d++) + Memory.FillRAM [d] = 0xff; + + Memory.FillRAM [c + 0xf] = 0xff; + } +} diff --git a/src/dma.h b/src/dma.h new file mode 100644 index 0000000..c0277b9 --- /dev/null +++ b/src/dma.h @@ -0,0 +1,51 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _DMA_H_ +#define _DMA_H_ + +START_EXTERN_C +void S9xResetDMA (void); +uint8 S9xDoHDMA (uint8); +void S9xStartHDMA (); +void S9xDoDMA (uint8); +END_EXTERN_C + +#endif diff --git a/src/dsp1.cpp b/src/dsp1.cpp new file mode 100644 index 0000000..f2ea308 --- /dev/null +++ b/src/dsp1.cpp @@ -0,0 +1,1195 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#include "snes9x.h" +#include "dsp1.h" +#include "missing.h" +#include "memmap.h" +#include + +#include "dsp1emu.c" +#include "dsp2emu.c" +//#include "dsp3emu.cpp" + +void (*SetDSP)(uint8, uint16)=&DSP1SetByte; +uint8 (*GetDSP)(uint16)=&DSP1GetByte; + +void S9xInitDSP1 () +{ + static bool8 init = FALSE; + + if (!init) + { + InitDSP (); + init = TRUE; + } +} + +void S9xResetDSP1 () +{ + S9xInitDSP1 (); + + DSP1.waiting4command = TRUE; + DSP1.in_count = 0; + DSP1.out_count = 0; + DSP1.in_index = 0; + DSP1.out_index = 0; + DSP1.first_parameter = TRUE; +} + +uint8 S9xGetDSP (uint16 address) +{ + uint8 t; + +#ifdef DEBUGGER + if (Settings.TraceDSP) + { + sprintf (String, "DSP read: 0x%04X", address); + S9xMessage (S9X_TRACE, S9X_TRACE_DSP1, String); + } +#endif + + t=(*GetDSP)(address); + //DSP1GetByte(address); + return (t); +} + +void S9xSetDSP (uint8 byte, uint16 address) +{ +#ifdef DEBUGGER + missing.unknowndsp_write = address; + if (Settings.TraceDSP) + { + sprintf (String, "DSP write: 0x%04X=0x%02X", address, byte); + S9xMessage (S9X_TRACE, S9X_TRACE_DSP1, String); + } +#endif + (*SetDSP)(byte, address); + //DSP1SetByte(byte, address); +} + +void DSP1SetByte(uint8 byte, uint16 address) +{ + if( (address & 0xf000) == 0x6000 || (address & 0x7fff) < 0x4000 ) + { +// if ((address & 1) == 0) +// { + if((DSP1.command==0x0A||DSP1.command==0x1A)&&DSP1.out_count!=0) + { + DSP1.out_count--; + DSP1.out_index++; + return; + } + else if (DSP1.waiting4command) + { + DSP1.command = byte; + DSP1.in_index = 0; + DSP1.waiting4command = FALSE; + DSP1.first_parameter = TRUE; +// printf("Op%02X\n",byte); + // Mario Kart uses 0x00, 0x02, 0x06, 0x0c, 0x28, 0x0a + switch (byte) + { + case 0x00: DSP1.in_count = 2; break; + case 0x30: + case 0x10: DSP1.in_count = 2; break; + case 0x20: DSP1.in_count = 2; break; + case 0x24: + case 0x04: DSP1.in_count = 2; break; + case 0x08: DSP1.in_count = 3; break; + case 0x18: DSP1.in_count = 4; break; + case 0x28: DSP1.in_count = 3; break; + case 0x38: DSP1.in_count = 4; break; + case 0x2c: + case 0x0c: DSP1.in_count = 3; break; + case 0x3c: + case 0x1c: DSP1.in_count = 6; break; + case 0x32: + case 0x22: + case 0x12: + case 0x02: DSP1.in_count = 7; break; + case 0x0a: DSP1.in_count = 1; break; + case 0x3a: + case 0x2a: + case 0x1a: + DSP1. command =0x1a; + DSP1.in_count = 1; break; + case 0x16: + case 0x26: + case 0x36: + case 0x06: DSP1.in_count = 3; break; + case 0x1e: + case 0x2e: + case 0x3e: + case 0x0e: DSP1.in_count = 2; break; + case 0x05: + case 0x35: + case 0x31: + case 0x01: DSP1.in_count = 4; break; + case 0x15: + case 0x11: DSP1.in_count = 4; break; + case 0x25: + case 0x21: DSP1.in_count = 4; break; + case 0x09: + case 0x39: + case 0x3d: + case 0x0d: DSP1.in_count = 3; break; + case 0x19: + case 0x1d: DSP1.in_count = 3; break; + case 0x29: + case 0x2d: DSP1.in_count = 3; break; + case 0x33: + case 0x03: DSP1.in_count = 3; break; + case 0x13: DSP1.in_count = 3; break; + case 0x23: DSP1.in_count = 3; break; + case 0x3b: + case 0x0b: DSP1.in_count = 3; break; + case 0x1b: DSP1.in_count = 3; break; + case 0x2b: DSP1.in_count = 3; break; + case 0x34: + case 0x14: DSP1.in_count = 6; break; + case 0x07: + case 0x0f: DSP1.in_count = 1; break; + case 0x27: + case 0x2F: DSP1.in_count=1; break; + case 0x17: + case 0x37: + case 0x3F: + DSP1.command=0x1f; + case 0x1f: DSP1.in_count = 1; break; + // case 0x80: DSP1.in_count = 2; break; + default: + //printf("Op%02X\n",byte); + case 0x80: + DSP1.in_count = 0; + DSP1.waiting4command = TRUE; + DSP1.first_parameter = TRUE; + break; + } + DSP1.in_count<<=1; + } + else + { + DSP1.parameters [DSP1.in_index] = byte; + DSP1.first_parameter = FALSE; + DSP1.in_index++; + } + + if (DSP1.waiting4command || + (DSP1.first_parameter && byte == 0x80)) + { + DSP1.waiting4command = TRUE; + DSP1.first_parameter = FALSE; + } + else if(DSP1.first_parameter && (DSP1.in_count != 0 || (DSP1.in_count==0&&DSP1.in_index==0))) + { + } +// else if (DSP1.first_parameter) +// { +// } + else + { + if (DSP1.in_count) + { + //DSP1.parameters [DSP1.in_index] |= (byte << 8); + if (--DSP1.in_count == 0) + { + // Actually execute the command + DSP1.waiting4command = TRUE; + DSP1.out_index = 0; + switch (DSP1.command) + { + case 0x1f: + DSP1.out_count=2048; + break; + case 0x00: // Multiple + Op00Multiplicand = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op00Multiplier = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + + DSPOp00 (); + + DSP1.out_count = 2; + DSP1.output [0] = Op00Result&0xFF; + DSP1.output [1] = (Op00Result>>8)&0xFF; + break; + + case 0x20: // Multiple + Op20Multiplicand = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op20Multiplier = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + + DSPOp20 (); + + DSP1.out_count = 2; + DSP1.output [0] = Op20Result&0xFF; + DSP1.output [1] = (Op20Result>>8)&0xFF; + break; + + case 0x30: + case 0x10: // Inverse + Op10Coefficient = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op10Exponent = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + + DSPOp10 (); + + DSP1.out_count = 4; + DSP1.output [0] = (uint8) (((int16) Op10CoefficientR)&0xFF); + DSP1.output [1] = (uint8) ((((int16) Op10CoefficientR)>>8)&0xFF); + DSP1.output [2] = (uint8) (((int16) Op10ExponentR)&0xff); + DSP1.output [3] = (uint8) ((((int16) Op10ExponentR)>>8)&0xff); + break; + + case 0x24: + case 0x04: // Sin and Cos of angle + Op04Angle = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op04Radius = (uint16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + + DSPOp04 (); + + DSP1.out_count = 4; + DSP1.output [0] = (uint8) (Op04Sin&0xFF); + DSP1.output [1] = (uint8) ((Op04Sin>>8)&0xFF); + DSP1.output [2] = (uint8) (Op04Cos&0xFF); + DSP1.output [3] = (uint8) ((Op04Cos>>8)&0xFF); + break; + + case 0x08: // Radius + Op08X = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op08Y = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op08Z = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp08 (); + + DSP1.out_count = 4; + DSP1.output [0] = (uint8) (((int16) Op08Ll)&0xFF); + DSP1.output [1] = (uint8) ((((int16) Op08Ll)>>8)&0xFF); + DSP1.output [2] = (uint8) (((int16) Op08Lh)&0xFF); + DSP1.output [3] = (uint8) ((((int16) Op08Lh)>>8)&0xFF); + break; + + case 0x18: // Range + + Op18X = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op18Y = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op18Z = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + Op18R = (int16) (DSP1.parameters [6]|(DSP1.parameters[7]<<8)); + + DSPOp18 (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint8) (Op18D&0xFF); + DSP1.output [1] = (uint8) ((Op18D>>8)&0xFF); + break; + + case 0x38: // Range + + Op38X = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op38Y = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op38Z = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + Op38R = (int16) (DSP1.parameters [6]|(DSP1.parameters[7]<<8)); + + DSPOp38 (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint8) (Op38D&0xFF); + DSP1.output [1] = (uint8) ((Op38D>>8)&0xFF); + break; + + case 0x28: // Distance (vector length) + Op28X = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op28Y = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op28Z = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp28 (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint8) (Op28R&0xFF); + DSP1.output [1] = (uint8) ((Op28R>>8)&0xFF); + break; + + case 0x2c: + case 0x0c: // Rotate (2D rotate) + Op0CA = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op0CX1 = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op0CY1 = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp0C (); + + DSP1.out_count = 4; + DSP1.output [0] = (uint8) (Op0CX2&0xFF); + DSP1.output [1] = (uint8) ((Op0CX2>>8)&0xFF); + DSP1.output [2] = (uint8) (Op0CY2&0xFF); + DSP1.output [3] = (uint8) ((Op0CY2>>8)&0xFF); + break; + + case 0x3c: + case 0x1c: // Polar (3D rotate) + Op1CZ = (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + //MK: reversed X and Y on neviksti and John's advice. + Op1CY = (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op1CX = (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + Op1CXBR = (DSP1.parameters [6]|(DSP1.parameters[7]<<8)); + Op1CYBR = (DSP1.parameters [8]|(DSP1.parameters[9]<<8)); + Op1CZBR = (DSP1.parameters [10]|(DSP1.parameters[11]<<8)); + + DSPOp1C (); + + DSP1.out_count = 6; + DSP1.output [0] = (uint8) (Op1CXAR&0xFF); + DSP1.output [1] = (uint8) ((Op1CXAR>>8)&0xFF); + DSP1.output [2] = (uint8) (Op1CYAR&0xFF); + DSP1.output [3] = (uint8) ((Op1CYAR>>8)&0xFF); + DSP1.output [4] = (uint8) (Op1CZAR&0xFF); + DSP1.output [5] = (uint8) ((Op1CZAR>>8)&0xFF); + break; + + case 0x32: + case 0x22: + case 0x12: + case 0x02: // Parameter (Projection) + Op02FX = (short)(DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op02FY = (short)(DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op02FZ = (short)(DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + Op02LFE = (short)(DSP1.parameters [6]|(DSP1.parameters[7]<<8)); + Op02LES = (short)(DSP1.parameters [8]|(DSP1.parameters[9]<<8)); + Op02AAS = (unsigned short)(DSP1.parameters [10]|(DSP1.parameters[11]<<8)); + Op02AZS = (unsigned short)(DSP1.parameters [12]|(DSP1.parameters[13]<<8)); + + DSPOp02 (); + + DSP1.out_count = 8; + DSP1.output [0] = (uint8) (Op02VOF&0xFF); + DSP1.output [1] = (uint8) ((Op02VOF>>8)&0xFF); + DSP1.output [2] = (uint8) (Op02VVA&0xFF); + DSP1.output [3] = (uint8) ((Op02VVA>>8)&0xFF); + DSP1.output [4] = (uint8) (Op02CX&0xFF); + DSP1.output [5] = (uint8) ((Op02CX>>8)&0xFF); + DSP1.output [6] = (uint8) (Op02CY&0xFF); + DSP1.output [7] = (uint8) ((Op02CY>>8)&0xFF); + break; + + case 0x3a: //1a Mirror + case 0x2a: //1a Mirror + case 0x1a: // Raster mode 7 matrix data + case 0x0a: + Op0AVS = (short)(DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + + DSPOp0A (); + + DSP1.out_count = 8; + DSP1.output [0] = (uint8) (Op0AA&0xFF); + DSP1.output [2] = (uint8) (Op0AB&0xFF); + DSP1.output [4] = (uint8) (Op0AC&0xFF); + DSP1.output [6] = (uint8) (Op0AD&0xFF); + DSP1.output [1] = (uint8) ((Op0AA>>8)&0xFF); + DSP1.output [3] = (uint8) ((Op0AB>>8)&0xFF); + DSP1.output [5] = (uint8) ((Op0AC>>8)&0xFF); + DSP1.output [7] = (uint8) ((Op0AD>>8)&0xFF); + DSP1.in_index=0; + break; + + case 0x16: + case 0x26: + case 0x36: + case 0x06: // Project object + Op06X = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op06Y = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op06Z = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp06 (); + + DSP1.out_count = 6; + DSP1.output [0] = (uint8) (Op06H&0xff); + DSP1.output [1] = (uint8) ((Op06H>>8)&0xFF); + DSP1.output [2] = (uint8) (Op06V&0xFF); + DSP1.output [3] = (uint8) ((Op06V>>8)&0xFF); + DSP1.output [4] = (uint8) (Op06S&0xFF); + DSP1.output [5] = (uint8) ((Op06S>>8)&0xFF); + break; + + case 0x1e: + case 0x2e: + case 0x3e: + case 0x0e: // Target + Op0EH = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op0EV = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + + DSPOp0E (); + + DSP1.out_count = 4; + DSP1.output [0] = (uint8) (Op0EX&0xFF); + DSP1.output [1] = (uint8) ((Op0EX>>8)&0xFF); + DSP1.output [2] = (uint8) (Op0EY&0xFF); + DSP1.output [3] = (uint8) ((Op0EY>>8)&0xFF); + break; + + // Extra commands used by Pilot Wings + case 0x05: + case 0x35: + case 0x31: + case 0x01: // Set attitude matrix A + Op01m = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op01Zr = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op01Yr = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + Op01Xr = (int16) (DSP1.parameters [6]|(DSP1.parameters[7]<<8)); + + DSPOp01 (); + break; + + case 0x15: + case 0x11: // Set attitude matrix B + Op11m = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op11Zr = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op11Yr = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + Op11Xr = (int16) (DSP1.parameters [7]|(DSP1.parameters[7]<<8)); + + DSPOp11 (); + break; + + case 0x25: + case 0x21: // Set attitude matrix C + Op21m = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op21Zr = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op21Yr = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + Op21Xr = (int16) (DSP1.parameters [6]|(DSP1.parameters[7]<<8)); + + DSPOp21 (); + break; + + case 0x09: + case 0x39: + case 0x3d: + case 0x0d: // Objective matrix A + Op0DX = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op0DY = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op0DZ = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp0D (); + + DSP1.out_count = 6; + DSP1.output [0] = (uint8) (Op0DF&0xFF); + DSP1.output [1] = (uint8) ((Op0DF>>8)&0xFF); + DSP1.output [2] = (uint8) (Op0DL&0xFF); + DSP1.output [3] = (uint8) ((Op0DL>>8)&0xFF); + DSP1.output [4] = (uint8) (Op0DU&0xFF); + DSP1.output [5] = (uint8) ((Op0DU>>8)&0xFF); + break; + + case 0x19: + case 0x1d: // Objective matrix B + Op1DX = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op1DY = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op1DZ = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp1D (); + + DSP1.out_count = 6; + DSP1.output [0] = (uint8) (Op1DF&0xFF); + DSP1.output [1] = (uint8) ((Op1DF>>8)&0xFF); + DSP1.output [2] = (uint8) (Op1DL&0xFF); + DSP1.output [3] = (uint8) ((Op1DL>>8)&0xFF); + DSP1.output [4] = (uint8) (Op1DU&0xFF); + DSP1.output [5] = (uint8) ((Op1DU>>8)&0xFF); + break; + + case 0x29: + case 0x2d: // Objective matrix C + Op2DX = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op2DY = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op2DZ = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp2D (); + + DSP1.out_count = 6; + DSP1.output [0] = (uint8) (Op2DF&0xFF); + DSP1.output [1] = (uint8) ((Op2DF>>8)&0xFF); + DSP1.output [2] = (uint8) (Op2DL&0xFF); + DSP1.output [3] = (uint8) ((Op2DL>>8)&0xFF); + DSP1.output [4] = (uint8) (Op2DU&0xFF); + DSP1.output [5] = (uint8) ((Op2DU>>8)&0xFF); + break; + + case 0x33: + case 0x03: // Subjective matrix A + Op03F = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op03L = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op03U = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp03 (); + + DSP1.out_count = 6; + DSP1.output [0] = (uint8) (Op03X&0xFF); + DSP1.output [1] = (uint8) ((Op03X>>8)&0xFF); + DSP1.output [2] = (uint8) (Op03Y&0xFF); + DSP1.output [3] = (uint8) ((Op03Y>>8)&0xFF); + DSP1.output [4] = (uint8) (Op03Z&0xFF); + DSP1.output [5] = (uint8) ((Op03Z>>8)&0xFF); + break; + + case 0x13: // Subjective matrix B + Op13F = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op13L = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op13U = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp13 (); + + DSP1.out_count = 6; + DSP1.output [0] = (uint8) (Op13X&0xFF); + DSP1.output [1] = (uint8) ((Op13X>>8)&0xFF); + DSP1.output [2] = (uint8) (Op13Y&0xFF); + DSP1.output [3] = (uint8) ((Op13Y>>8)&0xFF); + DSP1.output [4] = (uint8) (Op13Z&0xFF); + DSP1.output [5] = (uint8) ((Op13Z>>8)&0xFF); + break; + + case 0x23: // Subjective matrix C + Op23F = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op23L = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op23U = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp23 (); + + DSP1.out_count = 6; + DSP1.output [0] = (uint8) (Op23X&0xFF); + DSP1.output [1] = (uint8) ((Op23X>>8)&0xFF); + DSP1.output [2] = (uint8) (Op23Y&0xFF); + DSP1.output [3] = (uint8) ((Op23Y>>8)&0xFF); + DSP1.output [4] = (uint8) (Op23Z&0xFF); + DSP1.output [5] = (uint8) ((Op23Z>>8)&0xFF); + break; + + case 0x3b: + case 0x0b: + Op0BX = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op0BY = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op0BZ = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp0B (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint8) (Op0BS&0xFF); + DSP1.output [1] = (uint8) ((Op0BS>>8)&0xFF); + break; + + case 0x1b: + Op1BX = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op1BY = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op1BZ = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp1B (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint8) (Op1BS&0xFF); + DSP1.output [1] = (uint8) ((Op1BS>>8)&0xFF); + break; + + case 0x2b: + Op2BX = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op2BY = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op2BZ = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + + DSPOp2B (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint8) (Op2BS&0xFF); + DSP1.output [1] = (uint8) ((Op2BS>>8)&0xFF); + break; + + case 0x34: + case 0x14: + Op14Zr = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + Op14Xr = (int16) (DSP1.parameters [2]|(DSP1.parameters[3]<<8)); + Op14Yr = (int16) (DSP1.parameters [4]|(DSP1.parameters[5]<<8)); + Op14U = (int16) (DSP1.parameters [6]|(DSP1.parameters[7]<<8)); + Op14F = (int16) (DSP1.parameters [8]|(DSP1.parameters[9]<<8)); + Op14L = (int16) (DSP1.parameters [10]|(DSP1.parameters[11]<<8)); + + DSPOp14 (); + + DSP1.out_count = 6; + DSP1.output [0] = (uint8) (Op14Zrr&0xFF); + DSP1.output [1] = (uint8) ((Op14Zrr>>8)&0xFF); + DSP1.output [2] = (uint8) (Op14Xrr&0xFF); + DSP1.output [3] = (uint8) ((Op14Xrr>>8)&0xFF); + DSP1.output [4] = (uint8) (Op14Yrr&0xFF); + DSP1.output [5] = (uint8) ((Op14Yrr>>8)&0xFF); + break; + + case 0x27: + case 0x2F: + Op2FUnknown = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + + DSPOp2F (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint8)(Op2FSize&0xFF); + DSP1.output [1] = (uint8)((Op2FSize>>8)&0xFF); + break; + + + case 0x07: + case 0x0F: + Op0FRamsize = (int16) (DSP1.parameters [0]|(DSP1.parameters[1]<<8)); + + DSPOp0F (); + + DSP1.out_count = 2; + DSP1.output [0] = (uint8)(Op0FPass&0xFF); + DSP1.output [1] = (uint8)((Op0FPass>>8)&0xFF); + break; + + default: + break; + } + } + } + } + } +} + +uint8 DSP1GetByte(uint16 address) +{ + uint8 t; + if ((address & 0xf000) == 0x6000 || +// (address >= 0x8000 && address < 0xc000)) + (address&0x7fff) < 0x4000) + { + if (DSP1.out_count) + { + //if ((address & 1) == 0) + t = (uint8) DSP1.output [DSP1.out_index]; + //else + //{ + // t = (uint8) (DSP1.output [DSP1.out_index] >> 8); + DSP1.out_index++; + if (--DSP1.out_count == 0) + { + if (DSP1.command == 0x1a || DSP1.command == 0x0a) + { + DSPOp0A (); + DSP1.out_count = 8; + DSP1.out_index = 0; + DSP1.output [0] = (Op0AA&0xFF); + DSP1.output [1] = (Op0AA>>8)&0xFF; + DSP1.output [2] = (Op0AB&0xFF); + DSP1.output [3] = (Op0AB>>8)&0xFF; + DSP1.output [4] = (Op0AC&0xFF); + DSP1.output [5] = (Op0AC>>8)&0xFF; + DSP1.output [6] = (Op0AD&0xFF); + DSP1.output [7] = (Op0AD>>8)&0xFF; + } + if(DSP1.command==0x1f) + { + if((DSP1.out_index%2)!=0) + { + t=(uint8)DSP1ROM[DSP1.out_index>>1]; + } + else + { + t=DSP1ROM[DSP1.out_index>>1]>>8; + } + } + } + DSP1.waiting4command = TRUE; + //} + } + else + { + // Top Gear 3000 requires this value.... + // if(4==Settings.DSPVersion) + t = 0xff; + //Ballz3d requires this one: + // else t = 0x00; + } + } + else t = 0x80; + return t; +} + +void DSP2SetByte(uint8 byte, uint16 address) +{ + if ((address & 0xf000) == 0x6000 || + (address >= 0x8000 && address < 0xc000)) + { + if (DSP1.waiting4command) + { + DSP1.command = byte; + DSP1.in_index = 0; + DSP1.waiting4command = FALSE; +// DSP1.first_parameter = TRUE; +// printf("Op%02X\n",byte); + switch (byte) + { + case 0x01:DSP1.in_count=32;break; + case 0x03:DSP1.in_count=1;break; + case 0x05:DSP1.in_count=1;break; + case 0x09:DSP1.in_count=4;break; + case 0x06:DSP1.in_count=1;break; + case 0x0D:DSP1.in_count=2;break; + default: + printf("Op%02X\n",byte); + case 0x0f:DSP1.in_count=0;break; + } + } + else + { + DSP1.parameters [DSP1.in_index] = byte; +// DSP1.first_parameter = FALSE; + DSP1.in_index++; + } + + if (DSP1.in_count==DSP1.in_index) + { + //DSP1.parameters [DSP1.in_index] |= (byte << 8); + // Actually execute the command + DSP1.waiting4command = TRUE; + DSP1.out_index = 0; + switch (DSP1.command) + { + case 0x0D: + if(DSP2Op0DHasLen) + { + DSP2Op0DHasLen=false; + DSP1.out_count=DSP2Op0DOutLen; + //execute Op5 + DSP2_Op0D(); + } + else + { + DSP2Op0DInLen=DSP1.parameters[0]; + DSP2Op0DOutLen=DSP1.parameters[1]; + DSP1.in_index=0; + DSP1.in_count=(DSP2Op0DInLen+1)>>1; + DSP2Op0DHasLen=true; + if(byte) + DSP1.waiting4command=false; + } + break; + case 0x06: + if(DSP2Op06HasLen) + { + DSP2Op06HasLen=false; + DSP1.out_count=DSP2Op06Len; + //execute Op5 + DSP2_Op06(); + } + else + { + DSP2Op06Len=DSP1.parameters[0]; + DSP1.in_index=0; + DSP1.in_count=DSP2Op06Len; + DSP2Op06HasLen=true; + if(byte) + DSP1.waiting4command=false; + } + break; + case 0x01: + DSP1.out_count=32; + DSP2_Op01(); + break; + case 0x09: + // Multiply - don't yet know if this is signed or unsigned + DSP2Op09Word1 = DSP1.parameters[0] | (DSP1.parameters[1]<<8); + DSP2Op09Word2 = DSP1.parameters[2] | (DSP1.parameters[3]<<8); + DSP1.out_count=4; +#ifdef FAST_LSB_WORD_ACCESS + *(uint32 *)DSP1.output = DSP2Op09Word1 * DSP2Op09Word2; +#else + uint32 temp; + temp=DSP2Op09Word1 * DSP2Op09Word2; + DSP1.output[0]=temp&0xFF; + DSP1.output[1]=(temp>>8)&0xFF; + DSP1.output[2]=(temp>>16)&0xFF; + DSP1.output[3]=(temp>>24)&0xFF; +#endif + break; + case 0x05: + if(DSP2Op05HasLen) + { + DSP2Op05HasLen=false; + DSP1.out_count=DSP2Op05Len; + //execute Op5 + DSP2_Op05(); + } + else + { + DSP2Op05Len=DSP1.parameters[0]; + DSP1.in_index=0; + DSP1.in_count=2*DSP2Op05Len; + DSP2Op05HasLen=true; + if(byte) + DSP1.waiting4command=false; + } + break; + + case 0x03: + DSP2Op05Transparent= DSP1.parameters[0]; + //DSP2Op03(); + break; + case 0x0f: + default: + break; + } + } + } +} + +uint8 DSP2GetByte(uint16 address) +{ + uint8 t; + if ((address & 0xf000) == 0x6000 || + (address >= 0x8000 && address < 0xc000)) + { + if (DSP1.out_count) + { + t = (uint8) DSP1.output [DSP1.out_index]; + DSP1.out_index++; + if(DSP1.out_count==DSP1.out_index) + DSP1.out_count=0; + } + else + { + t = 0xff; + } + } + else t = 0x80; + return t; +} + +/*struct SDSP4 { + bool8 waiting4command; + bool8 half_command; + uint16 command; + uint32 in_count; + uint32 in_index; + uint32 out_count; + uint32 out_index; + uint8 parameters [512]; + uint8 output [512]; +}; + +SDSP4 DSP4; + +//#include "dsp4emu.cpp" + +bool DSP4_init=FALSE; + +void DSP4SetByte(uint8 byte, uint16 address) +{ + if(!DSP4_init) + { + // bootup + DSP4.waiting4command=1; + DSP4_init=TRUE; + } + + if ((address & 0xf000) == 0x6000 || + (address >= 0x8000 && address < 0xc000)) + { + if(DSP4.out_index>16); + } + break; + + // unknown: horizontal mapping command + case 0x0011: + { + int16 a,b,c,d,m; + + a = DSP4_READ_WORD(6); + b = DSP4_READ_WORD(4); + c = DSP4_READ_WORD(2); + d = DSP4_READ_WORD(0); + + DSP4_UnknownOP11(a,b,c,d,m); + + DSP4.out_count = 2; + DSP4_WRITE_WORD(0,m); + break; + } + + // track projection + case 0x0001: DSP4_Op01(); break; + + // track projection (pass 2) + case 0x0007: DSP4_Op07(); break; + + // zone projections (fuel/repair/lap/teleport/...) + case 0x0008: DSP4_Op08(); break; + + // sprite transformation + case 0x0009: DSP4_Op09(); break; + + // fast track projection + case 0x000D: DSP4_Op0D(); break; + + // single-player selection + case 0x0003: DSP4_Op03(); break; + + // clear OAM + case 0x0005: + { + op06_index = 0; + op06_offset = 0; + for( int lcv=0; lcv<32; lcv++ ) + op06_OAM[lcv] = 0; + break; + } + + // multi-player selection + case 0x000E: DSP4_Op0E(); break; + +#undef PRINT + + // transfer OAM + case 0x0006: + { + DSP4.out_count = 32; + for( int lcv=0; lcv<32; lcv++ ) + DSP4.output[lcv] = op06_OAM[lcv]; + } + break; + + // unknown + case 0x000A: + { + int16 in1a = DSP4_READ_WORD(0); + int16 in2a = DSP4_READ_WORD(2); + int16 in3a = DSP4_READ_WORD(4); + int16 out1a,out2a,out3a,out4a; + + // NOTE: Snes9x only! + // For some odd reason, the input nybbles are reversed + + DSP4_Op0A(in2a,out1a,out2a,out3a,out4a); + + DSP4.out_count=8; + + // Hack: Reverse the outputs for now to compensate + // Otherwise the AI gets really flaky + DSP4_WRITE_WORD(0,out2a); + DSP4_WRITE_WORD(2,out1a); + DSP4_WRITE_WORD(4,out4a); + DSP4_WRITE_WORD(6,out3a); + } + break; + + // set OAM + case 0x000B: + { + int16 sp_x = DSP4_READ_WORD(0); + int16 sp_y = DSP4_READ_WORD(2); + int16 oam = DSP4_READ_WORD(4); + + if ((sp_y < 0) || ((sp_y & 0x01ff) < 0x00eb)) + { + short Row = (sp_y >> 3) & 0x1f; + + if (RowCount[Row] < MaxTilesPerRow) + { + RowCount[Row]++; + + // yield OAM output + DSP4.out_count = 6; + DSP4_WRITE_WORD(0,1); + + // pack OAM data: x,y,name,attr + DSP4.output[2] = sp_x & 0xff; + DSP4.output[3] = sp_y & 0xff; + DSP4_WRITE_WORD(4,oam); + + // OAM: size,msb data + DSP4_Op06(0,0); + } + } + } + break; + + default: break; + } + } + } +} + +uint8 DSP4GetByte(uint16 address) +{ + uint8 t; + if ((address & 0xf000) == 0x6000 || + (address >= 0x8000 && address < 0xc000)) + { + if (DSP4.out_count) + { + t = (uint8) DSP4.output [DSP4.out_index]; + DSP4.out_index++; + if(DSP4.out_count==DSP4.out_index) + DSP4.out_count=0; + } + else + t = 0xff; + } + else + { + t = 0x80; + } + + return t; +} +*/ \ No newline at end of file diff --git a/src/dsp1.h b/src/dsp1.h new file mode 100644 index 0000000..82fe3f1 --- /dev/null +++ b/src/dsp1.h @@ -0,0 +1,130 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ + +#ifndef _DSP1_H_ +#define _DSP1_H_ + +extern void (*SetDSP)(uint8, uint16); +extern uint8 (*GetDSP)(uint16); + +void DSP1SetByte(uint8 byte, uint16 address); +uint8 DSP1GetByte(uint16 address); + +void DSP2SetByte(uint8 byte, uint16 address); +uint8 DSP2GetByte(uint16 address); + +void DSP3SetByte(uint8 byte, uint16 address); +uint8 DSP3GetByte(uint16 address); +void DSP3_Reset(); + +void DSP4SetByte(uint8 byte, uint16 address); +uint8 DSP4GetByte(uint16 address); + +struct SDSP1 { + uint8 version; + bool8 waiting4command; + bool8 first_parameter; + uint8 command; + uint32 in_count; + uint32 in_index; + uint32 out_count; + uint32 out_index; + uint8 parameters [512]; + uint8 output [512]; +}; + +START_EXTERN_C +void S9xResetDSP1 (); +uint8 S9xGetDSP (uint16 Address); +void S9xSetDSP (uint8 Byte, uint16 Address); +END_EXTERN_C + +extern struct SDSP1 DSP1; + +#endif diff --git a/src/dsp1_gp32.h b/src/dsp1_gp32.h new file mode 100644 index 0000000..bd3ced1 --- /dev/null +++ b/src/dsp1_gp32.h @@ -0,0 +1,244 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _DSP1_H_ +#define _DSP1_H_ + +// Simple vector and matrix types +typedef double MATRIX[3][3]; +typedef double VECTOR[3]; + +enum AttitudeMatrix { MatrixA, MatrixB, MatrixC }; + +struct SDSP1 { + bool8 waiting4command; + bool8 first_parameter; + uint8 command; + uint32 in_count; + uint32 in_index; + uint32 out_count; + uint32 out_index; + uint16 parameters [10]; + uint16 output [10]; + + // Attitude matrices + MATRIX vMa; + MATRIX vMb; + MATRIX vMc; + + // Matrix and translaton vector for + // transforming a 3D position into the global coordinate system, + // from the view space coordinate system. + MATRIX vM; + VECTOR vT; + + // Focal distance + double vFov; + + // A precalculated value for optimization + double vPlaneD; + + // Raster position of horizon + double vHorizon; + + // Convert a 2D screen coordinate to a 3D ground coordinate in global coordinate system. + void ScreenToGround(VECTOR &v, double X2d, double Y2d); + + MATRIX &GetMatrix( AttitudeMatrix Matrix ); +}; + +///////////////// DSP Commands //////////////////// + +// DSP1 Command 02h +struct DSP1_Parameter +{ + DSP1_Parameter( int16 Fx, int16 Fy, int16 Fz, + uint16 Lfe, uint16 Les, + int8 Aas, int8 Azs ); + + // Raster number of imaginary center + int16 Vof; // -32768 ~ +32767 + + // Raster number representing + // horizontal line. + int16 Vva; // -32768 ~ +32767 + + // X,Y coordinate of the point + // projected on the center of the screen + // (ground coordinate) + int16 Cx; // -32768 ~ +32767 + int16 Cy; // -32768 ~ +32767 +}; + +// DSP1 Command 0Ah +struct DSP1_Raster +{ + DSP1_Raster( int16 Vs ); + + // Linear transformation matrix elements + // for each raster + int16 An; + int16 Bn; + int16 Cn; + int16 Dn; +}; + +// DSP1 Command 06h +struct DSP1_Project +{ + DSP1_Project( int16 x, int16 y, int16 z ); + + int16 H; + int16 V; + int16 M; +}; + +// DSP1 Command 0Eh +struct DSP1_Target +{ + DSP1_Target( int16 h, int16 v ); + + int16 X; + int16 Y; +}; + +// DSP1 Command 04h +struct DSP1_Triangle +{ + DSP1_Triangle (int16 Theta, int16 r ); + int16 S; + int16 C; +}; + +// DSP1 Command 08h +struct DSP1_Radius +{ + DSP1_Radius( int16 x, int16 y, int16 z ); + int16 Ll; + int16 Lh; +}; + +// DSP1 Command 18h +int16 DSP1_Range( int16 x, int16 y, int16 z, int16 r ); + +// DSP1 Command 28h +int16 DSP1_Distance( int16 x, int16 y, int16 z ); + +// DSP1 Command 0Ch +struct DSP1_Rotate +{ + DSP1_Rotate (int16 A, int16 x1, int16 y1); + + int16 x2; + int16 y2; +}; + +// DSP1 Command 1Ch +struct DSP1_Polar +{ + DSP1_Polar( int8 Za, int8 Xa, int8 Ya, int16 x, int16 y, int16 z ); + + int16 X; + int16 Y; + int16 Z; +}; + +// DSP1 Command 01h, 11h and 21h +void DSP1_Attitude( int16 m, int8 Za, int8 Xa, int8 Ya, AttitudeMatrix Matrix ); + +// DSP1 Command 0Dh, 1Dh and 2Dh +struct DSP1_Objective +{ + DSP1_Objective( int16 x, int16 y, int16 z, AttitudeMatrix Matrix ); + + int16 F; + int16 L; + int16 U; +}; + +// DSP1 Command 03h, 13h and 23h +struct DSP1_Subjective +{ + DSP1_Subjective( int16 F, int16 L, int16 U, AttitudeMatrix Matrix ); + + int16 X; + int16 Y; + int16 Z; +}; + +// DSP1 Command 0Bh, 1Bh and 2Bh +int16 DSP1_Scalar( int16 x, int16 y, int16 z, AttitudeMatrix Matrix ); + +// DSP1 Command 14h +struct DSP1_Gyrate +{ + DSP1_Gyrate( int8 Zi, int8 Xi, int8 Yi, + int8 dU, int8 dF, int8 dL ); + + int8 Z0; + int8 X0; + int8 Y0; +}; + +// DSP1 Command 00h +int16 DSP1_Multiply( int16 k, int16 I ); + +// DSP1 Command 10h +struct DSP1_Inverse +{ + DSP1_Inverse( int16 a, int16 b ); + + int16 A; + int16 B; +}; + +START_EXTERN_C +void S9xResetDSP1 (); +uint8 S9xGetDSP (uint16 Address); +void S9xSetDSP (uint8 Byte, uint16 Address); +END_EXTERN_C + +#ifndef __GP32__ +extern struct SDSP1 DSP1; +#else +extern "C" struct SDSP1 DSP1; +#endif + +#endif diff --git a/src/dsp1emu.c b/src/dsp1emu.c new file mode 100644 index 0000000..ea402a7 --- /dev/null +++ b/src/dsp1emu.c @@ -0,0 +1,1451 @@ +//Copyright (C) 1997-2001 ZSNES Team ( zsknight@zsnes.com / _demo_@zsnes.com ) +// +//This program is free software; you can redistribute it and/or +//modify it under the terms of the GNU General Public License +//as published by the Free Software Foundation; either +//version 2 of the License, or (at your option) any later +//version. +// +//This program is distributed in the hope that it will be useful, +//but WITHOUT ANY WARRANTY; without even the implied warranty of +//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +//GNU General Public License for more details. +// +//You should have received a copy of the GNU General Public License +//along with this program; if not, write to the Free Software +//Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +//#define __ZSNES__ + +#if (defined __ZSNES__ && __LINUX__) +#include "../gblhdr.h" +#else +#endif + + +#include + + + +//#define DebugDSP1 + +// uncomment some lines to test +//#define printinfo +//#define debug02 +//#define debug0A +//#define debug06 + +#define __OPT__ +#define __OPT02__ +#define __OPT06__ + +#ifdef DebugDSP1 + +FILE * LogFile = NULL; + +void Log_Message (char *Message, ...) +{ + char Msg[400]; + va_list ap; + + va_start(ap,Message); + vsprintf(Msg,Message,ap ); + va_end(ap); + + strcat(Msg,"\r\n\0"); + fwrite(Msg,strlen(Msg),1,LogFile); + fflush (LogFile); +} + + +#endif + +const unsigned short DSP1ROM[1024] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, + 0x0040, 0x0080, 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, + 0x4000, 0x7fff, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, + 0x0100, 0x0080, 0x0040, 0x0020, 0x0001, 0x0008, 0x0004, 0x0002, + 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x8000, 0xffe5, 0x0100, 0x7fff, 0x7f02, 0x7e08, + 0x7d12, 0x7c1f, 0x7b30, 0x7a45, 0x795d, 0x7878, 0x7797, 0x76ba, + 0x75df, 0x7507, 0x7433, 0x7361, 0x7293, 0x71c7, 0x70fe, 0x7038, + 0x6f75, 0x6eb4, 0x6df6, 0x6d3a, 0x6c81, 0x6bca, 0x6b16, 0x6a64, + 0x69b4, 0x6907, 0x685b, 0x67b2, 0x670b, 0x6666, 0x65c4, 0x6523, + 0x6484, 0x63e7, 0x634c, 0x62b3, 0x621c, 0x6186, 0x60f2, 0x6060, + 0x5fd0, 0x5f41, 0x5eb5, 0x5e29, 0x5d9f, 0x5d17, 0x5c91, 0x5c0c, + 0x5b88, 0x5b06, 0x5a85, 0x5a06, 0x5988, 0x590b, 0x5890, 0x5816, + 0x579d, 0x5726, 0x56b0, 0x563b, 0x55c8, 0x5555, 0x54e4, 0x5474, + 0x5405, 0x5398, 0x532b, 0x52bf, 0x5255, 0x51ec, 0x5183, 0x511c, + 0x50b6, 0x5050, 0x4fec, 0x4f89, 0x4f26, 0x4ec5, 0x4e64, 0x4e05, + 0x4da6, 0x4d48, 0x4cec, 0x4c90, 0x4c34, 0x4bda, 0x4b81, 0x4b28, + 0x4ad0, 0x4a79, 0x4a23, 0x49cd, 0x4979, 0x4925, 0x48d1, 0x487f, + 0x482d, 0x47dc, 0x478c, 0x473c, 0x46ed, 0x469f, 0x4651, 0x4604, + 0x45b8, 0x456c, 0x4521, 0x44d7, 0x448d, 0x4444, 0x43fc, 0x43b4, + 0x436d, 0x4326, 0x42e0, 0x429a, 0x4255, 0x4211, 0x41cd, 0x4189, + 0x4146, 0x4104, 0x40c2, 0x4081, 0x4040, 0x3fff, 0x41f7, 0x43e1, + 0x45bd, 0x478d, 0x4951, 0x4b0b, 0x4cbb, 0x4e61, 0x4fff, 0x5194, + 0x5322, 0x54a9, 0x5628, 0x57a2, 0x5914, 0x5a81, 0x5be9, 0x5d4a, + 0x5ea7, 0x5fff, 0x6152, 0x62a0, 0x63ea, 0x6530, 0x6672, 0x67b0, + 0x68ea, 0x6a20, 0x6b53, 0x6c83, 0x6daf, 0x6ed9, 0x6fff, 0x7122, + 0x7242, 0x735f, 0x747a, 0x7592, 0x76a7, 0x77ba, 0x78cb, 0x79d9, + 0x7ae5, 0x7bee, 0x7cf5, 0x7dfa, 0x7efe, 0x7fff, 0x0000, 0x0324, + 0x0647, 0x096a, 0x0c8b, 0x0fab, 0x12c8, 0x15e2, 0x18f8, 0x1c0b, + 0x1f19, 0x2223, 0x2528, 0x2826, 0x2b1f, 0x2e11, 0x30fb, 0x33de, + 0x36ba, 0x398c, 0x3c56, 0x3f17, 0x41ce, 0x447a, 0x471c, 0x49b4, + 0x4c3f, 0x4ebf, 0x5133, 0x539b, 0x55f5, 0x5842, 0x5a82, 0x5cb4, + 0x5ed7, 0x60ec, 0x62f2, 0x64e8, 0x66cf, 0x68a6, 0x6a6d, 0x6c24, + 0x6dca, 0x6f5f, 0x70e2, 0x7255, 0x73b5, 0x7504, 0x7641, 0x776c, + 0x7884, 0x798a, 0x7a7d, 0x7b5d, 0x7c29, 0x7ce3, 0x7d8a, 0x7e1d, + 0x7e9d, 0x7f09, 0x7f62, 0x7fa7, 0x7fd8, 0x7ff6, 0x7fff, 0x7ff6, + 0x7fd8, 0x7fa7, 0x7f62, 0x7f09, 0x7e9d, 0x7e1d, 0x7d8a, 0x7ce3, + 0x7c29, 0x7b5d, 0x7a7d, 0x798a, 0x7884, 0x776c, 0x7641, 0x7504, + 0x73b5, 0x7255, 0x70e2, 0x6f5f, 0x6dca, 0x6c24, 0x6a6d, 0x68a6, + 0x66cf, 0x64e8, 0x62f2, 0x60ec, 0x5ed7, 0x5cb4, 0x5a82, 0x5842, + 0x55f5, 0x539b, 0x5133, 0x4ebf, 0x4c3f, 0x49b4, 0x471c, 0x447a, + 0x41ce, 0x3f17, 0x3c56, 0x398c, 0x36ba, 0x33de, 0x30fb, 0x2e11, + 0x2b1f, 0x2826, 0x2528, 0x2223, 0x1f19, 0x1c0b, 0x18f8, 0x15e2, + 0x12c8, 0x0fab, 0x0c8b, 0x096a, 0x0647, 0x0324, 0x7fff, 0x7ff6, + 0x7fd8, 0x7fa7, 0x7f62, 0x7f09, 0x7e9d, 0x7e1d, 0x7d8a, 0x7ce3, + 0x7c29, 0x7b5d, 0x7a7d, 0x798a, 0x7884, 0x776c, 0x7641, 0x7504, + 0x73b5, 0x7255, 0x70e2, 0x6f5f, 0x6dca, 0x6c24, 0x6a6d, 0x68a6, + 0x66cf, 0x64e8, 0x62f2, 0x60ec, 0x5ed7, 0x5cb4, 0x5a82, 0x5842, + 0x55f5, 0x539b, 0x5133, 0x4ebf, 0x4c3f, 0x49b4, 0x471c, 0x447a, + 0x41ce, 0x3f17, 0x3c56, 0x398c, 0x36ba, 0x33de, 0x30fb, 0x2e11, + 0x2b1f, 0x2826, 0x2528, 0x2223, 0x1f19, 0x1c0b, 0x18f8, 0x15e2, + 0x12c8, 0x0fab, 0x0c8b, 0x096a, 0x0647, 0x0324, 0x0000, 0xfcdc, + 0xf9b9, 0xf696, 0xf375, 0xf055, 0xed38, 0xea1e, 0xe708, 0xe3f5, + 0xe0e7, 0xdddd, 0xdad8, 0xd7da, 0xd4e1, 0xd1ef, 0xcf05, 0xcc22, + 0xc946, 0xc674, 0xc3aa, 0xc0e9, 0xbe32, 0xbb86, 0xb8e4, 0xb64c, + 0xb3c1, 0xb141, 0xaecd, 0xac65, 0xaa0b, 0xa7be, 0xa57e, 0xa34c, + 0xa129, 0x9f14, 0x9d0e, 0x9b18, 0x9931, 0x975a, 0x9593, 0x93dc, + 0x9236, 0x90a1, 0x8f1e, 0x8dab, 0x8c4b, 0x8afc, 0x89bf, 0x8894, + 0x877c, 0x8676, 0x8583, 0x84a3, 0x83d7, 0x831d, 0x8276, 0x81e3, + 0x8163, 0x80f7, 0x809e, 0x8059, 0x8028, 0x800a, 0x6488, 0x0080, + 0x03ff, 0x0116, 0x0002, 0x0080, 0x4000, 0x3fd7, 0x3faf, 0x3f86, + 0x3f5d, 0x3f34, 0x3f0c, 0x3ee3, 0x3eba, 0x3e91, 0x3e68, 0x3e40, + 0x3e17, 0x3dee, 0x3dc5, 0x3d9c, 0x3d74, 0x3d4b, 0x3d22, 0x3cf9, + 0x3cd0, 0x3ca7, 0x3c7f, 0x3c56, 0x3c2d, 0x3c04, 0x3bdb, 0x3bb2, + 0x3b89, 0x3b60, 0x3b37, 0x3b0e, 0x3ae5, 0x3abc, 0x3a93, 0x3a69, + 0x3a40, 0x3a17, 0x39ee, 0x39c5, 0x399c, 0x3972, 0x3949, 0x3920, + 0x38f6, 0x38cd, 0x38a4, 0x387a, 0x3851, 0x3827, 0x37fe, 0x37d4, + 0x37aa, 0x3781, 0x3757, 0x372d, 0x3704, 0x36da, 0x36b0, 0x3686, + 0x365c, 0x3632, 0x3609, 0x35df, 0x35b4, 0x358a, 0x3560, 0x3536, + 0x350c, 0x34e1, 0x34b7, 0x348d, 0x3462, 0x3438, 0x340d, 0x33e3, + 0x33b8, 0x338d, 0x3363, 0x3338, 0x330d, 0x32e2, 0x32b7, 0x328c, + 0x3261, 0x3236, 0x320b, 0x31df, 0x31b4, 0x3188, 0x315d, 0x3131, + 0x3106, 0x30da, 0x30ae, 0x3083, 0x3057, 0x302b, 0x2fff, 0x2fd2, + 0x2fa6, 0x2f7a, 0x2f4d, 0x2f21, 0x2ef4, 0x2ec8, 0x2e9b, 0x2e6e, + 0x2e41, 0x2e14, 0x2de7, 0x2dba, 0x2d8d, 0x2d60, 0x2d32, 0x2d05, + 0x2cd7, 0x2ca9, 0x2c7b, 0x2c4d, 0x2c1f, 0x2bf1, 0x2bc3, 0x2b94, + 0x2b66, 0x2b37, 0x2b09, 0x2ada, 0x2aab, 0x2a7c, 0x2a4c, 0x2a1d, + 0x29ed, 0x29be, 0x298e, 0x295e, 0x292e, 0x28fe, 0x28ce, 0x289d, + 0x286d, 0x283c, 0x280b, 0x27da, 0x27a9, 0x2777, 0x2746, 0x2714, + 0x26e2, 0x26b0, 0x267e, 0x264c, 0x2619, 0x25e7, 0x25b4, 0x2581, + 0x254d, 0x251a, 0x24e6, 0x24b2, 0x247e, 0x244a, 0x2415, 0x23e1, + 0x23ac, 0x2376, 0x2341, 0x230b, 0x22d6, 0x229f, 0x2269, 0x2232, + 0x21fc, 0x21c4, 0x218d, 0x2155, 0x211d, 0x20e5, 0x20ad, 0x2074, + 0x203b, 0x2001, 0x1fc7, 0x1f8d, 0x1f53, 0x1f18, 0x1edd, 0x1ea1, + 0x1e66, 0x1e29, 0x1ded, 0x1db0, 0x1d72, 0x1d35, 0x1cf6, 0x1cb8, + 0x1c79, 0x1c39, 0x1bf9, 0x1bb8, 0x1b77, 0x1b36, 0x1af4, 0x1ab1, + 0x1a6e, 0x1a2a, 0x19e6, 0x19a1, 0x195c, 0x1915, 0x18ce, 0x1887, + 0x183f, 0x17f5, 0x17ac, 0x1761, 0x1715, 0x16c9, 0x167c, 0x162e, + 0x15df, 0x158e, 0x153d, 0x14eb, 0x1497, 0x1442, 0x13ec, 0x1395, + 0x133c, 0x12e2, 0x1286, 0x1228, 0x11c9, 0x1167, 0x1104, 0x109e, + 0x1036, 0x0fcc, 0x0f5f, 0x0eef, 0x0e7b, 0x0e04, 0x0d89, 0x0d0a, + 0x0c86, 0x0bfd, 0x0b6d, 0x0ad6, 0x0a36, 0x098d, 0x08d7, 0x0811, + 0x0736, 0x063e, 0x0519, 0x039a, 0x0000, 0x7fff, 0x0100, 0x0080, + 0x021d, 0x00c8, 0x00ce, 0x0048, 0x0a26, 0x277a, 0x00ce, 0x6488, + 0x14ac, 0x0001, 0x00f9, 0x00fc, 0x00ff, 0x00fc, 0x00f9, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff}; + +/***************************************************************************\ +* Math tables * +\***************************************************************************/ + +#define INCR 2048 +#define Angle(x) (((x)/(65536/INCR)) & (INCR-1)) +#define Cos(x) ((float) CosTable2[x]) +#define Sin(x) ((float) SinTable2[x]) +#ifdef PI +#undef PI +#endif +#define PI 3.1415926535897932384626433832795 +float CosTable2[INCR]; +float SinTable2[INCR]; + +int32 CosTable2Fix[INCR];//=NULL; +int32 SinTable2Fix[INCR];//=NULL; + + +#define AngleFix(x) (((x)>>5) & (INCR-1)) +#define CosFix(x) (CosTable2Fix[x]) +#define SinFix(x) (SinTable2Fix[x]) + + +float Atan(float x) +{ + if ((x>=1) || (x<=1)) + return (x/(1+0.28*x*x)); + else + return (PI/2 - Atan(1/x)); +} + + +/***************************************************************************\ +* DSP1 code * +\***************************************************************************/ + +void InitDSP(void) +{ +#ifdef __OPT__ + unsigned int i; + +// CosTable2Fix = (int32 *) ljz_malloc(INCR*sizeof(int32)); +// SinTable2Fix = (int32 *) ljz_malloc(INCR*sizeof(int32)); + + for (i=0; i> 15; + + #ifdef DebugDSP1 + Log_Message("OP00 MULT %d*%d/32768=%d",Op00Multiplicand,Op00Multiplier,Op00Result); + #endif +} + +short Op20Multiplicand; +short Op20Multiplier; +short Op20Result; + +void DSPOp20() +{ + Op20Result= Op20Multiplicand * Op20Multiplier >> 15; + Op20Result++; + + #ifdef DebugDSP1 + Log_Message("OP20 MULT %d*%d/32768=%d",Op20Multiplicand,Op20Multiplier,Op20Result); + #endif +} + +signed short Op10Coefficient; +signed short Op10Exponent; +signed short Op10CoefficientR; +signed short Op10ExponentR; + +void DSP1_Inverse(short Coefficient, short Exponent, short *iCoefficient, short *iExponent) +{ + // Step One: Division by Zero + if (Coefficient == 0x0000) + { + *iCoefficient = 0x7fff; + *iExponent = 0x002f; + } + else + { + short Sign = 1; + + // Step Two: Remove Sign + if (Coefficient < 0) + { + if (Coefficient < -32767) Coefficient = -32767; + Coefficient = -Coefficient; + Sign = -1; + } + + // Step Three: Normalize + while (Coefficient < 0x4000) + { + Coefficient <<= 1; + Exponent--; + } + + // Step Four: Special Case + if (Coefficient == 0x4000) + if (Sign == 1) *iCoefficient = 0x7fff; + else { + *iCoefficient = -0x4000; + Exponent--; + } + else { + // Step Five: Initial Guess + short i = DSP1ROM[(((Coefficient - 0x4000) >> 7) + 0x0065)&1023]; + + // Step Six: Iterate "estimated" Newton's Method + i = (i + (-i * (Coefficient * i >> 15) >> 15)) << 1; + i = (i + (-i * (Coefficient * i >> 15) >> 15)) << 1; + + *iCoefficient = i * Sign; + } + + *iExponent = 1 - Exponent; + } +} + +void DSPOp10() +{ + DSP1_Inverse(Op10Coefficient, Op10Exponent, &Op10CoefficientR, &Op10ExponentR); + #ifdef DebugDSP1 + Log_Message("OP10 INV %d*2^%d = %d*2^%d", Op10Coefficient, Op10Exponent, Op10CoefficientR, Op10ExponentR); + #endif +} + +short Op04Angle; +short Op04Radius; +short Op04Sin; +short Op04Cos; + +const short DSP1_MulTable[256] = { + 0x0000, 0x0003, 0x0006, 0x0009, 0x000c, 0x000f, 0x0012, 0x0015, + 0x0019, 0x001c, 0x001f, 0x0022, 0x0025, 0x0028, 0x002b, 0x002f, + 0x0032, 0x0035, 0x0038, 0x003b, 0x003e, 0x0041, 0x0045, 0x0048, + 0x004b, 0x004e, 0x0051, 0x0054, 0x0057, 0x005b, 0x005e, 0x0061, + 0x0064, 0x0067, 0x006a, 0x006d, 0x0071, 0x0074, 0x0077, 0x007a, + 0x007d, 0x0080, 0x0083, 0x0087, 0x008a, 0x008d, 0x0090, 0x0093, + 0x0096, 0x0099, 0x009d, 0x00a0, 0x00a3, 0x00a6, 0x00a9, 0x00ac, + 0x00af, 0x00b3, 0x00b6, 0x00b9, 0x00bc, 0x00bf, 0x00c2, 0x00c5, + 0x00c9, 0x00cc, 0x00cf, 0x00d2, 0x00d5, 0x00d8, 0x00db, 0x00df, + 0x00e2, 0x00e5, 0x00e8, 0x00eb, 0x00ee, 0x00f1, 0x00f5, 0x00f8, + 0x00fb, 0x00fe, 0x0101, 0x0104, 0x0107, 0x010b, 0x010e, 0x0111, + 0x0114, 0x0117, 0x011a, 0x011d, 0x0121, 0x0124, 0x0127, 0x012a, + 0x012d, 0x0130, 0x0133, 0x0137, 0x013a, 0x013d, 0x0140, 0x0143, + 0x0146, 0x0149, 0x014d, 0x0150, 0x0153, 0x0156, 0x0159, 0x015c, + 0x015f, 0x0163, 0x0166, 0x0169, 0x016c, 0x016f, 0x0172, 0x0175, + 0x0178, 0x017c, 0x017f, 0x0182, 0x0185, 0x0188, 0x018b, 0x018e, + 0x0192, 0x0195, 0x0198, 0x019b, 0x019e, 0x01a1, 0x01a4, 0x01a8, + 0x01ab, 0x01ae, 0x01b1, 0x01b4, 0x01b7, 0x01ba, 0x01be, 0x01c1, + 0x01c4, 0x01c7, 0x01ca, 0x01cd, 0x01d0, 0x01d4, 0x01d7, 0x01da, + 0x01dd, 0x01e0, 0x01e3, 0x01e6, 0x01ea, 0x01ed, 0x01f0, 0x01f3, + 0x01f6, 0x01f9, 0x01fc, 0x0200, 0x0203, 0x0206, 0x0209, 0x020c, + 0x020f, 0x0212, 0x0216, 0x0219, 0x021c, 0x021f, 0x0222, 0x0225, + 0x0228, 0x022c, 0x022f, 0x0232, 0x0235, 0x0238, 0x023b, 0x023e, + 0x0242, 0x0245, 0x0248, 0x024b, 0x024e, 0x0251, 0x0254, 0x0258, + 0x025b, 0x025e, 0x0261, 0x0264, 0x0267, 0x026a, 0x026e, 0x0271, + 0x0274, 0x0277, 0x027a, 0x027d, 0x0280, 0x0284, 0x0287, 0x028a, + 0x028d, 0x0290, 0x0293, 0x0296, 0x029a, 0x029d, 0x02a0, 0x02a3, + 0x02a6, 0x02a9, 0x02ac, 0x02b0, 0x02b3, 0x02b6, 0x02b9, 0x02bc, + 0x02bf, 0x02c2, 0x02c6, 0x02c9, 0x02cc, 0x02cf, 0x02d2, 0x02d5, + 0x02d8, 0x02db, 0x02df, 0x02e2, 0x02e5, 0x02e8, 0x02eb, 0x02ee, + 0x02f1, 0x02f5, 0x02f8, 0x02fb, 0x02fe, 0x0301, 0x0304, 0x0307, + 0x030b, 0x030e, 0x0311, 0x0314, 0x0317, 0x031a, 0x031d, 0x0321}; + +const short DSP1_SinTable[256] = { + 0x0000, 0x0324, 0x0647, 0x096a, 0x0c8b, 0x0fab, 0x12c8, 0x15e2, + 0x18f8, 0x1c0b, 0x1f19, 0x2223, 0x2528, 0x2826, 0x2b1f, 0x2e11, + 0x30fb, 0x33de, 0x36ba, 0x398c, 0x3c56, 0x3f17, 0x41ce, 0x447a, + 0x471c, 0x49b4, 0x4c3f, 0x4ebf, 0x5133, 0x539b, 0x55f5, 0x5842, + 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e8, 0x66cf, 0x68a6, + 0x6a6d, 0x6c24, 0x6dca, 0x6f5f, 0x70e2, 0x7255, 0x73b5, 0x7504, + 0x7641, 0x776c, 0x7884, 0x798a, 0x7a7d, 0x7b5d, 0x7c29, 0x7ce3, + 0x7d8a, 0x7e1d, 0x7e9d, 0x7f09, 0x7f62, 0x7fa7, 0x7fd8, 0x7ff6, + 0x7fff, 0x7ff6, 0x7fd8, 0x7fa7, 0x7f62, 0x7f09, 0x7e9d, 0x7e1d, + 0x7d8a, 0x7ce3, 0x7c29, 0x7b5d, 0x7a7d, 0x798a, 0x7884, 0x776c, + 0x7641, 0x7504, 0x73b5, 0x7255, 0x70e2, 0x6f5f, 0x6dca, 0x6c24, + 0x6a6d, 0x68a6, 0x66cf, 0x64e8, 0x62f2, 0x60ec, 0x5ed7, 0x5cb4, + 0x5a82, 0x5842, 0x55f5, 0x539b, 0x5133, 0x4ebf, 0x4c3f, 0x49b4, + 0x471c, 0x447a, 0x41ce, 0x3f17, 0x3c56, 0x398c, 0x36ba, 0x33de, + 0x30fb, 0x2e11, 0x2b1f, 0x2826, 0x2528, 0x2223, 0x1f19, 0x1c0b, + 0x18f8, 0x15e2, 0x12c8, 0x0fab, 0x0c8b, 0x096a, 0x0647, 0x0324, + -0x0000, -0x0324, -0x0647, -0x096a, -0x0c8b, -0x0fab, -0x12c8, -0x15e2, + -0x18f8, -0x1c0b, -0x1f19, -0x2223, -0x2528, -0x2826, -0x2b1f, -0x2e11, + -0x30fb, -0x33de, -0x36ba, -0x398c, -0x3c56, -0x3f17, -0x41ce, -0x447a, + -0x471c, -0x49b4, -0x4c3f, -0x4ebf, -0x5133, -0x539b, -0x55f5, -0x5842, + -0x5a82, -0x5cb4, -0x5ed7, -0x60ec, -0x62f2, -0x64e8, -0x66cf, -0x68a6, + -0x6a6d, -0x6c24, -0x6dca, -0x6f5f, -0x70e2, -0x7255, -0x73b5, -0x7504, + -0x7641, -0x776c, -0x7884, -0x798a, -0x7a7d, -0x7b5d, -0x7c29, -0x7ce3, + -0x7d8a, -0x7e1d, -0x7e9d, -0x7f09, -0x7f62, -0x7fa7, -0x7fd8, -0x7ff6, + -0x7fff, -0x7ff6, -0x7fd8, -0x7fa7, -0x7f62, -0x7f09, -0x7e9d, -0x7e1d, + -0x7d8a, -0x7ce3, -0x7c29, -0x7b5d, -0x7a7d, -0x798a, -0x7884, -0x776c, + -0x7641, -0x7504, -0x73b5, -0x7255, -0x70e2, -0x6f5f, -0x6dca, -0x6c24, + -0x6a6d, -0x68a6, -0x66cf, -0x64e8, -0x62f2, -0x60ec, -0x5ed7, -0x5cb4, + -0x5a82, -0x5842, -0x55f5, -0x539b, -0x5133, -0x4ebf, -0x4c3f, -0x49b4, + -0x471c, -0x447a, -0x41ce, -0x3f17, -0x3c56, -0x398c, -0x36ba, -0x33de, + -0x30fb, -0x2e11, -0x2b1f, -0x2826, -0x2528, -0x2223, -0x1f19, -0x1c0b, + -0x18f8, -0x15e2, -0x12c8, -0x0fab, -0x0c8b, -0x096a, -0x0647, -0x0324}; + +short DSP1_Sin(short Angle) +{ + if (Angle < 0) { + if (Angle == -32768) return 0; + return -DSP1_Sin(-Angle); + } + int S = DSP1_SinTable[Angle >> 8] + (DSP1_MulTable[Angle & 0xff] * DSP1_SinTable[0x40 + (Angle >> 8)] >> 15); + if (S > 32767) S = 32767; + return (short) S; +} + +short DSP1_Cos(short Angle) +{ + if (Angle < 0) { + if (Angle == -32768) return -32768; + Angle = -Angle; + } + int S = DSP1_SinTable[0x40 + (Angle >> 8)] - (DSP1_MulTable[Angle & 0xff] * DSP1_SinTable[Angle >> 8] >> 15); + if (S < -32768) S = -32767; + return (short) S; +} + +void DSP1_Normalize(short m, short *Coefficient, short *Exponent) +{ + short i = 0x4000; + short e = 0; + + if (m < 0) + while ((m & i) && i) { + i >>= 1; + e++; + } + else + while (!(m & i) && i) { + i >>= 1; + e++; + } + + if (e > 0) + *Coefficient = m * DSP1ROM[(0x21 + e)&1023] << 1; + else + *Coefficient = m; + + *Exponent -= e; +} + +void DSP1_Normalizefloat(int Product, short *Coefficient, short *Exponent) +{ + short n = Product & 0x7fff; + short m = Product >> 15; + short i = 0x4000; + short e = 0; + + if (m < 0) + while ((m & i) && i) { + i >>= 1; + e++; + } + else + while (!(m & i) && i) { + i >>= 1; + e++; + } + + if (e > 0) + { + *Coefficient = m * DSP1ROM[(0x0021 + e)&1023] << 1; + + if (e < 15) + *Coefficient += n * DSP1ROM[(0x0040 - e)&1023] >> 15; + else + { + i = 0x4000; + + if (m < 0) + while ((n & i) && i) { + i >>= 1; + e++; + } + else + while (!(n & i) && i) { + i >>= 1; + e++; + } + + if (e > 15) + *Coefficient = n * DSP1ROM[(0x0012 + e)&1023] << 1; + else + *Coefficient += n; + } + } + else + *Coefficient = m; + + *Exponent = e; +} + +void DSPOp04() +{ + Op04Sin = DSP1_Sin(Op04Angle) * Op04Radius >> 15; + Op04Cos = DSP1_Cos(Op04Angle) * Op04Radius >> 15; +} + +short Op0CA; +short Op0CX1; +short Op0CY1; +short Op0CX2; +short Op0CY2; + +void DSPOp0C() +{ + Op0CX2 = (Op0CY1 * DSP1_Sin(Op0CA) >> 15) + (Op0CX1 * DSP1_Cos(Op0CA) >> 15); + Op0CY2 = (Op0CY1 * DSP1_Cos(Op0CA) >> 15) - (Op0CX1 * DSP1_Sin(Op0CA) >> 15); +} + + +short Op02FX; +short Op02FY; +short Op02FZ; +short Op02LFE; +short Op02LES; +unsigned short Op02AAS; +unsigned short Op02AZS; +unsigned short Op02VOF; +unsigned short Op02VVA; + +short Op02CX; +short Op02CY; +float Op02CXF; +float Op02CYF; +float ViewerX0; +float ViewerY0; +float ViewerZ0; +float ViewerX1; +float ViewerY1; +float ViewerZ1; +float ViewerX; +float ViewerY; +float ViewerZ; +int ViewerAX; +int ViewerAY; +int ViewerAZ; +float NumberOfSlope; +float ScreenX; +float ScreenY; +float ScreenZ; +float TopLeftScreenX; +float TopLeftScreenY; +float TopLeftScreenZ; +float BottomRightScreenX; +float BottomRightScreenY; +float BottomRightScreenZ; +float Ready; +float RasterLX; +float RasterLY; +float RasterLZ; +float ScreenLX1; +float ScreenLY1; +float ScreenLZ1; +int ReversedLES; +short Op02LESb; +float NAzsB,NAasB; +float ViewerXc; +float ViewerYc; +float ViewerZc; +float CenterX,CenterY; +short Op02CYSup,Op02CXSup; +float CXdistance; + +#define VofAngle 0x3880 + +short TValDebug,TValDebug2; +short ScrDispl; + + +#ifdef __OPT02__ +void DSPOp02() +{ + ViewerZ1=-Cos(Angle(Op02AZS)); + ViewerX1=Sin(Angle(Op02AZS))*Sin(Angle(Op02AAS)); + ViewerY1=Sin(Angle(Op02AZS))*Cos(Angle(Op02AAS)); + + + #ifdef debug02 + printf("\nViewerX1 : %f ViewerY1 : %f ViewerZ1 : %f\n",ViewerX1,ViewerY1, + ViewerZ1); + getch(); + #endif + ViewerX=Op02FX-ViewerX1*Op02LFE; + ViewerY=Op02FY-ViewerY1*Op02LFE; + ViewerZ=Op02FZ-ViewerZ1*Op02LFE; + + ScreenX=Op02FX+ViewerX1*(Op02LES-Op02LFE); + ScreenY=Op02FY+ViewerY1*(Op02LES-Op02LFE); + ScreenZ=Op02FZ+ViewerZ1*(Op02LES-Op02LFE); + + #ifdef debug02 + printf("ViewerX : %f ViewerY : %f ViewerZ : %f\n",ViewerX,ViewerY,ViewerZ); + printf("Op02FX : %d Op02FY : %d Op02FZ : %d\n",Op02FX,Op02FY,Op02FZ); + printf("ScreenX : %f ScreenY : %f ScreenZ : %f\n",ScreenX,ScreenY,ScreenZ); + getch(); + #endif + if (ViewerZ1==0)ViewerZ1++; + NumberOfSlope=ViewerZ/-ViewerZ1; + + Op02CX=(short)(Op02CXF=ViewerX+ViewerX1*NumberOfSlope); + Op02CY=(short)(Op02CYF=ViewerY+ViewerY1*NumberOfSlope); + + Op02VOF=0x0000; + ReversedLES=0; + Op02LESb=Op02LES; + if ((Op02LES>=VofAngle+16384.0) && (Op02LES=VofAngle) && (Op02LESb<=VofAngle+0x4000)) { + Op02VOF= (short)(Op02LESb * tanf((Op02AZS-0x4000-VofAngle)*6.2832/65536.0)); + Op02VVA-=Op02VOF; + } + if (ReversedLES){ + Op02VOF=-Op02VOF; + } + + NAzsB = (Op02AZS-0x4000)*6.2832/65536.0; + NAasB = Op02AAS*6.2832/65536.0; + + if (tanf(NAzsB)==0) NAzsB=0.1; + + ScrDispl=0; + if (NAzsB>-0.15) {NAzsB=-0.15;ScrDispl=Op02VVA-0xFFDA;} + + CXdistance=1/tanf(NAzsB); + + ViewerXc=Op02FX; + ViewerYc=Op02FY; + ViewerZc=Op02FZ; + + CenterX = (-sinf(NAasB)*ViewerZc*CXdistance)+ViewerXc; + CenterY = (cosf(NAasB)*ViewerZc*CXdistance)+ViewerYc; + Op02CX = (short)CenterX; + Op02CY = (short)CenterY; + + ViewerXc=ViewerX;//-Op02FX); + ViewerYc=ViewerY;//-Op02FY); + ViewerZc=ViewerZ;//-Op02FZ); + + CenterX = (-sinf(NAasB)*ViewerZc*CXdistance)+ViewerXc; + if (CenterX<-32768) CenterX = -32768; if (CenterX>32767) CenterX=32767; + CenterY = (cosf(NAasB)*ViewerZc*CXdistance)+ViewerYc; + if (CenterY<-32768) CenterY = -32768; if (CenterY>32767) CenterY=32767; + + TValDebug = (short)((NAzsB*65536/6.28)); + TValDebug2 = ScrDispl; + +// if (Op02CY < 0) {Op02CYSup = Op02CY/256; Op02CY = 0;} +// if (Op02CX < 0) {Op02CXSup = Op02CX/256; Op02CX = 0;} + +// [4/15/2001] (ViewerX+ViewerX1*NumberOfSlope); +// [4/15/2001] (ViewerY+ViewerY1*NumberOfSlope); + +// if(Op02LFE==0x2200)Op02VVA=0xFECD; +// else Op02VVA=0xFFB2; + + + #ifdef DebugDSP1 + Log_Message("OP02 FX:%d FY:%d FZ:%d LFE:%d LES:%d",Op02FX,Op02FY,Op02FZ,Op02LFE,Op02LES); + Log_Message(" AAS:%d AZS:%d VOF:%d VVA:%d",Op02AAS,Op02AZS,Op02VOF,Op02VVA); + Log_Message(" VX:%d VY:%d VZ:%d",(short)ViewerX,(short)ViewerY,(short)ViewerZ); + #endif + +} +#else + +void DSPOp02() +{ + ViewerZ1=-cosf(Op02AZS*6.2832/65536.0); + ViewerX1=sinf(Op02AZS*6.2832/65536.0)*sinf(Op02AAS*6.2832/65536.0); + ViewerY1=sinf(Op02AZS*6.2832/65536.0)*cosf(-Op02AAS*6.2832/65536.0); + + #ifdef debug02 + printf("\nViewerX1 : %f ViewerY1 : %f ViewerZ1 : %f\n",ViewerX1,ViewerY1, + ViewerZ1); + getch(); + #endif + ViewerX=Op02FX-ViewerX1*Op02LFE; + ViewerY=Op02FY-ViewerY1*Op02LFE; + ViewerZ=Op02FZ-ViewerZ1*Op02LFE; + + ScreenX=Op02FX+ViewerX1*(Op02LES-Op02LFE); + ScreenY=Op02FY+ViewerY1*(Op02LES-Op02LFE); + ScreenZ=Op02FZ+ViewerZ1*(Op02LES-Op02LFE); + + #ifdef debug02 + printf("ViewerX : %f ViewerY : %f ViewerZ : %f\n",ViewerX,ViewerY,ViewerZ); + printf("Op02FX : %d Op02FY : %d Op02FZ : %d\n",Op02FX,Op02FY,Op02FZ); + printf("ScreenX : %f ScreenY : %f ScreenZ : %f\n",ScreenX,ScreenY,ScreenZ); + getch(); + #endif + if (ViewerZ1==0)ViewerZ1++; + NumberOfSlope=ViewerZ/-ViewerZ1; + + Op02CX=(short)(Op02CXF=ViewerX+ViewerX1*NumberOfSlope); + Op02CY=(short)(Op02CYF=ViewerY+ViewerY1*NumberOfSlope); + + ViewerXc=ViewerX;//-Op02FX); + ViewerYc=ViewerY;//-Op02FY); + ViewerZc=ViewerZ;//-Op02FZ); + + Op02VOF=0x0000; + ReversedLES=0; + Op02LESb=Op02LES; + if ((Op02LES>=VofAngle+16384.0) && (Op02LES=VofAngle) && (Op02LESb<=VofAngle+0x4000)) { + Op02VOF= (short)(Op02LESb * tanf((Op02AZS-0x4000-VofAngle)*6.2832/65536.0)); + Op02VVA-=Op02VOF; + } + if (ReversedLES){ + Op02VOF=-Op02VOF; + } + + NAzsB = (Op02AZS-0x4000)*6.2832/65536.0; + NAasB = Op02AAS*6.2832/65536.0; + + if (tanf(NAzsB)==0) NAzsB=0.1; + + ScrDispl=0; + if (NAzsB>-0.15) {NAzsB=-0.15;ScrDispl=Op02VVA-0xFFDA;} + + CXdistance=1/tanf(NAzsB); + + CenterX = (-sinf(NAasB)*ViewerZc*CXdistance)+ViewerXc; + if (CenterX<-32768) CenterX = -32768; if (CenterX>32767) CenterX=32767; + Op02CX = (short)CenterX; + CenterY = (cosf(NAasB)*ViewerZc*CXdistance)+ViewerYc; + if (CenterY<-32768) CenterY = -32768; if (CenterY>32767) CenterY=32767; + Op02CY = (short)CenterY; + + TValDebug = (NAzsB*65536/6.28); + TValDebug2 = ScrDispl; + +// if (Op02CY < 0) {Op02CYSup = Op02CY/256; Op02CY = 0;} +// if (Op02CX < 0) {Op02CXSup = Op02CX/256; Op02CX = 0;} + +// [4/15/2001] (ViewerX+ViewerX1*NumberOfSlope); +// [4/15/2001] (ViewerY+ViewerY1*NumberOfSlope); + +// if(Op02LFE==0x2200)Op02VVA=0xFECD; +// else Op02VVA=0xFFB2; + + + #ifdef DebugDSP1 + Log_Message("OP02 FX:%d FY:%d FZ:%d LFE:%d LES:%d",Op02FX,Op02FY,Op02FZ,Op02LFE,Op02LES); + Log_Message(" AAS:%d AZS:%d VOF:%d VVA:%d",Op02AAS,Op02AZS,Op02VOF,Op02VVA); + Log_Message(" VX:%d VY:%d VZ:%d",(short)ViewerX,(short)ViewerY,(short)ViewerZ); + #endif + +} +#endif + +short Op0AVS; +short Op0AA; +short Op0AB; +short Op0AC; +short Op0AD; + +float RasterRX; +float RasterRY; +float RasterRZ; +float RasterLSlopeX; +float RasterLSlopeY; +float RasterLSlopeZ; +float RasterRSlopeX; +float RasterRSlopeY; +float RasterRSlopeZ; +float GroundLX; +float GroundLY; +float GroundRX; +float GroundRY; +float Distance; + +float NAzs,NAas; +float RVPos,RHPos,RXRes,RYRes; + + +void GetRXYPos(){ + float scalar; + + if (Op02LES==0) return; + + + NAzs = NAzsB - Atan((RVPos) / (float)Op02LES); + NAas = NAasB;// + Atan(RHPos) / (float)Op02LES); + + if (cosf(NAzs)==0) NAzs+=0.001; + if (tanf(NAzs)==0) NAzs+=0.001; + + RXRes = (-sinf(NAas)*ViewerZc/(tanf(NAzs))+ViewerXc); + RYRes = (cosf(NAas)*ViewerZc/(tanf(NAzs))+ViewerYc); + scalar = ((ViewerZc/sinf(NAzs))/(float)Op02LES); + RXRes += scalar*-sinf(NAas+PI/2)*RHPos; + RYRes += scalar*cosf(NAas+PI/2)*RHPos; +} + +void DSPOp0A() +{ + float x2,y2,x3,y3,x4,y4,m,ypos; + + + if(Op0AVS==0) {Op0AVS++; return;} + ypos=Op0AVS-ScrDispl; + // CenterX,CenterX = Center (x1,y1) + // Get (0,Vs) coords (x2,y2) + RVPos = ypos; RHPos = 0; + GetRXYPos(); x2 = RXRes; y2 = RYRes; + // Get (-128,Vs) coords (x3,y3) + RVPos = ypos; RHPos = -128; + GetRXYPos(); x3 = RXRes; y3 = RYRes; + // Get (127,Vs) coords (x4,y4) + RVPos = ypos; RHPos = 127; + GetRXYPos(); x4 = RXRes; y4 = RYRes; + + // A = (x4-x3)/256 + m = (x4-x3)/256*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AA = (short)(m); + // C = (y4-y3)/256 + m = (y4-y3)/256*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AC = (short)(m); + if (ypos==0){ + Op0AB = 0; + Op0AD = 0; + } + else { + // B = (x2-x1)/Vs + m = (x2-CenterX)/ypos*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AB = (short)(m); + // D = (y2-y1)/Vs + m = (y2-CenterY)/ypos*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AD = (short)(m); + } + + Op0AVS+=1; +} + +short Op06X; +short Op06Y; +short Op06Z; +short Op06H; +short Op06V; +unsigned short Op06S; + +/*float ObjPX; +float ObjPY; +float ObjPZ; +float ObjPX1; +float ObjPY1; +float ObjPZ1; +float ObjPX2; +float ObjPY2; +float ObjPZ2;*/ +int32 ObjPX; +int32 ObjPY; +int32 ObjPZ; +int32 ObjPX1; +int32 ObjPY1; +int32 ObjPZ1; +int32 ObjPX2; +int32 ObjPY2; +int32 ObjPZ2; + +float DivideOp06; +int Temp; +int tanval2; + +#define SADDMULT1616(res,a,b,c,d) res=((int64)a*(int64)b+(int64)c*(int64)d)>>16; + +#ifdef __OPT06__ +void DSPOp06() +{ + + ObjPX=Op06X-Op02FX; + ObjPY=Op06Y-Op02FY; + ObjPZ=Op06Z-Op02FZ; + + // rotate around Z +/* tanval2 = Angle(-Op02AAS+32768); +// tanval2 = (-Op02AAS+32768)/(65536/INCR); + ObjPX1=(ObjPX*Cos(tanval2)+ObjPY*-Sin(tanval2)); + ObjPY1=(ObjPX*Sin(tanval2)+ObjPY*Cos(tanval2)); + ObjPZ1=ObjPZ;*/ + tanval2 = AngleFix(-Op02AAS+32768); + SADDMULT1616(ObjPX1,ObjPX,CosFix(tanval2),ObjPY,-SinFix(tanval2)) + SADDMULT1616(ObjPY1,ObjPX,SinFix(tanval2),ObjPY,CosFix(tanval2)) + ObjPZ1=ObjPZ; + + + // rotate around X +// tanval2 = (-Op02AZS/(65536/INCR)) & 1023; +/* tanval2 = Angle(-Op02AZS); +// tanval2 = (-Op02AZS)/256; + ObjPX2=ObjPX1; + ObjPY2=(ObjPY1*Cos(tanval2)+ObjPZ1*-Sin(tanval2)); + ObjPZ2=(ObjPY1*Sin(tanval2)+ObjPZ1*Cos(tanval2));*/ + tanval2 = AngleFix(-Op02AZS); + ObjPX2=ObjPX1; + SADDMULT1616(ObjPY2,ObjPY1,CosFix(tanval2),ObjPZ1,-SinFix(tanval2)) + SADDMULT1616(ObjPZ2,ObjPY1,SinFix(tanval2),ObjPZ1,CosFix(tanval2)) + + #ifdef debug06 + Log_Message("ObjPX2: %f ObjPY2: %f ObjPZ2: %f\n",ObjPX2,ObjPY2,ObjPZ2); + #endif + + ObjPZ2=ObjPZ2-Op02LFE; + + if (ObjPZ2<0) + { + //float d; + int32 d; + Op06H=(short)(-ObjPX2*Op02LES/-(ObjPZ2)); //-ObjPX2*256/-ObjPZ2; + Op06V=(short)(-ObjPY2*Op02LES/-(ObjPZ2)); //-ObjPY2*256/-ObjPZ2; + /*d=(float)Op02LES; + d*=256.0; + d/=(-ObjPZ2); + if(d>65535.0) + d=65535.0; + else if(d<0.0) + d=0.0;*/ + d=(((int32)Op02LES)<<8)/(-ObjPZ2); + if (d>65535) d=65535; + if (d<0) d=0; + Op06S=(unsigned short)d; + //Op06S=(unsigned short)(256*(float)Op02LES/-ObjPZ2); + //Op06S=(unsigned short)((float)(256.0*((float)Op02LES)/(-ObjPZ2))); + } + else + { + Op06H=0; + Op06V=14*16; + Op06S=0xFFFF; + } + + + #ifdef DebugDSP1 + Log_Message("OP06 X:%d Y:%d Z:%d",Op06X,Op06Y,Op06Z); + Log_Message("OP06 H:%d V:%d S:%d",Op06H,Op06V,Op06S); + #endif +} +#else + +void DSPOp06() +{ + ObjPX=Op06X-Op02FX; + ObjPY=Op06Y-Op02FY; + ObjPZ=Op06Z-Op02FZ; + + // rotate around Z + tanval = (-Op02AAS+32768)/65536.0*6.2832; + ObjPX1=(ObjPX*cosf(tanval)+ObjPY*-sinf(tanval)); + ObjPY1=(ObjPX*sinf(tanval)+ObjPY*cosf(tanval)); + ObjPZ1=ObjPZ; + + #ifdef debug06 + Log_Message("Angle : %f", tanval); + Log_Message("ObjPX1: %f ObjPY1: %f ObjPZ1: %f\n",ObjPX1,ObjPY1,ObjPZ1); + Log_Message("cos(tanval) : %f sin(tanval) : %f", cosf(tanval), sinf(tanval)); + #endif + + // rotate around X + tanval = (-Op02AZS)/65536.0*6.2832; + ObjPX2=ObjPX1; + ObjPY2=(ObjPY1*cosf(tanval)+ObjPZ1*-sinf(tanval)); + ObjPZ2=(ObjPY1*sinf(tanval)+ObjPZ1*cosf(tanval)); + + #ifdef debug06 + Log_Message("ObjPX2: %f ObjPY2: %f ObjPZ2: %f\n",ObjPX2,ObjPY2,ObjPZ2); + #endif + + ObjPZ2=ObjPZ2-Op02LFE; + + if (ObjPZ2<0) + { + Op06H=(short)(-ObjPX2*Op02LES/-(ObjPZ2)); //-ObjPX2*256/-ObjPZ2; + Op06V=(short)(-ObjPY2*Op02LES/-(ObjPZ2)); //-ObjPY2*256/-ObjPZ2; + float d=(float)Op02LES; + d*=256.0; + d/=(-ObjPZ2); + if(d>65535.0) + d=65535.0; + else if(d<0.0) + d=0.0; + Op06S=(unsigned short)d; +// Op06S=(unsigned short)(256*(float)Op02LES/-ObjPZ2); + } + else + { + Op06H=0; + Op06V=14*16; + Op06S=0xFFFF; + } + + #ifdef DebugDSP1 + Log_Message("OP06 X:%d Y:%d Z:%d",Op06X,Op06Y,Op06Z); + Log_Message("OP06 H:%d V:%d S:%d",Op06H,Op06V,Op06S); + #endif +} +#endif + + +short matrixC[3][3]; +short matrixB[3][3]; +short matrixA[3][3]; + +short Op01m; +short Op01Zr; +short Op01Xr; +short Op01Yr; +short Op11m; +short Op11Zr; +short Op11Xr; +short Op11Yr; +short Op21m; +short Op21Zr; +short Op21Xr; +short Op21Yr; + +void DSPOp01() +{ + short SinAz = DSP1_Sin(Op01Zr); + short CosAz = DSP1_Cos(Op01Zr); + short SinAy = DSP1_Sin(Op01Yr); + short CosAy = DSP1_Cos(Op01Yr); + short SinAx = DSP1_Sin(Op01Xr); + short CosAx = DSP1_Cos(Op01Xr); + + Op01m >>= 1; + + matrixA[0][0] = (Op01m * CosAz >> 15) * CosAy >> 15; + matrixA[0][1] = -((Op01m * SinAz >> 15) * CosAy >> 15); + matrixA[0][2] = Op01m * SinAy >> 15; + + matrixA[1][0] = ((Op01m * SinAz >> 15) * CosAx >> 15) + (((Op01m * CosAz >> 15) * SinAx >> 15) * SinAy >> 15); + matrixA[1][1] = ((Op01m * CosAz >> 15) * CosAx >> 15) - (((Op01m * SinAz >> 15) * SinAx >> 15) * SinAy >> 15); + matrixA[1][2] = -((Op01m * SinAx >> 15) * CosAy >> 15); + + matrixA[2][0] = ((Op01m * SinAz >> 15) * SinAx >> 15) - (((Op01m * CosAz >> 15) * CosAx >> 15) * SinAy >> 15); + matrixA[2][1] = ((Op01m * CosAz >> 15) * SinAx >> 15) + (((Op01m * SinAz >> 15) * CosAx >> 15) * SinAy >> 15); + matrixA[2][2] = (Op01m * CosAx >> 15) * CosAy >> 15; +} + +void DSPOp11() +{ + short SinAz = DSP1_Sin(Op11Zr); + short CosAz = DSP1_Cos(Op11Zr); + short SinAy = DSP1_Sin(Op11Yr); + short CosAy = DSP1_Cos(Op11Yr); + short SinAx = DSP1_Sin(Op11Xr); + short CosAx = DSP1_Cos(Op11Xr); + + Op11m >>= 1; + + matrixB[0][0] = (Op11m * CosAz >> 15) * CosAy >> 15; + matrixB[0][1] = -((Op11m * SinAz >> 15) * CosAy >> 15); + matrixB[0][2] = Op11m * SinAy >> 15; + + matrixB[1][0] = ((Op11m * SinAz >> 15) * CosAx >> 15) + (((Op11m * CosAz >> 15) * SinAx >> 15) * SinAy >> 15); + matrixB[1][1] = ((Op11m * CosAz >> 15) * CosAx >> 15) - (((Op11m * SinAz >> 15) * SinAx >> 15) * SinAy >> 15); + matrixB[1][2] = -((Op11m * SinAx >> 15) * CosAy >> 15); + + matrixB[2][0] = ((Op11m * SinAz >> 15) * SinAx >> 15) - (((Op11m * CosAz >> 15) * CosAx >> 15) * SinAy >> 15); + matrixB[2][1] = ((Op11m * CosAz >> 15) * SinAx >> 15) + (((Op11m * SinAz >> 15) * CosAx >> 15) * SinAy >> 15); + matrixB[2][2] = (Op11m * CosAx >> 15) * CosAy >> 15; +} + +void DSPOp21() +{ + short SinAz = DSP1_Sin(Op21Zr); + short CosAz = DSP1_Cos(Op21Zr); + short SinAy = DSP1_Sin(Op21Yr); + short CosAy = DSP1_Cos(Op21Yr); + short SinAx = DSP1_Sin(Op21Xr); + short CosAx = DSP1_Cos(Op21Xr); + + Op21m >>= 1; + + matrixC[0][0] = (Op21m * CosAz >> 15) * CosAy >> 15; + matrixC[0][1] = -((Op21m * SinAz >> 15) * CosAy >> 15); + matrixC[0][2] = Op21m * SinAy >> 15; + + matrixC[1][0] = ((Op21m * SinAz >> 15) * CosAx >> 15) + (((Op21m * CosAz >> 15) * SinAx >> 15) * SinAy >> 15); + matrixC[1][1] = ((Op21m * CosAz >> 15) * CosAx >> 15) - (((Op21m * SinAz >> 15) * SinAx >> 15) * SinAy >> 15); + matrixC[1][2] = -((Op21m * SinAx >> 15) * CosAy >> 15); + + matrixC[2][0] = ((Op21m * SinAz >> 15) * SinAx >> 15) - (((Op21m * CosAz >> 15) * CosAx >> 15) * SinAy >> 15); + matrixC[2][1] = ((Op21m * CosAz >> 15) * SinAx >> 15) + (((Op21m * SinAz >> 15) * CosAx >> 15) * SinAy >> 15); + matrixC[2][2] = (Op21m * CosAx >> 15) * CosAy >> 15; +} + +short Op0DX; +short Op0DY; +short Op0DZ; +short Op0DF; +short Op0DL; +short Op0DU; +short Op1DX; +short Op1DY; +short Op1DZ; +short Op1DF; +short Op1DL; +short Op1DU; +short Op2DX; +short Op2DY; +short Op2DZ; +short Op2DF; +short Op2DL; +short Op2DU; + +void DSPOp0D() +{ + Op0DF = (Op0DX * matrixA[0][0] >> 15) + (Op0DY * matrixA[0][1] >> 15) + (Op0DZ * matrixA[0][2] >> 15); + Op0DL = (Op0DX * matrixA[1][0] >> 15) + (Op0DY * matrixA[1][1] >> 15) + (Op0DZ * matrixA[1][2] >> 15); + Op0DU = (Op0DX * matrixA[2][0] >> 15) + (Op0DY * matrixA[2][1] >> 15) + (Op0DZ * matrixA[2][2] >> 15); + + #ifdef DebugDSP1 + Log_Message("OP0D X: %d Y: %d Z: %d / F: %d L: %d U: %d",Op0DX,Op0DY,Op0DZ,Op0DF,Op0DL,Op0DU); + #endif +} + +void DSPOp1D() +{ + Op1DF = (Op1DX * matrixB[0][0] >> 15) + (Op1DY * matrixB[0][1] >> 15) + (Op1DZ * matrixB[0][2] >> 15); + Op1DL = (Op1DX * matrixB[1][0] >> 15) + (Op1DY * matrixB[1][1] >> 15) + (Op1DZ * matrixB[1][2] >> 15); + Op1DU = (Op1DX * matrixB[2][0] >> 15) + (Op1DY * matrixB[2][1] >> 15) + (Op1DZ * matrixB[2][2] >> 15); + + #ifdef DebugDSP1 + Log_Message("OP1D X: %d Y: %d Z: %d / F: %d L: %d U: %d",Op1DX,Op1DY,Op1DZ,Op1DF,Op1DL,Op1DU); + #endif +} + +void DSPOp2D() +{ + Op2DF = (Op2DX * matrixC[0][0] >> 15) + (Op2DY * matrixC[0][1] >> 15) + (Op2DZ * matrixC[0][2] >> 15); + Op2DL = (Op2DX * matrixC[1][0] >> 15) + (Op2DY * matrixC[1][1] >> 15) + (Op2DZ * matrixC[1][2] >> 15); + Op2DU = (Op2DX * matrixC[2][0] >> 15) + (Op2DY * matrixC[2][1] >> 15) + (Op2DZ * matrixC[2][2] >> 15); + + #ifdef DebugDSP1 + Log_Message("OP2D X: %d Y: %d Z: %d / F: %d L: %d U: %d",Op2DX,Op2DY,Op2DZ,Op2DF,Op2DL,Op2DU); + #endif +} + +short Op03F; +short Op03L; +short Op03U; +short Op03X; +short Op03Y; +short Op03Z; +short Op13F; +short Op13L; +short Op13U; +short Op13X; +short Op13Y; +short Op13Z; +short Op23F; +short Op23L; +short Op23U; +short Op23X; +short Op23Y; +short Op23Z; + +void DSPOp03() +{ + Op03X = (Op03F * matrixA[0][0] >> 15) + (Op03L * matrixA[1][0] >> 15) + (Op03U * matrixA[2][0] >> 15); + Op03Y = (Op03F * matrixA[0][1] >> 15) + (Op03L * matrixA[1][1] >> 15) + (Op03U * matrixA[2][1] >> 15); + Op03Z = (Op03F * matrixA[0][2] >> 15) + (Op03L * matrixA[1][2] >> 15) + (Op03U * matrixA[2][2] >> 15); + + #ifdef DebugDSP1 + Log_Message("OP03 F: %d L: %d U: %d / X: %d Y: %d Z: %d",Op03F,Op03L,Op03U,Op03X,Op03Y,Op03Z); + #endif +} + +void DSPOp13() +{ + Op13X = (Op13F * matrixB[0][0] >> 15) + (Op13L * matrixB[1][0] >> 15) + (Op13U * matrixB[2][0] >> 15); + Op13Y = (Op13F * matrixB[0][1] >> 15) + (Op13L * matrixB[1][1] >> 15) + (Op13U * matrixB[2][1] >> 15); + Op13Z = (Op13F * matrixB[0][2] >> 15) + (Op13L * matrixB[1][2] >> 15) + (Op13U * matrixB[2][2] >> 15); + + #ifdef DebugDSP1 + Log_Message("OP13 F: %d L: %d U: %d / X: %d Y: %d Z: %d",Op13F,Op13L,Op13U,Op13X,Op13Y,Op13Z); + #endif +} + +void DSPOp23() +{ + Op23X = (Op23F * matrixC[0][0] >> 15) + (Op23L * matrixC[1][0] >> 15) + (Op23U * matrixC[2][0] >> 15); + Op23Y = (Op23F * matrixC[0][1] >> 15) + (Op23L * matrixC[1][1] >> 15) + (Op23U * matrixC[2][1] >> 15); + Op23Z = (Op23F * matrixC[0][2] >> 15) + (Op23L * matrixC[1][2] >> 15) + (Op23U * matrixC[2][2] >> 15); + + #ifdef DebugDSP1 + Log_Message("OP23 F: %d L: %d U: %d / X: %d Y: %d Z: %d",Op23F,Op23L,Op23U,Op23X,Op23Y,Op23Z); + #endif +} + +short Op14Zr; +short Op14Xr; +short Op14Yr; +short Op14U; +short Op14F; +short Op14L; +short Op14Zrr; +short Op14Xrr; +short Op14Yrr; + +void DSPOp14() +{ + short CSec, ESec, CTan, CSin, C, E; + + DSP1_Inverse(DSP1_Cos(Op14Xr), 0, &CSec, &ESec); + + // Rotation Around Z + DSP1_Normalizefloat(Op14U * DSP1_Cos(Op14Yr) - Op14F * DSP1_Sin(Op14Yr), &C, &E); + + E = ESec - E; + + DSP1_Normalize(C * CSec >> 15, &C, &E); + + if (E > 0) { + if (C > 0) C = 32767; else if (C < 0) C = -32767; + } else { + if (E < 0) C = C * DSP1ROM[(0x31 + E)&1023] >> 15; + } + + Op14Zrr = Op14Zr + C; + + // Rotation Around X + Op14Xrr = Op14Xr + (Op14U * DSP1_Sin(Op14Yr) >> 15) + (Op14F * DSP1_Cos(Op14Yr) >> 15); + + // Rotation Around Y + DSP1_Normalizefloat(Op14U * DSP1_Cos(Op14Yr) + Op14F * DSP1_Sin(Op14Yr), &C, &E); + + E = ESec - E; + + DSP1_Normalize(DSP1_Sin(Op14Xr), &CSin, &E); + + CTan = CSec * CSin >> 15; + + DSP1_Normalize(-(C * CTan >> 15), &C, &E); + + if (E > 0) { + if (C > 0) C = 32767; else if (C < 0) C = -32767; + } else { + if (E < 0) C = C * DSP1ROM[(0x31 + E)&1023] >> 15; + } + + Op14Yrr = Op14Yr + C + Op14L; +} + +short Op0EH; +short Op0EV; +short Op0EX; +short Op0EY; + +void DSPOp0E() +{ + // screen Directions UP + RVPos = Op0EV; + RHPos = Op0EH; + GetRXYPos(); + Op0EX = (short)(RXRes); + Op0EY = (short)(RYRes); + + #ifdef DebugDSP1 + Log_Message("OP0E COORDINATE H:%d V:%d X:%d Y:%d",Op0EH,Op0EV,Op0EX,Op0EY); + #endif +} + +short Op0BX; +short Op0BY; +short Op0BZ; +short Op0BS; +short Op1BX; +short Op1BY; +short Op1BZ; +short Op1BS; +short Op2BX; +short Op2BY; +short Op2BZ; +short Op2BS; + +void DSPOp0B() +{ + Op0BS = (Op0BX * matrixA[0][0] + Op0BY * matrixA[0][1] + Op0BZ * matrixA[0][2]) >> 15; + + #ifdef DebugDSP1 + Log_Message("OP0B"); + #endif +} + +void DSPOp1B() +{ + Op1BS = (Op1BX * matrixB[0][0] + Op1BY * matrixB[0][1] + Op1BZ * matrixB[0][2]) >> 15; + + #ifdef DebugDSP1 + Log_Message("OP1B X: %d Y: %d Z: %d S: %d",Op1BX,Op1BY,Op1BZ,Op1BS); + Log_Message(" MX: %d MY: %d MZ: %d Scale: %d",(short)(matrixB[0][0]*100),(short)(matrixB[0][1]*100),(short)(matrixB[0][2]*100),(short)(sc2*100)); + #endif +} + +void DSPOp2B() +{ + Op2BS = (Op2BX * matrixC[0][0] + Op2BY * matrixC[0][1] + Op2BZ * matrixC[0][2]) >> 15; + + #ifdef DebugDSP1 + Log_Message("OP2B"); + #endif +} + +short Op08X,Op08Y,Op08Z,Op08Ll,Op08Lh; + +void DSPOp08() +{ + int Op08Size = (Op08X * Op08X + Op08Y * Op08Y + Op08Z * Op08Z) << 1; + Op08Ll = Op08Size & 0xffff; + Op08Lh = (Op08Size >> 16) & 0xffff; + + #ifdef DebugDSP1 + Log_Message("OP08 %d,%d,%d",Op08X,Op08Y,Op08Z); + Log_Message("OP08 ((Op08X^2)+(Op08Y^2)+(Op08X^2))=%x",Op08Size ); + #endif +} + +short Op18X,Op18Y,Op18Z,Op18R,Op18D; + +void DSPOp18() +{ + Op18D = (Op18X * Op18X + Op18Y * Op18Y + Op18Z * Op18Z - Op18R * Op18R) >> 15; + + #ifdef DebugDSP1 + Log_Message("Op18 X: %d Y: %d Z: %d R: %D DIFF %d",Op18X,Op18Y,Op38Z,Op18D); + #endif +} + +short Op38X,Op38Y,Op38Z,Op38R,Op38D; + +void DSPOp38() +{ + Op38D = (Op38X * Op38X + Op38Y * Op38Y + Op38Z * Op38Z - Op38R * Op38R) >> 15; + Op38D++; + + #ifdef DebugDSP1 + Log_Message("OP38 X: %d Y: %d Z: %d R: %D DIFF %d",Op38X,Op38Y,Op38Z,Op38D); + #endif +} + +short Op28X; +short Op28Y; +short Op28Z; +short Op28R; + +void DSPOp28() +{ + int Radius = Op28X * Op28X + Op28Y * Op28Y + Op28Z * Op28Z; + + if (Radius == 0) Op28R = 0; + else + { + short C, E; + DSP1_Normalizefloat(Radius, &C, &E); + if (E & 1) C = C * 0x4000 >> 15; + + short Pos = C * 0x0040 >> 15; + + short Node1 = DSP1ROM[(0x00d5 + Pos)&1023]; + short Node2 = DSP1ROM[(0x00d6 + Pos)&1023]; + + Op28R = ((Node2 - Node1) * (C & 0x1ff) >> 9) + Node1; + Op28R >>= (E >> 1); + } + + #ifdef DebugDSP1 + Log_Message("OP28 X:%d Y:%d Z:%d",Op28X,Op28Y,Op28Z); + Log_Message("OP28 Vector Length %d",Op28R); + #endif +} + +short Op1CX,Op1CY,Op1CZ; +short Op1CXBR,Op1CYBR,Op1CZBR,Op1CXAR,Op1CYAR,Op1CZAR; +short Op1CX1; +short Op1CY1; +short Op1CZ1; +short Op1CX2; +short Op1CY2; +short Op1CZ2; + +void DSPOp1C() +{ + + // Rotate Around Op1CZ1 + Op1CX1 = (Op1CYBR * DSP1_Sin(Op1CZ) >> 15) + (Op1CXBR * DSP1_Cos(Op1CZ) >> 15); + Op1CY1 = (Op1CYBR * DSP1_Cos(Op1CZ) >> 15) - (Op1CXBR * DSP1_Sin(Op1CZ) >> 15); + Op1CXBR = Op1CX1; Op1CYBR = Op1CY1; + + // Rotate Around Op1CY1 + Op1CZ1 = (Op1CXBR * DSP1_Sin(Op1CY) >> 15) + (Op1CZBR * DSP1_Cos(Op1CY) >> 15); + Op1CX1 = (Op1CXBR * DSP1_Cos(Op1CY) >> 15) - (Op1CZBR * DSP1_Sin(Op1CY) >> 15); + Op1CXAR = Op1CX1; Op1CZBR = Op1CZ1; + + // Rotate Around Op1CX1 + Op1CY1 = (Op1CZBR * DSP1_Sin(Op1CX) >> 15) + (Op1CYBR * DSP1_Cos(Op1CX) >> 15); + Op1CZ1 = (Op1CZBR * DSP1_Cos(Op1CX) >> 15) - (Op1CYBR * DSP1_Sin(Op1CX) >> 15); + Op1CYAR = Op1CY1; Op1CZAR = Op1CZ1; + + #ifdef DebugDSP1 + Log_Message("OP1C Apply Matrix CX:%d CY:%d CZ",Op1CXAR,Op1CYAR,Op1CZAR); + #endif +} + +unsigned short Op0FRamsize; +unsigned short Op0FPass; + +void DSPOp0F() +{ + Op0FPass = 0x0000; + + #ifdef DebugDSP1 + Log_Message("OP0F RAM Test Pass:%d", Op0FPass); + #endif +} + +short Op2FUnknown; +short Op2FSize; + +void DSPOp2F() +{ + Op2FSize=0x100; +} diff --git a/src/dsp1emu_fixed.c b/src/dsp1emu_fixed.c new file mode 100644 index 0000000..91204a4 --- /dev/null +++ b/src/dsp1emu_fixed.c @@ -0,0 +1,1691 @@ +//Copyright (C) 1997-2001 ZSNES Team ( zsknight@zsnes.com / _demo_@zsnes.com ) +// +//This program is free software; you can redistribute it and/or +//modify it under the terms of the GNU General Public License +//as published by the Free Software Foundation; either +//version 2 of the License, or (at your option) any later +//version. +// +//This program is distributed in the hope that it will be useful, +//but WITHOUT ANY WARRANTY; without even the implied warranty of +//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +//GNU General Public License for more details. +// +//You should have received a copy of the GNU General Public License +//along with this program; if not, write to the Free Software +//Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +#ifndef __GP32__ +#include +#include +#endif +#include + +#ifndef __GP32__ +#include +#include +#endif +//#define DebugDSP1 + +#define funcSADDMULT1616(a,b,c,d) (((int64)a*(int64)b+(int64)c*(int64)d)>>16); + +#define SADDMULT1616(res,a,b,c,d) {\ + res=funcSADDMULT1616(a,b,c,d);\ + } +#define SMULT1616(res,a,b) {\ + res=funcSADDMULT1616(a,b,0,0);\ + } + +// uncomment some lines to test +//#define printinfo +//#define debug02 +//#define debug0A +//#define debug06 + +//#ifdef __GP32__ +//for the SMUL1616 & UMUL1616 +//#include "gp32_func.h" +//#endif + +#define __OPT__ +#define __OPT01__ +#define __OPT02__ +#define __OPT04__ +#define __OPT06__ +#define __OPT0C__ // this optimisation may break pilotwings +#define __OPT11__ +#define __OPT21__ +#define __OPT1C__ + +#ifdef DebugDSP1 + +FILE * LogFile = NULL; + +void Log_Message (char *Message, ...) +{ + char Msg[400]; + va_list ap; + + va_start(ap,Message); + vsprintf(Msg,Message,ap ); + va_end(ap); + + strcat(Msg,"\r\n\0"); + fwrite(Msg,strlen(Msg),1,LogFile); + fflush (LogFile); +} + +void Start_Log (void) +{ + char LogFileName[255]; +// [4/15/2001] char *p; + + strcpy(LogFileName,"dsp1emu.log\0"); + + LogFile = fopen(LogFileName,"wb"); +} + +void Stop_Log (void) +{ + if (LogFile) + { + fclose(LogFile); + LogFile = NULL; + } +} + +#endif + +const unsigned short DSP1ROM[1024] = { + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, + 0x0040, 0x0080, 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, + 0x4000, 0x7fff, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, + 0x0100, 0x0080, 0x0040, 0x0020, 0x0001, 0x0008, 0x0004, 0x0002, + 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x8000, 0xffe5, 0x0100, 0x7fff, 0x7f02, 0x7e08, + 0x7d12, 0x7c1f, 0x7b30, 0x7a45, 0x795d, 0x7878, 0x7797, 0x76ba, + 0x75df, 0x7507, 0x7433, 0x7361, 0x7293, 0x71c7, 0x70fe, 0x7038, + 0x6f75, 0x6eb4, 0x6df6, 0x6d3a, 0x6c81, 0x6bca, 0x6b16, 0x6a64, + 0x69b4, 0x6907, 0x685b, 0x67b2, 0x670b, 0x6666, 0x65c4, 0x6523, + 0x6484, 0x63e7, 0x634c, 0x62b3, 0x621c, 0x6186, 0x60f2, 0x6060, + 0x5fd0, 0x5f41, 0x5eb5, 0x5e29, 0x5d9f, 0x5d17, 0x5c91, 0x5c0c, + 0x5b88, 0x5b06, 0x5a85, 0x5a06, 0x5988, 0x590b, 0x5890, 0x5816, + 0x579d, 0x5726, 0x56b0, 0x563b, 0x55c8, 0x5555, 0x54e4, 0x5474, + 0x5405, 0x5398, 0x532b, 0x52bf, 0x5255, 0x51ec, 0x5183, 0x511c, + 0x50b6, 0x5050, 0x4fec, 0x4f89, 0x4f26, 0x4ec5, 0x4e64, 0x4e05, + 0x4da6, 0x4d48, 0x4cec, 0x4c90, 0x4c34, 0x4bda, 0x4b81, 0x4b28, + 0x4ad0, 0x4a79, 0x4a23, 0x49cd, 0x4979, 0x4925, 0x48d1, 0x487f, + 0x482d, 0x47dc, 0x478c, 0x473c, 0x46ed, 0x469f, 0x4651, 0x4604, + 0x45b8, 0x456c, 0x4521, 0x44d7, 0x448d, 0x4444, 0x43fc, 0x43b4, + 0x436d, 0x4326, 0x42e0, 0x429a, 0x4255, 0x4211, 0x41cd, 0x4189, + 0x4146, 0x4104, 0x40c2, 0x4081, 0x4040, 0x3fff, 0x41f7, 0x43e1, + 0x45bd, 0x478d, 0x4951, 0x4b0b, 0x4cbb, 0x4e61, 0x4fff, 0x5194, + 0x5322, 0x54a9, 0x5628, 0x57a2, 0x5914, 0x5a81, 0x5be9, 0x5d4a, + 0x5ea7, 0x5fff, 0x6152, 0x62a0, 0x63ea, 0x6530, 0x6672, 0x67b0, + 0x68ea, 0x6a20, 0x6b53, 0x6c83, 0x6daf, 0x6ed9, 0x6fff, 0x7122, + 0x7242, 0x735f, 0x747a, 0x7592, 0x76a7, 0x77ba, 0x78cb, 0x79d9, + 0x7ae5, 0x7bee, 0x7cf5, 0x7dfa, 0x7efe, 0x7fff, 0x0000, 0x0324, + 0x0647, 0x096a, 0x0c8b, 0x0fab, 0x12c8, 0x15e2, 0x18f8, 0x1c0b, + 0x1f19, 0x2223, 0x2528, 0x2826, 0x2b1f, 0x2e11, 0x30fb, 0x33de, + 0x36ba, 0x398c, 0x3c56, 0x3f17, 0x41ce, 0x447a, 0x471c, 0x49b4, + 0x4c3f, 0x4ebf, 0x5133, 0x539b, 0x55f5, 0x5842, 0x5a82, 0x5cb4, + 0x5ed7, 0x60ec, 0x62f2, 0x64e8, 0x66cf, 0x68a6, 0x6a6d, 0x6c24, + 0x6dca, 0x6f5f, 0x70e2, 0x7255, 0x73b5, 0x7504, 0x7641, 0x776c, + 0x7884, 0x798a, 0x7a7d, 0x7b5d, 0x7c29, 0x7ce3, 0x7d8a, 0x7e1d, + 0x7e9d, 0x7f09, 0x7f62, 0x7fa7, 0x7fd8, 0x7ff6, 0x7fff, 0x7ff6, + 0x7fd8, 0x7fa7, 0x7f62, 0x7f09, 0x7e9d, 0x7e1d, 0x7d8a, 0x7ce3, + 0x7c29, 0x7b5d, 0x7a7d, 0x798a, 0x7884, 0x776c, 0x7641, 0x7504, + 0x73b5, 0x7255, 0x70e2, 0x6f5f, 0x6dca, 0x6c24, 0x6a6d, 0x68a6, + 0x66cf, 0x64e8, 0x62f2, 0x60ec, 0x5ed7, 0x5cb4, 0x5a82, 0x5842, + 0x55f5, 0x539b, 0x5133, 0x4ebf, 0x4c3f, 0x49b4, 0x471c, 0x447a, + 0x41ce, 0x3f17, 0x3c56, 0x398c, 0x36ba, 0x33de, 0x30fb, 0x2e11, + 0x2b1f, 0x2826, 0x2528, 0x2223, 0x1f19, 0x1c0b, 0x18f8, 0x15e2, + 0x12c8, 0x0fab, 0x0c8b, 0x096a, 0x0647, 0x0324, 0x7fff, 0x7ff6, + 0x7fd8, 0x7fa7, 0x7f62, 0x7f09, 0x7e9d, 0x7e1d, 0x7d8a, 0x7ce3, + 0x7c29, 0x7b5d, 0x7a7d, 0x798a, 0x7884, 0x776c, 0x7641, 0x7504, + 0x73b5, 0x7255, 0x70e2, 0x6f5f, 0x6dca, 0x6c24, 0x6a6d, 0x68a6, + 0x66cf, 0x64e8, 0x62f2, 0x60ec, 0x5ed7, 0x5cb4, 0x5a82, 0x5842, + 0x55f5, 0x539b, 0x5133, 0x4ebf, 0x4c3f, 0x49b4, 0x471c, 0x447a, + 0x41ce, 0x3f17, 0x3c56, 0x398c, 0x36ba, 0x33de, 0x30fb, 0x2e11, + 0x2b1f, 0x2826, 0x2528, 0x2223, 0x1f19, 0x1c0b, 0x18f8, 0x15e2, + 0x12c8, 0x0fab, 0x0c8b, 0x096a, 0x0647, 0x0324, 0x0000, 0xfcdc, + 0xf9b9, 0xf696, 0xf375, 0xf055, 0xed38, 0xea1e, 0xe708, 0xe3f5, + 0xe0e7, 0xdddd, 0xdad8, 0xd7da, 0xd4e1, 0xd1ef, 0xcf05, 0xcc22, + 0xc946, 0xc674, 0xc3aa, 0xc0e9, 0xbe32, 0xbb86, 0xb8e4, 0xb64c, + 0xb3c1, 0xb141, 0xaecd, 0xac65, 0xaa0b, 0xa7be, 0xa57e, 0xa34c, + 0xa129, 0x9f14, 0x9d0e, 0x9b18, 0x9931, 0x975a, 0x9593, 0x93dc, + 0x9236, 0x90a1, 0x8f1e, 0x8dab, 0x8c4b, 0x8afc, 0x89bf, 0x8894, + 0x877c, 0x8676, 0x8583, 0x84a3, 0x83d7, 0x831d, 0x8276, 0x81e3, + 0x8163, 0x80f7, 0x809e, 0x8059, 0x8028, 0x800a, 0x6488, 0x0080, + 0x03ff, 0x0116, 0x0002, 0x0080, 0x4000, 0x3fd7, 0x3faf, 0x3f86, + 0x3f5d, 0x3f34, 0x3f0c, 0x3ee3, 0x3eba, 0x3e91, 0x3e68, 0x3e40, + 0x3e17, 0x3dee, 0x3dc5, 0x3d9c, 0x3d74, 0x3d4b, 0x3d22, 0x3cf9, + 0x3cd0, 0x3ca7, 0x3c7f, 0x3c56, 0x3c2d, 0x3c04, 0x3bdb, 0x3bb2, + 0x3b89, 0x3b60, 0x3b37, 0x3b0e, 0x3ae5, 0x3abc, 0x3a93, 0x3a69, + 0x3a40, 0x3a17, 0x39ee, 0x39c5, 0x399c, 0x3972, 0x3949, 0x3920, + 0x38f6, 0x38cd, 0x38a4, 0x387a, 0x3851, 0x3827, 0x37fe, 0x37d4, + 0x37aa, 0x3781, 0x3757, 0x372d, 0x3704, 0x36da, 0x36b0, 0x3686, + 0x365c, 0x3632, 0x3609, 0x35df, 0x35b4, 0x358a, 0x3560, 0x3536, + 0x350c, 0x34e1, 0x34b7, 0x348d, 0x3462, 0x3438, 0x340d, 0x33e3, + 0x33b8, 0x338d, 0x3363, 0x3338, 0x330d, 0x32e2, 0x32b7, 0x328c, + 0x3261, 0x3236, 0x320b, 0x31df, 0x31b4, 0x3188, 0x315d, 0x3131, + 0x3106, 0x30da, 0x30ae, 0x3083, 0x3057, 0x302b, 0x2fff, 0x2fd2, + 0x2fa6, 0x2f7a, 0x2f4d, 0x2f21, 0x2ef4, 0x2ec8, 0x2e9b, 0x2e6e, + 0x2e41, 0x2e14, 0x2de7, 0x2dba, 0x2d8d, 0x2d60, 0x2d32, 0x2d05, + 0x2cd7, 0x2ca9, 0x2c7b, 0x2c4d, 0x2c1f, 0x2bf1, 0x2bc3, 0x2b94, + 0x2b66, 0x2b37, 0x2b09, 0x2ada, 0x2aab, 0x2a7c, 0x2a4c, 0x2a1d, + 0x29ed, 0x29be, 0x298e, 0x295e, 0x292e, 0x28fe, 0x28ce, 0x289d, + 0x286d, 0x283c, 0x280b, 0x27da, 0x27a9, 0x2777, 0x2746, 0x2714, + 0x26e2, 0x26b0, 0x267e, 0x264c, 0x2619, 0x25e7, 0x25b4, 0x2581, + 0x254d, 0x251a, 0x24e6, 0x24b2, 0x247e, 0x244a, 0x2415, 0x23e1, + 0x23ac, 0x2376, 0x2341, 0x230b, 0x22d6, 0x229f, 0x2269, 0x2232, + 0x21fc, 0x21c4, 0x218d, 0x2155, 0x211d, 0x20e5, 0x20ad, 0x2074, + 0x203b, 0x2001, 0x1fc7, 0x1f8d, 0x1f53, 0x1f18, 0x1edd, 0x1ea1, + 0x1e66, 0x1e29, 0x1ded, 0x1db0, 0x1d72, 0x1d35, 0x1cf6, 0x1cb8, + 0x1c79, 0x1c39, 0x1bf9, 0x1bb8, 0x1b77, 0x1b36, 0x1af4, 0x1ab1, + 0x1a6e, 0x1a2a, 0x19e6, 0x19a1, 0x195c, 0x1915, 0x18ce, 0x1887, + 0x183f, 0x17f5, 0x17ac, 0x1761, 0x1715, 0x16c9, 0x167c, 0x162e, + 0x15df, 0x158e, 0x153d, 0x14eb, 0x1497, 0x1442, 0x13ec, 0x1395, + 0x133c, 0x12e2, 0x1286, 0x1228, 0x11c9, 0x1167, 0x1104, 0x109e, + 0x1036, 0x0fcc, 0x0f5f, 0x0eef, 0x0e7b, 0x0e04, 0x0d89, 0x0d0a, + 0x0c86, 0x0bfd, 0x0b6d, 0x0ad6, 0x0a36, 0x098d, 0x08d7, 0x0811, + 0x0736, 0x063e, 0x0519, 0x039a, 0x0000, 0x7fff, 0x0100, 0x0080, + 0x021d, 0x00c8, 0x00ce, 0x0048, 0x0a26, 0x277a, 0x00ce, 0x6488, + 0x14ac, 0x0001, 0x00f9, 0x00fc, 0x00ff, 0x00fc, 0x00f9, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff}; + + + +/***************************************************************************\ +* Math tables * +\***************************************************************************/ + +#define INCR 2048 //<<11 +#define INCR_SHIFT 5 //16-11 coz (>>INCR_SHIFT) = (*INCR/65536) +#define _FIX_SHIFT_ 16 +//double *CosTable2; +int32 CosTable2[INCR]; +//double *SinTable2; +int32 SinTable2[INCR]; + +//#define Angle(x) (((x)/(65536/INCR)) & (INCR-1)) +#define Angle(x) (((int32)(x)>>INCR_SHIFT) & (INCR-1) ) +//#define Cos(x) ((double) CosTable2[x]) +#define Cos(x) ((int32) CosTable2[x]) +//#define Sin(x) ((double) SinTable2[x]) +#define Sin(x) ((int32) SinTable2[x]) +//#define PI 3.14159265358979323846264338327 +#define PI_float 3.14159265358979323846264338327f +#define PI 205887 //3.14159265358979323846264338327 << _FIX_SHIFT_ + +//double Atan(double x) +int32 Atan(int32 x) +{ +// if ((x>=1) || (x<=1)) //stupid ? + if ((x>=(1<<_FIX_SHIFT_)) || (x<=(1<<_FIX_SHIFT_))) //stupid ? + //return (x/(1+0.28*x*x)); + {int32 t;SMULT1616(t,x,x) + return ( ( (int64)x<<_FIX_SHIFT_ ) /(1+0.28f*t) );} + else + //return ( PI/2 - Atan(1/x)); + return ( PI/2 - Atan( ((int64)1<<(_FIX_SHIFT_*2))/x) ); +} + +/***************************************************************************\ +* DSP1 code * +\***************************************************************************/ + + +void InitDSP(void) +{ +#ifdef __OPT__ + unsigned int i; + //CosTable2 = (double *) malloc(INCR*sizeof(double)); + //CosTable2 = (int32 *) malloc(INCR*sizeof(int32)); + //SinTable2 = (double *) malloc(INCR*sizeof(double)); + //SinTable2 = (int32 *) malloc(INCR*sizeof(int32)); + for (i=0; i>15; + #ifdef DebugDSP1 + Log_Message("OP00 MULT %d*%d/32768=%d",Op00Multiplicand,Op00Multiplier,Op00Result); + #endif +} + +short Op20Multiplicand; +short Op20Multiplier; +short Op20Result; + +void DSPOp20() +{ + Op20Result= Op20Multiplicand * Op20Multiplier >> 15; + Op20Result++; + + #ifdef DebugDSP1 + Log_Message("OP20 MULT %d*%d/32768=%d",Op20Multiplicand,Op20Multiplier,Op20Result); + #endif +} + + +signed short Op10Coefficient; +signed short Op10Exponent; +signed short Op10CoefficientR; +signed short Op10ExponentR; +//float Op10Temp; +int32 Op10Temp; + +void DSPOp10() +{ + Op10ExponentR=-Op10Exponent; + //Op10Temp = Op10Coefficient / 32768.0; + Op10Temp = (Op10Coefficient<<(_FIX_SHIFT_-15)); + if (Op10Temp == 0) { + Op10CoefficientR = 0; + } else + //Op10Temp = 1/Op10Temp; + Op10Temp = ((int64)(1)<<(_FIX_SHIFT_*2)) /Op10Temp ; + if (Op10Temp > 0) + //while (Op10Temp>=1.0) { + while (Op10Temp>=(1<<_FIX_SHIFT_)) { + //Op10Temp=Op10Temp/2.0; + Op10Temp=Op10Temp>>1; + Op10ExponentR++; + } + else + //while (Op10Temp<-1.0) { + while (Op10Temp<-(1<<_FIX_SHIFT_)) { + //Op10Temp=Op10Temp/2.0; + Op10Temp=Op10Temp>>1; + Op10ExponentR++; + } + //Op10CoefficientR = Op10Temp*32768; + Op10CoefficientR = Op10Temp>>(_FIX_SHIFT_-15); + #ifdef DebugDSP1 + Log_Message("OP10 INV %d*2^%d = %d*2^%d", Op10Coefficient, Op10Exponent, Op10CoefficientR, Op10ExponentR); + #endif +} + + +short Op04Angle; +unsigned short Op04Radius; +short Op04Sin; +short Op04Cos; + +#ifdef __OPT04__ + +void DSPOp04() +{ + int angle; + + angle = Angle(Op04Angle); + + //Op04Sin = Sin(angle) * Op04Radius; + //Op04Cos = Cos(angle) * Op04Radius; + SMULT1616(Op04Sin,Sin(angle),Op04Radius) + SMULT1616(Op04Cos,Cos(angle),Op04Radius) + + #ifdef DebugDSP1 + Log_Message("OP04 Angle:%d Radius:%d",(Op04Angle/256)&255,Op04Radius); + Log_Message("OP04 SIN:%d COS:%d",Op04Sin,Op04Cos); + #endif +} +#else + +void DSPOp04() +{ + double angle; + + angle = Op04Angle*2*PI/65536.0; + + Op04Sin = sin(angle) * Op04Radius; + Op04Cos = cos(angle) * Op04Radius; + + #ifdef DebugDSP1 + Log_Message("OP04 Angle:%d Radius:%d",(Op04Angle/256)&255,Op04Radius); + Log_Message("OP04 SIN:%d COS:%d",Op04Sin,Op04Cos); + #endif +} +#endif + +unsigned short Op0CA; +short Op0CX1; +short Op0CY1; +short Op0CX2; +short Op0CY2; + +#ifdef __OPT0C__ +void DSPOp0C() +{ + //Op0CX2=Op0CX1*Cos(Angle(Op0CA))+Op0CY1*Sin(Angle(Op0CA)); + //Op0CY2=Op0CX1*-Sin(Angle(Op0CA))+Op0CY1*Cos(Angle(Op0CA)); + Op0CX2=((int32)Op0CX1*Cos(Angle(Op0CA))+(int32)Op0CY1*Sin(Angle(Op0CA)))>>_FIX_SHIFT_; + Op0CY2=((int32)Op0CX1*-Sin(Angle(Op0CA))+(int32)Op0CY1*Cos(Angle(Op0CA)))>>_FIX_SHIFT_; + + #ifdef DebugDSP1 + Log_Message("OP0C Angle:%d X:%d Y:%d CX:%d CY:%d",(Op0CA/256)&255,Op0CX1,Op0CY1,Op0CX2,Op0CY2); + #endif +} +#else +void DSPOp0C() +{ + + Op0CX2=(Op0CX1*cos(Op0CA*2*PI/65536.0)+Op0CY1*sin(Op0CA*2*PI/65536.0)); + Op0CY2=(Op0CX1*-sin(Op0CA*2*PI/65536.0)+Op0CY1*cos(Op0CA*2*PI/65536.0)); + #ifdef DebugDSP1 + Log_Message("OP0C Angle:%d X:%d Y:%d CX:%d CY:%d",(Op0CA/256)&255,Op0CX1,Op0CY1,Op0CX2,Op0CY2); + #endif +} + +#endif + +short Op02FX; +short Op02FY; +short Op02FZ; +short Op02LFE; +short Op02LES; +unsigned short Op02AAS; +unsigned short Op02AZS; +unsigned short Op02VOF; +unsigned short Op02VVA; + +short Op02CX; +short Op02CY; +/*double Op02CXF; +double Op02CYF; +double ViewerX0; +double ViewerY0; +double ViewerZ0; +double ViewerX1; +double ViewerY1; +double ViewerZ1; +double ViewerX; +double ViewerY; +double ViewerZ;*/ +int32 Op02CXF; +int32 Op02CYF; +int32 ViewerX0; +int32 ViewerY0; +int32 ViewerZ0; +int32 ViewerX1; +int32 ViewerY1; +int32 ViewerZ1; +int32 ViewerX; +int32 ViewerY; +int32 ViewerZ; +int ViewerAX; +int ViewerAY; +int ViewerAZ; +/*double NumberOfSlope; +double ScreenX; +double ScreenY; +double ScreenZ; +double TopLeftScreenX; +double TopLeftScreenY; +double TopLeftScreenZ; +double BottomRightScreenX; +double BottomRightScreenY; +double BottomRightScreenZ; +double Ready; +double RasterLX; +double RasterLY; +double RasterLZ; +double ScreenLX1; +double ScreenLY1; +double ScreenLZ1;*/ +int32 NumberOfSlope; +int32 ScreenX; +int32 ScreenY; +int32 ScreenZ; +int32 TopLeftScreenX; +int32 TopLeftScreenY; +int32 TopLeftScreenZ; +int32 BottomRightScreenX; +int32 BottomRightScreenY; +int32 BottomRightScreenZ; +int32 Ready; +int32 RasterLX; +int32 RasterLY; +int32 RasterLZ; +int32 ScreenLX1; +int32 ScreenLY1; +int32 ScreenLZ1; +int ReversedLES; +short Op02LESb; +/*double NAzsB,NAasB; +double ViewerXc; +double ViewerYc; +double ViewerZc; +double CenterX,CenterY;*/ +int32 NAzsB,NAasB; +int32 ViewerXc; +int32 ViewerYc; +int32 ViewerZc; +int32 CenterX,CenterY; +short Op02CYSup,Op02CXSup; +//double CXdistance; +int32 CXdistance; + +#define VofAngle 0x3880 + +short TValDebug,TValDebug2; +short ScrDispl; + + +#ifdef __OPT02__ +void DSPOp02() +{ + ViewerZ1=-Cos(Angle(Op02AZS)); +/* ViewerX1=Sin(Angle(Op02AZS))*Sin(Angle(Op02AAS)); + ViewerY1=Sin(Angle(Op02AZS))*Cos(Angle(Op02AAS));*/ + SMULT1616(ViewerX1,Sin(Angle(Op02AZS)),Sin(Angle(Op02AAS))) + SMULT1616(ViewerY1,Sin(Angle(Op02AZS)),Cos(Angle(Op02AAS))) + + + #ifdef debug02 + printf("\nViewerX1 : %f ViewerY1 : %f ViewerZ1 : %f\n",ViewerX1,ViewerY1, + ViewerZ1); + getch(); + #endif + /*ViewerX=Op02FX-ViewerX1*Op02LFE; + ViewerY=Op02FY-ViewerY1*Op02LFE; + ViewerZ=Op02FZ-ViewerZ1*Op02LFE; + + ScreenX=Op02FX+ViewerX1*(Op02LES-Op02LFE); + ScreenY=Op02FY+ViewerY1*(Op02LES-Op02LFE); + ScreenZ=Op02FZ+ViewerZ1*(Op02LES-Op02LFE);*/ + ViewerX=((int32)Op02FX<<_FIX_SHIFT_)-ViewerX1*(int32)Op02LFE; + ViewerY=((int32)Op02FY<<_FIX_SHIFT_)-ViewerY1*(int32)Op02LFE; + ViewerZ=((int32)Op02FZ<<_FIX_SHIFT_)-ViewerZ1*(int32)Op02LFE; + + ScreenX=((int32)Op02FX<<_FIX_SHIFT_)+ViewerX1*(int32)(Op02LES-Op02LFE); + ScreenY=((int32)Op02FY<<_FIX_SHIFT_)+ViewerY1*(int32)(Op02LES-Op02LFE); + ScreenZ=((int32)Op02FZ<<_FIX_SHIFT_)+ViewerZ1*(int32)(Op02LES-Op02LFE); + + #ifdef debug02 + printf("ViewerX : %f ViewerY : %f ViewerZ : %f\n",ViewerX,ViewerY,ViewerZ); + printf("Op02FX : %d Op02FY : %d Op02FZ : %d\n",Op02FX,Op02FY,Op02FZ); + printf("ScreenX : %f ScreenY : %f ScreenZ : %f\n",ScreenX,ScreenY,ScreenZ); + getch(); + #endif + if (ViewerZ1==0)ViewerZ1++; + NumberOfSlope=((int64)ViewerZ<<_FIX_SHIFT_)/(-ViewerZ1); + + //Op02CX=(short)(Op02CXF=ViewerX+ViewerX1*NumberOfSlope); + //Op02CY=(short)(Op02CYF=ViewerY+ViewerY1*NumberOfSlope); + int32 t; + SMULT1616(t,ViewerX1,NumberOfSlope) + Op02CX=(short)(Op02CXF=(ViewerX+t)>>_FIX_SHIFT_); + SMULT1616(t,ViewerY1,NumberOfSlope) + Op02CY=(short)(Op02CYF=(ViewerY+t)>>_FIX_SHIFT_); + + Op02VOF=0x0000; + ReversedLES=0; + Op02LESb=Op02LES; + //if ((Op02LES>=VofAngle+16384.0) && (Op02LES=VofAngle+16384) && (Op02LES=VofAngle) && (Op02LESb<=VofAngle+0x4000)) { + Op02VOF= (short)(Op02LESb * tan((Op02AZS-0x4000-VofAngle)*6.2832/65536.0)); + Op02VVA-=Op02VOF; + } + if (ReversedLES){ + Op02VOF=-Op02VOF; + } + + //NAzsB = (Op02AZS-0x4000)*6.2832/65536.0; + NAzsB = (int32)(Op02AZS-0x4000); + //NAasB = Op02AAS*6.2832/65536.0; + NAasB = (int32)(Op02AAS); + + //if (tan(NAzsB)==0) NAzsB=0.1; + if (Sin(Angle(NAzsB))==0) NAzsB=1043; //0.1*65536/(2*pi) + + ScrDispl=0; + //if (NAzsB>-0.15) {NAzsB=-0.15;ScrDispl=Op02VVA-0xFFDA;} + if (NAzsB>-1565 /*0.15*65536/2/pi*/) {NAzsB=-1565;ScrDispl=Op02VVA-0xFFDA;} + + //CXdistance=1/tan(NAzsB); + CXdistance=((int64)Cos(Angle(NAzsB))<<_FIX_SHIFT_)/Sin(Angle((NAzsB))); + + + ViewerXc=(int32)Op02FX<<_FIX_SHIFT_; + ViewerYc=(int32)Op02FY<<_FIX_SHIFT_; + ViewerZc=(int32)Op02FZ<<_FIX_SHIFT_; + + //CenterX = (-sin(NAasB)*ViewerZc*CXdistance)+ViewerXc; + //CenterY = (cos(NAasB)*ViewerZc*CXdistance)+ViewerYc; + //Op02CX = (short)CenterX; + //Op02CY = (short)CenterY; + SMULT1616(t,-Sin(Angle(NAasB)),ViewerZc) + SMULT1616(t,t,CXdistance) + CenterX = t+ViewerXc; + SMULT1616(t,Cos(Angle(NAasB)),ViewerZc) + SMULT1616(t,t,CXdistance) + CenterY = t+ViewerYc; + Op02CX=CenterX>>_FIX_SHIFT_; + Op02CY=CenterY>>_FIX_SHIFT_; + + ViewerXc=ViewerX;//-Op02FX); + ViewerYc=ViewerY;//-Op02FY); + ViewerZc=ViewerZ;//-Op02FZ); + + //CenterX = (-sin(NAasB)*ViewerZc*CXdistance)+ViewerXc; + SMULT1616(t,-Sin(Angle(NAasB)),ViewerZc) + SMULT1616(t,t,CXdistance) + CenterX = t+ViewerXc; + + /*if (CenterX<-32768) CenterX = -32768; if (CenterX>32767) CenterX=32767; + CenterY = (cos(NAasB)*ViewerZc*CXdistance)+ViewerYc; + if (CenterY<-32768) CenterY = -32768; if (CenterY>32767) CenterY=32767;*/ + + //BUG en puissance : overflow + if (CenterX<(-32768<<_FIX_SHIFT_)) CenterX = (-32768<<_FIX_SHIFT_); if (CenterX>(32767<<_FIX_SHIFT_)) CenterX=(32767<<_FIX_SHIFT_); + SMULT1616(t,Cos(Angle(NAasB)),ViewerZc) + SMULT1616(t,t,CXdistance) + CenterY = t+ViewerYc; + if (CenterY<(-32768<<_FIX_SHIFT_)) CenterY = (-32768<<_FIX_SHIFT_); if (CenterY>(32767<<_FIX_SHIFT_)) CenterY=(32767<<_FIX_SHIFT_); + +// TValDebug = (NAzsB*65536/6.28); + // TValDebug2 = ScrDispl; + +// if (Op02CY < 0) {Op02CYSup = Op02CY/256; Op02CY = 0;} +// if (Op02CX < 0) {Op02CXSup = Op02CX/256; Op02CX = 0;} + +// [4/15/2001] (ViewerX+ViewerX1*NumberOfSlope); +// [4/15/2001] (ViewerY+ViewerY1*NumberOfSlope); + +// if(Op02LFE==0x2200)Op02VVA=0xFECD; +// else Op02VVA=0xFFB2; + + + #ifdef DebugDSP1 + Log_Message("OP02 FX:%d FY:%d FZ:%d LFE:%d LES:%d",Op02FX,Op02FY,Op02FZ,Op02LFE,Op02LES); + Log_Message(" AAS:%d AZS:%d VOF:%d VVA:%d",Op02AAS,Op02AZS,Op02VOF,Op02VVA); + Log_Message(" VX:%d VY:%d VZ:%d",(short)ViewerX,(short)ViewerY,(short)ViewerZ); + #endif + +} +#else + +void DSPOp02() +{ + ViewerZ1=-cos(Op02AZS*6.2832/65536.0); + ViewerX1=sin(Op02AZS*6.2832/65536.0)*sin(Op02AAS*6.2832/65536.0); + ViewerY1=sin(Op02AZS*6.2832/65536.0)*cos(-Op02AAS*6.2832/65536.0); + + #ifdef debug02 + printf("\nViewerX1 : %f ViewerY1 : %f ViewerZ1 : %f\n",ViewerX1,ViewerY1, + ViewerZ1); + getch(); + #endif + ViewerX=Op02FX-ViewerX1*Op02LFE; + ViewerY=Op02FY-ViewerY1*Op02LFE; + ViewerZ=Op02FZ-ViewerZ1*Op02LFE; + + ScreenX=Op02FX+ViewerX1*(Op02LES-Op02LFE); + ScreenY=Op02FY+ViewerY1*(Op02LES-Op02LFE); + ScreenZ=Op02FZ+ViewerZ1*(Op02LES-Op02LFE); + + #ifdef debug02 + printf("ViewerX : %f ViewerY : %f ViewerZ : %f\n",ViewerX,ViewerY,ViewerZ); + printf("Op02FX : %d Op02FY : %d Op02FZ : %d\n",Op02FX,Op02FY,Op02FZ); + printf("ScreenX : %f ScreenY : %f ScreenZ : %f\n",ScreenX,ScreenY,ScreenZ); + getch(); + #endif + if (ViewerZ1==0)ViewerZ1++; + NumberOfSlope=ViewerZ/-ViewerZ1; + + Op02CX=(short)(Op02CXF=ViewerX+ViewerX1*NumberOfSlope); + Op02CY=(short)(Op02CYF=ViewerY+ViewerY1*NumberOfSlope); + + ViewerXc=ViewerX;//-Op02FX); + ViewerYc=ViewerY;//-Op02FY); + ViewerZc=ViewerZ;//-Op02FZ); + + Op02VOF=0x0000; + ReversedLES=0; + Op02LESb=Op02LES; + if ((Op02LES>=VofAngle+16384.0) && (Op02LES=VofAngle) && (Op02LESb<=VofAngle+0x4000)) { + Op02VOF= (short)(Op02LESb * tan((Op02AZS-0x4000-VofAngle)*6.2832/65536.0)); + Op02VVA-=Op02VOF; + } + if (ReversedLES){ + Op02VOF=-Op02VOF; + } + + NAzsB = (Op02AZS-0x4000)*6.2832/65536.0; + NAasB = Op02AAS*6.2832/65536.0; + + if (tan(NAzsB)==0) NAzsB=0.1; + + ScrDispl=0; + if (NAzsB>-0.15) {NAzsB=-0.15;ScrDispl=Op02VVA-0xFFDA;} + + CXdistance=1/tan(NAzsB); + + CenterX = (-sin(NAasB)*ViewerZc*CXdistance)+ViewerXc; + if (CenterX<-32768) CenterX = -32768; if (CenterX>32767) CenterX=32767; + Op02CX = (short)CenterX; + CenterY = (cos(NAasB)*ViewerZc*CXdistance)+ViewerYc; + if (CenterY<-32768) CenterY = -32768; if (CenterY>32767) CenterY=32767; + Op02CY = (short)CenterY; + +// TValDebug = (NAzsB*65536/6.28); + // TValDebug2 = ScrDispl; + +// if (Op02CY < 0) {Op02CYSup = Op02CY/256; Op02CY = 0;} +// if (Op02CX < 0) {Op02CXSup = Op02CX/256; Op02CX = 0;} + +// [4/15/2001] (ViewerX+ViewerX1*NumberOfSlope); +// [4/15/2001] (ViewerY+ViewerY1*NumberOfSlope); + +// if(Op02LFE==0x2200)Op02VVA=0xFECD; +// else Op02VVA=0xFFB2; + + + #ifdef DebugDSP1 + Log_Message("OP02 FX:%d FY:%d FZ:%d LFE:%d LES:%d",Op02FX,Op02FY,Op02FZ,Op02LFE,Op02LES); + Log_Message(" AAS:%d AZS:%d VOF:%d VVA:%d",Op02AAS,Op02AZS,Op02VOF,Op02VVA); + Log_Message(" VX:%d VY:%d VZ:%d",(short)ViewerX,(short)ViewerY,(short)ViewerZ); + #endif + +} +#endif + +short Op0AVS; +short Op0AA; +short Op0AB; +short Op0AC; +short Op0AD; + +/*double RasterRX; +double RasterRY; +double RasterRZ; +double RasterLSlopeX; +double RasterLSlopeY; +double RasterLSlopeZ; +double RasterRSlopeX; +double RasterRSlopeY; +double RasterRSlopeZ; +double GroundLX; +double GroundLY; +double GroundRX; +double GroundRY; +double Distance; + +double NAzs,NAas; +double RVPos,RHPos,RXRes,RYRes;*/ + +int32 RasterRX; +int32 RasterRY; +int32 RasterRZ; +int32 RasterLSlopeX; +int32 RasterLSlopeY; +int32 RasterLSlopeZ; +int32 RasterRSlopeX; +int32 RasterRSlopeY; +int32 RasterRSlopeZ; +int32 GroundLX; +int32 GroundLY; +int32 GroundRX; +int32 GroundRY; +int32 Distance; + +int32 NAzs,NAas; +int32 RVPos,RHPos,RXRes,RYRes; + + + +void GetRXYPos(){ + int32 scalar; + + if (Op02LES==0) return; + + + NAzs = NAzsB - Atan((RVPos) / (int32)Op02LES); + NAas = NAasB;// + Atan(RHPos) / (double)Op02LES); + + /* if (cos(NAzs)==0) NAzs+=0.001; + if (tan(NAzs)==0) NAzs+=0.001;*/ + if (Cos(Angle(NAzs))==0) NAzs+=10; + if (Sin(Angle(NAzs))==0) NAzs+=10; + + /*RXRes = (-sin(NAas)*ViewerZc/(tan(NAzs))+ViewerXc); + RYRes = (cos(NAas)*ViewerZc/(tan(NAzs))+ViewerYc); + scalar = ((ViewerZc/sin(NAzs))/(double)Op02LES); + RXRes += scalar*-sin(NAas+PI_float/2)*RHPos; + RYRes += scalar*cos(NAas+PI_float/2)*RHPos;*/ + RXRes = ((int64)-Sin(Angle(NAas))*(int64)ViewerZc/ ((int64)(Sin(Angle(NAzs))<<_FIX_SHIFT_)/(int64)Cos(Angle(NAzs)) )+ViewerXc); + RYRes = ((int64)Cos(Angle(NAas))*(int64)ViewerZc/ ((int64)(Sin(Angle(NAzs))<<_FIX_SHIFT_)/(int64)Cos(Angle(NAzs)) )+ViewerYc); + scalar = ((ViewerZc/Sin(Angle(NAzs)))/(int32)Op02LES); + int32 t; + SMULT1616(t,-Sin(Angle(NAas+PI/2)),RHPos) + RXRes += scalar*t; + SMULT1616(t,Cos(Angle(NAas+PI/2)),RHPos) + RYRes += scalar*t; +} + +void DSPOp0A() +{ + //double x2,y2,x3,y3,x4,y4,m,ypos; + int32 x2,y2,x3,y3,x4,y4,m,ypos; + + + if(Op0AVS==0) {Op0AVS++; return;} + ypos=(int32)(Op0AVS-ScrDispl)<<_FIX_SHIFT_; + // CenterX,CenterX = Center (x1,y1) + // Get (0,Vs) coords (x2,y2) + RVPos = ypos; RHPos = 0; + GetRXYPos(); x2 = RXRes; y2 = RYRes; + // Get (-128,Vs) coords (x3,y3) + RVPos = ypos; RHPos = -128<<_FIX_SHIFT_; + GetRXYPos(); x3 = RXRes; y3 = RYRes; + // Get (127,Vs) coords (x4,y4) + RVPos = ypos; RHPos = 127<<_FIX_SHIFT_; + GetRXYPos(); x4 = RXRes; y4 = RYRes; + + // A = (x4-x3)/256 + //m = (x4-x3)/256*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + m = (x4-x3)>>16; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AA = (short)(m); + // C = (y4-y3)/256 + //m = (y4-y3)/256*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + m = (y4-y3)>>16; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AC = (short)(m); + if (ypos==0){ + Op0AB = 0; + Op0AD = 0; + } + else { + // B = (x2-x1)/Vs + m = (x2-CenterX)/ypos*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AB = (short)(m); + // D = (y2-y1)/Vs + m = (y2-CenterY)/ypos*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AD = (short)(m); + } + + Op0AVS+=1; +} + +short Op06X; +short Op06Y; +short Op06Z; +short Op06H; +short Op06V; +unsigned short Op06S; + +/*double ObjPX; +double ObjPY; +double ObjPZ; +double ObjPX1; +double ObjPY1; +double ObjPZ1; +double ObjPX2; +double ObjPY2; +double ObjPZ2; +double DivideOp06;*/ +int32 ObjPX; +int32 ObjPY; +int32 ObjPZ; +int32 ObjPX1; +int32 ObjPY1; +int32 ObjPZ1; +int32 ObjPX2; +int32 ObjPY2; +int32 ObjPZ2; +int32 DivideOp06; +int Temp; +int tanval2; + +#ifdef __OPT06__ +void DSPOp06() +{ + + ObjPX=Op06X-Op02FX; + ObjPY=Op06Y-Op02FY; + ObjPZ=Op06Z-Op02FZ; + + + + // rotate around Z + tanval2 = Angle(-Op02AAS+32768); +// tanval2 = (-Op02AAS+32768)/(65536/INCR); + //ObjPX1=(ObjPX*Cos(tanval2)+ObjPY*-Sin(tanval2)); + SADDMULT1616(ObjPX1,ObjPX,Cos(tanval2),ObjPY,-Sin(tanval2)) + //ObjPY1=(ObjPX*Sin(tanval2)+ObjPY*Cos(tanval2)); + SADDMULT1616(ObjPY1,ObjPX,Sin(tanval2),ObjPY,Cos(tanval2)) + ObjPZ1=ObjPZ; + + + // rotate around X +// tanval2 = (-Op02AZS/(65536/INCR)) & 1023; + tanval2 = Angle(-Op02AZS); +// tanval2 = (-Op02AZS)/256; + ObjPX2=ObjPX1; + //ObjPY2=(ObjPY1*Cos(tanval2)+ObjPZ1*-Sin(tanval2)); + SADDMULT1616(ObjPY2,ObjPY1,Cos(tanval2),ObjPZ1,-Sin(tanval2)) + //ObjPZ2=(ObjPY1*Sin(tanval2)+ObjPZ1*Cos(tanval2)); + SADDMULT1616(ObjPZ2,ObjPY1,Sin(tanval2),ObjPZ1,Cos(tanval2)) + + #ifdef debug06 + Log_Message("ObjPX2: %f ObjPY2: %f ObjPZ2: %f\n",ObjPX2,ObjPY2,ObjPZ2); + #endif + + ObjPZ2=ObjPZ2-Op02LFE; + + if (ObjPZ2<0) + { + Op06H=(short)(-(int64)ObjPX2*(int64)Op02LES/-(ObjPZ2)); //-ObjPX2*256/-ObjPZ2; + Op06V=(short)(-(int64)ObjPY2*(int64)Op02LES/-(ObjPZ2)); //-ObjPY2*256/-ObjPZ2; + Op06S=(unsigned short)(256*(int64)(Op02LES<<_FIX_SHIFT_)/-ObjPZ2); + } + else + { + Op06H=0; + Op06V=14*16; + Op06S=0xFFFF; + } + + + #ifdef DebugDSP1 + Log_Message("OP06 X:%d Y:%d Z:%d",Op06X,Op06Y,Op06Z); + Log_Message("OP06 H:%d V:%d S:%d",Op06H,Op06V,Op06S); + #endif +} +#else + +void DSPOp06() +{ + ObjPX=Op06X-Op02FX; + ObjPY=Op06Y-Op02FY; + ObjPZ=Op06Z-Op02FZ; + + // rotate around Z + tanval = (-Op02AAS+32768)/65536.0*6.2832; + ObjPX1=(ObjPX*cos(tanval)+ObjPY*-sin(tanval)); + ObjPY1=(ObjPX*sin(tanval)+ObjPY*cos(tanval)); + ObjPZ1=ObjPZ; + + #ifdef debug06 + Log_Message("Angle : %f", tanval); + Log_Message("ObjPX1: %f ObjPY1: %f ObjPZ1: %f\n",ObjPX1,ObjPY1,ObjPZ1); + Log_Message("cos(tanval) : %f sin(tanval) : %f", cos(tanval), sin(tanval)); + #endif + + // rotate around X + tanval = (-Op02AZS)/65536.0*6.2832; + ObjPX2=ObjPX1; + ObjPY2=(ObjPY1*cos(tanval)+ObjPZ1*-sin(tanval)); + ObjPZ2=(ObjPY1*sin(tanval)+ObjPZ1*cos(tanval)); + + #ifdef debug06 + Log_Message("ObjPX2: %f ObjPY2: %f ObjPZ2: %f\n",ObjPX2,ObjPY2,ObjPZ2); + #endif + + ObjPZ2=ObjPZ2-Op02LFE; + + if (ObjPZ2<0) + { + Op06H=(short)(-ObjPX2*Op02LES/-(ObjPZ2)); //-ObjPX2*256/-ObjPZ2; + Op06V=(short)(-ObjPY2*Op02LES/-(ObjPZ2)); //-ObjPY2*256/-ObjPZ2; + Op06S=(unsigned short)(256*(double)Op02LES/-ObjPZ2); + } + else + { + Op06H=0; + Op06V=14*16; + Op06S=0xFFFF; + } + + + #ifdef DebugDSP1 + Log_Message("OP06 X:%d Y:%d Z:%d",Op06X,Op06Y,Op06Z); + Log_Message("OP06 H:%d V:%d S:%d",Op06H,Op06V,Op06S); + #endif +} +#endif + + + +/*double matrixB[3][3]; +double matrixB2[3][3]; +double matrixB3[3][3]; + +double matrixA[3][3]; +double matrixA2[3][3]; +double matrixA3[3][3];*/ +int32 matrixB[3][3]; +int32 matrixB2[3][3]; +int32 matrixB3[3][3]; + +int32 matrixA[3][3]; +int32 matrixA2[3][3]; +int32 matrixA3[3][3]; + + +void MultMatrixB(int32 result[3][3],int32 mat1[3][3],int32 mat2[3][3]) +{ + result[0][0]=(mat1[0][0]*mat2[0][0]+mat1[0][1]*mat2[1][0]+mat1[0][2]*mat2[2][0])>>_FIX_SHIFT_; + result[0][1]=(mat1[0][0]*mat2[0][1]+mat1[0][1]*mat2[1][1]+mat1[0][2]*mat2[2][1])>>_FIX_SHIFT_; + result[0][2]=(mat1[0][0]*mat2[0][2]+mat1[0][1]*mat2[1][2]+mat1[0][2]*mat2[2][2])>>_FIX_SHIFT_; + + result[1][0]=(mat1[1][0]*mat2[0][0]+mat1[1][1]*mat2[1][0]+mat1[1][2]*mat2[2][0])>>_FIX_SHIFT_; + result[1][1]=(mat1[1][0]*mat2[0][1]+mat1[1][1]*mat2[1][1]+mat1[1][2]*mat2[2][1])>>_FIX_SHIFT_; + result[1][2]=(mat1[1][0]*mat2[0][2]+mat1[1][1]*mat2[1][2]+mat1[1][2]*mat2[2][2])>>_FIX_SHIFT_; + + result[2][0]=(mat1[2][0]*mat2[0][0]+mat1[2][1]*mat2[1][0]+mat1[2][2]*mat2[2][0])>>_FIX_SHIFT_; + result[2][1]=(mat1[2][0]*mat2[0][1]+mat1[2][1]*mat2[1][1]+mat1[2][2]*mat2[2][1])>>_FIX_SHIFT_; + result[2][2]=(mat1[2][0]*mat2[0][2]+mat1[2][1]*mat2[1][2]+mat1[2][2]*mat2[2][2])>>_FIX_SHIFT_; + +} + + +short Op01m; +short Op01Zr; +short Op01Xr; +short Op01Yr; +short Op11m; +short Op11Zr; +short Op11Xr; +short Op11Yr; +short Op21m; +short Op21Zr; +short Op21Xr; +short Op21Yr; +//double sc,sc2,sc3; +int32 sc,sc2,sc3; + + + +#ifdef __OPT01__ +void DSPOp01() +{ + unsigned short zr,yr,xr; + + zr = Angle(Op01Zr); + xr = Angle(Op01Yr); + yr = Angle(Op01Xr); + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=Cos(xr); matrixB[1][2]=-Sin(xr); + matrixB[2][0]=0; matrixB[2][1]=Sin(xr); matrixB[2][2]=Cos(xr); + + matrixB2[0][0]=Cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=Sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-Sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=Cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=Cos(zr); matrixB2[0][1]=-Sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=Sin(zr); matrixB2[1][1]=Cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc = ((double)Op01m)/32768.0; + + matrixA[0][0]=matrixB[0][0]; matrixA[0][1]=matrixB[0][1]; matrixA[0][2]=matrixB[0][2]; + matrixA[1][0]=matrixB[1][0]; matrixA[1][1]=matrixB[1][1]; matrixA[1][2]=matrixB[1][2]; + matrixA[2][0]=matrixB[2][0]; matrixA[2][1]=matrixB[2][1]; matrixA[2][2]=matrixB[2][2]; + + #ifdef DebugDSP1 + Log_Message("OP01 ZR: %d XR: %d YR: %d",Op01Zr,Op01Xr,Op01Yr); + #endif +} + +#else + +void DSPOp01() +{ + double zr,yr,xr; + + zr = ((double)Op01Zr)*6.2832/65536; + xr = ((double)Op01Yr)*6.2832/65536; + yr = ((double)Op01Xr)*6.2832/65536; + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=cos(xr); matrixB[1][2]=-sin(xr); + matrixB[2][0]=0; matrixB[2][1]=sin(xr); matrixB[2][2]=cos(xr); + + matrixB2[0][0]=cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=cos(zr); matrixB2[0][1]=-sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=sin(zr); matrixB2[1][1]=cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc = ((double)Op01m)/32768.0; + + matrixA[0][0]=matrixB[0][0]; matrixA[0][1]=matrixB[0][1]; matrixA[0][2]=matrixB[0][2]; + matrixA[1][0]=matrixB[1][0]; matrixA[1][1]=matrixB[1][1]; matrixA[1][2]=matrixB[1][2]; + matrixA[2][0]=matrixB[2][0]; matrixA[2][1]=matrixB[2][1]; matrixA[2][2]=matrixB[2][2]; + + #ifdef DebugDSP1 + Log_Message("OP01 ZR: %d XR: %d YR: %d",Op01Zr,Op01Xr,Op01Yr); + #endif +} +#endif + + +#ifdef __OPT11__ +void DSPOp11() +{ + short zr,yr,xr; + + zr = Angle(Op11Zr); + xr = Angle(Op11Yr); + yr = Angle(Op11Xr); + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=Cos(xr); matrixB[1][2]=-Sin(xr); + matrixB[2][0]=0; matrixB[2][1]=Sin(xr); matrixB[2][2]=Cos(xr); + + matrixB2[0][0]=Cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=Sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-Sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=Cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=Cos(zr); matrixB2[0][1]=-Sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=Sin(zr); matrixB2[1][1]=Cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc2 = ((double)Op11m)/32768.0; + + matrixA2[0][0]=matrixB[0][0]; matrixA2[0][1]=matrixB[0][1]; matrixA2[0][2]=matrixB[0][2]; + matrixA2[1][0]=matrixB[1][0]; matrixA2[1][1]=matrixB[1][1]; matrixA2[1][2]=matrixB[1][2]; + matrixA2[2][0]=matrixB[2][0]; matrixA2[2][1]=matrixB[2][1]; matrixA2[2][2]=matrixB[2][2]; + #ifdef DebugDSP1 + Log_Message("OP11 ZR: %d XR: %d YR: %d SC: %d",Op11Zr,Op11Xr,Op11Yr,Op11m); + #endif +} +#else + +void DSPOp11() +{ + double zr,yr,xr; + + zr = ((double)Op11Zr)*6.2832/65536; + xr = ((double)Op11Yr)*6.2832/65536; + yr = ((double)Op11Xr)*6.2832/65536; + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=cos(xr); matrixB[1][2]=-sin(xr); + matrixB[2][0]=0; matrixB[2][1]=sin(xr); matrixB[2][2]=cos(xr); + + matrixB2[0][0]=cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=cos(zr); matrixB2[0][1]=-sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=sin(zr); matrixB2[1][1]=cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc2 = ((double)Op11m)/32768.0; + + matrixA2[0][0]=matrixB[0][0]; matrixA2[0][1]=matrixB[0][1]; matrixA2[0][2]=matrixB[0][2]; + matrixA2[1][0]=matrixB[1][0]; matrixA2[1][1]=matrixB[1][1]; matrixA2[1][2]=matrixB[1][2]; + matrixA2[2][0]=matrixB[2][0]; matrixA2[2][1]=matrixB[2][1]; matrixA2[2][2]=matrixB[2][2]; + #ifdef DebugDSP1 + Log_Message("OP11 ZR: %d XR: %d YR: %d SC: %d",Op11Zr,Op11Xr,Op11Yr,Op11m); + #endif +} +#endif + + +#ifdef __OPT21__ +void DSPOp21() +{ + short zr,yr,xr; + + zr = Angle(Op21Zr); + xr = Angle(Op21Yr); + yr = Angle(Op21Xr); + + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=Cos(xr); matrixB[1][2]=-Sin(xr); + matrixB[2][0]=0; matrixB[2][1]=Sin(xr); matrixB[2][2]=Cos(xr); + + matrixB2[0][0]=Cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=Sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-Sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=Cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=Cos(zr); matrixB2[0][1]=-Sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=Sin(zr); matrixB2[1][1]=Cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc3 = ((double)Op21m)/32768.0; + + matrixA3[0][0]=matrixB[0][0]; matrixA3[0][1]=matrixB[0][1]; matrixA3[0][2]=matrixB[0][2]; + matrixA3[1][0]=matrixB[1][0]; matrixA3[1][1]=matrixB[1][1]; matrixA3[1][2]=matrixB[1][2]; + matrixA3[2][0]=matrixB[2][0]; matrixA3[2][1]=matrixB[2][1]; matrixA3[2][2]=matrixB[2][2]; + #ifdef DebugDSP1 + Log_Message("OP21 ZR: %d XR: %d YR: %d",Op21Zr,Op21Xr,Op21Yr); + #endif +} +#else + +void DSPOp21() +{ + double zr,yr,xr; + + zr = ((double)Op21Zr)*6.2832/65536; + xr = ((double)Op21Yr)*6.2832/65536; + yr = ((double)Op21Xr)*6.2832/65536; + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=cos(xr); matrixB[1][2]=-sin(xr); + matrixB[2][0]=0; matrixB[2][1]=sin(xr); matrixB[2][2]=cos(xr); + + matrixB2[0][0]=cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=cos(zr); matrixB2[0][1]=-sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=sin(zr); matrixB2[1][1]=cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc3 = ((double)Op21m)/32768.0; + + matrixA3[0][0]=matrixB[0][0]; matrixA3[0][1]=matrixB[0][1]; matrixA3[0][2]=matrixB[0][2]; + matrixA3[1][0]=matrixB[1][0]; matrixA3[1][1]=matrixB[1][1]; matrixA3[1][2]=matrixB[1][2]; + matrixA3[2][0]=matrixB[2][0]; matrixA3[2][1]=matrixB[2][1]; matrixA3[2][2]=matrixB[2][2]; + #ifdef DebugDSP1 + Log_Message("OP21 ZR: %d XR: %d YR: %d",Op21Zr,Op21Xr,Op21Yr); + #endif +} +#endif + +short Op0DX; +short Op0DY; +short Op0DZ; +short Op0DF; +short Op0DL; +short Op0DU; +short Op1DX; +short Op1DY; +short Op1DZ; +short Op1DF; +short Op1DL; +short Op1DU; +short Op2DX; +short Op2DY; +short Op2DZ; +short Op2DF; +short Op2DL; +short Op2DU; + +#define swap(a,b) temp=a;a=b;b=temp; + +void DSPOp0D() +{ + double a,b,c,d,e,f,g,h,i,det,temp; + double a2,b2,c2,d2,e2,f2,g2,h2,i2,x,y,z; + + a = matrixA[0][0]; b=matrixA[0][1]; c=matrixA[0][2]; + d = matrixA[1][0]; e=matrixA[1][1]; f=matrixA[1][2]; + g = matrixA[2][0]; h=matrixA[2][1]; i=matrixA[2][2]; + //abc + //def + //ghi + det = a*e*i+b*f*g+c*d*h-g*e*c-h*f*a-i*d*b; + if (det==0) { + Op0DF=Op0DX; + Op0DL=Op0DY; + Op0DU=Op0DZ; + #ifdef DebugDSP1 + Log_Message("OP0D Error! Det == 0"); + #endif + return; + } + swap(d,b); swap(g,c); swap(h,f); + b=-b; d=-d; f=-f; h=-h; + a2=(e*i-h*f)/det; b2=(d*i-g*f)/det; c2=(d*h-g*e)/det; + d2=(b*i-h*c)/det; e2=(a*i-g*c)/det; f2=(a*h-g*b)/det; + g2=(b*f-e*c)/det; h2=(a*f-d*c)/det; i2=(a*e-d*b)/det; + x=Op0DX; y=Op0DY; z=Op0DZ; + Op0DF=(short)((x*a2+y*d2+z*g2)/2*sc); + Op0DL=(short)((x*b2+y*e2+z*h2)/2*sc); + Op0DU=(short)((x*c2+y*f2+z*i2)/2*sc); + + #ifdef DebugDSP1 + Log_Message("OP0D X: %d Y: %d Z: %d / F: %d L: %d U: %d",Op0DX,Op0DY,Op0DZ,Op0DF,Op0DL,Op0DU); + #endif +} + +void DSPOp1D() +{ + double a,b,c,d,e,f,g,h,i,det,temp; + double a2,b2,c2,d2,e2,f2,g2,h2,i2,x,y,z; + a = matrixA2[0][0]; b=matrixA2[0][1]; c=matrixA2[0][2]; + d = matrixA2[1][0]; e=matrixA2[1][1]; f=matrixA2[1][2]; + g = matrixA2[2][0]; h=matrixA2[2][1]; i=matrixA2[2][2]; + //abc + //def + //ghi + det = a*e*i+b*f*g+c*d*h-g*e*c-h*f*a-i*d*b; + if (det==0) { + Op1DF=0; Op1DL=0; Op1DU=0; + return; + } + swap(d,b); swap(g,c); swap(h,f); + b=-b; d=-d; f=-f; h=-h; + a2=(e*i-h*f)/det; b2=(d*i-g*f)/det; c2=(d*h-g*e)/det; + d2=(b*i-h*c)/det; e2=(a*i-g*c)/det; f2=(a*h-g*b)/det; + g2=(b*f-e*c)/det; h2=(a*f-d*c)/det; i2=(a*e-d*b)/det; + x=Op1DX; y=Op1DY; z=Op1DZ; + Op1DF=(short)((x*a2+y*d2+z*g2)/2*sc2); + Op1DL=(short)((x*b2+y*e2+z*h2)/2*sc2); + Op1DU=(short)((x*c2+y*f2+z*i2)/2*sc2); + #ifdef DebugDSP1 + Log_Message("OP1D X: %d Y: %d Z: %d / F: %d L: %d U: %d",Op1DX,Op1DY,Op1DZ,Op1DF,Op1DL,Op1DU); + #endif +} + +void DSPOp2D() +{ + double a,b,c,d,e,f,g,h,i,det,temp; + double a2,b2,c2,d2,e2,f2,g2,h2,i2,x,y,z; + a = matrixA3[0][0]; b=matrixA3[0][1]; c=matrixA3[0][2]; + d = matrixA3[1][0]; e=matrixA3[1][1]; f=matrixA3[1][2]; + g = matrixA3[2][0]; h=matrixA3[2][1]; i=matrixA3[2][2]; + //abc + //def + //ghi + det = a*e*i+b*f*g+c*d*h-g*e*c-h*f*a-i*d*b; + if (det==0) { + Op2DF=0; Op2DL=0; Op2DU=0; + return; + } + swap(d,b); swap(g,c); swap(h,f); + b=-b; d=-d; f=-f; h=-h; + a2=(e*i-h*f)/det; b2=(d*i-g*f)/det; c2=(d*h-g*e)/det; + d2=(b*i-h*c)/det; e2=(a*i-g*c)/det; f2=(a*h-g*b)/det; + g2=(b*f-e*c)/det; h2=(a*f-d*c)/det; i2=(a*e-d*b)/det; + x=Op2DX; y=Op2DY; z=Op2DZ; + Op2DF=(short)((x*a2+y*d2+z*g2)/2*sc3); + Op2DL=(short)((x*b2+y*e2+z*h2)/2*sc3); + Op2DU=(short)((x*c2+y*f2+z*i2)/2*sc3); + #ifdef DebugDSP1 + Log_Message("OP2D X: %d Y: %d Z: %d / F: %d L: %d U: %d",Op2DX,Op2DY,Op2DZ,Op2DF,Op2DL,Op2DU); + #endif +} + +short Op03F; +short Op03L; +short Op03U; +short Op03X; +short Op03Y; +short Op03Z; +short Op13F; +short Op13L; +short Op13U; +short Op13X; +short Op13Y; +short Op13Z; +short Op23F; +short Op23L; +short Op23U; +short Op23X; +short Op23Y; +short Op23Z; + +void DSPOp03() +{ + double F,L,U; + + F=Op03F; L=Op03L; U=Op03U; + Op03X=(short)((F*matrixA[0][0]+L*matrixA[1][0]+U*matrixA[2][0])/2*sc); + Op03Y=(short)((F*matrixA[0][1]+L*matrixA[1][1]+U*matrixA[2][1])/2*sc); + Op03Z=(short)((F*matrixA[0][2]+L*matrixA[1][2]+U*matrixA[2][2])/2*sc); + + #ifdef DebugDSP1 + Log_Message("OP03 F: %d L: %d U: %d / X: %d Y: %d Z: %d",Op03F,Op03L,Op03U,Op03X,Op03Y,Op03Z); + #endif +} + +void DSPOp13() +{ + double F,L,U; + F=Op13F; L=Op13L; U=Op13U; + Op13X=(short)((F*matrixA2[0][0]+L*matrixA2[1][0]+U*matrixA2[2][0])/2*sc2); + Op13Y=(short)((F*matrixA2[0][1]+L*matrixA2[1][1]+U*matrixA2[2][1])/2*sc2); + Op13Z=(short)((F*matrixA2[0][2]+L*matrixA2[1][2]+U*matrixA2[2][2])/2*sc2); + #ifdef DebugDSP1 + Log_Message("OP13 F: %d L: %d U: %d / X: %d Y: %d Z: %d",Op13F,Op13L,Op13U,Op13X,Op13Y,Op13Z); + #endif +} + +void DSPOp23() +{ + double F,L,U; + F=Op23F; L=Op23L; U=Op23U; + Op23X=(short)((F*matrixA3[0][0]+L*matrixA3[1][0]+U*matrixA3[2][0])/2*sc3); + Op23Y=(short)((F*matrixA3[0][1]+L*matrixA3[1][1]+U*matrixA3[2][1])/2*sc3); + Op23Z=(short)((F*matrixA3[0][2]+L*matrixA3[1][2]+U*matrixA3[2][2])/2*sc3); + #ifdef DebugDSP1 + Log_Message("OP23 F: %d L: %d U: %d / X: %d Y: %d Z: %d",Op23F,Op23L,Op23U,Op23X,Op23Y,Op23Z); + #endif +} + +short Op14Zr; +short Op14Xr; +short Op14Yr; +short Op14U; +short Op14F; +short Op14L; +short Op14Zrr; +short Op14Xrr; +short Op14Yrr; + +//double Op14Temp; +int32 Op14Temp; +void DSPOp14() +{ +//TODO + Op14Temp=(Op14Zr*6.2832/65536.0)+(1/cos(Op14Xr*6.2832/65536.0))*((Op14U*6.2832/65536.0)*cos(Op14Yr*6.2832/65536.0)-(Op14F*6.2832/65536.0)*sin(Op14Yr*6.2832/65536.0)); + Op14Zrr=(short)(Op14Temp*65536.0/6.2832); + Op14Temp=(Op14Xr*6.2832/65536.0)+((Op14U*6.2832/65536.0)*sin(Op14Yr*6.2832/65536.0)+(Op14F*6.2832/65536.0)*cos(Op14Yr*6.2832/65536.0)); + Op14Xrr=(short)(Op14Temp*65536.0/6.2832); + Op14Temp=(Op14Yr*6.2832/65536.0)-tan(Op14Xr*6.2832/65536.0)*((Op14U*6.2832/65536.0)*cos(Op14Yr*6.2832/65536.0)+(Op14F*6.2832/65536.0)*sin(Op14Yr*6.2832/65536.0))+(Op14L*6.2832/65536.0); + Op14Yrr=(short)(Op14Temp*65536.0/6.2832); + + + #ifdef DebugDSP1 + Log_Message("OP14 X:%d Y%d Z:%D U:%d F:%d L:%d",Op14Xr,Op14Yr,Op14Zr,Op14U,Op14F,Op14L); + Log_Message("OP14 X:%d Y%d Z:%D",Op14Xrr,Op14Yrr,Op14Zrr); + #endif +} + +short Op0EH; +short Op0EV; +short Op0EX; +short Op0EY; + +void DSPOp0E() +{ + + // screen Directions UP + //RVPos = Op0EV; + RVPos = Op0EV<<_FIX_SHIFT_; + //RHPos = Op0EH; + RHPos = Op0EH<<_FIX_SHIFT_; + GetRXYPos(); + //Op0EX = RXRes; + Op0EX = RXRes>>_FIX_SHIFT_; + //Op0EY = RYRes; + Op0EY = RYRes>>_FIX_SHIFT_; + + #ifdef DebugDSP1 + Log_Message("OP0E COORDINATE H:%d V:%d X:%d Y:%d",Op0EH,Op0EV,Op0EX,Op0EY); + #endif +} + +short Op0BX; +short Op0BY; +short Op0BZ; +short Op0BS; +short Op1BX; +short Op1BY; +short Op1BZ; +short Op1BS; +short Op2BX; +short Op2BY; +short Op2BZ; +short Op2BS; + +void DSPOp0B() +{ + //Op0BS = (Op0BX*matrixA[0][0]+Op0BY*matrixA2[0][1]+Op0BZ*matrixA2[0][2]); + Op0BS = (Op0BX*matrixA[0][0]+Op0BY*matrixA2[0][1]+Op0BZ*matrixA2[0][2])>>_FIX_SHIFT_; +#ifdef DebugDSP1 + Log_Message("OP0B"); +#endif +} + +void DSPOp1B() +{ + //Op1BS = (Op1BX*matrixA2[0][0]+Op1BY*matrixA2[0][1]+Op1BZ*matrixA2[0][2]); + Op1BS = (Op1BX*matrixA2[0][0]+Op1BY*matrixA2[0][1]+Op1BZ*matrixA2[0][2])>>_FIX_SHIFT_; +#ifdef DebugDSP1 + Log_Message("OP1B X: %d Y: %d Z: %d S: %d",Op1BX,Op1BY,Op1BZ,Op1BS); + Log_Message(" MX: %d MY: %d MZ: %d Scale: %d",(short)(matrixA2[0][0]*100),(short)(matrixA2[0][1]*100),(short)(matrixA2[0][2]*100),(short)(sc2*100)); +#endif + +} + +void DSPOp2B() +{ + //Op2BS = (Op2BX*matrixA3[0][0]+Op2BY*matrixA3[0][1]+Op2BZ*matrixA3[0][2]); + Op2BS = (Op2BX*matrixA3[0][0]+Op2BY*matrixA3[0][1]+Op2BZ*matrixA3[0][2])>>_FIX_SHIFT_; +#ifdef DebugDSP1 + Log_Message("OP2B"); +#endif +} + +short Op08X,Op08Y,Op08Z,Op08Ll,Op08Lh; +long Op08Size; + +void DSPOp08() +{ + Op08Size=(Op08X*Op08X+Op08Y*Op08Y+Op08Z*Op08Z)*2; + Op08Ll = Op08Size&0xFFFF; + Op08Lh = (Op08Size>>16) & 0xFFFF; + #ifdef DebugDSP1 + Log_Message("OP08 %d,%d,%d",Op08X,Op08Y,Op08Z); + Log_Message("OP08 ((Op08X^2)+(Op08Y^2)+(Op08X^2))=%x",Op08Size ); + #endif +} + +short Op18X,Op18Y,Op18Z,Op18R,Op18D; + +void DSPOp18() +{ + //double x,y,z,r; + int32 x,y,z,r; + x=Op18X; y=Op18Y; z=Op18Z; r=Op18R; + r = (x*x+y*y+z*z-r*r); + if (r>32767) r=32767; + if (r<-32768) r=-32768; + Op18D=(short)r; + #ifdef DebugDSP1 + Log_Message("OP18 X: %d Y: %d Z: %d R: %D DIFF %d",Op18X,Op18Y,Op18Z,Op18D); + #endif +} + +short Op38X,Op38Y,Op38Z,Op38R,Op38D; + +void DSPOp38() +{ + Op38D = (Op38X * Op38X + Op38Y * Op38Y + Op38Z * Op38Z - Op38R * Op38R) >> 15; + Op38D++; + + #ifdef DebugDSP1 + Log_Message("OP38 X: %d Y: %d Z: %d R: %D DIFF %d",Op38X,Op38Y,Op38Z,Op38D); + #endif +} + + +short Op28X; +short Op28Y; +short Op28Z; +short Op28R; + +void DSPOp28() +{ + //to optimize... sqrt + Op28R=(short)sqrt((double)(Op28X*Op28X+Op28Y*Op28Y+Op28Z*Op28Z)); + #ifdef DebugDSP1 + Log_Message("OP28 X:%d Y:%d Z:%d",Op28X,Op28Y,Op28Z); + Log_Message("OP28 Vector Length %d",Op28R); + #endif +} + +short Op1CAZ; +unsigned short Op1CX,Op1CY,Op1CZ; +short Op1CXBR,Op1CYBR,Op1CZBR,Op1CXAR,Op1CYAR,Op1CZAR; +short Op1CX1; +short Op1CY1; +short Op1CZ1; +short Op1CX2; +short Op1CY2; +short Op1CZ2; + +#ifdef __OPT1C__ +void DSPOp1C() +{ + short ya,xa,za; + ya = Angle(Op1CX); + xa = Angle(Op1CY); + za = Angle(Op1CZ); + + // rotate around Z + //Op1CX1=(Op1CXBR*Cos(za)+Op1CYBR*Sin(za)); + Op1CX1=(Op1CXBR*Cos(za)+Op1CYBR*Sin(za))>>_FIX_SHIFT_; + //Op1CY1=(Op1CXBR*-Sin(za)+Op1CYBR*Cos(za)); + Op1CY1=(Op1CXBR*-Sin(za)+Op1CYBR*Cos(za))>>_FIX_SHIFT_; + Op1CZ1=Op1CZBR; + // rotate around Y + //Op1CX2=(Op1CX1*Cos(ya)+Op1CZ1*-Sin(ya)); + Op1CX2=(Op1CX1*Cos(ya)+Op1CZ1*-Sin(ya))>>_FIX_SHIFT_; + Op1CY2=Op1CY1; + //Op1CZ2=(Op1CX1*Sin(ya)+Op1CZ1*Cos(ya)); + Op1CZ2=(Op1CX1*Sin(ya)+Op1CZ1*Cos(ya))>>_FIX_SHIFT_; + // rotate around X + Op1CXAR=Op1CX2; + //Op1CYAR=(Op1CY2*Cos(xa)+Op1CZ2*Sin(xa)); + Op1CYAR=(Op1CY2*Cos(xa)+Op1CZ2*Sin(xa))>>_FIX_SHIFT_; + //Op1CZAR=(Op1CY2*-Sin(xa)+Op1CZ2*Cos(xa)); + Op1CZAR=(Op1CY2*-Sin(xa)+Op1CZ2*Cos(xa))>>_FIX_SHIFT_; + + #ifdef DebugDSP1 + Log_Message("OP1C Apply Matrix CX:%d CY:%d CZ",Op1CXAR,Op1CYAR,Op1CZAR); + #endif +} +#else +void DSPOp1C() +{ + double ya,xa,za; + ya = Op1CX/65536.0*PI*2; + xa = Op1CY/65536.0*PI*2; + za = Op1CZ/65536.0*PI*2; + // rotate around Z + Op1CX1=(Op1CXBR*cos(za)+Op1CYBR*sin(za)); + Op1CY1=(Op1CXBR*-sin(za)+Op1CYBR*cos(za)); + Op1CZ1=Op1CZBR; + // rotate around Y + Op1CX2=(Op1CX1*cos(ya)+Op1CZ1*-sin(ya)); + Op1CY2=Op1CY1; + Op1CZ2=(Op1CX1*sin(ya)+Op1CZ1*cos(ya)); + // rotate around X + Op1CXAR=Op1CX2; + Op1CYAR=(Op1CY2*cos(xa)+Op1CZ2*sin(xa)); + Op1CZAR=(Op1CY2*-sin(xa)+Op1CZ2*cos(xa)); + + #ifdef DebugDSP1 + Log_Message("OP1C Apply Matrix CX:%d CY:%d CZ",Op1CXAR,Op1CYAR,Op1CZAR); + #endif +} + +#endif + +unsigned short Op0FRamsize; +unsigned short Op0FPass; + +void DSPOp0F() +{ + Op0FPass = 0x0000; + + #ifdef DebugDSP1 + Log_Message("OP0F RAM Test Pass:%d", Op0FPass); + #endif +} + + +short Op2FUnknown; +short Op2FSize; + +void DSPOp2F() +{ + Op2FSize=0x100; +} diff --git a/src/dsp1emu_yo.c b/src/dsp1emu_yo.c new file mode 100644 index 0000000..4b4e579 --- /dev/null +++ b/src/dsp1emu_yo.c @@ -0,0 +1,1423 @@ +//Copyright (C) 1997-2001 ZSNES Team ( zsknight@zsnes.com / _demo_@zsnes.com ) +// +//This program is free software; you can redistribute it and/or +//modify it under the terms of the GNU General Public License +//as published by the Free Software Foundation; either +//version 2 of the License, or (at your option) any later +//version. +// +//This program is distributed in the hope that it will be useful, +//but WITHOUT ANY WARRANTY; without even the implied warranty of +//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +//GNU General Public License for more details. +// +//You should have received a copy of the GNU General Public License +//along with this program; if not, write to the Free Software +//Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + + +#ifndef __GP32__ +#include +#include +#endif +#include + +#ifndef __GP32__ +#include +#include +#endif + +#ifdef __GP32__ +#include "gp32_func.h" +#endif +//#define DebugDSP1 + +// uncomment some lines to test +//#define printinfo +//#define debug02 +//#define debug0A +//#define debug06 + +#define __OPT__ +#define __OPT01__ +#define __OPT02__ +#define __OPT04__ //was commented on original source (yoyo) +#define __OPT06__ +#define __OPT0C__ // this optimisation may break pilotwings +#define __OPT11__ +#define __OPT21__ +#define __OPT1C__ + +#ifdef DebugDSP1 + +FILE * LogFile = NULL; + +void Log_Message (char *Message, ...) +{ + char Msg[400]; + va_list ap; + + va_start(ap,Message); + vsprintf(Msg,Message,ap ); + va_end(ap); + + strcat(Msg,"\r\n\0"); + fwrite(Msg,strlen(Msg),1,LogFile); + fflush (LogFile); +} + +void Start_Log (void) +{ + char LogFileName[255]; +// [4/15/2001] char *p; + + strcpy(LogFileName,"dsp1emu.log\0"); + + LogFile = fopen(LogFileName,"wb"); +} + +void Stop_Log (void) +{ + if (LogFile) + { + fclose(LogFile); + LogFile = NULL; + } +} + +#endif + + +/***************************************************************************\ +* Math tables * +\***************************************************************************/ + +double *CosTable2; +double *SinTable2; + +int32 *CosTable2Fix; +int32 *SinTable2Fix; + +#define INCR 2048 +#define Angle(x) (((x)/(65536/INCR)) & (INCR-1)) + +#define AngleFix(x) (((x)>>5) & (INCR-1)) + +#define Cos(x) ((double) CosTable2[x]) +#define Sin(x) ((double) SinTable2[x]) + +#define CosFix(x) (CosTable2Fix[x]) +#define SinFix(x) (SinTable2Fix[x]) + +#define PI 3.14159265358979323846264338327 + +double Atan(double x) +{ + if ((x>=1) || (x<=1)) + return (x/(1+0.28*x*x)); + else + return (PI/2 - Atan(1/x)); +} + + +/***************************************************************************\ +* DSP1 code * +\***************************************************************************/ + + +void InitDSP(void) +{ +#ifdef __OPT__ + unsigned int i; + CosTable2 = (double *) malloc(INCR*sizeof(double)); + SinTable2 = (double *) malloc(INCR*sizeof(double)); + + CosTable2Fix = (int32 *) malloc(INCR*sizeof(int32)); + SinTable2Fix = (int32 *) malloc(INCR*sizeof(int32)); + for (i=0; i 0) + while (Op10Temp>=1.0) { + Op10Temp=Op10Temp/2.0; + Op10ExponentR++; + } + else + while (Op10Temp<-1.0) { + Op10Temp=Op10Temp/2.0; + Op10ExponentR++; + } + Op10CoefficientR = Op10Temp*32768; + #ifdef DebugDSP1 + Log_Message("OP10 INV %d*2^%d = %d*2^%d", Op10Coefficient, Op10Exponent, Op10CoefficientR, Op10ExponentR); + #endif +} + + +short Op04Angle; +unsigned short Op04Radius; +short Op04Sin; +short Op04Cos; + +#ifdef __OPT04__ + +void DSPOp04() +{ + dsp_opcode[0x04]++; + + int32 angle; + //angle = Angle(Op04Angle); + angle = AngleFix(Op04Angle); + + //Op04Sin = Sin(angle) * Op04Radius; + SMULT1616(Op04Sin,SinFix(angle),(int32)Op04Radius) + //Op04Cos = Cos(angle) * Op04Radius; + SMULT1616(Op04Cos,CosFix(angle),(int32)Op04Radius); + + #ifdef DebugDSP1 + Log_Message("OP04 Angle:%d Radius:%d",(Op04Angle/256)&255,Op04Radius); + Log_Message("OP04 SIN:%d COS:%d",Op04Sin,Op04Cos); + #endif +} +#else + +void DSPOp04() +{ + double angle; + + angle = Op04Angle*2*PI/65536.0; + + Op04Sin = sin(angle) * Op04Radius; + Op04Cos = cos(angle) * Op04Radius; + + #ifdef DebugDSP1 + Log_Message("OP04 Angle:%d Radius:%d",(Op04Angle/256)&255,Op04Radius); + Log_Message("OP04 SIN:%d COS:%d",Op04Sin,Op04Cos); + #endif +} +#endif + +unsigned short Op0CA; +short Op0CX1; +short Op0CY1; +short Op0CX2; +short Op0CY2; + +#ifdef __OPT0C__ +void DSPOp0C() +{ +dsp_opcode[0x0C]++; + + Op0CX2=(Op0CX1*Cos(Angle(Op0CA))+Op0CY1*Sin(Angle(Op0CA))); + Op0CY2=(Op0CX1*-Sin(Angle(Op0CA))+Op0CY1*Cos(Angle(Op0CA))); + #ifdef DebugDSP1 + Log_Message("OP0C Angle:%d X:%d Y:%d CX:%d CY:%d",(Op0CA/256)&255,Op0CX1,Op0CY1,Op0CX2,Op0CY2); + #endif +} +#else +void DSPOp0C() +{ + + Op0CX2=(Op0CX1*cos(Op0CA*2*PI/65536.0)+Op0CY1*sin(Op0CA*2*PI/65536.0)); + Op0CY2=(Op0CX1*-sin(Op0CA*2*PI/65536.0)+Op0CY1*cos(Op0CA*2*PI/65536.0)); + #ifdef DebugDSP1 + Log_Message("OP0C Angle:%d X:%d Y:%d CX:%d CY:%d",(Op0CA/256)&255,Op0CX1,Op0CY1,Op0CX2,Op0CY2); + #endif +} + +#endif + +short Op02FX; +short Op02FY; +short Op02FZ; +short Op02LFE; +short Op02LES; +unsigned short Op02AAS; +unsigned short Op02AZS; +unsigned short Op02VOF; +unsigned short Op02VVA; + +short Op02CX; +short Op02CY; +double Op02CXF; +double Op02CYF; +double ViewerX0; +double ViewerY0; +double ViewerZ0; +double ViewerX1; +double ViewerY1; +double ViewerZ1; +double ViewerX; +double ViewerY; +double ViewerZ; +int ViewerAX; +int ViewerAY; +int ViewerAZ; +double NumberOfSlope; +double ScreenX; +double ScreenY; +double ScreenZ; +double TopLeftScreenX; +double TopLeftScreenY; +double TopLeftScreenZ; +double BottomRightScreenX; +double BottomRightScreenY; +double BottomRightScreenZ; +double Ready; +double RasterLX; +double RasterLY; +double RasterLZ; +double ScreenLX1; +double ScreenLY1; +double ScreenLZ1; +int ReversedLES; +short Op02LESb; +double NAzsB,NAasB; +double ViewerXc; +double ViewerYc; +double ViewerZc; +double CenterX,CenterY; +short Op02CYSup,Op02CXSup; +double CXdistance; + +#define VofAngle 0x3880 + +short TValDebug,TValDebug2; +short ScrDispl; + + +#ifdef __OPT02__ +void DSPOp02() +{ +dsp_opcode[0x02]++; + + ViewerZ1=-Cos(Angle(Op02AZS)); + ViewerX1=Sin(Angle(Op02AZS))*Sin(Angle(Op02AAS)); + ViewerY1=Sin(Angle(Op02AZS))*Cos(Angle(Op02AAS)); + + + #ifdef debug02 + printf("\nViewerX1 : %f ViewerY1 : %f ViewerZ1 : %f\n",ViewerX1,ViewerY1, + ViewerZ1); + getch(); + #endif + ViewerX=Op02FX-ViewerX1*Op02LFE; + ViewerY=Op02FY-ViewerY1*Op02LFE; + ViewerZ=Op02FZ-ViewerZ1*Op02LFE; + + ScreenX=Op02FX+ViewerX1*(Op02LES-Op02LFE); + ScreenY=Op02FY+ViewerY1*(Op02LES-Op02LFE); + ScreenZ=Op02FZ+ViewerZ1*(Op02LES-Op02LFE); + + #ifdef debug02 + printf("ViewerX : %f ViewerY : %f ViewerZ : %f\n",ViewerX,ViewerY,ViewerZ); + printf("Op02FX : %d Op02FY : %d Op02FZ : %d\n",Op02FX,Op02FY,Op02FZ); + printf("ScreenX : %f ScreenY : %f ScreenZ : %f\n",ScreenX,ScreenY,ScreenZ); + getch(); + #endif + if (ViewerZ1==0)ViewerZ1++; + NumberOfSlope=ViewerZ/-ViewerZ1; + + Op02CX=(short)(Op02CXF=ViewerX+ViewerX1*NumberOfSlope); + Op02CY=(short)(Op02CYF=ViewerY+ViewerY1*NumberOfSlope); + + Op02VOF=0x0000; + ReversedLES=0; + Op02LESb=Op02LES; + if ((Op02LES>=VofAngle+16384.0) && (Op02LES=VofAngle) && (Op02LESb<=VofAngle+0x4000)) { + Op02VOF= (short)(Op02LESb * tan((Op02AZS-0x4000-VofAngle)*6.2832/65536.0)); + Op02VVA-=Op02VOF; + } + if (ReversedLES){ + Op02VOF=-Op02VOF; + } + + NAzsB = (Op02AZS-0x4000)*6.2832/65536.0; + NAasB = Op02AAS*6.2832/65536.0; + + if (tan(NAzsB)==0) NAzsB=0.1; + + ScrDispl=0; + if (NAzsB>-0.15) {NAzsB=-0.15;ScrDispl=Op02VVA-0xFFDA;} + + CXdistance=1/tan(NAzsB); + + ViewerXc=Op02FX; + ViewerYc=Op02FY; + ViewerZc=Op02FZ; + + CenterX = (-sin(NAasB)*ViewerZc*CXdistance)+ViewerXc; + CenterY = (cos(NAasB)*ViewerZc*CXdistance)+ViewerYc; + Op02CX = (short)CenterX; + Op02CY = (short)CenterY; + + ViewerXc=ViewerX;//-Op02FX); + ViewerYc=ViewerY;//-Op02FY); + ViewerZc=ViewerZ;//-Op02FZ); + + CenterX = (-sin(NAasB)*ViewerZc*CXdistance)+ViewerXc; + if (CenterX<-32768) CenterX = -32768; if (CenterX>32767) CenterX=32767; + CenterY = (cos(NAasB)*ViewerZc*CXdistance)+ViewerYc; + if (CenterY<-32768) CenterY = -32768; if (CenterY>32767) CenterY=32767; + + TValDebug = (NAzsB*65536/6.28); + TValDebug2 = ScrDispl; + +// if (Op02CY < 0) {Op02CYSup = Op02CY/256; Op02CY = 0;} +// if (Op02CX < 0) {Op02CXSup = Op02CX/256; Op02CX = 0;} + +// [4/15/2001] (ViewerX+ViewerX1*NumberOfSlope); +// [4/15/2001] (ViewerY+ViewerY1*NumberOfSlope); + +// if(Op02LFE==0x2200)Op02VVA=0xFECD; +// else Op02VVA=0xFFB2; + + + #ifdef DebugDSP1 + Log_Message("OP02 FX:%d FY:%d FZ:%d LFE:%d LES:%d",Op02FX,Op02FY,Op02FZ,Op02LFE,Op02LES); + Log_Message(" AAS:%d AZS:%d VOF:%d VVA:%d",Op02AAS,Op02AZS,Op02VOF,Op02VVA); + Log_Message(" VX:%d VY:%d VZ:%d",(short)ViewerX,(short)ViewerY,(short)ViewerZ); + #endif + +} +#else + +void DSPOp02() +{ + ViewerZ1=-cos(Op02AZS*6.2832/65536.0); + ViewerX1=sin(Op02AZS*6.2832/65536.0)*sin(Op02AAS*6.2832/65536.0); + ViewerY1=sin(Op02AZS*6.2832/65536.0)*cos(-Op02AAS*6.2832/65536.0); + + #ifdef debug02 + printf("\nViewerX1 : %f ViewerY1 : %f ViewerZ1 : %f\n",ViewerX1,ViewerY1, + ViewerZ1); + getch(); + #endif + ViewerX=Op02FX-ViewerX1*Op02LFE; + ViewerY=Op02FY-ViewerY1*Op02LFE; + ViewerZ=Op02FZ-ViewerZ1*Op02LFE; + + ScreenX=Op02FX+ViewerX1*(Op02LES-Op02LFE); + ScreenY=Op02FY+ViewerY1*(Op02LES-Op02LFE); + ScreenZ=Op02FZ+ViewerZ1*(Op02LES-Op02LFE); + + #ifdef debug02 + printf("ViewerX : %f ViewerY : %f ViewerZ : %f\n",ViewerX,ViewerY,ViewerZ); + printf("Op02FX : %d Op02FY : %d Op02FZ : %d\n",Op02FX,Op02FY,Op02FZ); + printf("ScreenX : %f ScreenY : %f ScreenZ : %f\n",ScreenX,ScreenY,ScreenZ); + getch(); + #endif + if (ViewerZ1==0)ViewerZ1++; + NumberOfSlope=ViewerZ/-ViewerZ1; + + Op02CX=(short)(Op02CXF=ViewerX+ViewerX1*NumberOfSlope); + Op02CY=(short)(Op02CYF=ViewerY+ViewerY1*NumberOfSlope); + + ViewerXc=ViewerX;//-Op02FX); + ViewerYc=ViewerY;//-Op02FY); + ViewerZc=ViewerZ;//-Op02FZ); + + Op02VOF=0x0000; + ReversedLES=0; + Op02LESb=Op02LES; + if ((Op02LES>=VofAngle+16384.0) && (Op02LES=VofAngle) && (Op02LESb<=VofAngle+0x4000)) { + Op02VOF= (short)(Op02LESb * tan((Op02AZS-0x4000-VofAngle)*6.2832/65536.0)); + Op02VVA-=Op02VOF; + } + if (ReversedLES){ + Op02VOF=-Op02VOF; + } + + NAzsB = (Op02AZS-0x4000)*6.2832/65536.0; + NAasB = Op02AAS*6.2832/65536.0; + + if (tan(NAzsB)==0) NAzsB=0.1; + + ScrDispl=0; + if (NAzsB>-0.15) {NAzsB=-0.15;ScrDispl=Op02VVA-0xFFDA;} + + CXdistance=1/tan(NAzsB); + + CenterX = (-sin(NAasB)*ViewerZc*CXdistance)+ViewerXc; + if (CenterX<-32768) CenterX = -32768; if (CenterX>32767) CenterX=32767; + Op02CX = (short)CenterX; + CenterY = (cos(NAasB)*ViewerZc*CXdistance)+ViewerYc; + if (CenterY<-32768) CenterY = -32768; if (CenterY>32767) CenterY=32767; + Op02CY = (short)CenterY; + + TValDebug = (NAzsB*65536/6.28); + TValDebug2 = ScrDispl; + +// if (Op02CY < 0) {Op02CYSup = Op02CY/256; Op02CY = 0;} +// if (Op02CX < 0) {Op02CXSup = Op02CX/256; Op02CX = 0;} + +// [4/15/2001] (ViewerX+ViewerX1*NumberOfSlope); +// [4/15/2001] (ViewerY+ViewerY1*NumberOfSlope); + +// if(Op02LFE==0x2200)Op02VVA=0xFECD; +// else Op02VVA=0xFFB2; + + + #ifdef DebugDSP1 + Log_Message("OP02 FX:%d FY:%d FZ:%d LFE:%d LES:%d",Op02FX,Op02FY,Op02FZ,Op02LFE,Op02LES); + Log_Message(" AAS:%d AZS:%d VOF:%d VVA:%d",Op02AAS,Op02AZS,Op02VOF,Op02VVA); + Log_Message(" VX:%d VY:%d VZ:%d",(short)ViewerX,(short)ViewerY,(short)ViewerZ); + #endif + +} +#endif + +short Op0AVS; +short Op0AA; +short Op0AB; +short Op0AC; +short Op0AD; + +double RasterRX; +double RasterRY; +double RasterRZ; +double RasterLSlopeX; +double RasterLSlopeY; +double RasterLSlopeZ; +double RasterRSlopeX; +double RasterRSlopeY; +double RasterRSlopeZ; +double GroundLX; +double GroundLY; +double GroundRX; +double GroundRY; +double Distance; + +double NAzs,NAas; +double RVPos,RHPos,RXRes,RYRes; + + +void GetRXYPos(){ + double scalar; + + if (Op02LES==0) return; + + + NAzs = NAzsB - Atan((RVPos) / (double)Op02LES); + NAas = NAasB;// + Atan(RHPos) / (double)Op02LES); + + if (cos(NAzs)==0) NAzs+=0.001; + if (tan(NAzs)==0) NAzs+=0.001; + + RXRes = (-sin(NAas)*ViewerZc/(tan(NAzs))+ViewerXc); + RYRes = (cos(NAas)*ViewerZc/(tan(NAzs))+ViewerYc); + scalar = ((ViewerZc/sin(NAzs))/(double)Op02LES); + RXRes += scalar*-sin(NAas+PI/2)*RHPos; + RYRes += scalar*cos(NAas+PI/2)*RHPos; +} + +void DSPOp0A() +{ +dsp_opcode[0x0A]++; + + double x2,y2,x3,y3,x4,y4,m,ypos; + + + if(Op0AVS==0) {Op0AVS++; return;} + ypos=Op0AVS-ScrDispl; + // CenterX,CenterX = Center (x1,y1) + // Get (0,Vs) coords (x2,y2) + RVPos = ypos; RHPos = 0; + GetRXYPos(); x2 = RXRes; y2 = RYRes; + // Get (-128,Vs) coords (x3,y3) + RVPos = ypos; RHPos = -128; + GetRXYPos(); x3 = RXRes; y3 = RYRes; + // Get (127,Vs) coords (x4,y4) + RVPos = ypos; RHPos = 127; + GetRXYPos(); x4 = RXRes; y4 = RYRes; + + // A = (x4-x3)/256 + m = (x4-x3)/256*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AA = (short)(m); + // C = (y4-y3)/256 + m = (y4-y3)/256*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AC = (short)(m); + if (ypos==0){ + Op0AB = 0; + Op0AD = 0; + } + else { + // B = (x2-x1)/Vs + m = (x2-CenterX)/ypos*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AB = (short)(m); + // D = (y2-y1)/Vs + m = (y2-CenterY)/ypos*256; if (m>32767) m=32767; if (m<-32768) m=-32768; + Op0AD = (short)(m); + } + + Op0AVS+=1; +} + +short Op06X; +short Op06Y; +short Op06Z; +short Op06H; +short Op06V; +unsigned short Op06S; + +/*double ObjPX; +double ObjPY; +double ObjPZ; +double ObjPX1; +double ObjPY1; +double ObjPZ1; +double ObjPX2; +double ObjPY2; +double ObjPZ2;*/ +int32 ObjPX; +int32 ObjPY; +int32 ObjPZ; +int32 ObjPX1; +int32 ObjPY1; +int32 ObjPZ1; +int32 ObjPX2; +int32 ObjPY2; +int32 ObjPZ2; +double DivideOp06; +int Temp; +int tanval2; + +#ifdef __OPT06__ +void DSPOp06() +{ + + dsp_opcode[0x06]++; + + ObjPX=Op06X-Op02FX; + ObjPY=Op06Y-Op02FY; + ObjPZ=Op06Z-Op02FZ; + + + + // rotate around Z + //tanval2 = Angle(-Op02AAS+32768); +// tanval2 = (-Op02AAS+32768)/(65536/INCR); + //ObjPX1=(ObjPX*Cos(tanval2)+ObjPY*-Sin(tanval2)); + //ObjPY1=(ObjPX*Sin(tanval2)+ObjPY*Cos(tanval2)); + //ObjPZ1=ObjPZ; + tanval2 = AngleFix(-Op02AAS+32768); + SADDMULT1616(ObjPX1,ObjPX,CosFix(tanval2),ObjPY,-SinFix(tanval2)) + SADDMULT1616(ObjPY1,ObjPX,SinFix(tanval2),ObjPY,CosFix(tanval2)) + ObjPZ1=ObjPZ; + + + // rotate around X +// tanval2 = (-Op02AZS/(65536/INCR)) & 1023; + //tanval2 = Angle(-Op02AZS); +// tanval2 = (-Op02AZS)/256; + /*ObjPX2=ObjPX1; + ObjPY2=(ObjPY1*Cos(tanval2)+ObjPZ1*-Sin(tanval2)); + ObjPZ2=(ObjPY1*Sin(tanval2)+ObjPZ1*Cos(tanval2));*/ + tanval2 = AngleFix(-Op02AZS); + ObjPX2=ObjPX1; + SADDMULT1616(ObjPY2,ObjPY1,CosFix(tanval2),ObjPZ1,-SinFix(tanval2)) + SADDMULT1616(ObjPZ2,ObjPY1,SinFix(tanval2),ObjPZ1,CosFix(tanval2)) + + #ifdef debug06 + Log_Message("ObjPX2: %f ObjPY2: %f ObjPZ2: %f\n",ObjPX2,ObjPY2,ObjPZ2); + #endif + + ObjPZ2=ObjPZ2-Op02LFE; + + if (ObjPZ2<0) + { + Op06H=(short)(-ObjPX2*Op02LES/-(ObjPZ2)); //-ObjPX2*256/-ObjPZ2; + Op06V=(short)(-ObjPY2*Op02LES/-(ObjPZ2)); //-ObjPY2*256/-ObjPZ2; + //Op06S=(unsigned short)(256*(double)Op02LES/-ObjPZ2); + Op06S=(unsigned short)(256*(int32)Op02LES/-ObjPZ2); + } + else + { + Op06H=0; + Op06V=14*16; + Op06S=0xFFFF; + } + + + #ifdef DebugDSP1 + Log_Message("OP06 X:%d Y:%d Z:%d",Op06X,Op06Y,Op06Z); + Log_Message("OP06 H:%d V:%d S:%d",Op06H,Op06V,Op06S); + #endif +} +#else + +void DSPOp06() +{ + ObjPX=Op06X-Op02FX; + ObjPY=Op06Y-Op02FY; + ObjPZ=Op06Z-Op02FZ; + + // rotate around Z + tanval = (-Op02AAS+32768)/65536.0*6.2832; + ObjPX1=(ObjPX*cos(tanval)+ObjPY*-sin(tanval)); + ObjPY1=(ObjPX*sin(tanval)+ObjPY*cos(tanval)); + ObjPZ1=ObjPZ; + + #ifdef debug06 + Log_Message("Angle : %f", tanval); + Log_Message("ObjPX1: %f ObjPY1: %f ObjPZ1: %f\n",ObjPX1,ObjPY1,ObjPZ1); + Log_Message("cos(tanval) : %f sin(tanval) : %f", cos(tanval), sin(tanval)); + #endif + + // rotate around X + tanval = (-Op02AZS)/65536.0*6.2832; + ObjPX2=ObjPX1; + ObjPY2=(ObjPY1*cos(tanval)+ObjPZ1*-sin(tanval)); + ObjPZ2=(ObjPY1*sin(tanval)+ObjPZ1*cos(tanval)); + + #ifdef debug06 + Log_Message("ObjPX2: %f ObjPY2: %f ObjPZ2: %f\n",ObjPX2,ObjPY2,ObjPZ2); + #endif + + ObjPZ2=ObjPZ2-Op02LFE; + + if (ObjPZ2<0) + { + Op06H=(short)(-ObjPX2*Op02LES/-(ObjPZ2)); //-ObjPX2*256/-ObjPZ2; + Op06V=(short)(-ObjPY2*Op02LES/-(ObjPZ2)); //-ObjPY2*256/-ObjPZ2; + Op06S=(unsigned short)(256*(double)Op02LES/-ObjPZ2); + } + else + { + Op06H=0; + Op06V=14*16; + Op06S=0xFFFF; + } + + + #ifdef DebugDSP1 + Log_Message("OP06 X:%d Y:%d Z:%d",Op06X,Op06Y,Op06Z); + Log_Message("OP06 H:%d V:%d S:%d",Op06H,Op06V,Op06S); + #endif +} +#endif + + + +double matrixB[3][3]; +double matrixB2[3][3]; +double matrixB3[3][3]; + +double matrixA[3][3]; +double matrixA2[3][3]; +double matrixA3[3][3]; + +void MultMatrixB(double result[3][3],double mat1[3][3],double mat2[3][3]) +{ + result[0][0]=(mat1[0][0]*mat2[0][0]+mat1[0][1]*mat2[1][0]+mat1[0][2]*mat2[2][0]); + result[0][1]=(mat1[0][0]*mat2[0][1]+mat1[0][1]*mat2[1][1]+mat1[0][2]*mat2[2][1]); + result[0][2]=(mat1[0][0]*mat2[0][2]+mat1[0][1]*mat2[1][2]+mat1[0][2]*mat2[2][2]); + + result[1][0]=(mat1[1][0]*mat2[0][0]+mat1[1][1]*mat2[1][0]+mat1[1][2]*mat2[2][0]); + result[1][1]=(mat1[1][0]*mat2[0][1]+mat1[1][1]*mat2[1][1]+mat1[1][2]*mat2[2][1]); + result[1][2]=(mat1[1][0]*mat2[0][2]+mat1[1][1]*mat2[1][2]+mat1[1][2]*mat2[2][2]); + + result[2][0]=(mat1[2][0]*mat2[0][0]+mat1[2][1]*mat2[1][0]+mat1[2][2]*mat2[2][0]); + result[2][1]=(mat1[2][0]*mat2[0][1]+mat1[2][1]*mat2[1][1]+mat1[2][2]*mat2[2][1]); + result[2][2]=(mat1[2][0]*mat2[0][2]+mat1[2][1]*mat2[1][2]+mat1[2][2]*mat2[2][2]); + +} + + +short Op01m; +short Op01Zr; +short Op01Xr; +short Op01Yr; +short Op11m; +short Op11Zr; +short Op11Xr; +short Op11Yr; +short Op21m; +short Op21Zr; +short Op21Xr; +short Op21Yr; +double sc,sc2,sc3; + + + +#ifdef __OPT01__ +void DSPOp01() +{ +dsp_opcode[0x01]++; + + unsigned short zr,yr,xr; + + zr = Angle(Op01Zr); + xr = Angle(Op01Yr); + yr = Angle(Op01Xr); + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=Cos(xr); matrixB[1][2]=-Sin(xr); + matrixB[2][0]=0; matrixB[2][1]=Sin(xr); matrixB[2][2]=Cos(xr); + + matrixB2[0][0]=Cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=Sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-Sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=Cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=Cos(zr); matrixB2[0][1]=-Sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=Sin(zr); matrixB2[1][1]=Cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc = ((double)Op01m)/32768.0; + + matrixA[0][0]=matrixB[0][0]; matrixA[0][1]=matrixB[0][1]; matrixA[0][2]=matrixB[0][2]; + matrixA[1][0]=matrixB[1][0]; matrixA[1][1]=matrixB[1][1]; matrixA[1][2]=matrixB[1][2]; + matrixA[2][0]=matrixB[2][0]; matrixA[2][1]=matrixB[2][1]; matrixA[2][2]=matrixB[2][2]; + + #ifdef DebugDSP1 + Log_Message("OP01 ZR: %d XR: %d YR: %d",Op01Zr,Op01Xr,Op01Yr); + #endif +} + +#else + +void DSPOp01() +{ + double zr,yr,xr; + + zr = ((double)Op01Zr)*6.2832/65536; + xr = ((double)Op01Yr)*6.2832/65536; + yr = ((double)Op01Xr)*6.2832/65536; + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=cos(xr); matrixB[1][2]=-sin(xr); + matrixB[2][0]=0; matrixB[2][1]=sin(xr); matrixB[2][2]=cos(xr); + + matrixB2[0][0]=cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=cos(zr); matrixB2[0][1]=-sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=sin(zr); matrixB2[1][1]=cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc = ((double)Op01m)/32768.0; + + matrixA[0][0]=matrixB[0][0]; matrixA[0][1]=matrixB[0][1]; matrixA[0][2]=matrixB[0][2]; + matrixA[1][0]=matrixB[1][0]; matrixA[1][1]=matrixB[1][1]; matrixA[1][2]=matrixB[1][2]; + matrixA[2][0]=matrixB[2][0]; matrixA[2][1]=matrixB[2][1]; matrixA[2][2]=matrixB[2][2]; + + #ifdef DebugDSP1 + Log_Message("OP01 ZR: %d XR: %d YR: %d",Op01Zr,Op01Xr,Op01Yr); + #endif +} +#endif + + +#ifdef __OPT11__ +void DSPOp11() +{ +dsp_opcode[0x11]++; + + short zr,yr,xr; + + zr = Angle(Op11Zr); + xr = Angle(Op11Yr); + yr = Angle(Op11Xr); + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=Cos(xr); matrixB[1][2]=-Sin(xr); + matrixB[2][0]=0; matrixB[2][1]=Sin(xr); matrixB[2][2]=Cos(xr); + + matrixB2[0][0]=Cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=Sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-Sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=Cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=Cos(zr); matrixB2[0][1]=-Sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=Sin(zr); matrixB2[1][1]=Cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc2 = ((double)Op11m)/32768.0; + + matrixA2[0][0]=matrixB[0][0]; matrixA2[0][1]=matrixB[0][1]; matrixA2[0][2]=matrixB[0][2]; + matrixA2[1][0]=matrixB[1][0]; matrixA2[1][1]=matrixB[1][1]; matrixA2[1][2]=matrixB[1][2]; + matrixA2[2][0]=matrixB[2][0]; matrixA2[2][1]=matrixB[2][1]; matrixA2[2][2]=matrixB[2][2]; + #ifdef DebugDSP1 + Log_Message("OP11 ZR: %d XR: %d YR: %d SC: %d",Op11Zr,Op11Xr,Op11Yr,Op11m); + #endif +} +#else + +void DSPOp11() +{ + double zr,yr,xr; + + zr = ((double)Op11Zr)*6.2832/65536; + xr = ((double)Op11Yr)*6.2832/65536; + yr = ((double)Op11Xr)*6.2832/65536; + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=cos(xr); matrixB[1][2]=-sin(xr); + matrixB[2][0]=0; matrixB[2][1]=sin(xr); matrixB[2][2]=cos(xr); + + matrixB2[0][0]=cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=cos(zr); matrixB2[0][1]=-sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=sin(zr); matrixB2[1][1]=cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc2 = ((double)Op11m)/32768.0; + + matrixA2[0][0]=matrixB[0][0]; matrixA2[0][1]=matrixB[0][1]; matrixA2[0][2]=matrixB[0][2]; + matrixA2[1][0]=matrixB[1][0]; matrixA2[1][1]=matrixB[1][1]; matrixA2[1][2]=matrixB[1][2]; + matrixA2[2][0]=matrixB[2][0]; matrixA2[2][1]=matrixB[2][1]; matrixA2[2][2]=matrixB[2][2]; + #ifdef DebugDSP1 + Log_Message("OP11 ZR: %d XR: %d YR: %d SC: %d",Op11Zr,Op11Xr,Op11Yr,Op11m); + #endif +} +#endif + + +#ifdef __OPT21__ +void DSPOp21() +{ +dsp_opcode[0x21]++; + + short zr,yr,xr; + + zr = Angle(Op21Zr); + xr = Angle(Op21Yr); + yr = Angle(Op21Xr); + + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=Cos(xr); matrixB[1][2]=-Sin(xr); + matrixB[2][0]=0; matrixB[2][1]=Sin(xr); matrixB[2][2]=Cos(xr); + + matrixB2[0][0]=Cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=Sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-Sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=Cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=Cos(zr); matrixB2[0][1]=-Sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=Sin(zr); matrixB2[1][1]=Cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc3 = ((double)Op21m)/32768.0; + + matrixA3[0][0]=matrixB[0][0]; matrixA3[0][1]=matrixB[0][1]; matrixA3[0][2]=matrixB[0][2]; + matrixA3[1][0]=matrixB[1][0]; matrixA3[1][1]=matrixB[1][1]; matrixA3[1][2]=matrixB[1][2]; + matrixA3[2][0]=matrixB[2][0]; matrixA3[2][1]=matrixB[2][1]; matrixA3[2][2]=matrixB[2][2]; + #ifdef DebugDSP1 + Log_Message("OP21 ZR: %d XR: %d YR: %d",Op21Zr,Op21Xr,Op21Yr); + #endif +} +#else + +void DSPOp21() +{ + double zr,yr,xr; + + zr = ((double)Op21Zr)*6.2832/65536; + xr = ((double)Op21Yr)*6.2832/65536; + yr = ((double)Op21Xr)*6.2832/65536; + + matrixB[0][0]=1; matrixB[0][1]=0; matrixB[0][2]=0; + matrixB[1][0]=0; matrixB[1][1]=cos(xr); matrixB[1][2]=-sin(xr); + matrixB[2][0]=0; matrixB[2][1]=sin(xr); matrixB[2][2]=cos(xr); + + matrixB2[0][0]=cos(yr); matrixB2[0][1]=0; matrixB2[0][2]=sin(yr); + matrixB2[1][0]=0; matrixB2[1][1]=1; matrixB2[1][2]=0; + matrixB2[2][0]=-sin(yr); matrixB2[2][1]=0; matrixB2[2][2]=cos(yr); + + MultMatrixB(matrixB3,matrixB,matrixB2); + + matrixB2[0][0]=cos(zr); matrixB2[0][1]=-sin(zr); matrixB2[0][2]=0; + matrixB2[1][0]=sin(zr); matrixB2[1][1]=cos(zr); matrixB2[1][2]=0; + matrixB2[2][0]=0; matrixB2[2][1]=0; matrixB2[2][2]=1; + + MultMatrixB(matrixB,matrixB3,matrixB2); + + sc3 = ((double)Op21m)/32768.0; + + matrixA3[0][0]=matrixB[0][0]; matrixA3[0][1]=matrixB[0][1]; matrixA3[0][2]=matrixB[0][2]; + matrixA3[1][0]=matrixB[1][0]; matrixA3[1][1]=matrixB[1][1]; matrixA3[1][2]=matrixB[1][2]; + matrixA3[2][0]=matrixB[2][0]; matrixA3[2][1]=matrixB[2][1]; matrixA3[2][2]=matrixB[2][2]; + #ifdef DebugDSP1 + Log_Message("OP21 ZR: %d XR: %d YR: %d",Op21Zr,Op21Xr,Op21Yr); + #endif +} +#endif + +short Op0DX; +short Op0DY; +short Op0DZ; +short Op0DF; +short Op0DL; +short Op0DU; +short Op1DX; +short Op1DY; +short Op1DZ; +short Op1DF; +short Op1DL; +short Op1DU; +short Op2DX; +short Op2DY; +short Op2DZ; +short Op2DF; +short Op2DL; +short Op2DU; + +#define swap(a,b) temp=a;a=b;b=temp; + +void DSPOp0D() +{ +dsp_opcode[0x0D]++; + + double a,b,c,d,e,f,g,h,i,det,temp; + double a2,b2,c2,d2,e2,f2,g2,h2,i2,x,y,z; + + a = matrixA[0][0]; b=matrixA[0][1]; c=matrixA[0][2]; + d = matrixA[1][0]; e=matrixA[1][1]; f=matrixA[1][2]; + g = matrixA[2][0]; h=matrixA[2][1]; i=matrixA[2][2]; + //abc + //def + //ghi + det = a*e*i+b*f*g+c*d*h-g*e*c-h*f*a-i*d*b; + if (det==0) { + Op0DF=Op0DX; + Op0DL=Op0DY; + Op0DU=Op0DZ; + #ifdef DebugDSP1 + Log_Message("OP0D Error! Det == 0"); + #endif + return; + } + swap(d,b); swap(g,c); swap(h,f); + b=-b; d=-d; f=-f; h=-h; + a2=(e*i-h*f)/det; b2=(d*i-g*f)/det; c2=(d*h-g*e)/det; + d2=(b*i-h*c)/det; e2=(a*i-g*c)/det; f2=(a*h-g*b)/det; + g2=(b*f-e*c)/det; h2=(a*f-d*c)/det; i2=(a*e-d*b)/det; + x=Op0DX; y=Op0DY; z=Op0DZ; + Op0DF=(short)((x*a2+y*d2+z*g2)/2*sc); + Op0DL=(short)((x*b2+y*e2+z*h2)/2*sc); + Op0DU=(short)((x*c2+y*f2+z*i2)/2*sc); + + #ifdef DebugDSP1 + Log_Message("OP0D X: %d Y: %d Z: %d / F: %d L: %d U: %d",Op0DX,Op0DY,Op0DZ,Op0DF,Op0DL,Op0DU); + #endif +} + +void DSPOp1D() +{ +dsp_opcode[0x1D]++; + + double a,b,c,d,e,f,g,h,i,det,temp; + double a2,b2,c2,d2,e2,f2,g2,h2,i2,x,y,z; + a = matrixA2[0][0]; b=matrixA2[0][1]; c=matrixA2[0][2]; + d = matrixA2[1][0]; e=matrixA2[1][1]; f=matrixA2[1][2]; + g = matrixA2[2][0]; h=matrixA2[2][1]; i=matrixA2[2][2]; + //abc + //def + //ghi + det = a*e*i+b*f*g+c*d*h-g*e*c-h*f*a-i*d*b; + if (det==0) { + Op1DF=0; Op1DL=0; Op1DU=0; + return; + } + swap(d,b); swap(g,c); swap(h,f); + b=-b; d=-d; f=-f; h=-h; + a2=(e*i-h*f)/det; b2=(d*i-g*f)/det; c2=(d*h-g*e)/det; + d2=(b*i-h*c)/det; e2=(a*i-g*c)/det; f2=(a*h-g*b)/det; + g2=(b*f-e*c)/det; h2=(a*f-d*c)/det; i2=(a*e-d*b)/det; + x=Op1DX; y=Op1DY; z=Op1DZ; + Op1DF=(short)((x*a2+y*d2+z*g2)/2*sc2); + Op1DL=(short)((x*b2+y*e2+z*h2)/2*sc2); + Op1DU=(short)((x*c2+y*f2+z*i2)/2*sc2); + #ifdef DebugDSP1 + Log_Message("OP1D X: %d Y: %d Z: %d / F: %d L: %d U: %d",Op1DX,Op1DY,Op1DZ,Op1DF,Op1DL,Op1DU); + #endif +} + +void DSPOp2D() +{ +dsp_opcode[0x2D]++; + + double a,b,c,d,e,f,g,h,i,det,temp; + double a2,b2,c2,d2,e2,f2,g2,h2,i2,x,y,z; + a = matrixA3[0][0]; b=matrixA3[0][1]; c=matrixA3[0][2]; + d = matrixA3[1][0]; e=matrixA3[1][1]; f=matrixA3[1][2]; + g = matrixA3[2][0]; h=matrixA3[2][1]; i=matrixA3[2][2]; + //abc + //def + //ghi + det = a*e*i+b*f*g+c*d*h-g*e*c-h*f*a-i*d*b; + if (det==0) { + Op2DF=0; Op2DL=0; Op2DU=0; + return; + } + swap(d,b); swap(g,c); swap(h,f); + b=-b; d=-d; f=-f; h=-h; + a2=(e*i-h*f)/det; b2=(d*i-g*f)/det; c2=(d*h-g*e)/det; + d2=(b*i-h*c)/det; e2=(a*i-g*c)/det; f2=(a*h-g*b)/det; + g2=(b*f-e*c)/det; h2=(a*f-d*c)/det; i2=(a*e-d*b)/det; + x=Op2DX; y=Op2DY; z=Op2DZ; + Op2DF=(short)((x*a2+y*d2+z*g2)/2*sc3); + Op2DL=(short)((x*b2+y*e2+z*h2)/2*sc3); + Op2DU=(short)((x*c2+y*f2+z*i2)/2*sc3); + #ifdef DebugDSP1 + Log_Message("OP2D X: %d Y: %d Z: %d / F: %d L: %d U: %d",Op2DX,Op2DY,Op2DZ,Op2DF,Op2DL,Op2DU); + #endif +} + +short Op03F; +short Op03L; +short Op03U; +short Op03X; +short Op03Y; +short Op03Z; +short Op13F; +short Op13L; +short Op13U; +short Op13X; +short Op13Y; +short Op13Z; +short Op23F; +short Op23L; +short Op23U; +short Op23X; +short Op23Y; +short Op23Z; + +void DSPOp03() +{ +dsp_opcode[0x03]++; + + double F,L,U; + + F=Op03F; L=Op03L; U=Op03U; + Op03X=(short)((F*matrixA[0][0]+L*matrixA[1][0]+U*matrixA[2][0])/2*sc); + Op03Y=(short)((F*matrixA[0][1]+L*matrixA[1][1]+U*matrixA[2][1])/2*sc); + Op03Z=(short)((F*matrixA[0][2]+L*matrixA[1][2]+U*matrixA[2][2])/2*sc); + + #ifdef DebugDSP1 + Log_Message("OP03 F: %d L: %d U: %d / X: %d Y: %d Z: %d",Op03F,Op03L,Op03U,Op03X,Op03Y,Op03Z); + #endif +} + +void DSPOp13() +{ +dsp_opcode[0x13]++; + + double F,L,U; + F=Op13F; L=Op13L; U=Op13U; + Op13X=(short)((F*matrixA2[0][0]+L*matrixA2[1][0]+U*matrixA2[2][0])/2*sc2); + Op13Y=(short)((F*matrixA2[0][1]+L*matrixA2[1][1]+U*matrixA2[2][1])/2*sc2); + Op13Z=(short)((F*matrixA2[0][2]+L*matrixA2[1][2]+U*matrixA2[2][2])/2*sc2); + #ifdef DebugDSP1 + Log_Message("OP13 F: %d L: %d U: %d / X: %d Y: %d Z: %d",Op13F,Op13L,Op13U,Op13X,Op13Y,Op13Z); + #endif +} + +void DSPOp23() +{ +dsp_opcode[0x23]++; + + double F,L,U; + F=Op23F; L=Op23L; U=Op23U; + Op23X=(short)((F*matrixA3[0][0]+L*matrixA3[1][0]+U*matrixA3[2][0])/2*sc3); + Op23Y=(short)((F*matrixA3[0][1]+L*matrixA3[1][1]+U*matrixA3[2][1])/2*sc3); + Op23Z=(short)((F*matrixA3[0][2]+L*matrixA3[1][2]+U*matrixA3[2][2])/2*sc3); + #ifdef DebugDSP1 + Log_Message("OP23 F: %d L: %d U: %d / X: %d Y: %d Z: %d",Op23F,Op23L,Op23U,Op23X,Op23Y,Op23Z); + #endif +} + +short Op14Zr; +short Op14Xr; +short Op14Yr; +short Op14U; +short Op14F; +short Op14L; +short Op14Zrr; +short Op14Xrr; +short Op14Yrr; + +double Op14Temp; +void DSPOp14() +{ +dsp_opcode[0x14]++; + + Op14Temp=(Op14Zr*6.2832/65536.0)+(1/cos(Op14Xr*6.2832/65536.0))*((Op14U*6.2832/65536.0)*cos(Op14Yr*6.2832/65536.0)-(Op14F*6.2832/65536.0)*sin(Op14Yr*6.2832/65536.0)); + Op14Zrr=(short)(Op14Temp*65536.0/6.2832); + Op14Temp=(Op14Xr*6.2832/65536.0)+((Op14U*6.2832/65536.0)*sin(Op14Yr*6.2832/65536.0)+(Op14F*6.2832/65536.0)*cos(Op14Yr*6.2832/65536.0)); + Op14Xrr=(short)(Op14Temp*65536.0/6.2832); + Op14Temp=(Op14Yr*6.2832/65536.0)-tan(Op14Xr*6.2832/65536.0)*((Op14U*6.2832/65536.0)*cos(Op14Yr*6.2832/65536.0)+(Op14F*6.2832/65536.0)*sin(Op14Yr*6.2832/65536.0))+(Op14L*6.2832/65536.0); + Op14Yrr=(short)(Op14Temp*65536.0/6.2832); + #ifdef DebugDSP1 + Log_Message("OP14 X:%d Y%d Z:%D U:%d F:%d L:%d",Op14Xr,Op14Yr,Op14Zr,Op14U,Op14F,Op14L); + Log_Message("OP14 X:%d Y%d Z:%D",Op14Xrr,Op14Yrr,Op14Zrr); + #endif +} + +short Op0EH; +short Op0EV; +short Op0EX; +short Op0EY; + +void DSPOp0E() +{ +dsp_opcode[0x0E]++; + + // screen Directions UP + RVPos = Op0EV; + RHPos = Op0EH; + GetRXYPos(); + Op0EX = RXRes; + Op0EY = RYRes; + + #ifdef DebugDSP1 + Log_Message("OP0E COORDINATE H:%d V:%d X:%d Y:%d",Op0EH,Op0EV,Op0EX,Op0EY); + #endif +} + +short Op0BX; +short Op0BY; +short Op0BZ; +short Op0BS; +short Op1BX; +short Op1BY; +short Op1BZ; +short Op1BS; +short Op2BX; +short Op2BY; +short Op2BZ; +short Op2BS; + +void DSPOp0B() +{ +dsp_opcode[0x0B]++; + + Op0BS = (Op0BX*matrixA[0][0]+Op0BY*matrixA2[0][1]+Op0BZ*matrixA2[0][2]); +#ifdef DebugDSP1 + Log_Message("OP0B"); +#endif +} + +void DSPOp1B() +{ +dsp_opcode[0x1B]++; + + Op1BS = (Op1BX*matrixA2[0][0]+Op1BY*matrixA2[0][1]+Op1BZ*matrixA2[0][2]); +#ifdef DebugDSP1 + Log_Message("OP1B X: %d Y: %d Z: %d S: %d",Op1BX,Op1BY,Op1BZ,Op1BS); + Log_Message(" MX: %d MY: %d MZ: %d Scale: %d",(short)(matrixA2[0][0]*100),(short)(matrixA2[0][1]*100),(short)(matrixA2[0][2]*100),(short)(sc2*100)); +#endif + +} + +void DSPOp2B() +{ +dsp_opcode[0x2B]++; + + Op2BS = (Op2BX*matrixA3[0][0]+Op2BY*matrixA3[0][1]+Op2BZ*matrixA3[0][2]); +#ifdef DebugDSP1 + Log_Message("OP2B"); +#endif +} + +short Op08X,Op08Y,Op08Z,Op08Ll,Op08Lh; +long Op08Size; + +void DSPOp08() +{ +dsp_opcode[0x08]++; + + Op08Size=(Op08X*Op08X+Op08Y*Op08Y+Op08Z*Op08Z)*2; + Op08Ll = Op08Size&0xFFFF; + Op08Lh = (Op08Size>>16) & 0xFFFF; + #ifdef DebugDSP1 + Log_Message("OP08 %d,%d,%d",Op08X,Op08Y,Op08Z); + Log_Message("OP08 ((Op08X^2)+(Op08Y^2)+(Op08X^2))=%x",Op08Size ); + #endif +} + +short Op18X,Op18Y,Op18Z,Op18R,Op18D; + +void DSPOp18() +{ +dsp_opcode[0x18]++; + + double x,y,z,r; + x=Op18X; y=Op18Y; z=Op18Z; r=Op18R; + r = (x*x+y*y+z*z-r*r); + if (r>32767) r=32767; + if (r<-32768) r=-32768; + Op18D=(short)r; + #ifdef DebugDSP1 + Log_Message("OP18 X: %d Y: %d Z: %d R: %D DIFF %d",Op18X,Op18Y,Op18Z,Op18D); + #endif +} + +short Op28X; +short Op28Y; +short Op28Z; +short Op28R; + +int32 fixed_sqrt(int32 r) +{ + int32 t,b,c=0; + + for (b=0x10000000;b!=0;b>>=2) { + t = c + b; + c >>= 1; + if (t <= r) { + r -= t; + c += b; + } + } + return(c); +} + + +void DSPOp28() +{ +dsp_opcode[0x28]++; + +// Op28R=(short)sqrt((double)(Op28X*Op28X+Op28Y*Op28Y+Op28Z*Op28Z)); + Op28R=(short)fixed_sqrt((int32)(Op28X*Op28X+Op28Y*Op28Y+Op28Z*Op28Z)); + #ifdef DebugDSP1 + Log_Message("OP28 X:%d Y:%d Z:%d",Op28X,Op28Y,Op28Z); + Log_Message("OP28 Vector Length %d",Op28R); + #endif +} + +short Op1CAZ; +unsigned short Op1CX,Op1CY,Op1CZ; +short Op1CXBR,Op1CYBR,Op1CZBR,Op1CXAR,Op1CYAR,Op1CZAR; +short Op1CX1; +short Op1CY1; +short Op1CZ1; +short Op1CX2; +short Op1CY2; +short Op1CZ2; + +#ifdef __OPT1C__ +void DSPOp1C() +{ +dsp_opcode[0x1C]++; + + short ya,xa,za; + ya = Angle(Op1CX); + xa = Angle(Op1CY); + za = Angle(Op1CZ); + + // rotate around Z + Op1CX1=(Op1CXBR*Cos(za)+Op1CYBR*Sin(za)); + Op1CY1=(Op1CXBR*-Sin(za)+Op1CYBR*Cos(za)); + Op1CZ1=Op1CZBR; + // rotate around Y + Op1CX2=(Op1CX1*Cos(ya)+Op1CZ1*-Sin(ya)); + Op1CY2=Op1CY1; + Op1CZ2=(Op1CX1*Sin(ya)+Op1CZ1*Cos(ya)); + // rotate around X + Op1CXAR=Op1CX2; + Op1CYAR=(Op1CY2*Cos(xa)+Op1CZ2*Sin(xa)); + Op1CZAR=(Op1CY2*-Sin(xa)+Op1CZ2*Cos(xa)); + + #ifdef DebugDSP1 + Log_Message("OP1C Apply Matrix CX:%d CY:%d CZ",Op1CXAR,Op1CYAR,Op1CZAR); + #endif +} +#else +void DSPOp1C() +{ + double ya,xa,za; + ya = Op1CX/65536.0*PI*2; + xa = Op1CY/65536.0*PI*2; + za = Op1CZ/65536.0*PI*2; + // rotate around Z + Op1CX1=(Op1CXBR*cos(za)+Op1CYBR*sin(za)); + Op1CY1=(Op1CXBR*-sin(za)+Op1CYBR*cos(za)); + Op1CZ1=Op1CZBR; + // rotate around Y + Op1CX2=(Op1CX1*cos(ya)+Op1CZ1*-sin(ya)); + Op1CY2=Op1CY1; + Op1CZ2=(Op1CX1*sin(ya)+Op1CZ1*cos(ya)); + // rotate around X + Op1CXAR=Op1CX2; + Op1CYAR=(Op1CY2*cos(xa)+Op1CZ2*sin(xa)); + Op1CZAR=(Op1CY2*-sin(xa)+Op1CZ2*cos(xa)); + + #ifdef DebugDSP1 + Log_Message("OP1C Apply Matrix CX:%d CY:%d CZ",Op1CXAR,Op1CYAR,Op1CZAR); + #endif +} + +#endif diff --git a/src/dsp2emu.c b/src/dsp2emu.c new file mode 100644 index 0000000..1eeb021 --- /dev/null +++ b/src/dsp2emu.c @@ -0,0 +1,341 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ + + +uint16 DSP2Op09Word1=0; +uint16 DSP2Op09Word2=0; +bool DSP2Op05HasLen=false; +int DSP2Op05Len=0; +bool DSP2Op06HasLen=false; +int DSP2Op06Len=0; +uint8 DSP2Op05Transparent=0; + +void DSP2_Op05 () +{ + uint8 color; + // Overlay bitmap with transparency. + // Input: + // + // Bitmap 1: i[0] <=> i[size-1] + // Bitmap 2: i[size] <=> i[2*size-1] + // + // Output: + // + // Bitmap 3: o[0] <=> o[size-1] + // + // Processing: + // + // Process all 4-bit pixels (nibbles) in the bitmap + // + // if ( BM2_pixel == transparent_color ) + // pixelout = BM1_pixel + // else + // pixelout = BM2_pixel + + // The max size bitmap is limited to 255 because the size parameter is a byte + // I think size=0 is an error. The behavior of the chip on size=0 is to + // return the last value written to DR if you read DR on Op05 with + // size = 0. I don't think it's worth implementing this quirk unless it's + // proven necessary. + + int n; + unsigned char c1; + unsigned char c2; + unsigned char *p1 = DSP1.parameters; + unsigned char *p2 = &DSP1.parameters[DSP2Op05Len]; + unsigned char *p3 = DSP1.output; + + color = DSP2Op05Transparent&0x0f; + + for( n = 0; n < DSP2Op05Len; n++ ) + { + c1 = *p1++; + c2 = *p2++; + *p3++ = ( ((c2 >> 4) == color ) ? c1 & 0xf0: c2 & 0xf0 ) | + ( ((c2 & 0x0f)==color) ? c1 & 0x0f: c2 & 0x0f ); + } +} + +void DSP2_Op01 () +{ + // Op01 size is always 32 bytes input and output. + // The hardware does strange things if you vary the size. + + int j; + unsigned char c0, c1, c2, c3; + unsigned char *p1 = DSP1.parameters; + unsigned char *p2a = DSP1.output; + unsigned char *p2b = &DSP1.output[16]; // halfway + + // Process 8 blocks of 4 bytes each + + for ( j = 0; j < 8; j++ ) + { + c0 = *p1++; + c1 = *p1++; + c2 = *p1++; + c3 = *p1++; + + *p2a++ = (c0 & 0x10) << 3 | + (c0 & 0x01) << 6 | + (c1 & 0x10) << 1 | + (c1 & 0x01) << 4 | + (c2 & 0x10) >> 1 | + (c2 & 0x01) << 2 | + (c3 & 0x10) >> 3 | + (c3 & 0x01); + + *p2a++ = (c0 & 0x20) << 2 | + (c0 & 0x02) << 5 | + (c1 & 0x20) | + (c1 & 0x02) << 3 | + (c2 & 0x20) >> 2 | + (c2 & 0x02) << 1 | + (c3 & 0x20) >> 4 | + (c3 & 0x02) >> 1; + + *p2b++ = (c0 & 0x40) << 1 | + (c0 & 0x04) << 4 | + (c1 & 0x40) >> 1 | + (c1 & 0x04) << 2 | + (c2 & 0x40) >> 3 | + (c2 & 0x04) | + (c3 & 0x40) >> 5 | + (c3 & 0x04) >> 2; + + + *p2b++ = (c0 & 0x80) | + (c0 & 0x08) << 3 | + (c1 & 0x80) >> 2 | + (c1 & 0x08) << 1 | + (c2 & 0x80) >> 4 | + (c2 & 0x08) >> 1 | + (c3 & 0x80) >> 6 | + (c3 & 0x08) >> 3; + } + return; +} + +void DSP2_Op06 () +{ + // Input: + // size + // bitmap + + int i, j; + + for ( i = 0, j = DSP2Op06Len - 1; i < DSP2Op06Len; i++, j-- ) + { + DSP1.output[j] = (DSP1.parameters[i] << 4) | (DSP1.parameters[i] >> 4); + } +} + +bool DSP2Op0DHasLen=false; +int DSP2Op0DOutLen=0; +int DSP2Op0DInLen=0; + +#ifndef DSP2_BIT_ACCURRATE_CODE + +// Scale bitmap based on input length out output length + +void DSP2_Op0D() +{ + // Overload's algorithm - use this unless doing hardware testing + + // One note: the HW can do odd byte scaling but since we divide + // by two to get the count of bytes this won't work well for + // odd byte scaling (in any of the current algorithm implementations). + // So far I haven't seen Dungeon Master use it. + // If it does we can adjust the parameters and code to work with it + + int i; + int pixel_offset; + uint8 pixelarray[512]; + + for(i=0; i>1] >> 4; + else + pixelarray[i] = DSP1.parameters[pixel_offset>>1] & 0x0f; + } + + for ( i=0; i < DSP2Op0DOutLen; i++ ) + DSP1.output[i] = ( pixelarray[i<<1] << 4 ) | pixelarray[(i<<1)+1]; +} + +#else + +void DSP2_Op0D() +{ + // Bit accurate hardware algorithm - uses fixed point math + // This should match the DSP2 Op0D output exactly + // I wouldn't recommend using this unless you're doing hardware debug. + // In some situations it has small visual artifacts that + // are not readily apparent on a TV screen but show up clearly + // on a monitor. Use Overload's scaling instead. + // This is for hardware verification testing. + // + // One note: the HW can do odd byte scaling but since we divide + // by two to get the count of bytes this won't work well for + // odd byte scaling (in any of the current algorithm implementations). + // So far I haven't seen Dungeon Master use it. + // If it does we can adjust the parameters and code to work with it + + + uint32 multiplier; // Any size int >= 32-bits + uint32 pixloc; // match size of multiplier + int i, j; + uint8 pixelarray[512]; + + if (DSP2Op0DInLen <= DSP2Op0DOutLen) + multiplier = 0x10000; // In our self defined fixed point 0x10000 == 1 + else + multiplier = (DSP2Op0DInLen << 17) / ((DSP2Op0DOutLen<<1) + 1); + + pixloc = 0; + for ( i=0; i < DSP2Op0DOutLen * 2; i++ ) + { + j = pixloc >> 16; + + if ( j & 1 ) + pixelarray[i] = DSP1.parameters[j>>1] & 0x0f; + else + pixelarray[i] = (DSP1.parameters[j>>1] & 0xf0) >> 4; + + pixloc += multiplier; + } + + for ( i=0; i < DSP2Op0DOutLen; i++ ) + DSP1.output[i] = ( pixelarray[i<<1] << 4 ) | pixelarray[(i<<1)+1]; +} + +#endif + +#if 0 // Probably no reason to use this code - it's not quite bit accurate and it doesn't look as good as Overload's algorithm + +void DSP2_Op0D() +{ + // Float implementation of Neviksti's algorithm + // This is the right algorithm to match the DSP2 bits but the precision + // of the PC float does not match the precision of the fixed point math + // on the DSP2 causing occasional one off data mismatches (which should + // be no problem because its just a one pixel difference in a scaled image + // to be displayed). + + float multiplier; + float pixloc; + int i, j; + uint8 pixelarray[512]; + + if (DSP2Op0DInLen <= DSP2Op0DOutLen) + multiplier = (float) 1.0; + else + multiplier = (float) ((DSP2Op0DInLen * 2.0) / (DSP2Op0DOutLen * 2.0 + 1.0)); + + pixloc = 0.0; + for ( i=0; i < DSP2Op0DOutLen * 2; i++ ) + { + // j = (int)(i * multiplier); + j = (int) pixloc; + + if ( j & 1 ) + pixelarray[i] = DSP1.parameters[j>>1] & 0x0f; + else + pixelarray[i] = (DSP1.parameters[j>>1] & 0xf0) >> 4; + + pixloc += multiplier; // use an add in the loop instead of multiply to increase loop speed + } + + for ( i=0; i < DSP2Op0DOutLen; i++ ) + DSP1.output[i] = ( pixelarray[i<<1] << 4 ) | pixelarray[(i<<1)+1]; +} + +#endif \ No newline at end of file diff --git a/src/dspMixer.s b/src/dspMixer.s new file mode 100644 index 0000000..8fda1f4 --- /dev/null +++ b/src/dspMixer.s @@ -0,0 +1,837 @@ + .TEXT + .ARM + .ALIGN + +#include "mixrate.h" + +@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@ Function called with: +@ r0 - Raw brr data (s8*) +@ r1 - Decoded sample data (s16*) +@ r2 - DspChannel *channel +@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@ Function Data: +@ r4 - r4 +@ r5 - r5 +@ r6,r7 - tmp +@ r8 - shift amount +@ r9 - number of iterations left +@ r10 - 0xf +@ r11 - low clip +@ r12 - high clip + + +.GLOBAL brrHash +brrHash: +.word 0 + +.GLOBAL DecodeSampleBlockAsm +DecodeSampleBlockAsm: + stmfd sp!, {r4-r12,r14} + + @ Save the channel pointer + mov r14, r2 + +/* @ Hash the block, and skip the decode if we can + ldmia r0, {r4-r7} + ldr r8, =0x050C5D1F @ (2166136261 * 16777619) + ldr r9, =16777619 + eor r8, r8, r4 + mul r8, r9, r8 + eor r8, r8, r5 + mul r8, r9, r8 + eor r8, r8, r6 + + @ r8 is the hashed value + + ldr r4, brrHash + + @ Compute the actual brr location minus the apu ram base + ldr r6, =APU_MEM + ldr r6, [r6] + sub r6, r0, r6 + + @ Compute the address of the cached samples in brrHash + add r3, r4, #0x8000 + mov r6, r6, lsr #3 + add r3, r3, r6, lsl #5 + + @ Load the previous hash value + ldr r5, [r4, r6, lsl #2] + str r8, [r4, r6, lsl #2] + cmp r5, r8 + bne doDecode + + @ Load the cached samples + ldmia r3, {r4-r11} + stmia r1!, {r4-r11} + + ldrsh r2, [r1, #-2] + ldrsh r3, [r1, #-4] + + b doneDecodeCached + +doDecode: + stmfd sp!, {r3} +*/ + @ Load r2 and r3 + ldrsh r2, [r14, #62] + ldrsh r3, [r14, #64] + + ldrb r4, [r0], #1 + @ Compute the index into the brrTab to load the bytes from + mov r9, r4, lsr #4 + ldr r8, =brrTab + add r8, r8, r9, lsl #5 @ brrTabPtr = brrTab + (r4 * 32) + + mov r10, #0xf << 1 + ldr r11, =0xffff8000 + ldr r12, =0x7fff + + @ 16 samples to decode, but do two at a time + mov r9, #8 + @ Figure out the type of decode filter + mov r4, r4, lsr #2 + and r4, r4, #3 + ldr pc, [pc, r4, lsl #2] + nop +.word case0 +.word case1 +.word case2 +.word case3 +case0: + ldrb r4, [r0], #1 + and r5, r10, r4, lsl #1 + ldrsh r5, [r8, r5] + and r4, r10, r4, lsr #3 + ldrsh r4, [r8, r4] + + mov r4, r4, lsl #1 + mov r5, r5, lsl #1 + strh r4, [r1], #2 + strh r5, [r1], #2 + + subs r9, r9, #1 + bne case0 + + @ Set up r2 and r3 + ldrsh r2, [r1, #-2] + ldrsh r3, [r1, #-4] + + b doneDecode + +case1: + ldrb r4, [r0], #1 + and r5, r10, r4, lsl #1 + ldrsh r5, [r8, r5] + and r4, r10, r4, lsr #3 + ldrsh r4, [r8, r4] + + @ r3 = r4 + (last1 >> 1) - (last1 >> 5) + add r3, r4, r2, asr #1 + sub r3, r3, r2, asr #5 + + cmp r3, r12 + movgt r3, r12 + cmp r3, r11 + movlt r3, r11 + + mov r3, r3, lsl #1 + strh r3, [r1], #2 + ldrsh r3, [r1, #-2] + + @ same for r2 now + add r2, r5, r3, asr #1 + sub r2, r2, r3, asr #5 + + cmp r2, r12 + movgt r2, r12 + cmp r2, r11 + movlt r2, r11 + + mov r2, r2, lsl #1 + strh r2, [r1], #2 + ldrsh r2, [r1, #-2] + + subs r9, r9, #1 + bne case1 + + b doneDecode + +case2: + ldrb r4, [r0], #1 + and r5, r10, r4, lsl #1 + ldrsh r5, [r8, r5] + and r4, r10, r4, lsr #3 + ldrsh r4, [r8, r4] + + @ Sample 1 + mov r6, r3, asr #1 + rsb r6, r6, r3, asr #5 + mov r3, r2 + add r7, r2, r2, asr #1 + rsb r7, r7, #0 + add r6, r6, r7, asr #5 + add r7, r4, r2 + add r2, r6, r7 + + cmp r2, r12 + movgt r2, r12 + cmp r2, r11 + movlt r2, r11 + mov r2, r2, lsl #1 + strh r2, [r1], #2 + ldrsh r2, [r1, #-2] + + @ Sample 2 + mov r6, r3, asr #1 + rsb r6, r6, r3, asr #5 + mov r3, r2 + add r7, r2, r2, asr #1 + rsb r7, r7, #0 + add r6, r6, r7, asr #5 + add r7, r5, r2 + add r2, r6, r7 + + cmp r2, r12 + movgt r2, r12 + cmp r2, r11 + movlt r2, r11 + mov r2, r2, lsl #1 + strh r2, [r1], #2 + ldrsh r2, [r1, #-2] + + subs r9, r9, #1 + bne case2 + + b doneDecode + +case3: + ldrb r4, [r0], #1 + and r5, r10, r4, lsl #1 + ldrsh r5, [r8, r5] + and r4, r10, r4, lsr #3 + ldrsh r4, [r8, r4] + + @ Sample 1 + add r6, r3, r3, asr #1 + mov r6, r6, asr #4 + sub r6, r6, r3, asr #1 + mov r3, r2 + add r7, r2, r2, lsl #2 + add r7, r7, r2, lsl #3 + rsb r7, r7, #0 + add r6, r6, r7, asr #7 + add r6, r6, r2 + add r2, r4, r6 + + cmp r2, r12 + movgt r2, r12 + cmp r2, r11 + movlt r2, r11 + mov r2, r2, lsl #1 + strh r2, [r1], #2 + ldrsh r2, [r1, #-2] + + @ Sample 2 + add r6, r3, r3, asr #1 + mov r6, r6, asr #4 + sub r6, r6, r3, asr #1 + mov r3, r2 + add r7, r2, r2, lsl #2 + add r7, r7, r2, lsl #3 + rsb r7, r7, #0 + add r6, r6, r7, asr #7 + add r6, r6, r2 + add r2, r5, r6 + + cmp r2, r12 + movgt r2, r12 + cmp r2, r11 + movlt r2, r11 + mov r2, r2, lsl #1 + strh r2, [r1], #2 + ldrsh r2, [r1, #-2] + + subs r9, r9, #1 + bne case3 + +doneDecode: +/* sub r1, r1, #32 + ldmia r1, {r4-r11} + ldmfd sp!, {r1} + stmia r1, {r4-r11}*/ + +doneDecodeCached: + @ Store r2 and r3 + strh r2, [r14, #62] + strh r3, [r14, #64] + + ldmfd sp!, {r4-r12,r14} + bx lr + +#define ENVSTATE_INCREASE 6 +#define ENVSTATE_BENTLINE 7 +#define ENVSTATE_DECREASE 8 +#define ENVSTATE_DECEXP 9 + +@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@ Function called with: +@ r0 - int Number of samples to mix +@ r1 - u16* mix buffer (left first, right is always 4000 * 4 bytes ahead +@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + +#define PREVDECODE_OFFSET 16 +#define BLOCKPOS_OFFSET 66 +#define KEYWAIT_OFFSET 76 + +@ r0 - channel structure base +@ r1 - mix buffer +@ r2 - echo buffer ptr +@ r3 - numSamples +@ r4 - sampleSpeed +@ r5 - samplePos +@ r6 - envCount +@ r7 - envSpeed +@ r8 - sampleValue (value of the current sample) +@ r9 - tmp +@ r10 - leftCalcVol +@ r11 - rightCalcVol +@ r12 - tmp +@ r13 - tmp +@ r14 - tmp + +.GLOBAL DspMixSamplesStereo +.FUNC DspMixSamplesStereo +DspMixSamplesStereo: + stmfd sp!, {r4-r12, lr} + + mov r3, #0 + strb r3, channelNum + str r0, numSamples + + @ Store the original mix buffer for use later + stmfd sp!, {r1} + + @ Clear the left and right mix buffers, saving their initial positions + ldr r1, =r1 + ldr r2, =echoBuffer + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 +clearLoop: + stmia r1!, {r3-r6} + stmia r1!, {r3-r6} + stmia r2!, {r3-r6} + stmia r2!, {r3-r6} + subs r0, r0, #4 + cmp r0, #0 + bgt clearLoop + + @ Load the initial mix buffer and echo position + ldr r1, =r1 + ldr r2, =echoBuffer + + ldr r0, =channels +channelLoopback: + @ Check if active == 0, then next + ldrb r3, [r0, #77] + cmps r3, #0 + beq nextChannelNothingDone + + @ Save the start position of the mix buffer & echo buffer + stmfd sp!, {r1,r2} + + @ Get echo enabled, then replace the opcode there if it's enabled + ldrb r14, [r0, #79] + cmp r14, #1 + ldr r3, =0x01A00000 @ mov r0, r0 + streq r3, branchLocation + + ldrb r3, numSamples + @ Load the important variables into registers + ldmia r0, {r4-r7} + ldrsh r10, [r0, #68] + ldrsh r11, [r0, #70] + +mixLoopback: + + @ Commence the mixing + subs r6, r6, r7 + bpl noEnvelopeUpdate + + @ Update envelope + mov r6, #0x7800 + + ldrsh r9, [r0, #60] + ldrb r12, [r0, #72] + + ldr pc, [pc, r12, lsl #2] + nop +@ Jump table for envelope handling +.word noEnvelopeUpdate +.word envStateAttack +.word envStateDecay +.word envStateSustain +.word envStateRelease +.word noEnvelopeUpdate @ Actually direct, but we don't need to do anything +.word envStateIncrease +.word envStateBentline +.word envStateDecrease +.word envStateSustain @ Actually decrease exponential, but it's the same code + +envStateAttack: + add r9, r9, #4 << 8 + + cmp r9, #0x7f00 + ble storeEnvx + @ envx = 0x7f, state = decay, speed = decaySpeed + mov r9, #0x7f00 + mov r12, #2 + strb r12, [r0, #72] + ldrh r7, [r0, #56] + b storeEnvx + +envStateDecay: + rsb r9, r9, r9, lsl #8 + mov r9, r9, asr #8 + + ldrb r12, [r0, #73] + cmp r9, r12, lsl #8 + bge storeEnvx + @ state = sustain, speed = sustainSpeed + mov r12, #3 + strb r12, [r0, #72] + ldrh r7, [r0, #58] + + @ Make sure envx > 0 + cmp r9, #0 + bge storeEnvx + + @ If not, end channel, then go to next channel + stmfd sp!, {r0-r3, r14} + ldrb r0, channelNum + bl DspSetEndOfSample + ldmfd sp!, {r0-r3, r14} + b nextChannel + +envStateSustain: + rsb r9, r9, r9, lsl #8 + mov r9, r9, asr #8 + + @ Make sure envx > 0 + cmp r9, #0 + bge storeEnvx + + @ If not, end channel, then go to next channel + stmfd sp!, {r0-r3,r14} + ldrb r0, channelNum + bl DspSetEndOfSample + ldmfd sp!, {r0-r3,r14} + b nextChannel + +envStateRelease: + sub r9, r9, #1 << 8 + + @ Make sure envx > 0 + cmp r9, #0 + bge storeEnvx + + @ If not, end channel, then go to next channel + stmfd sp!, {r0-r3,r14} + ldrb r0, channelNum + bl DspSetEndOfSample + ldmfd sp!, {r0-r3,r14} + b nextChannel + +envStateIncrease: + add r9, r9, #4 << 8 + + cmp r9, #0x7f00 + ble storeEnvx + @ envx = 0x7f, state = direct, speed = 0 + mov r9, #0x7f00 + mov r12, #5 + strb r12, [r0, #72] + mov r7, #0 + b storeEnvx + +envStateBentline: + cmp r9, #0x5f << 8 + addgt r9, r9, #1 << 8 + addle r9, r9, #4 << 8 + + cmp r9, #0x7f00 + blt storeEnvx + @ envx = 0x7f, state = direct, speed = 0 + mov r9, #0x7f00 + mov r12, #5 + strb r12, [r0, #72] + mov r7, #0 + b storeEnvx + +envStateDecrease: + sub r9, r9, #4 << 8 + + @ Make sure envx > 0 + cmp r9, #0 + bge storeEnvx + + @ If not, end channel, then go to next channel + stmfd sp!, {r0-r3,r14} + ldrb r0, channelNum + bl DspSetEndOfSample + ldmfd sp!, {r0-r3,r14} + b nextChannel + +storeEnvx: + strh r9, [r0, #60] + + @ Recalculate leftCalcVol and rightCalcVol + ldrsb r10, [r0, #74] + mul r10, r9, r10 + mov r10, r10, asr #7 + + ldrsb r11, [r0, #75] + mul r11, r9, r11 + mov r11, r11, asr #7 + +noEnvelopeUpdate: + add r5, r5, r4 + cmp r5, #16 << 12 + blo noSampleUpdate + + @ Decode next 16 bytes... + sub r5, r5, #16 << 12 + + @ Decode the sample block, r0 = DspChannel* + stmfd sp!, {r0-r3, r14} + bl DecodeSampleBlock + cmps r0, #1 + ldmfd sp!, {r0-r3, r14} + beq nextChannel + +noSampleUpdate: + @ This is really a >> 12 then << 1, but since samplePos bit 0 will never be set, it's safe. + @ Must ensure that sampleSpeed bit 0 is never set, and samplePos is never set to anything but 0 + @ TODO - The speed up hack doesn't work. Find out why + mov r12, r5, lsr #12 + add r12, r0, r12, lsl #1 + ldrsh r8, [r12, #24] + +branchLocation: + b mixEchoDisabled + +mixEchoEnabled: + @ Echo mixing + ldr r9, [r2] + mla r9, r8, r10, r9 + str r9, [r2], #4 + + ldr r9, [r2] + mla r9, r8, r11, r9 + str r9, [r2], #4 + +mixEchoDisabled: + ldr r9, [r1] + mla r9, r8, r10, r9 + str r9, [r1], #4 + + ldr r9, [r1] + mla r9, r8, r11, r9 + str r9, [r1], #4 + + subs r3, r3, #1 + bne mixLoopback + +nextChannel: + + @ Set ENVX and OUTX + ldrb r3, channelNum + ldr r12, =DSP_MEM + add r12, r12, r3, lsl #4 + + @ Set ENVX + ldrsh r9, [r0, #60] + mov r9, r9, asr #8 + strb r9, [r12, #0x8] + + @ Set OUTX + mul r9, r8, r9 + mov r9, r9, asr #15 + strb r9, [r12, #0x9] + + strh r10, [r0, #68] + strh r11, [r0, #70] + + @ Store changing values + stmia r0, {r4-r7} + + @ Reload mix&echo buffer position + ldmfd sp!, {r1,r2} + +nextChannelNothingDone: + @ Move to next channel + add r0, r0, #80 + + @ Increment channelNum + ldrb r3, channelNum + add r3, r3, #1 + strb r3, channelNum + cmps r3, #8 + blt channelLoopback + +@ This is the end of normal mixing + +#ifdef NEVER + @ Store the original mix & echo buffers, cause we trash these regs + stmfd sp!, {r1, r2} + + @ r0 - + @ r1 - + @ r2 - + @ r3 - + @ r4 - + @ r5 - echo volume (right) + @ r6 - numSamples + @ r7 - echo in apu ram (r/w) + @ r8 - echo mix buffer (r/w) + @ r9 - end of echo in apu ram + @ r10 - echo volume (left) + @ r11 - echo feedback + @ r12 - FIR coefficients in DSP ram + @ r13 - FIR table base + @ r14 - FIR offset + +@ Process the echo filter stuff +echoMixSetup: + mov r8, r2 + + ldr r0, =DSP_MEM + + ldrsb r10, [r0, #0x2C] @ Get left echo volume + mov r10, r10, lsl #7 + ldrsb r5, [r0, #0x3C] @ Get right echo volume + mov r5, r5, lsl #7 + + @ Get echo feedback + ldrsb r11, [r0, #0x0D] + + @ Check if echo is enabled + ldrb r1, [r0, #0x6C] + strb r1, echoEnabled + @ Get echo base (APU_MEM + DSP_ESA << 8) + ldr r7, =echoBase + ldr r7, [r7] + str r7, echoBufferStart + @ Set up end of echo delay area in r8 + ldr r0, =echoDelay + ldrh r0, [r0] + add r9, r7, r0 + + @ Set up current echo cursor location + ldr r0, =echoCursor + ldrh r0, [r0] + add r7, r7, r0 + +@ str r13, tmpSp + + ldr r14, =firOffset + ldrb r14, [r14] + + @ Offset firTable to start at FIR #7 + ldr r12, =DSP_MEM + add r12, r12, #0x7F + + ldr r6, numSamples + +echoMixLoopback: + @ Load the old echo value (l,r) + ldrsh r0, [r7] + ldrsh r1, [r7, #2] + +/* @ Increment and wrap firOffset + add r14, r14, #2 + and r14, r14, #(8 * 2) - 1 + + @ Get &firTable[firOffset + 8] into r13 + ldr r13, =firTable + ((8 * 2) * 4) + add r13, r13, r14, lsl #2 + + @ Store the computed samples in the FIR ring buffer + str r0, [r13] + str r1, [r13, #4] + str r0, [r13, #-8 * 2 * 4] + str r1, [r13, #(-8 * 2 * 4) + 4] + + @ Process FIR sample 0 (special) + ldr r2, [r13], #4 + ldr r3, [r13], #-12 + ldrsb r4, [r12], #-0x10 + mul r0, r2, r4 + mul r1, r3, r4 + +.MACRO processFir + ldr r2, [r13], #4 + ldr r3, [r13], #-12 + ldrsb r4, [r12], #-0x10 + mla r0, r2, r4, r0 + mla r1, r3, r4, r1 +.ENDM + processFir + processFir + processFir + processFir + processFir + processFir + + @ Last FIR sample (special) + ldr r2, [r13], #4 + ldr r3, [r13], #-12 + ldrsb r4, [r12], #0x70 + + mla r0, r2, r4, r0 + mla r1, r3, r4, r1 + + @ Get rid of volume multiplication stuff + mov r0, r0, asr #7 + mov r1, r1, asr #7*/ + + @ r0,r1 contains the filtered samples + ldr r2, [r8] + @ Left channel = (feedback * filtered) >> 7 + mla r2, r11, r0, r2 + mov r2, r2, asr #15 + + ldr r3, [r8, #4] + @ Right channel = (feedback * filtered) >> 7 + mla r3, r11, r1, r3 + mov r3, r3, asr #15 + + @ Store (filtered * echoFB) + echobuffer into echobuffer + ldrb r5, echoEnabled + tst r5, #0x20 + streqh r2, [r7], #2 + streqh r3, [r7], #2 + cmp r7, r9 + ldrge r7, echoBufferStart + + @ Store (filtered * echoVol) into echomix + mul r2, r10, r0 + str r2, [r8], #4 + mul r2, r5, r1 + str r2, [r8], #4 + + subs r6, r6, #1 + bne echoMixLoopback + +doneEchoMix: + +/* ldr r13, tmpSp + + @ Store changed values + ldr r0, =firOffset + strb r14, [r0]*/ + + ldr r3, echoBufferStart + sub r7, r7, r3 + ldr r0, =echoCursor + strh r7, [r0] + + @ Reload mix buffer & echo positions + ldmfd sp!, {r1, r2} + +#endif + +clipAndMix: + @ Put the original output buffer into r3 + ldmfd sp!, {r3} + + @ Set up the preamp & overall volume + ldr r8, =dspPreamp + ldrh r8, [r8] + + ldr r9, =DSP_MEM + ldrsb r4, [r9, #0x0C] @ Main left volume + ldrsb r6, [r9, #0x1C] @ Main right volume + + mul r4, r8, r4 + mov r4, r4, asr #7 + mul r6, r8, r6 + mov r6, r6, asr #7 + + @ r0 - numSamples + @ r1 - mix buffer + @ r2 - echo buffer + @ r3 - output buffer + @ r4 - left volume + @ r5 - TMP (assigned to sample value) + @ r6 - right volume + @ r7 - TMP + @ r8 - preamp + @ r9 - + @ r10 - + @ r11 - + @ r12 - + @ r14 - + + @ Do volume multiplication, mix in echo buffer and clipping here + ldr r0, numSamples + +mixClipLoop: + @ Load and scale by volume (LEFT) + ldr r5, [r1], #4 + mov r5, r5, asr #15 + mul r5, r4, r5 + ldr r7, [r2], #4 + add r5, r5, r7, asr #7 + mov r5, r5, asr #7 + + @ Clip and store + cmp r5, #0x7f00 + movgt r5, #0x7f00 + cmn r5, #0x7f00 + movlt r5, #0x8100 + strh r5, [r3] + add r3, r3, #4000 * 4 + + @ Load and scale by volume (RIGHT) + ldr r5, [r1], #4 + mov r5, r5, asr #15 + mul r5, r6, r5 + ldr r7, [r2], #4 + add r5, r5, r7, asr #7 + mov r5, r5, asr #7 + + @ Clip and store + cmp r5, #0x7f00 + movgt r5, #0x7f00 + cmn r5, #0x7f00 + movlt r5, #0x8100 + strh r5, [r3], #2 + sub r3, r3, #4000 * 4 + + subs r0, r0, #1 + bne mixClipLoop + +doneMix: + ldmfd sp!, {r4-r12, lr} + bx lr +.ENDFUNC + +.GLOBAL channelNum + +tmpSp: +.word 0 +echoBufferStart: +.word 0 +numSamples: +.word 0 +channelNum: +.byte 0 +echoEnabled: +.byte 0 + +.align +.pool diff --git a/src/font.h b/src/font.h new file mode 100644 index 0000000..8fde4c2 --- /dev/null +++ b/src/font.h @@ -0,0 +1,99 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +static char *font[] = { +" . . . . .. . . ", +" .#. .#.#. . . ... .#. . . .##. .#. .#. . . . . ", +" .#. .#.#. .#.#. .###. .#..#. .#. .#. .#. .#. .#.#. .#. .#. ", +" .#. .#.#. .#####. .#.#. ..#. .#.#. .#. .#. .#. .#. ..#.. .... .#. ", +" .#. . . .#.#. .###. .#.. .#. . .#. .#. .###. .#####. .. .####. .. .#. ", +" . .#####. .#.#. .#..#. .#.#. .#. .#. .#. ..#.. .##. .... .##. .#. ", +" .#. .#.#. .###. . .#. .#.#. .#. .#. .#.#. .#. .#. .##. . ", +" . . . ... . . . . . . . . .#. .. ", +" . ", +" . . .. .... . .... .. .... .. .. . ", +" .#. .#. .##. .####. .#. .####. .##. .####. .##. .##. .. .. . . .#. ", +".#.#. .##. .#..#. ...#. .##. .#... .#.. ...#. .#..#. .#..#. .##. .##. .#. .... .#. .#.#. ", +".#.#. .#. . .#. .##. .#.#. .###. .###. .#. .##. .#..#. .##. .##. .#. .####. .#. ..#. ", +".#.#. .#. .#. ...#. .####. ...#. .#..#. .#. .#..#. .###. .. .. .#. .... .#. .#. ", +".#.#. .#. .#.. .#..#. ..#. .#..#. .#..#. .#. .#..#. ..#. .##. .##. .#. .####. .#. . ", +" .#. .###. .####. .##. .#. .##. .##. .#. .##. .##. .##. .#. .#. .... .#. .#. ", +" . ... .... .. . .. .. . .. .. .. .#. . . . ", +" . ", +" .. .. ... .. ... .... .... .. . . ... . . . . . . . . .. ", +" .##. .##. .###. .##. .###. .####. .####. .##. .#..#. .###. .#. .#..#. .#. .#. .#. .#. .#. .##. ", +".#..#. .#..#. .#..#. .#..#. .#..#. .#... .#... .#..#. .#..#. .#. .#. .#.#. .#. .##.##. .##..#. .#..#. ", +".#.##. .#..#. .###. .#. . .#..#. .###. .###. .#... .####. .#. .#. .##. .#. .#.#.#. .#.#.#. .#..#. ", +".#.##. .####. .#..#. .#. . .#..#. .#.. .#.. .#.##. .#..#. .#. . .#. .##. .#. .#...#. .#.#.#. .#..#. ", +".#... .#..#. .#..#. .#..#. .#..#. .#... .#. .#..#. .#..#. .#. .#..#. .#.#. .#... .#. .#. .#..##. .#..#. ", +" .##. .#..#. .###. .##. .###. .####. .#. .###. .#..#. .###. .##. .#..#. .####. .#. .#. .#. .#. .##. ", +" .. . . ... .. ... .... . ... . . ... .. . . .... . . . . .. ", +" ", +" ... .. ... .. ... . . . . . . . . . . .... ... ... . ", +".###. .##. .###. .##. .###. .#. .#. .#. .#. .#. .#. .#..#. .#.#. .####. .###. . .###. .#. ", +".#..#. .#..#. .#..#. .#..#. .#. .#. .#. .#. .#. .#...#. .#..#. .#.#. ...#. .#.. .#. ..#. .#.#. ", +".#..#. .#..#. .#..#. .#.. .#. .#. .#. .#. .#. .#.#.#. .##. .#.#. .#. .#. .#. .#. . . ", +".###. .#..#. .###. ..#. .#. .#. .#. .#. .#. .#.#.#. .#..#. .#. .#. .#. .#. .#. ", +".#.. .##.#. .#.#. .#..#. .#. .#...#. .#.#. .##.##. .#..#. .#. .#... .#.. .#. ..#. .... ", +".#. .##. .#..#. .##. .#. .###. .#. .#. .#. .#..#. .#. .####. .###. . .###. .####. ", +" . ..#. . . .. . ... . . . . . . .... ... ... .... ", +" . ", +" .. . . . . . . . .. ", +".##. .#. .#. .#. .#. .#. .#. .#. .##. ", +" .#. ... .#.. .. ..#. .. .#.#. ... .#.. .. . .#.. .#. .. .. ... .. ", +" .#. .###. .###. .##. .###. .##. .#.. .###. .###. .##. .#. .#.#. .#. .##.##. .###. .##. ", +" . .#..#. .#..#. .#.. .#..#. .#.##. .###. .#..#. .#..#. .#. .#. .##. .#. .#.#.#. .#..#. .#..#. ", +" .#.##. .#..#. .#.. .#..#. .##.. .#. .##. .#..#. .#. ..#. .#.#. .#. .#...#. .#..#. .#..#. ", +" .#.#. .###. .##. .###. .##. .#. .#... .#..#. .###. .#.#. .#..#. .###. .#. .#. .#..#. .##. ", +" . . ... .. ... .. . .###. . . ... .#. . . ... . . . . .. ", +" ... . ", +" . . . . . . ", +" .#. .#. .#. .#. .#.#. ", +" ... ... ... ... .#. . . . . . . . . . . .... .#. .#. .#. .#.#. ", +".###. .###. .###. .###. .###. .#..#. .#.#. .#...#. .#..#. .#..#. .####. .##. .#. .##. . . ", +".#..#. .#..#. .#..#. .##.. .#. .#..#. .#.#. .#.#.#. .##. .#..#. ..#. .#. .#. .#. ", +".#..#. .#..#. .#. . ..##. .#.. .#..#. .#.#. .#.#.#. .##. .#.#. .#.. .#. .#. .#. ", +".###. .###. .#. .###. .##. .###. .#. .#.#. .#..#. .#. .####. .#. .#. .#. ", +".#.. ..#. . ... .. ... . . . . . .#. .... . . . ", +" . . . ", +}; + +static int font_width = 8; +static int font_height = 9; diff --git a/src/frame_skip.cpp b/src/frame_skip.cpp new file mode 100644 index 0000000..d656a0d --- /dev/null +++ b/src/frame_skip.cpp @@ -0,0 +1,99 @@ +#include +#include +#include +#include +#include "frame_skip.h" +#include "memmap.h" + +#ifndef uclock_t +#define uclock_t unsigned int +#endif + +#define TICKS_PER_SEC 1000000UL +//#define CPU_FPS 60 +static int CPU_FPS=60; +static uclock_t F; + +#define MAX_FRAMESKIP 10 + + +static char init_frame_skip = 1; +char skip_next_frame = 0; +static struct timeval init_tv = { 0, 0 }; + + +void reset_frame_skip(void) +{ + //static Uint8 init=0; + + init_tv.tv_usec = 0; + init_tv.tv_sec = 0; + skip_next_frame = 0; + init_frame_skip = 1; + CPU_FPS=Memory.ROMFramesPerSecond; + + F = (uclock_t) ((double) TICKS_PER_SEC / CPU_FPS); +} + +uclock_t get_ticks(void) +{ + struct timeval tv; + + gettimeofday(&tv, 0); + if (init_tv.tv_sec == 0) + init_tv = tv; + return (tv.tv_sec - init_tv.tv_sec) * TICKS_PER_SEC + tv.tv_usec - + init_tv.tv_usec; + + +} + +int frame_skip(void) +{ + static int f2skip; + static uclock_t sec = 0; + static uclock_t rfd; + static uclock_t target; + static int nbFrame = 0; + static int skpFrm = 0; + + if (init_frame_skip) { + init_frame_skip = 0; + target = get_ticks(); + nbFrame = 0; + //f2skip=0; + //skpFrm=0; + sec = 0; + return 0; + } + + target += F; + if (f2skip > 0) { + f2skip--; + skpFrm++; + return 1; + } else + skpFrm = 0; + + + rfd = get_ticks(); + + if (rfd < target && f2skip == 0) { + while (get_ticks() < target); + } else { + f2skip = (rfd - target) / (double) F; + if (f2skip > MAX_FRAMESKIP) { + f2skip = MAX_FRAMESKIP; + reset_frame_skip(); + } + // printf("Skip %d frame(s) %lu %lu\n",f2skip,target,rfd); + } + + + nbFrame++; + if (get_ticks() - sec >= TICKS_PER_SEC) { + nbFrame = 0; + sec = get_ticks(); + } + return 0; +} diff --git a/src/frame_skip.h b/src/frame_skip.h new file mode 100644 index 0000000..0e3627f --- /dev/null +++ b/src/frame_skip.h @@ -0,0 +1,9 @@ +#ifndef _FRAME_SKIP_H +#define _FRAME_SKIP_H + + +void reset_frame_skip(void); +int frame_skip(void); + + +#endif diff --git a/src/fxdbg.cpp b/src/fxdbg.cpp new file mode 100644 index 0000000..71549cb --- /dev/null +++ b/src/fxdbg.cpp @@ -0,0 +1,360 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#include "fxemu.h" +#include "fxinst.h" +#include +#include + +extern const char *fx_apvMnemonicTable[]; +extern struct FxRegs_s GSU; + + +/* + When printing a line from the pipe, it could look like this: + + 01:8006 f4 fb 86 iwt r4,#$86fb + + The values are: + program bank: 01 + adress: 8006 + values at memory address 8006: f4 fb 86 + instruction in the pipe: iwt r4,#$86fb + + Note! If the instruction has more than one byte (like in 'iwt') + and the instruction is in a delay slot, the second and third + byte displayed will not be the same as those used. + Since the instrction is in a delay slot, the first byte + of the instruction will be taken from the pipe at the address + after the branch instruction, and the next one or two bytes + will be taken from the address that the branch points to. + This is a bit complicated, but I've taken this into account, + in this debug function. (See the diffrence of how the values + vPipe1 and vPipe2 are read, compared to the values vByte1 and + vByte2) + + */ +void FxPipeString(char * pvString) +{ + char *p; + uint32 vOpcode = (GSU.vStatusReg & 0x300) | ((uint32)PIPE); + const char *m = fx_apvMnemonicTable[vOpcode]; + uint8 vPipe1,vPipe2,vByte1,vByte2; + uint8 vPipeBank = GSU.vPipeAdr >> 16; + + /* The next two bytes after the pipe's address */ + vPipe1 = GSU.apvRomBank[vPipeBank][USEX16(GSU.vPipeAdr+1)]; + vPipe2 = GSU.apvRomBank[vPipeBank][USEX16(GSU.vPipeAdr+2)]; + + /* The actual next two bytes to be read */ + vByte1 = PRGBANK(USEX16(R15)); + vByte2 = PRGBANK(USEX16(R15+1)); + + /* Print ROM address of the pipe */ + sprintf(pvString, "%02x:%04x %02x ", + USEX8(vPipeBank), USEX16(GSU.vPipeAdr), USEX8(PIPE)); + p = &pvString[strlen(pvString)]; + + /* Check if it's a branch instruction */ + if( PIPE >= 0x05 && PIPE <= 0x0f ) + { + sprintf(&pvString[11], "%02x ", USEX8(vPipe1)); +#ifdef BRANCH_DELAY_RELATIVE + sprintf(p, m, USEX16(R15 + SEX8(vByte1) + 1 ) ); +#else + sprintf(p, m, USEX16(R15 + SEX8(vByte1) - 1 ) ); +#endif + } + /* Check for 'move' instruction */ + else if( PIPE >= 0x10 && PIPE <= 0x1f && TF(B) ) + sprintf(p, "move r%d,r%d", USEX8(PIPE & 0x0f), GSU.pvSreg - GSU.avReg); + /* Check for 'ibt', 'lms' or 'sms' */ + else if( PIPE >= 0xa0 && PIPE <= 0xaf ) + { + sprintf(&pvString[11], "%02x ", USEX8(vPipe1)); + if( (GSU.vStatusReg & 0x300) == 0x100 || (GSU.vStatusReg & 0x300) == 0x200 ) + sprintf(p, m, USEX16(vByte1) << 1 ); + else + sprintf(p, m, USEX16(vByte1) ); + } + /* Check for 'moves' */ + else if( PIPE >= 0xb0 && PIPE <= 0xbf && TF(B) ) + sprintf(p, "moves r%d,r%d", GSU.pvDreg - GSU.avReg, USEX8(PIPE & 0x0f) ); + /* Check for 'iwt', 'lm' or 'sm' */ + else if( PIPE >= 0xf0 ) + { + sprintf(&pvString[11], "%02x %02x ", USEX8(vPipe1), USEX8(vPipe2)); + sprintf(p, m, USEX8(vByte1) | (USEX16(vByte2)<<8) ); + } + /* Normal instruction */ + else + strcpy(p, m); +} + +const char *fx_apvMnemonicTable[] = +{ + /* + * ALT0 Table + */ + /* 00 - 0f */ + "stop", "nop", "cache", "lsr", "rol", "bra $%04x","blt $%04x","bge $%04x", + "bne $%04x","beq $%04x","bpl $%04x","bmi $%04x","bcc $%04x","bcs $%04x","bvc $%04x","bvs $%04x", + /* 10 - 1f */ + "to r0", "to r1", "to r2", "to r3", "to r4", "to r5", "to r6", "to r7", + "to r8", "to r9", "to r10", "to r11", "to r12", "to r13", "to r14", "to r15", + /* 20 - 2f */ + "with r0", "with r1", "with r2", "with r3", "with r4", "with r5", "with r6", "with r7", + "with r8", "with r9", "with r10", "with r11", "with r12", "with r13", "with r14", "with r15", + /* 30 - 3f */ + "stw (r0)","stw (r1)","stw (r2)", "stw (r3)", "stw (r4)", "stw (r5)", "stw (r6)", "stw (r7)", + "stw (r8)","stw (r9)","stw (r10)","stw (r11)","loop", "alt1", "alt2", "alt3", + /* 40 - 4f */ + "ldw (r0)","ldw (r1)","ldw (r2)", "ldw (r3)", "ldw (r4)", "ldw (r5)", "ldw (r6)", "ldw (r7)", + "ldw (r8)","ldw (r9)","ldw (r10)","ldw (r11)","plot", "swap", "color", "not", + /* 50 - 5f */ + "add r0", "add r1", "add r2", "add r3", "add r4", "add r5", "add r6", "add r7", + "add r8", "add r9", "add r10", "add r11", "add r12", "add r13", "add r14", "add r15", + /* 60 - 6f */ + "sub r0", "sub r1", "sub r2", "sub r3", "sub r4", "sub r5", "sub r6", "sub r7", + "sub r8", "sub r9", "sub r10", "sub r11", "sub r12", "sub r13", "sub r14", "sub r15", + /* 70 - 7f */ + "merge", "and r1", "and r2", "and r3", "and r4", "and r5", "and r6", "and r7", + "and r8", "and r9", "and r10", "and r11", "and r12", "and r13", "and r14", "and r15", + /* 80 - 8f */ + "mult r0", "mult r1", "mult r2", "mult r3", "mult r4", "mult r5", "mult r6", "mult r7", + "mult r8", "mult r9", "mult r10", "mult r11", "mult r12", "mult r13", "mult r14", "mult r15", + /* 90 - 9f */ + "sbk", "link #1", "link #2", "link #3", "link #4", "sex", "asr", "ror", + "jmp (r8)","jmp (r9)","jmp (r10)","jmp (r11)","jmp (r12)","jmp (r13)","lob", "fmult", + /* a0 - af */ + "ibt r0,#$%02x", "ibt r1,#$%02x", "ibt r2,#$%02x", "ibt r3,#$%02x", + "ibt r4,#$%02x", "ibt r5,#$%02x", "ibt r6,#$%02x", "ibt r7,#$%02x", + "ibt r8,#$%02x", "ibt r9,#$%02x", "ibt r10,#$%02x", "ibt r11,#$%02x", + "ibt r12,#$%02x", "ibt r13,#$%02x", "ibt r14,#$%02x", "ibt r15,#$%02x", + /* b0 - bf */ + "from r0", "from r1", "from r2", "from r3", "from r4", "from r5", "from r6", "from r7", + "from r8", "from r9", "from r10", "from r11", "from r12", "from r13", "from r14", "from r15", + /* c0 - cf */ + "hib", "or r1", "or r2", "or r3", "or r4", "or r5", "or r6", "or r7", + "or r8", "or r9", "or r10", "or r11", "or r12", "or r13", "or r14", "or r15", + /* d0 - df */ + "inc r0", "inc r1", "inc r2", "inc r3", "inc r4", "inc r5", "inc r6", "inc r7", + "inc r8", "inc r9", "inc r10", "inc r11", "inc r12", "inc r13", "inc r14", "getc", + /* e0 - ef */ + "dec r0", "dec r1", "dec r2", "dec r3", "dec r4", "dec r5", "dec r6", "dec r7", + "dec r8", "dec r9", "dec r10", "dec r11", "dec r12", "dec r13", "dec r14", "getb", + /* f0 - ff */ + "iwt r0,#$%04x", "iwt r1,#$%04x", "iwt r2,#$%04x", "iwt r3,#$%04x", + "iwt r4,#$%04x", "iwt r5,#$%04x", "iwt r6,#$%04x", "iwt r7,#$%04x", + "iwt r8,#$%04x", "iwt r9,#$%04x", "iwt r10,#$%04x", "iwt r11,#$%04x", + "iwt r12,#$%04x", "iwt r13,#$%04x", "iwt r14,#$%04x", "iwt r15,#$%04x", + + /* + * ALT1 Table + */ + + /* 00 - 0f */ + "stop", "nop", "cache", "lsr", "rol", "bra $%04x","blt $%04x","bge $%04x", + "bne $%04x","beq $%04x","bpl $%04x","bmi $%04x","bcc $%04x","bcs $%04x","bvc $%04x","bvs $%04x", + /* 10 - 1f */ + "to r0", "to r1", "to r2", "to r3", "to r4", "to r5", "to r6", "to r7", + "to r8", "to r9", "to r10", "to r11", "to r12", "to r13", "to r14", "to r15", + /* 20 - 2f */ + "with r0", "with r1", "with r2", "with r3", "with r4", "with r5", "with r6", "with r7", + "with r8", "with r9", "with r10", "with r11", "with r12", "with r13", "with r14", "with r15", + /* 30 - 3f */ + "stb (r0)","stb (r1)","stb (r2)", "stb (r3)", "stb (r4)", "stb (r5)", "stb (r6)", "stb (r7)", + "stb (r8)","stb (r9)","stb (r10)","stb (r11)","loop", "alt1", "alt2", "alt3", + /* 40 - 4f */ + "ldb (r0)","ldb (r1)","ldb (r2)", "ldb (r3)", "ldb (r4)", "ldb (r5)", "ldb (r6)", "ldb (r7)", + "ldb (r8)","ldb (r9)","ldb (r10)","ldb (r11)","rpix", "swap", "cmode", "not", + /* 50 - 5f */ + "adc r0", "adc r1", "adc r2", "adc r3", "adc r4", "adc r5", "adc r6", "adc r7", + "adc r8", "adc r9", "adc r10", "adc r11", "adc r12", "adc r13", "adc r14", "adc r15", + /* 60 - 6f */ + "sbc r0", "sbc r1", "sbc r2", "sbc r3", "sbc r4", "sbc r5", "sbc r6", "sbc r7", + "sbc r8", "sbc r9", "sbc r10", "sbc r11", "sbc r12", "sbc r13", "sbc r14", "sbc r15", + /* 70 - 7f */ + "merge", "bic r1", "bic r2", "bic r3", "bic r4", "bic r5", "bic r6", "bic r7", + "bic r8", "bic r9", "bic r10", "bic r11", "bic r12", "bic r13", "bic r14", "bic r15", + /* 80 - 8f */ + "umult r0","umult r1","umult r2", "umult r3", "umult r4", "umult r5", "umult r6", "umult r7", + "umult r8","umult r9","umult r10","umult r11","umult r12","umult r13","umult r14","umult r15", + /* 90 - 9f */ + "sbk", "link #1", "link #2", "link #3", "link #4", "sex", "div2", "ror", + "ljmp (r8)","ljmp (r9)","ljmp (r10)","ljmp (r11)", "ljmp (r12)", "ljmp (r13)", "lob", "lmult", + /* a0 - af */ + "lms r0,($%04x)", "lms r1,($%04x)", "lms r2,($%04x)", "lms r3,($%04x)", + "lms r4,($%04x)", "lms r5,($%04x)", "lms r6,($%04x)", "lms r7,($%04x)", + "lms r8,($%04x)", "lms r9,($%04x)", "lms r10,($%04x)", "lms r11,($%04x)", + "lms r12,($%04x)", "lms r13,($%04x)", "lms r14,($%04x)", "lms r15,($%04x)", + /* b0 - bf */ + "from r0", "from r1", "from r2", "from r3", "from r4", "from r5", "from r6", "from r7", + "from r8", "from r9", "from r10", "from r11", "from r12", "from r13", "from r14", "from r15", + /* c0 - cf */ + "hib", "xor r1", "xor r2", "xor r3", "xor r4", "xor r5", "xor r6", "xor r7", + "xor r8", "xor r9", "xor r10", "xor r11", "xor r12", "xor r13", "xor r14", "xor r15", + /* d0 - df */ + "inc r0", "inc r1", "inc r2", "inc r3", "inc r4", "inc r5", "inc r6", "inc r7", + "inc r8", "inc r9", "inc r10", "inc r11", "inc r12", "inc r13", "inc r14", "getc", + /* e0 - ef */ + "dec r0", "dec r1", "dec r2", "dec r3", "dec r4", "dec r5", "dec r6", "dec r7", + "dec r8", "dec r9", "dec r10", "dec r11", "dec r12", "dec r13", "dec r14", "getbh", + /* f0 - ff */ + "lm r0,($%04x)", "lm r1,($%04x)", "lm r2,($%04x)", "lm r3,($%04x)", + "lm r4,($%04x)", "lm r5,($%04x)", "lm r6,($%04x)", "lm r7,($%04x)", + "lm r8,($%04x)", "lm r9,($%04x)", "lm r10,($%04x)", "lm r11,($%04x)", + "lm r12,($%04x)", "lm r13,($%04x)", "lm r14,($%04x)", "lm r15,($%04x)", + + /* + * ALT2 Table + */ + + /* 00 - 0f */ + "stop", "nop", "cache", "lsr", "rol", "bra $%04x","blt $%04x","bge $%04x", + "bne $%04x","beq $%04x","bpl $%04x","bmi $%04x","bcc $%04x","bcs $%04x","bvc $%04x","bvs $%04x", + /* 10 - 1f */ + "to r0", "to r1", "to r2", "to r3", "to r4", "to r5", "to r6", "to r7", + "to r8", "to r9", "to r10", "to r11", "to r12", "to r13", "to r14", "to r15", + /* 20 - 2f */ + "with r0", "with r1", "with r2", "with r3", "with r4", "with r5", "with r6", "with r7", + "with r8", "with r9", "with r10", "with r11", "with r12", "with r13", "with r14", "with r15", + /* 30 - 3f */ + "stw (r0)","stw (r1)","stw (r2)", "stw (r3)", "stw (r4)", "stw (r5)", "stw (r6)", "stw (r7)", + "stw (r8)","stw (r9)","stw (r10)","stw (r11)","loop", "alt1", "alt2", "alt3", + /* 40 - 4f */ + "ldw (r0)","ldw (r1)","ldw (r2)", "ldw (r3)", "ldw (r4)", "ldw (r5)", "ldw (r6)", "ldw (r7)", + "ldw (r8)","ldw (r9)","ldw (r10)","ldw (r11)","plot", "swap", "color", "not", + /* 50 - 5f */ + "add #0", "add #1", "add #2", "add #3", "add #4", "add #5", "add #6", "add #7", + "add #8", "add #9", "add #10", "add #11", "add #12", "add #13", "add #14", "add #15", + /* 60 - 6f */ + "sub #0", "sub #1", "sub #2", "sub #3", "sub #4", "sub #5", "sub #6", "sub #7", + "sub #8", "sub #9", "sub #10", "sub #11", "sub #12", "sub #13", "sub #14", "sub #15", + /* 70 - 7f */ + "merge", "and #1", "and #2", "and #3", "and #4", "and #5", "and #6", "and #7", + "and #8", "and #9", "and #10", "and #11", "and #12", "and #13", "and #14", "and #15", + /* 80 - 8f */ + "mult #0", "mult #1", "mult #2", "mult #3", "mult #4", "mult #5", "mult #6", "mult #7", + "mult #8", "mult #9", "mult #10", "mult #11", "mult #12", "mult #13", "mult #14", "mult #15", + /* 90 - 9f */ + "sbk", "link #1", "link #2", "link #3", "link #4", "sex", "asr", "ror", + "jmp (r8)","jmp (r9)","jmp (r10)","jmp (r11)","jmp (r12)","jmp (r13)","lob", "fmult", + /* a0 - af */ + "sms ($%04x),r0", "sms ($%04x),r1", "sms ($%04x),r2", "sms ($%04x),r3", + "sms ($%04x),r4", "sms ($%04x),r5", "sms ($%04x),r6", "sms ($%04x),r7", + "sms ($%04x),r8", "sms ($%04x),r9", "sms ($%04x),r10", "sms ($%04x),r11", + "sms ($%04x),r12", "sms ($%04x),r13", "sms ($%04x),r14", "sms ($%04x),r15", + /* b0 - bf */ + "from r0", "from r1", "from r2", "from r3", "from r4", "from r5", "from r6", "from r7", + "from r8", "from r9", "from r10", "from r11", "from r12", "from r13", "from r14", "from r15", + /* c0 - cf */ + "hib", "or #1", "or #2", "or #3", "or #4", "or #5", "or #6", "or #7", + "or #8", "or #9", "or #10", "or #11", "or #12", "or #13", "or #14", "or #15", + /* d0 - df */ + "inc r0", "inc r1", "inc r2", "inc r3", "inc r4", "inc r5", "inc r6", "inc r7", + "inc r8", "inc r9", "inc r10", "inc r11", "inc r12", "inc r13", "inc r14", "ramb", + /* e0 - ef */ + "dec r0", "dec r1", "dec r2", "dec r3", "dec r4", "dec r5", "dec r6", "dec r7", + "dec r8", "dec r9", "dec r10", "dec r11", "dec r12", "dec r13", "dec r14", "getbl", + /* f0 - ff */ + "sm ($%04x),r0", "sm ($%04x),r1", "sm ($%04x),r2", "sm ($%04x),r3", + "sm ($%04x),r4", "sm ($%04x),r5", "sm ($%04x),r6", "sm ($%04x),r7", + "sm ($%04x),r8", "sm ($%04x),r9", "sm ($%04x),r10", "sm ($%04x),r11", + "sm ($%04x),r12", "sm ($%04x),r13", "sm ($%04x),r14", "sm ($%04x),r15", + + /* + * ALT3 Table + */ + + /* 00 - 0f */ + "stop", "nop", "cache", "lsr", "rol", "bra $%04x","blt $%04x","bge $%04x", + "bne $%04x","beq $%04x","bpl $%04x","bmi $%04x","bcc $%04x","bcs $%04x","bvc $%04x","bvs $%04x", + /* 10 - 1f */ + "to r0", "to r1", "to r2", "to r3", "to r4", "to r5", "to r6", "to r7", + "to r8", "to r9", "to r10", "to r11", "to r12", "to r13", "to r14", "to r15", + /* 20 - 2f */ + "with r0", "with r1", "with r2", "with r3", "with r4", "with r5", "with r6", "with r7", + "with r8", "with r9", "with r10", "with r11", "with r12", "with r13", "with r14", "with r15", + /* 30 - 3f */ + "stb (r0)","stb (r1)","stb (r2)", "stb (r3)", "stb (r4)", "stb (r5)", "stb (r6)", "stb (r7)", + "stb (r8)","stb (r9)","stb (r10)","stb (r11)","loop", "alt1", "alt2", "alt3", + /* 40 - 4f */ + "ldb (r0)","ldb (r1)","ldb (r2)", "ldb (r3)", "ldb (r4)", "ldb (r5)", "ldb (r6)", "ldb (r7)", + "ldb (r8)","ldb (r9)","ldb (r10)","ldb (r11)","rpix", "swap", "cmode", "not", + /* 50 - 5f */ + "adc #0", "adc #1", "adc #2", "adc #3", "adc #4", "adc #5", "adc #6", "adc #7", + "adc #8", "adc #9", "adc #10", "adc #11", "adc #12", "adc #13", "adc #14", "adc #15", + /* 60 - 6f */ + "cmp r0", "cmp r1", "cmp r2", "cmp r3", "cmp r4", "cmp r5", "cmp r6", "cmp r7", + "cmp r8", "cmp r9", "cmp r10", "cmp r11", "cmp r12", "cmp r13", "cmp r14", "cmp r15", + /* 70 - 7f */ + "merge", "bic #1", "bic #2", "bic #3", "bic #4", "bic #5", "bic #6", "bic #7", + "bic #8", "bic #9", "bic #10", "bic #11", "bic #12", "bic #13", "bic #14", "bic #15", + /* 80 - 8f */ + "umult #0","umult #1","umult #2", "umult #3", "umult #4", "umult #5", "umult #6", "umult #7", + "umult #8","umult #9","umult #10","umult #11","umult #12","umult #13","umult #14","umult #15", + /* 90 - 9f */ + "sbk", "link #1", "link #2", "link #3", "link #4", "sex", "div2", "ror", + "ljmp (r8)","ljmp (r9)","ljmp (r10)","ljmp (r11)", "ljmp (r12)", "ljmp (r13)", "lob", "lmult", + /* a0 - af */ + "lms r0,($%04x)", "lms r1,($%04x)", "lms r2,($%04x)", "lms r3,($%04x)", + "lms r4,($%04x)", "lms r5,($%04x)", "lms r6,($%04x)", "lms r7,($%04x)", + "lms r8,($%04x)", "lms r9,($%04x)", "lms r10,($%04x)", "lms r11,($%04x)", + "lms r12,($%04x)", "lms r13,($%04x)", "lms r14,($%04x)", "lms r15,($%04x)", + /* b0 - bf */ + "from r0", "from r1", "from r2", "from r3", "from r4", "from r5", "from r6", "from r7", + "from r8", "from r9", "from r10", "from r11", "from r12", "from r13", "from r14", "from r15", + /* c0 - cf */ + "hib", "xor #1", "xor #2", "xor #3", "xor #4", "xor #5", "xor #6", "xor #7", + "xor #8", "xor #9", "xor #10", "xor #11", "xor #12", "xor #13", "xor #14", "xor #15", + /* d0 - df */ + "inc r0", "inc r1", "inc r2", "inc r3", "inc r4", "inc r5", "inc r6", "inc r7", + "inc r8", "inc r9", "inc r10", "inc r11", "inc r12", "inc r13", "inc r14", "romb", + /* e0 - ef */ + "dec r0", "dec r1", "dec r2", "dec r3", "dec r4", "dec r5", "dec r6", "dec r7", + "dec r8", "dec r9", "dec r10", "dec r11", "dec r12", "dec r13", "dec r14", "getbs", + /* f0 - ff */ + "lm r0,($%04x)", "lm r1,($%04x)", "lm r2,($%04x)", "lm r3,($%04x)", + "lm r4,($%04x)", "lm r5,($%04x)", "lm r6,($%04x)", "lm r7,($%04x)", + "lm r8,($%04x)", "lm r9,($%04x)", "lm r10,($%04x)", "lm r11,($%04x)", + "lm r12,($%04x)", "lm r13,($%04x)", "lm r14,($%04x)", "lm r15,($%04x)", +}; diff --git a/src/fxemu.cpp b/src/fxemu.cpp new file mode 100644 index 0000000..b958862 --- /dev/null +++ b/src/fxemu.cpp @@ -0,0 +1,721 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#include "fxemu.h" +#include "fxinst.h" +#include +#include +#include + +/* The FxChip Emulator's internal variables */ +struct FxRegs_s GSU = FxRegs_s_null; + +uint32 (**fx_ppfFunctionTable)(uint32) = 0; +void (**fx_ppfPlotTable)() = 0; +void (**fx_ppfOpcodeTable)() = 0; + +#if 0 +void fx_setCache() +{ + uint32 c; + GSU.bCacheActive = TRUE; + GSU.pvRegisters[0x3e] &= 0xf0; + c = (uint32)GSU.pvRegisters[0x3e]; + c |= ((uint32)GSU.pvRegisters[0x3f])<<8; + if(c == GSU.vCacheBaseReg) + return; + GSU.vCacheBaseReg = c; + GSU.vCacheFlags = 0; + if(c < (0x10000-512)) + { + uint8 const* t = &ROM(c); + memcpy(GSU.pvCache,t,512); + } + else + { + uint8 const* t1; + uint8 const* t2; + uint32 i = 0x10000 - c; + t1 = &ROM(c); + t2 = &ROM(0); + memcpy(GSU.pvCache,t1,i); + memcpy(&GSU.pvCache[i],t2,512-i); + } +} +#endif + +void FxCacheWriteAccess(uint16 vAddress) +{ +#if 0 + if(!GSU.bCacheActive) + { + uint8 v = GSU.pvCache[GSU.pvCache[vAddress&0x1ff]; + fx_setCache(); + GSU.pvCache[GSU.pvCache[vAddress&0x1ff] = v; + } +#endif + if((vAddress & 0x00f) == 0x00f) + GSU.vCacheFlags |= 1 << ((vAddress&0x1f0) >> 4); +} + +void FxFlushCache() +{ + GSU.vCacheFlags = 0; + GSU.vCacheBaseReg = 0; + GSU.bCacheActive = FALSE; +// GSU.vPipe = 0x1; +} + +static inline void fx_backupCache() +{ +#if 0 + uint32 i; + uint32 v = GSU.vCacheFlags; + uint32 c = USEX16(GSU.vCacheBaseReg); + if(v) + for(i=0; i<32; i++) + { + if(v&1) + { + if(c < (0x10000-16)) + { + uint8 * t = &GSU.pvPrgBank[c]; + memcpy(&GSU.avCacheBackup[i<<4],t,16); + memcpy(t,&GSU.pvCache[i<<4],16); + } + else + { + uint8 * t1; + uint8 * t2; + uint32 a = 0x10000 - c; + t1 = &GSU.pvPrgBank[c]; + t2 = &GSU.pvPrgBank[0]; + memcpy(&GSU.avCacheBackup[i<<4],t1,a); + memcpy(t1,&GSU.pvCache[i<<4],a); + memcpy(&GSU.avCacheBackup[(i<<4)+a],t2,16-a); + memcpy(t2,&GSU.pvCache[(i<<4)+a],16-a); + } + } + c = USEX16(c+16); + v >>= 1; + } +#endif +} + +static inline void fx_restoreCache() +{ +#if 0 + uint32 i; + uint32 v = GSU.vCacheFlags; + uint32 c = USEX16(GSU.vCacheBaseReg); + if(v) + for(i=0; i<32; i++) + { + if(v&1) + { + if(c < (0x10000-16)) + { + uint8 * t = &GSU.pvPrgBank[c]; + memcpy(t,&GSU.avCacheBackup[i<<4],16); + memcpy(&GSU.pvCache[i<<4],t,16); + } + else + { + uint8 * t1; + uint8 * t2; + uint32 a = 0x10000 - c; + t1 = &GSU.pvPrgBank[c]; + t2 = &GSU.pvPrgBank[0]; + memcpy(t1,&GSU.avCacheBackup[i<<4],a); + memcpy(&GSU.pvCache[i<<4],t1,a); + memcpy(t2,&GSU.avCacheBackup[(i<<4)+a],16-a); + memcpy(&GSU.pvCache[(i<<4)+a],t2,16-a); + } + } + c = USEX16(c+16); + v >>= 1; + } +#endif +} + +void fx_flushCache() +{ + fx_restoreCache(); + GSU.vCacheFlags = 0; + GSU.bCacheActive = FALSE; +} + + +void fx_updateRamBank(uint8 Byte) +{ + // Update BankReg and Bank pointer + GSU.vRamBankReg = (uint32)Byte & (FX_RAM_BANKS-1); + GSU.pvRamBank = GSU.apvRamBank[Byte & 0x3]; +} + + +static inline void fx_readRegisterSpace() +{ + int i; + uint8 *p; + static uint32 avHeight[] = { 128, 160, 192, 256 }; + static uint32 avMult[] = { 16, 32, 32, 64 }; + + GSU.vErrorCode = 0; + + /* Update R0-R15 */ + p = GSU.pvRegisters; + for(i=0; i<16; i++) + { + GSU.avReg[i] = *p++; + GSU.avReg[i] += ((uint32)(*p++)) << 8; + } + + /* Update other registers */ + p = GSU.pvRegisters; + GSU.vStatusReg = (uint32)p[GSU_SFR]; + GSU.vStatusReg |= ((uint32)p[GSU_SFR+1]) << 8; + GSU.vPrgBankReg = (uint32)p[GSU_PBR]; + GSU.vRomBankReg = (uint32)p[GSU_ROMBR]; + GSU.vRamBankReg = ((uint32)p[GSU_RAMBR]) & (FX_RAM_BANKS-1); + GSU.vCacheBaseReg = (uint32)p[GSU_CBR]; + GSU.vCacheBaseReg |= ((uint32)p[GSU_CBR+1]) << 8; + + /* Update status register variables */ + GSU.vZero = !(GSU.vStatusReg & FLG_Z); + GSU.vSign = (GSU.vStatusReg & FLG_S) << 12; + GSU.vOverflow = (GSU.vStatusReg & FLG_OV) << 16; + GSU.vCarry = (GSU.vStatusReg & FLG_CY) >> 2; + + /* Set bank pointers */ + GSU.pvRamBank = GSU.apvRamBank[GSU.vRamBankReg & 0x3]; + GSU.pvRomBank = GSU.apvRomBank[GSU.vRomBankReg]; + GSU.pvPrgBank = GSU.apvRomBank[GSU.vPrgBankReg]; + + /* Set screen pointers */ + GSU.pvScreenBase = &GSU.pvRam[ USEX8(p[GSU_SCBR]) << 10 ]; + i = (int)(!!(p[GSU_SCMR] & 0x04)); + i |= ((int)(!!(p[GSU_SCMR] & 0x20))) << 1; + GSU.vScreenHeight = GSU.vScreenRealHeight = avHeight[i]; + GSU.vMode = p[GSU_SCMR] & 0x03; +#if 0 + if(GSU.vMode == 2) + error illegal color depth GSU.vMode; +#endif + if(i == 3) + GSU.vScreenSize = (256/8) * (256/8) * 32; + else + GSU.vScreenSize = (GSU.vScreenHeight/8) * (256/8) * avMult[GSU.vMode]; + if (GSU.vPlotOptionReg & 0x10) + { + /* OBJ Mode (for drawing into sprites) */ + GSU.vScreenHeight = 256; + } +#if 0 + if(GSU.pvScreenBase + GSU.vScreenSize > GSU.pvRam + (GSU.nRamBanks * 65536)) + error illegal address for screen base register +#else + if(GSU.pvScreenBase + GSU.vScreenSize > GSU.pvRam + (GSU.nRamBanks * 65536)) + GSU.pvScreenBase = GSU.pvRam + (GSU.nRamBanks * 65536) - GSU.vScreenSize; +#endif + GSU.pfPlot = fx_apfPlotTable[GSU.vMode]; + GSU.pfRpix = fx_apfPlotTable[GSU.vMode + 5]; + + fx_ppfOpcodeTable[0x04c] = GSU.pfPlot; + fx_ppfOpcodeTable[0x14c] = GSU.pfRpix; + fx_ppfOpcodeTable[0x24c] = GSU.pfPlot; + fx_ppfOpcodeTable[0x34c] = GSU.pfRpix; + + fx_computeScreenPointers (); + + fx_backupCache(); +} + +void fx_dirtySCBR() +{ + GSU.vSCBRDirty = TRUE; +} + +void fx_computeScreenPointers () +{ + if (GSU.vMode != GSU.vPrevMode || + GSU.vPrevScreenHeight != GSU.vScreenHeight || + GSU.vSCBRDirty) + { + int i; + + GSU.vSCBRDirty = FALSE; + + /* Make a list of pointers to the start of each screen column */ + switch (GSU.vScreenHeight) + { + case 128: + switch (GSU.vMode) + { + case 0: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + (i << 4); + GSU.x[i] = i << 8; + } + break; + case 1: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + (i << 5); + GSU.x[i] = i << 9; + } + break; + case 2: + case 3: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + (i << 6); + GSU.x[i] = i << 10; + } + break; + } + break; + case 160: + switch (GSU.vMode) + { + case 0: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + (i << 4); + GSU.x[i] = (i << 8) + (i << 6); + } + break; + case 1: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + (i << 5); + GSU.x[i] = (i << 9) + (i << 7); + } + break; + case 2: + case 3: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + (i << 6); + GSU.x[i] = (i << 10) + (i << 8); + } + break; + } + break; + case 192: + switch (GSU.vMode) + { + case 0: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + (i << 4); + GSU.x[i] = (i << 8) + (i << 7); + } + break; + case 1: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + (i << 5); + GSU.x[i] = (i << 9) + (i << 8); + } + break; + case 2: + case 3: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + (i << 6); + GSU.x[i] = (i << 10) + (i << 9); + } + break; + } + break; + case 256: + switch (GSU.vMode) + { + case 0: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + + ((i & 0x10) << 9) + ((i & 0xf) << 8); + GSU.x[i] = ((i & 0x10) << 8) + ((i & 0xf) << 4); + } + break; + case 1: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + + ((i & 0x10) << 10) + ((i & 0xf) << 9); + GSU.x[i] = ((i & 0x10) << 9) + ((i & 0xf) << 5); + } + break; + case 2: + case 3: + for (i = 0; i < 32; i++) + { + GSU.apvScreen[i] = GSU.pvScreenBase + + ((i & 0x10) << 11) + ((i & 0xf) << 10); + GSU.x[i] = ((i & 0x10) << 10) + ((i & 0xf) << 6); + } + break; + } + break; + } + GSU.vPrevMode = GSU.vMode; + GSU.vPrevScreenHeight = GSU.vScreenHeight; + } +} + +static inline void fx_writeRegisterSpace() +{ + int i; + uint8 *p; + + p = GSU.pvRegisters; + for(i=0; i<16; i++) + { + *p++ = (uint8)GSU.avReg[i]; + *p++ = (uint8)(GSU.avReg[i] >> 8); + } + + /* Update status register */ + if( USEX16(GSU.vZero) == 0 ) SF(Z); + else CF(Z); + if( GSU.vSign & 0x8000 ) SF(S); + else CF(S); + if(GSU.vOverflow >= 0x8000 || GSU.vOverflow < -0x8000) SF(OV); + else CF(OV); + if(GSU.vCarry) SF(CY); + else CF(CY); + + p = GSU.pvRegisters; + p[GSU_SFR] = (uint8)GSU.vStatusReg; + p[GSU_SFR+1] = (uint8)(GSU.vStatusReg>>8); + p[GSU_PBR] = (uint8)GSU.vPrgBankReg; + p[GSU_ROMBR] = (uint8)GSU.vRomBankReg; + p[GSU_RAMBR] = (uint8)GSU.vRamBankReg; + p[GSU_CBR] = (uint8)GSU.vCacheBaseReg; + p[GSU_CBR+1] = (uint8)(GSU.vCacheBaseReg>>8); + + fx_restoreCache(); +} + +/* Reset the FxChip */ +void FxReset(struct FxInit_s *psFxInfo) +{ + int i; + static uint32 (**appfFunction[])(uint32) = { + &fx_apfFunctionTable[0], +#if 0 + &fx_a_apfFunctionTable[0], + &fx_r_apfFunctionTable[0], + &fx_ar_apfFunctionTable[0], +#endif + }; + static void (**appfPlot[])() = { + &fx_apfPlotTable[0], +#if 0 + &fx_a_apfPlotTable[0], + &fx_r_apfPlotTable[0], + &fx_ar_apfPlotTable[0], +#endif + }; + static void (**appfOpcode[])() = { + &fx_apfOpcodeTable[0], +#if 0 + &fx_a_apfOpcodeTable[0], + &fx_r_apfOpcodeTable[0], + &fx_ar_apfOpcodeTable[0], +#endif + }; + + /* Get function pointers for the current emulation mode */ + fx_ppfFunctionTable = appfFunction[psFxInfo->vFlags & 0x3]; + fx_ppfPlotTable = appfPlot[psFxInfo->vFlags & 0x3]; + fx_ppfOpcodeTable = appfOpcode[psFxInfo->vFlags & 0x3]; + + /* Clear all internal variables */ + memset((uint8*)&GSU,0,sizeof(struct FxRegs_s)); + + /* Set default registers */ + GSU.pvSreg = GSU.pvDreg = &R0; + + /* Set RAM and ROM pointers */ + GSU.pvRegisters = psFxInfo->pvRegisters; + GSU.nRamBanks = psFxInfo->nRamBanks; + GSU.pvRam = psFxInfo->pvRam; + GSU.nRomBanks = psFxInfo->nRomBanks; + GSU.pvRom = psFxInfo->pvRom; + GSU.vPrevScreenHeight = ~0; + GSU.vPrevMode = ~0; + + /* The GSU can't access more than 2mb (16mbits) */ + if(GSU.nRomBanks > 0x20) + GSU.nRomBanks = 0x20; + + /* Clear FxChip register space */ + memset(GSU.pvRegisters,0,0x300); + + /* Set FxChip version Number */ + GSU.pvRegisters[0x3b] = 0; + + /* Make ROM bank table */ + for(i=0; i<256; i++) + { + uint32 b = i & 0x7f; + if (b >= 0x40) + { + if (GSU.nRomBanks > 1) + b %= GSU.nRomBanks; + else + b &= 1; + + GSU.apvRomBank[i] = &GSU.pvRom[ b << 16 ]; + } + else + { + b %= GSU.nRomBanks * 2; + GSU.apvRomBank[i] = &GSU.pvRom[ (b << 16) + 0x200000]; + } + } + + /* Make RAM bank table */ + for(i=0; i<4; i++) + { + GSU.apvRamBank[i] = &GSU.pvRam[(i % GSU.nRamBanks) << 16]; + GSU.apvRomBank[0x70 + i] = GSU.apvRamBank[i]; + } + + /* Start with a nop in the pipe */ + GSU.vPipe = 0x01; + + /* Set pointer to GSU cache */ + GSU.pvCache = &GSU.pvRegisters[0x100]; + + fx_readRegisterSpace(); +} + +static uint8 fx_checkStartAddress() +{ + /* Check if we start inside the cache */ + if(GSU.bCacheActive && R15 >= GSU.vCacheBaseReg && R15 < (GSU.vCacheBaseReg+512)) + return TRUE; + + /* Check if we're in an unused area */ + if(GSU.vPrgBankReg < 0x40 && R15 < 0x8000) + return FALSE; + if(GSU.vPrgBankReg >= 0x60 && GSU.vPrgBankReg <= 0x6f) + return FALSE; + if(GSU.vPrgBankReg >= 0x74) + return FALSE; + + /* Check if we're in RAM and the RAN flag is not set */ + if(GSU.vPrgBankReg >= 0x70 && GSU.vPrgBankReg <= 0x73 && !(SCMR&(1<<3)) ) + return FALSE; + + /* If not, we're in ROM, so check if the RON flag is set */ + if(!(SCMR&(1<<4))) + return FALSE; + + return TRUE; +} + +/* Execute until the next stop instruction */ +int FxEmulate(uint32 nInstructions) +{ + uint32 vCount; + + /* Read registers and initialize GSU session */ + fx_readRegisterSpace(); + + /* Check if the start address is valid */ + if(!fx_checkStartAddress()) + { + CF(G); + fx_writeRegisterSpace(); + return 0; + } + + /* Execute GSU session */ + CF(IRQ); + + if(GSU.bBreakPoint) + vCount = fx_ppfFunctionTable[FX_FUNCTION_RUN_TO_BREAKPOINT](nInstructions); + else + vCount = fx_ppfFunctionTable[FX_FUNCTION_RUN](nInstructions); + + /* Store GSU registers */ + fx_writeRegisterSpace(); + + /* Check for error code */ + if(GSU.vErrorCode) + return GSU.vErrorCode; + else + return vCount; +} + +/* Breakpoints */ +void FxBreakPointSet(uint32 vAddress) +{ + GSU.bBreakPoint = TRUE; + GSU.vBreakPoint = USEX16(vAddress); +} +void FxBreakPointClear() +{ + GSU.bBreakPoint = FALSE; +} + +/* Step by step execution */ +int FxStepOver(uint32 nInstructions) +{ + uint32 vCount; + fx_readRegisterSpace(); + + /* Check if the start address is valid */ + if(!fx_checkStartAddress()) + { + CF(G); +#if 0 + GSU.vIllegalAddress = (GSU.vPrgBankReg << 24) | R15; + return FX_ERROR_ILLEGAL_ADDRESS; +#else + return 0; +#endif + } + + if( PIPE >= 0xf0 ) + GSU.vStepPoint = USEX16(R15+3); + else if( (PIPE >= 0x05 && PIPE <= 0x0f) || (PIPE >= 0xa0 && PIPE <= 0xaf) ) + GSU.vStepPoint = USEX16(R15+2); + else + GSU.vStepPoint = USEX16(R15+1); + vCount = fx_ppfFunctionTable[FX_FUNCTION_STEP_OVER](nInstructions); + fx_writeRegisterSpace(); + if(GSU.vErrorCode) + return GSU.vErrorCode; + else + return vCount; +} + +/* Errors */ +int FxGetErrorCode() +{ + return GSU.vErrorCode; +} + +int FxGetIllegalAddress() +{ + return GSU.vIllegalAddress; +} + +/* Access to internal registers */ +uint32 FxGetColorRegister() +{ + return GSU.vColorReg & 0xff; +} + +uint32 FxGetPlotOptionRegister() +{ + return GSU.vPlotOptionReg & 0x1f; +} + +uint32 FxGetSourceRegisterIndex() +{ + return GSU.pvSreg - GSU.avReg; +} + +uint32 FxGetDestinationRegisterIndex() +{ + return GSU.pvDreg - GSU.avReg; +} + +uint8 FxPipe() +{ + return GSU.vPipe; +} + diff --git a/src/fxemu.h b/src/fxemu.h new file mode 100644 index 0000000..f4bdcf2 --- /dev/null +++ b/src/fxemu.h @@ -0,0 +1,178 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#ifndef _FXEMU_H_ +#define _FXEMU_H_ 1 + +/* Types used by structures and code */ +#ifndef snes9x_types_defined +#define snes9x_types_defined + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; +typedef unsigned char bool8; +typedef unsigned int bool32; +typedef signed char int8; +typedef short int16; +typedef int int32; +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/* The FxInfo_s structure, the link between the FxEmulator and the Snes Emulator */ +struct FxInit_s +{ + uint32 vFlags; + uint8 * pvRegisters; /* 768 bytes located in the memory at address 0x3000 */ + uint32 nRamBanks; /* Number of 64kb-banks in GSU-RAM/BackupRAM (banks 0x70-0x73) */ + uint8 * pvRam; /* Pointer to GSU-RAM */ + uint32 nRomBanks; /* Number of 32kb-banks in Cart-ROM */ + uint8 * pvRom; /* Pointer to Cart-ROM */ +}; + +/* Reset the FxChip */ +extern void FxReset(struct FxInit_s *psFxInfo); + +/* Execute until the next stop instruction */ +extern int FxEmulate(uint32 nInstructions); + +/* Write access to the cache */ +extern void FxCacheWriteAccess(uint16 vAddress); +extern void FxFlushCache(); /* Callled when the G flag in SFR is set to zero */ + +/* Breakpoint */ +extern void FxBreakPointSet(uint32 vAddress); +extern void FxBreakPointClear(); + +/* Step by step execution */ +extern int FxStepOver(uint32 nInstructions); + +/* Errors */ +extern int FxGetErrorCode(); +extern int FxGetIllegalAddress(); + +/* Access to internal registers */ +extern uint32 FxGetColorRegister(); +extern uint32 FxGetPlotOptionRegister(); +extern uint32 FxGetSourceRegisterIndex(); +extern uint32 FxGetDestinationRegisterIndex(); + +/* Get string for opcode currently in the pipe */ +extern void FxPipeString(char * pvString); + +/* Get the byte currently in the pipe */ +extern uint8 FxPipe(); + +/* SCBR write seen. We need to update our cached screen pointers */ +extern void fx_dirtySCBR (void); + +/* Update RamBankReg and RAM Bank pointer */ +extern void fx_updateRamBank(uint8 Byte); + +/* Option flags */ +#define FX_FLAG_ADDRESS_CHECKING 0x01 +#define FX_FLAG_ROM_BUFFER 0x02 + +/* Return codes from FxEmulate(), FxStepInto() or FxStepOver() */ +#define FX_BREAKPOINT -1 +#define FX_ERROR_ILLEGAL_ADDRESS -2 + +/* Return the number of bytes in an opcode */ +#define OPCODE_BYTES(op) ((((op)>=0x05&&(op)<=0xf)||((op)>=0xa0&&(op)<=0xaf))?2:(((op)>=0xf0)?3:1)) + +extern void fx_computeScreenPointers (); + +#endif + diff --git a/src/fxinst.cpp b/src/fxinst.cpp new file mode 100644 index 0000000..acdca50 --- /dev/null +++ b/src/fxinst.cpp @@ -0,0 +1,1916 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#define FX_DO_ROMBUFFER + +#include "fxemu.h" +#include "fxinst.h" +#include +#include + +extern struct FxRegs_s GSU; +int gsu_bank [512] = {0}; + +/* Set this define if you wish the plot instruction to check for y-pos limits */ +/* (I don't think it's nessecary) */ +#define CHECK_LIMITS + +/* Codes used: + * + * rn = a GSU register (r0-r15) + * #n = 4 bit immediate value + * #pp = 8 bit immediate value + * (yy) = 8 bit word address (0x0000 - 0x01fe) + * #xx = 16 bit immediate value + * (xx) = 16 bit address (0x0000 - 0xffff) + * + */ + +/* 00 - stop - stop GSU execution (and maybe generate an IRQ) */ +static inline void fx_stop() +{ + CF(G); + GSU.vCounter = 0; + GSU.vInstCount = GSU.vCounter; + + /* Check if we need to generate an IRQ */ + if(!(GSU.pvRegisters[GSU_CFGR] & 0x80)) + SF(IRQ); + + GSU.vPlotOptionReg = 0; + GSU.vPipe = 1; + CLRFLAGS; + R15++; +} + +/* 01 - nop - no operation */ +static inline void fx_nop() { CLRFLAGS; R15++; } + +extern void fx_flushCache(); + +/* 02 - cache - reintialize GSU cache */ +static inline void fx_cache() +{ + uint32 c = R15 & 0xfff0; + if(GSU.vCacheBaseReg != c || !GSU.bCacheActive) + { + fx_flushCache(); + GSU.vCacheBaseReg = c; + GSU.bCacheActive = TRUE; +#if 0 + if(c < (0x10000-512)) + { + uint8 const* t = &ROM(c); + memcpy(GSU.pvCache,t,512); + } + else + { + uint8 const* t1; + uint8 const* t2; + uint32 i = 0x10000 - c; + t1 = &ROM(c); + t2 = &ROM(0); + memcpy(GSU.pvCache,t1,i); + memcpy(&GSU.pvCache[i],t2,512-i); + } +#endif + } + R15++; + CLRFLAGS; +} + +/* 03 - lsr - logic shift right */ +static inline void fx_lsr() +{ + uint32 v; + GSU.vCarry = SREG & 1; + v = USEX16(SREG) >> 1; + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + TESTR14; + CLRFLAGS; +} + +/* 04 - rol - rotate left */ +static inline void fx_rol() +{ + uint32 v = USEX16((SREG << 1) + GSU.vCarry); + GSU.vCarry = (SREG >> 15) & 1; + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + TESTR14; + CLRFLAGS; +} + +/* 05 - bra - branch always */ +static inline void fx_bra() { uint8 v = PIPE; R15++; FETCHPIPE; R15 += SEX8(v); } + +/* Branch on condition */ +#define BRA_COND(cond) uint8 v = PIPE; R15++; FETCHPIPE; if(cond) R15 += SEX8(v); else R15++; + +#define TEST_S (GSU.vSign & 0x8000) +#define TEST_Z (USEX16(GSU.vZero) == 0) +#define TEST_OV (GSU.vOverflow >= 0x8000 || GSU.vOverflow < -0x8000) +#define TEST_CY (GSU.vCarry & 1) + +/* 06 - blt - branch on less than */ +static inline void fx_blt() { BRA_COND( (TEST_S!=0) != (TEST_OV!=0) ); } + +/* 07 - bge - branch on greater or equals */ +static inline void fx_bge() { BRA_COND( (TEST_S!=0) == (TEST_OV!=0)); } + +/* 08 - bne - branch on not equal */ +static inline void fx_bne() { BRA_COND( !TEST_Z ); } + +/* 09 - beq - branch on equal */ +static inline void fx_beq() { BRA_COND( TEST_Z ); } + +/* 0a - bpl - branch on plus */ +static inline void fx_bpl() { BRA_COND( !TEST_S ); } + +/* 0b - bmi - branch on minus */ +static inline void fx_bmi() { BRA_COND( TEST_S ); } + +/* 0c - bcc - branch on carry clear */ +static inline void fx_bcc() { BRA_COND( !TEST_CY ); } + +/* 0d - bcs - branch on carry set */ +static inline void fx_bcs() { BRA_COND( TEST_CY ); } + +/* 0e - bvc - branch on overflow clear */ +static inline void fx_bvc() { BRA_COND( !TEST_OV ); } + +/* 0f - bvs - branch on overflow set */ +static inline void fx_bvs() { BRA_COND( TEST_OV ); } + +/* 10-1f - to rn - set register n as destination register */ +/* 10-1f(B) - move rn - move one register to another (if B flag is set) */ +#define FX_TO(reg) \ +if(TF(B)) { GSU.avReg[(reg)] = SREG; CLRFLAGS; } \ +else { GSU.pvDreg = &GSU.avReg[reg]; } R15++; +#define FX_TO_R14(reg) \ +if(TF(B)) { GSU.avReg[(reg)] = SREG; CLRFLAGS; READR14; } \ +else { GSU.pvDreg = &GSU.avReg[reg]; } R15++; +#define FX_TO_R15(reg) \ +if(TF(B)) { GSU.avReg[(reg)] = SREG; CLRFLAGS; } \ +else { GSU.pvDreg = &GSU.avReg[reg]; R15++; } +static inline void fx_to_r0() { FX_TO(0); } +static inline void fx_to_r1() { FX_TO(1); } +static inline void fx_to_r2() { FX_TO(2); } +static inline void fx_to_r3() { FX_TO(3); } +static inline void fx_to_r4() { FX_TO(4); } +static inline void fx_to_r5() { FX_TO(5); } +static inline void fx_to_r6() { FX_TO(6); } +static inline void fx_to_r7() { FX_TO(7); } +static inline void fx_to_r8() { FX_TO(8); } +static inline void fx_to_r9() { FX_TO(9); } +static inline void fx_to_r10() { FX_TO(10); } +static inline void fx_to_r11() { FX_TO(11); } +static inline void fx_to_r12() { FX_TO(12); } +static inline void fx_to_r13() { FX_TO(13); } +static inline void fx_to_r14() { FX_TO_R14(14); } +static inline void fx_to_r15() { FX_TO_R15(15); } + +/* 20-2f - to rn - set register n as source and destination register */ +#define FX_WITH(reg) SF(B); GSU.pvSreg = GSU.pvDreg = &GSU.avReg[reg]; R15++; +static inline void fx_with_r0() { FX_WITH(0); } +static inline void fx_with_r1() { FX_WITH(1); } +static inline void fx_with_r2() { FX_WITH(2); } +static inline void fx_with_r3() { FX_WITH(3); } +static inline void fx_with_r4() { FX_WITH(4); } +static inline void fx_with_r5() { FX_WITH(5); } +static inline void fx_with_r6() { FX_WITH(6); } +static inline void fx_with_r7() { FX_WITH(7); } +static inline void fx_with_r8() { FX_WITH(8); } +static inline void fx_with_r9() { FX_WITH(9); } +static inline void fx_with_r10() { FX_WITH(10); } +static inline void fx_with_r11() { FX_WITH(11); } +static inline void fx_with_r12() { FX_WITH(12); } +static inline void fx_with_r13() { FX_WITH(13); } +static inline void fx_with_r14() { FX_WITH(14); } +static inline void fx_with_r15() { FX_WITH(15); } + +/* 30-3b - stw (rn) - store word */ +#define FX_STW(reg) \ +GSU.vLastRamAdr = GSU.avReg[reg]; \ +RAM(GSU.avReg[reg]) = (uint8)SREG; \ +RAM(GSU.avReg[reg]^1) = (uint8)(SREG>>8); \ +CLRFLAGS; R15++ +static inline void fx_stw_r0() { FX_STW(0); } +static inline void fx_stw_r1() { FX_STW(1); } +static inline void fx_stw_r2() { FX_STW(2); } +static inline void fx_stw_r3() { FX_STW(3); } +static inline void fx_stw_r4() { FX_STW(4); } +static inline void fx_stw_r5() { FX_STW(5); } +static inline void fx_stw_r6() { FX_STW(6); } +static inline void fx_stw_r7() { FX_STW(7); } +static inline void fx_stw_r8() { FX_STW(8); } +static inline void fx_stw_r9() { FX_STW(9); } +static inline void fx_stw_r10() { FX_STW(10); } +static inline void fx_stw_r11() { FX_STW(11); } + +/* 30-3b(ALT1) - stb (rn) - store byte */ +#define FX_STB(reg) \ +GSU.vLastRamAdr = GSU.avReg[reg]; \ +RAM(GSU.avReg[reg]) = (uint8)SREG; \ +CLRFLAGS; R15++ +static inline void fx_stb_r0() { FX_STB(0); } +static inline void fx_stb_r1() { FX_STB(1); } +static inline void fx_stb_r2() { FX_STB(2); } +static inline void fx_stb_r3() { FX_STB(3); } +static inline void fx_stb_r4() { FX_STB(4); } +static inline void fx_stb_r5() { FX_STB(5); } +static inline void fx_stb_r6() { FX_STB(6); } +static inline void fx_stb_r7() { FX_STB(7); } +static inline void fx_stb_r8() { FX_STB(8); } +static inline void fx_stb_r9() { FX_STB(9); } +static inline void fx_stb_r10() { FX_STB(10); } +static inline void fx_stb_r11() { FX_STB(11); } + +/* 3c - loop - decrement loop counter, and branch on not zero */ +static inline void fx_loop() +{ + GSU.vSign = GSU.vZero = --R12; + if( (uint16) R12 != 0 ) + R15 = R13; + else + R15++; + + CLRFLAGS; +} + +/* 3d - alt1 - set alt1 mode */ +static inline void fx_alt1() { SF(ALT1); CF(B); R15++; } + +/* 3e - alt2 - set alt2 mode */ +static inline void fx_alt2() { SF(ALT2); CF(B); R15++; } + +/* 3f - alt3 - set alt3 mode */ +static inline void fx_alt3() { SF(ALT1); SF(ALT2); CF(B); R15++; } + +/* 40-4b - ldw (rn) - load word from RAM */ +#define FX_LDW(reg) uint32 v; \ +GSU.vLastRamAdr = GSU.avReg[reg]; \ +v = (uint32)RAM(GSU.avReg[reg]); \ +v |= ((uint32)RAM(GSU.avReg[reg]^1))<<8; \ +R15++; DREG = v; \ +TESTR14; \ +CLRFLAGS +static inline void fx_ldw_r0() { FX_LDW(0); } +static inline void fx_ldw_r1() { FX_LDW(1); } +static inline void fx_ldw_r2() { FX_LDW(2); } +static inline void fx_ldw_r3() { FX_LDW(3); } +static inline void fx_ldw_r4() { FX_LDW(4); } +static inline void fx_ldw_r5() { FX_LDW(5); } +static inline void fx_ldw_r6() { FX_LDW(6); } +static inline void fx_ldw_r7() { FX_LDW(7); } +static inline void fx_ldw_r8() { FX_LDW(8); } +static inline void fx_ldw_r9() { FX_LDW(9); } +static inline void fx_ldw_r10() { FX_LDW(10); } +static inline void fx_ldw_r11() { FX_LDW(11); } + +/* 40-4b(ALT1) - ldb (rn) - load byte */ +#define FX_LDB(reg) uint32 v; \ +GSU.vLastRamAdr = GSU.avReg[reg]; \ +v = (uint32)RAM(GSU.avReg[reg]); \ +R15++; DREG = v; \ +TESTR14; \ +CLRFLAGS +static inline void fx_ldb_r0() { FX_LDB(0); } +static inline void fx_ldb_r1() { FX_LDB(1); } +static inline void fx_ldb_r2() { FX_LDB(2); } +static inline void fx_ldb_r3() { FX_LDB(3); } +static inline void fx_ldb_r4() { FX_LDB(4); } +static inline void fx_ldb_r5() { FX_LDB(5); } +static inline void fx_ldb_r6() { FX_LDB(6); } +static inline void fx_ldb_r7() { FX_LDB(7); } +static inline void fx_ldb_r8() { FX_LDB(8); } +static inline void fx_ldb_r9() { FX_LDB(9); } +static inline void fx_ldb_r10() { FX_LDB(10); } +static inline void fx_ldb_r11() { FX_LDB(11); } + +/* 4c - plot - plot pixel with R1,R2 as x,y and the color register as the color */ +static inline void fx_plot_2bit() +{ + uint32 x = USEX8(R1); + uint32 y = USEX8(R2); + uint8 *a; + uint8 v,c; + + R15++; + CLRFLAGS; + R1++; + +#ifdef CHECK_LIMITS + if(y >= GSU.vScreenHeight) return; +#endif + if(GSU.vPlotOptionReg & 0x02) + c = (x^y)&1 ? (uint8)(GSU.vColorReg>>4) : (uint8)GSU.vColorReg; + else + c = (uint8)GSU.vColorReg; + + if( !(GSU.vPlotOptionReg & 0x01) && !(c & 0xf)) return; + a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); + v = 128 >> (x&7); + + if(c & 0x01) a[0] |= v; + else a[0] &= ~v; + if(c & 0x02) a[1] |= v; + else a[1] &= ~v; +} + +/* 2c(ALT1) - rpix - read color of the pixel with R1,R2 as x,y */ +static inline void fx_rpix_2bit() +{ + uint32 x = USEX8(R1); + uint32 y = USEX8(R2); + uint8 *a; + uint8 v; + + R15++; + CLRFLAGS; +#ifdef CHECK_LIMITS + if(y >= GSU.vScreenHeight) return; +#endif + + a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); + v = 128 >> (x&7); + + DREG = 0; + DREG |= ((uint32)((a[0] & v) != 0)) << 0; + DREG |= ((uint32)((a[1] & v) != 0)) << 1; + TESTR14; +} + +/* 4c - plot - plot pixel with R1,R2 as x,y and the color register as the color */ +static inline void fx_plot_4bit() +{ + uint32 x = USEX8(R1); + uint32 y = USEX8(R2); + uint8 *a; + uint8 v,c; + + R15++; + CLRFLAGS; + R1++; + +#ifdef CHECK_LIMITS + if(y >= GSU.vScreenHeight) return; +#endif + if(GSU.vPlotOptionReg & 0x02) + c = (x^y)&1 ? (uint8)(GSU.vColorReg>>4) : (uint8)GSU.vColorReg; + else + c = (uint8)GSU.vColorReg; + + if( !(GSU.vPlotOptionReg & 0x01) && !(c & 0xf)) return; + + a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); + v = 128 >> (x&7); + + if(c & 0x01) a[0x00] |= v; + else a[0x00] &= ~v; + if(c & 0x02) a[0x01] |= v; + else a[0x01] &= ~v; + if(c & 0x04) a[0x10] |= v; + else a[0x10] &= ~v; + if(c & 0x08) a[0x11] |= v; + else a[0x11] &= ~v; +} + +/* 4c(ALT1) - rpix - read color of the pixel with R1,R2 as x,y */ +static inline void fx_rpix_4bit() +{ + uint32 x = USEX8(R1); + uint32 y = USEX8(R2); + uint8 *a; + uint8 v; + + R15++; + CLRFLAGS; + +#ifdef CHECK_LIMITS + if(y >= GSU.vScreenHeight) return; +#endif + + a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); + v = 128 >> (x&7); + + DREG = 0; + DREG |= ((uint32)((a[0x00] & v) != 0)) << 0; + DREG |= ((uint32)((a[0x01] & v) != 0)) << 1; + DREG |= ((uint32)((a[0x10] & v) != 0)) << 2; + DREG |= ((uint32)((a[0x11] & v) != 0)) << 3; + TESTR14; +} + +/* 8c - plot - plot pixel with R1,R2 as x,y and the color register as the color */ +static inline void fx_plot_8bit() +{ + uint32 x = USEX8(R1); + uint32 y = USEX8(R2); + uint8 *a; + uint8 v,c; + + R15++; + CLRFLAGS; + R1++; + +#ifdef CHECK_LIMITS + if(y >= GSU.vScreenHeight) return; +#endif + c = (uint8)GSU.vColorReg; + if( !(GSU.vPlotOptionReg & 0x10) ) + { + if( !(GSU.vPlotOptionReg & 0x01) && !(c&0xf)) return; + } + else + if( !(GSU.vPlotOptionReg & 0x01) && !c) return; + + a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); + v = 128 >> (x&7); + + if(c & 0x01) a[0x00] |= v; + else a[0x00] &= ~v; + if(c & 0x02) a[0x01] |= v; + else a[0x01] &= ~v; + if(c & 0x04) a[0x10] |= v; + else a[0x10] &= ~v; + if(c & 0x08) a[0x11] |= v; + else a[0x11] &= ~v; + if(c & 0x10) a[0x20] |= v; + else a[0x20] &= ~v; + if(c & 0x20) a[0x21] |= v; + else a[0x21] &= ~v; + if(c & 0x40) a[0x30] |= v; + else a[0x30] &= ~v; + if(c & 0x80) a[0x31] |= v; + else a[0x31] &= ~v; +} + +/* 4c(ALT1) - rpix - read color of the pixel with R1,R2 as x,y */ +static inline void fx_rpix_8bit() +{ + uint32 x = USEX8(R1); + uint32 y = USEX8(R2); + uint8 *a; + uint8 v; + + R15++; + CLRFLAGS; + +#ifdef CHECK_LIMITS + if(y >= GSU.vScreenHeight) return; +#endif + a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1); + v = 128 >> (x&7); + + DREG = 0; + DREG |= ((uint32)((a[0x00] & v) != 0)) << 0; + DREG |= ((uint32)((a[0x01] & v) != 0)) << 1; + DREG |= ((uint32)((a[0x10] & v) != 0)) << 2; + DREG |= ((uint32)((a[0x11] & v) != 0)) << 3; + DREG |= ((uint32)((a[0x20] & v) != 0)) << 4; + DREG |= ((uint32)((a[0x21] & v) != 0)) << 5; + DREG |= ((uint32)((a[0x30] & v) != 0)) << 6; + DREG |= ((uint32)((a[0x31] & v) != 0)) << 7; + GSU.vZero = DREG; + TESTR14; +} + +/* 4o - plot - plot pixel with R1,R2 as x,y and the color register as the color */ +static inline void fx_plot_obj() +{ + printf ("ERROR fx_plot_obj called\n"); +} + +/* 4c(ALT1) - rpix - read color of the pixel with R1,R2 as x,y */ +static inline void fx_rpix_obj() +{ + printf ("ERROR fx_rpix_obj called\n"); +} + +/* 4d - swap - swap upper and lower byte of a register */ +static inline void fx_swap() +{ + uint8 c = (uint8)SREG; + uint8 d = (uint8)(SREG>>8); + uint32 v = (((uint32)c)<<8)|((uint32)d); + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + TESTR14; + CLRFLAGS; +} + +/* 4e - color - copy source register to color register */ +static inline void fx_color() +{ + uint8 c = (uint8)SREG; + if(GSU.vPlotOptionReg & 0x04) + c = (c&0xf0) | (c>>4); + if(GSU.vPlotOptionReg & 0x08) + { + GSU.vColorReg &= 0xf0; + GSU.vColorReg |= c & 0x0f; + } + else + GSU.vColorReg = USEX8(c); + CLRFLAGS; + R15++; +} + +/* 4e(ALT1) - cmode - set plot option register */ +static inline void fx_cmode() +{ + GSU.vPlotOptionReg = SREG; + + if(GSU.vPlotOptionReg & 0x10) + { + /* OBJ Mode (for drawing into sprites) */ + GSU.vScreenHeight = 256; + } + else + GSU.vScreenHeight = GSU.vScreenRealHeight; + + fx_computeScreenPointers (); + CLRFLAGS; + R15++; +} + +/* 4f - not - perform exclusive exor with 1 on all bits */ +static inline void fx_not() +{ + uint32 v = ~SREG; + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + TESTR14; + CLRFLAGS; +} + +/* 50-5f - add rn - add, register + register */ +#define FX_ADD(reg) \ +int32 s = SUSEX16(SREG) + SUSEX16(GSU.avReg[reg]); \ +GSU.vCarry = s >= 0x10000; \ +GSU.vOverflow = ~(SREG ^ GSU.avReg[reg]) & (GSU.avReg[reg] ^ s) & 0x8000; \ +GSU.vSign = s; \ +GSU.vZero = s; \ +R15++; DREG = s; \ +TESTR14; \ +CLRFLAGS +static inline void fx_add_r0() { FX_ADD(0); } +static inline void fx_add_r1() { FX_ADD(1); } +static inline void fx_add_r2() { FX_ADD(2); } +static inline void fx_add_r3() { FX_ADD(3); } +static inline void fx_add_r4() { FX_ADD(4); } +static inline void fx_add_r5() { FX_ADD(5); } +static inline void fx_add_r6() { FX_ADD(6); } +static inline void fx_add_r7() { FX_ADD(7); } +static inline void fx_add_r8() { FX_ADD(8); } +static inline void fx_add_r9() { FX_ADD(9); } +static inline void fx_add_r10() { FX_ADD(10); } +static inline void fx_add_r11() { FX_ADD(11); } +static inline void fx_add_r12() { FX_ADD(12); } +static inline void fx_add_r13() { FX_ADD(13); } +static inline void fx_add_r14() { FX_ADD(14); } +static inline void fx_add_r15() { FX_ADD(15); } + +/* 50-5f(ALT1) - adc rn - add with carry, register + register */ +#define FX_ADC(reg) \ +int32 s = SUSEX16(SREG) + SUSEX16(GSU.avReg[reg]) + SEX16(GSU.vCarry); \ +GSU.vCarry = s >= 0x10000; \ +GSU.vOverflow = ~(SREG ^ GSU.avReg[reg]) & (GSU.avReg[reg] ^ s) & 0x8000; \ +GSU.vSign = s; \ +GSU.vZero = s; \ +R15++; DREG = s; \ +TESTR14; \ +CLRFLAGS +static inline void fx_adc_r0() { FX_ADC(0); } +static inline void fx_adc_r1() { FX_ADC(1); } +static inline void fx_adc_r2() { FX_ADC(2); } +static inline void fx_adc_r3() { FX_ADC(3); } +static inline void fx_adc_r4() { FX_ADC(4); } +static inline void fx_adc_r5() { FX_ADC(5); } +static inline void fx_adc_r6() { FX_ADC(6); } +static inline void fx_adc_r7() { FX_ADC(7); } +static inline void fx_adc_r8() { FX_ADC(8); } +static inline void fx_adc_r9() { FX_ADC(9); } +static inline void fx_adc_r10() { FX_ADC(10); } +static inline void fx_adc_r11() { FX_ADC(11); } +static inline void fx_adc_r12() { FX_ADC(12); } +static inline void fx_adc_r13() { FX_ADC(13); } +static inline void fx_adc_r14() { FX_ADC(14); } +static inline void fx_adc_r15() { FX_ADC(15); } + +/* 50-5f(ALT2) - add #n - add, register + immediate */ +#define FX_ADD_I(imm) \ +int32 s = SUSEX16(SREG) + imm; \ +GSU.vCarry = s >= 0x10000; \ +GSU.vOverflow = ~(SREG ^ imm) & (imm ^ s) & 0x8000; \ +GSU.vSign = s; \ +GSU.vZero = s; \ +R15++; DREG = s; \ +TESTR14; \ +CLRFLAGS +static inline void fx_add_i0() { FX_ADD_I(0); } +static inline void fx_add_i1() { FX_ADD_I(1); } +static inline void fx_add_i2() { FX_ADD_I(2); } +static inline void fx_add_i3() { FX_ADD_I(3); } +static inline void fx_add_i4() { FX_ADD_I(4); } +static inline void fx_add_i5() { FX_ADD_I(5); } +static inline void fx_add_i6() { FX_ADD_I(6); } +static inline void fx_add_i7() { FX_ADD_I(7); } +static inline void fx_add_i8() { FX_ADD_I(8); } +static inline void fx_add_i9() { FX_ADD_I(9); } +static inline void fx_add_i10() { FX_ADD_I(10); } +static inline void fx_add_i11() { FX_ADD_I(11); } +static inline void fx_add_i12() { FX_ADD_I(12); } +static inline void fx_add_i13() { FX_ADD_I(13); } +static inline void fx_add_i14() { FX_ADD_I(14); } +static inline void fx_add_i15() { FX_ADD_I(15); } + +/* 50-5f(ALT3) - adc #n - add with carry, register + immediate */ +#define FX_ADC_I(imm) \ +int32 s = SUSEX16(SREG) + imm + SUSEX16(GSU.vCarry); \ +GSU.vCarry = s >= 0x10000; \ +GSU.vOverflow = ~(SREG ^ imm) & (imm ^ s) & 0x8000; \ +GSU.vSign = s; \ +GSU.vZero = s; \ +R15++; DREG = s; \ +TESTR14; \ +CLRFLAGS +static inline void fx_adc_i0() { FX_ADC_I(0); } +static inline void fx_adc_i1() { FX_ADC_I(1); } +static inline void fx_adc_i2() { FX_ADC_I(2); } +static inline void fx_adc_i3() { FX_ADC_I(3); } +static inline void fx_adc_i4() { FX_ADC_I(4); } +static inline void fx_adc_i5() { FX_ADC_I(5); } +static inline void fx_adc_i6() { FX_ADC_I(6); } +static inline void fx_adc_i7() { FX_ADC_I(7); } +static inline void fx_adc_i8() { FX_ADC_I(8); } +static inline void fx_adc_i9() { FX_ADC_I(9); } +static inline void fx_adc_i10() { FX_ADC_I(10); } +static inline void fx_adc_i11() { FX_ADC_I(11); } +static inline void fx_adc_i12() { FX_ADC_I(12); } +static inline void fx_adc_i13() { FX_ADC_I(13); } +static inline void fx_adc_i14() { FX_ADC_I(14); } +static inline void fx_adc_i15() { FX_ADC_I(15); } + +/* 60-6f - sub rn - subtract, register - register */ +#define FX_SUB(reg) \ +int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]); \ +GSU.vCarry = s >= 0; \ +GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \ +GSU.vSign = s; \ +GSU.vZero = s; \ +R15++; DREG = s; \ +TESTR14; \ +CLRFLAGS +static inline void fx_sub_r0() { FX_SUB(0); } +static inline void fx_sub_r1() { FX_SUB(1); } +static inline void fx_sub_r2() { FX_SUB(2); } +static inline void fx_sub_r3() { FX_SUB(3); } +static inline void fx_sub_r4() { FX_SUB(4); } +static inline void fx_sub_r5() { FX_SUB(5); } +static inline void fx_sub_r6() { FX_SUB(6); } +static inline void fx_sub_r7() { FX_SUB(7); } +static inline void fx_sub_r8() { FX_SUB(8); } +static inline void fx_sub_r9() { FX_SUB(9); } +static inline void fx_sub_r10() { FX_SUB(10); } +static inline void fx_sub_r11() { FX_SUB(11); } +static inline void fx_sub_r12() { FX_SUB(12); } +static inline void fx_sub_r13() { FX_SUB(13); } +static inline void fx_sub_r14() { FX_SUB(14); } +static inline void fx_sub_r15() { FX_SUB(15); } + +/* 60-6f(ALT1) - sbc rn - subtract with carry, register - register */ +#define FX_SBC(reg) \ +int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]) - (SUSEX16(GSU.vCarry^1)); \ +GSU.vCarry = s >= 0; \ +GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \ +GSU.vSign = s; \ +GSU.vZero = s; \ +R15++; DREG = s; \ +TESTR14; \ +CLRFLAGS +static inline void fx_sbc_r0() { FX_SBC(0); } +static inline void fx_sbc_r1() { FX_SBC(1); } +static inline void fx_sbc_r2() { FX_SBC(2); } +static inline void fx_sbc_r3() { FX_SBC(3); } +static inline void fx_sbc_r4() { FX_SBC(4); } +static inline void fx_sbc_r5() { FX_SBC(5); } +static inline void fx_sbc_r6() { FX_SBC(6); } +static inline void fx_sbc_r7() { FX_SBC(7); } +static inline void fx_sbc_r8() { FX_SBC(8); } +static inline void fx_sbc_r9() { FX_SBC(9); } +static inline void fx_sbc_r10() { FX_SBC(10); } +static inline void fx_sbc_r11() { FX_SBC(11); } +static inline void fx_sbc_r12() { FX_SBC(12); } +static inline void fx_sbc_r13() { FX_SBC(13); } +static inline void fx_sbc_r14() { FX_SBC(14); } +static inline void fx_sbc_r15() { FX_SBC(15); } + +/* 60-6f(ALT2) - sub #n - subtract, register - immediate */ +#define FX_SUB_I(imm) \ +int32 s = SUSEX16(SREG) - imm; \ +GSU.vCarry = s >= 0; \ +GSU.vOverflow = (SREG ^ imm) & (SREG ^ s) & 0x8000; \ +GSU.vSign = s; \ +GSU.vZero = s; \ +R15++; DREG = s; \ +TESTR14; \ +CLRFLAGS +static inline void fx_sub_i0() { FX_SUB_I(0); } +static inline void fx_sub_i1() { FX_SUB_I(1); } +static inline void fx_sub_i2() { FX_SUB_I(2); } +static inline void fx_sub_i3() { FX_SUB_I(3); } +static inline void fx_sub_i4() { FX_SUB_I(4); } +static inline void fx_sub_i5() { FX_SUB_I(5); } +static inline void fx_sub_i6() { FX_SUB_I(6); } +static inline void fx_sub_i7() { FX_SUB_I(7); } +static inline void fx_sub_i8() { FX_SUB_I(8); } +static inline void fx_sub_i9() { FX_SUB_I(9); } +static inline void fx_sub_i10() { FX_SUB_I(10); } +static inline void fx_sub_i11() { FX_SUB_I(11); } +static inline void fx_sub_i12() { FX_SUB_I(12); } +static inline void fx_sub_i13() { FX_SUB_I(13); } +static inline void fx_sub_i14() { FX_SUB_I(14); } +static inline void fx_sub_i15() { FX_SUB_I(15); } + +/* 60-6f(ALT3) - cmp rn - compare, register, register */ +#define FX_CMP(reg) \ +int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]); \ +GSU.vCarry = s >= 0; \ +GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \ +GSU.vSign = s; \ +GSU.vZero = s; \ +R15++; \ +CLRFLAGS; +static inline void fx_cmp_r0() { FX_CMP(0); } +static inline void fx_cmp_r1() { FX_CMP(1); } +static inline void fx_cmp_r2() { FX_CMP(2); } +static inline void fx_cmp_r3() { FX_CMP(3); } +static inline void fx_cmp_r4() { FX_CMP(4); } +static inline void fx_cmp_r5() { FX_CMP(5); } +static inline void fx_cmp_r6() { FX_CMP(6); } +static inline void fx_cmp_r7() { FX_CMP(7); } +static inline void fx_cmp_r8() { FX_CMP(8); } +static inline void fx_cmp_r9() { FX_CMP(9); } +static inline void fx_cmp_r10() { FX_CMP(10); } +static inline void fx_cmp_r11() { FX_CMP(11); } +static inline void fx_cmp_r12() { FX_CMP(12); } +static inline void fx_cmp_r13() { FX_CMP(13); } +static inline void fx_cmp_r14() { FX_CMP(14); } +static inline void fx_cmp_r15() { FX_CMP(15); } + +/* 70 - merge - R7 as upper byte, R8 as lower byte (used for texture-mapping) */ +static inline void fx_merge() +{ + uint32 v = (R7&0xff00) | ((R8&0xff00)>>8); + R15++; DREG = v; + GSU.vOverflow = (v & 0xc0c0) << 16; + GSU.vZero = !(v & 0xf0f0); + GSU.vSign = ((v | (v<<8)) & 0x8000); + GSU.vCarry = (v & 0xe0e0) != 0; + TESTR14; + CLRFLAGS; +} + +/* 71-7f - and rn - reister & register */ +#define FX_AND(reg) \ +uint32 v = SREG & GSU.avReg[reg]; \ +R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_and_r1() { FX_AND(1); } +static inline void fx_and_r2() { FX_AND(2); } +static inline void fx_and_r3() { FX_AND(3); } +static inline void fx_and_r4() { FX_AND(4); } +static inline void fx_and_r5() { FX_AND(5); } +static inline void fx_and_r6() { FX_AND(6); } +static inline void fx_and_r7() { FX_AND(7); } +static inline void fx_and_r8() { FX_AND(8); } +static inline void fx_and_r9() { FX_AND(9); } +static inline void fx_and_r10() { FX_AND(10); } +static inline void fx_and_r11() { FX_AND(11); } +static inline void fx_and_r12() { FX_AND(12); } +static inline void fx_and_r13() { FX_AND(13); } +static inline void fx_and_r14() { FX_AND(14); } +static inline void fx_and_r15() { FX_AND(15); } + +/* 71-7f(ALT1) - bic rn - reister & ~register */ +#define FX_BIC(reg) \ +uint32 v = SREG & ~GSU.avReg[reg]; \ +R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_bic_r1() { FX_BIC(1); } +static inline void fx_bic_r2() { FX_BIC(2); } +static inline void fx_bic_r3() { FX_BIC(3); } +static inline void fx_bic_r4() { FX_BIC(4); } +static inline void fx_bic_r5() { FX_BIC(5); } +static inline void fx_bic_r6() { FX_BIC(6); } +static inline void fx_bic_r7() { FX_BIC(7); } +static inline void fx_bic_r8() { FX_BIC(8); } +static inline void fx_bic_r9() { FX_BIC(9); } +static inline void fx_bic_r10() { FX_BIC(10); } +static inline void fx_bic_r11() { FX_BIC(11); } +static inline void fx_bic_r12() { FX_BIC(12); } +static inline void fx_bic_r13() { FX_BIC(13); } +static inline void fx_bic_r14() { FX_BIC(14); } +static inline void fx_bic_r15() { FX_BIC(15); } + +/* 71-7f(ALT2) - and #n - reister & immediate */ +#define FX_AND_I(imm) \ +uint32 v = SREG & imm; \ +R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_and_i1() { FX_AND_I(1); } +static inline void fx_and_i2() { FX_AND_I(2); } +static inline void fx_and_i3() { FX_AND_I(3); } +static inline void fx_and_i4() { FX_AND_I(4); } +static inline void fx_and_i5() { FX_AND_I(5); } +static inline void fx_and_i6() { FX_AND_I(6); } +static inline void fx_and_i7() { FX_AND_I(7); } +static inline void fx_and_i8() { FX_AND_I(8); } +static inline void fx_and_i9() { FX_AND_I(9); } +static inline void fx_and_i10() { FX_AND_I(10); } +static inline void fx_and_i11() { FX_AND_I(11); } +static inline void fx_and_i12() { FX_AND_I(12); } +static inline void fx_and_i13() { FX_AND_I(13); } +static inline void fx_and_i14() { FX_AND_I(14); } +static inline void fx_and_i15() { FX_AND_I(15); } + +/* 71-7f(ALT3) - bic #n - reister & ~immediate */ +#define FX_BIC_I(imm) \ +uint32 v = SREG & ~imm; \ +R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_bic_i1() { FX_BIC_I(1); } +static inline void fx_bic_i2() { FX_BIC_I(2); } +static inline void fx_bic_i3() { FX_BIC_I(3); } +static inline void fx_bic_i4() { FX_BIC_I(4); } +static inline void fx_bic_i5() { FX_BIC_I(5); } +static inline void fx_bic_i6() { FX_BIC_I(6); } +static inline void fx_bic_i7() { FX_BIC_I(7); } +static inline void fx_bic_i8() { FX_BIC_I(8); } +static inline void fx_bic_i9() { FX_BIC_I(9); } +static inline void fx_bic_i10() { FX_BIC_I(10); } +static inline void fx_bic_i11() { FX_BIC_I(11); } +static inline void fx_bic_i12() { FX_BIC_I(12); } +static inline void fx_bic_i13() { FX_BIC_I(13); } +static inline void fx_bic_i14() { FX_BIC_I(14); } +static inline void fx_bic_i15() { FX_BIC_I(15); } + +/* 80-8f - mult rn - 8 bit to 16 bit signed multiply, register * register */ +#define FX_MULT(reg) \ +uint32 v = (uint32)(SEX8(SREG) * SEX8(GSU.avReg[reg])); \ +R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_mult_r0() { FX_MULT(0); } +static inline void fx_mult_r1() { FX_MULT(1); } +static inline void fx_mult_r2() { FX_MULT(2); } +static inline void fx_mult_r3() { FX_MULT(3); } +static inline void fx_mult_r4() { FX_MULT(4); } +static inline void fx_mult_r5() { FX_MULT(5); } +static inline void fx_mult_r6() { FX_MULT(6); } +static inline void fx_mult_r7() { FX_MULT(7); } +static inline void fx_mult_r8() { FX_MULT(8); } +static inline void fx_mult_r9() { FX_MULT(9); } +static inline void fx_mult_r10() { FX_MULT(10); } +static inline void fx_mult_r11() { FX_MULT(11); } +static inline void fx_mult_r12() { FX_MULT(12); } +static inline void fx_mult_r13() { FX_MULT(13); } +static inline void fx_mult_r14() { FX_MULT(14); } +static inline void fx_mult_r15() { FX_MULT(15); } + +/* 80-8f(ALT1) - umult rn - 8 bit to 16 bit unsigned multiply, register * register */ +#define FX_UMULT(reg) \ +uint32 v = USEX8(SREG) * USEX8(GSU.avReg[reg]); \ +R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_umult_r0() { FX_UMULT(0); } +static inline void fx_umult_r1() { FX_UMULT(1); } +static inline void fx_umult_r2() { FX_UMULT(2); } +static inline void fx_umult_r3() { FX_UMULT(3); } +static inline void fx_umult_r4() { FX_UMULT(4); } +static inline void fx_umult_r5() { FX_UMULT(5); } +static inline void fx_umult_r6() { FX_UMULT(6); } +static inline void fx_umult_r7() { FX_UMULT(7); } +static inline void fx_umult_r8() { FX_UMULT(8); } +static inline void fx_umult_r9() { FX_UMULT(9); } +static inline void fx_umult_r10() { FX_UMULT(10); } +static inline void fx_umult_r11() { FX_UMULT(11); } +static inline void fx_umult_r12() { FX_UMULT(12); } +static inline void fx_umult_r13() { FX_UMULT(13); } +static inline void fx_umult_r14() { FX_UMULT(14); } +static inline void fx_umult_r15() { FX_UMULT(15); } + +/* 80-8f(ALT2) - mult #n - 8 bit to 16 bit signed multiply, register * immediate */ +#define FX_MULT_I(imm) \ +uint32 v = (uint32) (SEX8(SREG) * ((int32)imm)); \ +R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_mult_i0() { FX_MULT_I(0); } +static inline void fx_mult_i1() { FX_MULT_I(1); } +static inline void fx_mult_i2() { FX_MULT_I(2); } +static inline void fx_mult_i3() { FX_MULT_I(3); } +static inline void fx_mult_i4() { FX_MULT_I(4); } +static inline void fx_mult_i5() { FX_MULT_I(5); } +static inline void fx_mult_i6() { FX_MULT_I(6); } +static inline void fx_mult_i7() { FX_MULT_I(7); } +static inline void fx_mult_i8() { FX_MULT_I(8); } +static inline void fx_mult_i9() { FX_MULT_I(9); } +static inline void fx_mult_i10() { FX_MULT_I(10); } +static inline void fx_mult_i11() { FX_MULT_I(11); } +static inline void fx_mult_i12() { FX_MULT_I(12); } +static inline void fx_mult_i13() { FX_MULT_I(13); } +static inline void fx_mult_i14() { FX_MULT_I(14); } +static inline void fx_mult_i15() { FX_MULT_I(15); } + +/* 80-8f(ALT3) - umult #n - 8 bit to 16 bit unsigned multiply, register * immediate */ +#define FX_UMULT_I(imm) \ +uint32 v = USEX8(SREG) * ((uint32)imm); \ +R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_umult_i0() { FX_UMULT_I(0); } +static inline void fx_umult_i1() { FX_UMULT_I(1); } +static inline void fx_umult_i2() { FX_UMULT_I(2); } +static inline void fx_umult_i3() { FX_UMULT_I(3); } +static inline void fx_umult_i4() { FX_UMULT_I(4); } +static inline void fx_umult_i5() { FX_UMULT_I(5); } +static inline void fx_umult_i6() { FX_UMULT_I(6); } +static inline void fx_umult_i7() { FX_UMULT_I(7); } +static inline void fx_umult_i8() { FX_UMULT_I(8); } +static inline void fx_umult_i9() { FX_UMULT_I(9); } +static inline void fx_umult_i10() { FX_UMULT_I(10); } +static inline void fx_umult_i11() { FX_UMULT_I(11); } +static inline void fx_umult_i12() { FX_UMULT_I(12); } +static inline void fx_umult_i13() { FX_UMULT_I(13); } +static inline void fx_umult_i14() { FX_UMULT_I(14); } +static inline void fx_umult_i15() { FX_UMULT_I(15); } + +/* 90 - sbk - store word to last accessed RAM address */ +static inline void fx_sbk() +{ + RAM(GSU.vLastRamAdr) = (uint8)SREG; + RAM(GSU.vLastRamAdr^1) = (uint8)(SREG>>8); + CLRFLAGS; + R15++; +} + +/* 91-94 - link #n - R11 = R15 + immediate */ +#define FX_LINK_I(lkn) R11 = R15 + lkn; CLRFLAGS; R15++ +static inline void fx_link_i1() { FX_LINK_I(1); } +static inline void fx_link_i2() { FX_LINK_I(2); } +static inline void fx_link_i3() { FX_LINK_I(3); } +static inline void fx_link_i4() { FX_LINK_I(4); } + +/* 95 - sex - sign extend 8 bit to 16 bit */ +static inline void fx_sex() +{ + uint32 v = (uint32)SEX8(SREG); + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + TESTR14; + CLRFLAGS; +} + +/* 96 - asr - aritmetric shift right by one */ +static inline void fx_asr() +{ + uint32 v; + GSU.vCarry = SREG & 1; + v = (uint32)(SEX16(SREG)>>1); + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + TESTR14; + CLRFLAGS; +} + +/* 96(ALT1) - div2 - aritmetric shift right by one */ +static inline void fx_div2() +{ + uint32 v; + int32 s = SEX16(SREG); + GSU.vCarry = s & 1; + if(s == -1) + v = 0; + else + v = (uint32)(s>>1); + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + TESTR14; + CLRFLAGS; +} + +/* 97 - ror - rotate right by one */ +static inline void fx_ror() +{ + uint32 v = (USEX16(SREG)>>1) | (GSU.vCarry<<15); + GSU.vCarry = SREG & 1; + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + TESTR14; + CLRFLAGS; +} + +/* 98-9d - jmp rn - jump to address of register */ +#define FX_JMP(reg) \ +R15 = GSU.avReg[reg]; \ +CLRFLAGS; +static inline void fx_jmp_r8() { FX_JMP(8); } +static inline void fx_jmp_r9() { FX_JMP(9); } +static inline void fx_jmp_r10() { FX_JMP(10); } +static inline void fx_jmp_r11() { FX_JMP(11); } +static inline void fx_jmp_r12() { FX_JMP(12); } +static inline void fx_jmp_r13() { FX_JMP(13); } + +/* 98-9d(ALT1) - ljmp rn - set program bank to source register and jump to address of register */ +#define FX_LJMP(reg) \ +GSU.vPrgBankReg = GSU.avReg[reg] & 0x7f; \ +GSU.pvPrgBank = GSU.apvRomBank[GSU.vPrgBankReg]; \ +R15 = SREG; \ +GSU.bCacheActive = FALSE; fx_cache(); R15--; +static inline void fx_ljmp_r8() { FX_LJMP(8); } +static inline void fx_ljmp_r9() { FX_LJMP(9); } +static inline void fx_ljmp_r10() { FX_LJMP(10); } +static inline void fx_ljmp_r11() { FX_LJMP(11); } +static inline void fx_ljmp_r12() { FX_LJMP(12); } +static inline void fx_ljmp_r13() { FX_LJMP(13); } + +/* 9e - lob - set upper byte to zero (keep low byte) */ +static inline void fx_lob() +{ + uint32 v = USEX8(SREG); + R15++; DREG = v; + GSU.vSign = v<<8; + GSU.vZero = v<<8; + TESTR14; + CLRFLAGS; +} + +/* 9f - fmult - 16 bit to 32 bit signed multiplication, upper 16 bits only */ +static inline void fx_fmult() +{ + uint32 v; + uint32 c = (uint32) (SEX16(SREG) * SEX16(R6)); + v = c >> 16; + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + GSU.vCarry = (c >> 15) & 1; + TESTR14; + CLRFLAGS; +} + +/* 9f(ALT1) - lmult - 16 bit to 32 bit signed multiplication */ +static inline void fx_lmult() +{ + uint32 v; + uint32 c = (uint32) (SEX16(SREG) * SEX16(R6)); + R4 = c; + v = c >> 16; + R15++; DREG = v; + GSU.vSign = v; + GSU.vZero = v; + /* XXX R6 or R4? */ + GSU.vCarry = (R4 >> 15) & 1; /* should it be bit 15 of R4 instead? */ + TESTR14; + CLRFLAGS; +} + +/* a0-af - ibt rn,#pp - immediate byte transfer */ +#define FX_IBT(reg) \ +uint8 v = PIPE; R15++; \ +FETCHPIPE; R15++; \ +GSU.avReg[reg] = SEX8(v); \ +CLRFLAGS; +static inline void fx_ibt_r0() { FX_IBT(0); } +static inline void fx_ibt_r1() { FX_IBT(1); } +static inline void fx_ibt_r2() { FX_IBT(2); } +static inline void fx_ibt_r3() { FX_IBT(3); } +static inline void fx_ibt_r4() { FX_IBT(4); } +static inline void fx_ibt_r5() { FX_IBT(5); } +static inline void fx_ibt_r6() { FX_IBT(6); } +static inline void fx_ibt_r7() { FX_IBT(7); } +static inline void fx_ibt_r8() { FX_IBT(8); } +static inline void fx_ibt_r9() { FX_IBT(9); } +static inline void fx_ibt_r10() { FX_IBT(10); } +static inline void fx_ibt_r11() { FX_IBT(11); } +static inline void fx_ibt_r12() { FX_IBT(12); } +static inline void fx_ibt_r13() { FX_IBT(13); } +static inline void fx_ibt_r14() { FX_IBT(14); READR14; } +static inline void fx_ibt_r15() { FX_IBT(15); } + +/* a0-af(ALT1) - lms rn,(yy) - load word from RAM (short address) */ +#define FX_LMS(reg) \ +GSU.vLastRamAdr = ((uint32)PIPE) << 1; \ +R15++; FETCHPIPE; R15++; \ +GSU.avReg[reg] = (uint32)RAM(GSU.vLastRamAdr); \ +GSU.avReg[reg] |= ((uint32)RAM(GSU.vLastRamAdr+1))<<8; \ +CLRFLAGS; +static inline void fx_lms_r0() { FX_LMS(0); } +static inline void fx_lms_r1() { FX_LMS(1); } +static inline void fx_lms_r2() { FX_LMS(2); } +static inline void fx_lms_r3() { FX_LMS(3); } +static inline void fx_lms_r4() { FX_LMS(4); } +static inline void fx_lms_r5() { FX_LMS(5); } +static inline void fx_lms_r6() { FX_LMS(6); } +static inline void fx_lms_r7() { FX_LMS(7); } +static inline void fx_lms_r8() { FX_LMS(8); } +static inline void fx_lms_r9() { FX_LMS(9); } +static inline void fx_lms_r10() { FX_LMS(10); } +static inline void fx_lms_r11() { FX_LMS(11); } +static inline void fx_lms_r12() { FX_LMS(12); } +static inline void fx_lms_r13() { FX_LMS(13); } +static inline void fx_lms_r14() { FX_LMS(14); READR14; } +static inline void fx_lms_r15() { FX_LMS(15); } + +/* a0-af(ALT2) - sms (yy),rn - store word in RAM (short address) */ +/* If rn == r15, is the value of r15 before or after the extra byte is read? */ +#define FX_SMS(reg) \ +uint32 v = GSU.avReg[reg]; \ +GSU.vLastRamAdr = ((uint32)PIPE) << 1; \ +R15++; FETCHPIPE; \ +RAM(GSU.vLastRamAdr) = (uint8)v; \ +RAM(GSU.vLastRamAdr+1) = (uint8)(v>>8); \ +CLRFLAGS; R15++; +static inline void fx_sms_r0() { FX_SMS(0); } +static inline void fx_sms_r1() { FX_SMS(1); } +static inline void fx_sms_r2() { FX_SMS(2); } +static inline void fx_sms_r3() { FX_SMS(3); } +static inline void fx_sms_r4() { FX_SMS(4); } +static inline void fx_sms_r5() { FX_SMS(5); } +static inline void fx_sms_r6() { FX_SMS(6); } +static inline void fx_sms_r7() { FX_SMS(7); } +static inline void fx_sms_r8() { FX_SMS(8); } +static inline void fx_sms_r9() { FX_SMS(9); } +static inline void fx_sms_r10() { FX_SMS(10); } +static inline void fx_sms_r11() { FX_SMS(11); } +static inline void fx_sms_r12() { FX_SMS(12); } +static inline void fx_sms_r13() { FX_SMS(13); } +static inline void fx_sms_r14() { FX_SMS(14); } +static inline void fx_sms_r15() { FX_SMS(15); } + +/* b0-bf - from rn - set source register */ +/* b0-bf(B) - moves rn - move register to register, and set flags, (if B flag is set) */ +#define FX_FROM(reg) \ +if(TF(B)) { uint32 v = GSU.avReg[reg]; R15++; DREG = v; \ +GSU.vOverflow = (v&0x80) << 16; GSU.vSign = v; GSU.vZero = v; TESTR14; CLRFLAGS; } \ +else { GSU.pvSreg = &GSU.avReg[reg]; R15++; } +static inline void fx_from_r0() { FX_FROM(0); } +static inline void fx_from_r1() { FX_FROM(1); } +static inline void fx_from_r2() { FX_FROM(2); } +static inline void fx_from_r3() { FX_FROM(3); } +static inline void fx_from_r4() { FX_FROM(4); } +static inline void fx_from_r5() { FX_FROM(5); } +static inline void fx_from_r6() { FX_FROM(6); } +static inline void fx_from_r7() { FX_FROM(7); } +static inline void fx_from_r8() { FX_FROM(8); } +static inline void fx_from_r9() { FX_FROM(9); } +static inline void fx_from_r10() { FX_FROM(10); } +static inline void fx_from_r11() { FX_FROM(11); } +static inline void fx_from_r12() { FX_FROM(12); } +static inline void fx_from_r13() { FX_FROM(13); } +static inline void fx_from_r14() { FX_FROM(14); } +static inline void fx_from_r15() { FX_FROM(15); } + +/* c0 - hib - move high-byte to low-byte */ +static inline void fx_hib() +{ + uint32 v = USEX8(SREG>>8); + R15++; DREG = v; + GSU.vSign = v<<8; + GSU.vZero = v<<8; + TESTR14; + CLRFLAGS; +} + +/* c1-cf - or rn */ +#define FX_OR(reg) \ +uint32 v = SREG | GSU.avReg[reg]; R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_or_r1() { FX_OR(1); } +static inline void fx_or_r2() { FX_OR(2); } +static inline void fx_or_r3() { FX_OR(3); } +static inline void fx_or_r4() { FX_OR(4); } +static inline void fx_or_r5() { FX_OR(5); } +static inline void fx_or_r6() { FX_OR(6); } +static inline void fx_or_r7() { FX_OR(7); } +static inline void fx_or_r8() { FX_OR(8); } +static inline void fx_or_r9() { FX_OR(9); } +static inline void fx_or_r10() { FX_OR(10); } +static inline void fx_or_r11() { FX_OR(11); } +static inline void fx_or_r12() { FX_OR(12); } +static inline void fx_or_r13() { FX_OR(13); } +static inline void fx_or_r14() { FX_OR(14); } +static inline void fx_or_r15() { FX_OR(15); } + +/* c1-cf(ALT1) - xor rn */ +#define FX_XOR(reg) \ +uint32 v = SREG ^ GSU.avReg[reg]; R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_xor_r1() { FX_XOR(1); } +static inline void fx_xor_r2() { FX_XOR(2); } +static inline void fx_xor_r3() { FX_XOR(3); } +static inline void fx_xor_r4() { FX_XOR(4); } +static inline void fx_xor_r5() { FX_XOR(5); } +static inline void fx_xor_r6() { FX_XOR(6); } +static inline void fx_xor_r7() { FX_XOR(7); } +static inline void fx_xor_r8() { FX_XOR(8); } +static inline void fx_xor_r9() { FX_XOR(9); } +static inline void fx_xor_r10() { FX_XOR(10); } +static inline void fx_xor_r11() { FX_XOR(11); } +static inline void fx_xor_r12() { FX_XOR(12); } +static inline void fx_xor_r13() { FX_XOR(13); } +static inline void fx_xor_r14() { FX_XOR(14); } +static inline void fx_xor_r15() { FX_XOR(15); } + +/* c1-cf(ALT2) - or #n */ +#define FX_OR_I(imm) \ +uint32 v = SREG | imm; R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_or_i1() { FX_OR_I(1); } +static inline void fx_or_i2() { FX_OR_I(2); } +static inline void fx_or_i3() { FX_OR_I(3); } +static inline void fx_or_i4() { FX_OR_I(4); } +static inline void fx_or_i5() { FX_OR_I(5); } +static inline void fx_or_i6() { FX_OR_I(6); } +static inline void fx_or_i7() { FX_OR_I(7); } +static inline void fx_or_i8() { FX_OR_I(8); } +static inline void fx_or_i9() { FX_OR_I(9); } +static inline void fx_or_i10() { FX_OR_I(10); } +static inline void fx_or_i11() { FX_OR_I(11); } +static inline void fx_or_i12() { FX_OR_I(12); } +static inline void fx_or_i13() { FX_OR_I(13); } +static inline void fx_or_i14() { FX_OR_I(14); } +static inline void fx_or_i15() { FX_OR_I(15); } + +/* c1-cf(ALT3) - xor #n */ +#define FX_XOR_I(imm) \ +uint32 v = SREG ^ imm; R15++; DREG = v; \ +GSU.vSign = v; \ +GSU.vZero = v; \ +TESTR14; \ +CLRFLAGS; +static inline void fx_xor_i1() { FX_XOR_I(1); } +static inline void fx_xor_i2() { FX_XOR_I(2); } +static inline void fx_xor_i3() { FX_XOR_I(3); } +static inline void fx_xor_i4() { FX_XOR_I(4); } +static inline void fx_xor_i5() { FX_XOR_I(5); } +static inline void fx_xor_i6() { FX_XOR_I(6); } +static inline void fx_xor_i7() { FX_XOR_I(7); } +static inline void fx_xor_i8() { FX_XOR_I(8); } +static inline void fx_xor_i9() { FX_XOR_I(9); } +static inline void fx_xor_i10() { FX_XOR_I(10); } +static inline void fx_xor_i11() { FX_XOR_I(11); } +static inline void fx_xor_i12() { FX_XOR_I(12); } +static inline void fx_xor_i13() { FX_XOR_I(13); } +static inline void fx_xor_i14() { FX_XOR_I(14); } +static inline void fx_xor_i15() { FX_XOR_I(15); } + +/* d0-de - inc rn - increase by one */ +#define FX_INC(reg) \ +GSU.avReg[reg] += 1; \ +GSU.vSign = GSU.avReg[reg]; \ +GSU.vZero = GSU.avReg[reg]; \ +CLRFLAGS; R15++; +static inline void fx_inc_r0() { FX_INC(0); } +static inline void fx_inc_r1() { FX_INC(1); } +static inline void fx_inc_r2() { FX_INC(2); } +static inline void fx_inc_r3() { FX_INC(3); } +static inline void fx_inc_r4() { FX_INC(4); } +static inline void fx_inc_r5() { FX_INC(5); } +static inline void fx_inc_r6() { FX_INC(6); } +static inline void fx_inc_r7() { FX_INC(7); } +static inline void fx_inc_r8() { FX_INC(8); } +static inline void fx_inc_r9() { FX_INC(9); } +static inline void fx_inc_r10() { FX_INC(10); } +static inline void fx_inc_r11() { FX_INC(11); } +static inline void fx_inc_r12() { FX_INC(12); } +static inline void fx_inc_r13() { FX_INC(13); } +static inline void fx_inc_r14() { FX_INC(14); READR14; } + +/* df - getc - transfer ROM buffer to color register */ +static inline void fx_getc() +{ +#ifndef FX_DO_ROMBUFFER + uint8 c; + c = ROM(R14); +#else + uint8 c = GSU.vRomBuffer; +#endif + if(GSU.vPlotOptionReg & 0x04) + c = (c&0xf0) | (c>>4); + if(GSU.vPlotOptionReg & 0x08) + { + GSU.vColorReg &= 0xf0; + GSU.vColorReg |= c & 0x0f; + } + else + GSU.vColorReg = USEX8(c); + CLRFLAGS; + R15++; +} + +/* df(ALT2) - ramb - set current RAM bank */ +static inline void fx_ramb() +{ + GSU.vRamBankReg = SREG & (FX_RAM_BANKS-1); + GSU.pvRamBank = GSU.apvRamBank[GSU.vRamBankReg & 0x3]; + CLRFLAGS; + R15++; +} + +/* df(ALT3) - romb - set current ROM bank */ +static inline void fx_romb() +{ + GSU.vRomBankReg = USEX8(SREG) & 0x7f; + GSU.pvRomBank = GSU.apvRomBank[GSU.vRomBankReg]; + CLRFLAGS; + R15++; +} + +/* e0-ee - dec rn - decrement by one */ +#define FX_DEC(reg) \ +GSU.avReg[reg] -= 1; \ +GSU.vSign = GSU.avReg[reg]; \ +GSU.vZero = GSU.avReg[reg]; \ +CLRFLAGS; R15++; +static inline void fx_dec_r0() { FX_DEC(0); } +static inline void fx_dec_r1() { FX_DEC(1); } +static inline void fx_dec_r2() { FX_DEC(2); } +static inline void fx_dec_r3() { FX_DEC(3); } +static inline void fx_dec_r4() { FX_DEC(4); } +static inline void fx_dec_r5() { FX_DEC(5); } +static inline void fx_dec_r6() { FX_DEC(6); } +static inline void fx_dec_r7() { FX_DEC(7); } +static inline void fx_dec_r8() { FX_DEC(8); } +static inline void fx_dec_r9() { FX_DEC(9); } +static inline void fx_dec_r10() { FX_DEC(10); } +static inline void fx_dec_r11() { FX_DEC(11); } +static inline void fx_dec_r12() { FX_DEC(12); } +static inline void fx_dec_r13() { FX_DEC(13); } +static inline void fx_dec_r14() { FX_DEC(14); READR14; } + +/* ef - getb - get byte from ROM at address R14 */ +static inline void fx_getb() +{ + uint32 v; +#ifndef FX_DO_ROMBUFFER + v = (uint32)ROM(R14); +#else + v = (uint32)GSU.vRomBuffer; +#endif + R15++; DREG = v; + TESTR14; + CLRFLAGS; +} + +/* ef(ALT1) - getbh - get high-byte from ROM at address R14 */ +static inline void fx_getbh() +{ + uint32 v; +#ifndef FX_DO_ROMBUFFER + uint32 c; + c = (uint32)ROM(R14); +#else + uint32 c = USEX8(GSU.vRomBuffer); +#endif + v = USEX8(SREG) | (c<<8); + R15++; DREG = v; + TESTR14; + CLRFLAGS; +} + +/* ef(ALT2) - getbl - get low-byte from ROM at address R14 */ +static inline void fx_getbl() +{ + uint32 v; +#ifndef FX_DO_ROMBUFFER + uint32 c; + c = (uint32)ROM(R14); +#else + uint32 c = USEX8(GSU.vRomBuffer); +#endif + v = (SREG & 0xff00) | c; + R15++; DREG = v; + TESTR14; + CLRFLAGS; +} + +/* ef(ALT3) - getbs - get sign extended byte from ROM at address R14 */ +static inline void fx_getbs() +{ + uint32 v; +#ifndef FX_DO_ROMBUFFER + int8 c; + c = ROM(R14); + v = SEX8(c); +#else + v = SEX8(GSU.vRomBuffer); +#endif + R15++; DREG = v; + TESTR14; + CLRFLAGS; +} + +/* f0-ff - iwt rn,#xx - immediate word transfer to register */ +#define FX_IWT(reg) \ +uint32 v = PIPE; R15++; FETCHPIPE; R15++; \ +v |= USEX8(PIPE) << 8; FETCHPIPE; R15++; \ +GSU.avReg[reg] = v; \ +CLRFLAGS; +static inline void fx_iwt_r0() { FX_IWT(0); } +static inline void fx_iwt_r1() { FX_IWT(1); } +static inline void fx_iwt_r2() { FX_IWT(2); } +static inline void fx_iwt_r3() { FX_IWT(3); } +static inline void fx_iwt_r4() { FX_IWT(4); } +static inline void fx_iwt_r5() { FX_IWT(5); } +static inline void fx_iwt_r6() { FX_IWT(6); } +static inline void fx_iwt_r7() { FX_IWT(7); } +static inline void fx_iwt_r8() { FX_IWT(8); } +static inline void fx_iwt_r9() { FX_IWT(9); } +static inline void fx_iwt_r10() { FX_IWT(10); } +static inline void fx_iwt_r11() { FX_IWT(11); } +static inline void fx_iwt_r12() { FX_IWT(12); } +static inline void fx_iwt_r13() { FX_IWT(13); } +static inline void fx_iwt_r14() { FX_IWT(14); READR14; } +static inline void fx_iwt_r15() { FX_IWT(15); } + +/* f0-ff(ALT1) - lm rn,(xx) - load word from RAM */ +#define FX_LM(reg) \ +GSU.vLastRamAdr = PIPE; R15++; FETCHPIPE; R15++; \ +GSU.vLastRamAdr |= USEX8(PIPE) << 8; FETCHPIPE; R15++; \ +GSU.avReg[reg] = RAM(GSU.vLastRamAdr); \ +GSU.avReg[reg] |= USEX8(RAM(GSU.vLastRamAdr^1)) << 8; \ +CLRFLAGS; +static inline void fx_lm_r0() { FX_LM(0); } +static inline void fx_lm_r1() { FX_LM(1); } +static inline void fx_lm_r2() { FX_LM(2); } +static inline void fx_lm_r3() { FX_LM(3); } +static inline void fx_lm_r4() { FX_LM(4); } +static inline void fx_lm_r5() { FX_LM(5); } +static inline void fx_lm_r6() { FX_LM(6); } +static inline void fx_lm_r7() { FX_LM(7); } +static inline void fx_lm_r8() { FX_LM(8); } +static inline void fx_lm_r9() { FX_LM(9); } +static inline void fx_lm_r10() { FX_LM(10); } +static inline void fx_lm_r11() { FX_LM(11); } +static inline void fx_lm_r12() { FX_LM(12); } +static inline void fx_lm_r13() { FX_LM(13); } +static inline void fx_lm_r14() { FX_LM(14); READR14; } +static inline void fx_lm_r15() { FX_LM(15); } + +/* f0-ff(ALT2) - sm (xx),rn - store word in RAM */ +/* If rn == r15, is the value of r15 before or after the extra bytes are read? */ +#define FX_SM(reg) \ +uint32 v = GSU.avReg[reg]; \ +GSU.vLastRamAdr = PIPE; R15++; FETCHPIPE; R15++; \ +GSU.vLastRamAdr |= USEX8(PIPE) << 8; FETCHPIPE; \ +RAM(GSU.vLastRamAdr) = (uint8)v; \ +RAM(GSU.vLastRamAdr^1) = (uint8)(v>>8); \ +CLRFLAGS; R15++; +static inline void fx_sm_r0() { FX_SM(0); } +static inline void fx_sm_r1() { FX_SM(1); } +static inline void fx_sm_r2() { FX_SM(2); } +static inline void fx_sm_r3() { FX_SM(3); } +static inline void fx_sm_r4() { FX_SM(4); } +static inline void fx_sm_r5() { FX_SM(5); } +static inline void fx_sm_r6() { FX_SM(6); } +static inline void fx_sm_r7() { FX_SM(7); } +static inline void fx_sm_r8() { FX_SM(8); } +static inline void fx_sm_r9() { FX_SM(9); } +static inline void fx_sm_r10() { FX_SM(10); } +static inline void fx_sm_r11() { FX_SM(11); } +static inline void fx_sm_r12() { FX_SM(12); } +static inline void fx_sm_r13() { FX_SM(13); } +static inline void fx_sm_r14() { FX_SM(14); } +static inline void fx_sm_r15() { FX_SM(15); } + +/*** GSU executions functions ***/ + +static uint32 fx_run(uint32 nInstructions) +{ + GSU.vCounter = nInstructions; + READR14; + while( TF(G) && (GSU.vCounter-- > 0) ) + FX_STEP; + /* +#ifndef FX_ADDRESS_CHECK + GSU.vPipeAdr = USEX16(R15-1) | (USEX8(GSU.vPrgBankReg)<<16); +#endif +*/ + return (nInstructions - GSU.vInstCount); +} + +static uint32 fx_run_to_breakpoint(uint32 nInstructions) +{ + uint32 vCounter = 0; + while(TF(G) && vCounter < nInstructions) + { + vCounter++; + FX_STEP; + if(USEX16(R15) == GSU.vBreakPoint) + { + GSU.vErrorCode = FX_BREAKPOINT; + break; + } + } + /* +#ifndef FX_ADDRESS_CHECK + GSU.vPipeAdr = USEX16(R15-1) | (USEX8(GSU.vPrgBankReg)<<16); +#endif +*/ + return vCounter; +} + +static uint32 fx_step_over(uint32 nInstructions) +{ + uint32 vCounter = 0; + while(TF(G) && vCounter < nInstructions) + { + vCounter++; + FX_STEP; + if(USEX16(R15) == GSU.vBreakPoint) + { + GSU.vErrorCode = FX_BREAKPOINT; + break; + } + if(USEX16(R15) == GSU.vStepPoint) + break; + } + /* +#ifndef FX_ADDRESS_CHECK + GSU.vPipeAdr = USEX16(R15-1) | (USEX8(GSU.vPrgBankReg)<<16); +#endif +*/ + return vCounter; +} + +#ifdef FX_FUNCTION_TABLE +uint32 (*FX_FUNCTION_TABLE[])(uint32) = +#else +uint32 (*fx_apfFunctionTable[])(uint32) = +#endif +{ + &fx_run, + &fx_run_to_breakpoint, + &fx_step_over, +}; + +/*** Special table for the different plot configurations ***/ + +#ifdef FX_PLOT_TABLE +void (*FX_PLOT_TABLE[])() = +#else +void (*fx_apfPlotTable[])() = +#endif +{ + &fx_plot_2bit, &fx_plot_4bit, &fx_plot_4bit, &fx_plot_8bit, &fx_plot_obj, + &fx_rpix_2bit, &fx_rpix_4bit, &fx_rpix_4bit, &fx_rpix_8bit, &fx_rpix_obj, +}; + +/*** Opcode table ***/ + +#ifdef FX_OPCODE_TABLE +void (*FX_OPCODE_TABLE[])() = +#else +void (*fx_apfOpcodeTable[])() = +#endif +{ + /* + * ALT0 Table + */ + /* 00 - 0f */ + &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt, + &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs, + /* 10 - 1f */ + &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7, + &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15, + /* 20 - 2f */ + &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7, + &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15, + /* 30 - 3f */ + &fx_stw_r0, &fx_stw_r1, &fx_stw_r2, &fx_stw_r3, &fx_stw_r4, &fx_stw_r5, &fx_stw_r6, &fx_stw_r7, + &fx_stw_r8, &fx_stw_r9, &fx_stw_r10, &fx_stw_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3, + /* 40 - 4f */ + &fx_ldw_r0, &fx_ldw_r1, &fx_ldw_r2, &fx_ldw_r3, &fx_ldw_r4, &fx_ldw_r5, &fx_ldw_r6, &fx_ldw_r7, + &fx_ldw_r8, &fx_ldw_r9, &fx_ldw_r10, &fx_ldw_r11, &fx_plot_2bit,&fx_swap, &fx_color, &fx_not, + /* 50 - 5f */ + &fx_add_r0, &fx_add_r1, &fx_add_r2, &fx_add_r3, &fx_add_r4, &fx_add_r5, &fx_add_r6, &fx_add_r7, + &fx_add_r8, &fx_add_r9, &fx_add_r10, &fx_add_r11, &fx_add_r12, &fx_add_r13, &fx_add_r14, &fx_add_r15, + /* 60 - 6f */ + &fx_sub_r0, &fx_sub_r1, &fx_sub_r2, &fx_sub_r3, &fx_sub_r4, &fx_sub_r5, &fx_sub_r6, &fx_sub_r7, + &fx_sub_r8, &fx_sub_r9, &fx_sub_r10, &fx_sub_r11, &fx_sub_r12, &fx_sub_r13, &fx_sub_r14, &fx_sub_r15, + /* 70 - 7f */ + &fx_merge, &fx_and_r1, &fx_and_r2, &fx_and_r3, &fx_and_r4, &fx_and_r5, &fx_and_r6, &fx_and_r7, + &fx_and_r8, &fx_and_r9, &fx_and_r10, &fx_and_r11, &fx_and_r12, &fx_and_r13, &fx_and_r14, &fx_and_r15, + /* 80 - 8f */ + &fx_mult_r0, &fx_mult_r1, &fx_mult_r2, &fx_mult_r3, &fx_mult_r4, &fx_mult_r5, &fx_mult_r6, &fx_mult_r7, + &fx_mult_r8, &fx_mult_r9, &fx_mult_r10, &fx_mult_r11, &fx_mult_r12, &fx_mult_r13, &fx_mult_r14, &fx_mult_r15, + /* 90 - 9f */ + &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_asr, &fx_ror, + &fx_jmp_r8, &fx_jmp_r9, &fx_jmp_r10, &fx_jmp_r11, &fx_jmp_r12, &fx_jmp_r13, &fx_lob, &fx_fmult, + /* a0 - af */ + &fx_ibt_r0, &fx_ibt_r1, &fx_ibt_r2, &fx_ibt_r3, &fx_ibt_r4, &fx_ibt_r5, &fx_ibt_r6, &fx_ibt_r7, + &fx_ibt_r8, &fx_ibt_r9, &fx_ibt_r10, &fx_ibt_r11, &fx_ibt_r12, &fx_ibt_r13, &fx_ibt_r14, &fx_ibt_r15, + /* b0 - bf */ + &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7, + &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15, + /* c0 - cf */ + &fx_hib, &fx_or_r1, &fx_or_r2, &fx_or_r3, &fx_or_r4, &fx_or_r5, &fx_or_r6, &fx_or_r7, + &fx_or_r8, &fx_or_r9, &fx_or_r10, &fx_or_r11, &fx_or_r12, &fx_or_r13, &fx_or_r14, &fx_or_r15, + /* d0 - df */ + &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7, + &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_getc, + /* e0 - ef */ + &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7, + &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getb, + /* f0 - ff */ + &fx_iwt_r0, &fx_iwt_r1, &fx_iwt_r2, &fx_iwt_r3, &fx_iwt_r4, &fx_iwt_r5, &fx_iwt_r6, &fx_iwt_r7, + &fx_iwt_r8, &fx_iwt_r9, &fx_iwt_r10, &fx_iwt_r11, &fx_iwt_r12, &fx_iwt_r13, &fx_iwt_r14, &fx_iwt_r15, + + /* + * ALT1 Table + */ + + /* 00 - 0f */ + &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt, + &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs, + /* 10 - 1f */ + &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7, + &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15, + /* 20 - 2f */ + &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7, + &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15, + /* 30 - 3f */ + &fx_stb_r0, &fx_stb_r1, &fx_stb_r2, &fx_stb_r3, &fx_stb_r4, &fx_stb_r5, &fx_stb_r6, &fx_stb_r7, + &fx_stb_r8, &fx_stb_r9, &fx_stb_r10, &fx_stb_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3, + /* 40 - 4f */ + &fx_ldb_r0, &fx_ldb_r1, &fx_ldb_r2, &fx_ldb_r3, &fx_ldb_r4, &fx_ldb_r5, &fx_ldb_r6, &fx_ldb_r7, + &fx_ldb_r8, &fx_ldb_r9, &fx_ldb_r10, &fx_ldb_r11, &fx_rpix_2bit,&fx_swap, &fx_cmode, &fx_not, + /* 50 - 5f */ + &fx_adc_r0, &fx_adc_r1, &fx_adc_r2, &fx_adc_r3, &fx_adc_r4, &fx_adc_r5, &fx_adc_r6, &fx_adc_r7, + &fx_adc_r8, &fx_adc_r9, &fx_adc_r10, &fx_adc_r11, &fx_adc_r12, &fx_adc_r13, &fx_adc_r14, &fx_adc_r15, + /* 60 - 6f */ + &fx_sbc_r0, &fx_sbc_r1, &fx_sbc_r2, &fx_sbc_r3, &fx_sbc_r4, &fx_sbc_r5, &fx_sbc_r6, &fx_sbc_r7, + &fx_sbc_r8, &fx_sbc_r9, &fx_sbc_r10, &fx_sbc_r11, &fx_sbc_r12, &fx_sbc_r13, &fx_sbc_r14, &fx_sbc_r15, + /* 70 - 7f */ + &fx_merge, &fx_bic_r1, &fx_bic_r2, &fx_bic_r3, &fx_bic_r4, &fx_bic_r5, &fx_bic_r6, &fx_bic_r7, + &fx_bic_r8, &fx_bic_r9, &fx_bic_r10, &fx_bic_r11, &fx_bic_r12, &fx_bic_r13, &fx_bic_r14, &fx_bic_r15, + /* 80 - 8f */ + &fx_umult_r0,&fx_umult_r1,&fx_umult_r2, &fx_umult_r3, &fx_umult_r4, &fx_umult_r5, &fx_umult_r6, &fx_umult_r7, + &fx_umult_r8,&fx_umult_r9,&fx_umult_r10,&fx_umult_r11,&fx_umult_r12,&fx_umult_r13,&fx_umult_r14,&fx_umult_r15, + /* 90 - 9f */ + &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_div2, &fx_ror, + &fx_ljmp_r8, &fx_ljmp_r9, &fx_ljmp_r10, &fx_ljmp_r11, &fx_ljmp_r12, &fx_ljmp_r13, &fx_lob, &fx_lmult, + /* a0 - af */ + &fx_lms_r0, &fx_lms_r1, &fx_lms_r2, &fx_lms_r3, &fx_lms_r4, &fx_lms_r5, &fx_lms_r6, &fx_lms_r7, + &fx_lms_r8, &fx_lms_r9, &fx_lms_r10, &fx_lms_r11, &fx_lms_r12, &fx_lms_r13, &fx_lms_r14, &fx_lms_r15, + /* b0 - bf */ + &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7, + &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15, + /* c0 - cf */ + &fx_hib, &fx_xor_r1, &fx_xor_r2, &fx_xor_r3, &fx_xor_r4, &fx_xor_r5, &fx_xor_r6, &fx_xor_r7, + &fx_xor_r8, &fx_xor_r9, &fx_xor_r10, &fx_xor_r11, &fx_xor_r12, &fx_xor_r13, &fx_xor_r14, &fx_xor_r15, + /* d0 - df */ + &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7, + &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_getc, + /* e0 - ef */ + &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7, + &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getbh, + /* f0 - ff */ + &fx_lm_r0, &fx_lm_r1, &fx_lm_r2, &fx_lm_r3, &fx_lm_r4, &fx_lm_r5, &fx_lm_r6, &fx_lm_r7, + &fx_lm_r8, &fx_lm_r9, &fx_lm_r10, &fx_lm_r11, &fx_lm_r12, &fx_lm_r13, &fx_lm_r14, &fx_lm_r15, + + /* + * ALT2 Table + */ + + /* 00 - 0f */ + &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt, + &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs, + /* 10 - 1f */ + &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7, + &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15, + /* 20 - 2f */ + &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7, + &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15, + /* 30 - 3f */ + &fx_stw_r0, &fx_stw_r1, &fx_stw_r2, &fx_stw_r3, &fx_stw_r4, &fx_stw_r5, &fx_stw_r6, &fx_stw_r7, + &fx_stw_r8, &fx_stw_r9, &fx_stw_r10, &fx_stw_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3, + /* 40 - 4f */ + &fx_ldw_r0, &fx_ldw_r1, &fx_ldw_r2, &fx_ldw_r3, &fx_ldw_r4, &fx_ldw_r5, &fx_ldw_r6, &fx_ldw_r7, + &fx_ldw_r8, &fx_ldw_r9, &fx_ldw_r10, &fx_ldw_r11, &fx_plot_2bit,&fx_swap, &fx_color, &fx_not, + /* 50 - 5f */ + &fx_add_i0, &fx_add_i1, &fx_add_i2, &fx_add_i3, &fx_add_i4, &fx_add_i5, &fx_add_i6, &fx_add_i7, + &fx_add_i8, &fx_add_i9, &fx_add_i10, &fx_add_i11, &fx_add_i12, &fx_add_i13, &fx_add_i14, &fx_add_i15, + /* 60 - 6f */ + &fx_sub_i0, &fx_sub_i1, &fx_sub_i2, &fx_sub_i3, &fx_sub_i4, &fx_sub_i5, &fx_sub_i6, &fx_sub_i7, + &fx_sub_i8, &fx_sub_i9, &fx_sub_i10, &fx_sub_i11, &fx_sub_i12, &fx_sub_i13, &fx_sub_i14, &fx_sub_i15, + /* 70 - 7f */ + &fx_merge, &fx_and_i1, &fx_and_i2, &fx_and_i3, &fx_and_i4, &fx_and_i5, &fx_and_i6, &fx_and_i7, + &fx_and_i8, &fx_and_i9, &fx_and_i10, &fx_and_i11, &fx_and_i12, &fx_and_i13, &fx_and_i14, &fx_and_i15, + /* 80 - 8f */ + &fx_mult_i0, &fx_mult_i1, &fx_mult_i2, &fx_mult_i3, &fx_mult_i4, &fx_mult_i5, &fx_mult_i6, &fx_mult_i7, + &fx_mult_i8, &fx_mult_i9, &fx_mult_i10, &fx_mult_i11, &fx_mult_i12, &fx_mult_i13, &fx_mult_i14, &fx_mult_i15, + /* 90 - 9f */ + &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_asr, &fx_ror, + &fx_jmp_r8, &fx_jmp_r9, &fx_jmp_r10, &fx_jmp_r11, &fx_jmp_r12, &fx_jmp_r13, &fx_lob, &fx_fmult, + /* a0 - af */ + &fx_sms_r0, &fx_sms_r1, &fx_sms_r2, &fx_sms_r3, &fx_sms_r4, &fx_sms_r5, &fx_sms_r6, &fx_sms_r7, + &fx_sms_r8, &fx_sms_r9, &fx_sms_r10, &fx_sms_r11, &fx_sms_r12, &fx_sms_r13, &fx_sms_r14, &fx_sms_r15, + /* b0 - bf */ + &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7, + &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15, + /* c0 - cf */ + &fx_hib, &fx_or_i1, &fx_or_i2, &fx_or_i3, &fx_or_i4, &fx_or_i5, &fx_or_i6, &fx_or_i7, + &fx_or_i8, &fx_or_i9, &fx_or_i10, &fx_or_i11, &fx_or_i12, &fx_or_i13, &fx_or_i14, &fx_or_i15, + /* d0 - df */ + &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7, + &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_ramb, + /* e0 - ef */ + &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7, + &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getbl, + /* f0 - ff */ + &fx_sm_r0, &fx_sm_r1, &fx_sm_r2, &fx_sm_r3, &fx_sm_r4, &fx_sm_r5, &fx_sm_r6, &fx_sm_r7, + &fx_sm_r8, &fx_sm_r9, &fx_sm_r10, &fx_sm_r11, &fx_sm_r12, &fx_sm_r13, &fx_sm_r14, &fx_sm_r15, + + /* + * ALT3 Table + */ + + /* 00 - 0f */ + &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt, + &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs, + /* 10 - 1f */ + &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7, + &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15, + /* 20 - 2f */ + &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7, + &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15, + /* 30 - 3f */ + &fx_stb_r0, &fx_stb_r1, &fx_stb_r2, &fx_stb_r3, &fx_stb_r4, &fx_stb_r5, &fx_stb_r6, &fx_stb_r7, + &fx_stb_r8, &fx_stb_r9, &fx_stb_r10, &fx_stb_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3, + /* 40 - 4f */ + &fx_ldb_r0, &fx_ldb_r1, &fx_ldb_r2, &fx_ldb_r3, &fx_ldb_r4, &fx_ldb_r5, &fx_ldb_r6, &fx_ldb_r7, + &fx_ldb_r8, &fx_ldb_r9, &fx_ldb_r10, &fx_ldb_r11, &fx_rpix_2bit,&fx_swap, &fx_cmode, &fx_not, + /* 50 - 5f */ + &fx_adc_i0, &fx_adc_i1, &fx_adc_i2, &fx_adc_i3, &fx_adc_i4, &fx_adc_i5, &fx_adc_i6, &fx_adc_i7, + &fx_adc_i8, &fx_adc_i9, &fx_adc_i10, &fx_adc_i11, &fx_adc_i12, &fx_adc_i13, &fx_adc_i14, &fx_adc_i15, + /* 60 - 6f */ + &fx_cmp_r0, &fx_cmp_r1, &fx_cmp_r2, &fx_cmp_r3, &fx_cmp_r4, &fx_cmp_r5, &fx_cmp_r6, &fx_cmp_r7, + &fx_cmp_r8, &fx_cmp_r9, &fx_cmp_r10, &fx_cmp_r11, &fx_cmp_r12, &fx_cmp_r13, &fx_cmp_r14, &fx_cmp_r15, + /* 70 - 7f */ + &fx_merge, &fx_bic_i1, &fx_bic_i2, &fx_bic_i3, &fx_bic_i4, &fx_bic_i5, &fx_bic_i6, &fx_bic_i7, + &fx_bic_i8, &fx_bic_i9, &fx_bic_i10, &fx_bic_i11, &fx_bic_i12, &fx_bic_i13, &fx_bic_i14, &fx_bic_i15, + /* 80 - 8f */ + &fx_umult_i0,&fx_umult_i1,&fx_umult_i2, &fx_umult_i3, &fx_umult_i4, &fx_umult_i5, &fx_umult_i6, &fx_umult_i7, + &fx_umult_i8,&fx_umult_i9,&fx_umult_i10,&fx_umult_i11,&fx_umult_i12,&fx_umult_i13,&fx_umult_i14,&fx_umult_i15, + /* 90 - 9f */ + &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_div2, &fx_ror, + &fx_ljmp_r8, &fx_ljmp_r9, &fx_ljmp_r10, &fx_ljmp_r11, &fx_ljmp_r12, &fx_ljmp_r13, &fx_lob, &fx_lmult, + /* a0 - af */ + &fx_lms_r0, &fx_lms_r1, &fx_lms_r2, &fx_lms_r3, &fx_lms_r4, &fx_lms_r5, &fx_lms_r6, &fx_lms_r7, + &fx_lms_r8, &fx_lms_r9, &fx_lms_r10, &fx_lms_r11, &fx_lms_r12, &fx_lms_r13, &fx_lms_r14, &fx_lms_r15, + /* b0 - bf */ + &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7, + &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15, + /* c0 - cf */ + &fx_hib, &fx_xor_i1, &fx_xor_i2, &fx_xor_i3, &fx_xor_i4, &fx_xor_i5, &fx_xor_i6, &fx_xor_i7, + &fx_xor_i8, &fx_xor_i9, &fx_xor_i10, &fx_xor_i11, &fx_xor_i12, &fx_xor_i13, &fx_xor_i14, &fx_xor_i15, + /* d0 - df */ + &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7, + &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_romb, + /* e0 - ef */ + &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7, + &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getbs, + /* f0 - ff */ + &fx_lm_r0, &fx_lm_r1, &fx_lm_r2, &fx_lm_r3, &fx_lm_r4, &fx_lm_r5, &fx_lm_r6, &fx_lm_r7, + &fx_lm_r8, &fx_lm_r9, &fx_lm_r10, &fx_lm_r11, &fx_lm_r12, &fx_lm_r13, &fx_lm_r14, &fx_lm_r15, +}; + diff --git a/src/fxinst.h b/src/fxinst.h new file mode 100644 index 0000000..bc0143c --- /dev/null +++ b/src/fxinst.h @@ -0,0 +1,475 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#ifndef _FXINST_H_ +#define _FXINST_H_ 1 + +/* + * FxChip(GSU) register space specification + * (Register address space 3000->32ff) + * + * The 16 generic 16 bit registers: + * (Some have a special function in special circumstances) + * 3000 - R0 default source/destination register + * 3002 - R1 pixel plot X position register + * 3004 - R2 pixel plot Y position register + * 3006 - R3 + * 3008 - R4 lower 16 bit result of lmult + * 300a - R5 + * 300c - R6 multiplier for fmult and lmult + * 300e - R7 fixed point texel X position for merge + * 3010 - R8 fixed point texel Y position for merge + * 3012 - R9 + * 3014 - R10 + * 3016 - R11 return address set by link + * 3018 - R12 loop counter + * 301a - R13 loop point address + * 301c - R14 rom address for getb, getbh, getbl, getbs + * 301e - R15 program counter + * + * 3020-302f - unused + * + * Other internal registers + * 3030 - SFR status flag register (16bit) + * 3032 - unused + * 3033 - BRAMR Backup RAM register (8bit) + * 3034 - PBR program bank register (8bit) + * 3035 - unused + * 3036 - ROMBR rom bank register (8bit) + * 3037 - CFGR control flags register (8bit) + * 3038 - SCBR screen base register (8bit) + * 3039 - CLSR clock speed register (8bit) + * 303a - SCMR screen mode register (8bit) + * 303b - VCR version code register (8bit) (read only) + * 303c - RAMBR ram bank register (8bit) + * 303d - unused + * 303e - CBR cache base register (16bit) + * + * 3040-30ff - unused + * + * 3100-32ff - CACHERAM 512 bytes of GSU cache memory + * + * SFR status flag register bits: + * 0 - + * 1 Z Zero flag + * 2 CY Carry flag + * 3 S Sign flag + * 4 OV Overflow flag + * 5 G Go flag (set to 1 when the GSU is running) + * 6 R Set to 1 when reading ROM using R14 address + * 7 - + * 8 ALT1 Mode set-up flag for the next instruction + * 9 ALT2 Mode set-up flag for the next instruction + * 10 IL Immediate lower 8-bit flag + * 11 IH Immediate higher 8-bit flag + * 12 B Set to 1 when the WITH instruction is executed + * 13 - + * 14 - + * 15 IRQ Set to 1 when GSU caused an interrupt + * Set to 0 when read by 658c16 + * + * BRAMR = 0, BackupRAM is disabled + * BRAMR = 1, BackupRAM is enabled + * + * CFGR control flags register bits: + * 0 - + * 1 - + * 2 - + * 3 - + * 4 - + * 5 MS0 Multiplier speed, 0=standard, 1=high speed + * 6 - + * 7 IRQ Set to 1 when GSU interrupt request is masked + * + * CLSR clock speed register bits: + * 0 CLSR clock speed, 0 = 10.7Mhz, 1 = 21.4Mhz + * + * SCMR screen mode register bits: + * 0 MD0 color depth mode bit 0 + * 1 MD1 color depth mode bit 1 + * 2 HT0 screen height bit 1 + * 3 RAN RAM access control + * 4 RON ROM access control + * 5 HT1 screen height bit 2 + * 6 - + * 7 - + * + * RON = 0 SNES CPU has ROM access + * RON = 1 GSU has ROM access + * + * RAN = 0 SNES has game pak RAM access + * RAN = 1 GSU has game pak RAM access + * + * HT1 HT0 Screen height mode + * 0 0 128 pixels high + * 0 1 160 pixels high + * 1 0 192 pixels high + * 1 1 OBJ mode + * + * MD1 MD0 Color depth mode + * 0 0 4 color mode + * 0 1 16 color mode + * 1 0 not used + * 1 1 256 color mode + * + * CBR cache base register bits: + * 15-4 Specify base address for data to cache from ROM or RAM + * 3-0 Are 0 when address is read + * + * Write access to the program counter (301e) from + * the SNES-CPU will start the GSU, and it will not + * stop until it reaches a stop instruction. + * + */ + +/* Number of banks in GSU RAM */ +#define FX_RAM_BANKS 4 + +/* Emulate proper R14 ROM access (slower, but safer) */ +/* #define FX_DO_ROMBUFFER */ + +/* Address checking (definately slow) */ +/* #define FX_ADDRESS_CHECK */ + +struct FxRegs_s +{ + /* FxChip registers */ + uint32 avReg[16]; /* 16 Generic registers */ + uint32 vColorReg; /* Internal color register */ + uint32 vPlotOptionReg; /* Plot option register */ + uint32 vStatusReg; /* Status register */ + uint32 vPrgBankReg; /* Program bank index register */ + uint32 vRomBankReg; /* Rom bank index register */ + uint32 vRamBankReg; /* Ram bank index register */ + uint32 vCacheBaseReg; /* Cache base address register */ + uint32 vCacheFlags; /* Saying what parts of the cache was written to */ + uint32 vLastRamAdr; /* Last RAM address accessed */ + uint32 * pvDreg; /* Pointer to current destination register */ + uint32 * pvSreg; /* Pointer to current source register */ + uint8 vRomBuffer; /* Current byte read by R14 */ + uint8 vPipe; /* Instructionset pipe */ + uint32 vPipeAdr; /* The address of where the pipe was read from */ + + /* status register optimization stuff */ + uint32 vSign; /* v & 0x8000 */ + uint32 vZero; /* v == 0 */ + uint32 vCarry; /* a value of 1 or 0 */ + int32 vOverflow; /* (v >= 0x8000 || v < -0x8000) */ + + /* Other emulator variables */ + + int32 vErrorCode; + uint32 vIllegalAddress; + + uint8 bBreakPoint; + uint32 vBreakPoint; + uint32 vStepPoint; + + uint8 * pvRegisters; /* 768 bytes located in the memory at address 0x3000 */ + uint32 nRamBanks; /* Number of 64kb-banks in FxRam (Don't confuse it with SNES-Ram!!!) */ + uint8 * pvRam; /* Pointer to FxRam */ + uint32 nRomBanks; /* Number of 32kb-banks in Cart-ROM */ + uint8 * pvRom; /* Pointer to Cart-ROM */ + + uint32 vMode; /* Color depth/mode */ + uint32 vPrevMode; /* Previous depth */ + uint8 * pvScreenBase; + uint8 * apvScreen[32]; /* Pointer to each of the 32 screen colums */ + int x[32]; + uint32 vScreenHeight; /* 128, 160, 192 or 256 (could be overriden by cmode) */ + uint32 vScreenRealHeight; /* 128, 160, 192 or 256 */ + uint32 vPrevScreenHeight; + uint32 vScreenSize; + void (*pfPlot)(); + void (*pfRpix)(); + + uint8 * pvRamBank; /* Pointer to current RAM-bank */ + uint8 * pvRomBank; /* Pointer to current ROM-bank */ + uint8 * pvPrgBank; /* Pointer to current program ROM-bank */ + + uint8 * apvRamBank[FX_RAM_BANKS];/* Ram bank table (max 256kb) */ + uint8 * apvRomBank[256]; /* Rom bank table */ + + uint8 bCacheActive; + uint8 * pvCache; /* Pointer to the GSU cache */ + uint8 avCacheBackup[512]; /* Backup of ROM when the cache has replaced it */ + uint32 vCounter; + uint32 vInstCount; + uint32 vSCBRDirty; /* if SCBR is written, our cached screen pointers need updating */ +}; + +#define FxRegs_s_null { \ + {0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + NULL, NULL, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, NULL, 0, NULL, 0, NULL, 0, \ + 0, NULL, {NULL}, {0}, 0, 0, 0, 0, NULL, NULL, \ + NULL, NULL, NULL, {NULL}, {NULL}, 0, NULL, {0}, 0, 0, \ +} + +/* GSU registers */ +#define GSU_R0 0x000 +#define GSU_R1 0x002 +#define GSU_R2 0x004 +#define GSU_R3 0x006 +#define GSU_R4 0x008 +#define GSU_R5 0x00a +#define GSU_R6 0x00c +#define GSU_R7 0x00e +#define GSU_R8 0x010 +#define GSU_R9 0x012 +#define GSU_R10 0x014 +#define GSU_R11 0x016 +#define GSU_R12 0x018 +#define GSU_R13 0x01a +#define GSU_R14 0x01c +#define GSU_R15 0x01e +#define GSU_SFR 0x030 +#define GSU_BRAMR 0x033 +#define GSU_PBR 0x034 +#define GSU_ROMBR 0x036 +#define GSU_CFGR 0x037 +#define GSU_SCBR 0x038 +#define GSU_CLSR 0x039 +#define GSU_SCMR 0x03a +#define GSU_VCR 0x03b +#define GSU_RAMBR 0x03c +#define GSU_CBR 0x03e +#define GSU_CACHERAM 0x100 + +/* SFR flags */ +#define FLG_Z (1<<1) +#define FLG_CY (1<<2) +#define FLG_S (1<<3) +#define FLG_OV (1<<4) +#define FLG_G (1<<5) +#define FLG_R (1<<6) +#define FLG_ALT1 (1<<8) +#define FLG_ALT2 (1<<9) +#define FLG_IL (1<<10) +#define FLG_IH (1<<11) +#define FLG_B (1<<12) +#define FLG_IRQ (1<<15) + +/* Test flag */ +#define TF(a) (GSU.vStatusReg & FLG_##a ) +#define CF(a) (GSU.vStatusReg &= ~FLG_##a ) +#define SF(a) (GSU.vStatusReg |= FLG_##a ) + +/* Test and set flag if condition, clear if not */ +#define TS(a,b) GSU.vStatusReg = ( (GSU.vStatusReg & (~FLG_##a)) | ( (!!(##b)) * FLG_##a ) ) + +/* Testing ALT1 & ALT2 bits */ +#define ALT0 (!TF(ALT1)&&!TF(ALT2)) +#define ALT1 (TF(ALT1)&&!TF(ALT2)) +#define ALT2 (!TF(ALT1)&&TF(ALT2)) +#define ALT3 (TF(ALT1)&&TF(ALT2)) + +/* Sign extend from 8/16 bit to 32 bit */ +#define SEX16(a) ((int32)((int16)(a))) +#define SEX8(a) ((int32)((int8)(a))) + +/* Unsign extend from 8/16 bit to 32 bit */ +#define USEX16(a) ((uint32)((uint16)(a))) +#define USEX8(a) ((uint32)((uint8)(a))) + +#define SUSEX16(a) ((int32)((uint16)(a))) + +/* Set/Clr Sign and Zero flag */ +#define TSZ(num) TS(S, (num & 0x8000)); TS(Z, (!USEX16(num)) ) + +/* Clear flags */ +#define CLRFLAGS GSU.vStatusReg &= ~(FLG_ALT1|FLG_ALT2|FLG_B); GSU.pvDreg = GSU.pvSreg = &R0; + +/* Read current RAM-Bank */ +#define RAM(adr) GSU.pvRamBank[USEX16(adr)] + +/* Read current ROM-Bank */ +#define ROM(idx) (GSU.pvRomBank[USEX16(idx)]) + +/* Access the current value in the pipe */ +#define PIPE GSU.vPipe + +/* Access data in the current program bank */ +#define PRGBANK(idx) GSU.pvPrgBank[USEX16(idx)] + +/* Update pipe from ROM */ +#if 0 +#define FETCHPIPE { PIPE = PRGBANK(R15); GSU.vPipeAdr = (GSU.vPrgBankReg<<16) + R15; } +#else +#define FETCHPIPE { PIPE = PRGBANK(R15); } +#endif + +/* ABS */ +#define ABS(x) ((x)<0?-(x):(x)) + +/* Access source register */ +#define SREG (*GSU.pvSreg) + +/* Access destination register */ +#define DREG (*GSU.pvDreg) + +#ifndef FX_DO_ROMBUFFER + +/* Don't read R14 */ +#define READR14 + +/* Don't test and/or read R14 */ +#define TESTR14 + +#else + +/* Read R14 */ +#define READR14 GSU.vRomBuffer = ROM(R14) + +/* Test and/or read R14 */ +#define TESTR14 if(GSU.pvDreg == &R14) READR14 + +#endif + +/* Access to registers */ +#define R0 GSU.avReg[0] +#define R1 GSU.avReg[1] +#define R2 GSU.avReg[2] +#define R3 GSU.avReg[3] +#define R4 GSU.avReg[4] +#define R5 GSU.avReg[5] +#define R6 GSU.avReg[6] +#define R7 GSU.avReg[7] +#define R8 GSU.avReg[8] +#define R9 GSU.avReg[9] +#define R10 GSU.avReg[10] +#define R11 GSU.avReg[11] +#define R12 GSU.avReg[12] +#define R13 GSU.avReg[13] +#define R14 GSU.avReg[14] +#define R15 GSU.avReg[15] +#define SFR GSU.vStatusReg +#define PBR GSU.vPrgBankReg +#define ROMBR GSU.vRomBankReg +#define RAMBR GSU.vRamBankReg +#define CBR GSU.vCacheBaseReg +#define SCBR USEX8(GSU.pvRegisters[GSU_SCBR]) +#define SCMR USEX8(GSU.pvRegisters[GSU_SCMR]) +#define COLR GSU.vColorReg +#define POR GSU.vPlotOptionReg +#define BRAMR USEX8(GSU.pvRegisters[GSU_BRAMR]) +#define VCR USEX8(GSU.pvRegisters[GSU_VCR]) +#define CFGR USEX8(GSU.pvRegisters[GSU_CFGR]) +#define CLSR USEX8(GSU.pvRegisters[GSU_CLSR]) + +/* Execute instruction from the pipe, and fetch next byte to the pipe */ +#define FX_STEP { uint32 vOpcode = (uint32)PIPE; FETCHPIPE; \ +(*fx_ppfOpcodeTable[ (GSU.vStatusReg & 0x300) | vOpcode ])(); } \ + +#define FX_FUNCTION_RUN 0 +#define FX_FUNCTION_RUN_TO_BREAKPOINT 1 +#define FX_FUNCTION_STEP_OVER 2 + +extern uint32 (**fx_ppfFunctionTable)(uint32); +extern void (**fx_ppfPlotTable)(); +extern void (**fx_ppfOpcodeTable)(); + +extern uint32 (*fx_apfFunctionTable[])(uint32); +extern void (*fx_apfOpcodeTable[])(); +extern void (*fx_apfPlotTable[])(); +extern uint32 (*fx_a_apfFunctionTable[])(uint32); +extern void (*fx_a_apfOpcodeTable[])(); +extern void (*fx_a_apfPlotTable[])(); +extern uint32 (*fx_r_apfFunctionTable[])(uint32); +extern void (*fx_r_apfOpcodeTable[])(); +extern void (*fx_r_apfPlotTable[])(); +extern uint32 (*fx_ar_apfFunctionTable[])(uint32); +extern void (*fx_ar_apfOpcodeTable[])(); +extern void (*fx_ar_apfPlotTable[])(); + +/* Set this define if branches are relative to the instruction in the delay slot */ +/* (I think they are) */ +#define BRANCH_DELAY_RELATIVE + +#endif + diff --git a/src/fxinst.s b/src/fxinst.s new file mode 100644 index 0000000..f3302fe --- /dev/null +++ b/src/fxinst.s @@ -0,0 +1,44480 @@ + .file "fxinst.cpp" + .text + .align 2 + .type _Z7fx_stopv, %function +_Z7fx_stopv: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L5 + ldr r3, [r3, #72] + bic r2, r3, #32 + ldr r3, .L5 + str r2, [r3, #72] + ldr r2, .L5 + mov r3, #0 + str r3, [r2, #2036] + ldr r3, .L5 + ldr r2, [r3, #2036] + ldr r3, .L5 + str r2, [r3, #2040] + ldr r3, .L5 + ldr r3, [r3, #152] + add r3, r3, #55 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + cmp r3, #0 + blt .L2 + ldr r3, .L5 + ldr r3, [r3, #72] + orr r2, r3, #32768 + ldr r3, .L5 + str r2, [r3, #72] +.L2: + ldr r2, .L5 + mov r3, #0 + str r3, [r2, #68] + ldr r2, .L5 + mov r3, #1 + strb r3, [r2, #109] + ldr r3, .L5 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L5 + str r2, [r3, #72] + ldr r2, .L5 + ldr r3, .L5 + str r3, [r2, #104] + ldr r3, .L5 + ldr r2, [r3, #104] + ldr r3, .L5 + str r2, [r3, #100] + ldr r3, .L5 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L5 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L6: + .align 2 +.L5: + .word GSU + .size _Z7fx_stopv, .-_Z7fx_stopv + .global __gxx_personality_sj0 + .align 2 + .type _Z6fx_nopv, %function +_Z6fx_nopv: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L9 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L9 + str r2, [r3, #72] + ldr r2, .L9 + ldr r3, .L9 + str r3, [r2, #104] + ldr r3, .L9 + ldr r2, [r3, #104] + ldr r3, .L9 + str r2, [r3, #100] + ldr r3, .L9 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L9 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L10: + .align 2 +.L9: + .word GSU + .size _Z6fx_nopv, .-_Z6fx_nopv + .align 2 + .type _Z6fx_lsrv, %function +_Z6fx_lsrv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L15 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r2, r3, #1 + ldr r3, .L15 + str r2, [r3, #124] + ldr r3, .L15 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, lsr #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + str r3, [fp, #-16] + ldr r3, .L15 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L15 + str r2, [r3, #60] + ldr r3, .L15 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L15 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L15 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L15 + ldr r2, [r3, #100] + ldr r3, .L15+4 + cmp r2, r3 + bne .L12 + ldr r3, .L15 + ldr r2, [r3, #468] + ldr r3, .L15 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L15 + strb r3, [r2, #108] +.L12: + ldr r3, .L15 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L15 + str r2, [r3, #72] + ldr r2, .L15 + ldr r3, .L15 + str r3, [r2, #104] + ldr r3, .L15 + ldr r2, [r3, #104] + ldr r3, .L15 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L16: + .align 2 +.L15: + .word GSU + .word GSU+56 + .size _Z6fx_lsrv, .-_Z6fx_lsrv + .align 2 + .type _Z6fx_rolv, %function +_Z6fx_rolv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L21 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #1 + mov r3, r3, asl #16 + mov r2, r3, lsr #16 + ldr r3, .L21 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + str r3, [fp, #-16] + ldr r3, .L21 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #15 + and r2, r3, #1 + ldr r3, .L21 + str r2, [r3, #124] + ldr r3, .L21 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L21 + str r2, [r3, #60] + ldr r3, .L21 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L21 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L21 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L21 + ldr r2, [r3, #100] + ldr r3, .L21+4 + cmp r2, r3 + bne .L18 + ldr r3, .L21 + ldr r2, [r3, #468] + ldr r3, .L21 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L21 + strb r3, [r2, #108] +.L18: + ldr r3, .L21 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L21 + str r2, [r3, #72] + ldr r2, .L21 + ldr r3, .L21 + str r3, [r2, #104] + ldr r3, .L21 + ldr r2, [r3, #104] + ldr r3, .L21 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L22: + .align 2 +.L21: + .word GSU + .word GSU+56 + .size _Z6fx_rolv, .-_Z6fx_rolv + .align 2 + .type _Z6fx_brav, %function +_Z6fx_brav: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L25 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L25 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L25 + str r2, [r3, #60] + ldr r3, .L25 + ldr r2, [r3, #472] + ldr r3, .L25 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L25 + strb r3, [r2, #109] + ldr r3, .L25 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L25 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L26: + .align 2 +.L25: + .word GSU + .size _Z6fx_brav, .-_Z6fx_brav + .align 2 + .type _Z6fx_bltv, %function +_Z6fx_bltv: + @ args = 0, pretend = 0, frame = 12 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #12 + ldr r3, .L36 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L36 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L36 + str r2, [r3, #60] + ldr r3, .L36 + ldr r2, [r3, #472] + ldr r3, .L36 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L36 + strb r3, [r2, #109] + ldr r3, .L36 + ldr r3, [r3, #116] + and r3, r3, #32768 + cmp r3, #0 + moveq r2, #0 + movne r2, #1 + str r2, [fp, #-24] + ldr r3, .L36 + ldr r2, [r3, #128] + ldr r3, .L36+4 + cmp r2, r3 + bgt .L28 + ldr r3, .L36 + ldr r3, [r3, #128] + cmn r3, #32768 + bge .L30 +.L28: + mov r3, #1 + str r3, [fp, #-20] + b .L31 +.L30: + mov r2, #0 + str r2, [fp, #-20] +.L31: + ldr r3, [fp, #-20] + ldr r2, [fp, #-24] + cmp r2, r3 + beq .L32 + ldr r3, .L36 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L36 + str r2, [r3, #60] + b .L35 +.L32: + ldr r3, .L36 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L36 + str r2, [r3, #60] +.L35: + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L37: + .align 2 +.L36: + .word GSU + .word 32767 + .size _Z6fx_bltv, .-_Z6fx_bltv + .align 2 + .type _Z6fx_bgev, %function +_Z6fx_bgev: + @ args = 0, pretend = 0, frame = 12 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #12 + ldr r3, .L47 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L47 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L47 + str r2, [r3, #60] + ldr r3, .L47 + ldr r2, [r3, #472] + ldr r3, .L47 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L47 + strb r3, [r2, #109] + ldr r3, .L47 + ldr r3, [r3, #116] + and r3, r3, #32768 + cmp r3, #0 + moveq r2, #0 + movne r2, #1 + str r2, [fp, #-24] + ldr r3, .L47 + ldr r2, [r3, #128] + ldr r3, .L47+4 + cmp r2, r3 + bgt .L39 + ldr r3, .L47 + ldr r3, [r3, #128] + cmn r3, #32768 + bge .L41 +.L39: + mov r3, #1 + str r3, [fp, #-20] + b .L42 +.L41: + mov r2, #0 + str r2, [fp, #-20] +.L42: + ldr r3, [fp, #-20] + ldr r2, [fp, #-24] + cmp r2, r3 + bne .L43 + ldr r3, .L47 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L47 + str r2, [r3, #60] + b .L46 +.L43: + ldr r3, .L47 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L47 + str r2, [r3, #60] +.L46: + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L48: + .align 2 +.L47: + .word GSU + .word 32767 + .size _Z6fx_bgev, .-_Z6fx_bgev + .align 2 + .type _Z6fx_bnev, %function +_Z6fx_bnev: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L54 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L54 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L54 + str r2, [r3, #60] + ldr r3, .L54 + ldr r2, [r3, #472] + ldr r3, .L54 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L54 + strb r3, [r2, #109] + ldr r3, .L54 + ldr r3, [r3, #120] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + cmp r3, #0 + beq .L50 + ldr r3, .L54 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L54 + str r2, [r3, #60] + b .L53 +.L50: + ldr r3, .L54 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L54 + str r2, [r3, #60] +.L53: + ldmib sp, {fp, sp, pc} +.L55: + .align 2 +.L54: + .word GSU + .size _Z6fx_bnev, .-_Z6fx_bnev + .align 2 + .type _Z6fx_beqv, %function +_Z6fx_beqv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L61 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L61 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L61 + str r2, [r3, #60] + ldr r3, .L61 + ldr r2, [r3, #472] + ldr r3, .L61 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L61 + strb r3, [r2, #109] + ldr r3, .L61 + ldr r3, [r3, #120] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + cmp r3, #0 + bne .L57 + ldr r3, .L61 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L61 + str r2, [r3, #60] + b .L60 +.L57: + ldr r3, .L61 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L61 + str r2, [r3, #60] +.L60: + ldmib sp, {fp, sp, pc} +.L62: + .align 2 +.L61: + .word GSU + .size _Z6fx_beqv, .-_Z6fx_beqv + .align 2 + .type _Z6fx_bplv, %function +_Z6fx_bplv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L68 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L68 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L68 + str r2, [r3, #60] + ldr r3, .L68 + ldr r2, [r3, #472] + ldr r3, .L68 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L68 + strb r3, [r2, #109] + ldr r3, .L68 + ldr r3, [r3, #116] + and r3, r3, #32768 + cmp r3, #0 + bne .L64 + ldr r3, .L68 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L68 + str r2, [r3, #60] + b .L67 +.L64: + ldr r3, .L68 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L68 + str r2, [r3, #60] +.L67: + ldmib sp, {fp, sp, pc} +.L69: + .align 2 +.L68: + .word GSU + .size _Z6fx_bplv, .-_Z6fx_bplv + .align 2 + .type _Z6fx_bmiv, %function +_Z6fx_bmiv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L75 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L75 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L75 + str r2, [r3, #60] + ldr r3, .L75 + ldr r2, [r3, #472] + ldr r3, .L75 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L75 + strb r3, [r2, #109] + ldr r3, .L75 + ldr r3, [r3, #116] + and r3, r3, #32768 + cmp r3, #0 + beq .L71 + ldr r3, .L75 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L75 + str r2, [r3, #60] + b .L74 +.L71: + ldr r3, .L75 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L75 + str r2, [r3, #60] +.L74: + ldmib sp, {fp, sp, pc} +.L76: + .align 2 +.L75: + .word GSU + .size _Z6fx_bmiv, .-_Z6fx_bmiv + .align 2 + .type _Z6fx_bccv, %function +_Z6fx_bccv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L82 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L82 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L82 + str r2, [r3, #60] + ldr r3, .L82 + ldr r2, [r3, #472] + ldr r3, .L82 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L82 + strb r3, [r2, #109] + ldr r3, .L82 + ldr r3, [r3, #124] + and r3, r3, #1 + and r3, r3, #255 + eor r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L78 + ldr r3, .L82 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L82 + str r2, [r3, #60] + b .L81 +.L78: + ldr r3, .L82 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L82 + str r2, [r3, #60] +.L81: + ldmib sp, {fp, sp, pc} +.L83: + .align 2 +.L82: + .word GSU + .size _Z6fx_bccv, .-_Z6fx_bccv + .align 2 + .type _Z6fx_bcsv, %function +_Z6fx_bcsv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L89 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L89 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L89 + str r2, [r3, #60] + ldr r3, .L89 + ldr r2, [r3, #472] + ldr r3, .L89 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L89 + strb r3, [r2, #109] + ldr r3, .L89 + ldr r3, [r3, #124] + and r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L85 + ldr r3, .L89 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L89 + str r2, [r3, #60] + b .L88 +.L85: + ldr r3, .L89 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L89 + str r2, [r3, #60] +.L88: + ldmib sp, {fp, sp, pc} +.L90: + .align 2 +.L89: + .word GSU + .size _Z6fx_bcsv, .-_Z6fx_bcsv + .align 2 + .type _Z6fx_bvcv, %function +_Z6fx_bvcv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L97 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L97 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L97 + str r2, [r3, #60] + ldr r3, .L97 + ldr r2, [r3, #472] + ldr r3, .L97 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L97 + strb r3, [r2, #109] + ldr r3, .L97 + ldr r2, [r3, #128] + ldr r3, .L97+4 + cmp r2, r3 + bgt .L92 + ldr r3, .L97 + ldr r3, [r3, #128] + cmn r3, #32768 + blt .L92 + ldr r3, .L97 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L97 + str r2, [r3, #60] + b .L96 +.L92: + ldr r3, .L97 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L97 + str r2, [r3, #60] +.L96: + ldmib sp, {fp, sp, pc} +.L98: + .align 2 +.L97: + .word GSU + .word 32767 + .size _Z6fx_bvcv, .-_Z6fx_bvcv + .align 2 + .type _Z6fx_bvsv, %function +_Z6fx_bvsv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L105 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L105 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L105 + str r2, [r3, #60] + ldr r3, .L105 + ldr r2, [r3, #472] + ldr r3, .L105 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L105 + strb r3, [r2, #109] + ldr r3, .L105 + ldr r2, [r3, #128] + ldr r3, .L105+4 + cmp r2, r3 + bgt .L100 + ldr r3, .L105 + ldr r3, [r3, #128] + cmn r3, #32768 + bge .L102 +.L100: + ldr r3, .L105 + ldr r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + add r2, r2, r3 + ldr r3, .L105 + str r2, [r3, #60] + b .L104 +.L102: + ldr r3, .L105 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L105 + str r2, [r3, #60] +.L104: + ldmib sp, {fp, sp, pc} +.L106: + .align 2 +.L105: + .word GSU + .word 32767 + .size _Z6fx_bvsv, .-_Z6fx_bvsv + .align 2 + .type _Z8fx_to_r0v, %function +_Z8fx_to_r0v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L112 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L108 + ldr r3, .L112 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L112 + str r2, [r3, #0] + ldr r3, .L112 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L112 + str r2, [r3, #72] + ldr r2, .L112 + ldr r3, .L112 + str r3, [r2, #104] + ldr r3, .L112 + ldr r2, [r3, #104] + ldr r3, .L112 + str r2, [r3, #100] + b .L110 +.L108: + ldr r2, .L112 + ldr r3, .L112 + str r3, [r2, #100] +.L110: + ldr r3, .L112 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L112 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L113: + .align 2 +.L112: + .word GSU + .size _Z8fx_to_r0v, .-_Z8fx_to_r0v + .align 2 + .type _Z8fx_to_r1v, %function +_Z8fx_to_r1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L119 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L115 + ldr r3, .L119 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L119 + str r2, [r3, #4] + ldr r3, .L119 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L119 + str r2, [r3, #72] + ldr r2, .L119 + ldr r3, .L119 + str r3, [r2, #104] + ldr r3, .L119 + ldr r2, [r3, #104] + ldr r3, .L119 + str r2, [r3, #100] + b .L117 +.L115: + ldr r2, .L119 + ldr r3, .L119+4 + str r3, [r2, #100] +.L117: + ldr r3, .L119 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L119 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L120: + .align 2 +.L119: + .word GSU + .word GSU+4 + .size _Z8fx_to_r1v, .-_Z8fx_to_r1v + .align 2 + .type _Z8fx_to_r2v, %function +_Z8fx_to_r2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L126 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L122 + ldr r3, .L126 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L126 + str r2, [r3, #8] + ldr r3, .L126 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L126 + str r2, [r3, #72] + ldr r2, .L126 + ldr r3, .L126 + str r3, [r2, #104] + ldr r3, .L126 + ldr r2, [r3, #104] + ldr r3, .L126 + str r2, [r3, #100] + b .L124 +.L122: + ldr r2, .L126 + ldr r3, .L126+4 + str r3, [r2, #100] +.L124: + ldr r3, .L126 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L126 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L127: + .align 2 +.L126: + .word GSU + .word GSU+8 + .size _Z8fx_to_r2v, .-_Z8fx_to_r2v + .align 2 + .type _Z8fx_to_r3v, %function +_Z8fx_to_r3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L133 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L129 + ldr r3, .L133 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L133 + str r2, [r3, #12] + ldr r3, .L133 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L133 + str r2, [r3, #72] + ldr r2, .L133 + ldr r3, .L133 + str r3, [r2, #104] + ldr r3, .L133 + ldr r2, [r3, #104] + ldr r3, .L133 + str r2, [r3, #100] + b .L131 +.L129: + ldr r2, .L133 + ldr r3, .L133+4 + str r3, [r2, #100] +.L131: + ldr r3, .L133 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L133 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L134: + .align 2 +.L133: + .word GSU + .word GSU+12 + .size _Z8fx_to_r3v, .-_Z8fx_to_r3v + .align 2 + .type _Z8fx_to_r4v, %function +_Z8fx_to_r4v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L140 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L136 + ldr r3, .L140 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L140 + str r2, [r3, #16] + ldr r3, .L140 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L140 + str r2, [r3, #72] + ldr r2, .L140 + ldr r3, .L140 + str r3, [r2, #104] + ldr r3, .L140 + ldr r2, [r3, #104] + ldr r3, .L140 + str r2, [r3, #100] + b .L138 +.L136: + ldr r2, .L140 + ldr r3, .L140+4 + str r3, [r2, #100] +.L138: + ldr r3, .L140 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L140 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L141: + .align 2 +.L140: + .word GSU + .word GSU+16 + .size _Z8fx_to_r4v, .-_Z8fx_to_r4v + .align 2 + .type _Z8fx_to_r5v, %function +_Z8fx_to_r5v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L147 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L143 + ldr r3, .L147 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L147 + str r2, [r3, #20] + ldr r3, .L147 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L147 + str r2, [r3, #72] + ldr r2, .L147 + ldr r3, .L147 + str r3, [r2, #104] + ldr r3, .L147 + ldr r2, [r3, #104] + ldr r3, .L147 + str r2, [r3, #100] + b .L145 +.L143: + ldr r2, .L147 + ldr r3, .L147+4 + str r3, [r2, #100] +.L145: + ldr r3, .L147 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L147 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L148: + .align 2 +.L147: + .word GSU + .word GSU+20 + .size _Z8fx_to_r5v, .-_Z8fx_to_r5v + .align 2 + .type _Z8fx_to_r6v, %function +_Z8fx_to_r6v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L154 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L150 + ldr r3, .L154 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L154 + str r2, [r3, #24] + ldr r3, .L154 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L154 + str r2, [r3, #72] + ldr r2, .L154 + ldr r3, .L154 + str r3, [r2, #104] + ldr r3, .L154 + ldr r2, [r3, #104] + ldr r3, .L154 + str r2, [r3, #100] + b .L152 +.L150: + ldr r2, .L154 + ldr r3, .L154+4 + str r3, [r2, #100] +.L152: + ldr r3, .L154 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L154 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L155: + .align 2 +.L154: + .word GSU + .word GSU+24 + .size _Z8fx_to_r6v, .-_Z8fx_to_r6v + .align 2 + .type _Z8fx_to_r7v, %function +_Z8fx_to_r7v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L161 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L157 + ldr r3, .L161 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L161 + str r2, [r3, #28] + ldr r3, .L161 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L161 + str r2, [r3, #72] + ldr r2, .L161 + ldr r3, .L161 + str r3, [r2, #104] + ldr r3, .L161 + ldr r2, [r3, #104] + ldr r3, .L161 + str r2, [r3, #100] + b .L159 +.L157: + ldr r2, .L161 + ldr r3, .L161+4 + str r3, [r2, #100] +.L159: + ldr r3, .L161 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L161 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L162: + .align 2 +.L161: + .word GSU + .word GSU+28 + .size _Z8fx_to_r7v, .-_Z8fx_to_r7v + .align 2 + .type _Z8fx_to_r8v, %function +_Z8fx_to_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L168 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L164 + ldr r3, .L168 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L168 + str r2, [r3, #32] + ldr r3, .L168 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L168 + str r2, [r3, #72] + ldr r2, .L168 + ldr r3, .L168 + str r3, [r2, #104] + ldr r3, .L168 + ldr r2, [r3, #104] + ldr r3, .L168 + str r2, [r3, #100] + b .L166 +.L164: + ldr r2, .L168 + ldr r3, .L168+4 + str r3, [r2, #100] +.L166: + ldr r3, .L168 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L168 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L169: + .align 2 +.L168: + .word GSU + .word GSU+32 + .size _Z8fx_to_r8v, .-_Z8fx_to_r8v + .align 2 + .type _Z8fx_to_r9v, %function +_Z8fx_to_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L175 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L171 + ldr r3, .L175 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L175 + str r2, [r3, #36] + ldr r3, .L175 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L175 + str r2, [r3, #72] + ldr r2, .L175 + ldr r3, .L175 + str r3, [r2, #104] + ldr r3, .L175 + ldr r2, [r3, #104] + ldr r3, .L175 + str r2, [r3, #100] + b .L173 +.L171: + ldr r2, .L175 + ldr r3, .L175+4 + str r3, [r2, #100] +.L173: + ldr r3, .L175 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L175 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L176: + .align 2 +.L175: + .word GSU + .word GSU+36 + .size _Z8fx_to_r9v, .-_Z8fx_to_r9v + .align 2 + .type _Z9fx_to_r10v, %function +_Z9fx_to_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L182 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L178 + ldr r3, .L182 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L182 + str r2, [r3, #40] + ldr r3, .L182 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L182 + str r2, [r3, #72] + ldr r2, .L182 + ldr r3, .L182 + str r3, [r2, #104] + ldr r3, .L182 + ldr r2, [r3, #104] + ldr r3, .L182 + str r2, [r3, #100] + b .L180 +.L178: + ldr r2, .L182 + ldr r3, .L182+4 + str r3, [r2, #100] +.L180: + ldr r3, .L182 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L182 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L183: + .align 2 +.L182: + .word GSU + .word GSU+40 + .size _Z9fx_to_r10v, .-_Z9fx_to_r10v + .align 2 + .type _Z9fx_to_r11v, %function +_Z9fx_to_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L189 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L185 + ldr r3, .L189 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L189 + str r2, [r3, #44] + ldr r3, .L189 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L189 + str r2, [r3, #72] + ldr r2, .L189 + ldr r3, .L189 + str r3, [r2, #104] + ldr r3, .L189 + ldr r2, [r3, #104] + ldr r3, .L189 + str r2, [r3, #100] + b .L187 +.L185: + ldr r2, .L189 + ldr r3, .L189+4 + str r3, [r2, #100] +.L187: + ldr r3, .L189 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L189 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L190: + .align 2 +.L189: + .word GSU + .word GSU+44 + .size _Z9fx_to_r11v, .-_Z9fx_to_r11v + .align 2 + .type _Z9fx_to_r12v, %function +_Z9fx_to_r12v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L196 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L192 + ldr r3, .L196 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L196 + str r2, [r3, #48] + ldr r3, .L196 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L196 + str r2, [r3, #72] + ldr r2, .L196 + ldr r3, .L196 + str r3, [r2, #104] + ldr r3, .L196 + ldr r2, [r3, #104] + ldr r3, .L196 + str r2, [r3, #100] + b .L194 +.L192: + ldr r2, .L196 + ldr r3, .L196+4 + str r3, [r2, #100] +.L194: + ldr r3, .L196 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L196 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L197: + .align 2 +.L196: + .word GSU + .word GSU+48 + .size _Z9fx_to_r12v, .-_Z9fx_to_r12v + .align 2 + .type _Z9fx_to_r13v, %function +_Z9fx_to_r13v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L203 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L199 + ldr r3, .L203 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L203 + str r2, [r3, #52] + ldr r3, .L203 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L203 + str r2, [r3, #72] + ldr r2, .L203 + ldr r3, .L203 + str r3, [r2, #104] + ldr r3, .L203 + ldr r2, [r3, #104] + ldr r3, .L203 + str r2, [r3, #100] + b .L201 +.L199: + ldr r2, .L203 + ldr r3, .L203+4 + str r3, [r2, #100] +.L201: + ldr r3, .L203 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L203 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L204: + .align 2 +.L203: + .word GSU + .word GSU+52 + .size _Z9fx_to_r13v, .-_Z9fx_to_r13v + .align 2 + .type _Z9fx_to_r14v, %function +_Z9fx_to_r14v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L210 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L206 + ldr r3, .L210 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L210 + str r2, [r3, #56] + ldr r3, .L210 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L210 + str r2, [r3, #72] + ldr r2, .L210 + ldr r3, .L210 + str r3, [r2, #104] + ldr r3, .L210 + ldr r2, [r3, #104] + ldr r3, .L210 + str r2, [r3, #100] + ldr r3, .L210 + ldr r2, [r3, #468] + ldr r3, .L210 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L210 + strb r3, [r2, #108] + b .L208 +.L206: + ldr r2, .L210 + ldr r3, .L210+4 + str r3, [r2, #100] +.L208: + ldr r3, .L210 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L210 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L211: + .align 2 +.L210: + .word GSU + .word GSU+56 + .size _Z9fx_to_r14v, .-_Z9fx_to_r14v + .align 2 + .type _Z9fx_to_r15v, %function +_Z9fx_to_r15v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L217 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L213 + ldr r3, .L217 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L217 + str r2, [r3, #60] + ldr r3, .L217 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L217 + str r2, [r3, #72] + ldr r2, .L217 + ldr r3, .L217 + str r3, [r2, #104] + ldr r3, .L217 + ldr r2, [r3, #104] + ldr r3, .L217 + str r2, [r3, #100] + b .L216 +.L213: + ldr r2, .L217 + ldr r3, .L217+4 + str r3, [r2, #100] + ldr r3, .L217 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L217 + str r2, [r3, #60] +.L216: + ldmfd sp, {fp, sp, pc} +.L218: + .align 2 +.L217: + .word GSU + .word GSU+60 + .size _Z9fx_to_r15v, .-_Z9fx_to_r15v + .align 2 + .type _Z10fx_with_r0v, %function +_Z10fx_with_r0v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L221 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L221 + str r2, [r3, #72] + ldr r2, .L221 + ldr r3, .L221 + str r3, [r2, #100] + ldr r3, .L221 + ldr r2, [r3, #100] + ldr r3, .L221 + str r2, [r3, #104] + ldr r3, .L221 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L221 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L222: + .align 2 +.L221: + .word GSU + .size _Z10fx_with_r0v, .-_Z10fx_with_r0v + .align 2 + .type _Z10fx_with_r1v, %function +_Z10fx_with_r1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L225 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L225 + str r2, [r3, #72] + ldr r2, .L225 + ldr r3, .L225+4 + str r3, [r2, #100] + ldr r3, .L225 + ldr r2, [r3, #100] + ldr r3, .L225 + str r2, [r3, #104] + ldr r3, .L225 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L225 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L226: + .align 2 +.L225: + .word GSU + .word GSU+4 + .size _Z10fx_with_r1v, .-_Z10fx_with_r1v + .align 2 + .type _Z10fx_with_r2v, %function +_Z10fx_with_r2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L229 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L229 + str r2, [r3, #72] + ldr r2, .L229 + ldr r3, .L229+4 + str r3, [r2, #100] + ldr r3, .L229 + ldr r2, [r3, #100] + ldr r3, .L229 + str r2, [r3, #104] + ldr r3, .L229 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L229 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L230: + .align 2 +.L229: + .word GSU + .word GSU+8 + .size _Z10fx_with_r2v, .-_Z10fx_with_r2v + .align 2 + .type _Z10fx_with_r3v, %function +_Z10fx_with_r3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L233 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L233 + str r2, [r3, #72] + ldr r2, .L233 + ldr r3, .L233+4 + str r3, [r2, #100] + ldr r3, .L233 + ldr r2, [r3, #100] + ldr r3, .L233 + str r2, [r3, #104] + ldr r3, .L233 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L233 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L234: + .align 2 +.L233: + .word GSU + .word GSU+12 + .size _Z10fx_with_r3v, .-_Z10fx_with_r3v + .align 2 + .type _Z10fx_with_r4v, %function +_Z10fx_with_r4v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L237 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L237 + str r2, [r3, #72] + ldr r2, .L237 + ldr r3, .L237+4 + str r3, [r2, #100] + ldr r3, .L237 + ldr r2, [r3, #100] + ldr r3, .L237 + str r2, [r3, #104] + ldr r3, .L237 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L237 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L238: + .align 2 +.L237: + .word GSU + .word GSU+16 + .size _Z10fx_with_r4v, .-_Z10fx_with_r4v + .align 2 + .type _Z10fx_with_r5v, %function +_Z10fx_with_r5v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L241 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L241 + str r2, [r3, #72] + ldr r2, .L241 + ldr r3, .L241+4 + str r3, [r2, #100] + ldr r3, .L241 + ldr r2, [r3, #100] + ldr r3, .L241 + str r2, [r3, #104] + ldr r3, .L241 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L241 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L242: + .align 2 +.L241: + .word GSU + .word GSU+20 + .size _Z10fx_with_r5v, .-_Z10fx_with_r5v + .align 2 + .type _Z10fx_with_r6v, %function +_Z10fx_with_r6v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L245 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L245 + str r2, [r3, #72] + ldr r2, .L245 + ldr r3, .L245+4 + str r3, [r2, #100] + ldr r3, .L245 + ldr r2, [r3, #100] + ldr r3, .L245 + str r2, [r3, #104] + ldr r3, .L245 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L245 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L246: + .align 2 +.L245: + .word GSU + .word GSU+24 + .size _Z10fx_with_r6v, .-_Z10fx_with_r6v + .align 2 + .type _Z10fx_with_r7v, %function +_Z10fx_with_r7v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L249 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L249 + str r2, [r3, #72] + ldr r2, .L249 + ldr r3, .L249+4 + str r3, [r2, #100] + ldr r3, .L249 + ldr r2, [r3, #100] + ldr r3, .L249 + str r2, [r3, #104] + ldr r3, .L249 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L249 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L250: + .align 2 +.L249: + .word GSU + .word GSU+28 + .size _Z10fx_with_r7v, .-_Z10fx_with_r7v + .align 2 + .type _Z10fx_with_r8v, %function +_Z10fx_with_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L253 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L253 + str r2, [r3, #72] + ldr r2, .L253 + ldr r3, .L253+4 + str r3, [r2, #100] + ldr r3, .L253 + ldr r2, [r3, #100] + ldr r3, .L253 + str r2, [r3, #104] + ldr r3, .L253 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L253 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L254: + .align 2 +.L253: + .word GSU + .word GSU+32 + .size _Z10fx_with_r8v, .-_Z10fx_with_r8v + .align 2 + .type _Z10fx_with_r9v, %function +_Z10fx_with_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L257 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L257 + str r2, [r3, #72] + ldr r2, .L257 + ldr r3, .L257+4 + str r3, [r2, #100] + ldr r3, .L257 + ldr r2, [r3, #100] + ldr r3, .L257 + str r2, [r3, #104] + ldr r3, .L257 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L257 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L258: + .align 2 +.L257: + .word GSU + .word GSU+36 + .size _Z10fx_with_r9v, .-_Z10fx_with_r9v + .align 2 + .type _Z11fx_with_r10v, %function +_Z11fx_with_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L261 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L261 + str r2, [r3, #72] + ldr r2, .L261 + ldr r3, .L261+4 + str r3, [r2, #100] + ldr r3, .L261 + ldr r2, [r3, #100] + ldr r3, .L261 + str r2, [r3, #104] + ldr r3, .L261 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L261 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L262: + .align 2 +.L261: + .word GSU + .word GSU+40 + .size _Z11fx_with_r10v, .-_Z11fx_with_r10v + .align 2 + .type _Z11fx_with_r11v, %function +_Z11fx_with_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L265 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L265 + str r2, [r3, #72] + ldr r2, .L265 + ldr r3, .L265+4 + str r3, [r2, #100] + ldr r3, .L265 + ldr r2, [r3, #100] + ldr r3, .L265 + str r2, [r3, #104] + ldr r3, .L265 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L265 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L266: + .align 2 +.L265: + .word GSU + .word GSU+44 + .size _Z11fx_with_r11v, .-_Z11fx_with_r11v + .align 2 + .type _Z11fx_with_r12v, %function +_Z11fx_with_r12v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L269 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L269 + str r2, [r3, #72] + ldr r2, .L269 + ldr r3, .L269+4 + str r3, [r2, #100] + ldr r3, .L269 + ldr r2, [r3, #100] + ldr r3, .L269 + str r2, [r3, #104] + ldr r3, .L269 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L269 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L270: + .align 2 +.L269: + .word GSU + .word GSU+48 + .size _Z11fx_with_r12v, .-_Z11fx_with_r12v + .align 2 + .type _Z11fx_with_r13v, %function +_Z11fx_with_r13v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L273 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L273 + str r2, [r3, #72] + ldr r2, .L273 + ldr r3, .L273+4 + str r3, [r2, #100] + ldr r3, .L273 + ldr r2, [r3, #100] + ldr r3, .L273 + str r2, [r3, #104] + ldr r3, .L273 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L273 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L274: + .align 2 +.L273: + .word GSU + .word GSU+52 + .size _Z11fx_with_r13v, .-_Z11fx_with_r13v + .align 2 + .type _Z11fx_with_r14v, %function +_Z11fx_with_r14v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L277 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L277 + str r2, [r3, #72] + ldr r2, .L277 + ldr r3, .L277+4 + str r3, [r2, #100] + ldr r3, .L277 + ldr r2, [r3, #100] + ldr r3, .L277 + str r2, [r3, #104] + ldr r3, .L277 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L277 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L278: + .align 2 +.L277: + .word GSU + .word GSU+56 + .size _Z11fx_with_r14v, .-_Z11fx_with_r14v + .align 2 + .type _Z11fx_with_r15v, %function +_Z11fx_with_r15v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L281 + ldr r3, [r3, #72] + orr r2, r3, #4096 + ldr r3, .L281 + str r2, [r3, #72] + ldr r2, .L281 + ldr r3, .L281+4 + str r3, [r2, #100] + ldr r3, .L281 + ldr r2, [r3, #100] + ldr r3, .L281 + str r2, [r3, #104] + ldr r3, .L281 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L281 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L282: + .align 2 +.L281: + .word GSU + .word GSU+60 + .size _Z11fx_with_r15v, .-_Z11fx_with_r15v + .align 2 + .type _Z9fx_stw_r0v, %function +_Z9fx_stw_r0v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L285 + ldr r2, [r3, #0] + ldr r3, .L285 + str r2, [r3, #96] + ldr r3, .L285 + ldr r2, [r3, #464] + ldr r3, .L285 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L285 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L285 + ldr r2, [r3, #464] + ldr r3, .L285 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L285 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L285 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L285 + str r2, [r3, #72] + ldr r2, .L285 + ldr r3, .L285 + str r3, [r2, #104] + ldr r3, .L285 + ldr r2, [r3, #104] + ldr r3, .L285 + str r2, [r3, #100] + ldr r3, .L285 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L285 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L286: + .align 2 +.L285: + .word GSU + .size _Z9fx_stw_r0v, .-_Z9fx_stw_r0v + .align 2 + .type _Z9fx_stw_r1v, %function +_Z9fx_stw_r1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L289 + ldr r2, [r3, #4] + ldr r3, .L289 + str r2, [r3, #96] + ldr r3, .L289 + ldr r2, [r3, #464] + ldr r3, .L289 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L289 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L289 + ldr r2, [r3, #464] + ldr r3, .L289 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L289 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L289 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L289 + str r2, [r3, #72] + ldr r2, .L289 + ldr r3, .L289 + str r3, [r2, #104] + ldr r3, .L289 + ldr r2, [r3, #104] + ldr r3, .L289 + str r2, [r3, #100] + ldr r3, .L289 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L289 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L290: + .align 2 +.L289: + .word GSU + .size _Z9fx_stw_r1v, .-_Z9fx_stw_r1v + .align 2 + .type _Z9fx_stw_r2v, %function +_Z9fx_stw_r2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L293 + ldr r2, [r3, #8] + ldr r3, .L293 + str r2, [r3, #96] + ldr r3, .L293 + ldr r2, [r3, #464] + ldr r3, .L293 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L293 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L293 + ldr r2, [r3, #464] + ldr r3, .L293 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L293 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L293 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L293 + str r2, [r3, #72] + ldr r2, .L293 + ldr r3, .L293 + str r3, [r2, #104] + ldr r3, .L293 + ldr r2, [r3, #104] + ldr r3, .L293 + str r2, [r3, #100] + ldr r3, .L293 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L293 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L294: + .align 2 +.L293: + .word GSU + .size _Z9fx_stw_r2v, .-_Z9fx_stw_r2v + .align 2 + .type _Z9fx_stw_r3v, %function +_Z9fx_stw_r3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L297 + ldr r2, [r3, #12] + ldr r3, .L297 + str r2, [r3, #96] + ldr r3, .L297 + ldr r2, [r3, #464] + ldr r3, .L297 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L297 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L297 + ldr r2, [r3, #464] + ldr r3, .L297 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L297 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L297 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L297 + str r2, [r3, #72] + ldr r2, .L297 + ldr r3, .L297 + str r3, [r2, #104] + ldr r3, .L297 + ldr r2, [r3, #104] + ldr r3, .L297 + str r2, [r3, #100] + ldr r3, .L297 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L297 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L298: + .align 2 +.L297: + .word GSU + .size _Z9fx_stw_r3v, .-_Z9fx_stw_r3v + .align 2 + .type _Z9fx_stw_r4v, %function +_Z9fx_stw_r4v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L301 + ldr r2, [r3, #16] + ldr r3, .L301 + str r2, [r3, #96] + ldr r3, .L301 + ldr r2, [r3, #464] + ldr r3, .L301 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L301 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L301 + ldr r2, [r3, #464] + ldr r3, .L301 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L301 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L301 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L301 + str r2, [r3, #72] + ldr r2, .L301 + ldr r3, .L301 + str r3, [r2, #104] + ldr r3, .L301 + ldr r2, [r3, #104] + ldr r3, .L301 + str r2, [r3, #100] + ldr r3, .L301 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L301 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L302: + .align 2 +.L301: + .word GSU + .size _Z9fx_stw_r4v, .-_Z9fx_stw_r4v + .align 2 + .type _Z9fx_stw_r5v, %function +_Z9fx_stw_r5v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L305 + ldr r2, [r3, #20] + ldr r3, .L305 + str r2, [r3, #96] + ldr r3, .L305 + ldr r2, [r3, #464] + ldr r3, .L305 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L305 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L305 + ldr r2, [r3, #464] + ldr r3, .L305 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L305 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L305 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L305 + str r2, [r3, #72] + ldr r2, .L305 + ldr r3, .L305 + str r3, [r2, #104] + ldr r3, .L305 + ldr r2, [r3, #104] + ldr r3, .L305 + str r2, [r3, #100] + ldr r3, .L305 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L305 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L306: + .align 2 +.L305: + .word GSU + .size _Z9fx_stw_r5v, .-_Z9fx_stw_r5v + .align 2 + .type _Z9fx_stw_r6v, %function +_Z9fx_stw_r6v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L309 + ldr r2, [r3, #24] + ldr r3, .L309 + str r2, [r3, #96] + ldr r3, .L309 + ldr r2, [r3, #464] + ldr r3, .L309 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L309 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L309 + ldr r2, [r3, #464] + ldr r3, .L309 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L309 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L309 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L309 + str r2, [r3, #72] + ldr r2, .L309 + ldr r3, .L309 + str r3, [r2, #104] + ldr r3, .L309 + ldr r2, [r3, #104] + ldr r3, .L309 + str r2, [r3, #100] + ldr r3, .L309 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L309 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L310: + .align 2 +.L309: + .word GSU + .size _Z9fx_stw_r6v, .-_Z9fx_stw_r6v + .align 2 + .type _Z9fx_stw_r7v, %function +_Z9fx_stw_r7v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L313 + ldr r2, [r3, #28] + ldr r3, .L313 + str r2, [r3, #96] + ldr r3, .L313 + ldr r2, [r3, #464] + ldr r3, .L313 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L313 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L313 + ldr r2, [r3, #464] + ldr r3, .L313 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L313 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L313 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L313 + str r2, [r3, #72] + ldr r2, .L313 + ldr r3, .L313 + str r3, [r2, #104] + ldr r3, .L313 + ldr r2, [r3, #104] + ldr r3, .L313 + str r2, [r3, #100] + ldr r3, .L313 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L313 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L314: + .align 2 +.L313: + .word GSU + .size _Z9fx_stw_r7v, .-_Z9fx_stw_r7v + .align 2 + .type _Z9fx_stw_r8v, %function +_Z9fx_stw_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L317 + ldr r2, [r3, #32] + ldr r3, .L317 + str r2, [r3, #96] + ldr r3, .L317 + ldr r2, [r3, #464] + ldr r3, .L317 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L317 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L317 + ldr r2, [r3, #464] + ldr r3, .L317 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L317 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L317 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L317 + str r2, [r3, #72] + ldr r2, .L317 + ldr r3, .L317 + str r3, [r2, #104] + ldr r3, .L317 + ldr r2, [r3, #104] + ldr r3, .L317 + str r2, [r3, #100] + ldr r3, .L317 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L317 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L318: + .align 2 +.L317: + .word GSU + .size _Z9fx_stw_r8v, .-_Z9fx_stw_r8v + .align 2 + .type _Z9fx_stw_r9v, %function +_Z9fx_stw_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L321 + ldr r2, [r3, #36] + ldr r3, .L321 + str r2, [r3, #96] + ldr r3, .L321 + ldr r2, [r3, #464] + ldr r3, .L321 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L321 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L321 + ldr r2, [r3, #464] + ldr r3, .L321 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L321 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L321 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L321 + str r2, [r3, #72] + ldr r2, .L321 + ldr r3, .L321 + str r3, [r2, #104] + ldr r3, .L321 + ldr r2, [r3, #104] + ldr r3, .L321 + str r2, [r3, #100] + ldr r3, .L321 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L321 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L322: + .align 2 +.L321: + .word GSU + .size _Z9fx_stw_r9v, .-_Z9fx_stw_r9v + .align 2 + .type _Z10fx_stw_r10v, %function +_Z10fx_stw_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L325 + ldr r2, [r3, #40] + ldr r3, .L325 + str r2, [r3, #96] + ldr r3, .L325 + ldr r2, [r3, #464] + ldr r3, .L325 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L325 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L325 + ldr r2, [r3, #464] + ldr r3, .L325 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L325 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L325 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L325 + str r2, [r3, #72] + ldr r2, .L325 + ldr r3, .L325 + str r3, [r2, #104] + ldr r3, .L325 + ldr r2, [r3, #104] + ldr r3, .L325 + str r2, [r3, #100] + ldr r3, .L325 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L325 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L326: + .align 2 +.L325: + .word GSU + .size _Z10fx_stw_r10v, .-_Z10fx_stw_r10v + .align 2 + .type _Z10fx_stw_r11v, %function +_Z10fx_stw_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L329 + ldr r2, [r3, #44] + ldr r3, .L329 + str r2, [r3, #96] + ldr r3, .L329 + ldr r2, [r3, #464] + ldr r3, .L329 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L329 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L329 + ldr r2, [r3, #464] + ldr r3, .L329 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L329 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L329 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L329 + str r2, [r3, #72] + ldr r2, .L329 + ldr r3, .L329 + str r3, [r2, #104] + ldr r3, .L329 + ldr r2, [r3, #104] + ldr r3, .L329 + str r2, [r3, #100] + ldr r3, .L329 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L329 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L330: + .align 2 +.L329: + .word GSU + .size _Z10fx_stw_r11v, .-_Z10fx_stw_r11v + .align 2 + .type _Z9fx_stb_r0v, %function +_Z9fx_stb_r0v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L333 + ldr r2, [r3, #0] + ldr r3, .L333 + str r2, [r3, #96] + ldr r3, .L333 + ldr r2, [r3, #464] + ldr r3, .L333 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L333 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L333 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L333 + str r2, [r3, #72] + ldr r2, .L333 + ldr r3, .L333 + str r3, [r2, #104] + ldr r3, .L333 + ldr r2, [r3, #104] + ldr r3, .L333 + str r2, [r3, #100] + ldr r3, .L333 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L333 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L334: + .align 2 +.L333: + .word GSU + .size _Z9fx_stb_r0v, .-_Z9fx_stb_r0v + .align 2 + .type _Z9fx_stb_r1v, %function +_Z9fx_stb_r1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L337 + ldr r2, [r3, #4] + ldr r3, .L337 + str r2, [r3, #96] + ldr r3, .L337 + ldr r2, [r3, #464] + ldr r3, .L337 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L337 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L337 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L337 + str r2, [r3, #72] + ldr r2, .L337 + ldr r3, .L337 + str r3, [r2, #104] + ldr r3, .L337 + ldr r2, [r3, #104] + ldr r3, .L337 + str r2, [r3, #100] + ldr r3, .L337 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L337 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L338: + .align 2 +.L337: + .word GSU + .size _Z9fx_stb_r1v, .-_Z9fx_stb_r1v + .align 2 + .type _Z9fx_stb_r2v, %function +_Z9fx_stb_r2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L341 + ldr r2, [r3, #8] + ldr r3, .L341 + str r2, [r3, #96] + ldr r3, .L341 + ldr r2, [r3, #464] + ldr r3, .L341 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L341 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L341 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L341 + str r2, [r3, #72] + ldr r2, .L341 + ldr r3, .L341 + str r3, [r2, #104] + ldr r3, .L341 + ldr r2, [r3, #104] + ldr r3, .L341 + str r2, [r3, #100] + ldr r3, .L341 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L341 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L342: + .align 2 +.L341: + .word GSU + .size _Z9fx_stb_r2v, .-_Z9fx_stb_r2v + .align 2 + .type _Z9fx_stb_r3v, %function +_Z9fx_stb_r3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L345 + ldr r2, [r3, #12] + ldr r3, .L345 + str r2, [r3, #96] + ldr r3, .L345 + ldr r2, [r3, #464] + ldr r3, .L345 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L345 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L345 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L345 + str r2, [r3, #72] + ldr r2, .L345 + ldr r3, .L345 + str r3, [r2, #104] + ldr r3, .L345 + ldr r2, [r3, #104] + ldr r3, .L345 + str r2, [r3, #100] + ldr r3, .L345 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L345 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L346: + .align 2 +.L345: + .word GSU + .size _Z9fx_stb_r3v, .-_Z9fx_stb_r3v + .align 2 + .type _Z9fx_stb_r4v, %function +_Z9fx_stb_r4v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L349 + ldr r2, [r3, #16] + ldr r3, .L349 + str r2, [r3, #96] + ldr r3, .L349 + ldr r2, [r3, #464] + ldr r3, .L349 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L349 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L349 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L349 + str r2, [r3, #72] + ldr r2, .L349 + ldr r3, .L349 + str r3, [r2, #104] + ldr r3, .L349 + ldr r2, [r3, #104] + ldr r3, .L349 + str r2, [r3, #100] + ldr r3, .L349 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L349 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L350: + .align 2 +.L349: + .word GSU + .size _Z9fx_stb_r4v, .-_Z9fx_stb_r4v + .align 2 + .type _Z9fx_stb_r5v, %function +_Z9fx_stb_r5v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L353 + ldr r2, [r3, #20] + ldr r3, .L353 + str r2, [r3, #96] + ldr r3, .L353 + ldr r2, [r3, #464] + ldr r3, .L353 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L353 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L353 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L353 + str r2, [r3, #72] + ldr r2, .L353 + ldr r3, .L353 + str r3, [r2, #104] + ldr r3, .L353 + ldr r2, [r3, #104] + ldr r3, .L353 + str r2, [r3, #100] + ldr r3, .L353 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L353 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L354: + .align 2 +.L353: + .word GSU + .size _Z9fx_stb_r5v, .-_Z9fx_stb_r5v + .align 2 + .type _Z9fx_stb_r6v, %function +_Z9fx_stb_r6v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L357 + ldr r2, [r3, #24] + ldr r3, .L357 + str r2, [r3, #96] + ldr r3, .L357 + ldr r2, [r3, #464] + ldr r3, .L357 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L357 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L357 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L357 + str r2, [r3, #72] + ldr r2, .L357 + ldr r3, .L357 + str r3, [r2, #104] + ldr r3, .L357 + ldr r2, [r3, #104] + ldr r3, .L357 + str r2, [r3, #100] + ldr r3, .L357 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L357 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L358: + .align 2 +.L357: + .word GSU + .size _Z9fx_stb_r6v, .-_Z9fx_stb_r6v + .align 2 + .type _Z9fx_stb_r7v, %function +_Z9fx_stb_r7v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L361 + ldr r2, [r3, #28] + ldr r3, .L361 + str r2, [r3, #96] + ldr r3, .L361 + ldr r2, [r3, #464] + ldr r3, .L361 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L361 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L361 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L361 + str r2, [r3, #72] + ldr r2, .L361 + ldr r3, .L361 + str r3, [r2, #104] + ldr r3, .L361 + ldr r2, [r3, #104] + ldr r3, .L361 + str r2, [r3, #100] + ldr r3, .L361 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L361 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L362: + .align 2 +.L361: + .word GSU + .size _Z9fx_stb_r7v, .-_Z9fx_stb_r7v + .align 2 + .type _Z9fx_stb_r8v, %function +_Z9fx_stb_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L365 + ldr r2, [r3, #32] + ldr r3, .L365 + str r2, [r3, #96] + ldr r3, .L365 + ldr r2, [r3, #464] + ldr r3, .L365 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L365 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L365 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L365 + str r2, [r3, #72] + ldr r2, .L365 + ldr r3, .L365 + str r3, [r2, #104] + ldr r3, .L365 + ldr r2, [r3, #104] + ldr r3, .L365 + str r2, [r3, #100] + ldr r3, .L365 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L365 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L366: + .align 2 +.L365: + .word GSU + .size _Z9fx_stb_r8v, .-_Z9fx_stb_r8v + .align 2 + .type _Z9fx_stb_r9v, %function +_Z9fx_stb_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L369 + ldr r2, [r3, #36] + ldr r3, .L369 + str r2, [r3, #96] + ldr r3, .L369 + ldr r2, [r3, #464] + ldr r3, .L369 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L369 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L369 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L369 + str r2, [r3, #72] + ldr r2, .L369 + ldr r3, .L369 + str r3, [r2, #104] + ldr r3, .L369 + ldr r2, [r3, #104] + ldr r3, .L369 + str r2, [r3, #100] + ldr r3, .L369 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L369 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L370: + .align 2 +.L369: + .word GSU + .size _Z9fx_stb_r9v, .-_Z9fx_stb_r9v + .align 2 + .type _Z10fx_stb_r10v, %function +_Z10fx_stb_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L373 + ldr r2, [r3, #40] + ldr r3, .L373 + str r2, [r3, #96] + ldr r3, .L373 + ldr r2, [r3, #464] + ldr r3, .L373 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L373 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L373 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L373 + str r2, [r3, #72] + ldr r2, .L373 + ldr r3, .L373 + str r3, [r2, #104] + ldr r3, .L373 + ldr r2, [r3, #104] + ldr r3, .L373 + str r2, [r3, #100] + ldr r3, .L373 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L373 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L374: + .align 2 +.L373: + .word GSU + .size _Z10fx_stb_r10v, .-_Z10fx_stb_r10v + .align 2 + .type _Z10fx_stb_r11v, %function +_Z10fx_stb_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L377 + ldr r2, [r3, #44] + ldr r3, .L377 + str r2, [r3, #96] + ldr r3, .L377 + ldr r2, [r3, #464] + ldr r3, .L377 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L377 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L377 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L377 + str r2, [r3, #72] + ldr r2, .L377 + ldr r3, .L377 + str r3, [r2, #104] + ldr r3, .L377 + ldr r2, [r3, #104] + ldr r3, .L377 + str r2, [r3, #100] + ldr r3, .L377 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L377 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L378: + .align 2 +.L377: + .word GSU + .size _Z10fx_stb_r11v, .-_Z10fx_stb_r11v + .align 2 + .type _Z7fx_loopv, %function +_Z7fx_loopv: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L384 + ldr r3, [r3, #48] + sub r2, r3, #1 + ldr r3, .L384 + str r2, [r3, #48] + ldr r3, .L384 + ldr r2, [r3, #48] + ldr r3, .L384 + str r2, [r3, #120] + ldr r3, .L384 + ldr r2, [r3, #120] + ldr r3, .L384 + str r2, [r3, #116] + ldr r3, .L384 + ldr r3, [r3, #48] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + cmp r3, #0 + beq .L380 + ldr r3, .L384 + ldr r2, [r3, #52] + ldr r3, .L384 + str r2, [r3, #60] + b .L382 +.L380: + ldr r3, .L384 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L384 + str r2, [r3, #60] +.L382: + ldr r3, .L384 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L384 + str r2, [r3, #72] + ldr r2, .L384 + ldr r3, .L384 + str r3, [r2, #104] + ldr r3, .L384 + ldr r2, [r3, #104] + ldr r3, .L384 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L385: + .align 2 +.L384: + .word GSU + .size _Z7fx_loopv, .-_Z7fx_loopv + .align 2 + .type _Z7fx_alt1v, %function +_Z7fx_alt1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L388 + ldr r3, [r3, #72] + orr r2, r3, #256 + ldr r3, .L388 + str r2, [r3, #72] + ldr r3, .L388 + ldr r3, [r3, #72] + bic r2, r3, #4096 + ldr r3, .L388 + str r2, [r3, #72] + ldr r3, .L388 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L388 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L389: + .align 2 +.L388: + .word GSU + .size _Z7fx_alt1v, .-_Z7fx_alt1v + .align 2 + .type _Z7fx_alt2v, %function +_Z7fx_alt2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L392 + ldr r3, [r3, #72] + orr r2, r3, #512 + ldr r3, .L392 + str r2, [r3, #72] + ldr r3, .L392 + ldr r3, [r3, #72] + bic r2, r3, #4096 + ldr r3, .L392 + str r2, [r3, #72] + ldr r3, .L392 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L392 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L393: + .align 2 +.L392: + .word GSU + .size _Z7fx_alt2v, .-_Z7fx_alt2v + .align 2 + .type _Z7fx_alt3v, %function +_Z7fx_alt3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L396 + ldr r3, [r3, #72] + orr r2, r3, #256 + ldr r3, .L396 + str r2, [r3, #72] + ldr r3, .L396 + ldr r3, [r3, #72] + orr r2, r3, #512 + ldr r3, .L396 + str r2, [r3, #72] + ldr r3, .L396 + ldr r3, [r3, #72] + bic r2, r3, #4096 + ldr r3, .L396 + str r2, [r3, #72] + ldr r3, .L396 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L396 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L397: + .align 2 +.L396: + .word GSU + .size _Z7fx_alt3v, .-_Z7fx_alt3v + .align 2 + .type _Z9fx_ldw_r0v, %function +_Z9fx_ldw_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L402 + ldr r2, [r3, #0] + ldr r3, .L402 + str r2, [r3, #96] + ldr r3, .L402 + ldr r2, [r3, #464] + ldr r3, .L402 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L402 + ldr r2, [r3, #464] + ldr r3, .L402 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L402 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L402 + str r2, [r3, #60] + ldr r3, .L402 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L402 + ldr r2, [r3, #100] + ldr r3, .L402+4 + cmp r2, r3 + bne .L399 + ldr r3, .L402 + ldr r2, [r3, #468] + ldr r3, .L402 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L402 + strb r3, [r2, #108] +.L399: + ldr r3, .L402 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L402 + str r2, [r3, #72] + ldr r2, .L402 + ldr r3, .L402 + str r3, [r2, #104] + ldr r3, .L402 + ldr r2, [r3, #104] + ldr r3, .L402 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L403: + .align 2 +.L402: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r0v, .-_Z9fx_ldw_r0v + .align 2 + .type _Z9fx_ldw_r1v, %function +_Z9fx_ldw_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L408 + ldr r2, [r3, #4] + ldr r3, .L408 + str r2, [r3, #96] + ldr r3, .L408 + ldr r2, [r3, #464] + ldr r3, .L408 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L408 + ldr r2, [r3, #464] + ldr r3, .L408 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L408 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L408 + str r2, [r3, #60] + ldr r3, .L408 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L408 + ldr r2, [r3, #100] + ldr r3, .L408+4 + cmp r2, r3 + bne .L405 + ldr r3, .L408 + ldr r2, [r3, #468] + ldr r3, .L408 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L408 + strb r3, [r2, #108] +.L405: + ldr r3, .L408 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L408 + str r2, [r3, #72] + ldr r2, .L408 + ldr r3, .L408 + str r3, [r2, #104] + ldr r3, .L408 + ldr r2, [r3, #104] + ldr r3, .L408 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L409: + .align 2 +.L408: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r1v, .-_Z9fx_ldw_r1v + .align 2 + .type _Z9fx_ldw_r2v, %function +_Z9fx_ldw_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L414 + ldr r2, [r3, #8] + ldr r3, .L414 + str r2, [r3, #96] + ldr r3, .L414 + ldr r2, [r3, #464] + ldr r3, .L414 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L414 + ldr r2, [r3, #464] + ldr r3, .L414 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L414 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L414 + str r2, [r3, #60] + ldr r3, .L414 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L414 + ldr r2, [r3, #100] + ldr r3, .L414+4 + cmp r2, r3 + bne .L411 + ldr r3, .L414 + ldr r2, [r3, #468] + ldr r3, .L414 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L414 + strb r3, [r2, #108] +.L411: + ldr r3, .L414 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L414 + str r2, [r3, #72] + ldr r2, .L414 + ldr r3, .L414 + str r3, [r2, #104] + ldr r3, .L414 + ldr r2, [r3, #104] + ldr r3, .L414 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L415: + .align 2 +.L414: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r2v, .-_Z9fx_ldw_r2v + .align 2 + .type _Z9fx_ldw_r3v, %function +_Z9fx_ldw_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L420 + ldr r2, [r3, #12] + ldr r3, .L420 + str r2, [r3, #96] + ldr r3, .L420 + ldr r2, [r3, #464] + ldr r3, .L420 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L420 + ldr r2, [r3, #464] + ldr r3, .L420 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L420 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L420 + str r2, [r3, #60] + ldr r3, .L420 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L420 + ldr r2, [r3, #100] + ldr r3, .L420+4 + cmp r2, r3 + bne .L417 + ldr r3, .L420 + ldr r2, [r3, #468] + ldr r3, .L420 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L420 + strb r3, [r2, #108] +.L417: + ldr r3, .L420 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L420 + str r2, [r3, #72] + ldr r2, .L420 + ldr r3, .L420 + str r3, [r2, #104] + ldr r3, .L420 + ldr r2, [r3, #104] + ldr r3, .L420 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L421: + .align 2 +.L420: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r3v, .-_Z9fx_ldw_r3v + .align 2 + .type _Z9fx_ldw_r4v, %function +_Z9fx_ldw_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L426 + ldr r2, [r3, #16] + ldr r3, .L426 + str r2, [r3, #96] + ldr r3, .L426 + ldr r2, [r3, #464] + ldr r3, .L426 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L426 + ldr r2, [r3, #464] + ldr r3, .L426 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L426 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L426 + str r2, [r3, #60] + ldr r3, .L426 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L426 + ldr r2, [r3, #100] + ldr r3, .L426+4 + cmp r2, r3 + bne .L423 + ldr r3, .L426 + ldr r2, [r3, #468] + ldr r3, .L426 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L426 + strb r3, [r2, #108] +.L423: + ldr r3, .L426 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L426 + str r2, [r3, #72] + ldr r2, .L426 + ldr r3, .L426 + str r3, [r2, #104] + ldr r3, .L426 + ldr r2, [r3, #104] + ldr r3, .L426 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L427: + .align 2 +.L426: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r4v, .-_Z9fx_ldw_r4v + .align 2 + .type _Z9fx_ldw_r5v, %function +_Z9fx_ldw_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L432 + ldr r2, [r3, #20] + ldr r3, .L432 + str r2, [r3, #96] + ldr r3, .L432 + ldr r2, [r3, #464] + ldr r3, .L432 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L432 + ldr r2, [r3, #464] + ldr r3, .L432 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L432 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L432 + str r2, [r3, #60] + ldr r3, .L432 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L432 + ldr r2, [r3, #100] + ldr r3, .L432+4 + cmp r2, r3 + bne .L429 + ldr r3, .L432 + ldr r2, [r3, #468] + ldr r3, .L432 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L432 + strb r3, [r2, #108] +.L429: + ldr r3, .L432 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L432 + str r2, [r3, #72] + ldr r2, .L432 + ldr r3, .L432 + str r3, [r2, #104] + ldr r3, .L432 + ldr r2, [r3, #104] + ldr r3, .L432 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L433: + .align 2 +.L432: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r5v, .-_Z9fx_ldw_r5v + .align 2 + .type _Z9fx_ldw_r6v, %function +_Z9fx_ldw_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L438 + ldr r2, [r3, #24] + ldr r3, .L438 + str r2, [r3, #96] + ldr r3, .L438 + ldr r2, [r3, #464] + ldr r3, .L438 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L438 + ldr r2, [r3, #464] + ldr r3, .L438 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L438 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L438 + str r2, [r3, #60] + ldr r3, .L438 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L438 + ldr r2, [r3, #100] + ldr r3, .L438+4 + cmp r2, r3 + bne .L435 + ldr r3, .L438 + ldr r2, [r3, #468] + ldr r3, .L438 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L438 + strb r3, [r2, #108] +.L435: + ldr r3, .L438 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L438 + str r2, [r3, #72] + ldr r2, .L438 + ldr r3, .L438 + str r3, [r2, #104] + ldr r3, .L438 + ldr r2, [r3, #104] + ldr r3, .L438 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L439: + .align 2 +.L438: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r6v, .-_Z9fx_ldw_r6v + .align 2 + .type _Z9fx_ldw_r7v, %function +_Z9fx_ldw_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L444 + ldr r2, [r3, #28] + ldr r3, .L444 + str r2, [r3, #96] + ldr r3, .L444 + ldr r2, [r3, #464] + ldr r3, .L444 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L444 + ldr r2, [r3, #464] + ldr r3, .L444 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L444 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L444 + str r2, [r3, #60] + ldr r3, .L444 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L444 + ldr r2, [r3, #100] + ldr r3, .L444+4 + cmp r2, r3 + bne .L441 + ldr r3, .L444 + ldr r2, [r3, #468] + ldr r3, .L444 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L444 + strb r3, [r2, #108] +.L441: + ldr r3, .L444 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L444 + str r2, [r3, #72] + ldr r2, .L444 + ldr r3, .L444 + str r3, [r2, #104] + ldr r3, .L444 + ldr r2, [r3, #104] + ldr r3, .L444 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L445: + .align 2 +.L444: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r7v, .-_Z9fx_ldw_r7v + .align 2 + .type _Z9fx_ldw_r8v, %function +_Z9fx_ldw_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L450 + ldr r2, [r3, #32] + ldr r3, .L450 + str r2, [r3, #96] + ldr r3, .L450 + ldr r2, [r3, #464] + ldr r3, .L450 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L450 + ldr r2, [r3, #464] + ldr r3, .L450 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L450 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L450 + str r2, [r3, #60] + ldr r3, .L450 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L450 + ldr r2, [r3, #100] + ldr r3, .L450+4 + cmp r2, r3 + bne .L447 + ldr r3, .L450 + ldr r2, [r3, #468] + ldr r3, .L450 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L450 + strb r3, [r2, #108] +.L447: + ldr r3, .L450 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L450 + str r2, [r3, #72] + ldr r2, .L450 + ldr r3, .L450 + str r3, [r2, #104] + ldr r3, .L450 + ldr r2, [r3, #104] + ldr r3, .L450 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L451: + .align 2 +.L450: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r8v, .-_Z9fx_ldw_r8v + .align 2 + .type _Z9fx_ldw_r9v, %function +_Z9fx_ldw_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L456 + ldr r2, [r3, #36] + ldr r3, .L456 + str r2, [r3, #96] + ldr r3, .L456 + ldr r2, [r3, #464] + ldr r3, .L456 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L456 + ldr r2, [r3, #464] + ldr r3, .L456 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L456 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L456 + str r2, [r3, #60] + ldr r3, .L456 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L456 + ldr r2, [r3, #100] + ldr r3, .L456+4 + cmp r2, r3 + bne .L453 + ldr r3, .L456 + ldr r2, [r3, #468] + ldr r3, .L456 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L456 + strb r3, [r2, #108] +.L453: + ldr r3, .L456 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L456 + str r2, [r3, #72] + ldr r2, .L456 + ldr r3, .L456 + str r3, [r2, #104] + ldr r3, .L456 + ldr r2, [r3, #104] + ldr r3, .L456 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L457: + .align 2 +.L456: + .word GSU + .word GSU+56 + .size _Z9fx_ldw_r9v, .-_Z9fx_ldw_r9v + .align 2 + .type _Z10fx_ldw_r10v, %function +_Z10fx_ldw_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L462 + ldr r2, [r3, #40] + ldr r3, .L462 + str r2, [r3, #96] + ldr r3, .L462 + ldr r2, [r3, #464] + ldr r3, .L462 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L462 + ldr r2, [r3, #464] + ldr r3, .L462 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L462 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L462 + str r2, [r3, #60] + ldr r3, .L462 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L462 + ldr r2, [r3, #100] + ldr r3, .L462+4 + cmp r2, r3 + bne .L459 + ldr r3, .L462 + ldr r2, [r3, #468] + ldr r3, .L462 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L462 + strb r3, [r2, #108] +.L459: + ldr r3, .L462 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L462 + str r2, [r3, #72] + ldr r2, .L462 + ldr r3, .L462 + str r3, [r2, #104] + ldr r3, .L462 + ldr r2, [r3, #104] + ldr r3, .L462 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L463: + .align 2 +.L462: + .word GSU + .word GSU+56 + .size _Z10fx_ldw_r10v, .-_Z10fx_ldw_r10v + .align 2 + .type _Z10fx_ldw_r11v, %function +_Z10fx_ldw_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L468 + ldr r2, [r3, #44] + ldr r3, .L468 + str r2, [r3, #96] + ldr r3, .L468 + ldr r2, [r3, #464] + ldr r3, .L468 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L468 + ldr r2, [r3, #464] + ldr r3, .L468 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L468 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L468 + str r2, [r3, #60] + ldr r3, .L468 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L468 + ldr r2, [r3, #100] + ldr r3, .L468+4 + cmp r2, r3 + bne .L465 + ldr r3, .L468 + ldr r2, [r3, #468] + ldr r3, .L468 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L468 + strb r3, [r2, #108] +.L465: + ldr r3, .L468 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L468 + str r2, [r3, #72] + ldr r2, .L468 + ldr r3, .L468 + str r3, [r2, #104] + ldr r3, .L468 + ldr r2, [r3, #104] + ldr r3, .L468 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L469: + .align 2 +.L468: + .word GSU + .word GSU+56 + .size _Z10fx_ldw_r11v, .-_Z10fx_ldw_r11v + .align 2 + .type _Z9fx_ldb_r0v, %function +_Z9fx_ldb_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L474 + ldr r2, [r3, #0] + ldr r3, .L474 + str r2, [r3, #96] + ldr r3, .L474 + ldr r2, [r3, #464] + ldr r3, .L474 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L474 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L474 + str r2, [r3, #60] + ldr r3, .L474 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L474 + ldr r2, [r3, #100] + ldr r3, .L474+4 + cmp r2, r3 + bne .L471 + ldr r3, .L474 + ldr r2, [r3, #468] + ldr r3, .L474 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L474 + strb r3, [r2, #108] +.L471: + ldr r3, .L474 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L474 + str r2, [r3, #72] + ldr r2, .L474 + ldr r3, .L474 + str r3, [r2, #104] + ldr r3, .L474 + ldr r2, [r3, #104] + ldr r3, .L474 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L475: + .align 2 +.L474: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r0v, .-_Z9fx_ldb_r0v + .align 2 + .type _Z9fx_ldb_r1v, %function +_Z9fx_ldb_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L480 + ldr r2, [r3, #4] + ldr r3, .L480 + str r2, [r3, #96] + ldr r3, .L480 + ldr r2, [r3, #464] + ldr r3, .L480 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L480 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L480 + str r2, [r3, #60] + ldr r3, .L480 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L480 + ldr r2, [r3, #100] + ldr r3, .L480+4 + cmp r2, r3 + bne .L477 + ldr r3, .L480 + ldr r2, [r3, #468] + ldr r3, .L480 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L480 + strb r3, [r2, #108] +.L477: + ldr r3, .L480 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L480 + str r2, [r3, #72] + ldr r2, .L480 + ldr r3, .L480 + str r3, [r2, #104] + ldr r3, .L480 + ldr r2, [r3, #104] + ldr r3, .L480 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L481: + .align 2 +.L480: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r1v, .-_Z9fx_ldb_r1v + .align 2 + .type _Z9fx_ldb_r2v, %function +_Z9fx_ldb_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L486 + ldr r2, [r3, #8] + ldr r3, .L486 + str r2, [r3, #96] + ldr r3, .L486 + ldr r2, [r3, #464] + ldr r3, .L486 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L486 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L486 + str r2, [r3, #60] + ldr r3, .L486 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L486 + ldr r2, [r3, #100] + ldr r3, .L486+4 + cmp r2, r3 + bne .L483 + ldr r3, .L486 + ldr r2, [r3, #468] + ldr r3, .L486 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L486 + strb r3, [r2, #108] +.L483: + ldr r3, .L486 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L486 + str r2, [r3, #72] + ldr r2, .L486 + ldr r3, .L486 + str r3, [r2, #104] + ldr r3, .L486 + ldr r2, [r3, #104] + ldr r3, .L486 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L487: + .align 2 +.L486: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r2v, .-_Z9fx_ldb_r2v + .align 2 + .type _Z9fx_ldb_r3v, %function +_Z9fx_ldb_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L492 + ldr r2, [r3, #12] + ldr r3, .L492 + str r2, [r3, #96] + ldr r3, .L492 + ldr r2, [r3, #464] + ldr r3, .L492 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L492 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L492 + str r2, [r3, #60] + ldr r3, .L492 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L492 + ldr r2, [r3, #100] + ldr r3, .L492+4 + cmp r2, r3 + bne .L489 + ldr r3, .L492 + ldr r2, [r3, #468] + ldr r3, .L492 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L492 + strb r3, [r2, #108] +.L489: + ldr r3, .L492 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L492 + str r2, [r3, #72] + ldr r2, .L492 + ldr r3, .L492 + str r3, [r2, #104] + ldr r3, .L492 + ldr r2, [r3, #104] + ldr r3, .L492 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L493: + .align 2 +.L492: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r3v, .-_Z9fx_ldb_r3v + .align 2 + .type _Z9fx_ldb_r4v, %function +_Z9fx_ldb_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L498 + ldr r2, [r3, #16] + ldr r3, .L498 + str r2, [r3, #96] + ldr r3, .L498 + ldr r2, [r3, #464] + ldr r3, .L498 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L498 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L498 + str r2, [r3, #60] + ldr r3, .L498 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L498 + ldr r2, [r3, #100] + ldr r3, .L498+4 + cmp r2, r3 + bne .L495 + ldr r3, .L498 + ldr r2, [r3, #468] + ldr r3, .L498 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L498 + strb r3, [r2, #108] +.L495: + ldr r3, .L498 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L498 + str r2, [r3, #72] + ldr r2, .L498 + ldr r3, .L498 + str r3, [r2, #104] + ldr r3, .L498 + ldr r2, [r3, #104] + ldr r3, .L498 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L499: + .align 2 +.L498: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r4v, .-_Z9fx_ldb_r4v + .align 2 + .type _Z9fx_ldb_r5v, %function +_Z9fx_ldb_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L504 + ldr r2, [r3, #20] + ldr r3, .L504 + str r2, [r3, #96] + ldr r3, .L504 + ldr r2, [r3, #464] + ldr r3, .L504 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L504 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L504 + str r2, [r3, #60] + ldr r3, .L504 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L504 + ldr r2, [r3, #100] + ldr r3, .L504+4 + cmp r2, r3 + bne .L501 + ldr r3, .L504 + ldr r2, [r3, #468] + ldr r3, .L504 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L504 + strb r3, [r2, #108] +.L501: + ldr r3, .L504 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L504 + str r2, [r3, #72] + ldr r2, .L504 + ldr r3, .L504 + str r3, [r2, #104] + ldr r3, .L504 + ldr r2, [r3, #104] + ldr r3, .L504 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L505: + .align 2 +.L504: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r5v, .-_Z9fx_ldb_r5v + .align 2 + .type _Z9fx_ldb_r6v, %function +_Z9fx_ldb_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L510 + ldr r2, [r3, #24] + ldr r3, .L510 + str r2, [r3, #96] + ldr r3, .L510 + ldr r2, [r3, #464] + ldr r3, .L510 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L510 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L510 + str r2, [r3, #60] + ldr r3, .L510 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L510 + ldr r2, [r3, #100] + ldr r3, .L510+4 + cmp r2, r3 + bne .L507 + ldr r3, .L510 + ldr r2, [r3, #468] + ldr r3, .L510 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L510 + strb r3, [r2, #108] +.L507: + ldr r3, .L510 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L510 + str r2, [r3, #72] + ldr r2, .L510 + ldr r3, .L510 + str r3, [r2, #104] + ldr r3, .L510 + ldr r2, [r3, #104] + ldr r3, .L510 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L511: + .align 2 +.L510: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r6v, .-_Z9fx_ldb_r6v + .align 2 + .type _Z9fx_ldb_r7v, %function +_Z9fx_ldb_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L516 + ldr r2, [r3, #28] + ldr r3, .L516 + str r2, [r3, #96] + ldr r3, .L516 + ldr r2, [r3, #464] + ldr r3, .L516 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L516 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L516 + str r2, [r3, #60] + ldr r3, .L516 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L516 + ldr r2, [r3, #100] + ldr r3, .L516+4 + cmp r2, r3 + bne .L513 + ldr r3, .L516 + ldr r2, [r3, #468] + ldr r3, .L516 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L516 + strb r3, [r2, #108] +.L513: + ldr r3, .L516 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L516 + str r2, [r3, #72] + ldr r2, .L516 + ldr r3, .L516 + str r3, [r2, #104] + ldr r3, .L516 + ldr r2, [r3, #104] + ldr r3, .L516 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L517: + .align 2 +.L516: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r7v, .-_Z9fx_ldb_r7v + .align 2 + .type _Z9fx_ldb_r8v, %function +_Z9fx_ldb_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L522 + ldr r2, [r3, #32] + ldr r3, .L522 + str r2, [r3, #96] + ldr r3, .L522 + ldr r2, [r3, #464] + ldr r3, .L522 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L522 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L522 + str r2, [r3, #60] + ldr r3, .L522 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L522 + ldr r2, [r3, #100] + ldr r3, .L522+4 + cmp r2, r3 + bne .L519 + ldr r3, .L522 + ldr r2, [r3, #468] + ldr r3, .L522 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L522 + strb r3, [r2, #108] +.L519: + ldr r3, .L522 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L522 + str r2, [r3, #72] + ldr r2, .L522 + ldr r3, .L522 + str r3, [r2, #104] + ldr r3, .L522 + ldr r2, [r3, #104] + ldr r3, .L522 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L523: + .align 2 +.L522: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r8v, .-_Z9fx_ldb_r8v + .align 2 + .type _Z9fx_ldb_r9v, %function +_Z9fx_ldb_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L528 + ldr r2, [r3, #36] + ldr r3, .L528 + str r2, [r3, #96] + ldr r3, .L528 + ldr r2, [r3, #464] + ldr r3, .L528 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L528 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L528 + str r2, [r3, #60] + ldr r3, .L528 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L528 + ldr r2, [r3, #100] + ldr r3, .L528+4 + cmp r2, r3 + bne .L525 + ldr r3, .L528 + ldr r2, [r3, #468] + ldr r3, .L528 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L528 + strb r3, [r2, #108] +.L525: + ldr r3, .L528 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L528 + str r2, [r3, #72] + ldr r2, .L528 + ldr r3, .L528 + str r3, [r2, #104] + ldr r3, .L528 + ldr r2, [r3, #104] + ldr r3, .L528 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L529: + .align 2 +.L528: + .word GSU + .word GSU+56 + .size _Z9fx_ldb_r9v, .-_Z9fx_ldb_r9v + .align 2 + .type _Z10fx_ldb_r10v, %function +_Z10fx_ldb_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L534 + ldr r2, [r3, #40] + ldr r3, .L534 + str r2, [r3, #96] + ldr r3, .L534 + ldr r2, [r3, #464] + ldr r3, .L534 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L534 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L534 + str r2, [r3, #60] + ldr r3, .L534 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L534 + ldr r2, [r3, #100] + ldr r3, .L534+4 + cmp r2, r3 + bne .L531 + ldr r3, .L534 + ldr r2, [r3, #468] + ldr r3, .L534 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L534 + strb r3, [r2, #108] +.L531: + ldr r3, .L534 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L534 + str r2, [r3, #72] + ldr r2, .L534 + ldr r3, .L534 + str r3, [r2, #104] + ldr r3, .L534 + ldr r2, [r3, #104] + ldr r3, .L534 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L535: + .align 2 +.L534: + .word GSU + .word GSU+56 + .size _Z10fx_ldb_r10v, .-_Z10fx_ldb_r10v + .align 2 + .type _Z10fx_ldb_r11v, %function +_Z10fx_ldb_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L540 + ldr r2, [r3, #44] + ldr r3, .L540 + str r2, [r3, #96] + ldr r3, .L540 + ldr r2, [r3, #464] + ldr r3, .L540 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L540 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L540 + str r2, [r3, #60] + ldr r3, .L540 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L540 + ldr r2, [r3, #100] + ldr r3, .L540+4 + cmp r2, r3 + bne .L537 + ldr r3, .L540 + ldr r2, [r3, #468] + ldr r3, .L540 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L540 + strb r3, [r2, #108] +.L537: + ldr r3, .L540 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L540 + str r2, [r3, #72] + ldr r2, .L540 + ldr r3, .L540 + str r3, [r2, #104] + ldr r3, .L540 + ldr r2, [r3, #104] + ldr r3, .L540 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L541: + .align 2 +.L540: + .word GSU + .word GSU+56 + .size _Z10fx_ldb_r11v, .-_Z10fx_ldb_r11v + .align 2 + .type _Z12fx_plot_2bitv, %function +_Z12fx_plot_2bitv: + @ args = 0, pretend = 0, frame = 20 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #20 + ldr r3, .L559 + ldr r3, [r3, #4] + and r3, r3, #255 + str r3, [fp, #-28] + ldr r3, .L559 + ldr r3, [r3, #8] + and r3, r3, #255 + str r3, [fp, #-24] + ldr r3, .L559 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L559 + str r2, [r3, #60] + ldr r3, .L559 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L559 + str r2, [r3, #72] + ldr r2, .L559 + ldr r3, .L559 + str r3, [r2, #104] + ldr r3, .L559 + ldr r2, [r3, #104] + ldr r3, .L559 + str r2, [r3, #100] + ldr r3, .L559 + ldr r3, [r3, #4] + add r2, r3, #1 + ldr r3, .L559 + str r2, [r3, #4] + ldr r3, .L559 + ldr r2, [r3, #440] + ldr r3, [fp, #-24] + cmp r2, r3 + bls .L558 + ldr r3, .L559 + ldr r3, [r3, #68] + and r3, r3, #2 + cmp r3, #0 + beq .L545 + ldr r2, [fp, #-28] + ldr r3, [fp, #-24] + eor r3, r2, r3 + and r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L547 + ldr r3, .L559 + ldr r3, [r3, #64] + mov r3, r3, lsr #4 + and r3, r3, #255 + str r3, [fp, #-32] + b .L549 +.L547: + ldr r3, .L559 + ldr r3, [r3, #64] + and r3, r3, #255 + str r3, [fp, #-32] +.L549: + ldr r2, [fp, #-32] + mov r3, r2 + strb r3, [fp, #-13] + b .L550 +.L545: + ldr r3, .L559 + ldr r3, [r3, #64] + strb r3, [fp, #-13] +.L550: + ldr r3, .L559 + ldr r3, [r3, #68] + and r3, r3, #1 + and r3, r3, #255 + eor r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L551 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #15 + cmp r3, #0 + beq .L558 +.L551: + ldr r3, [fp, #-24] + mov r3, r3, lsr #3 + ldr r2, .L559 + mov r1, #184 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r0, [r3, #0] + ldr r3, [fp, #-28] + mov r3, r3, lsr #3 + ldr r2, .L559 + mov r1, #312 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r3, [r3, #0] + add r2, r0, r3 + ldr r3, [fp, #-24] + and r3, r3, #7 + mov r3, r3, asl #1 + add r3, r2, r3 + str r3, [fp, #-20] + ldr r3, [fp, #-28] + and r2, r3, #7 + mov r3, #128 + mov r3, r3, asr r2 + strb r3, [fp, #-14] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L553 + ldr r3, [fp, #-20] + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + ldr r2, [fp, #-20] + strb r3, [r2, #0] + b .L555 +.L553: + ldr r3, [fp, #-20] + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + ldr r2, [fp, #-20] + strb r3, [r2, #0] +.L555: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #2 + cmp r3, #0 + beq .L556 + ldr r3, [fp, #-20] + add r1, r3, #1 + ldr r3, [fp, #-20] + add r3, r3, #1 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L558 +.L556: + ldr r3, [fp, #-20] + add r1, r3, #1 + ldr r3, [fp, #-20] + add r3, r3, #1 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L558: + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L560: + .align 2 +.L559: + .word GSU + .size _Z12fx_plot_2bitv, .-_Z12fx_plot_2bitv + .align 2 + .type _Z12fx_rpix_2bitv, %function +_Z12fx_rpix_2bitv: + @ args = 0, pretend = 0, frame = 28 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #28 + ldr r3, .L569 + ldr r3, [r3, #4] + and r3, r3, #255 + str r3, [fp, #-28] + ldr r3, .L569 + ldr r3, [r3, #8] + and r3, r3, #255 + str r3, [fp, #-24] + ldr r3, .L569 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L569 + str r2, [r3, #60] + ldr r3, .L569 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L569 + str r2, [r3, #72] + ldr r2, .L569 + ldr r3, .L569 + str r3, [r2, #104] + ldr r3, .L569 + ldr r2, [r3, #104] + ldr r3, .L569 + str r2, [r3, #100] + ldr r3, .L569 + ldr r2, [r3, #440] + ldr r3, [fp, #-24] + cmp r2, r3 + bls .L568 + ldr r3, [fp, #-24] + mov r3, r3, lsr #3 + ldr r2, .L569 + mov r1, #184 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r0, [r3, #0] + ldr r3, [fp, #-28] + mov r3, r3, lsr #3 + ldr r2, .L569 + mov r1, #312 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r3, [r3, #0] + add r2, r0, r3 + ldr r3, [fp, #-24] + and r3, r3, #7 + mov r3, r3, asl #1 + add r3, r2, r3 + str r3, [fp, #-20] + ldr r3, [fp, #-28] + and r2, r3, #7 + mov r3, #128 + mov r3, r3, asr r2 + strb r3, [fp, #-13] + ldr r3, .L569 + ldr r2, [r3, #100] + mov r3, #0 + str r3, [r2, #0] + ldr r3, .L569 + ldr r0, [r3, #100] + ldr r3, .L569 + ldr r3, [r3, #100] + ldr r1, [r3, #0] + ldr r3, [fp, #-20] + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + moveq r3, #0 + movne r3, #1 + orr r3, r1, r3 + str r3, [r0, #0] + ldr r3, .L569 + ldr r3, [r3, #100] + str r3, [fp, #-40] + ldr r3, .L569 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-36] + ldr r3, [fp, #-20] + add r3, r3, #1 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L564 + mov r1, #2 + str r1, [fp, #-32] + b .L566 +.L564: + mov r2, #0 + str r2, [fp, #-32] +.L566: + ldr r1, [fp, #-36] + ldr r2, [fp, #-32] + orr r3, r1, r2 + ldr r1, [fp, #-40] + str r3, [r1, #0] + ldr r3, .L569 + ldr r2, [r3, #100] + ldr r3, .L569+4 + cmp r2, r3 + bne .L568 + ldr r3, .L569 + ldr r2, [r3, #468] + ldr r3, .L569 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L569 + strb r3, [r2, #108] +.L568: + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L570: + .align 2 +.L569: + .word GSU + .word GSU+56 + .size _Z12fx_rpix_2bitv, .-_Z12fx_rpix_2bitv + .align 2 + .type _Z12fx_plot_4bitv, %function +_Z12fx_plot_4bitv: + @ args = 0, pretend = 0, frame = 20 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #20 + ldr r3, .L594 + ldr r3, [r3, #4] + and r3, r3, #255 + str r3, [fp, #-28] + ldr r3, .L594 + ldr r3, [r3, #8] + and r3, r3, #255 + str r3, [fp, #-24] + ldr r3, .L594 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L594 + str r2, [r3, #60] + ldr r3, .L594 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L594 + str r2, [r3, #72] + ldr r2, .L594 + ldr r3, .L594 + str r3, [r2, #104] + ldr r3, .L594 + ldr r2, [r3, #104] + ldr r3, .L594 + str r2, [r3, #100] + ldr r3, .L594 + ldr r3, [r3, #4] + add r2, r3, #1 + ldr r3, .L594 + str r2, [r3, #4] + ldr r3, .L594 + ldr r2, [r3, #440] + ldr r3, [fp, #-24] + cmp r2, r3 + bls .L593 + ldr r3, .L594 + ldr r3, [r3, #68] + and r3, r3, #2 + cmp r3, #0 + beq .L574 + ldr r2, [fp, #-28] + ldr r3, [fp, #-24] + eor r3, r2, r3 + and r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L576 + ldr r3, .L594 + ldr r3, [r3, #64] + mov r3, r3, lsr #4 + and r3, r3, #255 + str r3, [fp, #-32] + b .L578 +.L576: + ldr r3, .L594 + ldr r3, [r3, #64] + and r3, r3, #255 + str r3, [fp, #-32] +.L578: + ldr r2, [fp, #-32] + mov r3, r2 + strb r3, [fp, #-13] + b .L579 +.L574: + ldr r3, .L594 + ldr r3, [r3, #64] + strb r3, [fp, #-13] +.L579: + ldr r3, .L594 + ldr r3, [r3, #68] + and r3, r3, #1 + and r3, r3, #255 + eor r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L580 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #15 + cmp r3, #0 + beq .L593 +.L580: + ldr r3, [fp, #-24] + mov r3, r3, lsr #3 + ldr r2, .L594 + mov r1, #184 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r0, [r3, #0] + ldr r3, [fp, #-28] + mov r3, r3, lsr #3 + ldr r2, .L594 + mov r1, #312 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r3, [r3, #0] + add r2, r0, r3 + ldr r3, [fp, #-24] + and r3, r3, #7 + mov r3, r3, asl #1 + add r3, r2, r3 + str r3, [fp, #-20] + ldr r3, [fp, #-28] + and r2, r3, #7 + mov r3, #128 + mov r3, r3, asr r2 + strb r3, [fp, #-14] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L582 + ldr r3, [fp, #-20] + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + ldr r2, [fp, #-20] + strb r3, [r2, #0] + b .L584 +.L582: + ldr r3, [fp, #-20] + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + ldr r2, [fp, #-20] + strb r3, [r2, #0] +.L584: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #2 + cmp r3, #0 + beq .L585 + ldr r3, [fp, #-20] + add r1, r3, #1 + ldr r3, [fp, #-20] + add r3, r3, #1 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L587 +.L585: + ldr r3, [fp, #-20] + add r1, r3, #1 + ldr r3, [fp, #-20] + add r3, r3, #1 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L587: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #4 + cmp r3, #0 + beq .L588 + ldr r3, [fp, #-20] + add r1, r3, #16 + ldr r3, [fp, #-20] + add r3, r3, #16 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L590 +.L588: + ldr r3, [fp, #-20] + add r1, r3, #16 + ldr r3, [fp, #-20] + add r3, r3, #16 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L590: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #8 + cmp r3, #0 + beq .L591 + ldr r3, [fp, #-20] + add r1, r3, #17 + ldr r3, [fp, #-20] + add r3, r3, #17 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L593 +.L591: + ldr r3, [fp, #-20] + add r1, r3, #17 + ldr r3, [fp, #-20] + add r3, r3, #17 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L593: + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L595: + .align 2 +.L594: + .word GSU + .size _Z12fx_plot_4bitv, .-_Z12fx_plot_4bitv + .align 2 + .type _Z12fx_rpix_4bitv, %function +_Z12fx_rpix_4bitv: + @ args = 0, pretend = 0, frame = 52 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #52 + ldr r3, .L610 + ldr r3, [r3, #4] + and r3, r3, #255 + str r3, [fp, #-28] + ldr r3, .L610 + ldr r3, [r3, #8] + and r3, r3, #255 + str r3, [fp, #-24] + ldr r3, .L610 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L610 + str r2, [r3, #60] + ldr r3, .L610 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L610 + str r2, [r3, #72] + ldr r2, .L610 + ldr r3, .L610 + str r3, [r2, #104] + ldr r3, .L610 + ldr r2, [r3, #104] + ldr r3, .L610 + str r2, [r3, #100] + ldr r3, .L610 + ldr r2, [r3, #440] + ldr r3, [fp, #-24] + cmp r2, r3 + bls .L609 + ldr r3, [fp, #-24] + mov r3, r3, lsr #3 + ldr r2, .L610 + mov r1, #184 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r0, [r3, #0] + ldr r3, [fp, #-28] + mov r3, r3, lsr #3 + ldr r2, .L610 + mov r1, #312 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r3, [r3, #0] + add r2, r0, r3 + ldr r3, [fp, #-24] + and r3, r3, #7 + mov r3, r3, asl #1 + add r3, r2, r3 + str r3, [fp, #-20] + ldr r3, [fp, #-28] + and r2, r3, #7 + mov r3, #128 + mov r3, r3, asr r2 + strb r3, [fp, #-13] + ldr r3, .L610 + ldr r2, [r3, #100] + mov r3, #0 + str r3, [r2, #0] + ldr r3, .L610 + ldr r0, [r3, #100] + ldr r3, .L610 + ldr r3, [r3, #100] + ldr r1, [r3, #0] + ldr r3, [fp, #-20] + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + moveq r3, #0 + movne r3, #1 + orr r3, r1, r3 + str r3, [r0, #0] + ldr r3, .L610 + ldr r3, [r3, #100] + str r3, [fp, #-64] + ldr r3, .L610 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-60] + ldr r3, [fp, #-20] + add r3, r3, #1 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L599 + mov r1, #2 + str r1, [fp, #-56] + b .L601 +.L599: + mov r2, #0 + str r2, [fp, #-56] +.L601: + ldr r1, [fp, #-60] + ldr r2, [fp, #-56] + orr r3, r1, r2 + ldr r1, [fp, #-64] + str r3, [r1, #0] + ldr r3, .L610 + ldr r3, [r3, #100] + str r3, [fp, #-52] + ldr r3, .L610 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-48] + ldr r3, [fp, #-20] + add r3, r3, #16 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L602 + mov r2, #4 + str r2, [fp, #-44] + b .L604 +.L602: + mov r3, #0 + str r3, [fp, #-44] +.L604: + ldr r1, [fp, #-48] + ldr r2, [fp, #-44] + orr r3, r1, r2 + ldr r1, [fp, #-52] + str r3, [r1, #0] + ldr r3, .L610 + ldr r3, [r3, #100] + str r3, [fp, #-40] + ldr r3, .L610 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-36] + ldr r3, [fp, #-20] + add r3, r3, #17 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L605 + mov r2, #8 + str r2, [fp, #-32] + b .L607 +.L605: + mov r3, #0 + str r3, [fp, #-32] +.L607: + ldr r1, [fp, #-36] + ldr r2, [fp, #-32] + orr r3, r1, r2 + ldr r1, [fp, #-40] + str r3, [r1, #0] + ldr r3, .L610 + ldr r2, [r3, #100] + ldr r3, .L610+4 + cmp r2, r3 + bne .L609 + ldr r3, .L610 + ldr r2, [r3, #468] + ldr r3, .L610 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L610 + strb r3, [r2, #108] +.L609: + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L611: + .align 2 +.L610: + .word GSU + .word GSU+56 + .size _Z12fx_rpix_4bitv, .-_Z12fx_rpix_4bitv + .align 2 + .type _Z12fx_plot_8bitv, %function +_Z12fx_plot_8bitv: + @ args = 0, pretend = 0, frame = 16 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #16 + ldr r3, .L645 + ldr r3, [r3, #4] + and r3, r3, #255 + str r3, [fp, #-28] + ldr r3, .L645 + ldr r3, [r3, #8] + and r3, r3, #255 + str r3, [fp, #-24] + ldr r3, .L645 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L645 + str r2, [r3, #60] + ldr r3, .L645 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L645 + str r2, [r3, #72] + ldr r2, .L645 + ldr r3, .L645 + str r3, [r2, #104] + ldr r3, .L645 + ldr r2, [r3, #104] + ldr r3, .L645 + str r2, [r3, #100] + ldr r3, .L645 + ldr r3, [r3, #4] + add r2, r3, #1 + ldr r3, .L645 + str r2, [r3, #4] + ldr r3, .L645 + ldr r2, [r3, #440] + ldr r3, [fp, #-24] + cmp r2, r3 + bls .L644 + ldr r3, .L645 + ldr r3, [r3, #64] + strb r3, [fp, #-13] + ldr r3, .L645 + ldr r3, [r3, #68] + and r3, r3, #16 + cmp r3, #0 + bne .L615 + ldr r3, .L645 + ldr r3, [r3, #68] + and r3, r3, #1 + and r3, r3, #255 + eor r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L619 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #15 + cmp r3, #0 + beq .L644 + b .L619 +.L615: + ldr r3, .L645 + ldr r3, [r3, #68] + and r3, r3, #1 + and r3, r3, #255 + eor r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L619 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + cmp r3, #0 + beq .L644 +.L619: + ldr r3, [fp, #-24] + mov r3, r3, lsr #3 + ldr r2, .L645 + mov r1, #184 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r0, [r3, #0] + ldr r3, [fp, #-28] + mov r3, r3, lsr #3 + ldr r2, .L645 + mov r1, #312 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r3, [r3, #0] + add r2, r0, r3 + ldr r3, [fp, #-24] + and r3, r3, #7 + mov r3, r3, asl #1 + add r3, r2, r3 + str r3, [fp, #-20] + ldr r3, [fp, #-28] + and r2, r3, #7 + mov r3, #128 + mov r3, r3, asr r2 + strb r3, [fp, #-14] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #1 + and r3, r3, #255 + cmp r3, #0 + beq .L621 + ldr r3, [fp, #-20] + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + ldr r2, [fp, #-20] + strb r3, [r2, #0] + b .L623 +.L621: + ldr r3, [fp, #-20] + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + ldr r2, [fp, #-20] + strb r3, [r2, #0] +.L623: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #2 + cmp r3, #0 + beq .L624 + ldr r3, [fp, #-20] + add r1, r3, #1 + ldr r3, [fp, #-20] + add r3, r3, #1 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L626 +.L624: + ldr r3, [fp, #-20] + add r1, r3, #1 + ldr r3, [fp, #-20] + add r3, r3, #1 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L626: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #4 + cmp r3, #0 + beq .L627 + ldr r3, [fp, #-20] + add r1, r3, #16 + ldr r3, [fp, #-20] + add r3, r3, #16 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L629 +.L627: + ldr r3, [fp, #-20] + add r1, r3, #16 + ldr r3, [fp, #-20] + add r3, r3, #16 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L629: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #8 + cmp r3, #0 + beq .L630 + ldr r3, [fp, #-20] + add r1, r3, #17 + ldr r3, [fp, #-20] + add r3, r3, #17 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L632 +.L630: + ldr r3, [fp, #-20] + add r1, r3, #17 + ldr r3, [fp, #-20] + add r3, r3, #17 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L632: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #16 + cmp r3, #0 + beq .L633 + ldr r3, [fp, #-20] + add r1, r3, #32 + ldr r3, [fp, #-20] + add r3, r3, #32 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L635 +.L633: + ldr r3, [fp, #-20] + add r1, r3, #32 + ldr r3, [fp, #-20] + add r3, r3, #32 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L635: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #32 + cmp r3, #0 + beq .L636 + ldr r3, [fp, #-20] + add r1, r3, #33 + ldr r3, [fp, #-20] + add r3, r3, #33 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L638 +.L636: + ldr r3, [fp, #-20] + add r1, r3, #33 + ldr r3, [fp, #-20] + add r3, r3, #33 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L638: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #64 + cmp r3, #0 + beq .L639 + ldr r3, [fp, #-20] + add r1, r3, #48 + ldr r3, [fp, #-20] + add r3, r3, #48 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L641 +.L639: + ldr r3, [fp, #-20] + add r1, r3, #48 + ldr r3, [fp, #-20] + add r3, r3, #48 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L641: + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + cmp r3, #0 + bge .L642 + ldr r3, [fp, #-20] + add r1, r3, #49 + ldr r3, [fp, #-20] + add r3, r3, #49 + ldrb r2, [r3, #0] @ zero_extendqisi2 + ldrb r3, [fp, #-14] + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [r1, #0] + b .L644 +.L642: + ldr r3, [fp, #-20] + add r1, r3, #49 + ldr r3, [fp, #-20] + add r3, r3, #49 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-14] @ zero_extendqisi2 + mvn r3, r3 + and r3, r3, #255 + and r3, r2, r3 + and r3, r3, #255 + and r3, r3, #255 + strb r3, [r1, #0] +.L644: + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L646: + .align 2 +.L645: + .word GSU + .size _Z12fx_plot_8bitv, .-_Z12fx_plot_8bitv + .align 2 + .type _Z12fx_rpix_8bitv, %function +_Z12fx_rpix_8bitv: + @ args = 0, pretend = 0, frame = 100 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #100 + ldr r3, .L673 + ldr r3, [r3, #4] + and r3, r3, #255 + str r3, [fp, #-28] + ldr r3, .L673 + ldr r3, [r3, #8] + and r3, r3, #255 + str r3, [fp, #-24] + ldr r3, .L673 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L673 + str r2, [r3, #60] + ldr r3, .L673 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L673 + str r2, [r3, #72] + ldr r2, .L673 + ldr r3, .L673 + str r3, [r2, #104] + ldr r3, .L673 + ldr r2, [r3, #104] + ldr r3, .L673 + str r2, [r3, #100] + ldr r3, .L673 + ldr r2, [r3, #440] + ldr r3, [fp, #-24] + cmp r2, r3 + bls .L672 + ldr r3, [fp, #-24] + mov r3, r3, lsr #3 + ldr r2, .L673 + mov r1, #184 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r0, [r3, #0] + ldr r3, [fp, #-28] + mov r3, r3, lsr #3 + ldr r2, .L673 + mov r1, #312 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r3, [r3, #0] + add r2, r0, r3 + ldr r3, [fp, #-24] + and r3, r3, #7 + mov r3, r3, asl #1 + add r3, r2, r3 + str r3, [fp, #-20] + ldr r3, [fp, #-28] + and r2, r3, #7 + mov r3, #128 + mov r3, r3, asr r2 + strb r3, [fp, #-13] + ldr r3, .L673 + ldr r2, [r3, #100] + mov r3, #0 + str r3, [r2, #0] + ldr r3, .L673 + ldr r0, [r3, #100] + ldr r3, .L673 + ldr r3, [r3, #100] + ldr r1, [r3, #0] + ldr r3, [fp, #-20] + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + moveq r3, #0 + movne r3, #1 + orr r3, r1, r3 + str r3, [r0, #0] + ldr r3, .L673 + ldr r3, [r3, #100] + str r3, [fp, #-112] + ldr r3, .L673 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-108] + ldr r3, [fp, #-20] + add r3, r3, #1 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L650 + mov r1, #2 + str r1, [fp, #-104] + b .L652 +.L650: + mov r2, #0 + str r2, [fp, #-104] +.L652: + ldr r1, [fp, #-108] + ldr r2, [fp, #-104] + orr r3, r1, r2 + ldr r1, [fp, #-112] + str r3, [r1, #0] + ldr r3, .L673 + ldr r3, [r3, #100] + str r3, [fp, #-100] + ldr r3, .L673 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-96] + ldr r3, [fp, #-20] + add r3, r3, #16 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L653 + mov r2, #4 + str r2, [fp, #-92] + b .L655 +.L653: + mov r3, #0 + str r3, [fp, #-92] +.L655: + ldr r1, [fp, #-96] + ldr r2, [fp, #-92] + orr r3, r1, r2 + ldr r1, [fp, #-100] + str r3, [r1, #0] + ldr r3, .L673 + ldr r3, [r3, #100] + str r3, [fp, #-88] + ldr r3, .L673 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-84] + ldr r3, [fp, #-20] + add r3, r3, #17 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L656 + mov r2, #8 + str r2, [fp, #-80] + b .L658 +.L656: + mov r3, #0 + str r3, [fp, #-80] +.L658: + ldr r1, [fp, #-84] + ldr r2, [fp, #-80] + orr r3, r1, r2 + ldr r1, [fp, #-88] + str r3, [r1, #0] + ldr r3, .L673 + ldr r3, [r3, #100] + str r3, [fp, #-76] + ldr r3, .L673 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-72] + ldr r3, [fp, #-20] + add r3, r3, #32 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L659 + mov r2, #16 + str r2, [fp, #-68] + b .L661 +.L659: + mov r3, #0 + str r3, [fp, #-68] +.L661: + ldr r1, [fp, #-72] + ldr r2, [fp, #-68] + orr r3, r1, r2 + ldr r1, [fp, #-76] + str r3, [r1, #0] + ldr r3, .L673 + ldr r3, [r3, #100] + str r3, [fp, #-64] + ldr r3, .L673 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-60] + ldr r3, [fp, #-20] + add r3, r3, #33 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L662 + mov r2, #32 + str r2, [fp, #-56] + b .L664 +.L662: + mov r3, #0 + str r3, [fp, #-56] +.L664: + ldr r1, [fp, #-60] + ldr r2, [fp, #-56] + orr r3, r1, r2 + ldr r1, [fp, #-64] + str r3, [r1, #0] + ldr r3, .L673 + ldr r3, [r3, #100] + str r3, [fp, #-52] + ldr r3, .L673 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-48] + ldr r3, [fp, #-20] + add r3, r3, #48 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L665 + mov r2, #64 + str r2, [fp, #-44] + b .L667 +.L665: + mov r3, #0 + str r3, [fp, #-44] +.L667: + ldr r1, [fp, #-48] + ldr r2, [fp, #-44] + orr r3, r1, r2 + ldr r1, [fp, #-52] + str r3, [r1, #0] + ldr r3, .L673 + ldr r3, [r3, #100] + str r3, [fp, #-40] + ldr r3, .L673 + ldr r3, [r3, #100] + ldr r3, [r3, #0] + str r3, [fp, #-36] + ldr r3, [fp, #-20] + add r3, r3, #49 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r2, r3 + cmp r3, #0 + beq .L668 + mov r2, #128 + str r2, [fp, #-32] + b .L670 +.L668: + mov r3, #0 + str r3, [fp, #-32] +.L670: + ldr r1, [fp, #-36] + ldr r2, [fp, #-32] + orr r3, r1, r2 + ldr r1, [fp, #-40] + str r3, [r1, #0] + ldr r3, .L673 + ldr r3, [r3, #100] + ldr r2, [r3, #0] + ldr r3, .L673 + str r2, [r3, #120] + ldr r3, .L673 + ldr r2, [r3, #100] + ldr r3, .L673+4 + cmp r2, r3 + bne .L672 + ldr r3, .L673 + ldr r2, [r3, #468] + ldr r3, .L673 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L673 + strb r3, [r2, #108] +.L672: + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L674: + .align 2 +.L673: + .word GSU + .word GSU+56 + .size _Z12fx_rpix_8bitv, .-_Z12fx_rpix_8bitv + .align 2 + .type _Z7fx_swapv, %function +_Z7fx_swapv: + @ args = 0, pretend = 0, frame = 8 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #8 + ldr r3, .L679 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + strb r3, [fp, #-18] + ldr r3, .L679 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + strb r3, [fp, #-17] + ldrb r3, [fp, #-18] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldrb r3, [fp, #-17] @ zero_extendqisi2 + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L679 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L679 + str r2, [r3, #60] + ldr r3, .L679 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L679 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L679 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L679 + ldr r2, [r3, #100] + ldr r3, .L679+4 + cmp r2, r3 + bne .L676 + ldr r3, .L679 + ldr r2, [r3, #468] + ldr r3, .L679 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L679 + strb r3, [r2, #108] +.L676: + ldr r3, .L679 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L679 + str r2, [r3, #72] + ldr r2, .L679 + ldr r3, .L679 + str r3, [r2, #104] + ldr r3, .L679 + ldr r2, [r3, #104] + ldr r3, .L679 + str r2, [r3, #100] + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L680: + .align 2 +.L679: + .word GSU + .word GSU+56 + .size _Z7fx_swapv, .-_Z7fx_swapv + .align 2 + .type _Z8fx_colorv, %function +_Z8fx_colorv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L688 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + strb r3, [fp, #-13] + ldr r3, .L688 + ldr r3, [r3, #68] + and r3, r3, #4 + cmp r3, #0 + beq .L682 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r2, r3, #255 + mov r3, #240 + and r2, r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, lsr #4 + and r3, r3, #255 + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [fp, #-13] +.L682: + ldr r3, .L688 + ldr r3, [r3, #68] + and r3, r3, #8 + cmp r3, #0 + beq .L684 + ldr r3, .L688 + ldr r3, [r3, #64] + and r2, r3, #240 + ldr r3, .L688 + str r2, [r3, #64] + ldr r3, .L688 + ldr r2, [r3, #64] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #15 + orr r2, r2, r3 + ldr r3, .L688 + str r2, [r3, #64] + b .L686 +.L684: + ldrb r2, [fp, #-13] @ zero_extendqisi2 + ldr r3, .L688 + str r2, [r3, #64] +.L686: + ldr r3, .L688 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L688 + str r2, [r3, #72] + ldr r2, .L688 + ldr r3, .L688 + str r3, [r2, #104] + ldr r3, .L688 + ldr r2, [r3, #104] + ldr r3, .L688 + str r2, [r3, #100] + ldr r3, .L688 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L688 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L689: + .align 2 +.L688: + .word GSU + .size _Z8fx_colorv, .-_Z8fx_colorv + .align 2 + .type _Z6fx_notv, %function +_Z6fx_notv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L694 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mvn r3, r3 + str r3, [fp, #-16] + ldr r3, .L694 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L694 + str r2, [r3, #60] + ldr r3, .L694 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L694 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L694 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L694 + ldr r2, [r3, #100] + ldr r3, .L694+4 + cmp r2, r3 + bne .L691 + ldr r3, .L694 + ldr r2, [r3, #468] + ldr r3, .L694 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L694 + strb r3, [r2, #108] +.L691: + ldr r3, .L694 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L694 + str r2, [r3, #72] + ldr r2, .L694 + ldr r3, .L694 + str r3, [r2, #104] + ldr r3, .L694 + ldr r2, [r3, #104] + ldr r3, .L694 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L695: + .align 2 +.L694: + .word GSU + .word GSU+56 + .size _Z6fx_notv, .-_Z6fx_notv + .align 2 + .type _Z9fx_add_r0v, %function +_Z9fx_add_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L700 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L700 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L700+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L700 + str r2, [r3, #124] + ldr r3, .L700 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L700 + ldr r3, [r3, #0] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L700 + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L700 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L700 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L700 + str r2, [r3, #120] + ldr r3, .L700 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L700 + str r2, [r3, #60] + ldr r3, .L700 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L700 + ldr r2, [r3, #100] + ldr r3, .L700+8 + cmp r2, r3 + bne .L697 + ldr r3, .L700 + ldr r2, [r3, #468] + ldr r3, .L700 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L700 + strb r3, [r2, #108] +.L697: + ldr r3, .L700 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L700 + str r2, [r3, #72] + ldr r2, .L700 + ldr r3, .L700 + str r3, [r2, #104] + ldr r3, .L700 + ldr r2, [r3, #104] + ldr r3, .L700 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L701: + .align 2 +.L700: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r0v, .-_Z9fx_add_r0v + .align 2 + .type _Z9fx_add_r1v, %function +_Z9fx_add_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L706 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L706 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L706+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L706 + str r2, [r3, #124] + ldr r3, .L706 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L706 + ldr r3, [r3, #4] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L706 + ldr r2, [r3, #4] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L706 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L706 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L706 + str r2, [r3, #120] + ldr r3, .L706 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L706 + str r2, [r3, #60] + ldr r3, .L706 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L706 + ldr r2, [r3, #100] + ldr r3, .L706+8 + cmp r2, r3 + bne .L703 + ldr r3, .L706 + ldr r2, [r3, #468] + ldr r3, .L706 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L706 + strb r3, [r2, #108] +.L703: + ldr r3, .L706 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L706 + str r2, [r3, #72] + ldr r2, .L706 + ldr r3, .L706 + str r3, [r2, #104] + ldr r3, .L706 + ldr r2, [r3, #104] + ldr r3, .L706 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L707: + .align 2 +.L706: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r1v, .-_Z9fx_add_r1v + .align 2 + .type _Z9fx_add_r2v, %function +_Z9fx_add_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L712 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L712 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L712+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L712 + str r2, [r3, #124] + ldr r3, .L712 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L712 + ldr r3, [r3, #8] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L712 + ldr r2, [r3, #8] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L712 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L712 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L712 + str r2, [r3, #120] + ldr r3, .L712 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L712 + str r2, [r3, #60] + ldr r3, .L712 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L712 + ldr r2, [r3, #100] + ldr r3, .L712+8 + cmp r2, r3 + bne .L709 + ldr r3, .L712 + ldr r2, [r3, #468] + ldr r3, .L712 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L712 + strb r3, [r2, #108] +.L709: + ldr r3, .L712 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L712 + str r2, [r3, #72] + ldr r2, .L712 + ldr r3, .L712 + str r3, [r2, #104] + ldr r3, .L712 + ldr r2, [r3, #104] + ldr r3, .L712 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L713: + .align 2 +.L712: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r2v, .-_Z9fx_add_r2v + .align 2 + .type _Z9fx_add_r3v, %function +_Z9fx_add_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L718 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L718 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L718+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L718 + str r2, [r3, #124] + ldr r3, .L718 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L718 + ldr r3, [r3, #12] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L718 + ldr r2, [r3, #12] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L718 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L718 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L718 + str r2, [r3, #120] + ldr r3, .L718 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L718 + str r2, [r3, #60] + ldr r3, .L718 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L718 + ldr r2, [r3, #100] + ldr r3, .L718+8 + cmp r2, r3 + bne .L715 + ldr r3, .L718 + ldr r2, [r3, #468] + ldr r3, .L718 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L718 + strb r3, [r2, #108] +.L715: + ldr r3, .L718 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L718 + str r2, [r3, #72] + ldr r2, .L718 + ldr r3, .L718 + str r3, [r2, #104] + ldr r3, .L718 + ldr r2, [r3, #104] + ldr r3, .L718 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L719: + .align 2 +.L718: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r3v, .-_Z9fx_add_r3v + .align 2 + .type _Z9fx_add_r4v, %function +_Z9fx_add_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L724 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L724 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L724+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L724 + str r2, [r3, #124] + ldr r3, .L724 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L724 + ldr r3, [r3, #16] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L724 + ldr r2, [r3, #16] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L724 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L724 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L724 + str r2, [r3, #120] + ldr r3, .L724 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L724 + str r2, [r3, #60] + ldr r3, .L724 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L724 + ldr r2, [r3, #100] + ldr r3, .L724+8 + cmp r2, r3 + bne .L721 + ldr r3, .L724 + ldr r2, [r3, #468] + ldr r3, .L724 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L724 + strb r3, [r2, #108] +.L721: + ldr r3, .L724 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L724 + str r2, [r3, #72] + ldr r2, .L724 + ldr r3, .L724 + str r3, [r2, #104] + ldr r3, .L724 + ldr r2, [r3, #104] + ldr r3, .L724 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L725: + .align 2 +.L724: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r4v, .-_Z9fx_add_r4v + .align 2 + .type _Z9fx_add_r5v, %function +_Z9fx_add_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L730 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L730 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L730+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L730 + str r2, [r3, #124] + ldr r3, .L730 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L730 + ldr r3, [r3, #20] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L730 + ldr r2, [r3, #20] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L730 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L730 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L730 + str r2, [r3, #120] + ldr r3, .L730 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L730 + str r2, [r3, #60] + ldr r3, .L730 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L730 + ldr r2, [r3, #100] + ldr r3, .L730+8 + cmp r2, r3 + bne .L727 + ldr r3, .L730 + ldr r2, [r3, #468] + ldr r3, .L730 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L730 + strb r3, [r2, #108] +.L727: + ldr r3, .L730 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L730 + str r2, [r3, #72] + ldr r2, .L730 + ldr r3, .L730 + str r3, [r2, #104] + ldr r3, .L730 + ldr r2, [r3, #104] + ldr r3, .L730 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L731: + .align 2 +.L730: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r5v, .-_Z9fx_add_r5v + .align 2 + .type _Z9fx_add_r6v, %function +_Z9fx_add_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L736 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L736 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L736+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L736 + str r2, [r3, #124] + ldr r3, .L736 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L736 + ldr r3, [r3, #24] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L736 + ldr r2, [r3, #24] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L736 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L736 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L736 + str r2, [r3, #120] + ldr r3, .L736 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L736 + str r2, [r3, #60] + ldr r3, .L736 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L736 + ldr r2, [r3, #100] + ldr r3, .L736+8 + cmp r2, r3 + bne .L733 + ldr r3, .L736 + ldr r2, [r3, #468] + ldr r3, .L736 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L736 + strb r3, [r2, #108] +.L733: + ldr r3, .L736 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L736 + str r2, [r3, #72] + ldr r2, .L736 + ldr r3, .L736 + str r3, [r2, #104] + ldr r3, .L736 + ldr r2, [r3, #104] + ldr r3, .L736 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L737: + .align 2 +.L736: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r6v, .-_Z9fx_add_r6v + .align 2 + .type _Z9fx_add_r7v, %function +_Z9fx_add_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L742 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L742 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L742+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L742 + str r2, [r3, #124] + ldr r3, .L742 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L742 + ldr r3, [r3, #28] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L742 + ldr r2, [r3, #28] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L742 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L742 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L742 + str r2, [r3, #120] + ldr r3, .L742 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L742 + str r2, [r3, #60] + ldr r3, .L742 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L742 + ldr r2, [r3, #100] + ldr r3, .L742+8 + cmp r2, r3 + bne .L739 + ldr r3, .L742 + ldr r2, [r3, #468] + ldr r3, .L742 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L742 + strb r3, [r2, #108] +.L739: + ldr r3, .L742 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L742 + str r2, [r3, #72] + ldr r2, .L742 + ldr r3, .L742 + str r3, [r2, #104] + ldr r3, .L742 + ldr r2, [r3, #104] + ldr r3, .L742 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L743: + .align 2 +.L742: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r7v, .-_Z9fx_add_r7v + .align 2 + .type _Z9fx_add_r8v, %function +_Z9fx_add_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L748 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L748 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L748+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L748 + str r2, [r3, #124] + ldr r3, .L748 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L748 + ldr r3, [r3, #32] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L748 + ldr r2, [r3, #32] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L748 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L748 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L748 + str r2, [r3, #120] + ldr r3, .L748 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L748 + str r2, [r3, #60] + ldr r3, .L748 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L748 + ldr r2, [r3, #100] + ldr r3, .L748+8 + cmp r2, r3 + bne .L745 + ldr r3, .L748 + ldr r2, [r3, #468] + ldr r3, .L748 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L748 + strb r3, [r2, #108] +.L745: + ldr r3, .L748 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L748 + str r2, [r3, #72] + ldr r2, .L748 + ldr r3, .L748 + str r3, [r2, #104] + ldr r3, .L748 + ldr r2, [r3, #104] + ldr r3, .L748 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L749: + .align 2 +.L748: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r8v, .-_Z9fx_add_r8v + .align 2 + .type _Z9fx_add_r9v, %function +_Z9fx_add_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L754 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L754 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L754+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L754 + str r2, [r3, #124] + ldr r3, .L754 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L754 + ldr r3, [r3, #36] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L754 + ldr r2, [r3, #36] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L754 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L754 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L754 + str r2, [r3, #120] + ldr r3, .L754 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L754 + str r2, [r3, #60] + ldr r3, .L754 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L754 + ldr r2, [r3, #100] + ldr r3, .L754+8 + cmp r2, r3 + bne .L751 + ldr r3, .L754 + ldr r2, [r3, #468] + ldr r3, .L754 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L754 + strb r3, [r2, #108] +.L751: + ldr r3, .L754 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L754 + str r2, [r3, #72] + ldr r2, .L754 + ldr r3, .L754 + str r3, [r2, #104] + ldr r3, .L754 + ldr r2, [r3, #104] + ldr r3, .L754 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L755: + .align 2 +.L754: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_r9v, .-_Z9fx_add_r9v + .align 2 + .type _Z10fx_add_r10v, %function +_Z10fx_add_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L760 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L760 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L760+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L760 + str r2, [r3, #124] + ldr r3, .L760 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L760 + ldr r3, [r3, #40] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L760 + ldr r2, [r3, #40] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L760 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L760 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L760 + str r2, [r3, #120] + ldr r3, .L760 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L760 + str r2, [r3, #60] + ldr r3, .L760 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L760 + ldr r2, [r3, #100] + ldr r3, .L760+8 + cmp r2, r3 + bne .L757 + ldr r3, .L760 + ldr r2, [r3, #468] + ldr r3, .L760 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L760 + strb r3, [r2, #108] +.L757: + ldr r3, .L760 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L760 + str r2, [r3, #72] + ldr r2, .L760 + ldr r3, .L760 + str r3, [r2, #104] + ldr r3, .L760 + ldr r2, [r3, #104] + ldr r3, .L760 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L761: + .align 2 +.L760: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_r10v, .-_Z10fx_add_r10v + .align 2 + .type _Z10fx_add_r11v, %function +_Z10fx_add_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L766 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L766 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L766+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L766 + str r2, [r3, #124] + ldr r3, .L766 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L766 + ldr r3, [r3, #44] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L766 + ldr r2, [r3, #44] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L766 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L766 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L766 + str r2, [r3, #120] + ldr r3, .L766 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L766 + str r2, [r3, #60] + ldr r3, .L766 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L766 + ldr r2, [r3, #100] + ldr r3, .L766+8 + cmp r2, r3 + bne .L763 + ldr r3, .L766 + ldr r2, [r3, #468] + ldr r3, .L766 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L766 + strb r3, [r2, #108] +.L763: + ldr r3, .L766 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L766 + str r2, [r3, #72] + ldr r2, .L766 + ldr r3, .L766 + str r3, [r2, #104] + ldr r3, .L766 + ldr r2, [r3, #104] + ldr r3, .L766 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L767: + .align 2 +.L766: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_r11v, .-_Z10fx_add_r11v + .align 2 + .type _Z10fx_add_r12v, %function +_Z10fx_add_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L772 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L772 + ldr r3, [r3, #48] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L772+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L772 + str r2, [r3, #124] + ldr r3, .L772 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L772 + ldr r3, [r3, #48] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L772 + ldr r2, [r3, #48] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L772 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L772 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L772 + str r2, [r3, #120] + ldr r3, .L772 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L772 + str r2, [r3, #60] + ldr r3, .L772 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L772 + ldr r2, [r3, #100] + ldr r3, .L772+8 + cmp r2, r3 + bne .L769 + ldr r3, .L772 + ldr r2, [r3, #468] + ldr r3, .L772 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L772 + strb r3, [r2, #108] +.L769: + ldr r3, .L772 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L772 + str r2, [r3, #72] + ldr r2, .L772 + ldr r3, .L772 + str r3, [r2, #104] + ldr r3, .L772 + ldr r2, [r3, #104] + ldr r3, .L772 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L773: + .align 2 +.L772: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_r12v, .-_Z10fx_add_r12v + .align 2 + .type _Z10fx_add_r13v, %function +_Z10fx_add_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L778 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L778 + ldr r3, [r3, #52] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L778+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L778 + str r2, [r3, #124] + ldr r3, .L778 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L778 + ldr r3, [r3, #52] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L778 + ldr r2, [r3, #52] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L778 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L778 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L778 + str r2, [r3, #120] + ldr r3, .L778 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L778 + str r2, [r3, #60] + ldr r3, .L778 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L778 + ldr r2, [r3, #100] + ldr r3, .L778+8 + cmp r2, r3 + bne .L775 + ldr r3, .L778 + ldr r2, [r3, #468] + ldr r3, .L778 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L778 + strb r3, [r2, #108] +.L775: + ldr r3, .L778 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L778 + str r2, [r3, #72] + ldr r2, .L778 + ldr r3, .L778 + str r3, [r2, #104] + ldr r3, .L778 + ldr r2, [r3, #104] + ldr r3, .L778 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L779: + .align 2 +.L778: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_r13v, .-_Z10fx_add_r13v + .align 2 + .type _Z10fx_add_r14v, %function +_Z10fx_add_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L784 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L784 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L784+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L784 + str r2, [r3, #124] + ldr r3, .L784 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L784 + ldr r3, [r3, #56] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L784 + ldr r2, [r3, #56] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L784 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L784 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L784 + str r2, [r3, #120] + ldr r3, .L784 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L784 + str r2, [r3, #60] + ldr r3, .L784 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L784 + ldr r2, [r3, #100] + ldr r3, .L784+8 + cmp r2, r3 + bne .L781 + ldr r3, .L784 + ldr r2, [r3, #468] + ldr r3, .L784 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L784 + strb r3, [r2, #108] +.L781: + ldr r3, .L784 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L784 + str r2, [r3, #72] + ldr r2, .L784 + ldr r3, .L784 + str r3, [r2, #104] + ldr r3, .L784 + ldr r2, [r3, #104] + ldr r3, .L784 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L785: + .align 2 +.L784: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_r14v, .-_Z10fx_add_r14v + .align 2 + .type _Z10fx_add_r15v, %function +_Z10fx_add_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L790 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L790 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L790+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L790 + str r2, [r3, #124] + ldr r3, .L790 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L790 + ldr r3, [r3, #60] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L790 + ldr r2, [r3, #60] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L790 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L790 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L790 + str r2, [r3, #120] + ldr r3, .L790 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L790 + str r2, [r3, #60] + ldr r3, .L790 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L790 + ldr r2, [r3, #100] + ldr r3, .L790+8 + cmp r2, r3 + bne .L787 + ldr r3, .L790 + ldr r2, [r3, #468] + ldr r3, .L790 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L790 + strb r3, [r2, #108] +.L787: + ldr r3, .L790 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L790 + str r2, [r3, #72] + ldr r2, .L790 + ldr r3, .L790 + str r3, [r2, #104] + ldr r3, .L790 + ldr r2, [r3, #104] + ldr r3, .L790 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L791: + .align 2 +.L790: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_r15v, .-_Z10fx_add_r15v + .align 2 + .type _Z9fx_adc_r0v, %function +_Z9fx_adc_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L796 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L796 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L796 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L796+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L796 + str r2, [r3, #124] + ldr r3, .L796 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L796 + ldr r3, [r3, #0] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L796 + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L796 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L796 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L796 + str r2, [r3, #120] + ldr r3, .L796 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L796 + str r2, [r3, #60] + ldr r3, .L796 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L796 + ldr r2, [r3, #100] + ldr r3, .L796+8 + cmp r2, r3 + bne .L793 + ldr r3, .L796 + ldr r2, [r3, #468] + ldr r3, .L796 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L796 + strb r3, [r2, #108] +.L793: + ldr r3, .L796 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L796 + str r2, [r3, #72] + ldr r2, .L796 + ldr r3, .L796 + str r3, [r2, #104] + ldr r3, .L796 + ldr r2, [r3, #104] + ldr r3, .L796 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L797: + .align 2 +.L796: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r0v, .-_Z9fx_adc_r0v + .align 2 + .type _Z9fx_adc_r1v, %function +_Z9fx_adc_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L802 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L802 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L802 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L802+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L802 + str r2, [r3, #124] + ldr r3, .L802 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L802 + ldr r3, [r3, #4] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L802 + ldr r2, [r3, #4] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L802 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L802 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L802 + str r2, [r3, #120] + ldr r3, .L802 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L802 + str r2, [r3, #60] + ldr r3, .L802 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L802 + ldr r2, [r3, #100] + ldr r3, .L802+8 + cmp r2, r3 + bne .L799 + ldr r3, .L802 + ldr r2, [r3, #468] + ldr r3, .L802 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L802 + strb r3, [r2, #108] +.L799: + ldr r3, .L802 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L802 + str r2, [r3, #72] + ldr r2, .L802 + ldr r3, .L802 + str r3, [r2, #104] + ldr r3, .L802 + ldr r2, [r3, #104] + ldr r3, .L802 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L803: + .align 2 +.L802: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r1v, .-_Z9fx_adc_r1v + .align 2 + .type _Z9fx_adc_r2v, %function +_Z9fx_adc_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L808 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L808 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L808 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L808+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L808 + str r2, [r3, #124] + ldr r3, .L808 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L808 + ldr r3, [r3, #8] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L808 + ldr r2, [r3, #8] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L808 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L808 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L808 + str r2, [r3, #120] + ldr r3, .L808 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L808 + str r2, [r3, #60] + ldr r3, .L808 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L808 + ldr r2, [r3, #100] + ldr r3, .L808+8 + cmp r2, r3 + bne .L805 + ldr r3, .L808 + ldr r2, [r3, #468] + ldr r3, .L808 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L808 + strb r3, [r2, #108] +.L805: + ldr r3, .L808 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L808 + str r2, [r3, #72] + ldr r2, .L808 + ldr r3, .L808 + str r3, [r2, #104] + ldr r3, .L808 + ldr r2, [r3, #104] + ldr r3, .L808 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L809: + .align 2 +.L808: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r2v, .-_Z9fx_adc_r2v + .align 2 + .type _Z9fx_adc_r3v, %function +_Z9fx_adc_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L814 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L814 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L814 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L814+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L814 + str r2, [r3, #124] + ldr r3, .L814 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L814 + ldr r3, [r3, #12] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L814 + ldr r2, [r3, #12] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L814 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L814 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L814 + str r2, [r3, #120] + ldr r3, .L814 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L814 + str r2, [r3, #60] + ldr r3, .L814 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L814 + ldr r2, [r3, #100] + ldr r3, .L814+8 + cmp r2, r3 + bne .L811 + ldr r3, .L814 + ldr r2, [r3, #468] + ldr r3, .L814 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L814 + strb r3, [r2, #108] +.L811: + ldr r3, .L814 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L814 + str r2, [r3, #72] + ldr r2, .L814 + ldr r3, .L814 + str r3, [r2, #104] + ldr r3, .L814 + ldr r2, [r3, #104] + ldr r3, .L814 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L815: + .align 2 +.L814: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r3v, .-_Z9fx_adc_r3v + .align 2 + .type _Z9fx_adc_r4v, %function +_Z9fx_adc_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L820 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L820 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L820 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L820+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L820 + str r2, [r3, #124] + ldr r3, .L820 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L820 + ldr r3, [r3, #16] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L820 + ldr r2, [r3, #16] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L820 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L820 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L820 + str r2, [r3, #120] + ldr r3, .L820 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L820 + str r2, [r3, #60] + ldr r3, .L820 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L820 + ldr r2, [r3, #100] + ldr r3, .L820+8 + cmp r2, r3 + bne .L817 + ldr r3, .L820 + ldr r2, [r3, #468] + ldr r3, .L820 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L820 + strb r3, [r2, #108] +.L817: + ldr r3, .L820 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L820 + str r2, [r3, #72] + ldr r2, .L820 + ldr r3, .L820 + str r3, [r2, #104] + ldr r3, .L820 + ldr r2, [r3, #104] + ldr r3, .L820 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L821: + .align 2 +.L820: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r4v, .-_Z9fx_adc_r4v + .align 2 + .type _Z9fx_adc_r5v, %function +_Z9fx_adc_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L826 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L826 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L826 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L826+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L826 + str r2, [r3, #124] + ldr r3, .L826 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L826 + ldr r3, [r3, #20] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L826 + ldr r2, [r3, #20] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L826 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L826 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L826 + str r2, [r3, #120] + ldr r3, .L826 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L826 + str r2, [r3, #60] + ldr r3, .L826 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L826 + ldr r2, [r3, #100] + ldr r3, .L826+8 + cmp r2, r3 + bne .L823 + ldr r3, .L826 + ldr r2, [r3, #468] + ldr r3, .L826 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L826 + strb r3, [r2, #108] +.L823: + ldr r3, .L826 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L826 + str r2, [r3, #72] + ldr r2, .L826 + ldr r3, .L826 + str r3, [r2, #104] + ldr r3, .L826 + ldr r2, [r3, #104] + ldr r3, .L826 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L827: + .align 2 +.L826: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r5v, .-_Z9fx_adc_r5v + .align 2 + .type _Z9fx_adc_r6v, %function +_Z9fx_adc_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L832 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L832 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L832 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L832+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L832 + str r2, [r3, #124] + ldr r3, .L832 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L832 + ldr r3, [r3, #24] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L832 + ldr r2, [r3, #24] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L832 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L832 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L832 + str r2, [r3, #120] + ldr r3, .L832 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L832 + str r2, [r3, #60] + ldr r3, .L832 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L832 + ldr r2, [r3, #100] + ldr r3, .L832+8 + cmp r2, r3 + bne .L829 + ldr r3, .L832 + ldr r2, [r3, #468] + ldr r3, .L832 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L832 + strb r3, [r2, #108] +.L829: + ldr r3, .L832 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L832 + str r2, [r3, #72] + ldr r2, .L832 + ldr r3, .L832 + str r3, [r2, #104] + ldr r3, .L832 + ldr r2, [r3, #104] + ldr r3, .L832 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L833: + .align 2 +.L832: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r6v, .-_Z9fx_adc_r6v + .align 2 + .type _Z9fx_adc_r7v, %function +_Z9fx_adc_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L838 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L838 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L838 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L838+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L838 + str r2, [r3, #124] + ldr r3, .L838 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L838 + ldr r3, [r3, #28] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L838 + ldr r2, [r3, #28] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L838 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L838 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L838 + str r2, [r3, #120] + ldr r3, .L838 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L838 + str r2, [r3, #60] + ldr r3, .L838 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L838 + ldr r2, [r3, #100] + ldr r3, .L838+8 + cmp r2, r3 + bne .L835 + ldr r3, .L838 + ldr r2, [r3, #468] + ldr r3, .L838 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L838 + strb r3, [r2, #108] +.L835: + ldr r3, .L838 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L838 + str r2, [r3, #72] + ldr r2, .L838 + ldr r3, .L838 + str r3, [r2, #104] + ldr r3, .L838 + ldr r2, [r3, #104] + ldr r3, .L838 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L839: + .align 2 +.L838: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r7v, .-_Z9fx_adc_r7v + .align 2 + .type _Z9fx_adc_r8v, %function +_Z9fx_adc_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L844 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L844 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L844 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L844+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L844 + str r2, [r3, #124] + ldr r3, .L844 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L844 + ldr r3, [r3, #32] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L844 + ldr r2, [r3, #32] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L844 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L844 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L844 + str r2, [r3, #120] + ldr r3, .L844 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L844 + str r2, [r3, #60] + ldr r3, .L844 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L844 + ldr r2, [r3, #100] + ldr r3, .L844+8 + cmp r2, r3 + bne .L841 + ldr r3, .L844 + ldr r2, [r3, #468] + ldr r3, .L844 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L844 + strb r3, [r2, #108] +.L841: + ldr r3, .L844 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L844 + str r2, [r3, #72] + ldr r2, .L844 + ldr r3, .L844 + str r3, [r2, #104] + ldr r3, .L844 + ldr r2, [r3, #104] + ldr r3, .L844 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L845: + .align 2 +.L844: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r8v, .-_Z9fx_adc_r8v + .align 2 + .type _Z9fx_adc_r9v, %function +_Z9fx_adc_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L850 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L850 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L850 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L850+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L850 + str r2, [r3, #124] + ldr r3, .L850 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L850 + ldr r3, [r3, #36] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L850 + ldr r2, [r3, #36] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L850 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L850 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L850 + str r2, [r3, #120] + ldr r3, .L850 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L850 + str r2, [r3, #60] + ldr r3, .L850 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L850 + ldr r2, [r3, #100] + ldr r3, .L850+8 + cmp r2, r3 + bne .L847 + ldr r3, .L850 + ldr r2, [r3, #468] + ldr r3, .L850 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L850 + strb r3, [r2, #108] +.L847: + ldr r3, .L850 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L850 + str r2, [r3, #72] + ldr r2, .L850 + ldr r3, .L850 + str r3, [r2, #104] + ldr r3, .L850 + ldr r2, [r3, #104] + ldr r3, .L850 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L851: + .align 2 +.L850: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_r9v, .-_Z9fx_adc_r9v + .align 2 + .type _Z10fx_adc_r10v, %function +_Z10fx_adc_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L856 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L856 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L856 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L856+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L856 + str r2, [r3, #124] + ldr r3, .L856 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L856 + ldr r3, [r3, #40] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L856 + ldr r2, [r3, #40] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L856 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L856 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L856 + str r2, [r3, #120] + ldr r3, .L856 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L856 + str r2, [r3, #60] + ldr r3, .L856 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L856 + ldr r2, [r3, #100] + ldr r3, .L856+8 + cmp r2, r3 + bne .L853 + ldr r3, .L856 + ldr r2, [r3, #468] + ldr r3, .L856 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L856 + strb r3, [r2, #108] +.L853: + ldr r3, .L856 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L856 + str r2, [r3, #72] + ldr r2, .L856 + ldr r3, .L856 + str r3, [r2, #104] + ldr r3, .L856 + ldr r2, [r3, #104] + ldr r3, .L856 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L857: + .align 2 +.L856: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_r10v, .-_Z10fx_adc_r10v + .align 2 + .type _Z10fx_adc_r11v, %function +_Z10fx_adc_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L862 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L862 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L862 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L862+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L862 + str r2, [r3, #124] + ldr r3, .L862 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L862 + ldr r3, [r3, #44] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L862 + ldr r2, [r3, #44] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L862 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L862 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L862 + str r2, [r3, #120] + ldr r3, .L862 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L862 + str r2, [r3, #60] + ldr r3, .L862 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L862 + ldr r2, [r3, #100] + ldr r3, .L862+8 + cmp r2, r3 + bne .L859 + ldr r3, .L862 + ldr r2, [r3, #468] + ldr r3, .L862 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L862 + strb r3, [r2, #108] +.L859: + ldr r3, .L862 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L862 + str r2, [r3, #72] + ldr r2, .L862 + ldr r3, .L862 + str r3, [r2, #104] + ldr r3, .L862 + ldr r2, [r3, #104] + ldr r3, .L862 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L863: + .align 2 +.L862: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_r11v, .-_Z10fx_adc_r11v + .align 2 + .type _Z10fx_adc_r12v, %function +_Z10fx_adc_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L868 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L868 + ldr r3, [r3, #48] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L868 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L868+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L868 + str r2, [r3, #124] + ldr r3, .L868 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L868 + ldr r3, [r3, #48] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L868 + ldr r2, [r3, #48] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L868 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L868 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L868 + str r2, [r3, #120] + ldr r3, .L868 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L868 + str r2, [r3, #60] + ldr r3, .L868 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L868 + ldr r2, [r3, #100] + ldr r3, .L868+8 + cmp r2, r3 + bne .L865 + ldr r3, .L868 + ldr r2, [r3, #468] + ldr r3, .L868 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L868 + strb r3, [r2, #108] +.L865: + ldr r3, .L868 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L868 + str r2, [r3, #72] + ldr r2, .L868 + ldr r3, .L868 + str r3, [r2, #104] + ldr r3, .L868 + ldr r2, [r3, #104] + ldr r3, .L868 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L869: + .align 2 +.L868: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_r12v, .-_Z10fx_adc_r12v + .align 2 + .type _Z10fx_adc_r13v, %function +_Z10fx_adc_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L874 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L874 + ldr r3, [r3, #52] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L874 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L874+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L874 + str r2, [r3, #124] + ldr r3, .L874 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L874 + ldr r3, [r3, #52] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L874 + ldr r2, [r3, #52] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L874 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L874 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L874 + str r2, [r3, #120] + ldr r3, .L874 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L874 + str r2, [r3, #60] + ldr r3, .L874 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L874 + ldr r2, [r3, #100] + ldr r3, .L874+8 + cmp r2, r3 + bne .L871 + ldr r3, .L874 + ldr r2, [r3, #468] + ldr r3, .L874 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L874 + strb r3, [r2, #108] +.L871: + ldr r3, .L874 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L874 + str r2, [r3, #72] + ldr r2, .L874 + ldr r3, .L874 + str r3, [r2, #104] + ldr r3, .L874 + ldr r2, [r3, #104] + ldr r3, .L874 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L875: + .align 2 +.L874: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_r13v, .-_Z10fx_adc_r13v + .align 2 + .type _Z10fx_adc_r14v, %function +_Z10fx_adc_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L880 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L880 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L880 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L880+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L880 + str r2, [r3, #124] + ldr r3, .L880 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L880 + ldr r3, [r3, #56] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L880 + ldr r2, [r3, #56] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L880 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L880 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L880 + str r2, [r3, #120] + ldr r3, .L880 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L880 + str r2, [r3, #60] + ldr r3, .L880 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L880 + ldr r2, [r3, #100] + ldr r3, .L880+8 + cmp r2, r3 + bne .L877 + ldr r3, .L880 + ldr r2, [r3, #468] + ldr r3, .L880 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L880 + strb r3, [r2, #108] +.L877: + ldr r3, .L880 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L880 + str r2, [r3, #72] + ldr r2, .L880 + ldr r3, .L880 + str r3, [r2, #104] + ldr r3, .L880 + ldr r2, [r3, #104] + ldr r3, .L880 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L881: + .align 2 +.L880: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_r14v, .-_Z10fx_adc_r14v + .align 2 + .type _Z10fx_adc_r15v, %function +_Z10fx_adc_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L886 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L886 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L886 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L886+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L886 + str r2, [r3, #124] + ldr r3, .L886 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L886 + ldr r3, [r3, #60] + eor r3, r2, r3 + mvn r1, r3 + ldr r3, .L886 + ldr r2, [r3, #60] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L886 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L886 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L886 + str r2, [r3, #120] + ldr r3, .L886 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L886 + str r2, [r3, #60] + ldr r3, .L886 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L886 + ldr r2, [r3, #100] + ldr r3, .L886+8 + cmp r2, r3 + bne .L883 + ldr r3, .L886 + ldr r2, [r3, #468] + ldr r3, .L886 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L886 + strb r3, [r2, #108] +.L883: + ldr r3, .L886 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L886 + str r2, [r3, #72] + ldr r2, .L886 + ldr r3, .L886 + str r3, [r2, #104] + ldr r3, .L886 + ldr r2, [r3, #104] + ldr r3, .L886 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L887: + .align 2 +.L886: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_r15v, .-_Z10fx_adc_r15v + .align 2 + .type _Z9fx_add_i0v, %function +_Z9fx_add_i0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L892 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L892+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L892 + str r2, [r3, #124] + ldr r3, .L892 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mvn r2, r3 + ldr r3, [fp, #-16] + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L892 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L892 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L892 + str r2, [r3, #120] + ldr r3, .L892 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L892 + str r2, [r3, #60] + ldr r3, .L892 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L892 + ldr r2, [r3, #100] + ldr r3, .L892+8 + cmp r2, r3 + bne .L889 + ldr r3, .L892 + ldr r2, [r3, #468] + ldr r3, .L892 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L892 + strb r3, [r2, #108] +.L889: + ldr r3, .L892 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L892 + str r2, [r3, #72] + ldr r2, .L892 + ldr r3, .L892 + str r3, [r2, #104] + ldr r3, .L892 + ldr r2, [r3, #104] + ldr r3, .L892 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L893: + .align 2 +.L892: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i0v, .-_Z9fx_add_i0v + .align 2 + .type _Z9fx_add_i1v, %function +_Z9fx_add_i1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L898 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L898+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L898 + str r2, [r3, #124] + ldr r3, .L898 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #1 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #1 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L898 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L898 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L898 + str r2, [r3, #120] + ldr r3, .L898 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L898 + str r2, [r3, #60] + ldr r3, .L898 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L898 + ldr r2, [r3, #100] + ldr r3, .L898+8 + cmp r2, r3 + bne .L895 + ldr r3, .L898 + ldr r2, [r3, #468] + ldr r3, .L898 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L898 + strb r3, [r2, #108] +.L895: + ldr r3, .L898 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L898 + str r2, [r3, #72] + ldr r2, .L898 + ldr r3, .L898 + str r3, [r2, #104] + ldr r3, .L898 + ldr r2, [r3, #104] + ldr r3, .L898 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L899: + .align 2 +.L898: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i1v, .-_Z9fx_add_i1v + .align 2 + .type _Z9fx_add_i2v, %function +_Z9fx_add_i2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L904 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #2 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L904+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L904 + str r2, [r3, #124] + ldr r3, .L904 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #2 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #2 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L904 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L904 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L904 + str r2, [r3, #120] + ldr r3, .L904 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L904 + str r2, [r3, #60] + ldr r3, .L904 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L904 + ldr r2, [r3, #100] + ldr r3, .L904+8 + cmp r2, r3 + bne .L901 + ldr r3, .L904 + ldr r2, [r3, #468] + ldr r3, .L904 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L904 + strb r3, [r2, #108] +.L901: + ldr r3, .L904 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L904 + str r2, [r3, #72] + ldr r2, .L904 + ldr r3, .L904 + str r3, [r2, #104] + ldr r3, .L904 + ldr r2, [r3, #104] + ldr r3, .L904 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L905: + .align 2 +.L904: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i2v, .-_Z9fx_add_i2v + .align 2 + .type _Z9fx_add_i3v, %function +_Z9fx_add_i3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L910 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L910+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L910 + str r2, [r3, #124] + ldr r3, .L910 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #3 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #3 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L910 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L910 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L910 + str r2, [r3, #120] + ldr r3, .L910 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L910 + str r2, [r3, #60] + ldr r3, .L910 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L910 + ldr r2, [r3, #100] + ldr r3, .L910+8 + cmp r2, r3 + bne .L907 + ldr r3, .L910 + ldr r2, [r3, #468] + ldr r3, .L910 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L910 + strb r3, [r2, #108] +.L907: + ldr r3, .L910 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L910 + str r2, [r3, #72] + ldr r2, .L910 + ldr r3, .L910 + str r3, [r2, #104] + ldr r3, .L910 + ldr r2, [r3, #104] + ldr r3, .L910 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L911: + .align 2 +.L910: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i3v, .-_Z9fx_add_i3v + .align 2 + .type _Z9fx_add_i4v, %function +_Z9fx_add_i4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L916 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #4 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L916+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L916 + str r2, [r3, #124] + ldr r3, .L916 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #4 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #4 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L916 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L916 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L916 + str r2, [r3, #120] + ldr r3, .L916 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L916 + str r2, [r3, #60] + ldr r3, .L916 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L916 + ldr r2, [r3, #100] + ldr r3, .L916+8 + cmp r2, r3 + bne .L913 + ldr r3, .L916 + ldr r2, [r3, #468] + ldr r3, .L916 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L916 + strb r3, [r2, #108] +.L913: + ldr r3, .L916 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L916 + str r2, [r3, #72] + ldr r2, .L916 + ldr r3, .L916 + str r3, [r2, #104] + ldr r3, .L916 + ldr r2, [r3, #104] + ldr r3, .L916 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L917: + .align 2 +.L916: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i4v, .-_Z9fx_add_i4v + .align 2 + .type _Z9fx_add_i5v, %function +_Z9fx_add_i5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L922 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #5 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L922+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L922 + str r2, [r3, #124] + ldr r3, .L922 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #5 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #5 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L922 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L922 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L922 + str r2, [r3, #120] + ldr r3, .L922 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L922 + str r2, [r3, #60] + ldr r3, .L922 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L922 + ldr r2, [r3, #100] + ldr r3, .L922+8 + cmp r2, r3 + bne .L919 + ldr r3, .L922 + ldr r2, [r3, #468] + ldr r3, .L922 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L922 + strb r3, [r2, #108] +.L919: + ldr r3, .L922 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L922 + str r2, [r3, #72] + ldr r2, .L922 + ldr r3, .L922 + str r3, [r2, #104] + ldr r3, .L922 + ldr r2, [r3, #104] + ldr r3, .L922 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L923: + .align 2 +.L922: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i5v, .-_Z9fx_add_i5v + .align 2 + .type _Z9fx_add_i6v, %function +_Z9fx_add_i6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L928 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #6 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L928+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L928 + str r2, [r3, #124] + ldr r3, .L928 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #6 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #6 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L928 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L928 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L928 + str r2, [r3, #120] + ldr r3, .L928 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L928 + str r2, [r3, #60] + ldr r3, .L928 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L928 + ldr r2, [r3, #100] + ldr r3, .L928+8 + cmp r2, r3 + bne .L925 + ldr r3, .L928 + ldr r2, [r3, #468] + ldr r3, .L928 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L928 + strb r3, [r2, #108] +.L925: + ldr r3, .L928 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L928 + str r2, [r3, #72] + ldr r2, .L928 + ldr r3, .L928 + str r3, [r2, #104] + ldr r3, .L928 + ldr r2, [r3, #104] + ldr r3, .L928 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L929: + .align 2 +.L928: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i6v, .-_Z9fx_add_i6v + .align 2 + .type _Z9fx_add_i7v, %function +_Z9fx_add_i7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L934 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #7 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L934+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L934 + str r2, [r3, #124] + ldr r3, .L934 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #7 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #7 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L934 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L934 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L934 + str r2, [r3, #120] + ldr r3, .L934 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L934 + str r2, [r3, #60] + ldr r3, .L934 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L934 + ldr r2, [r3, #100] + ldr r3, .L934+8 + cmp r2, r3 + bne .L931 + ldr r3, .L934 + ldr r2, [r3, #468] + ldr r3, .L934 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L934 + strb r3, [r2, #108] +.L931: + ldr r3, .L934 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L934 + str r2, [r3, #72] + ldr r2, .L934 + ldr r3, .L934 + str r3, [r2, #104] + ldr r3, .L934 + ldr r2, [r3, #104] + ldr r3, .L934 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L935: + .align 2 +.L934: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i7v, .-_Z9fx_add_i7v + .align 2 + .type _Z9fx_add_i8v, %function +_Z9fx_add_i8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L940 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #8 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L940+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L940 + str r2, [r3, #124] + ldr r3, .L940 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #8 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #8 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L940 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L940 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L940 + str r2, [r3, #120] + ldr r3, .L940 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L940 + str r2, [r3, #60] + ldr r3, .L940 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L940 + ldr r2, [r3, #100] + ldr r3, .L940+8 + cmp r2, r3 + bne .L937 + ldr r3, .L940 + ldr r2, [r3, #468] + ldr r3, .L940 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L940 + strb r3, [r2, #108] +.L937: + ldr r3, .L940 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L940 + str r2, [r3, #72] + ldr r2, .L940 + ldr r3, .L940 + str r3, [r2, #104] + ldr r3, .L940 + ldr r2, [r3, #104] + ldr r3, .L940 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L941: + .align 2 +.L940: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i8v, .-_Z9fx_add_i8v + .align 2 + .type _Z9fx_add_i9v, %function +_Z9fx_add_i9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L946 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #9 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L946+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L946 + str r2, [r3, #124] + ldr r3, .L946 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #9 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #9 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L946 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L946 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L946 + str r2, [r3, #120] + ldr r3, .L946 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L946 + str r2, [r3, #60] + ldr r3, .L946 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L946 + ldr r2, [r3, #100] + ldr r3, .L946+8 + cmp r2, r3 + bne .L943 + ldr r3, .L946 + ldr r2, [r3, #468] + ldr r3, .L946 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L946 + strb r3, [r2, #108] +.L943: + ldr r3, .L946 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L946 + str r2, [r3, #72] + ldr r2, .L946 + ldr r3, .L946 + str r3, [r2, #104] + ldr r3, .L946 + ldr r2, [r3, #104] + ldr r3, .L946 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L947: + .align 2 +.L946: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_add_i9v, .-_Z9fx_add_i9v + .align 2 + .type _Z10fx_add_i10v, %function +_Z10fx_add_i10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L952 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #10 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L952+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L952 + str r2, [r3, #124] + ldr r3, .L952 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #10 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #10 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L952 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L952 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L952 + str r2, [r3, #120] + ldr r3, .L952 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L952 + str r2, [r3, #60] + ldr r3, .L952 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L952 + ldr r2, [r3, #100] + ldr r3, .L952+8 + cmp r2, r3 + bne .L949 + ldr r3, .L952 + ldr r2, [r3, #468] + ldr r3, .L952 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L952 + strb r3, [r2, #108] +.L949: + ldr r3, .L952 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L952 + str r2, [r3, #72] + ldr r2, .L952 + ldr r3, .L952 + str r3, [r2, #104] + ldr r3, .L952 + ldr r2, [r3, #104] + ldr r3, .L952 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L953: + .align 2 +.L952: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_i10v, .-_Z10fx_add_i10v + .align 2 + .type _Z10fx_add_i11v, %function +_Z10fx_add_i11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L958 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #11 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L958+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L958 + str r2, [r3, #124] + ldr r3, .L958 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #11 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #11 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L958 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L958 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L958 + str r2, [r3, #120] + ldr r3, .L958 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L958 + str r2, [r3, #60] + ldr r3, .L958 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L958 + ldr r2, [r3, #100] + ldr r3, .L958+8 + cmp r2, r3 + bne .L955 + ldr r3, .L958 + ldr r2, [r3, #468] + ldr r3, .L958 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L958 + strb r3, [r2, #108] +.L955: + ldr r3, .L958 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L958 + str r2, [r3, #72] + ldr r2, .L958 + ldr r3, .L958 + str r3, [r2, #104] + ldr r3, .L958 + ldr r2, [r3, #104] + ldr r3, .L958 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L959: + .align 2 +.L958: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_i11v, .-_Z10fx_add_i11v + .align 2 + .type _Z10fx_add_i12v, %function +_Z10fx_add_i12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L964 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #12 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L964+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L964 + str r2, [r3, #124] + ldr r3, .L964 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #12 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #12 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L964 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L964 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L964 + str r2, [r3, #120] + ldr r3, .L964 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L964 + str r2, [r3, #60] + ldr r3, .L964 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L964 + ldr r2, [r3, #100] + ldr r3, .L964+8 + cmp r2, r3 + bne .L961 + ldr r3, .L964 + ldr r2, [r3, #468] + ldr r3, .L964 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L964 + strb r3, [r2, #108] +.L961: + ldr r3, .L964 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L964 + str r2, [r3, #72] + ldr r2, .L964 + ldr r3, .L964 + str r3, [r2, #104] + ldr r3, .L964 + ldr r2, [r3, #104] + ldr r3, .L964 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L965: + .align 2 +.L964: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_i12v, .-_Z10fx_add_i12v + .align 2 + .type _Z10fx_add_i13v, %function +_Z10fx_add_i13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L970 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #13 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L970+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L970 + str r2, [r3, #124] + ldr r3, .L970 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #13 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #13 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L970 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L970 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L970 + str r2, [r3, #120] + ldr r3, .L970 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L970 + str r2, [r3, #60] + ldr r3, .L970 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L970 + ldr r2, [r3, #100] + ldr r3, .L970+8 + cmp r2, r3 + bne .L967 + ldr r3, .L970 + ldr r2, [r3, #468] + ldr r3, .L970 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L970 + strb r3, [r2, #108] +.L967: + ldr r3, .L970 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L970 + str r2, [r3, #72] + ldr r2, .L970 + ldr r3, .L970 + str r3, [r2, #104] + ldr r3, .L970 + ldr r2, [r3, #104] + ldr r3, .L970 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L971: + .align 2 +.L970: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_i13v, .-_Z10fx_add_i13v + .align 2 + .type _Z10fx_add_i14v, %function +_Z10fx_add_i14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L976 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #14 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L976+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L976 + str r2, [r3, #124] + ldr r3, .L976 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #14 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #14 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L976 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L976 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L976 + str r2, [r3, #120] + ldr r3, .L976 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L976 + str r2, [r3, #60] + ldr r3, .L976 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L976 + ldr r2, [r3, #100] + ldr r3, .L976+8 + cmp r2, r3 + bne .L973 + ldr r3, .L976 + ldr r2, [r3, #468] + ldr r3, .L976 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L976 + strb r3, [r2, #108] +.L973: + ldr r3, .L976 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L976 + str r2, [r3, #72] + ldr r2, .L976 + ldr r3, .L976 + str r3, [r2, #104] + ldr r3, .L976 + ldr r2, [r3, #104] + ldr r3, .L976 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L977: + .align 2 +.L976: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_i14v, .-_Z10fx_add_i14v + .align 2 + .type _Z10fx_add_i15v, %function +_Z10fx_add_i15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L982 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #15 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L982+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L982 + str r2, [r3, #124] + ldr r3, .L982 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #15 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #15 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L982 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L982 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L982 + str r2, [r3, #120] + ldr r3, .L982 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L982 + str r2, [r3, #60] + ldr r3, .L982 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L982 + ldr r2, [r3, #100] + ldr r3, .L982+8 + cmp r2, r3 + bne .L979 + ldr r3, .L982 + ldr r2, [r3, #468] + ldr r3, .L982 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L982 + strb r3, [r2, #108] +.L979: + ldr r3, .L982 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L982 + str r2, [r3, #72] + ldr r2, .L982 + ldr r3, .L982 + str r3, [r2, #104] + ldr r3, .L982 + ldr r2, [r3, #104] + ldr r3, .L982 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L983: + .align 2 +.L982: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_add_i15v, .-_Z10fx_add_i15v + .align 2 + .type _Z9fx_adc_i0v, %function +_Z9fx_adc_i0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L988 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L988 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L988+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L988 + str r2, [r3, #124] + ldr r3, .L988 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mvn r2, r3 + ldr r3, [fp, #-16] + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L988 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L988 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L988 + str r2, [r3, #120] + ldr r3, .L988 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L988 + str r2, [r3, #60] + ldr r3, .L988 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L988 + ldr r2, [r3, #100] + ldr r3, .L988+8 + cmp r2, r3 + bne .L985 + ldr r3, .L988 + ldr r2, [r3, #468] + ldr r3, .L988 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L988 + strb r3, [r2, #108] +.L985: + ldr r3, .L988 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L988 + str r2, [r3, #72] + ldr r2, .L988 + ldr r3, .L988 + str r3, [r2, #104] + ldr r3, .L988 + ldr r2, [r3, #104] + ldr r3, .L988 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L989: + .align 2 +.L988: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i0v, .-_Z9fx_adc_i0v + .align 2 + .type _Z9fx_adc_i1v, %function +_Z9fx_adc_i1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L994 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #1 + ldr r3, .L994 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L994+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L994 + str r2, [r3, #124] + ldr r3, .L994 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #1 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #1 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L994 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L994 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L994 + str r2, [r3, #120] + ldr r3, .L994 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L994 + str r2, [r3, #60] + ldr r3, .L994 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L994 + ldr r2, [r3, #100] + ldr r3, .L994+8 + cmp r2, r3 + bne .L991 + ldr r3, .L994 + ldr r2, [r3, #468] + ldr r3, .L994 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L994 + strb r3, [r2, #108] +.L991: + ldr r3, .L994 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L994 + str r2, [r3, #72] + ldr r2, .L994 + ldr r3, .L994 + str r3, [r2, #104] + ldr r3, .L994 + ldr r2, [r3, #104] + ldr r3, .L994 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L995: + .align 2 +.L994: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i1v, .-_Z9fx_adc_i1v + .align 2 + .type _Z9fx_adc_i2v, %function +_Z9fx_adc_i2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1000 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #2 + ldr r3, .L1000 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1000+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1000 + str r2, [r3, #124] + ldr r3, .L1000 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #2 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #2 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1000 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1000 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1000 + str r2, [r3, #120] + ldr r3, .L1000 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1000 + str r2, [r3, #60] + ldr r3, .L1000 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1000 + ldr r2, [r3, #100] + ldr r3, .L1000+8 + cmp r2, r3 + bne .L997 + ldr r3, .L1000 + ldr r2, [r3, #468] + ldr r3, .L1000 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1000 + strb r3, [r2, #108] +.L997: + ldr r3, .L1000 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1000 + str r2, [r3, #72] + ldr r2, .L1000 + ldr r3, .L1000 + str r3, [r2, #104] + ldr r3, .L1000 + ldr r2, [r3, #104] + ldr r3, .L1000 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1001: + .align 2 +.L1000: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i2v, .-_Z9fx_adc_i2v + .align 2 + .type _Z9fx_adc_i3v, %function +_Z9fx_adc_i3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1006 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #3 + ldr r3, .L1006 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1006+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1006 + str r2, [r3, #124] + ldr r3, .L1006 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #3 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #3 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1006 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1006 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1006 + str r2, [r3, #120] + ldr r3, .L1006 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1006 + str r2, [r3, #60] + ldr r3, .L1006 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1006 + ldr r2, [r3, #100] + ldr r3, .L1006+8 + cmp r2, r3 + bne .L1003 + ldr r3, .L1006 + ldr r2, [r3, #468] + ldr r3, .L1006 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1006 + strb r3, [r2, #108] +.L1003: + ldr r3, .L1006 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1006 + str r2, [r3, #72] + ldr r2, .L1006 + ldr r3, .L1006 + str r3, [r2, #104] + ldr r3, .L1006 + ldr r2, [r3, #104] + ldr r3, .L1006 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1007: + .align 2 +.L1006: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i3v, .-_Z9fx_adc_i3v + .align 2 + .type _Z9fx_adc_i4v, %function +_Z9fx_adc_i4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1012 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #4 + ldr r3, .L1012 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1012+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1012 + str r2, [r3, #124] + ldr r3, .L1012 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #4 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #4 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1012 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1012 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1012 + str r2, [r3, #120] + ldr r3, .L1012 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1012 + str r2, [r3, #60] + ldr r3, .L1012 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1012 + ldr r2, [r3, #100] + ldr r3, .L1012+8 + cmp r2, r3 + bne .L1009 + ldr r3, .L1012 + ldr r2, [r3, #468] + ldr r3, .L1012 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1012 + strb r3, [r2, #108] +.L1009: + ldr r3, .L1012 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1012 + str r2, [r3, #72] + ldr r2, .L1012 + ldr r3, .L1012 + str r3, [r2, #104] + ldr r3, .L1012 + ldr r2, [r3, #104] + ldr r3, .L1012 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1013: + .align 2 +.L1012: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i4v, .-_Z9fx_adc_i4v + .align 2 + .type _Z9fx_adc_i5v, %function +_Z9fx_adc_i5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1018 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #5 + ldr r3, .L1018 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1018+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1018 + str r2, [r3, #124] + ldr r3, .L1018 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #5 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #5 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1018 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1018 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1018 + str r2, [r3, #120] + ldr r3, .L1018 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1018 + str r2, [r3, #60] + ldr r3, .L1018 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1018 + ldr r2, [r3, #100] + ldr r3, .L1018+8 + cmp r2, r3 + bne .L1015 + ldr r3, .L1018 + ldr r2, [r3, #468] + ldr r3, .L1018 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1018 + strb r3, [r2, #108] +.L1015: + ldr r3, .L1018 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1018 + str r2, [r3, #72] + ldr r2, .L1018 + ldr r3, .L1018 + str r3, [r2, #104] + ldr r3, .L1018 + ldr r2, [r3, #104] + ldr r3, .L1018 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1019: + .align 2 +.L1018: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i5v, .-_Z9fx_adc_i5v + .align 2 + .type _Z9fx_adc_i6v, %function +_Z9fx_adc_i6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1024 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #6 + ldr r3, .L1024 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1024+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1024 + str r2, [r3, #124] + ldr r3, .L1024 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #6 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #6 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1024 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1024 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1024 + str r2, [r3, #120] + ldr r3, .L1024 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1024 + str r2, [r3, #60] + ldr r3, .L1024 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1024 + ldr r2, [r3, #100] + ldr r3, .L1024+8 + cmp r2, r3 + bne .L1021 + ldr r3, .L1024 + ldr r2, [r3, #468] + ldr r3, .L1024 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1024 + strb r3, [r2, #108] +.L1021: + ldr r3, .L1024 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1024 + str r2, [r3, #72] + ldr r2, .L1024 + ldr r3, .L1024 + str r3, [r2, #104] + ldr r3, .L1024 + ldr r2, [r3, #104] + ldr r3, .L1024 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1025: + .align 2 +.L1024: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i6v, .-_Z9fx_adc_i6v + .align 2 + .type _Z9fx_adc_i7v, %function +_Z9fx_adc_i7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1030 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #7 + ldr r3, .L1030 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1030+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1030 + str r2, [r3, #124] + ldr r3, .L1030 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #7 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #7 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1030 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1030 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1030 + str r2, [r3, #120] + ldr r3, .L1030 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1030 + str r2, [r3, #60] + ldr r3, .L1030 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1030 + ldr r2, [r3, #100] + ldr r3, .L1030+8 + cmp r2, r3 + bne .L1027 + ldr r3, .L1030 + ldr r2, [r3, #468] + ldr r3, .L1030 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1030 + strb r3, [r2, #108] +.L1027: + ldr r3, .L1030 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1030 + str r2, [r3, #72] + ldr r2, .L1030 + ldr r3, .L1030 + str r3, [r2, #104] + ldr r3, .L1030 + ldr r2, [r3, #104] + ldr r3, .L1030 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1031: + .align 2 +.L1030: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i7v, .-_Z9fx_adc_i7v + .align 2 + .type _Z9fx_adc_i8v, %function +_Z9fx_adc_i8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1036 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #8 + ldr r3, .L1036 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1036+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1036 + str r2, [r3, #124] + ldr r3, .L1036 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #8 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #8 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1036 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1036 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1036 + str r2, [r3, #120] + ldr r3, .L1036 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1036 + str r2, [r3, #60] + ldr r3, .L1036 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1036 + ldr r2, [r3, #100] + ldr r3, .L1036+8 + cmp r2, r3 + bne .L1033 + ldr r3, .L1036 + ldr r2, [r3, #468] + ldr r3, .L1036 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1036 + strb r3, [r2, #108] +.L1033: + ldr r3, .L1036 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1036 + str r2, [r3, #72] + ldr r2, .L1036 + ldr r3, .L1036 + str r3, [r2, #104] + ldr r3, .L1036 + ldr r2, [r3, #104] + ldr r3, .L1036 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1037: + .align 2 +.L1036: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i8v, .-_Z9fx_adc_i8v + .align 2 + .type _Z9fx_adc_i9v, %function +_Z9fx_adc_i9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1042 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #9 + ldr r3, .L1042 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1042+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1042 + str r2, [r3, #124] + ldr r3, .L1042 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #9 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #9 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1042 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1042 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1042 + str r2, [r3, #120] + ldr r3, .L1042 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1042 + str r2, [r3, #60] + ldr r3, .L1042 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1042 + ldr r2, [r3, #100] + ldr r3, .L1042+8 + cmp r2, r3 + bne .L1039 + ldr r3, .L1042 + ldr r2, [r3, #468] + ldr r3, .L1042 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1042 + strb r3, [r2, #108] +.L1039: + ldr r3, .L1042 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1042 + str r2, [r3, #72] + ldr r2, .L1042 + ldr r3, .L1042 + str r3, [r2, #104] + ldr r3, .L1042 + ldr r2, [r3, #104] + ldr r3, .L1042 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1043: + .align 2 +.L1042: + .word GSU + .word 65535 + .word GSU+56 + .size _Z9fx_adc_i9v, .-_Z9fx_adc_i9v + .align 2 + .type _Z10fx_adc_i10v, %function +_Z10fx_adc_i10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1048 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #10 + ldr r3, .L1048 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1048+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1048 + str r2, [r3, #124] + ldr r3, .L1048 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #10 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #10 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1048 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1048 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1048 + str r2, [r3, #120] + ldr r3, .L1048 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1048 + str r2, [r3, #60] + ldr r3, .L1048 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1048 + ldr r2, [r3, #100] + ldr r3, .L1048+8 + cmp r2, r3 + bne .L1045 + ldr r3, .L1048 + ldr r2, [r3, #468] + ldr r3, .L1048 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1048 + strb r3, [r2, #108] +.L1045: + ldr r3, .L1048 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1048 + str r2, [r3, #72] + ldr r2, .L1048 + ldr r3, .L1048 + str r3, [r2, #104] + ldr r3, .L1048 + ldr r2, [r3, #104] + ldr r3, .L1048 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1049: + .align 2 +.L1048: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_i10v, .-_Z10fx_adc_i10v + .align 2 + .type _Z10fx_adc_i11v, %function +_Z10fx_adc_i11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1054 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #11 + ldr r3, .L1054 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1054+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1054 + str r2, [r3, #124] + ldr r3, .L1054 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #11 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #11 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1054 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1054 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1054 + str r2, [r3, #120] + ldr r3, .L1054 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1054 + str r2, [r3, #60] + ldr r3, .L1054 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1054 + ldr r2, [r3, #100] + ldr r3, .L1054+8 + cmp r2, r3 + bne .L1051 + ldr r3, .L1054 + ldr r2, [r3, #468] + ldr r3, .L1054 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1054 + strb r3, [r2, #108] +.L1051: + ldr r3, .L1054 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1054 + str r2, [r3, #72] + ldr r2, .L1054 + ldr r3, .L1054 + str r3, [r2, #104] + ldr r3, .L1054 + ldr r2, [r3, #104] + ldr r3, .L1054 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1055: + .align 2 +.L1054: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_i11v, .-_Z10fx_adc_i11v + .align 2 + .type _Z10fx_adc_i12v, %function +_Z10fx_adc_i12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1060 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #12 + ldr r3, .L1060 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1060+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1060 + str r2, [r3, #124] + ldr r3, .L1060 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #12 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #12 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1060 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1060 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1060 + str r2, [r3, #120] + ldr r3, .L1060 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1060 + str r2, [r3, #60] + ldr r3, .L1060 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1060 + ldr r2, [r3, #100] + ldr r3, .L1060+8 + cmp r2, r3 + bne .L1057 + ldr r3, .L1060 + ldr r2, [r3, #468] + ldr r3, .L1060 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1060 + strb r3, [r2, #108] +.L1057: + ldr r3, .L1060 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1060 + str r2, [r3, #72] + ldr r2, .L1060 + ldr r3, .L1060 + str r3, [r2, #104] + ldr r3, .L1060 + ldr r2, [r3, #104] + ldr r3, .L1060 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1061: + .align 2 +.L1060: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_i12v, .-_Z10fx_adc_i12v + .align 2 + .type _Z10fx_adc_i13v, %function +_Z10fx_adc_i13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1066 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #13 + ldr r3, .L1066 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1066+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1066 + str r2, [r3, #124] + ldr r3, .L1066 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #13 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #13 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1066 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1066 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1066 + str r2, [r3, #120] + ldr r3, .L1066 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1066 + str r2, [r3, #60] + ldr r3, .L1066 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1066 + ldr r2, [r3, #100] + ldr r3, .L1066+8 + cmp r2, r3 + bne .L1063 + ldr r3, .L1066 + ldr r2, [r3, #468] + ldr r3, .L1066 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1066 + strb r3, [r2, #108] +.L1063: + ldr r3, .L1066 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1066 + str r2, [r3, #72] + ldr r2, .L1066 + ldr r3, .L1066 + str r3, [r2, #104] + ldr r3, .L1066 + ldr r2, [r3, #104] + ldr r3, .L1066 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1067: + .align 2 +.L1066: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_i13v, .-_Z10fx_adc_i13v + .align 2 + .type _Z10fx_adc_i14v, %function +_Z10fx_adc_i14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1072 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #14 + ldr r3, .L1072 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1072+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1072 + str r2, [r3, #124] + ldr r3, .L1072 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #14 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #14 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1072 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1072 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1072 + str r2, [r3, #120] + ldr r3, .L1072 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1072 + str r2, [r3, #60] + ldr r3, .L1072 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1072 + ldr r2, [r3, #100] + ldr r3, .L1072+8 + cmp r2, r3 + bne .L1069 + ldr r3, .L1072 + ldr r2, [r3, #468] + ldr r3, .L1072 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1072 + strb r3, [r2, #108] +.L1069: + ldr r3, .L1072 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1072 + str r2, [r3, #72] + ldr r2, .L1072 + ldr r3, .L1072 + str r3, [r2, #104] + ldr r3, .L1072 + ldr r2, [r3, #104] + ldr r3, .L1072 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1073: + .align 2 +.L1072: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_i14v, .-_Z10fx_adc_i14v + .align 2 + .type _Z10fx_adc_i15v, %function +_Z10fx_adc_i15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1078 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r3, #15 + ldr r3, .L1078 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r2, [fp, #-16] + ldr r3, .L1078+4 + cmp r2, r3 + movle r2, #0 + movgt r2, #1 + ldr r3, .L1078 + str r2, [r3, #124] + ldr r3, .L1078 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + mvn r3, #15 + eor r2, r2, r3 + ldr r3, [fp, #-16] + eor r3, r3, #15 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1078 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1078 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1078 + str r2, [r3, #120] + ldr r3, .L1078 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1078 + str r2, [r3, #60] + ldr r3, .L1078 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1078 + ldr r2, [r3, #100] + ldr r3, .L1078+8 + cmp r2, r3 + bne .L1075 + ldr r3, .L1078 + ldr r2, [r3, #468] + ldr r3, .L1078 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1078 + strb r3, [r2, #108] +.L1075: + ldr r3, .L1078 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1078 + str r2, [r3, #72] + ldr r2, .L1078 + ldr r3, .L1078 + str r3, [r2, #104] + ldr r3, .L1078 + ldr r2, [r3, #104] + ldr r3, .L1078 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1079: + .align 2 +.L1078: + .word GSU + .word 65535 + .word GSU+56 + .size _Z10fx_adc_i15v, .-_Z10fx_adc_i15v + .align 2 + .type _Z9fx_sub_r0v, %function +_Z9fx_sub_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1084 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1084 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1084 + str r2, [r3, #124] + ldr r3, .L1084 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1084 + ldr r3, [r3, #0] + eor r1, r2, r3 + ldr r3, .L1084 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1084 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1084 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1084 + str r2, [r3, #120] + ldr r3, .L1084 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1084 + str r2, [r3, #60] + ldr r3, .L1084 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1084 + ldr r2, [r3, #100] + ldr r3, .L1084+4 + cmp r2, r3 + bne .L1081 + ldr r3, .L1084 + ldr r2, [r3, #468] + ldr r3, .L1084 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1084 + strb r3, [r2, #108] +.L1081: + ldr r3, .L1084 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1084 + str r2, [r3, #72] + ldr r2, .L1084 + ldr r3, .L1084 + str r3, [r2, #104] + ldr r3, .L1084 + ldr r2, [r3, #104] + ldr r3, .L1084 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1085: + .align 2 +.L1084: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r0v, .-_Z9fx_sub_r0v + .align 2 + .type _Z9fx_sub_r1v, %function +_Z9fx_sub_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1090 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1090 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1090 + str r2, [r3, #124] + ldr r3, .L1090 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1090 + ldr r3, [r3, #4] + eor r1, r2, r3 + ldr r3, .L1090 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1090 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1090 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1090 + str r2, [r3, #120] + ldr r3, .L1090 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1090 + str r2, [r3, #60] + ldr r3, .L1090 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1090 + ldr r2, [r3, #100] + ldr r3, .L1090+4 + cmp r2, r3 + bne .L1087 + ldr r3, .L1090 + ldr r2, [r3, #468] + ldr r3, .L1090 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1090 + strb r3, [r2, #108] +.L1087: + ldr r3, .L1090 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1090 + str r2, [r3, #72] + ldr r2, .L1090 + ldr r3, .L1090 + str r3, [r2, #104] + ldr r3, .L1090 + ldr r2, [r3, #104] + ldr r3, .L1090 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1091: + .align 2 +.L1090: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r1v, .-_Z9fx_sub_r1v + .align 2 + .type _Z9fx_sub_r2v, %function +_Z9fx_sub_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1096 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1096 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1096 + str r2, [r3, #124] + ldr r3, .L1096 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1096 + ldr r3, [r3, #8] + eor r1, r2, r3 + ldr r3, .L1096 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1096 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1096 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1096 + str r2, [r3, #120] + ldr r3, .L1096 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1096 + str r2, [r3, #60] + ldr r3, .L1096 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1096 + ldr r2, [r3, #100] + ldr r3, .L1096+4 + cmp r2, r3 + bne .L1093 + ldr r3, .L1096 + ldr r2, [r3, #468] + ldr r3, .L1096 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1096 + strb r3, [r2, #108] +.L1093: + ldr r3, .L1096 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1096 + str r2, [r3, #72] + ldr r2, .L1096 + ldr r3, .L1096 + str r3, [r2, #104] + ldr r3, .L1096 + ldr r2, [r3, #104] + ldr r3, .L1096 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1097: + .align 2 +.L1096: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r2v, .-_Z9fx_sub_r2v + .align 2 + .type _Z9fx_sub_r3v, %function +_Z9fx_sub_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1102 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1102 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1102 + str r2, [r3, #124] + ldr r3, .L1102 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1102 + ldr r3, [r3, #12] + eor r1, r2, r3 + ldr r3, .L1102 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1102 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1102 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1102 + str r2, [r3, #120] + ldr r3, .L1102 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1102 + str r2, [r3, #60] + ldr r3, .L1102 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1102 + ldr r2, [r3, #100] + ldr r3, .L1102+4 + cmp r2, r3 + bne .L1099 + ldr r3, .L1102 + ldr r2, [r3, #468] + ldr r3, .L1102 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1102 + strb r3, [r2, #108] +.L1099: + ldr r3, .L1102 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1102 + str r2, [r3, #72] + ldr r2, .L1102 + ldr r3, .L1102 + str r3, [r2, #104] + ldr r3, .L1102 + ldr r2, [r3, #104] + ldr r3, .L1102 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1103: + .align 2 +.L1102: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r3v, .-_Z9fx_sub_r3v + .align 2 + .type _Z9fx_sub_r4v, %function +_Z9fx_sub_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1108 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1108 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1108 + str r2, [r3, #124] + ldr r3, .L1108 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1108 + ldr r3, [r3, #16] + eor r1, r2, r3 + ldr r3, .L1108 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1108 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1108 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1108 + str r2, [r3, #120] + ldr r3, .L1108 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1108 + str r2, [r3, #60] + ldr r3, .L1108 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1108 + ldr r2, [r3, #100] + ldr r3, .L1108+4 + cmp r2, r3 + bne .L1105 + ldr r3, .L1108 + ldr r2, [r3, #468] + ldr r3, .L1108 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1108 + strb r3, [r2, #108] +.L1105: + ldr r3, .L1108 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1108 + str r2, [r3, #72] + ldr r2, .L1108 + ldr r3, .L1108 + str r3, [r2, #104] + ldr r3, .L1108 + ldr r2, [r3, #104] + ldr r3, .L1108 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1109: + .align 2 +.L1108: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r4v, .-_Z9fx_sub_r4v + .align 2 + .type _Z9fx_sub_r5v, %function +_Z9fx_sub_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1114 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1114 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1114 + str r2, [r3, #124] + ldr r3, .L1114 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1114 + ldr r3, [r3, #20] + eor r1, r2, r3 + ldr r3, .L1114 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1114 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1114 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1114 + str r2, [r3, #120] + ldr r3, .L1114 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1114 + str r2, [r3, #60] + ldr r3, .L1114 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1114 + ldr r2, [r3, #100] + ldr r3, .L1114+4 + cmp r2, r3 + bne .L1111 + ldr r3, .L1114 + ldr r2, [r3, #468] + ldr r3, .L1114 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1114 + strb r3, [r2, #108] +.L1111: + ldr r3, .L1114 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1114 + str r2, [r3, #72] + ldr r2, .L1114 + ldr r3, .L1114 + str r3, [r2, #104] + ldr r3, .L1114 + ldr r2, [r3, #104] + ldr r3, .L1114 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1115: + .align 2 +.L1114: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r5v, .-_Z9fx_sub_r5v + .align 2 + .type _Z9fx_sub_r6v, %function +_Z9fx_sub_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1120 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1120 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1120 + str r2, [r3, #124] + ldr r3, .L1120 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1120 + ldr r3, [r3, #24] + eor r1, r2, r3 + ldr r3, .L1120 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1120 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1120 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1120 + str r2, [r3, #120] + ldr r3, .L1120 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1120 + str r2, [r3, #60] + ldr r3, .L1120 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1120 + ldr r2, [r3, #100] + ldr r3, .L1120+4 + cmp r2, r3 + bne .L1117 + ldr r3, .L1120 + ldr r2, [r3, #468] + ldr r3, .L1120 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1120 + strb r3, [r2, #108] +.L1117: + ldr r3, .L1120 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1120 + str r2, [r3, #72] + ldr r2, .L1120 + ldr r3, .L1120 + str r3, [r2, #104] + ldr r3, .L1120 + ldr r2, [r3, #104] + ldr r3, .L1120 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1121: + .align 2 +.L1120: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r6v, .-_Z9fx_sub_r6v + .align 2 + .type _Z9fx_sub_r7v, %function +_Z9fx_sub_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1126 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1126 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1126 + str r2, [r3, #124] + ldr r3, .L1126 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1126 + ldr r3, [r3, #28] + eor r1, r2, r3 + ldr r3, .L1126 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1126 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1126 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1126 + str r2, [r3, #120] + ldr r3, .L1126 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1126 + str r2, [r3, #60] + ldr r3, .L1126 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1126 + ldr r2, [r3, #100] + ldr r3, .L1126+4 + cmp r2, r3 + bne .L1123 + ldr r3, .L1126 + ldr r2, [r3, #468] + ldr r3, .L1126 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1126 + strb r3, [r2, #108] +.L1123: + ldr r3, .L1126 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1126 + str r2, [r3, #72] + ldr r2, .L1126 + ldr r3, .L1126 + str r3, [r2, #104] + ldr r3, .L1126 + ldr r2, [r3, #104] + ldr r3, .L1126 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1127: + .align 2 +.L1126: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r7v, .-_Z9fx_sub_r7v + .align 2 + .type _Z9fx_sub_r8v, %function +_Z9fx_sub_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1132 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1132 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1132 + str r2, [r3, #124] + ldr r3, .L1132 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1132 + ldr r3, [r3, #32] + eor r1, r2, r3 + ldr r3, .L1132 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1132 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1132 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1132 + str r2, [r3, #120] + ldr r3, .L1132 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1132 + str r2, [r3, #60] + ldr r3, .L1132 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1132 + ldr r2, [r3, #100] + ldr r3, .L1132+4 + cmp r2, r3 + bne .L1129 + ldr r3, .L1132 + ldr r2, [r3, #468] + ldr r3, .L1132 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1132 + strb r3, [r2, #108] +.L1129: + ldr r3, .L1132 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1132 + str r2, [r3, #72] + ldr r2, .L1132 + ldr r3, .L1132 + str r3, [r2, #104] + ldr r3, .L1132 + ldr r2, [r3, #104] + ldr r3, .L1132 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1133: + .align 2 +.L1132: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r8v, .-_Z9fx_sub_r8v + .align 2 + .type _Z9fx_sub_r9v, %function +_Z9fx_sub_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1138 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1138 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1138 + str r2, [r3, #124] + ldr r3, .L1138 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1138 + ldr r3, [r3, #36] + eor r1, r2, r3 + ldr r3, .L1138 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1138 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1138 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1138 + str r2, [r3, #120] + ldr r3, .L1138 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1138 + str r2, [r3, #60] + ldr r3, .L1138 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1138 + ldr r2, [r3, #100] + ldr r3, .L1138+4 + cmp r2, r3 + bne .L1135 + ldr r3, .L1138 + ldr r2, [r3, #468] + ldr r3, .L1138 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1138 + strb r3, [r2, #108] +.L1135: + ldr r3, .L1138 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1138 + str r2, [r3, #72] + ldr r2, .L1138 + ldr r3, .L1138 + str r3, [r2, #104] + ldr r3, .L1138 + ldr r2, [r3, #104] + ldr r3, .L1138 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1139: + .align 2 +.L1138: + .word GSU + .word GSU+56 + .size _Z9fx_sub_r9v, .-_Z9fx_sub_r9v + .align 2 + .type _Z10fx_sub_r10v, %function +_Z10fx_sub_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1144 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1144 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1144 + str r2, [r3, #124] + ldr r3, .L1144 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1144 + ldr r3, [r3, #40] + eor r1, r2, r3 + ldr r3, .L1144 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1144 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1144 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1144 + str r2, [r3, #120] + ldr r3, .L1144 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1144 + str r2, [r3, #60] + ldr r3, .L1144 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1144 + ldr r2, [r3, #100] + ldr r3, .L1144+4 + cmp r2, r3 + bne .L1141 + ldr r3, .L1144 + ldr r2, [r3, #468] + ldr r3, .L1144 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1144 + strb r3, [r2, #108] +.L1141: + ldr r3, .L1144 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1144 + str r2, [r3, #72] + ldr r2, .L1144 + ldr r3, .L1144 + str r3, [r2, #104] + ldr r3, .L1144 + ldr r2, [r3, #104] + ldr r3, .L1144 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1145: + .align 2 +.L1144: + .word GSU + .word GSU+56 + .size _Z10fx_sub_r10v, .-_Z10fx_sub_r10v + .align 2 + .type _Z10fx_sub_r11v, %function +_Z10fx_sub_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1150 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1150 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1150 + str r2, [r3, #124] + ldr r3, .L1150 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1150 + ldr r3, [r3, #44] + eor r1, r2, r3 + ldr r3, .L1150 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1150 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1150 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1150 + str r2, [r3, #120] + ldr r3, .L1150 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1150 + str r2, [r3, #60] + ldr r3, .L1150 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1150 + ldr r2, [r3, #100] + ldr r3, .L1150+4 + cmp r2, r3 + bne .L1147 + ldr r3, .L1150 + ldr r2, [r3, #468] + ldr r3, .L1150 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1150 + strb r3, [r2, #108] +.L1147: + ldr r3, .L1150 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1150 + str r2, [r3, #72] + ldr r2, .L1150 + ldr r3, .L1150 + str r3, [r2, #104] + ldr r3, .L1150 + ldr r2, [r3, #104] + ldr r3, .L1150 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1151: + .align 2 +.L1150: + .word GSU + .word GSU+56 + .size _Z10fx_sub_r11v, .-_Z10fx_sub_r11v + .align 2 + .type _Z10fx_sub_r12v, %function +_Z10fx_sub_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1156 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1156 + ldr r3, [r3, #48] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1156 + str r2, [r3, #124] + ldr r3, .L1156 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1156 + ldr r3, [r3, #48] + eor r1, r2, r3 + ldr r3, .L1156 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1156 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1156 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1156 + str r2, [r3, #120] + ldr r3, .L1156 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1156 + str r2, [r3, #60] + ldr r3, .L1156 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1156 + ldr r2, [r3, #100] + ldr r3, .L1156+4 + cmp r2, r3 + bne .L1153 + ldr r3, .L1156 + ldr r2, [r3, #468] + ldr r3, .L1156 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1156 + strb r3, [r2, #108] +.L1153: + ldr r3, .L1156 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1156 + str r2, [r3, #72] + ldr r2, .L1156 + ldr r3, .L1156 + str r3, [r2, #104] + ldr r3, .L1156 + ldr r2, [r3, #104] + ldr r3, .L1156 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1157: + .align 2 +.L1156: + .word GSU + .word GSU+56 + .size _Z10fx_sub_r12v, .-_Z10fx_sub_r12v + .align 2 + .type _Z10fx_sub_r13v, %function +_Z10fx_sub_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1162 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1162 + ldr r3, [r3, #52] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1162 + str r2, [r3, #124] + ldr r3, .L1162 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1162 + ldr r3, [r3, #52] + eor r1, r2, r3 + ldr r3, .L1162 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1162 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1162 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1162 + str r2, [r3, #120] + ldr r3, .L1162 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1162 + str r2, [r3, #60] + ldr r3, .L1162 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1162 + ldr r2, [r3, #100] + ldr r3, .L1162+4 + cmp r2, r3 + bne .L1159 + ldr r3, .L1162 + ldr r2, [r3, #468] + ldr r3, .L1162 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1162 + strb r3, [r2, #108] +.L1159: + ldr r3, .L1162 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1162 + str r2, [r3, #72] + ldr r2, .L1162 + ldr r3, .L1162 + str r3, [r2, #104] + ldr r3, .L1162 + ldr r2, [r3, #104] + ldr r3, .L1162 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1163: + .align 2 +.L1162: + .word GSU + .word GSU+56 + .size _Z10fx_sub_r13v, .-_Z10fx_sub_r13v + .align 2 + .type _Z10fx_sub_r14v, %function +_Z10fx_sub_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1168 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1168 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1168 + str r2, [r3, #124] + ldr r3, .L1168 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1168 + ldr r3, [r3, #56] + eor r1, r2, r3 + ldr r3, .L1168 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1168 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1168 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1168 + str r2, [r3, #120] + ldr r3, .L1168 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1168 + str r2, [r3, #60] + ldr r3, .L1168 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1168 + ldr r2, [r3, #100] + ldr r3, .L1168+4 + cmp r2, r3 + bne .L1165 + ldr r3, .L1168 + ldr r2, [r3, #468] + ldr r3, .L1168 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1168 + strb r3, [r2, #108] +.L1165: + ldr r3, .L1168 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1168 + str r2, [r3, #72] + ldr r2, .L1168 + ldr r3, .L1168 + str r3, [r2, #104] + ldr r3, .L1168 + ldr r2, [r3, #104] + ldr r3, .L1168 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1169: + .align 2 +.L1168: + .word GSU + .word GSU+56 + .size _Z10fx_sub_r14v, .-_Z10fx_sub_r14v + .align 2 + .type _Z10fx_sub_r15v, %function +_Z10fx_sub_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1174 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1174 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1174 + str r2, [r3, #124] + ldr r3, .L1174 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1174 + ldr r3, [r3, #60] + eor r1, r2, r3 + ldr r3, .L1174 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1174 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1174 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1174 + str r2, [r3, #120] + ldr r3, .L1174 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1174 + str r2, [r3, #60] + ldr r3, .L1174 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1174 + ldr r2, [r3, #100] + ldr r3, .L1174+4 + cmp r2, r3 + bne .L1171 + ldr r3, .L1174 + ldr r2, [r3, #468] + ldr r3, .L1174 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1174 + strb r3, [r2, #108] +.L1171: + ldr r3, .L1174 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1174 + str r2, [r3, #72] + ldr r2, .L1174 + ldr r3, .L1174 + str r3, [r2, #104] + ldr r3, .L1174 + ldr r2, [r3, #104] + ldr r3, .L1174 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1175: + .align 2 +.L1174: + .word GSU + .word GSU+56 + .size _Z10fx_sub_r15v, .-_Z10fx_sub_r15v + .align 2 + .type _Z9fx_sbc_r0v, %function +_Z9fx_sbc_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1180 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1180 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1180 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1180 + str r2, [r3, #124] + ldr r3, .L1180 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1180 + ldr r3, [r3, #0] + eor r1, r2, r3 + ldr r3, .L1180 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1180 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1180 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1180 + str r2, [r3, #120] + ldr r3, .L1180 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1180 + str r2, [r3, #60] + ldr r3, .L1180 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1180 + ldr r2, [r3, #100] + ldr r3, .L1180+4 + cmp r2, r3 + bne .L1177 + ldr r3, .L1180 + ldr r2, [r3, #468] + ldr r3, .L1180 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1180 + strb r3, [r2, #108] +.L1177: + ldr r3, .L1180 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1180 + str r2, [r3, #72] + ldr r2, .L1180 + ldr r3, .L1180 + str r3, [r2, #104] + ldr r3, .L1180 + ldr r2, [r3, #104] + ldr r3, .L1180 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1181: + .align 2 +.L1180: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r0v, .-_Z9fx_sbc_r0v + .align 2 + .type _Z9fx_sbc_r1v, %function +_Z9fx_sbc_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1186 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1186 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1186 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1186 + str r2, [r3, #124] + ldr r3, .L1186 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1186 + ldr r3, [r3, #4] + eor r1, r2, r3 + ldr r3, .L1186 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1186 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1186 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1186 + str r2, [r3, #120] + ldr r3, .L1186 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1186 + str r2, [r3, #60] + ldr r3, .L1186 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1186 + ldr r2, [r3, #100] + ldr r3, .L1186+4 + cmp r2, r3 + bne .L1183 + ldr r3, .L1186 + ldr r2, [r3, #468] + ldr r3, .L1186 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1186 + strb r3, [r2, #108] +.L1183: + ldr r3, .L1186 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1186 + str r2, [r3, #72] + ldr r2, .L1186 + ldr r3, .L1186 + str r3, [r2, #104] + ldr r3, .L1186 + ldr r2, [r3, #104] + ldr r3, .L1186 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1187: + .align 2 +.L1186: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r1v, .-_Z9fx_sbc_r1v + .align 2 + .type _Z9fx_sbc_r2v, %function +_Z9fx_sbc_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1192 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1192 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1192 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1192 + str r2, [r3, #124] + ldr r3, .L1192 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1192 + ldr r3, [r3, #8] + eor r1, r2, r3 + ldr r3, .L1192 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1192 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1192 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1192 + str r2, [r3, #120] + ldr r3, .L1192 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1192 + str r2, [r3, #60] + ldr r3, .L1192 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1192 + ldr r2, [r3, #100] + ldr r3, .L1192+4 + cmp r2, r3 + bne .L1189 + ldr r3, .L1192 + ldr r2, [r3, #468] + ldr r3, .L1192 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1192 + strb r3, [r2, #108] +.L1189: + ldr r3, .L1192 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1192 + str r2, [r3, #72] + ldr r2, .L1192 + ldr r3, .L1192 + str r3, [r2, #104] + ldr r3, .L1192 + ldr r2, [r3, #104] + ldr r3, .L1192 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1193: + .align 2 +.L1192: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r2v, .-_Z9fx_sbc_r2v + .align 2 + .type _Z9fx_sbc_r3v, %function +_Z9fx_sbc_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1198 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1198 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1198 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1198 + str r2, [r3, #124] + ldr r3, .L1198 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1198 + ldr r3, [r3, #12] + eor r1, r2, r3 + ldr r3, .L1198 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1198 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1198 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1198 + str r2, [r3, #120] + ldr r3, .L1198 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1198 + str r2, [r3, #60] + ldr r3, .L1198 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1198 + ldr r2, [r3, #100] + ldr r3, .L1198+4 + cmp r2, r3 + bne .L1195 + ldr r3, .L1198 + ldr r2, [r3, #468] + ldr r3, .L1198 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1198 + strb r3, [r2, #108] +.L1195: + ldr r3, .L1198 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1198 + str r2, [r3, #72] + ldr r2, .L1198 + ldr r3, .L1198 + str r3, [r2, #104] + ldr r3, .L1198 + ldr r2, [r3, #104] + ldr r3, .L1198 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1199: + .align 2 +.L1198: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r3v, .-_Z9fx_sbc_r3v + .align 2 + .type _Z9fx_sbc_r4v, %function +_Z9fx_sbc_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1204 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1204 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1204 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1204 + str r2, [r3, #124] + ldr r3, .L1204 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1204 + ldr r3, [r3, #16] + eor r1, r2, r3 + ldr r3, .L1204 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1204 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1204 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1204 + str r2, [r3, #120] + ldr r3, .L1204 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1204 + str r2, [r3, #60] + ldr r3, .L1204 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1204 + ldr r2, [r3, #100] + ldr r3, .L1204+4 + cmp r2, r3 + bne .L1201 + ldr r3, .L1204 + ldr r2, [r3, #468] + ldr r3, .L1204 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1204 + strb r3, [r2, #108] +.L1201: + ldr r3, .L1204 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1204 + str r2, [r3, #72] + ldr r2, .L1204 + ldr r3, .L1204 + str r3, [r2, #104] + ldr r3, .L1204 + ldr r2, [r3, #104] + ldr r3, .L1204 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1205: + .align 2 +.L1204: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r4v, .-_Z9fx_sbc_r4v + .align 2 + .type _Z9fx_sbc_r5v, %function +_Z9fx_sbc_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1210 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1210 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1210 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1210 + str r2, [r3, #124] + ldr r3, .L1210 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1210 + ldr r3, [r3, #20] + eor r1, r2, r3 + ldr r3, .L1210 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1210 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1210 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1210 + str r2, [r3, #120] + ldr r3, .L1210 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1210 + str r2, [r3, #60] + ldr r3, .L1210 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1210 + ldr r2, [r3, #100] + ldr r3, .L1210+4 + cmp r2, r3 + bne .L1207 + ldr r3, .L1210 + ldr r2, [r3, #468] + ldr r3, .L1210 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1210 + strb r3, [r2, #108] +.L1207: + ldr r3, .L1210 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1210 + str r2, [r3, #72] + ldr r2, .L1210 + ldr r3, .L1210 + str r3, [r2, #104] + ldr r3, .L1210 + ldr r2, [r3, #104] + ldr r3, .L1210 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1211: + .align 2 +.L1210: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r5v, .-_Z9fx_sbc_r5v + .align 2 + .type _Z9fx_sbc_r6v, %function +_Z9fx_sbc_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1216 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1216 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1216 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1216 + str r2, [r3, #124] + ldr r3, .L1216 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1216 + ldr r3, [r3, #24] + eor r1, r2, r3 + ldr r3, .L1216 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1216 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1216 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1216 + str r2, [r3, #120] + ldr r3, .L1216 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1216 + str r2, [r3, #60] + ldr r3, .L1216 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1216 + ldr r2, [r3, #100] + ldr r3, .L1216+4 + cmp r2, r3 + bne .L1213 + ldr r3, .L1216 + ldr r2, [r3, #468] + ldr r3, .L1216 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1216 + strb r3, [r2, #108] +.L1213: + ldr r3, .L1216 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1216 + str r2, [r3, #72] + ldr r2, .L1216 + ldr r3, .L1216 + str r3, [r2, #104] + ldr r3, .L1216 + ldr r2, [r3, #104] + ldr r3, .L1216 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1217: + .align 2 +.L1216: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r6v, .-_Z9fx_sbc_r6v + .align 2 + .type _Z9fx_sbc_r7v, %function +_Z9fx_sbc_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1222 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1222 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1222 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1222 + str r2, [r3, #124] + ldr r3, .L1222 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1222 + ldr r3, [r3, #28] + eor r1, r2, r3 + ldr r3, .L1222 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1222 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1222 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1222 + str r2, [r3, #120] + ldr r3, .L1222 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1222 + str r2, [r3, #60] + ldr r3, .L1222 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1222 + ldr r2, [r3, #100] + ldr r3, .L1222+4 + cmp r2, r3 + bne .L1219 + ldr r3, .L1222 + ldr r2, [r3, #468] + ldr r3, .L1222 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1222 + strb r3, [r2, #108] +.L1219: + ldr r3, .L1222 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1222 + str r2, [r3, #72] + ldr r2, .L1222 + ldr r3, .L1222 + str r3, [r2, #104] + ldr r3, .L1222 + ldr r2, [r3, #104] + ldr r3, .L1222 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1223: + .align 2 +.L1222: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r7v, .-_Z9fx_sbc_r7v + .align 2 + .type _Z9fx_sbc_r8v, %function +_Z9fx_sbc_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1228 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1228 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1228 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1228 + str r2, [r3, #124] + ldr r3, .L1228 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1228 + ldr r3, [r3, #32] + eor r1, r2, r3 + ldr r3, .L1228 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1228 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1228 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1228 + str r2, [r3, #120] + ldr r3, .L1228 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1228 + str r2, [r3, #60] + ldr r3, .L1228 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1228 + ldr r2, [r3, #100] + ldr r3, .L1228+4 + cmp r2, r3 + bne .L1225 + ldr r3, .L1228 + ldr r2, [r3, #468] + ldr r3, .L1228 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1228 + strb r3, [r2, #108] +.L1225: + ldr r3, .L1228 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1228 + str r2, [r3, #72] + ldr r2, .L1228 + ldr r3, .L1228 + str r3, [r2, #104] + ldr r3, .L1228 + ldr r2, [r3, #104] + ldr r3, .L1228 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1229: + .align 2 +.L1228: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r8v, .-_Z9fx_sbc_r8v + .align 2 + .type _Z9fx_sbc_r9v, %function +_Z9fx_sbc_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1234 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1234 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1234 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1234 + str r2, [r3, #124] + ldr r3, .L1234 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1234 + ldr r3, [r3, #36] + eor r1, r2, r3 + ldr r3, .L1234 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1234 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1234 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1234 + str r2, [r3, #120] + ldr r3, .L1234 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1234 + str r2, [r3, #60] + ldr r3, .L1234 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1234 + ldr r2, [r3, #100] + ldr r3, .L1234+4 + cmp r2, r3 + bne .L1231 + ldr r3, .L1234 + ldr r2, [r3, #468] + ldr r3, .L1234 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1234 + strb r3, [r2, #108] +.L1231: + ldr r3, .L1234 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1234 + str r2, [r3, #72] + ldr r2, .L1234 + ldr r3, .L1234 + str r3, [r2, #104] + ldr r3, .L1234 + ldr r2, [r3, #104] + ldr r3, .L1234 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1235: + .align 2 +.L1234: + .word GSU + .word GSU+56 + .size _Z9fx_sbc_r9v, .-_Z9fx_sbc_r9v + .align 2 + .type _Z10fx_sbc_r10v, %function +_Z10fx_sbc_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1240 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1240 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1240 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1240 + str r2, [r3, #124] + ldr r3, .L1240 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1240 + ldr r3, [r3, #40] + eor r1, r2, r3 + ldr r3, .L1240 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1240 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1240 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1240 + str r2, [r3, #120] + ldr r3, .L1240 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1240 + str r2, [r3, #60] + ldr r3, .L1240 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1240 + ldr r2, [r3, #100] + ldr r3, .L1240+4 + cmp r2, r3 + bne .L1237 + ldr r3, .L1240 + ldr r2, [r3, #468] + ldr r3, .L1240 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1240 + strb r3, [r2, #108] +.L1237: + ldr r3, .L1240 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1240 + str r2, [r3, #72] + ldr r2, .L1240 + ldr r3, .L1240 + str r3, [r2, #104] + ldr r3, .L1240 + ldr r2, [r3, #104] + ldr r3, .L1240 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1241: + .align 2 +.L1240: + .word GSU + .word GSU+56 + .size _Z10fx_sbc_r10v, .-_Z10fx_sbc_r10v + .align 2 + .type _Z10fx_sbc_r11v, %function +_Z10fx_sbc_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1246 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1246 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1246 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1246 + str r2, [r3, #124] + ldr r3, .L1246 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1246 + ldr r3, [r3, #44] + eor r1, r2, r3 + ldr r3, .L1246 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1246 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1246 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1246 + str r2, [r3, #120] + ldr r3, .L1246 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1246 + str r2, [r3, #60] + ldr r3, .L1246 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1246 + ldr r2, [r3, #100] + ldr r3, .L1246+4 + cmp r2, r3 + bne .L1243 + ldr r3, .L1246 + ldr r2, [r3, #468] + ldr r3, .L1246 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1246 + strb r3, [r2, #108] +.L1243: + ldr r3, .L1246 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1246 + str r2, [r3, #72] + ldr r2, .L1246 + ldr r3, .L1246 + str r3, [r2, #104] + ldr r3, .L1246 + ldr r2, [r3, #104] + ldr r3, .L1246 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1247: + .align 2 +.L1246: + .word GSU + .word GSU+56 + .size _Z10fx_sbc_r11v, .-_Z10fx_sbc_r11v + .align 2 + .type _Z10fx_sbc_r12v, %function +_Z10fx_sbc_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1252 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1252 + ldr r3, [r3, #48] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1252 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1252 + str r2, [r3, #124] + ldr r3, .L1252 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1252 + ldr r3, [r3, #48] + eor r1, r2, r3 + ldr r3, .L1252 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1252 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1252 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1252 + str r2, [r3, #120] + ldr r3, .L1252 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1252 + str r2, [r3, #60] + ldr r3, .L1252 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1252 + ldr r2, [r3, #100] + ldr r3, .L1252+4 + cmp r2, r3 + bne .L1249 + ldr r3, .L1252 + ldr r2, [r3, #468] + ldr r3, .L1252 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1252 + strb r3, [r2, #108] +.L1249: + ldr r3, .L1252 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1252 + str r2, [r3, #72] + ldr r2, .L1252 + ldr r3, .L1252 + str r3, [r2, #104] + ldr r3, .L1252 + ldr r2, [r3, #104] + ldr r3, .L1252 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1253: + .align 2 +.L1252: + .word GSU + .word GSU+56 + .size _Z10fx_sbc_r12v, .-_Z10fx_sbc_r12v + .align 2 + .type _Z10fx_sbc_r13v, %function +_Z10fx_sbc_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1258 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1258 + ldr r3, [r3, #52] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1258 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1258 + str r2, [r3, #124] + ldr r3, .L1258 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1258 + ldr r3, [r3, #52] + eor r1, r2, r3 + ldr r3, .L1258 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1258 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1258 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1258 + str r2, [r3, #120] + ldr r3, .L1258 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1258 + str r2, [r3, #60] + ldr r3, .L1258 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1258 + ldr r2, [r3, #100] + ldr r3, .L1258+4 + cmp r2, r3 + bne .L1255 + ldr r3, .L1258 + ldr r2, [r3, #468] + ldr r3, .L1258 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1258 + strb r3, [r2, #108] +.L1255: + ldr r3, .L1258 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1258 + str r2, [r3, #72] + ldr r2, .L1258 + ldr r3, .L1258 + str r3, [r2, #104] + ldr r3, .L1258 + ldr r2, [r3, #104] + ldr r3, .L1258 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1259: + .align 2 +.L1258: + .word GSU + .word GSU+56 + .size _Z10fx_sbc_r13v, .-_Z10fx_sbc_r13v + .align 2 + .type _Z10fx_sbc_r14v, %function +_Z10fx_sbc_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1264 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1264 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1264 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1264 + str r2, [r3, #124] + ldr r3, .L1264 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1264 + ldr r3, [r3, #56] + eor r1, r2, r3 + ldr r3, .L1264 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1264 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1264 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1264 + str r2, [r3, #120] + ldr r3, .L1264 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1264 + str r2, [r3, #60] + ldr r3, .L1264 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1264 + ldr r2, [r3, #100] + ldr r3, .L1264+4 + cmp r2, r3 + bne .L1261 + ldr r3, .L1264 + ldr r2, [r3, #468] + ldr r3, .L1264 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1264 + strb r3, [r2, #108] +.L1261: + ldr r3, .L1264 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1264 + str r2, [r3, #72] + ldr r2, .L1264 + ldr r3, .L1264 + str r3, [r2, #104] + ldr r3, .L1264 + ldr r2, [r3, #104] + ldr r3, .L1264 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1265: + .align 2 +.L1264: + .word GSU + .word GSU+56 + .size _Z10fx_sbc_r14v, .-_Z10fx_sbc_r14v + .align 2 + .type _Z10fx_sbc_r15v, %function +_Z10fx_sbc_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1270 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1270 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r2, r3, r2 + ldr r3, .L1270 + ldr r3, [r3, #124] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1270 + str r2, [r3, #124] + ldr r3, .L1270 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1270 + ldr r3, [r3, #60] + eor r1, r2, r3 + ldr r3, .L1270 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1270 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1270 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1270 + str r2, [r3, #120] + ldr r3, .L1270 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1270 + str r2, [r3, #60] + ldr r3, .L1270 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1270 + ldr r2, [r3, #100] + ldr r3, .L1270+4 + cmp r2, r3 + bne .L1267 + ldr r3, .L1270 + ldr r2, [r3, #468] + ldr r3, .L1270 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1270 + strb r3, [r2, #108] +.L1267: + ldr r3, .L1270 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1270 + str r2, [r3, #72] + ldr r2, .L1270 + ldr r3, .L1270 + str r3, [r2, #104] + ldr r3, .L1270 + ldr r2, [r3, #104] + ldr r3, .L1270 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1271: + .align 2 +.L1270: + .word GSU + .word GSU+56 + .size _Z10fx_sbc_r15v, .-_Z10fx_sbc_r15v + .align 2 + .type _Z9fx_sub_i0v, %function +_Z9fx_sub_i0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1276 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1276 + str r2, [r3, #124] + ldr r3, .L1276 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + mvn r3, r3 + and r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1276 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1276 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1276 + str r2, [r3, #120] + ldr r3, .L1276 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1276 + str r2, [r3, #60] + ldr r3, .L1276 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1276 + ldr r2, [r3, #100] + ldr r3, .L1276+4 + cmp r2, r3 + bne .L1273 + ldr r3, .L1276 + ldr r2, [r3, #468] + ldr r3, .L1276 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1276 + strb r3, [r2, #108] +.L1273: + ldr r3, .L1276 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1276 + str r2, [r3, #72] + ldr r2, .L1276 + ldr r3, .L1276 + str r3, [r2, #104] + ldr r3, .L1276 + ldr r2, [r3, #104] + ldr r3, .L1276 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1277: + .align 2 +.L1276: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i0v, .-_Z9fx_sub_i0v + .align 2 + .type _Z9fx_sub_i1v, %function +_Z9fx_sub_i1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1282 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #1 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1282 + str r2, [r3, #124] + ldr r3, .L1282 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #1 + ldr r3, .L1282 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1282 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1282 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1282 + str r2, [r3, #120] + ldr r3, .L1282 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1282 + str r2, [r3, #60] + ldr r3, .L1282 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1282 + ldr r2, [r3, #100] + ldr r3, .L1282+4 + cmp r2, r3 + bne .L1279 + ldr r3, .L1282 + ldr r2, [r3, #468] + ldr r3, .L1282 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1282 + strb r3, [r2, #108] +.L1279: + ldr r3, .L1282 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1282 + str r2, [r3, #72] + ldr r2, .L1282 + ldr r3, .L1282 + str r3, [r2, #104] + ldr r3, .L1282 + ldr r2, [r3, #104] + ldr r3, .L1282 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1283: + .align 2 +.L1282: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i1v, .-_Z9fx_sub_i1v + .align 2 + .type _Z9fx_sub_i2v, %function +_Z9fx_sub_i2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1288 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1288 + str r2, [r3, #124] + ldr r3, .L1288 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #2 + ldr r3, .L1288 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1288 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1288 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1288 + str r2, [r3, #120] + ldr r3, .L1288 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1288 + str r2, [r3, #60] + ldr r3, .L1288 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1288 + ldr r2, [r3, #100] + ldr r3, .L1288+4 + cmp r2, r3 + bne .L1285 + ldr r3, .L1288 + ldr r2, [r3, #468] + ldr r3, .L1288 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1288 + strb r3, [r2, #108] +.L1285: + ldr r3, .L1288 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1288 + str r2, [r3, #72] + ldr r2, .L1288 + ldr r3, .L1288 + str r3, [r2, #104] + ldr r3, .L1288 + ldr r2, [r3, #104] + ldr r3, .L1288 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1289: + .align 2 +.L1288: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i2v, .-_Z9fx_sub_i2v + .align 2 + .type _Z9fx_sub_i3v, %function +_Z9fx_sub_i3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1294 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #3 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1294 + str r2, [r3, #124] + ldr r3, .L1294 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #3 + ldr r3, .L1294 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1294 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1294 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1294 + str r2, [r3, #120] + ldr r3, .L1294 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1294 + str r2, [r3, #60] + ldr r3, .L1294 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1294 + ldr r2, [r3, #100] + ldr r3, .L1294+4 + cmp r2, r3 + bne .L1291 + ldr r3, .L1294 + ldr r2, [r3, #468] + ldr r3, .L1294 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1294 + strb r3, [r2, #108] +.L1291: + ldr r3, .L1294 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1294 + str r2, [r3, #72] + ldr r2, .L1294 + ldr r3, .L1294 + str r3, [r2, #104] + ldr r3, .L1294 + ldr r2, [r3, #104] + ldr r3, .L1294 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1295: + .align 2 +.L1294: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i3v, .-_Z9fx_sub_i3v + .align 2 + .type _Z9fx_sub_i4v, %function +_Z9fx_sub_i4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1300 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #4 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1300 + str r2, [r3, #124] + ldr r3, .L1300 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #4 + ldr r3, .L1300 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1300 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1300 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1300 + str r2, [r3, #120] + ldr r3, .L1300 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1300 + str r2, [r3, #60] + ldr r3, .L1300 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1300 + ldr r2, [r3, #100] + ldr r3, .L1300+4 + cmp r2, r3 + bne .L1297 + ldr r3, .L1300 + ldr r2, [r3, #468] + ldr r3, .L1300 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1300 + strb r3, [r2, #108] +.L1297: + ldr r3, .L1300 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1300 + str r2, [r3, #72] + ldr r2, .L1300 + ldr r3, .L1300 + str r3, [r2, #104] + ldr r3, .L1300 + ldr r2, [r3, #104] + ldr r3, .L1300 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1301: + .align 2 +.L1300: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i4v, .-_Z9fx_sub_i4v + .align 2 + .type _Z9fx_sub_i5v, %function +_Z9fx_sub_i5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1306 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #5 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1306 + str r2, [r3, #124] + ldr r3, .L1306 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #5 + ldr r3, .L1306 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1306 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1306 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1306 + str r2, [r3, #120] + ldr r3, .L1306 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1306 + str r2, [r3, #60] + ldr r3, .L1306 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1306 + ldr r2, [r3, #100] + ldr r3, .L1306+4 + cmp r2, r3 + bne .L1303 + ldr r3, .L1306 + ldr r2, [r3, #468] + ldr r3, .L1306 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1306 + strb r3, [r2, #108] +.L1303: + ldr r3, .L1306 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1306 + str r2, [r3, #72] + ldr r2, .L1306 + ldr r3, .L1306 + str r3, [r2, #104] + ldr r3, .L1306 + ldr r2, [r3, #104] + ldr r3, .L1306 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1307: + .align 2 +.L1306: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i5v, .-_Z9fx_sub_i5v + .align 2 + .type _Z9fx_sub_i6v, %function +_Z9fx_sub_i6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1312 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #6 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1312 + str r2, [r3, #124] + ldr r3, .L1312 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #6 + ldr r3, .L1312 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1312 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1312 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1312 + str r2, [r3, #120] + ldr r3, .L1312 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1312 + str r2, [r3, #60] + ldr r3, .L1312 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1312 + ldr r2, [r3, #100] + ldr r3, .L1312+4 + cmp r2, r3 + bne .L1309 + ldr r3, .L1312 + ldr r2, [r3, #468] + ldr r3, .L1312 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1312 + strb r3, [r2, #108] +.L1309: + ldr r3, .L1312 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1312 + str r2, [r3, #72] + ldr r2, .L1312 + ldr r3, .L1312 + str r3, [r2, #104] + ldr r3, .L1312 + ldr r2, [r3, #104] + ldr r3, .L1312 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1313: + .align 2 +.L1312: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i6v, .-_Z9fx_sub_i6v + .align 2 + .type _Z9fx_sub_i7v, %function +_Z9fx_sub_i7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1318 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #7 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1318 + str r2, [r3, #124] + ldr r3, .L1318 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #7 + ldr r3, .L1318 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1318 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1318 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1318 + str r2, [r3, #120] + ldr r3, .L1318 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1318 + str r2, [r3, #60] + ldr r3, .L1318 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1318 + ldr r2, [r3, #100] + ldr r3, .L1318+4 + cmp r2, r3 + bne .L1315 + ldr r3, .L1318 + ldr r2, [r3, #468] + ldr r3, .L1318 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1318 + strb r3, [r2, #108] +.L1315: + ldr r3, .L1318 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1318 + str r2, [r3, #72] + ldr r2, .L1318 + ldr r3, .L1318 + str r3, [r2, #104] + ldr r3, .L1318 + ldr r2, [r3, #104] + ldr r3, .L1318 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1319: + .align 2 +.L1318: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i7v, .-_Z9fx_sub_i7v + .align 2 + .type _Z9fx_sub_i8v, %function +_Z9fx_sub_i8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1324 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #8 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1324 + str r2, [r3, #124] + ldr r3, .L1324 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #8 + ldr r3, .L1324 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1324 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1324 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1324 + str r2, [r3, #120] + ldr r3, .L1324 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1324 + str r2, [r3, #60] + ldr r3, .L1324 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1324 + ldr r2, [r3, #100] + ldr r3, .L1324+4 + cmp r2, r3 + bne .L1321 + ldr r3, .L1324 + ldr r2, [r3, #468] + ldr r3, .L1324 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1324 + strb r3, [r2, #108] +.L1321: + ldr r3, .L1324 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1324 + str r2, [r3, #72] + ldr r2, .L1324 + ldr r3, .L1324 + str r3, [r2, #104] + ldr r3, .L1324 + ldr r2, [r3, #104] + ldr r3, .L1324 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1325: + .align 2 +.L1324: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i8v, .-_Z9fx_sub_i8v + .align 2 + .type _Z9fx_sub_i9v, %function +_Z9fx_sub_i9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1330 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #9 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1330 + str r2, [r3, #124] + ldr r3, .L1330 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #9 + ldr r3, .L1330 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1330 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1330 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1330 + str r2, [r3, #120] + ldr r3, .L1330 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1330 + str r2, [r3, #60] + ldr r3, .L1330 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1330 + ldr r2, [r3, #100] + ldr r3, .L1330+4 + cmp r2, r3 + bne .L1327 + ldr r3, .L1330 + ldr r2, [r3, #468] + ldr r3, .L1330 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1330 + strb r3, [r2, #108] +.L1327: + ldr r3, .L1330 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1330 + str r2, [r3, #72] + ldr r2, .L1330 + ldr r3, .L1330 + str r3, [r2, #104] + ldr r3, .L1330 + ldr r2, [r3, #104] + ldr r3, .L1330 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1331: + .align 2 +.L1330: + .word GSU + .word GSU+56 + .size _Z9fx_sub_i9v, .-_Z9fx_sub_i9v + .align 2 + .type _Z10fx_sub_i10v, %function +_Z10fx_sub_i10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1336 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #10 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1336 + str r2, [r3, #124] + ldr r3, .L1336 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #10 + ldr r3, .L1336 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1336 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1336 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1336 + str r2, [r3, #120] + ldr r3, .L1336 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1336 + str r2, [r3, #60] + ldr r3, .L1336 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1336 + ldr r2, [r3, #100] + ldr r3, .L1336+4 + cmp r2, r3 + bne .L1333 + ldr r3, .L1336 + ldr r2, [r3, #468] + ldr r3, .L1336 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1336 + strb r3, [r2, #108] +.L1333: + ldr r3, .L1336 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1336 + str r2, [r3, #72] + ldr r2, .L1336 + ldr r3, .L1336 + str r3, [r2, #104] + ldr r3, .L1336 + ldr r2, [r3, #104] + ldr r3, .L1336 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1337: + .align 2 +.L1336: + .word GSU + .word GSU+56 + .size _Z10fx_sub_i10v, .-_Z10fx_sub_i10v + .align 2 + .type _Z10fx_sub_i11v, %function +_Z10fx_sub_i11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1342 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #11 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1342 + str r2, [r3, #124] + ldr r3, .L1342 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #11 + ldr r3, .L1342 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1342 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1342 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1342 + str r2, [r3, #120] + ldr r3, .L1342 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1342 + str r2, [r3, #60] + ldr r3, .L1342 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1342 + ldr r2, [r3, #100] + ldr r3, .L1342+4 + cmp r2, r3 + bne .L1339 + ldr r3, .L1342 + ldr r2, [r3, #468] + ldr r3, .L1342 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1342 + strb r3, [r2, #108] +.L1339: + ldr r3, .L1342 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1342 + str r2, [r3, #72] + ldr r2, .L1342 + ldr r3, .L1342 + str r3, [r2, #104] + ldr r3, .L1342 + ldr r2, [r3, #104] + ldr r3, .L1342 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1343: + .align 2 +.L1342: + .word GSU + .word GSU+56 + .size _Z10fx_sub_i11v, .-_Z10fx_sub_i11v + .align 2 + .type _Z10fx_sub_i12v, %function +_Z10fx_sub_i12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1348 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #12 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1348 + str r2, [r3, #124] + ldr r3, .L1348 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #12 + ldr r3, .L1348 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1348 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1348 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1348 + str r2, [r3, #120] + ldr r3, .L1348 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1348 + str r2, [r3, #60] + ldr r3, .L1348 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1348 + ldr r2, [r3, #100] + ldr r3, .L1348+4 + cmp r2, r3 + bne .L1345 + ldr r3, .L1348 + ldr r2, [r3, #468] + ldr r3, .L1348 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1348 + strb r3, [r2, #108] +.L1345: + ldr r3, .L1348 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1348 + str r2, [r3, #72] + ldr r2, .L1348 + ldr r3, .L1348 + str r3, [r2, #104] + ldr r3, .L1348 + ldr r2, [r3, #104] + ldr r3, .L1348 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1349: + .align 2 +.L1348: + .word GSU + .word GSU+56 + .size _Z10fx_sub_i12v, .-_Z10fx_sub_i12v + .align 2 + .type _Z10fx_sub_i13v, %function +_Z10fx_sub_i13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1354 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #13 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1354 + str r2, [r3, #124] + ldr r3, .L1354 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #13 + ldr r3, .L1354 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1354 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1354 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1354 + str r2, [r3, #120] + ldr r3, .L1354 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1354 + str r2, [r3, #60] + ldr r3, .L1354 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1354 + ldr r2, [r3, #100] + ldr r3, .L1354+4 + cmp r2, r3 + bne .L1351 + ldr r3, .L1354 + ldr r2, [r3, #468] + ldr r3, .L1354 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1354 + strb r3, [r2, #108] +.L1351: + ldr r3, .L1354 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1354 + str r2, [r3, #72] + ldr r2, .L1354 + ldr r3, .L1354 + str r3, [r2, #104] + ldr r3, .L1354 + ldr r2, [r3, #104] + ldr r3, .L1354 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1355: + .align 2 +.L1354: + .word GSU + .word GSU+56 + .size _Z10fx_sub_i13v, .-_Z10fx_sub_i13v + .align 2 + .type _Z10fx_sub_i14v, %function +_Z10fx_sub_i14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1360 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #14 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1360 + str r2, [r3, #124] + ldr r3, .L1360 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #14 + ldr r3, .L1360 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1360 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1360 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1360 + str r2, [r3, #120] + ldr r3, .L1360 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1360 + str r2, [r3, #60] + ldr r3, .L1360 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1360 + ldr r2, [r3, #100] + ldr r3, .L1360+4 + cmp r2, r3 + bne .L1357 + ldr r3, .L1360 + ldr r2, [r3, #468] + ldr r3, .L1360 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1360 + strb r3, [r2, #108] +.L1357: + ldr r3, .L1360 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1360 + str r2, [r3, #72] + ldr r2, .L1360 + ldr r3, .L1360 + str r3, [r2, #104] + ldr r3, .L1360 + ldr r2, [r3, #104] + ldr r3, .L1360 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1361: + .align 2 +.L1360: + .word GSU + .word GSU+56 + .size _Z10fx_sub_i14v, .-_Z10fx_sub_i14v + .align 2 + .type _Z10fx_sub_i15v, %function +_Z10fx_sub_i15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1366 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + sub r3, r3, #15 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1366 + str r2, [r3, #124] + ldr r3, .L1366 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r1, r3, #15 + ldr r3, .L1366 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1366 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1366 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1366 + str r2, [r3, #120] + ldr r3, .L1366 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1366 + str r2, [r3, #60] + ldr r3, .L1366 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L1366 + ldr r2, [r3, #100] + ldr r3, .L1366+4 + cmp r2, r3 + bne .L1363 + ldr r3, .L1366 + ldr r2, [r3, #468] + ldr r3, .L1366 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1366 + strb r3, [r2, #108] +.L1363: + ldr r3, .L1366 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1366 + str r2, [r3, #72] + ldr r2, .L1366 + ldr r3, .L1366 + str r3, [r2, #104] + ldr r3, .L1366 + ldr r2, [r3, #104] + ldr r3, .L1366 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1367: + .align 2 +.L1366: + .word GSU + .word GSU+56 + .size _Z10fx_sub_i15v, .-_Z10fx_sub_i15v + .align 2 + .type _Z9fx_cmp_r0v, %function +_Z9fx_cmp_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1370 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1370 + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1370 + str r2, [r3, #124] + ldr r3, .L1370 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1370 + ldr r3, [r3, #0] + eor r1, r2, r3 + ldr r3, .L1370 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1370 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1370 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1370 + str r2, [r3, #120] + ldr r3, .L1370 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1370 + str r2, [r3, #60] + ldr r3, .L1370 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1370 + str r2, [r3, #72] + ldr r2, .L1370 + ldr r3, .L1370 + str r3, [r2, #104] + ldr r3, .L1370 + ldr r2, [r3, #104] + ldr r3, .L1370 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1371: + .align 2 +.L1370: + .word GSU + .size _Z9fx_cmp_r0v, .-_Z9fx_cmp_r0v + .align 2 + .type _Z9fx_cmp_r1v, %function +_Z9fx_cmp_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1374 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1374 + ldr r3, [r3, #4] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1374 + str r2, [r3, #124] + ldr r3, .L1374 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1374 + ldr r3, [r3, #4] + eor r1, r2, r3 + ldr r3, .L1374 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1374 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1374 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1374 + str r2, [r3, #120] + ldr r3, .L1374 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1374 + str r2, [r3, #60] + ldr r3, .L1374 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1374 + str r2, [r3, #72] + ldr r2, .L1374 + ldr r3, .L1374 + str r3, [r2, #104] + ldr r3, .L1374 + ldr r2, [r3, #104] + ldr r3, .L1374 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1375: + .align 2 +.L1374: + .word GSU + .size _Z9fx_cmp_r1v, .-_Z9fx_cmp_r1v + .align 2 + .type _Z9fx_cmp_r2v, %function +_Z9fx_cmp_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1378 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1378 + ldr r3, [r3, #8] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1378 + str r2, [r3, #124] + ldr r3, .L1378 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1378 + ldr r3, [r3, #8] + eor r1, r2, r3 + ldr r3, .L1378 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1378 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1378 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1378 + str r2, [r3, #120] + ldr r3, .L1378 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1378 + str r2, [r3, #60] + ldr r3, .L1378 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1378 + str r2, [r3, #72] + ldr r2, .L1378 + ldr r3, .L1378 + str r3, [r2, #104] + ldr r3, .L1378 + ldr r2, [r3, #104] + ldr r3, .L1378 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1379: + .align 2 +.L1378: + .word GSU + .size _Z9fx_cmp_r2v, .-_Z9fx_cmp_r2v + .align 2 + .type _Z9fx_cmp_r3v, %function +_Z9fx_cmp_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1382 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1382 + ldr r3, [r3, #12] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1382 + str r2, [r3, #124] + ldr r3, .L1382 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1382 + ldr r3, [r3, #12] + eor r1, r2, r3 + ldr r3, .L1382 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1382 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1382 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1382 + str r2, [r3, #120] + ldr r3, .L1382 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1382 + str r2, [r3, #60] + ldr r3, .L1382 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1382 + str r2, [r3, #72] + ldr r2, .L1382 + ldr r3, .L1382 + str r3, [r2, #104] + ldr r3, .L1382 + ldr r2, [r3, #104] + ldr r3, .L1382 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1383: + .align 2 +.L1382: + .word GSU + .size _Z9fx_cmp_r3v, .-_Z9fx_cmp_r3v + .align 2 + .type _Z9fx_cmp_r4v, %function +_Z9fx_cmp_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1386 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1386 + ldr r3, [r3, #16] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1386 + str r2, [r3, #124] + ldr r3, .L1386 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1386 + ldr r3, [r3, #16] + eor r1, r2, r3 + ldr r3, .L1386 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1386 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1386 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1386 + str r2, [r3, #120] + ldr r3, .L1386 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1386 + str r2, [r3, #60] + ldr r3, .L1386 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1386 + str r2, [r3, #72] + ldr r2, .L1386 + ldr r3, .L1386 + str r3, [r2, #104] + ldr r3, .L1386 + ldr r2, [r3, #104] + ldr r3, .L1386 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1387: + .align 2 +.L1386: + .word GSU + .size _Z9fx_cmp_r4v, .-_Z9fx_cmp_r4v + .align 2 + .type _Z9fx_cmp_r5v, %function +_Z9fx_cmp_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1390 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1390 + ldr r3, [r3, #20] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1390 + str r2, [r3, #124] + ldr r3, .L1390 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1390 + ldr r3, [r3, #20] + eor r1, r2, r3 + ldr r3, .L1390 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1390 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1390 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1390 + str r2, [r3, #120] + ldr r3, .L1390 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1390 + str r2, [r3, #60] + ldr r3, .L1390 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1390 + str r2, [r3, #72] + ldr r2, .L1390 + ldr r3, .L1390 + str r3, [r2, #104] + ldr r3, .L1390 + ldr r2, [r3, #104] + ldr r3, .L1390 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1391: + .align 2 +.L1390: + .word GSU + .size _Z9fx_cmp_r5v, .-_Z9fx_cmp_r5v + .align 2 + .type _Z9fx_cmp_r6v, %function +_Z9fx_cmp_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1394 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1394 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1394 + str r2, [r3, #124] + ldr r3, .L1394 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1394 + ldr r3, [r3, #24] + eor r1, r2, r3 + ldr r3, .L1394 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1394 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1394 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1394 + str r2, [r3, #120] + ldr r3, .L1394 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1394 + str r2, [r3, #60] + ldr r3, .L1394 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1394 + str r2, [r3, #72] + ldr r2, .L1394 + ldr r3, .L1394 + str r3, [r2, #104] + ldr r3, .L1394 + ldr r2, [r3, #104] + ldr r3, .L1394 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1395: + .align 2 +.L1394: + .word GSU + .size _Z9fx_cmp_r6v, .-_Z9fx_cmp_r6v + .align 2 + .type _Z9fx_cmp_r7v, %function +_Z9fx_cmp_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1398 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1398 + ldr r3, [r3, #28] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1398 + str r2, [r3, #124] + ldr r3, .L1398 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1398 + ldr r3, [r3, #28] + eor r1, r2, r3 + ldr r3, .L1398 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1398 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1398 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1398 + str r2, [r3, #120] + ldr r3, .L1398 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1398 + str r2, [r3, #60] + ldr r3, .L1398 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1398 + str r2, [r3, #72] + ldr r2, .L1398 + ldr r3, .L1398 + str r3, [r2, #104] + ldr r3, .L1398 + ldr r2, [r3, #104] + ldr r3, .L1398 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1399: + .align 2 +.L1398: + .word GSU + .size _Z9fx_cmp_r7v, .-_Z9fx_cmp_r7v + .align 2 + .type _Z9fx_cmp_r8v, %function +_Z9fx_cmp_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1402 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1402 + ldr r3, [r3, #32] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1402 + str r2, [r3, #124] + ldr r3, .L1402 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1402 + ldr r3, [r3, #32] + eor r1, r2, r3 + ldr r3, .L1402 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1402 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1402 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1402 + str r2, [r3, #120] + ldr r3, .L1402 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1402 + str r2, [r3, #60] + ldr r3, .L1402 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1402 + str r2, [r3, #72] + ldr r2, .L1402 + ldr r3, .L1402 + str r3, [r2, #104] + ldr r3, .L1402 + ldr r2, [r3, #104] + ldr r3, .L1402 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1403: + .align 2 +.L1402: + .word GSU + .size _Z9fx_cmp_r8v, .-_Z9fx_cmp_r8v + .align 2 + .type _Z9fx_cmp_r9v, %function +_Z9fx_cmp_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1406 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1406 + ldr r3, [r3, #36] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1406 + str r2, [r3, #124] + ldr r3, .L1406 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1406 + ldr r3, [r3, #36] + eor r1, r2, r3 + ldr r3, .L1406 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1406 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1406 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1406 + str r2, [r3, #120] + ldr r3, .L1406 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1406 + str r2, [r3, #60] + ldr r3, .L1406 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1406 + str r2, [r3, #72] + ldr r2, .L1406 + ldr r3, .L1406 + str r3, [r2, #104] + ldr r3, .L1406 + ldr r2, [r3, #104] + ldr r3, .L1406 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1407: + .align 2 +.L1406: + .word GSU + .size _Z9fx_cmp_r9v, .-_Z9fx_cmp_r9v + .align 2 + .type _Z10fx_cmp_r10v, %function +_Z10fx_cmp_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1410 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1410 + ldr r3, [r3, #40] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1410 + str r2, [r3, #124] + ldr r3, .L1410 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1410 + ldr r3, [r3, #40] + eor r1, r2, r3 + ldr r3, .L1410 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1410 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1410 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1410 + str r2, [r3, #120] + ldr r3, .L1410 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1410 + str r2, [r3, #60] + ldr r3, .L1410 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1410 + str r2, [r3, #72] + ldr r2, .L1410 + ldr r3, .L1410 + str r3, [r2, #104] + ldr r3, .L1410 + ldr r2, [r3, #104] + ldr r3, .L1410 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1411: + .align 2 +.L1410: + .word GSU + .size _Z10fx_cmp_r10v, .-_Z10fx_cmp_r10v + .align 2 + .type _Z10fx_cmp_r11v, %function +_Z10fx_cmp_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1414 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1414 + ldr r3, [r3, #44] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1414 + str r2, [r3, #124] + ldr r3, .L1414 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1414 + ldr r3, [r3, #44] + eor r1, r2, r3 + ldr r3, .L1414 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1414 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1414 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1414 + str r2, [r3, #120] + ldr r3, .L1414 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1414 + str r2, [r3, #60] + ldr r3, .L1414 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1414 + str r2, [r3, #72] + ldr r2, .L1414 + ldr r3, .L1414 + str r3, [r2, #104] + ldr r3, .L1414 + ldr r2, [r3, #104] + ldr r3, .L1414 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1415: + .align 2 +.L1414: + .word GSU + .size _Z10fx_cmp_r11v, .-_Z10fx_cmp_r11v + .align 2 + .type _Z10fx_cmp_r12v, %function +_Z10fx_cmp_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1418 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1418 + ldr r3, [r3, #48] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1418 + str r2, [r3, #124] + ldr r3, .L1418 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1418 + ldr r3, [r3, #48] + eor r1, r2, r3 + ldr r3, .L1418 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1418 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1418 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1418 + str r2, [r3, #120] + ldr r3, .L1418 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1418 + str r2, [r3, #60] + ldr r3, .L1418 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1418 + str r2, [r3, #72] + ldr r2, .L1418 + ldr r3, .L1418 + str r3, [r2, #104] + ldr r3, .L1418 + ldr r2, [r3, #104] + ldr r3, .L1418 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1419: + .align 2 +.L1418: + .word GSU + .size _Z10fx_cmp_r12v, .-_Z10fx_cmp_r12v + .align 2 + .type _Z10fx_cmp_r13v, %function +_Z10fx_cmp_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1422 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1422 + ldr r3, [r3, #52] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1422 + str r2, [r3, #124] + ldr r3, .L1422 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1422 + ldr r3, [r3, #52] + eor r1, r2, r3 + ldr r3, .L1422 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1422 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1422 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1422 + str r2, [r3, #120] + ldr r3, .L1422 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1422 + str r2, [r3, #60] + ldr r3, .L1422 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1422 + str r2, [r3, #72] + ldr r2, .L1422 + ldr r3, .L1422 + str r3, [r2, #104] + ldr r3, .L1422 + ldr r2, [r3, #104] + ldr r3, .L1422 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1423: + .align 2 +.L1422: + .word GSU + .size _Z10fx_cmp_r13v, .-_Z10fx_cmp_r13v + .align 2 + .type _Z10fx_cmp_r14v, %function +_Z10fx_cmp_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1426 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1426 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1426 + str r2, [r3, #124] + ldr r3, .L1426 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1426 + ldr r3, [r3, #56] + eor r1, r2, r3 + ldr r3, .L1426 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1426 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1426 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1426 + str r2, [r3, #120] + ldr r3, .L1426 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1426 + str r2, [r3, #60] + ldr r3, .L1426 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1426 + str r2, [r3, #72] + ldr r2, .L1426 + ldr r3, .L1426 + str r3, [r2, #104] + ldr r3, .L1426 + ldr r2, [r3, #104] + ldr r3, .L1426 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1427: + .align 2 +.L1426: + .word GSU + .size _Z10fx_cmp_r14v, .-_Z10fx_cmp_r14v + .align 2 + .type _Z10fx_cmp_r15v, %function +_Z10fx_cmp_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1430 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L1430 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + rsb r3, r3, r2 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mvn r3, r3 + mov r2, r3, lsr #31 + ldr r3, .L1430 + str r2, [r3, #124] + ldr r3, .L1430 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1430 + ldr r3, [r3, #60] + eor r1, r2, r3 + ldr r3, .L1430 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, [fp, #-16] + eor r3, r2, r3 + and r3, r1, r3 + and r2, r3, #32768 + ldr r3, .L1430 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1430 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1430 + str r2, [r3, #120] + ldr r3, .L1430 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1430 + str r2, [r3, #60] + ldr r3, .L1430 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1430 + str r2, [r3, #72] + ldr r2, .L1430 + ldr r3, .L1430 + str r3, [r2, #104] + ldr r3, .L1430 + ldr r2, [r3, #104] + ldr r3, .L1430 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1431: + .align 2 +.L1430: + .word GSU + .size _Z10fx_cmp_r15v, .-_Z10fx_cmp_r15v + .align 2 + .type _Z8fx_mergev, %function +_Z8fx_mergev: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1436 + ldr r3, [r3, #28] + and r2, r3, #65280 + ldr r3, .L1436 + ldr r3, [r3, #32] + and r3, r3, #65280 + mov r3, r3, lsr #8 + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1436 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1436 + str r2, [r3, #60] + ldr r3, .L1436 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, [fp, #-16] + ldr r3, .L1436+4 + and r3, r2, r3 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L1436 + str r2, [r3, #128] + ldr r2, [fp, #-16] + ldr r3, .L1436+8 + and r3, r2, r3 + cmp r3, #0 + movne r2, #0 + moveq r2, #1 + ldr r3, .L1436 + str r2, [r3, #120] + ldr r3, [fp, #-16] + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r2, r3 + and r2, r3, #32768 + ldr r3, .L1436 + str r2, [r3, #116] + ldr r2, [fp, #-16] + ldr r3, .L1436+12 + and r3, r2, r3 + cmp r3, #0 + moveq r2, #0 + movne r2, #1 + ldr r3, .L1436 + str r2, [r3, #124] + ldr r3, .L1436 + ldr r2, [r3, #100] + ldr r3, .L1436+16 + cmp r2, r3 + bne .L1433 + ldr r3, .L1436 + ldr r2, [r3, #468] + ldr r3, .L1436 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1436 + strb r3, [r2, #108] +.L1433: + ldr r3, .L1436 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1436 + str r2, [r3, #72] + ldr r2, .L1436 + ldr r3, .L1436 + str r3, [r2, #104] + ldr r3, .L1436 + ldr r2, [r3, #104] + ldr r3, .L1436 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1437: + .align 2 +.L1436: + .word GSU + .word 49344 + .word 61680 + .word 57568 + .word GSU+56 + .size _Z8fx_mergev, .-_Z8fx_mergev + .align 2 + .type _Z9fx_and_r1v, %function +_Z9fx_and_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1442 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1442 + ldr r3, [r3, #4] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1442 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1442 + str r2, [r3, #60] + ldr r3, .L1442 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1442 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1442 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1442 + ldr r2, [r3, #100] + ldr r3, .L1442+4 + cmp r2, r3 + bne .L1439 + ldr r3, .L1442 + ldr r2, [r3, #468] + ldr r3, .L1442 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1442 + strb r3, [r2, #108] +.L1439: + ldr r3, .L1442 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1442 + str r2, [r3, #72] + ldr r2, .L1442 + ldr r3, .L1442 + str r3, [r2, #104] + ldr r3, .L1442 + ldr r2, [r3, #104] + ldr r3, .L1442 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1443: + .align 2 +.L1442: + .word GSU + .word GSU+56 + .size _Z9fx_and_r1v, .-_Z9fx_and_r1v + .align 2 + .type _Z9fx_and_r2v, %function +_Z9fx_and_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1448 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1448 + ldr r3, [r3, #8] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1448 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1448 + str r2, [r3, #60] + ldr r3, .L1448 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1448 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1448 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1448 + ldr r2, [r3, #100] + ldr r3, .L1448+4 + cmp r2, r3 + bne .L1445 + ldr r3, .L1448 + ldr r2, [r3, #468] + ldr r3, .L1448 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1448 + strb r3, [r2, #108] +.L1445: + ldr r3, .L1448 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1448 + str r2, [r3, #72] + ldr r2, .L1448 + ldr r3, .L1448 + str r3, [r2, #104] + ldr r3, .L1448 + ldr r2, [r3, #104] + ldr r3, .L1448 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1449: + .align 2 +.L1448: + .word GSU + .word GSU+56 + .size _Z9fx_and_r2v, .-_Z9fx_and_r2v + .align 2 + .type _Z9fx_and_r3v, %function +_Z9fx_and_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1454 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1454 + ldr r3, [r3, #12] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1454 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1454 + str r2, [r3, #60] + ldr r3, .L1454 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1454 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1454 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1454 + ldr r2, [r3, #100] + ldr r3, .L1454+4 + cmp r2, r3 + bne .L1451 + ldr r3, .L1454 + ldr r2, [r3, #468] + ldr r3, .L1454 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1454 + strb r3, [r2, #108] +.L1451: + ldr r3, .L1454 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1454 + str r2, [r3, #72] + ldr r2, .L1454 + ldr r3, .L1454 + str r3, [r2, #104] + ldr r3, .L1454 + ldr r2, [r3, #104] + ldr r3, .L1454 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1455: + .align 2 +.L1454: + .word GSU + .word GSU+56 + .size _Z9fx_and_r3v, .-_Z9fx_and_r3v + .align 2 + .type _Z9fx_and_r4v, %function +_Z9fx_and_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1460 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1460 + ldr r3, [r3, #16] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1460 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1460 + str r2, [r3, #60] + ldr r3, .L1460 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1460 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1460 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1460 + ldr r2, [r3, #100] + ldr r3, .L1460+4 + cmp r2, r3 + bne .L1457 + ldr r3, .L1460 + ldr r2, [r3, #468] + ldr r3, .L1460 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1460 + strb r3, [r2, #108] +.L1457: + ldr r3, .L1460 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1460 + str r2, [r3, #72] + ldr r2, .L1460 + ldr r3, .L1460 + str r3, [r2, #104] + ldr r3, .L1460 + ldr r2, [r3, #104] + ldr r3, .L1460 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1461: + .align 2 +.L1460: + .word GSU + .word GSU+56 + .size _Z9fx_and_r4v, .-_Z9fx_and_r4v + .align 2 + .type _Z9fx_and_r5v, %function +_Z9fx_and_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1466 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1466 + ldr r3, [r3, #20] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1466 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1466 + str r2, [r3, #60] + ldr r3, .L1466 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1466 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1466 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1466 + ldr r2, [r3, #100] + ldr r3, .L1466+4 + cmp r2, r3 + bne .L1463 + ldr r3, .L1466 + ldr r2, [r3, #468] + ldr r3, .L1466 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1466 + strb r3, [r2, #108] +.L1463: + ldr r3, .L1466 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1466 + str r2, [r3, #72] + ldr r2, .L1466 + ldr r3, .L1466 + str r3, [r2, #104] + ldr r3, .L1466 + ldr r2, [r3, #104] + ldr r3, .L1466 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1467: + .align 2 +.L1466: + .word GSU + .word GSU+56 + .size _Z9fx_and_r5v, .-_Z9fx_and_r5v + .align 2 + .type _Z9fx_and_r6v, %function +_Z9fx_and_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1472 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1472 + ldr r3, [r3, #24] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1472 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1472 + str r2, [r3, #60] + ldr r3, .L1472 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1472 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1472 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1472 + ldr r2, [r3, #100] + ldr r3, .L1472+4 + cmp r2, r3 + bne .L1469 + ldr r3, .L1472 + ldr r2, [r3, #468] + ldr r3, .L1472 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1472 + strb r3, [r2, #108] +.L1469: + ldr r3, .L1472 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1472 + str r2, [r3, #72] + ldr r2, .L1472 + ldr r3, .L1472 + str r3, [r2, #104] + ldr r3, .L1472 + ldr r2, [r3, #104] + ldr r3, .L1472 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1473: + .align 2 +.L1472: + .word GSU + .word GSU+56 + .size _Z9fx_and_r6v, .-_Z9fx_and_r6v + .align 2 + .type _Z9fx_and_r7v, %function +_Z9fx_and_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1478 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1478 + ldr r3, [r3, #28] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1478 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1478 + str r2, [r3, #60] + ldr r3, .L1478 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1478 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1478 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1478 + ldr r2, [r3, #100] + ldr r3, .L1478+4 + cmp r2, r3 + bne .L1475 + ldr r3, .L1478 + ldr r2, [r3, #468] + ldr r3, .L1478 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1478 + strb r3, [r2, #108] +.L1475: + ldr r3, .L1478 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1478 + str r2, [r3, #72] + ldr r2, .L1478 + ldr r3, .L1478 + str r3, [r2, #104] + ldr r3, .L1478 + ldr r2, [r3, #104] + ldr r3, .L1478 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1479: + .align 2 +.L1478: + .word GSU + .word GSU+56 + .size _Z9fx_and_r7v, .-_Z9fx_and_r7v + .align 2 + .type _Z9fx_and_r8v, %function +_Z9fx_and_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1484 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1484 + ldr r3, [r3, #32] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1484 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1484 + str r2, [r3, #60] + ldr r3, .L1484 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1484 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1484 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1484 + ldr r2, [r3, #100] + ldr r3, .L1484+4 + cmp r2, r3 + bne .L1481 + ldr r3, .L1484 + ldr r2, [r3, #468] + ldr r3, .L1484 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1484 + strb r3, [r2, #108] +.L1481: + ldr r3, .L1484 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1484 + str r2, [r3, #72] + ldr r2, .L1484 + ldr r3, .L1484 + str r3, [r2, #104] + ldr r3, .L1484 + ldr r2, [r3, #104] + ldr r3, .L1484 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1485: + .align 2 +.L1484: + .word GSU + .word GSU+56 + .size _Z9fx_and_r8v, .-_Z9fx_and_r8v + .align 2 + .type _Z9fx_and_r9v, %function +_Z9fx_and_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1490 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1490 + ldr r3, [r3, #36] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1490 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1490 + str r2, [r3, #60] + ldr r3, .L1490 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1490 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1490 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1490 + ldr r2, [r3, #100] + ldr r3, .L1490+4 + cmp r2, r3 + bne .L1487 + ldr r3, .L1490 + ldr r2, [r3, #468] + ldr r3, .L1490 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1490 + strb r3, [r2, #108] +.L1487: + ldr r3, .L1490 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1490 + str r2, [r3, #72] + ldr r2, .L1490 + ldr r3, .L1490 + str r3, [r2, #104] + ldr r3, .L1490 + ldr r2, [r3, #104] + ldr r3, .L1490 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1491: + .align 2 +.L1490: + .word GSU + .word GSU+56 + .size _Z9fx_and_r9v, .-_Z9fx_and_r9v + .align 2 + .type _Z10fx_and_r10v, %function +_Z10fx_and_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1496 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1496 + ldr r3, [r3, #40] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1496 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1496 + str r2, [r3, #60] + ldr r3, .L1496 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1496 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1496 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1496 + ldr r2, [r3, #100] + ldr r3, .L1496+4 + cmp r2, r3 + bne .L1493 + ldr r3, .L1496 + ldr r2, [r3, #468] + ldr r3, .L1496 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1496 + strb r3, [r2, #108] +.L1493: + ldr r3, .L1496 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1496 + str r2, [r3, #72] + ldr r2, .L1496 + ldr r3, .L1496 + str r3, [r2, #104] + ldr r3, .L1496 + ldr r2, [r3, #104] + ldr r3, .L1496 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1497: + .align 2 +.L1496: + .word GSU + .word GSU+56 + .size _Z10fx_and_r10v, .-_Z10fx_and_r10v + .align 2 + .type _Z10fx_and_r11v, %function +_Z10fx_and_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1502 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1502 + ldr r3, [r3, #44] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1502 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1502 + str r2, [r3, #60] + ldr r3, .L1502 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1502 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1502 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1502 + ldr r2, [r3, #100] + ldr r3, .L1502+4 + cmp r2, r3 + bne .L1499 + ldr r3, .L1502 + ldr r2, [r3, #468] + ldr r3, .L1502 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1502 + strb r3, [r2, #108] +.L1499: + ldr r3, .L1502 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1502 + str r2, [r3, #72] + ldr r2, .L1502 + ldr r3, .L1502 + str r3, [r2, #104] + ldr r3, .L1502 + ldr r2, [r3, #104] + ldr r3, .L1502 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1503: + .align 2 +.L1502: + .word GSU + .word GSU+56 + .size _Z10fx_and_r11v, .-_Z10fx_and_r11v + .align 2 + .type _Z10fx_and_r12v, %function +_Z10fx_and_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1508 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1508 + ldr r3, [r3, #48] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1508 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1508 + str r2, [r3, #60] + ldr r3, .L1508 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1508 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1508 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1508 + ldr r2, [r3, #100] + ldr r3, .L1508+4 + cmp r2, r3 + bne .L1505 + ldr r3, .L1508 + ldr r2, [r3, #468] + ldr r3, .L1508 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1508 + strb r3, [r2, #108] +.L1505: + ldr r3, .L1508 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1508 + str r2, [r3, #72] + ldr r2, .L1508 + ldr r3, .L1508 + str r3, [r2, #104] + ldr r3, .L1508 + ldr r2, [r3, #104] + ldr r3, .L1508 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1509: + .align 2 +.L1508: + .word GSU + .word GSU+56 + .size _Z10fx_and_r12v, .-_Z10fx_and_r12v + .align 2 + .type _Z10fx_and_r13v, %function +_Z10fx_and_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1514 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1514 + ldr r3, [r3, #52] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1514 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1514 + str r2, [r3, #60] + ldr r3, .L1514 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1514 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1514 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1514 + ldr r2, [r3, #100] + ldr r3, .L1514+4 + cmp r2, r3 + bne .L1511 + ldr r3, .L1514 + ldr r2, [r3, #468] + ldr r3, .L1514 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1514 + strb r3, [r2, #108] +.L1511: + ldr r3, .L1514 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1514 + str r2, [r3, #72] + ldr r2, .L1514 + ldr r3, .L1514 + str r3, [r2, #104] + ldr r3, .L1514 + ldr r2, [r3, #104] + ldr r3, .L1514 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1515: + .align 2 +.L1514: + .word GSU + .word GSU+56 + .size _Z10fx_and_r13v, .-_Z10fx_and_r13v + .align 2 + .type _Z10fx_and_r14v, %function +_Z10fx_and_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1520 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1520 + ldr r3, [r3, #56] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1520 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1520 + str r2, [r3, #60] + ldr r3, .L1520 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1520 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1520 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1520 + ldr r2, [r3, #100] + ldr r3, .L1520+4 + cmp r2, r3 + bne .L1517 + ldr r3, .L1520 + ldr r2, [r3, #468] + ldr r3, .L1520 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1520 + strb r3, [r2, #108] +.L1517: + ldr r3, .L1520 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1520 + str r2, [r3, #72] + ldr r2, .L1520 + ldr r3, .L1520 + str r3, [r2, #104] + ldr r3, .L1520 + ldr r2, [r3, #104] + ldr r3, .L1520 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1521: + .align 2 +.L1520: + .word GSU + .word GSU+56 + .size _Z10fx_and_r14v, .-_Z10fx_and_r14v + .align 2 + .type _Z10fx_and_r15v, %function +_Z10fx_and_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1526 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1526 + ldr r3, [r3, #60] + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1526 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1526 + str r2, [r3, #60] + ldr r3, .L1526 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1526 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1526 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1526 + ldr r2, [r3, #100] + ldr r3, .L1526+4 + cmp r2, r3 + bne .L1523 + ldr r3, .L1526 + ldr r2, [r3, #468] + ldr r3, .L1526 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1526 + strb r3, [r2, #108] +.L1523: + ldr r3, .L1526 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1526 + str r2, [r3, #72] + ldr r2, .L1526 + ldr r3, .L1526 + str r3, [r2, #104] + ldr r3, .L1526 + ldr r2, [r3, #104] + ldr r3, .L1526 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1527: + .align 2 +.L1526: + .word GSU + .word GSU+56 + .size _Z10fx_and_r15v, .-_Z10fx_and_r15v + .align 2 + .type _Z9fx_bic_r1v, %function +_Z9fx_bic_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1532 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1532 + ldr r3, [r3, #4] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1532 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1532 + str r2, [r3, #60] + ldr r3, .L1532 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1532 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1532 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1532 + ldr r2, [r3, #100] + ldr r3, .L1532+4 + cmp r2, r3 + bne .L1529 + ldr r3, .L1532 + ldr r2, [r3, #468] + ldr r3, .L1532 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1532 + strb r3, [r2, #108] +.L1529: + ldr r3, .L1532 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1532 + str r2, [r3, #72] + ldr r2, .L1532 + ldr r3, .L1532 + str r3, [r2, #104] + ldr r3, .L1532 + ldr r2, [r3, #104] + ldr r3, .L1532 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1533: + .align 2 +.L1532: + .word GSU + .word GSU+56 + .size _Z9fx_bic_r1v, .-_Z9fx_bic_r1v + .align 2 + .type _Z9fx_bic_r2v, %function +_Z9fx_bic_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1538 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1538 + ldr r3, [r3, #8] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1538 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1538 + str r2, [r3, #60] + ldr r3, .L1538 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1538 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1538 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1538 + ldr r2, [r3, #100] + ldr r3, .L1538+4 + cmp r2, r3 + bne .L1535 + ldr r3, .L1538 + ldr r2, [r3, #468] + ldr r3, .L1538 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1538 + strb r3, [r2, #108] +.L1535: + ldr r3, .L1538 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1538 + str r2, [r3, #72] + ldr r2, .L1538 + ldr r3, .L1538 + str r3, [r2, #104] + ldr r3, .L1538 + ldr r2, [r3, #104] + ldr r3, .L1538 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1539: + .align 2 +.L1538: + .word GSU + .word GSU+56 + .size _Z9fx_bic_r2v, .-_Z9fx_bic_r2v + .align 2 + .type _Z9fx_bic_r3v, %function +_Z9fx_bic_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1544 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1544 + ldr r3, [r3, #12] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1544 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1544 + str r2, [r3, #60] + ldr r3, .L1544 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1544 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1544 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1544 + ldr r2, [r3, #100] + ldr r3, .L1544+4 + cmp r2, r3 + bne .L1541 + ldr r3, .L1544 + ldr r2, [r3, #468] + ldr r3, .L1544 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1544 + strb r3, [r2, #108] +.L1541: + ldr r3, .L1544 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1544 + str r2, [r3, #72] + ldr r2, .L1544 + ldr r3, .L1544 + str r3, [r2, #104] + ldr r3, .L1544 + ldr r2, [r3, #104] + ldr r3, .L1544 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1545: + .align 2 +.L1544: + .word GSU + .word GSU+56 + .size _Z9fx_bic_r3v, .-_Z9fx_bic_r3v + .align 2 + .type _Z9fx_bic_r4v, %function +_Z9fx_bic_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1550 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1550 + ldr r3, [r3, #16] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1550 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1550 + str r2, [r3, #60] + ldr r3, .L1550 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1550 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1550 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1550 + ldr r2, [r3, #100] + ldr r3, .L1550+4 + cmp r2, r3 + bne .L1547 + ldr r3, .L1550 + ldr r2, [r3, #468] + ldr r3, .L1550 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1550 + strb r3, [r2, #108] +.L1547: + ldr r3, .L1550 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1550 + str r2, [r3, #72] + ldr r2, .L1550 + ldr r3, .L1550 + str r3, [r2, #104] + ldr r3, .L1550 + ldr r2, [r3, #104] + ldr r3, .L1550 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1551: + .align 2 +.L1550: + .word GSU + .word GSU+56 + .size _Z9fx_bic_r4v, .-_Z9fx_bic_r4v + .align 2 + .type _Z9fx_bic_r5v, %function +_Z9fx_bic_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1556 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1556 + ldr r3, [r3, #20] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1556 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1556 + str r2, [r3, #60] + ldr r3, .L1556 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1556 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1556 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1556 + ldr r2, [r3, #100] + ldr r3, .L1556+4 + cmp r2, r3 + bne .L1553 + ldr r3, .L1556 + ldr r2, [r3, #468] + ldr r3, .L1556 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1556 + strb r3, [r2, #108] +.L1553: + ldr r3, .L1556 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1556 + str r2, [r3, #72] + ldr r2, .L1556 + ldr r3, .L1556 + str r3, [r2, #104] + ldr r3, .L1556 + ldr r2, [r3, #104] + ldr r3, .L1556 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1557: + .align 2 +.L1556: + .word GSU + .word GSU+56 + .size _Z9fx_bic_r5v, .-_Z9fx_bic_r5v + .align 2 + .type _Z9fx_bic_r6v, %function +_Z9fx_bic_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1562 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1562 + ldr r3, [r3, #24] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1562 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1562 + str r2, [r3, #60] + ldr r3, .L1562 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1562 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1562 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1562 + ldr r2, [r3, #100] + ldr r3, .L1562+4 + cmp r2, r3 + bne .L1559 + ldr r3, .L1562 + ldr r2, [r3, #468] + ldr r3, .L1562 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1562 + strb r3, [r2, #108] +.L1559: + ldr r3, .L1562 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1562 + str r2, [r3, #72] + ldr r2, .L1562 + ldr r3, .L1562 + str r3, [r2, #104] + ldr r3, .L1562 + ldr r2, [r3, #104] + ldr r3, .L1562 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1563: + .align 2 +.L1562: + .word GSU + .word GSU+56 + .size _Z9fx_bic_r6v, .-_Z9fx_bic_r6v + .align 2 + .type _Z9fx_bic_r7v, %function +_Z9fx_bic_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1568 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1568 + ldr r3, [r3, #28] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1568 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1568 + str r2, [r3, #60] + ldr r3, .L1568 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1568 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1568 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1568 + ldr r2, [r3, #100] + ldr r3, .L1568+4 + cmp r2, r3 + bne .L1565 + ldr r3, .L1568 + ldr r2, [r3, #468] + ldr r3, .L1568 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1568 + strb r3, [r2, #108] +.L1565: + ldr r3, .L1568 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1568 + str r2, [r3, #72] + ldr r2, .L1568 + ldr r3, .L1568 + str r3, [r2, #104] + ldr r3, .L1568 + ldr r2, [r3, #104] + ldr r3, .L1568 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1569: + .align 2 +.L1568: + .word GSU + .word GSU+56 + .size _Z9fx_bic_r7v, .-_Z9fx_bic_r7v + .align 2 + .type _Z9fx_bic_r8v, %function +_Z9fx_bic_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1574 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1574 + ldr r3, [r3, #32] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1574 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1574 + str r2, [r3, #60] + ldr r3, .L1574 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1574 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1574 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1574 + ldr r2, [r3, #100] + ldr r3, .L1574+4 + cmp r2, r3 + bne .L1571 + ldr r3, .L1574 + ldr r2, [r3, #468] + ldr r3, .L1574 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1574 + strb r3, [r2, #108] +.L1571: + ldr r3, .L1574 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1574 + str r2, [r3, #72] + ldr r2, .L1574 + ldr r3, .L1574 + str r3, [r2, #104] + ldr r3, .L1574 + ldr r2, [r3, #104] + ldr r3, .L1574 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1575: + .align 2 +.L1574: + .word GSU + .word GSU+56 + .size _Z9fx_bic_r8v, .-_Z9fx_bic_r8v + .align 2 + .type _Z9fx_bic_r9v, %function +_Z9fx_bic_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1580 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1580 + ldr r3, [r3, #36] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1580 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1580 + str r2, [r3, #60] + ldr r3, .L1580 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1580 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1580 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1580 + ldr r2, [r3, #100] + ldr r3, .L1580+4 + cmp r2, r3 + bne .L1577 + ldr r3, .L1580 + ldr r2, [r3, #468] + ldr r3, .L1580 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1580 + strb r3, [r2, #108] +.L1577: + ldr r3, .L1580 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1580 + str r2, [r3, #72] + ldr r2, .L1580 + ldr r3, .L1580 + str r3, [r2, #104] + ldr r3, .L1580 + ldr r2, [r3, #104] + ldr r3, .L1580 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1581: + .align 2 +.L1580: + .word GSU + .word GSU+56 + .size _Z9fx_bic_r9v, .-_Z9fx_bic_r9v + .align 2 + .type _Z10fx_bic_r10v, %function +_Z10fx_bic_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1586 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1586 + ldr r3, [r3, #40] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1586 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1586 + str r2, [r3, #60] + ldr r3, .L1586 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1586 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1586 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1586 + ldr r2, [r3, #100] + ldr r3, .L1586+4 + cmp r2, r3 + bne .L1583 + ldr r3, .L1586 + ldr r2, [r3, #468] + ldr r3, .L1586 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1586 + strb r3, [r2, #108] +.L1583: + ldr r3, .L1586 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1586 + str r2, [r3, #72] + ldr r2, .L1586 + ldr r3, .L1586 + str r3, [r2, #104] + ldr r3, .L1586 + ldr r2, [r3, #104] + ldr r3, .L1586 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1587: + .align 2 +.L1586: + .word GSU + .word GSU+56 + .size _Z10fx_bic_r10v, .-_Z10fx_bic_r10v + .align 2 + .type _Z10fx_bic_r11v, %function +_Z10fx_bic_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1592 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1592 + ldr r3, [r3, #44] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1592 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1592 + str r2, [r3, #60] + ldr r3, .L1592 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1592 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1592 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1592 + ldr r2, [r3, #100] + ldr r3, .L1592+4 + cmp r2, r3 + bne .L1589 + ldr r3, .L1592 + ldr r2, [r3, #468] + ldr r3, .L1592 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1592 + strb r3, [r2, #108] +.L1589: + ldr r3, .L1592 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1592 + str r2, [r3, #72] + ldr r2, .L1592 + ldr r3, .L1592 + str r3, [r2, #104] + ldr r3, .L1592 + ldr r2, [r3, #104] + ldr r3, .L1592 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1593: + .align 2 +.L1592: + .word GSU + .word GSU+56 + .size _Z10fx_bic_r11v, .-_Z10fx_bic_r11v + .align 2 + .type _Z10fx_bic_r12v, %function +_Z10fx_bic_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1598 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1598 + ldr r3, [r3, #48] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1598 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1598 + str r2, [r3, #60] + ldr r3, .L1598 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1598 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1598 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1598 + ldr r2, [r3, #100] + ldr r3, .L1598+4 + cmp r2, r3 + bne .L1595 + ldr r3, .L1598 + ldr r2, [r3, #468] + ldr r3, .L1598 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1598 + strb r3, [r2, #108] +.L1595: + ldr r3, .L1598 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1598 + str r2, [r3, #72] + ldr r2, .L1598 + ldr r3, .L1598 + str r3, [r2, #104] + ldr r3, .L1598 + ldr r2, [r3, #104] + ldr r3, .L1598 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1599: + .align 2 +.L1598: + .word GSU + .word GSU+56 + .size _Z10fx_bic_r12v, .-_Z10fx_bic_r12v + .align 2 + .type _Z10fx_bic_r13v, %function +_Z10fx_bic_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1604 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1604 + ldr r3, [r3, #52] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1604 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1604 + str r2, [r3, #60] + ldr r3, .L1604 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1604 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1604 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1604 + ldr r2, [r3, #100] + ldr r3, .L1604+4 + cmp r2, r3 + bne .L1601 + ldr r3, .L1604 + ldr r2, [r3, #468] + ldr r3, .L1604 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1604 + strb r3, [r2, #108] +.L1601: + ldr r3, .L1604 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1604 + str r2, [r3, #72] + ldr r2, .L1604 + ldr r3, .L1604 + str r3, [r2, #104] + ldr r3, .L1604 + ldr r2, [r3, #104] + ldr r3, .L1604 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1605: + .align 2 +.L1604: + .word GSU + .word GSU+56 + .size _Z10fx_bic_r13v, .-_Z10fx_bic_r13v + .align 2 + .type _Z10fx_bic_r14v, %function +_Z10fx_bic_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1610 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1610 + ldr r3, [r3, #56] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1610 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1610 + str r2, [r3, #60] + ldr r3, .L1610 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1610 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1610 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1610 + ldr r2, [r3, #100] + ldr r3, .L1610+4 + cmp r2, r3 + bne .L1607 + ldr r3, .L1610 + ldr r2, [r3, #468] + ldr r3, .L1610 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1610 + strb r3, [r2, #108] +.L1607: + ldr r3, .L1610 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1610 + str r2, [r3, #72] + ldr r2, .L1610 + ldr r3, .L1610 + str r3, [r2, #104] + ldr r3, .L1610 + ldr r2, [r3, #104] + ldr r3, .L1610 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1611: + .align 2 +.L1610: + .word GSU + .word GSU+56 + .size _Z10fx_bic_r14v, .-_Z10fx_bic_r14v + .align 2 + .type _Z10fx_bic_r15v, %function +_Z10fx_bic_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1616 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L1616 + ldr r3, [r3, #60] + mvn r3, r3 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1616 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1616 + str r2, [r3, #60] + ldr r3, .L1616 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1616 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1616 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1616 + ldr r2, [r3, #100] + ldr r3, .L1616+4 + cmp r2, r3 + bne .L1613 + ldr r3, .L1616 + ldr r2, [r3, #468] + ldr r3, .L1616 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1616 + strb r3, [r2, #108] +.L1613: + ldr r3, .L1616 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1616 + str r2, [r3, #72] + ldr r2, .L1616 + ldr r3, .L1616 + str r3, [r2, #104] + ldr r3, .L1616 + ldr r2, [r3, #104] + ldr r3, .L1616 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1617: + .align 2 +.L1616: + .word GSU + .word GSU+56 + .size _Z10fx_bic_r15v, .-_Z10fx_bic_r15v + .align 2 + .type _Z9fx_and_i1v, %function +_Z9fx_and_i1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1622 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #1 + str r3, [fp, #-16] + ldr r3, .L1622 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1622 + str r2, [r3, #60] + ldr r3, .L1622 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1622 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1622 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1622 + ldr r2, [r3, #100] + ldr r3, .L1622+4 + cmp r2, r3 + bne .L1619 + ldr r3, .L1622 + ldr r2, [r3, #468] + ldr r3, .L1622 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1622 + strb r3, [r2, #108] +.L1619: + ldr r3, .L1622 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1622 + str r2, [r3, #72] + ldr r2, .L1622 + ldr r3, .L1622 + str r3, [r2, #104] + ldr r3, .L1622 + ldr r2, [r3, #104] + ldr r3, .L1622 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1623: + .align 2 +.L1622: + .word GSU + .word GSU+56 + .size _Z9fx_and_i1v, .-_Z9fx_and_i1v + .align 2 + .type _Z9fx_and_i2v, %function +_Z9fx_and_i2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1628 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #2 + str r3, [fp, #-16] + ldr r3, .L1628 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1628 + str r2, [r3, #60] + ldr r3, .L1628 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1628 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1628 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1628 + ldr r2, [r3, #100] + ldr r3, .L1628+4 + cmp r2, r3 + bne .L1625 + ldr r3, .L1628 + ldr r2, [r3, #468] + ldr r3, .L1628 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1628 + strb r3, [r2, #108] +.L1625: + ldr r3, .L1628 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1628 + str r2, [r3, #72] + ldr r2, .L1628 + ldr r3, .L1628 + str r3, [r2, #104] + ldr r3, .L1628 + ldr r2, [r3, #104] + ldr r3, .L1628 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1629: + .align 2 +.L1628: + .word GSU + .word GSU+56 + .size _Z9fx_and_i2v, .-_Z9fx_and_i2v + .align 2 + .type _Z9fx_and_i3v, %function +_Z9fx_and_i3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1634 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #3 + str r3, [fp, #-16] + ldr r3, .L1634 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1634 + str r2, [r3, #60] + ldr r3, .L1634 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1634 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1634 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1634 + ldr r2, [r3, #100] + ldr r3, .L1634+4 + cmp r2, r3 + bne .L1631 + ldr r3, .L1634 + ldr r2, [r3, #468] + ldr r3, .L1634 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1634 + strb r3, [r2, #108] +.L1631: + ldr r3, .L1634 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1634 + str r2, [r3, #72] + ldr r2, .L1634 + ldr r3, .L1634 + str r3, [r2, #104] + ldr r3, .L1634 + ldr r2, [r3, #104] + ldr r3, .L1634 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1635: + .align 2 +.L1634: + .word GSU + .word GSU+56 + .size _Z9fx_and_i3v, .-_Z9fx_and_i3v + .align 2 + .type _Z9fx_and_i4v, %function +_Z9fx_and_i4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1640 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #4 + str r3, [fp, #-16] + ldr r3, .L1640 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1640 + str r2, [r3, #60] + ldr r3, .L1640 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1640 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1640 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1640 + ldr r2, [r3, #100] + ldr r3, .L1640+4 + cmp r2, r3 + bne .L1637 + ldr r3, .L1640 + ldr r2, [r3, #468] + ldr r3, .L1640 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1640 + strb r3, [r2, #108] +.L1637: + ldr r3, .L1640 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1640 + str r2, [r3, #72] + ldr r2, .L1640 + ldr r3, .L1640 + str r3, [r2, #104] + ldr r3, .L1640 + ldr r2, [r3, #104] + ldr r3, .L1640 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1641: + .align 2 +.L1640: + .word GSU + .word GSU+56 + .size _Z9fx_and_i4v, .-_Z9fx_and_i4v + .align 2 + .type _Z9fx_and_i5v, %function +_Z9fx_and_i5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1646 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #5 + str r3, [fp, #-16] + ldr r3, .L1646 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1646 + str r2, [r3, #60] + ldr r3, .L1646 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1646 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1646 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1646 + ldr r2, [r3, #100] + ldr r3, .L1646+4 + cmp r2, r3 + bne .L1643 + ldr r3, .L1646 + ldr r2, [r3, #468] + ldr r3, .L1646 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1646 + strb r3, [r2, #108] +.L1643: + ldr r3, .L1646 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1646 + str r2, [r3, #72] + ldr r2, .L1646 + ldr r3, .L1646 + str r3, [r2, #104] + ldr r3, .L1646 + ldr r2, [r3, #104] + ldr r3, .L1646 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1647: + .align 2 +.L1646: + .word GSU + .word GSU+56 + .size _Z9fx_and_i5v, .-_Z9fx_and_i5v + .align 2 + .type _Z9fx_and_i6v, %function +_Z9fx_and_i6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1652 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #6 + str r3, [fp, #-16] + ldr r3, .L1652 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1652 + str r2, [r3, #60] + ldr r3, .L1652 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1652 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1652 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1652 + ldr r2, [r3, #100] + ldr r3, .L1652+4 + cmp r2, r3 + bne .L1649 + ldr r3, .L1652 + ldr r2, [r3, #468] + ldr r3, .L1652 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1652 + strb r3, [r2, #108] +.L1649: + ldr r3, .L1652 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1652 + str r2, [r3, #72] + ldr r2, .L1652 + ldr r3, .L1652 + str r3, [r2, #104] + ldr r3, .L1652 + ldr r2, [r3, #104] + ldr r3, .L1652 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1653: + .align 2 +.L1652: + .word GSU + .word GSU+56 + .size _Z9fx_and_i6v, .-_Z9fx_and_i6v + .align 2 + .type _Z9fx_and_i7v, %function +_Z9fx_and_i7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1658 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #7 + str r3, [fp, #-16] + ldr r3, .L1658 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1658 + str r2, [r3, #60] + ldr r3, .L1658 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1658 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1658 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1658 + ldr r2, [r3, #100] + ldr r3, .L1658+4 + cmp r2, r3 + bne .L1655 + ldr r3, .L1658 + ldr r2, [r3, #468] + ldr r3, .L1658 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1658 + strb r3, [r2, #108] +.L1655: + ldr r3, .L1658 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1658 + str r2, [r3, #72] + ldr r2, .L1658 + ldr r3, .L1658 + str r3, [r2, #104] + ldr r3, .L1658 + ldr r2, [r3, #104] + ldr r3, .L1658 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1659: + .align 2 +.L1658: + .word GSU + .word GSU+56 + .size _Z9fx_and_i7v, .-_Z9fx_and_i7v + .align 2 + .type _Z9fx_and_i8v, %function +_Z9fx_and_i8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1664 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #8 + str r3, [fp, #-16] + ldr r3, .L1664 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1664 + str r2, [r3, #60] + ldr r3, .L1664 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1664 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1664 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1664 + ldr r2, [r3, #100] + ldr r3, .L1664+4 + cmp r2, r3 + bne .L1661 + ldr r3, .L1664 + ldr r2, [r3, #468] + ldr r3, .L1664 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1664 + strb r3, [r2, #108] +.L1661: + ldr r3, .L1664 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1664 + str r2, [r3, #72] + ldr r2, .L1664 + ldr r3, .L1664 + str r3, [r2, #104] + ldr r3, .L1664 + ldr r2, [r3, #104] + ldr r3, .L1664 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1665: + .align 2 +.L1664: + .word GSU + .word GSU+56 + .size _Z9fx_and_i8v, .-_Z9fx_and_i8v + .align 2 + .type _Z9fx_and_i9v, %function +_Z9fx_and_i9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1670 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #9 + str r3, [fp, #-16] + ldr r3, .L1670 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1670 + str r2, [r3, #60] + ldr r3, .L1670 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1670 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1670 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1670 + ldr r2, [r3, #100] + ldr r3, .L1670+4 + cmp r2, r3 + bne .L1667 + ldr r3, .L1670 + ldr r2, [r3, #468] + ldr r3, .L1670 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1670 + strb r3, [r2, #108] +.L1667: + ldr r3, .L1670 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1670 + str r2, [r3, #72] + ldr r2, .L1670 + ldr r3, .L1670 + str r3, [r2, #104] + ldr r3, .L1670 + ldr r2, [r3, #104] + ldr r3, .L1670 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1671: + .align 2 +.L1670: + .word GSU + .word GSU+56 + .size _Z9fx_and_i9v, .-_Z9fx_and_i9v + .align 2 + .type _Z10fx_and_i10v, %function +_Z10fx_and_i10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1676 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #10 + str r3, [fp, #-16] + ldr r3, .L1676 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1676 + str r2, [r3, #60] + ldr r3, .L1676 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1676 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1676 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1676 + ldr r2, [r3, #100] + ldr r3, .L1676+4 + cmp r2, r3 + bne .L1673 + ldr r3, .L1676 + ldr r2, [r3, #468] + ldr r3, .L1676 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1676 + strb r3, [r2, #108] +.L1673: + ldr r3, .L1676 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1676 + str r2, [r3, #72] + ldr r2, .L1676 + ldr r3, .L1676 + str r3, [r2, #104] + ldr r3, .L1676 + ldr r2, [r3, #104] + ldr r3, .L1676 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1677: + .align 2 +.L1676: + .word GSU + .word GSU+56 + .size _Z10fx_and_i10v, .-_Z10fx_and_i10v + .align 2 + .type _Z10fx_and_i11v, %function +_Z10fx_and_i11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1682 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #11 + str r3, [fp, #-16] + ldr r3, .L1682 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1682 + str r2, [r3, #60] + ldr r3, .L1682 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1682 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1682 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1682 + ldr r2, [r3, #100] + ldr r3, .L1682+4 + cmp r2, r3 + bne .L1679 + ldr r3, .L1682 + ldr r2, [r3, #468] + ldr r3, .L1682 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1682 + strb r3, [r2, #108] +.L1679: + ldr r3, .L1682 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1682 + str r2, [r3, #72] + ldr r2, .L1682 + ldr r3, .L1682 + str r3, [r2, #104] + ldr r3, .L1682 + ldr r2, [r3, #104] + ldr r3, .L1682 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1683: + .align 2 +.L1682: + .word GSU + .word GSU+56 + .size _Z10fx_and_i11v, .-_Z10fx_and_i11v + .align 2 + .type _Z10fx_and_i12v, %function +_Z10fx_and_i12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1688 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #12 + str r3, [fp, #-16] + ldr r3, .L1688 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1688 + str r2, [r3, #60] + ldr r3, .L1688 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1688 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1688 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1688 + ldr r2, [r3, #100] + ldr r3, .L1688+4 + cmp r2, r3 + bne .L1685 + ldr r3, .L1688 + ldr r2, [r3, #468] + ldr r3, .L1688 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1688 + strb r3, [r2, #108] +.L1685: + ldr r3, .L1688 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1688 + str r2, [r3, #72] + ldr r2, .L1688 + ldr r3, .L1688 + str r3, [r2, #104] + ldr r3, .L1688 + ldr r2, [r3, #104] + ldr r3, .L1688 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1689: + .align 2 +.L1688: + .word GSU + .word GSU+56 + .size _Z10fx_and_i12v, .-_Z10fx_and_i12v + .align 2 + .type _Z10fx_and_i13v, %function +_Z10fx_and_i13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1694 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #13 + str r3, [fp, #-16] + ldr r3, .L1694 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1694 + str r2, [r3, #60] + ldr r3, .L1694 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1694 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1694 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1694 + ldr r2, [r3, #100] + ldr r3, .L1694+4 + cmp r2, r3 + bne .L1691 + ldr r3, .L1694 + ldr r2, [r3, #468] + ldr r3, .L1694 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1694 + strb r3, [r2, #108] +.L1691: + ldr r3, .L1694 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1694 + str r2, [r3, #72] + ldr r2, .L1694 + ldr r3, .L1694 + str r3, [r2, #104] + ldr r3, .L1694 + ldr r2, [r3, #104] + ldr r3, .L1694 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1695: + .align 2 +.L1694: + .word GSU + .word GSU+56 + .size _Z10fx_and_i13v, .-_Z10fx_and_i13v + .align 2 + .type _Z10fx_and_i14v, %function +_Z10fx_and_i14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1700 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #14 + str r3, [fp, #-16] + ldr r3, .L1700 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1700 + str r2, [r3, #60] + ldr r3, .L1700 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1700 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1700 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1700 + ldr r2, [r3, #100] + ldr r3, .L1700+4 + cmp r2, r3 + bne .L1697 + ldr r3, .L1700 + ldr r2, [r3, #468] + ldr r3, .L1700 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1700 + strb r3, [r2, #108] +.L1697: + ldr r3, .L1700 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1700 + str r2, [r3, #72] + ldr r2, .L1700 + ldr r3, .L1700 + str r3, [r2, #104] + ldr r3, .L1700 + ldr r2, [r3, #104] + ldr r3, .L1700 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1701: + .align 2 +.L1700: + .word GSU + .word GSU+56 + .size _Z10fx_and_i14v, .-_Z10fx_and_i14v + .align 2 + .type _Z10fx_and_i15v, %function +_Z10fx_and_i15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1706 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #15 + str r3, [fp, #-16] + ldr r3, .L1706 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1706 + str r2, [r3, #60] + ldr r3, .L1706 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1706 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1706 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1706 + ldr r2, [r3, #100] + ldr r3, .L1706+4 + cmp r2, r3 + bne .L1703 + ldr r3, .L1706 + ldr r2, [r3, #468] + ldr r3, .L1706 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1706 + strb r3, [r2, #108] +.L1703: + ldr r3, .L1706 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1706 + str r2, [r3, #72] + ldr r2, .L1706 + ldr r3, .L1706 + str r3, [r2, #104] + ldr r3, .L1706 + ldr r2, [r3, #104] + ldr r3, .L1706 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1707: + .align 2 +.L1706: + .word GSU + .word GSU+56 + .size _Z10fx_and_i15v, .-_Z10fx_and_i15v + .align 2 + .type _Z9fx_bic_i1v, %function +_Z9fx_bic_i1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1712 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #1 + str r3, [fp, #-16] + ldr r3, .L1712 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1712 + str r2, [r3, #60] + ldr r3, .L1712 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1712 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1712 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1712 + ldr r2, [r3, #100] + ldr r3, .L1712+4 + cmp r2, r3 + bne .L1709 + ldr r3, .L1712 + ldr r2, [r3, #468] + ldr r3, .L1712 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1712 + strb r3, [r2, #108] +.L1709: + ldr r3, .L1712 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1712 + str r2, [r3, #72] + ldr r2, .L1712 + ldr r3, .L1712 + str r3, [r2, #104] + ldr r3, .L1712 + ldr r2, [r3, #104] + ldr r3, .L1712 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1713: + .align 2 +.L1712: + .word GSU + .word GSU+56 + .size _Z9fx_bic_i1v, .-_Z9fx_bic_i1v + .align 2 + .type _Z9fx_bic_i2v, %function +_Z9fx_bic_i2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1718 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #2 + str r3, [fp, #-16] + ldr r3, .L1718 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1718 + str r2, [r3, #60] + ldr r3, .L1718 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1718 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1718 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1718 + ldr r2, [r3, #100] + ldr r3, .L1718+4 + cmp r2, r3 + bne .L1715 + ldr r3, .L1718 + ldr r2, [r3, #468] + ldr r3, .L1718 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1718 + strb r3, [r2, #108] +.L1715: + ldr r3, .L1718 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1718 + str r2, [r3, #72] + ldr r2, .L1718 + ldr r3, .L1718 + str r3, [r2, #104] + ldr r3, .L1718 + ldr r2, [r3, #104] + ldr r3, .L1718 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1719: + .align 2 +.L1718: + .word GSU + .word GSU+56 + .size _Z9fx_bic_i2v, .-_Z9fx_bic_i2v + .align 2 + .type _Z9fx_bic_i3v, %function +_Z9fx_bic_i3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1724 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #3 + str r3, [fp, #-16] + ldr r3, .L1724 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1724 + str r2, [r3, #60] + ldr r3, .L1724 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1724 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1724 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1724 + ldr r2, [r3, #100] + ldr r3, .L1724+4 + cmp r2, r3 + bne .L1721 + ldr r3, .L1724 + ldr r2, [r3, #468] + ldr r3, .L1724 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1724 + strb r3, [r2, #108] +.L1721: + ldr r3, .L1724 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1724 + str r2, [r3, #72] + ldr r2, .L1724 + ldr r3, .L1724 + str r3, [r2, #104] + ldr r3, .L1724 + ldr r2, [r3, #104] + ldr r3, .L1724 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1725: + .align 2 +.L1724: + .word GSU + .word GSU+56 + .size _Z9fx_bic_i3v, .-_Z9fx_bic_i3v + .align 2 + .type _Z9fx_bic_i4v, %function +_Z9fx_bic_i4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1730 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #4 + str r3, [fp, #-16] + ldr r3, .L1730 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1730 + str r2, [r3, #60] + ldr r3, .L1730 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1730 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1730 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1730 + ldr r2, [r3, #100] + ldr r3, .L1730+4 + cmp r2, r3 + bne .L1727 + ldr r3, .L1730 + ldr r2, [r3, #468] + ldr r3, .L1730 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1730 + strb r3, [r2, #108] +.L1727: + ldr r3, .L1730 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1730 + str r2, [r3, #72] + ldr r2, .L1730 + ldr r3, .L1730 + str r3, [r2, #104] + ldr r3, .L1730 + ldr r2, [r3, #104] + ldr r3, .L1730 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1731: + .align 2 +.L1730: + .word GSU + .word GSU+56 + .size _Z9fx_bic_i4v, .-_Z9fx_bic_i4v + .align 2 + .type _Z9fx_bic_i5v, %function +_Z9fx_bic_i5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1736 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #5 + str r3, [fp, #-16] + ldr r3, .L1736 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1736 + str r2, [r3, #60] + ldr r3, .L1736 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1736 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1736 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1736 + ldr r2, [r3, #100] + ldr r3, .L1736+4 + cmp r2, r3 + bne .L1733 + ldr r3, .L1736 + ldr r2, [r3, #468] + ldr r3, .L1736 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1736 + strb r3, [r2, #108] +.L1733: + ldr r3, .L1736 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1736 + str r2, [r3, #72] + ldr r2, .L1736 + ldr r3, .L1736 + str r3, [r2, #104] + ldr r3, .L1736 + ldr r2, [r3, #104] + ldr r3, .L1736 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1737: + .align 2 +.L1736: + .word GSU + .word GSU+56 + .size _Z9fx_bic_i5v, .-_Z9fx_bic_i5v + .align 2 + .type _Z9fx_bic_i6v, %function +_Z9fx_bic_i6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1742 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #6 + str r3, [fp, #-16] + ldr r3, .L1742 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1742 + str r2, [r3, #60] + ldr r3, .L1742 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1742 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1742 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1742 + ldr r2, [r3, #100] + ldr r3, .L1742+4 + cmp r2, r3 + bne .L1739 + ldr r3, .L1742 + ldr r2, [r3, #468] + ldr r3, .L1742 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1742 + strb r3, [r2, #108] +.L1739: + ldr r3, .L1742 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1742 + str r2, [r3, #72] + ldr r2, .L1742 + ldr r3, .L1742 + str r3, [r2, #104] + ldr r3, .L1742 + ldr r2, [r3, #104] + ldr r3, .L1742 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1743: + .align 2 +.L1742: + .word GSU + .word GSU+56 + .size _Z9fx_bic_i6v, .-_Z9fx_bic_i6v + .align 2 + .type _Z9fx_bic_i7v, %function +_Z9fx_bic_i7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1748 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #7 + str r3, [fp, #-16] + ldr r3, .L1748 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1748 + str r2, [r3, #60] + ldr r3, .L1748 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1748 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1748 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1748 + ldr r2, [r3, #100] + ldr r3, .L1748+4 + cmp r2, r3 + bne .L1745 + ldr r3, .L1748 + ldr r2, [r3, #468] + ldr r3, .L1748 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1748 + strb r3, [r2, #108] +.L1745: + ldr r3, .L1748 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1748 + str r2, [r3, #72] + ldr r2, .L1748 + ldr r3, .L1748 + str r3, [r2, #104] + ldr r3, .L1748 + ldr r2, [r3, #104] + ldr r3, .L1748 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1749: + .align 2 +.L1748: + .word GSU + .word GSU+56 + .size _Z9fx_bic_i7v, .-_Z9fx_bic_i7v + .align 2 + .type _Z9fx_bic_i8v, %function +_Z9fx_bic_i8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1754 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #8 + str r3, [fp, #-16] + ldr r3, .L1754 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1754 + str r2, [r3, #60] + ldr r3, .L1754 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1754 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1754 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1754 + ldr r2, [r3, #100] + ldr r3, .L1754+4 + cmp r2, r3 + bne .L1751 + ldr r3, .L1754 + ldr r2, [r3, #468] + ldr r3, .L1754 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1754 + strb r3, [r2, #108] +.L1751: + ldr r3, .L1754 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1754 + str r2, [r3, #72] + ldr r2, .L1754 + ldr r3, .L1754 + str r3, [r2, #104] + ldr r3, .L1754 + ldr r2, [r3, #104] + ldr r3, .L1754 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1755: + .align 2 +.L1754: + .word GSU + .word GSU+56 + .size _Z9fx_bic_i8v, .-_Z9fx_bic_i8v + .align 2 + .type _Z9fx_bic_i9v, %function +_Z9fx_bic_i9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1760 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #9 + str r3, [fp, #-16] + ldr r3, .L1760 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1760 + str r2, [r3, #60] + ldr r3, .L1760 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1760 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1760 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1760 + ldr r2, [r3, #100] + ldr r3, .L1760+4 + cmp r2, r3 + bne .L1757 + ldr r3, .L1760 + ldr r2, [r3, #468] + ldr r3, .L1760 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1760 + strb r3, [r2, #108] +.L1757: + ldr r3, .L1760 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1760 + str r2, [r3, #72] + ldr r2, .L1760 + ldr r3, .L1760 + str r3, [r2, #104] + ldr r3, .L1760 + ldr r2, [r3, #104] + ldr r3, .L1760 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1761: + .align 2 +.L1760: + .word GSU + .word GSU+56 + .size _Z9fx_bic_i9v, .-_Z9fx_bic_i9v + .align 2 + .type _Z10fx_bic_i10v, %function +_Z10fx_bic_i10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1766 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #10 + str r3, [fp, #-16] + ldr r3, .L1766 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1766 + str r2, [r3, #60] + ldr r3, .L1766 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1766 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1766 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1766 + ldr r2, [r3, #100] + ldr r3, .L1766+4 + cmp r2, r3 + bne .L1763 + ldr r3, .L1766 + ldr r2, [r3, #468] + ldr r3, .L1766 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1766 + strb r3, [r2, #108] +.L1763: + ldr r3, .L1766 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1766 + str r2, [r3, #72] + ldr r2, .L1766 + ldr r3, .L1766 + str r3, [r2, #104] + ldr r3, .L1766 + ldr r2, [r3, #104] + ldr r3, .L1766 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1767: + .align 2 +.L1766: + .word GSU + .word GSU+56 + .size _Z10fx_bic_i10v, .-_Z10fx_bic_i10v + .align 2 + .type _Z10fx_bic_i11v, %function +_Z10fx_bic_i11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1772 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #11 + str r3, [fp, #-16] + ldr r3, .L1772 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1772 + str r2, [r3, #60] + ldr r3, .L1772 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1772 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1772 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1772 + ldr r2, [r3, #100] + ldr r3, .L1772+4 + cmp r2, r3 + bne .L1769 + ldr r3, .L1772 + ldr r2, [r3, #468] + ldr r3, .L1772 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1772 + strb r3, [r2, #108] +.L1769: + ldr r3, .L1772 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1772 + str r2, [r3, #72] + ldr r2, .L1772 + ldr r3, .L1772 + str r3, [r2, #104] + ldr r3, .L1772 + ldr r2, [r3, #104] + ldr r3, .L1772 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1773: + .align 2 +.L1772: + .word GSU + .word GSU+56 + .size _Z10fx_bic_i11v, .-_Z10fx_bic_i11v + .align 2 + .type _Z10fx_bic_i12v, %function +_Z10fx_bic_i12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1778 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #12 + str r3, [fp, #-16] + ldr r3, .L1778 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1778 + str r2, [r3, #60] + ldr r3, .L1778 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1778 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1778 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1778 + ldr r2, [r3, #100] + ldr r3, .L1778+4 + cmp r2, r3 + bne .L1775 + ldr r3, .L1778 + ldr r2, [r3, #468] + ldr r3, .L1778 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1778 + strb r3, [r2, #108] +.L1775: + ldr r3, .L1778 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1778 + str r2, [r3, #72] + ldr r2, .L1778 + ldr r3, .L1778 + str r3, [r2, #104] + ldr r3, .L1778 + ldr r2, [r3, #104] + ldr r3, .L1778 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1779: + .align 2 +.L1778: + .word GSU + .word GSU+56 + .size _Z10fx_bic_i12v, .-_Z10fx_bic_i12v + .align 2 + .type _Z10fx_bic_i13v, %function +_Z10fx_bic_i13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1784 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #13 + str r3, [fp, #-16] + ldr r3, .L1784 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1784 + str r2, [r3, #60] + ldr r3, .L1784 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1784 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1784 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1784 + ldr r2, [r3, #100] + ldr r3, .L1784+4 + cmp r2, r3 + bne .L1781 + ldr r3, .L1784 + ldr r2, [r3, #468] + ldr r3, .L1784 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1784 + strb r3, [r2, #108] +.L1781: + ldr r3, .L1784 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1784 + str r2, [r3, #72] + ldr r2, .L1784 + ldr r3, .L1784 + str r3, [r2, #104] + ldr r3, .L1784 + ldr r2, [r3, #104] + ldr r3, .L1784 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1785: + .align 2 +.L1784: + .word GSU + .word GSU+56 + .size _Z10fx_bic_i13v, .-_Z10fx_bic_i13v + .align 2 + .type _Z10fx_bic_i14v, %function +_Z10fx_bic_i14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1790 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #14 + str r3, [fp, #-16] + ldr r3, .L1790 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1790 + str r2, [r3, #60] + ldr r3, .L1790 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1790 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1790 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1790 + ldr r2, [r3, #100] + ldr r3, .L1790+4 + cmp r2, r3 + bne .L1787 + ldr r3, .L1790 + ldr r2, [r3, #468] + ldr r3, .L1790 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1790 + strb r3, [r2, #108] +.L1787: + ldr r3, .L1790 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1790 + str r2, [r3, #72] + ldr r2, .L1790 + ldr r3, .L1790 + str r3, [r2, #104] + ldr r3, .L1790 + ldr r2, [r3, #104] + ldr r3, .L1790 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1791: + .align 2 +.L1790: + .word GSU + .word GSU+56 + .size _Z10fx_bic_i14v, .-_Z10fx_bic_i14v + .align 2 + .type _Z10fx_bic_i15v, %function +_Z10fx_bic_i15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1796 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + bic r3, r3, #15 + str r3, [fp, #-16] + ldr r3, .L1796 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1796 + str r2, [r3, #60] + ldr r3, .L1796 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1796 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1796 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1796 + ldr r2, [r3, #100] + ldr r3, .L1796+4 + cmp r2, r3 + bne .L1793 + ldr r3, .L1796 + ldr r2, [r3, #468] + ldr r3, .L1796 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1796 + strb r3, [r2, #108] +.L1793: + ldr r3, .L1796 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1796 + str r2, [r3, #72] + ldr r2, .L1796 + ldr r3, .L1796 + str r3, [r2, #104] + ldr r3, .L1796 + ldr r2, [r3, #104] + ldr r3, .L1796 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1797: + .align 2 +.L1796: + .word GSU + .word GSU+56 + .size _Z10fx_bic_i15v, .-_Z10fx_bic_i15v + .align 2 + .type _Z10fx_mult_r0v, %function +_Z10fx_mult_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1802 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1802 + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1802 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1802 + str r2, [r3, #60] + ldr r3, .L1802 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1802 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1802 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1802 + ldr r2, [r3, #100] + ldr r3, .L1802+4 + cmp r2, r3 + bne .L1799 + ldr r3, .L1802 + ldr r2, [r3, #468] + ldr r3, .L1802 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1802 + strb r3, [r2, #108] +.L1799: + ldr r3, .L1802 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1802 + str r2, [r3, #72] + ldr r2, .L1802 + ldr r3, .L1802 + str r3, [r2, #104] + ldr r3, .L1802 + ldr r2, [r3, #104] + ldr r3, .L1802 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1803: + .align 2 +.L1802: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r0v, .-_Z10fx_mult_r0v + .align 2 + .type _Z10fx_mult_r1v, %function +_Z10fx_mult_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1808 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1808 + ldr r3, [r3, #4] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1808 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1808 + str r2, [r3, #60] + ldr r3, .L1808 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1808 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1808 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1808 + ldr r2, [r3, #100] + ldr r3, .L1808+4 + cmp r2, r3 + bne .L1805 + ldr r3, .L1808 + ldr r2, [r3, #468] + ldr r3, .L1808 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1808 + strb r3, [r2, #108] +.L1805: + ldr r3, .L1808 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1808 + str r2, [r3, #72] + ldr r2, .L1808 + ldr r3, .L1808 + str r3, [r2, #104] + ldr r3, .L1808 + ldr r2, [r3, #104] + ldr r3, .L1808 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1809: + .align 2 +.L1808: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r1v, .-_Z10fx_mult_r1v + .align 2 + .type _Z10fx_mult_r2v, %function +_Z10fx_mult_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1814 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1814 + ldr r3, [r3, #8] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1814 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1814 + str r2, [r3, #60] + ldr r3, .L1814 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1814 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1814 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1814 + ldr r2, [r3, #100] + ldr r3, .L1814+4 + cmp r2, r3 + bne .L1811 + ldr r3, .L1814 + ldr r2, [r3, #468] + ldr r3, .L1814 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1814 + strb r3, [r2, #108] +.L1811: + ldr r3, .L1814 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1814 + str r2, [r3, #72] + ldr r2, .L1814 + ldr r3, .L1814 + str r3, [r2, #104] + ldr r3, .L1814 + ldr r2, [r3, #104] + ldr r3, .L1814 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1815: + .align 2 +.L1814: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r2v, .-_Z10fx_mult_r2v + .align 2 + .type _Z10fx_mult_r3v, %function +_Z10fx_mult_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1820 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1820 + ldr r3, [r3, #12] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1820 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1820 + str r2, [r3, #60] + ldr r3, .L1820 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1820 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1820 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1820 + ldr r2, [r3, #100] + ldr r3, .L1820+4 + cmp r2, r3 + bne .L1817 + ldr r3, .L1820 + ldr r2, [r3, #468] + ldr r3, .L1820 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1820 + strb r3, [r2, #108] +.L1817: + ldr r3, .L1820 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1820 + str r2, [r3, #72] + ldr r2, .L1820 + ldr r3, .L1820 + str r3, [r2, #104] + ldr r3, .L1820 + ldr r2, [r3, #104] + ldr r3, .L1820 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1821: + .align 2 +.L1820: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r3v, .-_Z10fx_mult_r3v + .align 2 + .type _Z10fx_mult_r4v, %function +_Z10fx_mult_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1826 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1826 + ldr r3, [r3, #16] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1826 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1826 + str r2, [r3, #60] + ldr r3, .L1826 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1826 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1826 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1826 + ldr r2, [r3, #100] + ldr r3, .L1826+4 + cmp r2, r3 + bne .L1823 + ldr r3, .L1826 + ldr r2, [r3, #468] + ldr r3, .L1826 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1826 + strb r3, [r2, #108] +.L1823: + ldr r3, .L1826 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1826 + str r2, [r3, #72] + ldr r2, .L1826 + ldr r3, .L1826 + str r3, [r2, #104] + ldr r3, .L1826 + ldr r2, [r3, #104] + ldr r3, .L1826 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1827: + .align 2 +.L1826: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r4v, .-_Z10fx_mult_r4v + .align 2 + .type _Z10fx_mult_r5v, %function +_Z10fx_mult_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1832 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1832 + ldr r3, [r3, #20] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1832 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1832 + str r2, [r3, #60] + ldr r3, .L1832 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1832 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1832 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1832 + ldr r2, [r3, #100] + ldr r3, .L1832+4 + cmp r2, r3 + bne .L1829 + ldr r3, .L1832 + ldr r2, [r3, #468] + ldr r3, .L1832 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1832 + strb r3, [r2, #108] +.L1829: + ldr r3, .L1832 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1832 + str r2, [r3, #72] + ldr r2, .L1832 + ldr r3, .L1832 + str r3, [r2, #104] + ldr r3, .L1832 + ldr r2, [r3, #104] + ldr r3, .L1832 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1833: + .align 2 +.L1832: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r5v, .-_Z10fx_mult_r5v + .align 2 + .type _Z10fx_mult_r6v, %function +_Z10fx_mult_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1838 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1838 + ldr r3, [r3, #24] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1838 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1838 + str r2, [r3, #60] + ldr r3, .L1838 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1838 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1838 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1838 + ldr r2, [r3, #100] + ldr r3, .L1838+4 + cmp r2, r3 + bne .L1835 + ldr r3, .L1838 + ldr r2, [r3, #468] + ldr r3, .L1838 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1838 + strb r3, [r2, #108] +.L1835: + ldr r3, .L1838 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1838 + str r2, [r3, #72] + ldr r2, .L1838 + ldr r3, .L1838 + str r3, [r2, #104] + ldr r3, .L1838 + ldr r2, [r3, #104] + ldr r3, .L1838 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1839: + .align 2 +.L1838: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r6v, .-_Z10fx_mult_r6v + .align 2 + .type _Z10fx_mult_r7v, %function +_Z10fx_mult_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1844 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1844 + ldr r3, [r3, #28] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1844 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1844 + str r2, [r3, #60] + ldr r3, .L1844 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1844 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1844 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1844 + ldr r2, [r3, #100] + ldr r3, .L1844+4 + cmp r2, r3 + bne .L1841 + ldr r3, .L1844 + ldr r2, [r3, #468] + ldr r3, .L1844 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1844 + strb r3, [r2, #108] +.L1841: + ldr r3, .L1844 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1844 + str r2, [r3, #72] + ldr r2, .L1844 + ldr r3, .L1844 + str r3, [r2, #104] + ldr r3, .L1844 + ldr r2, [r3, #104] + ldr r3, .L1844 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1845: + .align 2 +.L1844: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r7v, .-_Z10fx_mult_r7v + .align 2 + .type _Z10fx_mult_r8v, %function +_Z10fx_mult_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1850 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1850 + ldr r3, [r3, #32] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1850 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1850 + str r2, [r3, #60] + ldr r3, .L1850 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1850 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1850 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1850 + ldr r2, [r3, #100] + ldr r3, .L1850+4 + cmp r2, r3 + bne .L1847 + ldr r3, .L1850 + ldr r2, [r3, #468] + ldr r3, .L1850 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1850 + strb r3, [r2, #108] +.L1847: + ldr r3, .L1850 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1850 + str r2, [r3, #72] + ldr r2, .L1850 + ldr r3, .L1850 + str r3, [r2, #104] + ldr r3, .L1850 + ldr r2, [r3, #104] + ldr r3, .L1850 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1851: + .align 2 +.L1850: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r8v, .-_Z10fx_mult_r8v + .align 2 + .type _Z10fx_mult_r9v, %function +_Z10fx_mult_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1856 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1856 + ldr r3, [r3, #36] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1856 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1856 + str r2, [r3, #60] + ldr r3, .L1856 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1856 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1856 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1856 + ldr r2, [r3, #100] + ldr r3, .L1856+4 + cmp r2, r3 + bne .L1853 + ldr r3, .L1856 + ldr r2, [r3, #468] + ldr r3, .L1856 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1856 + strb r3, [r2, #108] +.L1853: + ldr r3, .L1856 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1856 + str r2, [r3, #72] + ldr r2, .L1856 + ldr r3, .L1856 + str r3, [r2, #104] + ldr r3, .L1856 + ldr r2, [r3, #104] + ldr r3, .L1856 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1857: + .align 2 +.L1856: + .word GSU + .word GSU+56 + .size _Z10fx_mult_r9v, .-_Z10fx_mult_r9v + .align 2 + .type _Z11fx_mult_r10v, %function +_Z11fx_mult_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1862 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1862 + ldr r3, [r3, #40] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1862 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1862 + str r2, [r3, #60] + ldr r3, .L1862 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1862 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1862 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1862 + ldr r2, [r3, #100] + ldr r3, .L1862+4 + cmp r2, r3 + bne .L1859 + ldr r3, .L1862 + ldr r2, [r3, #468] + ldr r3, .L1862 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1862 + strb r3, [r2, #108] +.L1859: + ldr r3, .L1862 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1862 + str r2, [r3, #72] + ldr r2, .L1862 + ldr r3, .L1862 + str r3, [r2, #104] + ldr r3, .L1862 + ldr r2, [r3, #104] + ldr r3, .L1862 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1863: + .align 2 +.L1862: + .word GSU + .word GSU+56 + .size _Z11fx_mult_r10v, .-_Z11fx_mult_r10v + .align 2 + .type _Z11fx_mult_r11v, %function +_Z11fx_mult_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1868 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1868 + ldr r3, [r3, #44] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1868 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1868 + str r2, [r3, #60] + ldr r3, .L1868 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1868 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1868 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1868 + ldr r2, [r3, #100] + ldr r3, .L1868+4 + cmp r2, r3 + bne .L1865 + ldr r3, .L1868 + ldr r2, [r3, #468] + ldr r3, .L1868 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1868 + strb r3, [r2, #108] +.L1865: + ldr r3, .L1868 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1868 + str r2, [r3, #72] + ldr r2, .L1868 + ldr r3, .L1868 + str r3, [r2, #104] + ldr r3, .L1868 + ldr r2, [r3, #104] + ldr r3, .L1868 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1869: + .align 2 +.L1868: + .word GSU + .word GSU+56 + .size _Z11fx_mult_r11v, .-_Z11fx_mult_r11v + .align 2 + .type _Z11fx_mult_r12v, %function +_Z11fx_mult_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1874 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1874 + ldr r3, [r3, #48] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1874 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1874 + str r2, [r3, #60] + ldr r3, .L1874 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1874 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1874 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1874 + ldr r2, [r3, #100] + ldr r3, .L1874+4 + cmp r2, r3 + bne .L1871 + ldr r3, .L1874 + ldr r2, [r3, #468] + ldr r3, .L1874 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1874 + strb r3, [r2, #108] +.L1871: + ldr r3, .L1874 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1874 + str r2, [r3, #72] + ldr r2, .L1874 + ldr r3, .L1874 + str r3, [r2, #104] + ldr r3, .L1874 + ldr r2, [r3, #104] + ldr r3, .L1874 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1875: + .align 2 +.L1874: + .word GSU + .word GSU+56 + .size _Z11fx_mult_r12v, .-_Z11fx_mult_r12v + .align 2 + .type _Z11fx_mult_r13v, %function +_Z11fx_mult_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1880 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1880 + ldr r3, [r3, #52] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1880 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1880 + str r2, [r3, #60] + ldr r3, .L1880 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1880 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1880 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1880 + ldr r2, [r3, #100] + ldr r3, .L1880+4 + cmp r2, r3 + bne .L1877 + ldr r3, .L1880 + ldr r2, [r3, #468] + ldr r3, .L1880 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1880 + strb r3, [r2, #108] +.L1877: + ldr r3, .L1880 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1880 + str r2, [r3, #72] + ldr r2, .L1880 + ldr r3, .L1880 + str r3, [r2, #104] + ldr r3, .L1880 + ldr r2, [r3, #104] + ldr r3, .L1880 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1881: + .align 2 +.L1880: + .word GSU + .word GSU+56 + .size _Z11fx_mult_r13v, .-_Z11fx_mult_r13v + .align 2 + .type _Z11fx_mult_r14v, %function +_Z11fx_mult_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1886 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1886 + ldr r3, [r3, #56] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1886 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1886 + str r2, [r3, #60] + ldr r3, .L1886 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1886 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1886 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1886 + ldr r2, [r3, #100] + ldr r3, .L1886+4 + cmp r2, r3 + bne .L1883 + ldr r3, .L1886 + ldr r2, [r3, #468] + ldr r3, .L1886 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1886 + strb r3, [r2, #108] +.L1883: + ldr r3, .L1886 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1886 + str r2, [r3, #72] + ldr r2, .L1886 + ldr r3, .L1886 + str r3, [r2, #104] + ldr r3, .L1886 + ldr r2, [r3, #104] + ldr r3, .L1886 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1887: + .align 2 +.L1886: + .word GSU + .word GSU+56 + .size _Z11fx_mult_r14v, .-_Z11fx_mult_r14v + .align 2 + .type _Z11fx_mult_r15v, %function +_Z11fx_mult_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1892 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L1892 + ldr r3, [r3, #60] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1892 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1892 + str r2, [r3, #60] + ldr r3, .L1892 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1892 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1892 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1892 + ldr r2, [r3, #100] + ldr r3, .L1892+4 + cmp r2, r3 + bne .L1889 + ldr r3, .L1892 + ldr r2, [r3, #468] + ldr r3, .L1892 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1892 + strb r3, [r2, #108] +.L1889: + ldr r3, .L1892 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1892 + str r2, [r3, #72] + ldr r2, .L1892 + ldr r3, .L1892 + str r3, [r2, #104] + ldr r3, .L1892 + ldr r2, [r3, #104] + ldr r3, .L1892 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1893: + .align 2 +.L1892: + .word GSU + .word GSU+56 + .size _Z11fx_mult_r15v, .-_Z11fx_mult_r15v + .align 2 + .type _Z11fx_umult_r0v, %function +_Z11fx_umult_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1898 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1898 + ldr r3, [r3, #0] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1898 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1898 + str r2, [r3, #60] + ldr r3, .L1898 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1898 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1898 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1898 + ldr r2, [r3, #100] + ldr r3, .L1898+4 + cmp r2, r3 + bne .L1895 + ldr r3, .L1898 + ldr r2, [r3, #468] + ldr r3, .L1898 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1898 + strb r3, [r2, #108] +.L1895: + ldr r3, .L1898 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1898 + str r2, [r3, #72] + ldr r2, .L1898 + ldr r3, .L1898 + str r3, [r2, #104] + ldr r3, .L1898 + ldr r2, [r3, #104] + ldr r3, .L1898 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1899: + .align 2 +.L1898: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r0v, .-_Z11fx_umult_r0v + .align 2 + .type _Z11fx_umult_r1v, %function +_Z11fx_umult_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1904 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1904 + ldr r3, [r3, #4] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1904 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1904 + str r2, [r3, #60] + ldr r3, .L1904 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1904 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1904 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1904 + ldr r2, [r3, #100] + ldr r3, .L1904+4 + cmp r2, r3 + bne .L1901 + ldr r3, .L1904 + ldr r2, [r3, #468] + ldr r3, .L1904 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1904 + strb r3, [r2, #108] +.L1901: + ldr r3, .L1904 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1904 + str r2, [r3, #72] + ldr r2, .L1904 + ldr r3, .L1904 + str r3, [r2, #104] + ldr r3, .L1904 + ldr r2, [r3, #104] + ldr r3, .L1904 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1905: + .align 2 +.L1904: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r1v, .-_Z11fx_umult_r1v + .align 2 + .type _Z11fx_umult_r2v, %function +_Z11fx_umult_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1910 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1910 + ldr r3, [r3, #8] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1910 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1910 + str r2, [r3, #60] + ldr r3, .L1910 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1910 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1910 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1910 + ldr r2, [r3, #100] + ldr r3, .L1910+4 + cmp r2, r3 + bne .L1907 + ldr r3, .L1910 + ldr r2, [r3, #468] + ldr r3, .L1910 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1910 + strb r3, [r2, #108] +.L1907: + ldr r3, .L1910 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1910 + str r2, [r3, #72] + ldr r2, .L1910 + ldr r3, .L1910 + str r3, [r2, #104] + ldr r3, .L1910 + ldr r2, [r3, #104] + ldr r3, .L1910 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1911: + .align 2 +.L1910: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r2v, .-_Z11fx_umult_r2v + .align 2 + .type _Z11fx_umult_r3v, %function +_Z11fx_umult_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1916 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1916 + ldr r3, [r3, #12] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1916 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1916 + str r2, [r3, #60] + ldr r3, .L1916 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1916 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1916 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1916 + ldr r2, [r3, #100] + ldr r3, .L1916+4 + cmp r2, r3 + bne .L1913 + ldr r3, .L1916 + ldr r2, [r3, #468] + ldr r3, .L1916 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1916 + strb r3, [r2, #108] +.L1913: + ldr r3, .L1916 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1916 + str r2, [r3, #72] + ldr r2, .L1916 + ldr r3, .L1916 + str r3, [r2, #104] + ldr r3, .L1916 + ldr r2, [r3, #104] + ldr r3, .L1916 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1917: + .align 2 +.L1916: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r3v, .-_Z11fx_umult_r3v + .align 2 + .type _Z11fx_umult_r4v, %function +_Z11fx_umult_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1922 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1922 + ldr r3, [r3, #16] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1922 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1922 + str r2, [r3, #60] + ldr r3, .L1922 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1922 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1922 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1922 + ldr r2, [r3, #100] + ldr r3, .L1922+4 + cmp r2, r3 + bne .L1919 + ldr r3, .L1922 + ldr r2, [r3, #468] + ldr r3, .L1922 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1922 + strb r3, [r2, #108] +.L1919: + ldr r3, .L1922 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1922 + str r2, [r3, #72] + ldr r2, .L1922 + ldr r3, .L1922 + str r3, [r2, #104] + ldr r3, .L1922 + ldr r2, [r3, #104] + ldr r3, .L1922 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1923: + .align 2 +.L1922: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r4v, .-_Z11fx_umult_r4v + .align 2 + .type _Z11fx_umult_r5v, %function +_Z11fx_umult_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1928 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1928 + ldr r3, [r3, #20] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1928 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1928 + str r2, [r3, #60] + ldr r3, .L1928 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1928 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1928 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1928 + ldr r2, [r3, #100] + ldr r3, .L1928+4 + cmp r2, r3 + bne .L1925 + ldr r3, .L1928 + ldr r2, [r3, #468] + ldr r3, .L1928 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1928 + strb r3, [r2, #108] +.L1925: + ldr r3, .L1928 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1928 + str r2, [r3, #72] + ldr r2, .L1928 + ldr r3, .L1928 + str r3, [r2, #104] + ldr r3, .L1928 + ldr r2, [r3, #104] + ldr r3, .L1928 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1929: + .align 2 +.L1928: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r5v, .-_Z11fx_umult_r5v + .align 2 + .type _Z11fx_umult_r6v, %function +_Z11fx_umult_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1934 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1934 + ldr r3, [r3, #24] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1934 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1934 + str r2, [r3, #60] + ldr r3, .L1934 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1934 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1934 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1934 + ldr r2, [r3, #100] + ldr r3, .L1934+4 + cmp r2, r3 + bne .L1931 + ldr r3, .L1934 + ldr r2, [r3, #468] + ldr r3, .L1934 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1934 + strb r3, [r2, #108] +.L1931: + ldr r3, .L1934 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1934 + str r2, [r3, #72] + ldr r2, .L1934 + ldr r3, .L1934 + str r3, [r2, #104] + ldr r3, .L1934 + ldr r2, [r3, #104] + ldr r3, .L1934 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1935: + .align 2 +.L1934: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r6v, .-_Z11fx_umult_r6v + .align 2 + .type _Z11fx_umult_r7v, %function +_Z11fx_umult_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1940 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1940 + ldr r3, [r3, #28] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1940 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1940 + str r2, [r3, #60] + ldr r3, .L1940 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1940 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1940 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1940 + ldr r2, [r3, #100] + ldr r3, .L1940+4 + cmp r2, r3 + bne .L1937 + ldr r3, .L1940 + ldr r2, [r3, #468] + ldr r3, .L1940 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1940 + strb r3, [r2, #108] +.L1937: + ldr r3, .L1940 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1940 + str r2, [r3, #72] + ldr r2, .L1940 + ldr r3, .L1940 + str r3, [r2, #104] + ldr r3, .L1940 + ldr r2, [r3, #104] + ldr r3, .L1940 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1941: + .align 2 +.L1940: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r7v, .-_Z11fx_umult_r7v + .align 2 + .type _Z11fx_umult_r8v, %function +_Z11fx_umult_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1946 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1946 + ldr r3, [r3, #32] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1946 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1946 + str r2, [r3, #60] + ldr r3, .L1946 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1946 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1946 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1946 + ldr r2, [r3, #100] + ldr r3, .L1946+4 + cmp r2, r3 + bne .L1943 + ldr r3, .L1946 + ldr r2, [r3, #468] + ldr r3, .L1946 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1946 + strb r3, [r2, #108] +.L1943: + ldr r3, .L1946 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1946 + str r2, [r3, #72] + ldr r2, .L1946 + ldr r3, .L1946 + str r3, [r2, #104] + ldr r3, .L1946 + ldr r2, [r3, #104] + ldr r3, .L1946 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1947: + .align 2 +.L1946: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r8v, .-_Z11fx_umult_r8v + .align 2 + .type _Z11fx_umult_r9v, %function +_Z11fx_umult_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1952 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1952 + ldr r3, [r3, #36] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1952 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1952 + str r2, [r3, #60] + ldr r3, .L1952 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1952 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1952 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1952 + ldr r2, [r3, #100] + ldr r3, .L1952+4 + cmp r2, r3 + bne .L1949 + ldr r3, .L1952 + ldr r2, [r3, #468] + ldr r3, .L1952 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1952 + strb r3, [r2, #108] +.L1949: + ldr r3, .L1952 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1952 + str r2, [r3, #72] + ldr r2, .L1952 + ldr r3, .L1952 + str r3, [r2, #104] + ldr r3, .L1952 + ldr r2, [r3, #104] + ldr r3, .L1952 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1953: + .align 2 +.L1952: + .word GSU + .word GSU+56 + .size _Z11fx_umult_r9v, .-_Z11fx_umult_r9v + .align 2 + .type _Z12fx_umult_r10v, %function +_Z12fx_umult_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1958 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1958 + ldr r3, [r3, #40] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1958 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1958 + str r2, [r3, #60] + ldr r3, .L1958 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1958 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1958 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1958 + ldr r2, [r3, #100] + ldr r3, .L1958+4 + cmp r2, r3 + bne .L1955 + ldr r3, .L1958 + ldr r2, [r3, #468] + ldr r3, .L1958 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1958 + strb r3, [r2, #108] +.L1955: + ldr r3, .L1958 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1958 + str r2, [r3, #72] + ldr r2, .L1958 + ldr r3, .L1958 + str r3, [r2, #104] + ldr r3, .L1958 + ldr r2, [r3, #104] + ldr r3, .L1958 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1959: + .align 2 +.L1958: + .word GSU + .word GSU+56 + .size _Z12fx_umult_r10v, .-_Z12fx_umult_r10v + .align 2 + .type _Z12fx_umult_r11v, %function +_Z12fx_umult_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1964 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1964 + ldr r3, [r3, #44] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1964 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1964 + str r2, [r3, #60] + ldr r3, .L1964 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1964 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1964 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1964 + ldr r2, [r3, #100] + ldr r3, .L1964+4 + cmp r2, r3 + bne .L1961 + ldr r3, .L1964 + ldr r2, [r3, #468] + ldr r3, .L1964 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1964 + strb r3, [r2, #108] +.L1961: + ldr r3, .L1964 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1964 + str r2, [r3, #72] + ldr r2, .L1964 + ldr r3, .L1964 + str r3, [r2, #104] + ldr r3, .L1964 + ldr r2, [r3, #104] + ldr r3, .L1964 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1965: + .align 2 +.L1964: + .word GSU + .word GSU+56 + .size _Z12fx_umult_r11v, .-_Z12fx_umult_r11v + .align 2 + .type _Z12fx_umult_r12v, %function +_Z12fx_umult_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1970 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1970 + ldr r3, [r3, #48] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1970 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1970 + str r2, [r3, #60] + ldr r3, .L1970 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1970 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1970 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1970 + ldr r2, [r3, #100] + ldr r3, .L1970+4 + cmp r2, r3 + bne .L1967 + ldr r3, .L1970 + ldr r2, [r3, #468] + ldr r3, .L1970 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1970 + strb r3, [r2, #108] +.L1967: + ldr r3, .L1970 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1970 + str r2, [r3, #72] + ldr r2, .L1970 + ldr r3, .L1970 + str r3, [r2, #104] + ldr r3, .L1970 + ldr r2, [r3, #104] + ldr r3, .L1970 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1971: + .align 2 +.L1970: + .word GSU + .word GSU+56 + .size _Z12fx_umult_r12v, .-_Z12fx_umult_r12v + .align 2 + .type _Z12fx_umult_r13v, %function +_Z12fx_umult_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1976 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1976 + ldr r3, [r3, #52] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1976 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1976 + str r2, [r3, #60] + ldr r3, .L1976 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1976 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1976 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1976 + ldr r2, [r3, #100] + ldr r3, .L1976+4 + cmp r2, r3 + bne .L1973 + ldr r3, .L1976 + ldr r2, [r3, #468] + ldr r3, .L1976 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1976 + strb r3, [r2, #108] +.L1973: + ldr r3, .L1976 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1976 + str r2, [r3, #72] + ldr r2, .L1976 + ldr r3, .L1976 + str r3, [r2, #104] + ldr r3, .L1976 + ldr r2, [r3, #104] + ldr r3, .L1976 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1977: + .align 2 +.L1976: + .word GSU + .word GSU+56 + .size _Z12fx_umult_r13v, .-_Z12fx_umult_r13v + .align 2 + .type _Z12fx_umult_r14v, %function +_Z12fx_umult_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1982 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1982 + ldr r3, [r3, #56] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1982 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1982 + str r2, [r3, #60] + ldr r3, .L1982 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1982 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1982 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1982 + ldr r2, [r3, #100] + ldr r3, .L1982+4 + cmp r2, r3 + bne .L1979 + ldr r3, .L1982 + ldr r2, [r3, #468] + ldr r3, .L1982 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1982 + strb r3, [r2, #108] +.L1979: + ldr r3, .L1982 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1982 + str r2, [r3, #72] + ldr r2, .L1982 + ldr r3, .L1982 + str r3, [r2, #104] + ldr r3, .L1982 + ldr r2, [r3, #104] + ldr r3, .L1982 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1983: + .align 2 +.L1982: + .word GSU + .word GSU+56 + .size _Z12fx_umult_r14v, .-_Z12fx_umult_r14v + .align 2 + .type _Z12fx_umult_r15v, %function +_Z12fx_umult_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L1988 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, .L1988 + ldr r3, [r3, #60] + and r3, r3, #255 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L1988 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1988 + str r2, [r3, #60] + ldr r3, .L1988 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1988 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1988 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1988 + ldr r2, [r3, #100] + ldr r3, .L1988+4 + cmp r2, r3 + bne .L1985 + ldr r3, .L1988 + ldr r2, [r3, #468] + ldr r3, .L1988 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1988 + strb r3, [r2, #108] +.L1985: + ldr r3, .L1988 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1988 + str r2, [r3, #72] + ldr r2, .L1988 + ldr r3, .L1988 + str r3, [r2, #104] + ldr r3, .L1988 + ldr r2, [r3, #104] + ldr r3, .L1988 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1989: + .align 2 +.L1988: + .word GSU + .word GSU+56 + .size _Z12fx_umult_r15v, .-_Z12fx_umult_r15v + .align 2 + .type _Z10fx_mult_i0v, %function +_Z10fx_mult_i0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + mov r3, #0 + str r3, [fp, #-16] + ldr r3, .L1994 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L1994 + str r2, [r3, #60] + ldr r3, .L1994 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L1994 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L1994 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L1994 + ldr r2, [r3, #100] + ldr r3, .L1994+4 + cmp r2, r3 + bne .L1991 + ldr r3, .L1994 + ldr r2, [r3, #468] + ldr r3, .L1994 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L1994 + strb r3, [r2, #108] +.L1991: + ldr r3, .L1994 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L1994 + str r2, [r3, #72] + ldr r2, .L1994 + ldr r3, .L1994 + str r3, [r2, #104] + ldr r3, .L1994 + ldr r2, [r3, #104] + ldr r3, .L1994 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L1995: + .align 2 +.L1994: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i0v, .-_Z10fx_mult_i0v + .align 2 + .type _Z10fx_mult_i1v, %function +_Z10fx_mult_i1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2000 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + str r3, [fp, #-16] + ldr r3, .L2000 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2000 + str r2, [r3, #60] + ldr r3, .L2000 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2000 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2000 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2000 + ldr r2, [r3, #100] + ldr r3, .L2000+4 + cmp r2, r3 + bne .L1997 + ldr r3, .L2000 + ldr r2, [r3, #468] + ldr r3, .L2000 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2000 + strb r3, [r2, #108] +.L1997: + ldr r3, .L2000 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2000 + str r2, [r3, #72] + ldr r2, .L2000 + ldr r3, .L2000 + str r3, [r2, #104] + ldr r3, .L2000 + ldr r2, [r3, #104] + ldr r3, .L2000 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2001: + .align 2 +.L2000: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i1v, .-_Z10fx_mult_i1v + .align 2 + .type _Z10fx_mult_i2v, %function +_Z10fx_mult_i2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2006 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mov r3, r3, asl #1 + str r3, [fp, #-16] + ldr r3, .L2006 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2006 + str r2, [r3, #60] + ldr r3, .L2006 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2006 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2006 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2006 + ldr r2, [r3, #100] + ldr r3, .L2006+4 + cmp r2, r3 + bne .L2003 + ldr r3, .L2006 + ldr r2, [r3, #468] + ldr r3, .L2006 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2006 + strb r3, [r2, #108] +.L2003: + ldr r3, .L2006 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2006 + str r2, [r3, #72] + ldr r2, .L2006 + ldr r3, .L2006 + str r3, [r2, #104] + ldr r3, .L2006 + ldr r2, [r3, #104] + ldr r3, .L2006 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2007: + .align 2 +.L2006: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i2v, .-_Z10fx_mult_i2v + .align 2 + .type _Z10fx_mult_i3v, %function +_Z10fx_mult_i3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2012 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + mov r3, r2 + mov r3, r3, asl #1 + add r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L2012 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2012 + str r2, [r3, #60] + ldr r3, .L2012 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2012 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2012 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2012 + ldr r2, [r3, #100] + ldr r3, .L2012+4 + cmp r2, r3 + bne .L2009 + ldr r3, .L2012 + ldr r2, [r3, #468] + ldr r3, .L2012 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2012 + strb r3, [r2, #108] +.L2009: + ldr r3, .L2012 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2012 + str r2, [r3, #72] + ldr r2, .L2012 + ldr r3, .L2012 + str r3, [r2, #104] + ldr r3, .L2012 + ldr r2, [r3, #104] + ldr r3, .L2012 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2013: + .align 2 +.L2012: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i3v, .-_Z10fx_mult_i3v + .align 2 + .type _Z10fx_mult_i4v, %function +_Z10fx_mult_i4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2018 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mov r3, r3, asl #2 + str r3, [fp, #-16] + ldr r3, .L2018 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2018 + str r2, [r3, #60] + ldr r3, .L2018 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2018 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2018 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2018 + ldr r2, [r3, #100] + ldr r3, .L2018+4 + cmp r2, r3 + bne .L2015 + ldr r3, .L2018 + ldr r2, [r3, #468] + ldr r3, .L2018 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2018 + strb r3, [r2, #108] +.L2015: + ldr r3, .L2018 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2018 + str r2, [r3, #72] + ldr r2, .L2018 + ldr r3, .L2018 + str r3, [r2, #104] + ldr r3, .L2018 + ldr r2, [r3, #104] + ldr r3, .L2018 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2019: + .align 2 +.L2018: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i4v, .-_Z10fx_mult_i4v + .align 2 + .type _Z10fx_mult_i5v, %function +_Z10fx_mult_i5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2024 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + mov r3, r2 + mov r3, r3, asl #2 + add r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L2024 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2024 + str r2, [r3, #60] + ldr r3, .L2024 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2024 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2024 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2024 + ldr r2, [r3, #100] + ldr r3, .L2024+4 + cmp r2, r3 + bne .L2021 + ldr r3, .L2024 + ldr r2, [r3, #468] + ldr r3, .L2024 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2024 + strb r3, [r2, #108] +.L2021: + ldr r3, .L2024 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2024 + str r2, [r3, #72] + ldr r2, .L2024 + ldr r3, .L2024 + str r3, [r2, #104] + ldr r3, .L2024 + ldr r2, [r3, #104] + ldr r3, .L2024 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2025: + .align 2 +.L2024: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i5v, .-_Z10fx_mult_i5v + .align 2 + .type _Z10fx_mult_i6v, %function +_Z10fx_mult_i6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2030 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mov r2, r3, asl #1 + mov r3, r2, asl #2 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2030 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2030 + str r2, [r3, #60] + ldr r3, .L2030 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2030 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2030 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2030 + ldr r2, [r3, #100] + ldr r3, .L2030+4 + cmp r2, r3 + bne .L2027 + ldr r3, .L2030 + ldr r2, [r3, #468] + ldr r3, .L2030 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2030 + strb r3, [r2, #108] +.L2027: + ldr r3, .L2030 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2030 + str r2, [r3, #72] + ldr r2, .L2030 + ldr r3, .L2030 + str r3, [r2, #104] + ldr r3, .L2030 + ldr r2, [r3, #104] + ldr r3, .L2030 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2031: + .align 2 +.L2030: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i6v, .-_Z10fx_mult_i6v + .align 2 + .type _Z10fx_mult_i7v, %function +_Z10fx_mult_i7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2036 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + mov r3, r2 + mov r3, r3, asl #3 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2036 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2036 + str r2, [r3, #60] + ldr r3, .L2036 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2036 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2036 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2036 + ldr r2, [r3, #100] + ldr r3, .L2036+4 + cmp r2, r3 + bne .L2033 + ldr r3, .L2036 + ldr r2, [r3, #468] + ldr r3, .L2036 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2036 + strb r3, [r2, #108] +.L2033: + ldr r3, .L2036 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2036 + str r2, [r3, #72] + ldr r2, .L2036 + ldr r3, .L2036 + str r3, [r2, #104] + ldr r3, .L2036 + ldr r2, [r3, #104] + ldr r3, .L2036 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2037: + .align 2 +.L2036: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i7v, .-_Z10fx_mult_i7v + .align 2 + .type _Z10fx_mult_i8v, %function +_Z10fx_mult_i8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2042 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mov r3, r3, asl #3 + str r3, [fp, #-16] + ldr r3, .L2042 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2042 + str r2, [r3, #60] + ldr r3, .L2042 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2042 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2042 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2042 + ldr r2, [r3, #100] + ldr r3, .L2042+4 + cmp r2, r3 + bne .L2039 + ldr r3, .L2042 + ldr r2, [r3, #468] + ldr r3, .L2042 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2042 + strb r3, [r2, #108] +.L2039: + ldr r3, .L2042 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2042 + str r2, [r3, #72] + ldr r2, .L2042 + ldr r3, .L2042 + str r3, [r2, #104] + ldr r3, .L2042 + ldr r2, [r3, #104] + ldr r3, .L2042 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2043: + .align 2 +.L2042: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i8v, .-_Z10fx_mult_i8v + .align 2 + .type _Z10fx_mult_i9v, %function +_Z10fx_mult_i9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2048 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + mov r3, r2 + mov r3, r3, asl #3 + add r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L2048 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2048 + str r2, [r3, #60] + ldr r3, .L2048 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2048 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2048 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2048 + ldr r2, [r3, #100] + ldr r3, .L2048+4 + cmp r2, r3 + bne .L2045 + ldr r3, .L2048 + ldr r2, [r3, #468] + ldr r3, .L2048 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2048 + strb r3, [r2, #108] +.L2045: + ldr r3, .L2048 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2048 + str r2, [r3, #72] + ldr r2, .L2048 + ldr r3, .L2048 + str r3, [r2, #104] + ldr r3, .L2048 + ldr r2, [r3, #104] + ldr r3, .L2048 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2049: + .align 2 +.L2048: + .word GSU + .word GSU+56 + .size _Z10fx_mult_i9v, .-_Z10fx_mult_i9v + .align 2 + .type _Z11fx_mult_i10v, %function +_Z11fx_mult_i10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2054 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mov r2, r3, asl #1 + mov r3, r2, asl #2 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2054 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2054 + str r2, [r3, #60] + ldr r3, .L2054 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2054 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2054 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2054 + ldr r2, [r3, #100] + ldr r3, .L2054+4 + cmp r2, r3 + bne .L2051 + ldr r3, .L2054 + ldr r2, [r3, #468] + ldr r3, .L2054 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2054 + strb r3, [r2, #108] +.L2051: + ldr r3, .L2054 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2054 + str r2, [r3, #72] + ldr r2, .L2054 + ldr r3, .L2054 + str r3, [r2, #104] + ldr r3, .L2054 + ldr r2, [r3, #104] + ldr r3, .L2054 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2055: + .align 2 +.L2054: + .word GSU + .word GSU+56 + .size _Z11fx_mult_i10v, .-_Z11fx_mult_i10v + .align 2 + .type _Z11fx_mult_i11v, %function +_Z11fx_mult_i11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2060 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r1, r3, asr #24 + mov r3, r1 + mov r2, r3, asl #2 + mov r3, r2, asl #2 + rsb r3, r2, r3 + rsb r3, r1, r3 + str r3, [fp, #-16] + ldr r3, .L2060 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2060 + str r2, [r3, #60] + ldr r3, .L2060 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2060 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2060 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2060 + ldr r2, [r3, #100] + ldr r3, .L2060+4 + cmp r2, r3 + bne .L2057 + ldr r3, .L2060 + ldr r2, [r3, #468] + ldr r3, .L2060 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2060 + strb r3, [r2, #108] +.L2057: + ldr r3, .L2060 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2060 + str r2, [r3, #72] + ldr r2, .L2060 + ldr r3, .L2060 + str r3, [r2, #104] + ldr r3, .L2060 + ldr r2, [r3, #104] + ldr r3, .L2060 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2061: + .align 2 +.L2060: + .word GSU + .word GSU+56 + .size _Z11fx_mult_i11v, .-_Z11fx_mult_i11v + .align 2 + .type _Z11fx_mult_i12v, %function +_Z11fx_mult_i12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2066 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mov r2, r3, asl #2 + mov r3, r2, asl #2 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2066 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2066 + str r2, [r3, #60] + ldr r3, .L2066 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2066 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2066 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2066 + ldr r2, [r3, #100] + ldr r3, .L2066+4 + cmp r2, r3 + bne .L2063 + ldr r3, .L2066 + ldr r2, [r3, #468] + ldr r3, .L2066 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2066 + strb r3, [r2, #108] +.L2063: + ldr r3, .L2066 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2066 + str r2, [r3, #72] + ldr r2, .L2066 + ldr r3, .L2066 + str r3, [r2, #104] + ldr r3, .L2066 + ldr r2, [r3, #104] + ldr r3, .L2066 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2067: + .align 2 +.L2066: + .word GSU + .word GSU+56 + .size _Z11fx_mult_i12v, .-_Z11fx_mult_i12v + .align 2 + .type _Z11fx_mult_i13v, %function +_Z11fx_mult_i13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2072 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r1, r3, asr #24 + mov r3, r1 + mov r2, r3, asl #2 + mov r3, r2, asl #2 + rsb r3, r2, r3 + add r3, r3, r1 + str r3, [fp, #-16] + ldr r3, .L2072 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2072 + str r2, [r3, #60] + ldr r3, .L2072 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2072 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2072 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2072 + ldr r2, [r3, #100] + ldr r3, .L2072+4 + cmp r2, r3 + bne .L2069 + ldr r3, .L2072 + ldr r2, [r3, #468] + ldr r3, .L2072 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2072 + strb r3, [r2, #108] +.L2069: + ldr r3, .L2072 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2072 + str r2, [r3, #72] + ldr r2, .L2072 + ldr r3, .L2072 + str r3, [r2, #104] + ldr r3, .L2072 + ldr r2, [r3, #104] + ldr r3, .L2072 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2073: + .align 2 +.L2072: + .word GSU + .word GSU+56 + .size _Z11fx_mult_i13v, .-_Z11fx_mult_i13v + .align 2 + .type _Z11fx_mult_i14v, %function +_Z11fx_mult_i14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2078 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + mov r2, r3, asl #1 + mov r3, r2, asl #3 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2078 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2078 + str r2, [r3, #60] + ldr r3, .L2078 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2078 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2078 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2078 + ldr r2, [r3, #100] + ldr r3, .L2078+4 + cmp r2, r3 + bne .L2075 + ldr r3, .L2078 + ldr r2, [r3, #468] + ldr r3, .L2078 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2078 + strb r3, [r2, #108] +.L2075: + ldr r3, .L2078 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2078 + str r2, [r3, #72] + ldr r2, .L2078 + ldr r3, .L2078 + str r3, [r2, #104] + ldr r3, .L2078 + ldr r2, [r3, #104] + ldr r3, .L2078 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2079: + .align 2 +.L2078: + .word GSU + .word GSU+56 + .size _Z11fx_mult_i14v, .-_Z11fx_mult_i14v + .align 2 + .type _Z11fx_mult_i15v, %function +_Z11fx_mult_i15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2084 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + mov r3, r2 + mov r3, r3, asl #4 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2084 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2084 + str r2, [r3, #60] + ldr r3, .L2084 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2084 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2084 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2084 + ldr r2, [r3, #100] + ldr r3, .L2084+4 + cmp r2, r3 + bne .L2081 + ldr r3, .L2084 + ldr r2, [r3, #468] + ldr r3, .L2084 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2084 + strb r3, [r2, #108] +.L2081: + ldr r3, .L2084 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2084 + str r2, [r3, #72] + ldr r2, .L2084 + ldr r3, .L2084 + str r3, [r2, #104] + ldr r3, .L2084 + ldr r2, [r3, #104] + ldr r3, .L2084 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2085: + .align 2 +.L2084: + .word GSU + .word GSU+56 + .size _Z11fx_mult_i15v, .-_Z11fx_mult_i15v + .align 2 + .type _Z11fx_umult_i0v, %function +_Z11fx_umult_i0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + mov r3, #0 + str r3, [fp, #-16] + ldr r3, .L2090 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2090 + str r2, [r3, #60] + ldr r3, .L2090 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2090 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2090 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2090 + ldr r2, [r3, #100] + ldr r3, .L2090+4 + cmp r2, r3 + bne .L2087 + ldr r3, .L2090 + ldr r2, [r3, #468] + ldr r3, .L2090 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2090 + strb r3, [r2, #108] +.L2087: + ldr r3, .L2090 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2090 + str r2, [r3, #72] + ldr r2, .L2090 + ldr r3, .L2090 + str r3, [r2, #104] + ldr r3, .L2090 + ldr r2, [r3, #104] + ldr r3, .L2090 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2091: + .align 2 +.L2090: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i0v, .-_Z11fx_umult_i0v + .align 2 + .type _Z11fx_umult_i1v, %function +_Z11fx_umult_i1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2096 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + str r3, [fp, #-16] + ldr r3, .L2096 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2096 + str r2, [r3, #60] + ldr r3, .L2096 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2096 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2096 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2096 + ldr r2, [r3, #100] + ldr r3, .L2096+4 + cmp r2, r3 + bne .L2093 + ldr r3, .L2096 + ldr r2, [r3, #468] + ldr r3, .L2096 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2096 + strb r3, [r2, #108] +.L2093: + ldr r3, .L2096 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2096 + str r2, [r3, #72] + ldr r2, .L2096 + ldr r3, .L2096 + str r3, [r2, #104] + ldr r3, .L2096 + ldr r2, [r3, #104] + ldr r3, .L2096 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2097: + .align 2 +.L2096: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i1v, .-_Z11fx_umult_i1v + .align 2 + .type _Z11fx_umult_i2v, %function +_Z11fx_umult_i2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2102 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #1 + str r3, [fp, #-16] + ldr r3, .L2102 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2102 + str r2, [r3, #60] + ldr r3, .L2102 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2102 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2102 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2102 + ldr r2, [r3, #100] + ldr r3, .L2102+4 + cmp r2, r3 + bne .L2099 + ldr r3, .L2102 + ldr r2, [r3, #468] + ldr r3, .L2102 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2102 + strb r3, [r2, #108] +.L2099: + ldr r3, .L2102 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2102 + str r2, [r3, #72] + ldr r2, .L2102 + ldr r3, .L2102 + str r3, [r2, #104] + ldr r3, .L2102 + ldr r2, [r3, #104] + ldr r3, .L2102 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2103: + .align 2 +.L2102: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i2v, .-_Z11fx_umult_i2v + .align 2 + .type _Z11fx_umult_i3v, %function +_Z11fx_umult_i3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2108 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + mov r3, r2 + mov r3, r3, asl #1 + add r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L2108 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2108 + str r2, [r3, #60] + ldr r3, .L2108 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2108 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2108 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2108 + ldr r2, [r3, #100] + ldr r3, .L2108+4 + cmp r2, r3 + bne .L2105 + ldr r3, .L2108 + ldr r2, [r3, #468] + ldr r3, .L2108 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2108 + strb r3, [r2, #108] +.L2105: + ldr r3, .L2108 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2108 + str r2, [r3, #72] + ldr r2, .L2108 + ldr r3, .L2108 + str r3, [r2, #104] + ldr r3, .L2108 + ldr r2, [r3, #104] + ldr r3, .L2108 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2109: + .align 2 +.L2108: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i3v, .-_Z11fx_umult_i3v + .align 2 + .type _Z11fx_umult_i4v, %function +_Z11fx_umult_i4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2114 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #2 + str r3, [fp, #-16] + ldr r3, .L2114 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2114 + str r2, [r3, #60] + ldr r3, .L2114 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2114 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2114 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2114 + ldr r2, [r3, #100] + ldr r3, .L2114+4 + cmp r2, r3 + bne .L2111 + ldr r3, .L2114 + ldr r2, [r3, #468] + ldr r3, .L2114 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2114 + strb r3, [r2, #108] +.L2111: + ldr r3, .L2114 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2114 + str r2, [r3, #72] + ldr r2, .L2114 + ldr r3, .L2114 + str r3, [r2, #104] + ldr r3, .L2114 + ldr r2, [r3, #104] + ldr r3, .L2114 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2115: + .align 2 +.L2114: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i4v, .-_Z11fx_umult_i4v + .align 2 + .type _Z11fx_umult_i5v, %function +_Z11fx_umult_i5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2120 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + mov r3, r2 + mov r3, r3, asl #2 + add r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L2120 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2120 + str r2, [r3, #60] + ldr r3, .L2120 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2120 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2120 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2120 + ldr r2, [r3, #100] + ldr r3, .L2120+4 + cmp r2, r3 + bne .L2117 + ldr r3, .L2120 + ldr r2, [r3, #468] + ldr r3, .L2120 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2120 + strb r3, [r2, #108] +.L2117: + ldr r3, .L2120 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2120 + str r2, [r3, #72] + ldr r2, .L2120 + ldr r3, .L2120 + str r3, [r2, #104] + ldr r3, .L2120 + ldr r2, [r3, #104] + ldr r3, .L2120 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2121: + .align 2 +.L2120: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i5v, .-_Z11fx_umult_i5v + .align 2 + .type _Z11fx_umult_i6v, %function +_Z11fx_umult_i6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2126 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3, asl #1 + mov r3, r2, asl #2 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2126 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2126 + str r2, [r3, #60] + ldr r3, .L2126 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2126 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2126 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2126 + ldr r2, [r3, #100] + ldr r3, .L2126+4 + cmp r2, r3 + bne .L2123 + ldr r3, .L2126 + ldr r2, [r3, #468] + ldr r3, .L2126 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2126 + strb r3, [r2, #108] +.L2123: + ldr r3, .L2126 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2126 + str r2, [r3, #72] + ldr r2, .L2126 + ldr r3, .L2126 + str r3, [r2, #104] + ldr r3, .L2126 + ldr r2, [r3, #104] + ldr r3, .L2126 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2127: + .align 2 +.L2126: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i6v, .-_Z11fx_umult_i6v + .align 2 + .type _Z11fx_umult_i7v, %function +_Z11fx_umult_i7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2132 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + mov r3, r2 + mov r3, r3, asl #3 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2132 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2132 + str r2, [r3, #60] + ldr r3, .L2132 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2132 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2132 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2132 + ldr r2, [r3, #100] + ldr r3, .L2132+4 + cmp r2, r3 + bne .L2129 + ldr r3, .L2132 + ldr r2, [r3, #468] + ldr r3, .L2132 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2132 + strb r3, [r2, #108] +.L2129: + ldr r3, .L2132 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2132 + str r2, [r3, #72] + ldr r2, .L2132 + ldr r3, .L2132 + str r3, [r2, #104] + ldr r3, .L2132 + ldr r2, [r3, #104] + ldr r3, .L2132 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2133: + .align 2 +.L2132: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i7v, .-_Z11fx_umult_i7v + .align 2 + .type _Z11fx_umult_i8v, %function +_Z11fx_umult_i8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2138 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #3 + str r3, [fp, #-16] + ldr r3, .L2138 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2138 + str r2, [r3, #60] + ldr r3, .L2138 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2138 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2138 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2138 + ldr r2, [r3, #100] + ldr r3, .L2138+4 + cmp r2, r3 + bne .L2135 + ldr r3, .L2138 + ldr r2, [r3, #468] + ldr r3, .L2138 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2138 + strb r3, [r2, #108] +.L2135: + ldr r3, .L2138 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2138 + str r2, [r3, #72] + ldr r2, .L2138 + ldr r3, .L2138 + str r3, [r2, #104] + ldr r3, .L2138 + ldr r2, [r3, #104] + ldr r3, .L2138 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2139: + .align 2 +.L2138: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i8v, .-_Z11fx_umult_i8v + .align 2 + .type _Z11fx_umult_i9v, %function +_Z11fx_umult_i9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2144 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + mov r3, r2 + mov r3, r3, asl #3 + add r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L2144 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2144 + str r2, [r3, #60] + ldr r3, .L2144 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2144 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2144 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2144 + ldr r2, [r3, #100] + ldr r3, .L2144+4 + cmp r2, r3 + bne .L2141 + ldr r3, .L2144 + ldr r2, [r3, #468] + ldr r3, .L2144 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2144 + strb r3, [r2, #108] +.L2141: + ldr r3, .L2144 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2144 + str r2, [r3, #72] + ldr r2, .L2144 + ldr r3, .L2144 + str r3, [r2, #104] + ldr r3, .L2144 + ldr r2, [r3, #104] + ldr r3, .L2144 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2145: + .align 2 +.L2144: + .word GSU + .word GSU+56 + .size _Z11fx_umult_i9v, .-_Z11fx_umult_i9v + .align 2 + .type _Z12fx_umult_i10v, %function +_Z12fx_umult_i10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2150 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3, asl #1 + mov r3, r2, asl #2 + add r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2150 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2150 + str r2, [r3, #60] + ldr r3, .L2150 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2150 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2150 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2150 + ldr r2, [r3, #100] + ldr r3, .L2150+4 + cmp r2, r3 + bne .L2147 + ldr r3, .L2150 + ldr r2, [r3, #468] + ldr r3, .L2150 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2150 + strb r3, [r2, #108] +.L2147: + ldr r3, .L2150 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2150 + str r2, [r3, #72] + ldr r2, .L2150 + ldr r3, .L2150 + str r3, [r2, #104] + ldr r3, .L2150 + ldr r2, [r3, #104] + ldr r3, .L2150 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2151: + .align 2 +.L2150: + .word GSU + .word GSU+56 + .size _Z12fx_umult_i10v, .-_Z12fx_umult_i10v + .align 2 + .type _Z12fx_umult_i11v, %function +_Z12fx_umult_i11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2156 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r1, r3 + mov r3, r1 + mov r2, r3, asl #2 + mov r3, r2, asl #2 + rsb r3, r2, r3 + rsb r3, r1, r3 + str r3, [fp, #-16] + ldr r3, .L2156 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2156 + str r2, [r3, #60] + ldr r3, .L2156 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2156 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2156 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2156 + ldr r2, [r3, #100] + ldr r3, .L2156+4 + cmp r2, r3 + bne .L2153 + ldr r3, .L2156 + ldr r2, [r3, #468] + ldr r3, .L2156 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2156 + strb r3, [r2, #108] +.L2153: + ldr r3, .L2156 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2156 + str r2, [r3, #72] + ldr r2, .L2156 + ldr r3, .L2156 + str r3, [r2, #104] + ldr r3, .L2156 + ldr r2, [r3, #104] + ldr r3, .L2156 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2157: + .align 2 +.L2156: + .word GSU + .word GSU+56 + .size _Z12fx_umult_i11v, .-_Z12fx_umult_i11v + .align 2 + .type _Z12fx_umult_i12v, %function +_Z12fx_umult_i12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2162 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3, asl #2 + mov r3, r2, asl #2 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2162 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2162 + str r2, [r3, #60] + ldr r3, .L2162 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2162 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2162 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2162 + ldr r2, [r3, #100] + ldr r3, .L2162+4 + cmp r2, r3 + bne .L2159 + ldr r3, .L2162 + ldr r2, [r3, #468] + ldr r3, .L2162 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2162 + strb r3, [r2, #108] +.L2159: + ldr r3, .L2162 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2162 + str r2, [r3, #72] + ldr r2, .L2162 + ldr r3, .L2162 + str r3, [r2, #104] + ldr r3, .L2162 + ldr r2, [r3, #104] + ldr r3, .L2162 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2163: + .align 2 +.L2162: + .word GSU + .word GSU+56 + .size _Z12fx_umult_i12v, .-_Z12fx_umult_i12v + .align 2 + .type _Z12fx_umult_i13v, %function +_Z12fx_umult_i13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2168 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r1, r3 + mov r3, r1 + mov r2, r3, asl #2 + mov r3, r2, asl #2 + rsb r3, r2, r3 + add r3, r3, r1 + str r3, [fp, #-16] + ldr r3, .L2168 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2168 + str r2, [r3, #60] + ldr r3, .L2168 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2168 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2168 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2168 + ldr r2, [r3, #100] + ldr r3, .L2168+4 + cmp r2, r3 + bne .L2165 + ldr r3, .L2168 + ldr r2, [r3, #468] + ldr r3, .L2168 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2168 + strb r3, [r2, #108] +.L2165: + ldr r3, .L2168 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2168 + str r2, [r3, #72] + ldr r2, .L2168 + ldr r3, .L2168 + str r3, [r2, #104] + ldr r3, .L2168 + ldr r2, [r3, #104] + ldr r3, .L2168 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2169: + .align 2 +.L2168: + .word GSU + .word GSU+56 + .size _Z12fx_umult_i13v, .-_Z12fx_umult_i13v + .align 2 + .type _Z12fx_umult_i14v, %function +_Z12fx_umult_i14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2174 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3, asl #1 + mov r3, r2, asl #3 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2174 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2174 + str r2, [r3, #60] + ldr r3, .L2174 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2174 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2174 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2174 + ldr r2, [r3, #100] + ldr r3, .L2174+4 + cmp r2, r3 + bne .L2171 + ldr r3, .L2174 + ldr r2, [r3, #468] + ldr r3, .L2174 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2174 + strb r3, [r2, #108] +.L2171: + ldr r3, .L2174 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2174 + str r2, [r3, #72] + ldr r2, .L2174 + ldr r3, .L2174 + str r3, [r2, #104] + ldr r3, .L2174 + ldr r2, [r3, #104] + ldr r3, .L2174 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2175: + .align 2 +.L2174: + .word GSU + .word GSU+56 + .size _Z12fx_umult_i14v, .-_Z12fx_umult_i14v + .align 2 + .type _Z12fx_umult_i15v, %function +_Z12fx_umult_i15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2180 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + mov r3, r2 + mov r3, r3, asl #4 + rsb r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2180 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2180 + str r2, [r3, #60] + ldr r3, .L2180 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2180 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2180 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2180 + ldr r2, [r3, #100] + ldr r3, .L2180+4 + cmp r2, r3 + bne .L2177 + ldr r3, .L2180 + ldr r2, [r3, #468] + ldr r3, .L2180 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2180 + strb r3, [r2, #108] +.L2177: + ldr r3, .L2180 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2180 + str r2, [r3, #72] + ldr r2, .L2180 + ldr r3, .L2180 + str r3, [r2, #104] + ldr r3, .L2180 + ldr r2, [r3, #104] + ldr r3, .L2180 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2181: + .align 2 +.L2180: + .word GSU + .word GSU+56 + .size _Z12fx_umult_i15v, .-_Z12fx_umult_i15v + .align 2 + .type _Z6fx_sbkv, %function +_Z6fx_sbkv: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2184 + ldr r2, [r3, #464] + ldr r3, .L2184 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L2184 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2184 + ldr r2, [r3, #464] + ldr r3, .L2184 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, .L2184 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2184 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2184 + str r2, [r3, #72] + ldr r2, .L2184 + ldr r3, .L2184 + str r3, [r2, #104] + ldr r3, .L2184 + ldr r2, [r3, #104] + ldr r3, .L2184 + str r2, [r3, #100] + ldr r3, .L2184 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2184 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2185: + .align 2 +.L2184: + .word GSU + .size _Z6fx_sbkv, .-_Z6fx_sbkv + .align 2 + .type _Z10fx_link_i1v, %function +_Z10fx_link_i1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2188 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2188 + str r2, [r3, #44] + ldr r3, .L2188 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2188 + str r2, [r3, #72] + ldr r2, .L2188 + ldr r3, .L2188 + str r3, [r2, #104] + ldr r3, .L2188 + ldr r2, [r3, #104] + ldr r3, .L2188 + str r2, [r3, #100] + ldr r3, .L2188 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2188 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2189: + .align 2 +.L2188: + .word GSU + .size _Z10fx_link_i1v, .-_Z10fx_link_i1v + .align 2 + .type _Z10fx_link_i2v, %function +_Z10fx_link_i2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2192 + ldr r3, [r3, #60] + add r2, r3, #2 + ldr r3, .L2192 + str r2, [r3, #44] + ldr r3, .L2192 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2192 + str r2, [r3, #72] + ldr r2, .L2192 + ldr r3, .L2192 + str r3, [r2, #104] + ldr r3, .L2192 + ldr r2, [r3, #104] + ldr r3, .L2192 + str r2, [r3, #100] + ldr r3, .L2192 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2192 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2193: + .align 2 +.L2192: + .word GSU + .size _Z10fx_link_i2v, .-_Z10fx_link_i2v + .align 2 + .type _Z10fx_link_i3v, %function +_Z10fx_link_i3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2196 + ldr r3, [r3, #60] + add r2, r3, #3 + ldr r3, .L2196 + str r2, [r3, #44] + ldr r3, .L2196 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2196 + str r2, [r3, #72] + ldr r2, .L2196 + ldr r3, .L2196 + str r3, [r2, #104] + ldr r3, .L2196 + ldr r2, [r3, #104] + ldr r3, .L2196 + str r2, [r3, #100] + ldr r3, .L2196 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2196 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2197: + .align 2 +.L2196: + .word GSU + .size _Z10fx_link_i3v, .-_Z10fx_link_i3v + .align 2 + .type _Z10fx_link_i4v, %function +_Z10fx_link_i4v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2200 + ldr r3, [r3, #60] + add r2, r3, #4 + ldr r3, .L2200 + str r2, [r3, #44] + ldr r3, .L2200 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2200 + str r2, [r3, #72] + ldr r2, .L2200 + ldr r3, .L2200 + str r3, [r2, #104] + ldr r3, .L2200 + ldr r2, [r3, #104] + ldr r3, .L2200 + str r2, [r3, #100] + ldr r3, .L2200 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2200 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2201: + .align 2 +.L2200: + .word GSU + .size _Z10fx_link_i4v, .-_Z10fx_link_i4v + .align 2 + .type _Z6fx_sexv, %function +_Z6fx_sexv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2206 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + str r3, [fp, #-16] + ldr r3, .L2206 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2206 + str r2, [r3, #60] + ldr r3, .L2206 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2206 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2206 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2206 + ldr r2, [r3, #100] + ldr r3, .L2206+4 + cmp r2, r3 + bne .L2203 + ldr r3, .L2206 + ldr r2, [r3, #468] + ldr r3, .L2206 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2206 + strb r3, [r2, #108] +.L2203: + ldr r3, .L2206 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2206 + str r2, [r3, #72] + ldr r2, .L2206 + ldr r3, .L2206 + str r3, [r2, #104] + ldr r3, .L2206 + ldr r2, [r3, #104] + ldr r3, .L2206 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2207: + .align 2 +.L2206: + .word GSU + .word GSU+56 + .size _Z6fx_sexv, .-_Z6fx_sexv + .align 2 + .type _Z6fx_asrv, %function +_Z6fx_asrv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2212 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r2, r3, #1 + ldr r3, .L2212 + str r2, [r3, #124] + ldr r3, .L2212 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + mov r3, r3, asr #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + str r3, [fp, #-16] + ldr r3, .L2212 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2212 + str r2, [r3, #60] + ldr r3, .L2212 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2212 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2212 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2212 + ldr r2, [r3, #100] + ldr r3, .L2212+4 + cmp r2, r3 + bne .L2209 + ldr r3, .L2212 + ldr r2, [r3, #468] + ldr r3, .L2212 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2212 + strb r3, [r2, #108] +.L2209: + ldr r3, .L2212 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2212 + str r2, [r3, #72] + ldr r2, .L2212 + ldr r3, .L2212 + str r3, [r2, #104] + ldr r3, .L2212 + ldr r2, [r3, #104] + ldr r3, .L2212 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2213: + .align 2 +.L2212: + .word GSU + .word GSU+56 + .size _Z6fx_asrv, .-_Z6fx_asrv + .align 2 + .type _Z7fx_div2v, %function +_Z7fx_div2v: + @ args = 0, pretend = 0, frame = 8 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #8 + ldr r3, .L2221 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + and r2, r3, #1 + ldr r3, .L2221 + str r2, [r3, #124] + ldr r3, [fp, #-16] + cmn r3, #1 + bne .L2215 + mov r3, #0 + str r3, [fp, #-20] + b .L2217 +.L2215: + ldr r3, [fp, #-16] + mov r3, r3, asr #1 + str r3, [fp, #-20] +.L2217: + ldr r3, .L2221 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2221 + str r2, [r3, #60] + ldr r3, .L2221 + ldr r2, [r3, #100] + ldr r3, [fp, #-20] + str r3, [r2, #0] + ldr r2, .L2221 + ldr r3, [fp, #-20] + str r3, [r2, #116] + ldr r2, .L2221 + ldr r3, [fp, #-20] + str r3, [r2, #120] + ldr r3, .L2221 + ldr r2, [r3, #100] + ldr r3, .L2221+4 + cmp r2, r3 + bne .L2218 + ldr r3, .L2221 + ldr r2, [r3, #468] + ldr r3, .L2221 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2221 + strb r3, [r2, #108] +.L2218: + ldr r3, .L2221 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2221 + str r2, [r3, #72] + ldr r2, .L2221 + ldr r3, .L2221 + str r3, [r2, #104] + ldr r3, .L2221 + ldr r2, [r3, #104] + ldr r3, .L2221 + str r2, [r3, #100] + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L2222: + .align 2 +.L2221: + .word GSU + .word GSU+56 + .size _Z7fx_div2v, .-_Z7fx_div2v + .align 2 + .type _Z6fx_rorv, %function +_Z6fx_rorv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2227 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, lsr #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L2227 + ldr r3, [r3, #124] + mov r3, r3, asl #15 + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2227 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r2, r3, #1 + ldr r3, .L2227 + str r2, [r3, #124] + ldr r3, .L2227 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2227 + str r2, [r3, #60] + ldr r3, .L2227 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2227 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2227 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2227 + ldr r2, [r3, #100] + ldr r3, .L2227+4 + cmp r2, r3 + bne .L2224 + ldr r3, .L2227 + ldr r2, [r3, #468] + ldr r3, .L2227 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2227 + strb r3, [r2, #108] +.L2224: + ldr r3, .L2227 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2227 + str r2, [r3, #72] + ldr r2, .L2227 + ldr r3, .L2227 + str r3, [r2, #104] + ldr r3, .L2227 + ldr r2, [r3, #104] + ldr r3, .L2227 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2228: + .align 2 +.L2227: + .word GSU + .word GSU+56 + .size _Z6fx_rorv, .-_Z6fx_rorv + .align 2 + .type _Z9fx_jmp_r8v, %function +_Z9fx_jmp_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2231 + ldr r2, [r3, #32] + ldr r3, .L2231 + str r2, [r3, #60] + ldr r3, .L2231 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2231 + str r2, [r3, #72] + ldr r2, .L2231 + ldr r3, .L2231 + str r3, [r2, #104] + ldr r3, .L2231 + ldr r2, [r3, #104] + ldr r3, .L2231 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2232: + .align 2 +.L2231: + .word GSU + .size _Z9fx_jmp_r8v, .-_Z9fx_jmp_r8v + .align 2 + .type _Z9fx_jmp_r9v, %function +_Z9fx_jmp_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2235 + ldr r2, [r3, #36] + ldr r3, .L2235 + str r2, [r3, #60] + ldr r3, .L2235 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2235 + str r2, [r3, #72] + ldr r2, .L2235 + ldr r3, .L2235 + str r3, [r2, #104] + ldr r3, .L2235 + ldr r2, [r3, #104] + ldr r3, .L2235 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2236: + .align 2 +.L2235: + .word GSU + .size _Z9fx_jmp_r9v, .-_Z9fx_jmp_r9v + .align 2 + .type _Z10fx_jmp_r10v, %function +_Z10fx_jmp_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2239 + ldr r2, [r3, #40] + ldr r3, .L2239 + str r2, [r3, #60] + ldr r3, .L2239 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2239 + str r2, [r3, #72] + ldr r2, .L2239 + ldr r3, .L2239 + str r3, [r2, #104] + ldr r3, .L2239 + ldr r2, [r3, #104] + ldr r3, .L2239 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2240: + .align 2 +.L2239: + .word GSU + .size _Z10fx_jmp_r10v, .-_Z10fx_jmp_r10v + .align 2 + .type _Z10fx_jmp_r11v, %function +_Z10fx_jmp_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2243 + ldr r2, [r3, #44] + ldr r3, .L2243 + str r2, [r3, #60] + ldr r3, .L2243 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2243 + str r2, [r3, #72] + ldr r2, .L2243 + ldr r3, .L2243 + str r3, [r2, #104] + ldr r3, .L2243 + ldr r2, [r3, #104] + ldr r3, .L2243 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2244: + .align 2 +.L2243: + .word GSU + .size _Z10fx_jmp_r11v, .-_Z10fx_jmp_r11v + .align 2 + .type _Z10fx_jmp_r12v, %function +_Z10fx_jmp_r12v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2247 + ldr r2, [r3, #48] + ldr r3, .L2247 + str r2, [r3, #60] + ldr r3, .L2247 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2247 + str r2, [r3, #72] + ldr r2, .L2247 + ldr r3, .L2247 + str r3, [r2, #104] + ldr r3, .L2247 + ldr r2, [r3, #104] + ldr r3, .L2247 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2248: + .align 2 +.L2247: + .word GSU + .size _Z10fx_jmp_r12v, .-_Z10fx_jmp_r12v + .align 2 + .type _Z10fx_jmp_r13v, %function +_Z10fx_jmp_r13v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2251 + ldr r2, [r3, #52] + ldr r3, .L2251 + str r2, [r3, #60] + ldr r3, .L2251 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2251 + str r2, [r3, #72] + ldr r2, .L2251 + ldr r3, .L2251 + str r3, [r2, #104] + ldr r3, .L2251 + ldr r2, [r3, #104] + ldr r3, .L2251 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2252: + .align 2 +.L2251: + .word GSU + .size _Z10fx_jmp_r13v, .-_Z10fx_jmp_r13v + .align 2 + .type _Z6fx_lobv, %function +_Z6fx_lobv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2257 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + str r3, [fp, #-16] + ldr r3, .L2257 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2257 + str r2, [r3, #60] + ldr r3, .L2257 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + mov r2, r3, asl #8 + ldr r3, .L2257 + str r2, [r3, #116] + ldr r3, [fp, #-16] + mov r2, r3, asl #8 + ldr r3, .L2257 + str r2, [r3, #120] + ldr r3, .L2257 + ldr r2, [r3, #100] + ldr r3, .L2257+4 + cmp r2, r3 + bne .L2254 + ldr r3, .L2257 + ldr r2, [r3, #468] + ldr r3, .L2257 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2257 + strb r3, [r2, #108] +.L2254: + ldr r3, .L2257 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2257 + str r2, [r3, #72] + ldr r2, .L2257 + ldr r3, .L2257 + str r3, [r2, #104] + ldr r3, .L2257 + ldr r2, [r3, #104] + ldr r3, .L2257 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2258: + .align 2 +.L2257: + .word GSU + .word GSU+56 + .size _Z6fx_lobv, .-_Z6fx_lobv + .align 2 + .type _Z8fx_fmultv, %function +_Z8fx_fmultv: + @ args = 0, pretend = 0, frame = 8 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #8 + ldr r3, .L2263 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r2, r3, asr #16 + ldr r3, .L2263 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r3, [fp, #-16] + mov r3, r3, lsr #16 + str r3, [fp, #-20] + ldr r3, .L2263 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2263 + str r2, [r3, #60] + ldr r3, .L2263 + ldr r2, [r3, #100] + ldr r3, [fp, #-20] + str r3, [r2, #0] + ldr r2, .L2263 + ldr r3, [fp, #-20] + str r3, [r2, #116] + ldr r2, .L2263 + ldr r3, [fp, #-20] + str r3, [r2, #120] + ldr r3, [fp, #-16] + mov r3, r3, lsr #15 + and r2, r3, #1 + ldr r3, .L2263 + str r2, [r3, #124] + ldr r3, .L2263 + ldr r2, [r3, #100] + ldr r3, .L2263+4 + cmp r2, r3 + bne .L2260 + ldr r3, .L2263 + ldr r2, [r3, #468] + ldr r3, .L2263 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2263 + strb r3, [r2, #108] +.L2260: + ldr r3, .L2263 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2263 + str r2, [r3, #72] + ldr r2, .L2263 + ldr r3, .L2263 + str r3, [r2, #104] + ldr r3, .L2263 + ldr r2, [r3, #104] + ldr r3, .L2263 + str r2, [r3, #100] + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L2264: + .align 2 +.L2263: + .word GSU + .word GSU+56 + .size _Z8fx_fmultv, .-_Z8fx_fmultv + .align 2 + .type _Z8fx_lmultv, %function +_Z8fx_lmultv: + @ args = 0, pretend = 0, frame = 8 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #8 + ldr r3, .L2269 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r2, r3, asr #16 + ldr r3, .L2269 + ldr r3, [r3, #24] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r3, r3, asl #16 + mov r3, r3, asr #16 + mul r3, r2, r3 + str r3, [fp, #-16] + ldr r2, .L2269 + ldr r3, [fp, #-16] + str r3, [r2, #16] + ldr r3, [fp, #-16] + mov r3, r3, lsr #16 + str r3, [fp, #-20] + ldr r3, .L2269 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2269 + str r2, [r3, #60] + ldr r3, .L2269 + ldr r2, [r3, #100] + ldr r3, [fp, #-20] + str r3, [r2, #0] + ldr r2, .L2269 + ldr r3, [fp, #-20] + str r3, [r2, #116] + ldr r2, .L2269 + ldr r3, [fp, #-20] + str r3, [r2, #120] + ldr r3, .L2269 + ldr r3, [r3, #16] + mov r3, r3, lsr #15 + and r2, r3, #1 + ldr r3, .L2269 + str r2, [r3, #124] + ldr r3, .L2269 + ldr r2, [r3, #100] + ldr r3, .L2269+4 + cmp r2, r3 + bne .L2266 + ldr r3, .L2269 + ldr r2, [r3, #468] + ldr r3, .L2269 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2269 + strb r3, [r2, #108] +.L2266: + ldr r3, .L2269 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2269 + str r2, [r3, #72] + ldr r2, .L2269 + ldr r3, .L2269 + str r3, [r2, #104] + ldr r3, .L2269 + ldr r2, [r3, #104] + ldr r3, .L2269 + str r2, [r3, #100] + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L2270: + .align 2 +.L2269: + .word GSU + .word GSU+56 + .size _Z8fx_lmultv, .-_Z8fx_lmultv + .align 2 + .type _Z9fx_ibt_r0v, %function +_Z9fx_ibt_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2273 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2273 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2273 + str r2, [r3, #60] + ldr r3, .L2273 + ldr r2, [r3, #472] + ldr r3, .L2273 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2273 + strb r3, [r2, #109] + ldr r3, .L2273 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2273 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2273 + str r2, [r3, #0] + ldr r3, .L2273 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2273 + str r2, [r3, #72] + ldr r2, .L2273 + ldr r3, .L2273 + str r3, [r2, #104] + ldr r3, .L2273 + ldr r2, [r3, #104] + ldr r3, .L2273 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2274: + .align 2 +.L2273: + .word GSU + .size _Z9fx_ibt_r0v, .-_Z9fx_ibt_r0v + .align 2 + .type _Z9fx_ibt_r1v, %function +_Z9fx_ibt_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2277 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2277 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2277 + str r2, [r3, #60] + ldr r3, .L2277 + ldr r2, [r3, #472] + ldr r3, .L2277 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2277 + strb r3, [r2, #109] + ldr r3, .L2277 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2277 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2277 + str r2, [r3, #4] + ldr r3, .L2277 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2277 + str r2, [r3, #72] + ldr r2, .L2277 + ldr r3, .L2277 + str r3, [r2, #104] + ldr r3, .L2277 + ldr r2, [r3, #104] + ldr r3, .L2277 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2278: + .align 2 +.L2277: + .word GSU + .size _Z9fx_ibt_r1v, .-_Z9fx_ibt_r1v + .align 2 + .type _Z9fx_ibt_r2v, %function +_Z9fx_ibt_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2281 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2281 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2281 + str r2, [r3, #60] + ldr r3, .L2281 + ldr r2, [r3, #472] + ldr r3, .L2281 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2281 + strb r3, [r2, #109] + ldr r3, .L2281 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2281 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2281 + str r2, [r3, #8] + ldr r3, .L2281 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2281 + str r2, [r3, #72] + ldr r2, .L2281 + ldr r3, .L2281 + str r3, [r2, #104] + ldr r3, .L2281 + ldr r2, [r3, #104] + ldr r3, .L2281 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2282: + .align 2 +.L2281: + .word GSU + .size _Z9fx_ibt_r2v, .-_Z9fx_ibt_r2v + .align 2 + .type _Z9fx_ibt_r3v, %function +_Z9fx_ibt_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2285 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2285 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2285 + str r2, [r3, #60] + ldr r3, .L2285 + ldr r2, [r3, #472] + ldr r3, .L2285 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2285 + strb r3, [r2, #109] + ldr r3, .L2285 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2285 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2285 + str r2, [r3, #12] + ldr r3, .L2285 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2285 + str r2, [r3, #72] + ldr r2, .L2285 + ldr r3, .L2285 + str r3, [r2, #104] + ldr r3, .L2285 + ldr r2, [r3, #104] + ldr r3, .L2285 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2286: + .align 2 +.L2285: + .word GSU + .size _Z9fx_ibt_r3v, .-_Z9fx_ibt_r3v + .align 2 + .type _Z9fx_ibt_r4v, %function +_Z9fx_ibt_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2289 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2289 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2289 + str r2, [r3, #60] + ldr r3, .L2289 + ldr r2, [r3, #472] + ldr r3, .L2289 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2289 + strb r3, [r2, #109] + ldr r3, .L2289 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2289 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2289 + str r2, [r3, #16] + ldr r3, .L2289 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2289 + str r2, [r3, #72] + ldr r2, .L2289 + ldr r3, .L2289 + str r3, [r2, #104] + ldr r3, .L2289 + ldr r2, [r3, #104] + ldr r3, .L2289 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2290: + .align 2 +.L2289: + .word GSU + .size _Z9fx_ibt_r4v, .-_Z9fx_ibt_r4v + .align 2 + .type _Z9fx_ibt_r5v, %function +_Z9fx_ibt_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2293 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2293 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2293 + str r2, [r3, #60] + ldr r3, .L2293 + ldr r2, [r3, #472] + ldr r3, .L2293 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2293 + strb r3, [r2, #109] + ldr r3, .L2293 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2293 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2293 + str r2, [r3, #20] + ldr r3, .L2293 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2293 + str r2, [r3, #72] + ldr r2, .L2293 + ldr r3, .L2293 + str r3, [r2, #104] + ldr r3, .L2293 + ldr r2, [r3, #104] + ldr r3, .L2293 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2294: + .align 2 +.L2293: + .word GSU + .size _Z9fx_ibt_r5v, .-_Z9fx_ibt_r5v + .align 2 + .type _Z9fx_ibt_r6v, %function +_Z9fx_ibt_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2297 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2297 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2297 + str r2, [r3, #60] + ldr r3, .L2297 + ldr r2, [r3, #472] + ldr r3, .L2297 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2297 + strb r3, [r2, #109] + ldr r3, .L2297 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2297 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2297 + str r2, [r3, #24] + ldr r3, .L2297 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2297 + str r2, [r3, #72] + ldr r2, .L2297 + ldr r3, .L2297 + str r3, [r2, #104] + ldr r3, .L2297 + ldr r2, [r3, #104] + ldr r3, .L2297 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2298: + .align 2 +.L2297: + .word GSU + .size _Z9fx_ibt_r6v, .-_Z9fx_ibt_r6v + .align 2 + .type _Z9fx_ibt_r7v, %function +_Z9fx_ibt_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2301 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2301 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2301 + str r2, [r3, #60] + ldr r3, .L2301 + ldr r2, [r3, #472] + ldr r3, .L2301 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2301 + strb r3, [r2, #109] + ldr r3, .L2301 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2301 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2301 + str r2, [r3, #28] + ldr r3, .L2301 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2301 + str r2, [r3, #72] + ldr r2, .L2301 + ldr r3, .L2301 + str r3, [r2, #104] + ldr r3, .L2301 + ldr r2, [r3, #104] + ldr r3, .L2301 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2302: + .align 2 +.L2301: + .word GSU + .size _Z9fx_ibt_r7v, .-_Z9fx_ibt_r7v + .align 2 + .type _Z9fx_ibt_r8v, %function +_Z9fx_ibt_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2305 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2305 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2305 + str r2, [r3, #60] + ldr r3, .L2305 + ldr r2, [r3, #472] + ldr r3, .L2305 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2305 + strb r3, [r2, #109] + ldr r3, .L2305 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2305 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2305 + str r2, [r3, #32] + ldr r3, .L2305 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2305 + str r2, [r3, #72] + ldr r2, .L2305 + ldr r3, .L2305 + str r3, [r2, #104] + ldr r3, .L2305 + ldr r2, [r3, #104] + ldr r3, .L2305 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2306: + .align 2 +.L2305: + .word GSU + .size _Z9fx_ibt_r8v, .-_Z9fx_ibt_r8v + .align 2 + .type _Z9fx_ibt_r9v, %function +_Z9fx_ibt_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2309 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2309 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2309 + str r2, [r3, #60] + ldr r3, .L2309 + ldr r2, [r3, #472] + ldr r3, .L2309 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2309 + strb r3, [r2, #109] + ldr r3, .L2309 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2309 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2309 + str r2, [r3, #36] + ldr r3, .L2309 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2309 + str r2, [r3, #72] + ldr r2, .L2309 + ldr r3, .L2309 + str r3, [r2, #104] + ldr r3, .L2309 + ldr r2, [r3, #104] + ldr r3, .L2309 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2310: + .align 2 +.L2309: + .word GSU + .size _Z9fx_ibt_r9v, .-_Z9fx_ibt_r9v + .align 2 + .type _Z10fx_ibt_r10v, %function +_Z10fx_ibt_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2313 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2313 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2313 + str r2, [r3, #60] + ldr r3, .L2313 + ldr r2, [r3, #472] + ldr r3, .L2313 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2313 + strb r3, [r2, #109] + ldr r3, .L2313 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2313 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2313 + str r2, [r3, #40] + ldr r3, .L2313 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2313 + str r2, [r3, #72] + ldr r2, .L2313 + ldr r3, .L2313 + str r3, [r2, #104] + ldr r3, .L2313 + ldr r2, [r3, #104] + ldr r3, .L2313 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2314: + .align 2 +.L2313: + .word GSU + .size _Z10fx_ibt_r10v, .-_Z10fx_ibt_r10v + .align 2 + .type _Z10fx_ibt_r11v, %function +_Z10fx_ibt_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2317 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2317 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2317 + str r2, [r3, #60] + ldr r3, .L2317 + ldr r2, [r3, #472] + ldr r3, .L2317 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2317 + strb r3, [r2, #109] + ldr r3, .L2317 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2317 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2317 + str r2, [r3, #44] + ldr r3, .L2317 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2317 + str r2, [r3, #72] + ldr r2, .L2317 + ldr r3, .L2317 + str r3, [r2, #104] + ldr r3, .L2317 + ldr r2, [r3, #104] + ldr r3, .L2317 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2318: + .align 2 +.L2317: + .word GSU + .size _Z10fx_ibt_r11v, .-_Z10fx_ibt_r11v + .align 2 + .type _Z10fx_ibt_r12v, %function +_Z10fx_ibt_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2321 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2321 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2321 + str r2, [r3, #60] + ldr r3, .L2321 + ldr r2, [r3, #472] + ldr r3, .L2321 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2321 + strb r3, [r2, #109] + ldr r3, .L2321 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2321 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2321 + str r2, [r3, #48] + ldr r3, .L2321 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2321 + str r2, [r3, #72] + ldr r2, .L2321 + ldr r3, .L2321 + str r3, [r2, #104] + ldr r3, .L2321 + ldr r2, [r3, #104] + ldr r3, .L2321 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2322: + .align 2 +.L2321: + .word GSU + .size _Z10fx_ibt_r12v, .-_Z10fx_ibt_r12v + .align 2 + .type _Z10fx_ibt_r13v, %function +_Z10fx_ibt_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2325 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2325 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2325 + str r2, [r3, #60] + ldr r3, .L2325 + ldr r2, [r3, #472] + ldr r3, .L2325 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2325 + strb r3, [r2, #109] + ldr r3, .L2325 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2325 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2325 + str r2, [r3, #52] + ldr r3, .L2325 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2325 + str r2, [r3, #72] + ldr r2, .L2325 + ldr r3, .L2325 + str r3, [r2, #104] + ldr r3, .L2325 + ldr r2, [r3, #104] + ldr r3, .L2325 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2326: + .align 2 +.L2325: + .word GSU + .size _Z10fx_ibt_r13v, .-_Z10fx_ibt_r13v + .align 2 + .type _Z10fx_ibt_r14v, %function +_Z10fx_ibt_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2329 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2329 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2329 + str r2, [r3, #60] + ldr r3, .L2329 + ldr r2, [r3, #472] + ldr r3, .L2329 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2329 + strb r3, [r2, #109] + ldr r3, .L2329 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2329 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2329 + str r2, [r3, #56] + ldr r3, .L2329 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2329 + str r2, [r3, #72] + ldr r2, .L2329 + ldr r3, .L2329 + str r3, [r2, #104] + ldr r3, .L2329 + ldr r2, [r3, #104] + ldr r3, .L2329 + str r2, [r3, #100] + ldr r3, .L2329 + ldr r2, [r3, #468] + ldr r3, .L2329 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2329 + strb r3, [r2, #108] + ldmib sp, {fp, sp, pc} +.L2330: + .align 2 +.L2329: + .word GSU + .size _Z10fx_ibt_r14v, .-_Z10fx_ibt_r14v + .align 2 + .type _Z10fx_ibt_r15v, %function +_Z10fx_ibt_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2333 + ldrb r3, [r3, #109] + strb r3, [fp, #-13] + ldr r3, .L2333 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2333 + str r2, [r3, #60] + ldr r3, .L2333 + ldr r2, [r3, #472] + ldr r3, .L2333 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2333 + strb r3, [r2, #109] + ldr r3, .L2333 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2333 + str r2, [r3, #60] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r2, r3, asr #24 + ldr r3, .L2333 + str r2, [r3, #60] + ldr r3, .L2333 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2333 + str r2, [r3, #72] + ldr r2, .L2333 + ldr r3, .L2333 + str r3, [r2, #104] + ldr r3, .L2333 + ldr r2, [r3, #104] + ldr r3, .L2333 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2334: + .align 2 +.L2333: + .word GSU + .size _Z10fx_ibt_r15v, .-_Z10fx_ibt_r15v + .align 2 + .type _Z9fx_lms_r0v, %function +_Z9fx_lms_r0v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2337 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2337 + str r2, [r3, #96] + ldr r3, .L2337 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2337 + str r2, [r3, #60] + ldr r3, .L2337 + ldr r2, [r3, #472] + ldr r3, .L2337 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2337 + strb r3, [r2, #109] + ldr r3, .L2337 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2337 + str r2, [r3, #60] + ldr r3, .L2337 + ldr r2, [r3, #464] + ldr r3, .L2337 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2337 + str r2, [r3, #0] + ldr r3, .L2337 + ldr r1, [r3, #0] + ldr r3, .L2337 + ldr r2, [r3, #464] + ldr r3, .L2337 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2337 + str r2, [r3, #0] + ldr r3, .L2337 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2337 + str r2, [r3, #72] + ldr r2, .L2337 + ldr r3, .L2337 + str r3, [r2, #104] + ldr r3, .L2337 + ldr r2, [r3, #104] + ldr r3, .L2337 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2338: + .align 2 +.L2337: + .word GSU + .size _Z9fx_lms_r0v, .-_Z9fx_lms_r0v + .align 2 + .type _Z9fx_lms_r1v, %function +_Z9fx_lms_r1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2341 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2341 + str r2, [r3, #96] + ldr r3, .L2341 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2341 + str r2, [r3, #60] + ldr r3, .L2341 + ldr r2, [r3, #472] + ldr r3, .L2341 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2341 + strb r3, [r2, #109] + ldr r3, .L2341 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2341 + str r2, [r3, #60] + ldr r3, .L2341 + ldr r2, [r3, #464] + ldr r3, .L2341 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2341 + str r2, [r3, #4] + ldr r3, .L2341 + ldr r1, [r3, #4] + ldr r3, .L2341 + ldr r2, [r3, #464] + ldr r3, .L2341 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2341 + str r2, [r3, #4] + ldr r3, .L2341 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2341 + str r2, [r3, #72] + ldr r2, .L2341 + ldr r3, .L2341 + str r3, [r2, #104] + ldr r3, .L2341 + ldr r2, [r3, #104] + ldr r3, .L2341 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2342: + .align 2 +.L2341: + .word GSU + .size _Z9fx_lms_r1v, .-_Z9fx_lms_r1v + .align 2 + .type _Z9fx_lms_r2v, %function +_Z9fx_lms_r2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2345 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2345 + str r2, [r3, #96] + ldr r3, .L2345 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2345 + str r2, [r3, #60] + ldr r3, .L2345 + ldr r2, [r3, #472] + ldr r3, .L2345 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2345 + strb r3, [r2, #109] + ldr r3, .L2345 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2345 + str r2, [r3, #60] + ldr r3, .L2345 + ldr r2, [r3, #464] + ldr r3, .L2345 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2345 + str r2, [r3, #8] + ldr r3, .L2345 + ldr r1, [r3, #8] + ldr r3, .L2345 + ldr r2, [r3, #464] + ldr r3, .L2345 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2345 + str r2, [r3, #8] + ldr r3, .L2345 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2345 + str r2, [r3, #72] + ldr r2, .L2345 + ldr r3, .L2345 + str r3, [r2, #104] + ldr r3, .L2345 + ldr r2, [r3, #104] + ldr r3, .L2345 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2346: + .align 2 +.L2345: + .word GSU + .size _Z9fx_lms_r2v, .-_Z9fx_lms_r2v + .align 2 + .type _Z9fx_lms_r3v, %function +_Z9fx_lms_r3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2349 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2349 + str r2, [r3, #96] + ldr r3, .L2349 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2349 + str r2, [r3, #60] + ldr r3, .L2349 + ldr r2, [r3, #472] + ldr r3, .L2349 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2349 + strb r3, [r2, #109] + ldr r3, .L2349 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2349 + str r2, [r3, #60] + ldr r3, .L2349 + ldr r2, [r3, #464] + ldr r3, .L2349 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2349 + str r2, [r3, #12] + ldr r3, .L2349 + ldr r1, [r3, #12] + ldr r3, .L2349 + ldr r2, [r3, #464] + ldr r3, .L2349 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2349 + str r2, [r3, #12] + ldr r3, .L2349 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2349 + str r2, [r3, #72] + ldr r2, .L2349 + ldr r3, .L2349 + str r3, [r2, #104] + ldr r3, .L2349 + ldr r2, [r3, #104] + ldr r3, .L2349 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2350: + .align 2 +.L2349: + .word GSU + .size _Z9fx_lms_r3v, .-_Z9fx_lms_r3v + .align 2 + .type _Z9fx_lms_r4v, %function +_Z9fx_lms_r4v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2353 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2353 + str r2, [r3, #96] + ldr r3, .L2353 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2353 + str r2, [r3, #60] + ldr r3, .L2353 + ldr r2, [r3, #472] + ldr r3, .L2353 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2353 + strb r3, [r2, #109] + ldr r3, .L2353 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2353 + str r2, [r3, #60] + ldr r3, .L2353 + ldr r2, [r3, #464] + ldr r3, .L2353 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2353 + str r2, [r3, #16] + ldr r3, .L2353 + ldr r1, [r3, #16] + ldr r3, .L2353 + ldr r2, [r3, #464] + ldr r3, .L2353 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2353 + str r2, [r3, #16] + ldr r3, .L2353 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2353 + str r2, [r3, #72] + ldr r2, .L2353 + ldr r3, .L2353 + str r3, [r2, #104] + ldr r3, .L2353 + ldr r2, [r3, #104] + ldr r3, .L2353 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2354: + .align 2 +.L2353: + .word GSU + .size _Z9fx_lms_r4v, .-_Z9fx_lms_r4v + .align 2 + .type _Z9fx_lms_r5v, %function +_Z9fx_lms_r5v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2357 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2357 + str r2, [r3, #96] + ldr r3, .L2357 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2357 + str r2, [r3, #60] + ldr r3, .L2357 + ldr r2, [r3, #472] + ldr r3, .L2357 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2357 + strb r3, [r2, #109] + ldr r3, .L2357 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2357 + str r2, [r3, #60] + ldr r3, .L2357 + ldr r2, [r3, #464] + ldr r3, .L2357 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2357 + str r2, [r3, #20] + ldr r3, .L2357 + ldr r1, [r3, #20] + ldr r3, .L2357 + ldr r2, [r3, #464] + ldr r3, .L2357 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2357 + str r2, [r3, #20] + ldr r3, .L2357 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2357 + str r2, [r3, #72] + ldr r2, .L2357 + ldr r3, .L2357 + str r3, [r2, #104] + ldr r3, .L2357 + ldr r2, [r3, #104] + ldr r3, .L2357 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2358: + .align 2 +.L2357: + .word GSU + .size _Z9fx_lms_r5v, .-_Z9fx_lms_r5v + .align 2 + .type _Z9fx_lms_r6v, %function +_Z9fx_lms_r6v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2361 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2361 + str r2, [r3, #96] + ldr r3, .L2361 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2361 + str r2, [r3, #60] + ldr r3, .L2361 + ldr r2, [r3, #472] + ldr r3, .L2361 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2361 + strb r3, [r2, #109] + ldr r3, .L2361 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2361 + str r2, [r3, #60] + ldr r3, .L2361 + ldr r2, [r3, #464] + ldr r3, .L2361 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2361 + str r2, [r3, #24] + ldr r3, .L2361 + ldr r1, [r3, #24] + ldr r3, .L2361 + ldr r2, [r3, #464] + ldr r3, .L2361 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2361 + str r2, [r3, #24] + ldr r3, .L2361 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2361 + str r2, [r3, #72] + ldr r2, .L2361 + ldr r3, .L2361 + str r3, [r2, #104] + ldr r3, .L2361 + ldr r2, [r3, #104] + ldr r3, .L2361 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2362: + .align 2 +.L2361: + .word GSU + .size _Z9fx_lms_r6v, .-_Z9fx_lms_r6v + .align 2 + .type _Z9fx_lms_r7v, %function +_Z9fx_lms_r7v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2365 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2365 + str r2, [r3, #96] + ldr r3, .L2365 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2365 + str r2, [r3, #60] + ldr r3, .L2365 + ldr r2, [r3, #472] + ldr r3, .L2365 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2365 + strb r3, [r2, #109] + ldr r3, .L2365 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2365 + str r2, [r3, #60] + ldr r3, .L2365 + ldr r2, [r3, #464] + ldr r3, .L2365 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2365 + str r2, [r3, #28] + ldr r3, .L2365 + ldr r1, [r3, #28] + ldr r3, .L2365 + ldr r2, [r3, #464] + ldr r3, .L2365 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2365 + str r2, [r3, #28] + ldr r3, .L2365 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2365 + str r2, [r3, #72] + ldr r2, .L2365 + ldr r3, .L2365 + str r3, [r2, #104] + ldr r3, .L2365 + ldr r2, [r3, #104] + ldr r3, .L2365 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2366: + .align 2 +.L2365: + .word GSU + .size _Z9fx_lms_r7v, .-_Z9fx_lms_r7v + .align 2 + .type _Z9fx_lms_r8v, %function +_Z9fx_lms_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2369 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2369 + str r2, [r3, #96] + ldr r3, .L2369 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2369 + str r2, [r3, #60] + ldr r3, .L2369 + ldr r2, [r3, #472] + ldr r3, .L2369 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2369 + strb r3, [r2, #109] + ldr r3, .L2369 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2369 + str r2, [r3, #60] + ldr r3, .L2369 + ldr r2, [r3, #464] + ldr r3, .L2369 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2369 + str r2, [r3, #32] + ldr r3, .L2369 + ldr r1, [r3, #32] + ldr r3, .L2369 + ldr r2, [r3, #464] + ldr r3, .L2369 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2369 + str r2, [r3, #32] + ldr r3, .L2369 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2369 + str r2, [r3, #72] + ldr r2, .L2369 + ldr r3, .L2369 + str r3, [r2, #104] + ldr r3, .L2369 + ldr r2, [r3, #104] + ldr r3, .L2369 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2370: + .align 2 +.L2369: + .word GSU + .size _Z9fx_lms_r8v, .-_Z9fx_lms_r8v + .align 2 + .type _Z9fx_lms_r9v, %function +_Z9fx_lms_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2373 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2373 + str r2, [r3, #96] + ldr r3, .L2373 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2373 + str r2, [r3, #60] + ldr r3, .L2373 + ldr r2, [r3, #472] + ldr r3, .L2373 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2373 + strb r3, [r2, #109] + ldr r3, .L2373 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2373 + str r2, [r3, #60] + ldr r3, .L2373 + ldr r2, [r3, #464] + ldr r3, .L2373 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2373 + str r2, [r3, #36] + ldr r3, .L2373 + ldr r1, [r3, #36] + ldr r3, .L2373 + ldr r2, [r3, #464] + ldr r3, .L2373 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2373 + str r2, [r3, #36] + ldr r3, .L2373 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2373 + str r2, [r3, #72] + ldr r2, .L2373 + ldr r3, .L2373 + str r3, [r2, #104] + ldr r3, .L2373 + ldr r2, [r3, #104] + ldr r3, .L2373 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2374: + .align 2 +.L2373: + .word GSU + .size _Z9fx_lms_r9v, .-_Z9fx_lms_r9v + .align 2 + .type _Z10fx_lms_r10v, %function +_Z10fx_lms_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2377 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2377 + str r2, [r3, #96] + ldr r3, .L2377 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2377 + str r2, [r3, #60] + ldr r3, .L2377 + ldr r2, [r3, #472] + ldr r3, .L2377 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2377 + strb r3, [r2, #109] + ldr r3, .L2377 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2377 + str r2, [r3, #60] + ldr r3, .L2377 + ldr r2, [r3, #464] + ldr r3, .L2377 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2377 + str r2, [r3, #40] + ldr r3, .L2377 + ldr r1, [r3, #40] + ldr r3, .L2377 + ldr r2, [r3, #464] + ldr r3, .L2377 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2377 + str r2, [r3, #40] + ldr r3, .L2377 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2377 + str r2, [r3, #72] + ldr r2, .L2377 + ldr r3, .L2377 + str r3, [r2, #104] + ldr r3, .L2377 + ldr r2, [r3, #104] + ldr r3, .L2377 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2378: + .align 2 +.L2377: + .word GSU + .size _Z10fx_lms_r10v, .-_Z10fx_lms_r10v + .align 2 + .type _Z10fx_lms_r11v, %function +_Z10fx_lms_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2381 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2381 + str r2, [r3, #96] + ldr r3, .L2381 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2381 + str r2, [r3, #60] + ldr r3, .L2381 + ldr r2, [r3, #472] + ldr r3, .L2381 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2381 + strb r3, [r2, #109] + ldr r3, .L2381 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2381 + str r2, [r3, #60] + ldr r3, .L2381 + ldr r2, [r3, #464] + ldr r3, .L2381 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2381 + str r2, [r3, #44] + ldr r3, .L2381 + ldr r1, [r3, #44] + ldr r3, .L2381 + ldr r2, [r3, #464] + ldr r3, .L2381 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2381 + str r2, [r3, #44] + ldr r3, .L2381 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2381 + str r2, [r3, #72] + ldr r2, .L2381 + ldr r3, .L2381 + str r3, [r2, #104] + ldr r3, .L2381 + ldr r2, [r3, #104] + ldr r3, .L2381 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2382: + .align 2 +.L2381: + .word GSU + .size _Z10fx_lms_r11v, .-_Z10fx_lms_r11v + .align 2 + .type _Z10fx_lms_r12v, %function +_Z10fx_lms_r12v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2385 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2385 + str r2, [r3, #96] + ldr r3, .L2385 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2385 + str r2, [r3, #60] + ldr r3, .L2385 + ldr r2, [r3, #472] + ldr r3, .L2385 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2385 + strb r3, [r2, #109] + ldr r3, .L2385 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2385 + str r2, [r3, #60] + ldr r3, .L2385 + ldr r2, [r3, #464] + ldr r3, .L2385 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2385 + str r2, [r3, #48] + ldr r3, .L2385 + ldr r1, [r3, #48] + ldr r3, .L2385 + ldr r2, [r3, #464] + ldr r3, .L2385 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2385 + str r2, [r3, #48] + ldr r3, .L2385 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2385 + str r2, [r3, #72] + ldr r2, .L2385 + ldr r3, .L2385 + str r3, [r2, #104] + ldr r3, .L2385 + ldr r2, [r3, #104] + ldr r3, .L2385 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2386: + .align 2 +.L2385: + .word GSU + .size _Z10fx_lms_r12v, .-_Z10fx_lms_r12v + .align 2 + .type _Z10fx_lms_r13v, %function +_Z10fx_lms_r13v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2389 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2389 + str r2, [r3, #96] + ldr r3, .L2389 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2389 + str r2, [r3, #60] + ldr r3, .L2389 + ldr r2, [r3, #472] + ldr r3, .L2389 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2389 + strb r3, [r2, #109] + ldr r3, .L2389 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2389 + str r2, [r3, #60] + ldr r3, .L2389 + ldr r2, [r3, #464] + ldr r3, .L2389 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2389 + str r2, [r3, #52] + ldr r3, .L2389 + ldr r1, [r3, #52] + ldr r3, .L2389 + ldr r2, [r3, #464] + ldr r3, .L2389 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2389 + str r2, [r3, #52] + ldr r3, .L2389 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2389 + str r2, [r3, #72] + ldr r2, .L2389 + ldr r3, .L2389 + str r3, [r2, #104] + ldr r3, .L2389 + ldr r2, [r3, #104] + ldr r3, .L2389 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2390: + .align 2 +.L2389: + .word GSU + .size _Z10fx_lms_r13v, .-_Z10fx_lms_r13v + .align 2 + .type _Z10fx_lms_r14v, %function +_Z10fx_lms_r14v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2393 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2393 + str r2, [r3, #96] + ldr r3, .L2393 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2393 + str r2, [r3, #60] + ldr r3, .L2393 + ldr r2, [r3, #472] + ldr r3, .L2393 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2393 + strb r3, [r2, #109] + ldr r3, .L2393 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2393 + str r2, [r3, #60] + ldr r3, .L2393 + ldr r2, [r3, #464] + ldr r3, .L2393 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2393 + str r2, [r3, #56] + ldr r3, .L2393 + ldr r1, [r3, #56] + ldr r3, .L2393 + ldr r2, [r3, #464] + ldr r3, .L2393 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2393 + str r2, [r3, #56] + ldr r3, .L2393 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2393 + str r2, [r3, #72] + ldr r2, .L2393 + ldr r3, .L2393 + str r3, [r2, #104] + ldr r3, .L2393 + ldr r2, [r3, #104] + ldr r3, .L2393 + str r2, [r3, #100] + ldr r3, .L2393 + ldr r2, [r3, #468] + ldr r3, .L2393 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2393 + strb r3, [r2, #108] + ldmfd sp, {fp, sp, pc} +.L2394: + .align 2 +.L2393: + .word GSU + .size _Z10fx_lms_r14v, .-_Z10fx_lms_r14v + .align 2 + .type _Z10fx_lms_r15v, %function +_Z10fx_lms_r15v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2397 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2397 + str r2, [r3, #96] + ldr r3, .L2397 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2397 + str r2, [r3, #60] + ldr r3, .L2397 + ldr r2, [r3, #472] + ldr r3, .L2397 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2397 + strb r3, [r2, #109] + ldr r3, .L2397 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2397 + str r2, [r3, #60] + ldr r3, .L2397 + ldr r2, [r3, #464] + ldr r3, .L2397 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L2397 + str r2, [r3, #60] + ldr r3, .L2397 + ldr r1, [r3, #60] + ldr r3, .L2397 + ldr r2, [r3, #464] + ldr r3, .L2397 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L2397 + str r2, [r3, #60] + ldr r3, .L2397 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2397 + str r2, [r3, #72] + ldr r2, .L2397 + ldr r3, .L2397 + str r3, [r2, #104] + ldr r3, .L2397 + ldr r2, [r3, #104] + ldr r3, .L2397 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L2398: + .align 2 +.L2397: + .word GSU + .size _Z10fx_lms_r15v, .-_Z10fx_lms_r15v + .align 2 + .type _Z9fx_sms_r0v, %function +_Z9fx_sms_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2401 + ldr r3, [r3, #0] + str r3, [fp, #-16] + ldr r3, .L2401 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2401 + str r2, [r3, #96] + ldr r3, .L2401 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2401 + str r2, [r3, #60] + ldr r3, .L2401 + ldr r2, [r3, #472] + ldr r3, .L2401 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2401 + strb r3, [r2, #109] + ldr r3, .L2401 + ldr r2, [r3, #464] + ldr r3, .L2401 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2401 + ldr r2, [r3, #464] + ldr r3, .L2401 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2401 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2401 + str r2, [r3, #72] + ldr r2, .L2401 + ldr r3, .L2401 + str r3, [r2, #104] + ldr r3, .L2401 + ldr r2, [r3, #104] + ldr r3, .L2401 + str r2, [r3, #100] + ldr r3, .L2401 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2401 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2402: + .align 2 +.L2401: + .word GSU + .size _Z9fx_sms_r0v, .-_Z9fx_sms_r0v + .align 2 + .type _Z9fx_sms_r1v, %function +_Z9fx_sms_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2405 + ldr r3, [r3, #4] + str r3, [fp, #-16] + ldr r3, .L2405 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2405 + str r2, [r3, #96] + ldr r3, .L2405 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2405 + str r2, [r3, #60] + ldr r3, .L2405 + ldr r2, [r3, #472] + ldr r3, .L2405 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2405 + strb r3, [r2, #109] + ldr r3, .L2405 + ldr r2, [r3, #464] + ldr r3, .L2405 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2405 + ldr r2, [r3, #464] + ldr r3, .L2405 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2405 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2405 + str r2, [r3, #72] + ldr r2, .L2405 + ldr r3, .L2405 + str r3, [r2, #104] + ldr r3, .L2405 + ldr r2, [r3, #104] + ldr r3, .L2405 + str r2, [r3, #100] + ldr r3, .L2405 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2405 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2406: + .align 2 +.L2405: + .word GSU + .size _Z9fx_sms_r1v, .-_Z9fx_sms_r1v + .align 2 + .type _Z9fx_sms_r2v, %function +_Z9fx_sms_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2409 + ldr r3, [r3, #8] + str r3, [fp, #-16] + ldr r3, .L2409 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2409 + str r2, [r3, #96] + ldr r3, .L2409 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2409 + str r2, [r3, #60] + ldr r3, .L2409 + ldr r2, [r3, #472] + ldr r3, .L2409 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2409 + strb r3, [r2, #109] + ldr r3, .L2409 + ldr r2, [r3, #464] + ldr r3, .L2409 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2409 + ldr r2, [r3, #464] + ldr r3, .L2409 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2409 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2409 + str r2, [r3, #72] + ldr r2, .L2409 + ldr r3, .L2409 + str r3, [r2, #104] + ldr r3, .L2409 + ldr r2, [r3, #104] + ldr r3, .L2409 + str r2, [r3, #100] + ldr r3, .L2409 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2409 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2410: + .align 2 +.L2409: + .word GSU + .size _Z9fx_sms_r2v, .-_Z9fx_sms_r2v + .align 2 + .type _Z9fx_sms_r3v, %function +_Z9fx_sms_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2413 + ldr r3, [r3, #12] + str r3, [fp, #-16] + ldr r3, .L2413 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2413 + str r2, [r3, #96] + ldr r3, .L2413 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2413 + str r2, [r3, #60] + ldr r3, .L2413 + ldr r2, [r3, #472] + ldr r3, .L2413 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2413 + strb r3, [r2, #109] + ldr r3, .L2413 + ldr r2, [r3, #464] + ldr r3, .L2413 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2413 + ldr r2, [r3, #464] + ldr r3, .L2413 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2413 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2413 + str r2, [r3, #72] + ldr r2, .L2413 + ldr r3, .L2413 + str r3, [r2, #104] + ldr r3, .L2413 + ldr r2, [r3, #104] + ldr r3, .L2413 + str r2, [r3, #100] + ldr r3, .L2413 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2413 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2414: + .align 2 +.L2413: + .word GSU + .size _Z9fx_sms_r3v, .-_Z9fx_sms_r3v + .align 2 + .type _Z9fx_sms_r4v, %function +_Z9fx_sms_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2417 + ldr r3, [r3, #16] + str r3, [fp, #-16] + ldr r3, .L2417 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2417 + str r2, [r3, #96] + ldr r3, .L2417 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2417 + str r2, [r3, #60] + ldr r3, .L2417 + ldr r2, [r3, #472] + ldr r3, .L2417 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2417 + strb r3, [r2, #109] + ldr r3, .L2417 + ldr r2, [r3, #464] + ldr r3, .L2417 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2417 + ldr r2, [r3, #464] + ldr r3, .L2417 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2417 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2417 + str r2, [r3, #72] + ldr r2, .L2417 + ldr r3, .L2417 + str r3, [r2, #104] + ldr r3, .L2417 + ldr r2, [r3, #104] + ldr r3, .L2417 + str r2, [r3, #100] + ldr r3, .L2417 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2417 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2418: + .align 2 +.L2417: + .word GSU + .size _Z9fx_sms_r4v, .-_Z9fx_sms_r4v + .align 2 + .type _Z9fx_sms_r5v, %function +_Z9fx_sms_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2421 + ldr r3, [r3, #20] + str r3, [fp, #-16] + ldr r3, .L2421 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2421 + str r2, [r3, #96] + ldr r3, .L2421 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2421 + str r2, [r3, #60] + ldr r3, .L2421 + ldr r2, [r3, #472] + ldr r3, .L2421 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2421 + strb r3, [r2, #109] + ldr r3, .L2421 + ldr r2, [r3, #464] + ldr r3, .L2421 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2421 + ldr r2, [r3, #464] + ldr r3, .L2421 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2421 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2421 + str r2, [r3, #72] + ldr r2, .L2421 + ldr r3, .L2421 + str r3, [r2, #104] + ldr r3, .L2421 + ldr r2, [r3, #104] + ldr r3, .L2421 + str r2, [r3, #100] + ldr r3, .L2421 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2421 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2422: + .align 2 +.L2421: + .word GSU + .size _Z9fx_sms_r5v, .-_Z9fx_sms_r5v + .align 2 + .type _Z9fx_sms_r6v, %function +_Z9fx_sms_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2425 + ldr r3, [r3, #24] + str r3, [fp, #-16] + ldr r3, .L2425 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2425 + str r2, [r3, #96] + ldr r3, .L2425 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2425 + str r2, [r3, #60] + ldr r3, .L2425 + ldr r2, [r3, #472] + ldr r3, .L2425 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2425 + strb r3, [r2, #109] + ldr r3, .L2425 + ldr r2, [r3, #464] + ldr r3, .L2425 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2425 + ldr r2, [r3, #464] + ldr r3, .L2425 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2425 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2425 + str r2, [r3, #72] + ldr r2, .L2425 + ldr r3, .L2425 + str r3, [r2, #104] + ldr r3, .L2425 + ldr r2, [r3, #104] + ldr r3, .L2425 + str r2, [r3, #100] + ldr r3, .L2425 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2425 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2426: + .align 2 +.L2425: + .word GSU + .size _Z9fx_sms_r6v, .-_Z9fx_sms_r6v + .align 2 + .type _Z9fx_sms_r7v, %function +_Z9fx_sms_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2429 + ldr r3, [r3, #28] + str r3, [fp, #-16] + ldr r3, .L2429 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2429 + str r2, [r3, #96] + ldr r3, .L2429 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2429 + str r2, [r3, #60] + ldr r3, .L2429 + ldr r2, [r3, #472] + ldr r3, .L2429 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2429 + strb r3, [r2, #109] + ldr r3, .L2429 + ldr r2, [r3, #464] + ldr r3, .L2429 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2429 + ldr r2, [r3, #464] + ldr r3, .L2429 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2429 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2429 + str r2, [r3, #72] + ldr r2, .L2429 + ldr r3, .L2429 + str r3, [r2, #104] + ldr r3, .L2429 + ldr r2, [r3, #104] + ldr r3, .L2429 + str r2, [r3, #100] + ldr r3, .L2429 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2429 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2430: + .align 2 +.L2429: + .word GSU + .size _Z9fx_sms_r7v, .-_Z9fx_sms_r7v + .align 2 + .type _Z9fx_sms_r8v, %function +_Z9fx_sms_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2433 + ldr r3, [r3, #32] + str r3, [fp, #-16] + ldr r3, .L2433 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2433 + str r2, [r3, #96] + ldr r3, .L2433 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2433 + str r2, [r3, #60] + ldr r3, .L2433 + ldr r2, [r3, #472] + ldr r3, .L2433 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2433 + strb r3, [r2, #109] + ldr r3, .L2433 + ldr r2, [r3, #464] + ldr r3, .L2433 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2433 + ldr r2, [r3, #464] + ldr r3, .L2433 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2433 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2433 + str r2, [r3, #72] + ldr r2, .L2433 + ldr r3, .L2433 + str r3, [r2, #104] + ldr r3, .L2433 + ldr r2, [r3, #104] + ldr r3, .L2433 + str r2, [r3, #100] + ldr r3, .L2433 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2433 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2434: + .align 2 +.L2433: + .word GSU + .size _Z9fx_sms_r8v, .-_Z9fx_sms_r8v + .align 2 + .type _Z9fx_sms_r9v, %function +_Z9fx_sms_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2437 + ldr r3, [r3, #36] + str r3, [fp, #-16] + ldr r3, .L2437 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2437 + str r2, [r3, #96] + ldr r3, .L2437 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2437 + str r2, [r3, #60] + ldr r3, .L2437 + ldr r2, [r3, #472] + ldr r3, .L2437 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2437 + strb r3, [r2, #109] + ldr r3, .L2437 + ldr r2, [r3, #464] + ldr r3, .L2437 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2437 + ldr r2, [r3, #464] + ldr r3, .L2437 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2437 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2437 + str r2, [r3, #72] + ldr r2, .L2437 + ldr r3, .L2437 + str r3, [r2, #104] + ldr r3, .L2437 + ldr r2, [r3, #104] + ldr r3, .L2437 + str r2, [r3, #100] + ldr r3, .L2437 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2437 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2438: + .align 2 +.L2437: + .word GSU + .size _Z9fx_sms_r9v, .-_Z9fx_sms_r9v + .align 2 + .type _Z10fx_sms_r10v, %function +_Z10fx_sms_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2441 + ldr r3, [r3, #40] + str r3, [fp, #-16] + ldr r3, .L2441 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2441 + str r2, [r3, #96] + ldr r3, .L2441 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2441 + str r2, [r3, #60] + ldr r3, .L2441 + ldr r2, [r3, #472] + ldr r3, .L2441 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2441 + strb r3, [r2, #109] + ldr r3, .L2441 + ldr r2, [r3, #464] + ldr r3, .L2441 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2441 + ldr r2, [r3, #464] + ldr r3, .L2441 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2441 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2441 + str r2, [r3, #72] + ldr r2, .L2441 + ldr r3, .L2441 + str r3, [r2, #104] + ldr r3, .L2441 + ldr r2, [r3, #104] + ldr r3, .L2441 + str r2, [r3, #100] + ldr r3, .L2441 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2441 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2442: + .align 2 +.L2441: + .word GSU + .size _Z10fx_sms_r10v, .-_Z10fx_sms_r10v + .align 2 + .type _Z10fx_sms_r11v, %function +_Z10fx_sms_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2445 + ldr r3, [r3, #44] + str r3, [fp, #-16] + ldr r3, .L2445 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2445 + str r2, [r3, #96] + ldr r3, .L2445 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2445 + str r2, [r3, #60] + ldr r3, .L2445 + ldr r2, [r3, #472] + ldr r3, .L2445 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2445 + strb r3, [r2, #109] + ldr r3, .L2445 + ldr r2, [r3, #464] + ldr r3, .L2445 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2445 + ldr r2, [r3, #464] + ldr r3, .L2445 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2445 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2445 + str r2, [r3, #72] + ldr r2, .L2445 + ldr r3, .L2445 + str r3, [r2, #104] + ldr r3, .L2445 + ldr r2, [r3, #104] + ldr r3, .L2445 + str r2, [r3, #100] + ldr r3, .L2445 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2445 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2446: + .align 2 +.L2445: + .word GSU + .size _Z10fx_sms_r11v, .-_Z10fx_sms_r11v + .align 2 + .type _Z10fx_sms_r12v, %function +_Z10fx_sms_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2449 + ldr r3, [r3, #48] + str r3, [fp, #-16] + ldr r3, .L2449 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2449 + str r2, [r3, #96] + ldr r3, .L2449 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2449 + str r2, [r3, #60] + ldr r3, .L2449 + ldr r2, [r3, #472] + ldr r3, .L2449 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2449 + strb r3, [r2, #109] + ldr r3, .L2449 + ldr r2, [r3, #464] + ldr r3, .L2449 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2449 + ldr r2, [r3, #464] + ldr r3, .L2449 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2449 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2449 + str r2, [r3, #72] + ldr r2, .L2449 + ldr r3, .L2449 + str r3, [r2, #104] + ldr r3, .L2449 + ldr r2, [r3, #104] + ldr r3, .L2449 + str r2, [r3, #100] + ldr r3, .L2449 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2449 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2450: + .align 2 +.L2449: + .word GSU + .size _Z10fx_sms_r12v, .-_Z10fx_sms_r12v + .align 2 + .type _Z10fx_sms_r13v, %function +_Z10fx_sms_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2453 + ldr r3, [r3, #52] + str r3, [fp, #-16] + ldr r3, .L2453 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2453 + str r2, [r3, #96] + ldr r3, .L2453 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2453 + str r2, [r3, #60] + ldr r3, .L2453 + ldr r2, [r3, #472] + ldr r3, .L2453 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2453 + strb r3, [r2, #109] + ldr r3, .L2453 + ldr r2, [r3, #464] + ldr r3, .L2453 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2453 + ldr r2, [r3, #464] + ldr r3, .L2453 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2453 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2453 + str r2, [r3, #72] + ldr r2, .L2453 + ldr r3, .L2453 + str r3, [r2, #104] + ldr r3, .L2453 + ldr r2, [r3, #104] + ldr r3, .L2453 + str r2, [r3, #100] + ldr r3, .L2453 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2453 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2454: + .align 2 +.L2453: + .word GSU + .size _Z10fx_sms_r13v, .-_Z10fx_sms_r13v + .align 2 + .type _Z10fx_sms_r14v, %function +_Z10fx_sms_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2457 + ldr r3, [r3, #56] + str r3, [fp, #-16] + ldr r3, .L2457 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2457 + str r2, [r3, #96] + ldr r3, .L2457 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2457 + str r2, [r3, #60] + ldr r3, .L2457 + ldr r2, [r3, #472] + ldr r3, .L2457 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2457 + strb r3, [r2, #109] + ldr r3, .L2457 + ldr r2, [r3, #464] + ldr r3, .L2457 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2457 + ldr r2, [r3, #464] + ldr r3, .L2457 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2457 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2457 + str r2, [r3, #72] + ldr r2, .L2457 + ldr r3, .L2457 + str r3, [r2, #104] + ldr r3, .L2457 + ldr r2, [r3, #104] + ldr r3, .L2457 + str r2, [r3, #100] + ldr r3, .L2457 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2457 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2458: + .align 2 +.L2457: + .word GSU + .size _Z10fx_sms_r14v, .-_Z10fx_sms_r14v + .align 2 + .type _Z10fx_sms_r15v, %function +_Z10fx_sms_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2461 + ldr r3, [r3, #60] + str r3, [fp, #-16] + ldr r3, .L2461 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #1 + ldr r3, .L2461 + str r2, [r3, #96] + ldr r3, .L2461 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2461 + str r2, [r3, #60] + ldr r3, .L2461 + ldr r2, [r3, #472] + ldr r3, .L2461 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2461 + strb r3, [r2, #109] + ldr r3, .L2461 + ldr r2, [r3, #464] + ldr r3, .L2461 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2461 + ldr r2, [r3, #464] + ldr r3, .L2461 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L2461 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2461 + str r2, [r3, #72] + ldr r2, .L2461 + ldr r3, .L2461 + str r3, [r2, #104] + ldr r3, .L2461 + ldr r2, [r3, #104] + ldr r3, .L2461 + str r2, [r3, #100] + ldr r3, .L2461 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2461 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L2462: + .align 2 +.L2461: + .word GSU + .size _Z10fx_sms_r15v, .-_Z10fx_sms_r15v + .align 2 + .type _Z10fx_from_r0v, %function +_Z10fx_from_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2470 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2464 + ldr r3, .L2470 + ldr r3, [r3, #0] + str r3, [fp, #-16] + ldr r3, .L2470 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2470 + str r2, [r3, #60] + ldr r3, .L2470 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2470 + str r2, [r3, #128] + ldr r2, .L2470 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2470 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2470 + ldr r2, [r3, #100] + ldr r3, .L2470+4 + cmp r2, r3 + bne .L2466 + ldr r3, .L2470 + ldr r2, [r3, #468] + ldr r3, .L2470 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2470 + strb r3, [r2, #108] +.L2466: + ldr r3, .L2470 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2470 + str r2, [r3, #72] + ldr r2, .L2470 + ldr r3, .L2470 + str r3, [r2, #104] + ldr r3, .L2470 + ldr r2, [r3, #104] + ldr r3, .L2470 + str r2, [r3, #100] + b .L2469 +.L2464: + ldr r2, .L2470 + ldr r3, .L2470 + str r3, [r2, #104] + ldr r3, .L2470 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2470 + str r2, [r3, #60] +.L2469: + ldmib sp, {fp, sp, pc} +.L2471: + .align 2 +.L2470: + .word GSU + .word GSU+56 + .size _Z10fx_from_r0v, .-_Z10fx_from_r0v + .align 2 + .type _Z10fx_from_r1v, %function +_Z10fx_from_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2479 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2473 + ldr r3, .L2479 + ldr r3, [r3, #4] + str r3, [fp, #-16] + ldr r3, .L2479 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2479 + str r2, [r3, #60] + ldr r3, .L2479 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2479 + str r2, [r3, #128] + ldr r2, .L2479 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2479 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2479 + ldr r2, [r3, #100] + ldr r3, .L2479+4 + cmp r2, r3 + bne .L2475 + ldr r3, .L2479 + ldr r2, [r3, #468] + ldr r3, .L2479 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2479 + strb r3, [r2, #108] +.L2475: + ldr r3, .L2479 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2479 + str r2, [r3, #72] + ldr r2, .L2479 + ldr r3, .L2479 + str r3, [r2, #104] + ldr r3, .L2479 + ldr r2, [r3, #104] + ldr r3, .L2479 + str r2, [r3, #100] + b .L2478 +.L2473: + ldr r2, .L2479 + ldr r3, .L2479+8 + str r3, [r2, #104] + ldr r3, .L2479 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2479 + str r2, [r3, #60] +.L2478: + ldmib sp, {fp, sp, pc} +.L2480: + .align 2 +.L2479: + .word GSU + .word GSU+56 + .word GSU+4 + .size _Z10fx_from_r1v, .-_Z10fx_from_r1v + .align 2 + .type _Z10fx_from_r2v, %function +_Z10fx_from_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2488 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2482 + ldr r3, .L2488 + ldr r3, [r3, #8] + str r3, [fp, #-16] + ldr r3, .L2488 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2488 + str r2, [r3, #60] + ldr r3, .L2488 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2488 + str r2, [r3, #128] + ldr r2, .L2488 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2488 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2488 + ldr r2, [r3, #100] + ldr r3, .L2488+4 + cmp r2, r3 + bne .L2484 + ldr r3, .L2488 + ldr r2, [r3, #468] + ldr r3, .L2488 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2488 + strb r3, [r2, #108] +.L2484: + ldr r3, .L2488 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2488 + str r2, [r3, #72] + ldr r2, .L2488 + ldr r3, .L2488 + str r3, [r2, #104] + ldr r3, .L2488 + ldr r2, [r3, #104] + ldr r3, .L2488 + str r2, [r3, #100] + b .L2487 +.L2482: + ldr r2, .L2488 + ldr r3, .L2488+8 + str r3, [r2, #104] + ldr r3, .L2488 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2488 + str r2, [r3, #60] +.L2487: + ldmib sp, {fp, sp, pc} +.L2489: + .align 2 +.L2488: + .word GSU + .word GSU+56 + .word GSU+8 + .size _Z10fx_from_r2v, .-_Z10fx_from_r2v + .align 2 + .type _Z10fx_from_r3v, %function +_Z10fx_from_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2497 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2491 + ldr r3, .L2497 + ldr r3, [r3, #12] + str r3, [fp, #-16] + ldr r3, .L2497 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2497 + str r2, [r3, #60] + ldr r3, .L2497 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2497 + str r2, [r3, #128] + ldr r2, .L2497 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2497 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2497 + ldr r2, [r3, #100] + ldr r3, .L2497+4 + cmp r2, r3 + bne .L2493 + ldr r3, .L2497 + ldr r2, [r3, #468] + ldr r3, .L2497 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2497 + strb r3, [r2, #108] +.L2493: + ldr r3, .L2497 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2497 + str r2, [r3, #72] + ldr r2, .L2497 + ldr r3, .L2497 + str r3, [r2, #104] + ldr r3, .L2497 + ldr r2, [r3, #104] + ldr r3, .L2497 + str r2, [r3, #100] + b .L2496 +.L2491: + ldr r2, .L2497 + ldr r3, .L2497+8 + str r3, [r2, #104] + ldr r3, .L2497 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2497 + str r2, [r3, #60] +.L2496: + ldmib sp, {fp, sp, pc} +.L2498: + .align 2 +.L2497: + .word GSU + .word GSU+56 + .word GSU+12 + .size _Z10fx_from_r3v, .-_Z10fx_from_r3v + .align 2 + .type _Z10fx_from_r4v, %function +_Z10fx_from_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2506 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2500 + ldr r3, .L2506 + ldr r3, [r3, #16] + str r3, [fp, #-16] + ldr r3, .L2506 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2506 + str r2, [r3, #60] + ldr r3, .L2506 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2506 + str r2, [r3, #128] + ldr r2, .L2506 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2506 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2506 + ldr r2, [r3, #100] + ldr r3, .L2506+4 + cmp r2, r3 + bne .L2502 + ldr r3, .L2506 + ldr r2, [r3, #468] + ldr r3, .L2506 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2506 + strb r3, [r2, #108] +.L2502: + ldr r3, .L2506 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2506 + str r2, [r3, #72] + ldr r2, .L2506 + ldr r3, .L2506 + str r3, [r2, #104] + ldr r3, .L2506 + ldr r2, [r3, #104] + ldr r3, .L2506 + str r2, [r3, #100] + b .L2505 +.L2500: + ldr r2, .L2506 + ldr r3, .L2506+8 + str r3, [r2, #104] + ldr r3, .L2506 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2506 + str r2, [r3, #60] +.L2505: + ldmib sp, {fp, sp, pc} +.L2507: + .align 2 +.L2506: + .word GSU + .word GSU+56 + .word GSU+16 + .size _Z10fx_from_r4v, .-_Z10fx_from_r4v + .align 2 + .type _Z10fx_from_r5v, %function +_Z10fx_from_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2515 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2509 + ldr r3, .L2515 + ldr r3, [r3, #20] + str r3, [fp, #-16] + ldr r3, .L2515 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2515 + str r2, [r3, #60] + ldr r3, .L2515 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2515 + str r2, [r3, #128] + ldr r2, .L2515 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2515 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2515 + ldr r2, [r3, #100] + ldr r3, .L2515+4 + cmp r2, r3 + bne .L2511 + ldr r3, .L2515 + ldr r2, [r3, #468] + ldr r3, .L2515 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2515 + strb r3, [r2, #108] +.L2511: + ldr r3, .L2515 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2515 + str r2, [r3, #72] + ldr r2, .L2515 + ldr r3, .L2515 + str r3, [r2, #104] + ldr r3, .L2515 + ldr r2, [r3, #104] + ldr r3, .L2515 + str r2, [r3, #100] + b .L2514 +.L2509: + ldr r2, .L2515 + ldr r3, .L2515+8 + str r3, [r2, #104] + ldr r3, .L2515 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2515 + str r2, [r3, #60] +.L2514: + ldmib sp, {fp, sp, pc} +.L2516: + .align 2 +.L2515: + .word GSU + .word GSU+56 + .word GSU+20 + .size _Z10fx_from_r5v, .-_Z10fx_from_r5v + .align 2 + .type _Z10fx_from_r6v, %function +_Z10fx_from_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2524 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2518 + ldr r3, .L2524 + ldr r3, [r3, #24] + str r3, [fp, #-16] + ldr r3, .L2524 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2524 + str r2, [r3, #60] + ldr r3, .L2524 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2524 + str r2, [r3, #128] + ldr r2, .L2524 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2524 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2524 + ldr r2, [r3, #100] + ldr r3, .L2524+4 + cmp r2, r3 + bne .L2520 + ldr r3, .L2524 + ldr r2, [r3, #468] + ldr r3, .L2524 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2524 + strb r3, [r2, #108] +.L2520: + ldr r3, .L2524 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2524 + str r2, [r3, #72] + ldr r2, .L2524 + ldr r3, .L2524 + str r3, [r2, #104] + ldr r3, .L2524 + ldr r2, [r3, #104] + ldr r3, .L2524 + str r2, [r3, #100] + b .L2523 +.L2518: + ldr r2, .L2524 + ldr r3, .L2524+8 + str r3, [r2, #104] + ldr r3, .L2524 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2524 + str r2, [r3, #60] +.L2523: + ldmib sp, {fp, sp, pc} +.L2525: + .align 2 +.L2524: + .word GSU + .word GSU+56 + .word GSU+24 + .size _Z10fx_from_r6v, .-_Z10fx_from_r6v + .align 2 + .type _Z10fx_from_r7v, %function +_Z10fx_from_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2533 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2527 + ldr r3, .L2533 + ldr r3, [r3, #28] + str r3, [fp, #-16] + ldr r3, .L2533 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2533 + str r2, [r3, #60] + ldr r3, .L2533 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2533 + str r2, [r3, #128] + ldr r2, .L2533 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2533 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2533 + ldr r2, [r3, #100] + ldr r3, .L2533+4 + cmp r2, r3 + bne .L2529 + ldr r3, .L2533 + ldr r2, [r3, #468] + ldr r3, .L2533 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2533 + strb r3, [r2, #108] +.L2529: + ldr r3, .L2533 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2533 + str r2, [r3, #72] + ldr r2, .L2533 + ldr r3, .L2533 + str r3, [r2, #104] + ldr r3, .L2533 + ldr r2, [r3, #104] + ldr r3, .L2533 + str r2, [r3, #100] + b .L2532 +.L2527: + ldr r2, .L2533 + ldr r3, .L2533+8 + str r3, [r2, #104] + ldr r3, .L2533 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2533 + str r2, [r3, #60] +.L2532: + ldmib sp, {fp, sp, pc} +.L2534: + .align 2 +.L2533: + .word GSU + .word GSU+56 + .word GSU+28 + .size _Z10fx_from_r7v, .-_Z10fx_from_r7v + .align 2 + .type _Z10fx_from_r8v, %function +_Z10fx_from_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2542 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2536 + ldr r3, .L2542 + ldr r3, [r3, #32] + str r3, [fp, #-16] + ldr r3, .L2542 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2542 + str r2, [r3, #60] + ldr r3, .L2542 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2542 + str r2, [r3, #128] + ldr r2, .L2542 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2542 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2542 + ldr r2, [r3, #100] + ldr r3, .L2542+4 + cmp r2, r3 + bne .L2538 + ldr r3, .L2542 + ldr r2, [r3, #468] + ldr r3, .L2542 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2542 + strb r3, [r2, #108] +.L2538: + ldr r3, .L2542 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2542 + str r2, [r3, #72] + ldr r2, .L2542 + ldr r3, .L2542 + str r3, [r2, #104] + ldr r3, .L2542 + ldr r2, [r3, #104] + ldr r3, .L2542 + str r2, [r3, #100] + b .L2541 +.L2536: + ldr r2, .L2542 + ldr r3, .L2542+8 + str r3, [r2, #104] + ldr r3, .L2542 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2542 + str r2, [r3, #60] +.L2541: + ldmib sp, {fp, sp, pc} +.L2543: + .align 2 +.L2542: + .word GSU + .word GSU+56 + .word GSU+32 + .size _Z10fx_from_r8v, .-_Z10fx_from_r8v + .align 2 + .type _Z10fx_from_r9v, %function +_Z10fx_from_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2551 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2545 + ldr r3, .L2551 + ldr r3, [r3, #36] + str r3, [fp, #-16] + ldr r3, .L2551 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2551 + str r2, [r3, #60] + ldr r3, .L2551 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2551 + str r2, [r3, #128] + ldr r2, .L2551 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2551 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2551 + ldr r2, [r3, #100] + ldr r3, .L2551+4 + cmp r2, r3 + bne .L2547 + ldr r3, .L2551 + ldr r2, [r3, #468] + ldr r3, .L2551 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2551 + strb r3, [r2, #108] +.L2547: + ldr r3, .L2551 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2551 + str r2, [r3, #72] + ldr r2, .L2551 + ldr r3, .L2551 + str r3, [r2, #104] + ldr r3, .L2551 + ldr r2, [r3, #104] + ldr r3, .L2551 + str r2, [r3, #100] + b .L2550 +.L2545: + ldr r2, .L2551 + ldr r3, .L2551+8 + str r3, [r2, #104] + ldr r3, .L2551 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2551 + str r2, [r3, #60] +.L2550: + ldmib sp, {fp, sp, pc} +.L2552: + .align 2 +.L2551: + .word GSU + .word GSU+56 + .word GSU+36 + .size _Z10fx_from_r9v, .-_Z10fx_from_r9v + .align 2 + .type _Z11fx_from_r10v, %function +_Z11fx_from_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2560 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2554 + ldr r3, .L2560 + ldr r3, [r3, #40] + str r3, [fp, #-16] + ldr r3, .L2560 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2560 + str r2, [r3, #60] + ldr r3, .L2560 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2560 + str r2, [r3, #128] + ldr r2, .L2560 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2560 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2560 + ldr r2, [r3, #100] + ldr r3, .L2560+4 + cmp r2, r3 + bne .L2556 + ldr r3, .L2560 + ldr r2, [r3, #468] + ldr r3, .L2560 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2560 + strb r3, [r2, #108] +.L2556: + ldr r3, .L2560 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2560 + str r2, [r3, #72] + ldr r2, .L2560 + ldr r3, .L2560 + str r3, [r2, #104] + ldr r3, .L2560 + ldr r2, [r3, #104] + ldr r3, .L2560 + str r2, [r3, #100] + b .L2559 +.L2554: + ldr r2, .L2560 + ldr r3, .L2560+8 + str r3, [r2, #104] + ldr r3, .L2560 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2560 + str r2, [r3, #60] +.L2559: + ldmib sp, {fp, sp, pc} +.L2561: + .align 2 +.L2560: + .word GSU + .word GSU+56 + .word GSU+40 + .size _Z11fx_from_r10v, .-_Z11fx_from_r10v + .align 2 + .type _Z11fx_from_r11v, %function +_Z11fx_from_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2569 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2563 + ldr r3, .L2569 + ldr r3, [r3, #44] + str r3, [fp, #-16] + ldr r3, .L2569 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2569 + str r2, [r3, #60] + ldr r3, .L2569 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2569 + str r2, [r3, #128] + ldr r2, .L2569 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2569 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2569 + ldr r2, [r3, #100] + ldr r3, .L2569+4 + cmp r2, r3 + bne .L2565 + ldr r3, .L2569 + ldr r2, [r3, #468] + ldr r3, .L2569 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2569 + strb r3, [r2, #108] +.L2565: + ldr r3, .L2569 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2569 + str r2, [r3, #72] + ldr r2, .L2569 + ldr r3, .L2569 + str r3, [r2, #104] + ldr r3, .L2569 + ldr r2, [r3, #104] + ldr r3, .L2569 + str r2, [r3, #100] + b .L2568 +.L2563: + ldr r2, .L2569 + ldr r3, .L2569+8 + str r3, [r2, #104] + ldr r3, .L2569 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2569 + str r2, [r3, #60] +.L2568: + ldmib sp, {fp, sp, pc} +.L2570: + .align 2 +.L2569: + .word GSU + .word GSU+56 + .word GSU+44 + .size _Z11fx_from_r11v, .-_Z11fx_from_r11v + .align 2 + .type _Z11fx_from_r12v, %function +_Z11fx_from_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2578 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2572 + ldr r3, .L2578 + ldr r3, [r3, #48] + str r3, [fp, #-16] + ldr r3, .L2578 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2578 + str r2, [r3, #60] + ldr r3, .L2578 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2578 + str r2, [r3, #128] + ldr r2, .L2578 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2578 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2578 + ldr r2, [r3, #100] + ldr r3, .L2578+4 + cmp r2, r3 + bne .L2574 + ldr r3, .L2578 + ldr r2, [r3, #468] + ldr r3, .L2578 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2578 + strb r3, [r2, #108] +.L2574: + ldr r3, .L2578 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2578 + str r2, [r3, #72] + ldr r2, .L2578 + ldr r3, .L2578 + str r3, [r2, #104] + ldr r3, .L2578 + ldr r2, [r3, #104] + ldr r3, .L2578 + str r2, [r3, #100] + b .L2577 +.L2572: + ldr r2, .L2578 + ldr r3, .L2578+8 + str r3, [r2, #104] + ldr r3, .L2578 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2578 + str r2, [r3, #60] +.L2577: + ldmib sp, {fp, sp, pc} +.L2579: + .align 2 +.L2578: + .word GSU + .word GSU+56 + .word GSU+48 + .size _Z11fx_from_r12v, .-_Z11fx_from_r12v + .align 2 + .type _Z11fx_from_r13v, %function +_Z11fx_from_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2587 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2581 + ldr r3, .L2587 + ldr r3, [r3, #52] + str r3, [fp, #-16] + ldr r3, .L2587 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2587 + str r2, [r3, #60] + ldr r3, .L2587 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2587 + str r2, [r3, #128] + ldr r2, .L2587 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2587 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2587 + ldr r2, [r3, #100] + ldr r3, .L2587+4 + cmp r2, r3 + bne .L2583 + ldr r3, .L2587 + ldr r2, [r3, #468] + ldr r3, .L2587 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2587 + strb r3, [r2, #108] +.L2583: + ldr r3, .L2587 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2587 + str r2, [r3, #72] + ldr r2, .L2587 + ldr r3, .L2587 + str r3, [r2, #104] + ldr r3, .L2587 + ldr r2, [r3, #104] + ldr r3, .L2587 + str r2, [r3, #100] + b .L2586 +.L2581: + ldr r2, .L2587 + ldr r3, .L2587+8 + str r3, [r2, #104] + ldr r3, .L2587 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2587 + str r2, [r3, #60] +.L2586: + ldmib sp, {fp, sp, pc} +.L2588: + .align 2 +.L2587: + .word GSU + .word GSU+56 + .word GSU+52 + .size _Z11fx_from_r13v, .-_Z11fx_from_r13v + .align 2 + .type _Z11fx_from_r14v, %function +_Z11fx_from_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2596 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2590 + ldr r3, .L2596 + ldr r3, [r3, #56] + str r3, [fp, #-16] + ldr r3, .L2596 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2596 + str r2, [r3, #60] + ldr r3, .L2596 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2596 + str r2, [r3, #128] + ldr r2, .L2596 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2596 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2596 + ldr r2, [r3, #100] + ldr r3, .L2596+4 + cmp r2, r3 + bne .L2592 + ldr r3, .L2596 + ldr r2, [r3, #468] + ldr r3, .L2596 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2596 + strb r3, [r2, #108] +.L2592: + ldr r3, .L2596 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2596 + str r2, [r3, #72] + ldr r2, .L2596 + ldr r3, .L2596 + str r3, [r2, #104] + ldr r3, .L2596 + ldr r2, [r3, #104] + ldr r3, .L2596 + str r2, [r3, #100] + b .L2595 +.L2590: + ldr r2, .L2596 + ldr r3, .L2596+4 + str r3, [r2, #104] + ldr r3, .L2596 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2596 + str r2, [r3, #60] +.L2595: + ldmib sp, {fp, sp, pc} +.L2597: + .align 2 +.L2596: + .word GSU + .word GSU+56 + .size _Z11fx_from_r14v, .-_Z11fx_from_r14v + .align 2 + .type _Z11fx_from_r15v, %function +_Z11fx_from_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2605 + ldr r3, [r3, #72] + and r3, r3, #4096 + cmp r3, #0 + beq .L2599 + ldr r3, .L2605 + ldr r3, [r3, #60] + str r3, [fp, #-16] + ldr r3, .L2605 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2605 + str r2, [r3, #60] + ldr r3, .L2605 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + and r3, r3, #128 + mov r3, r3, asl #16 + mov r2, r3 + ldr r3, .L2605 + str r2, [r3, #128] + ldr r2, .L2605 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2605 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2605 + ldr r2, [r3, #100] + ldr r3, .L2605+4 + cmp r2, r3 + bne .L2601 + ldr r3, .L2605 + ldr r2, [r3, #468] + ldr r3, .L2605 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2605 + strb r3, [r2, #108] +.L2601: + ldr r3, .L2605 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2605 + str r2, [r3, #72] + ldr r2, .L2605 + ldr r3, .L2605 + str r3, [r2, #104] + ldr r3, .L2605 + ldr r2, [r3, #104] + ldr r3, .L2605 + str r2, [r3, #100] + b .L2604 +.L2599: + ldr r2, .L2605 + ldr r3, .L2605+8 + str r3, [r2, #104] + ldr r3, .L2605 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2605 + str r2, [r3, #60] +.L2604: + ldmib sp, {fp, sp, pc} +.L2606: + .align 2 +.L2605: + .word GSU + .word GSU+56 + .word GSU+60 + .size _Z11fx_from_r15v, .-_Z11fx_from_r15v + .align 2 + .type _Z6fx_hibv, %function +_Z6fx_hibv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2611 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + mov r3, r3, lsr #8 + and r3, r3, #255 + str r3, [fp, #-16] + ldr r3, .L2611 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2611 + str r2, [r3, #60] + ldr r3, .L2611 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, [fp, #-16] + mov r2, r3, asl #8 + ldr r3, .L2611 + str r2, [r3, #116] + ldr r3, [fp, #-16] + mov r2, r3, asl #8 + ldr r3, .L2611 + str r2, [r3, #120] + ldr r3, .L2611 + ldr r2, [r3, #100] + ldr r3, .L2611+4 + cmp r2, r3 + bne .L2608 + ldr r3, .L2611 + ldr r2, [r3, #468] + ldr r3, .L2611 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2611 + strb r3, [r2, #108] +.L2608: + ldr r3, .L2611 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2611 + str r2, [r3, #72] + ldr r2, .L2611 + ldr r3, .L2611 + str r3, [r2, #104] + ldr r3, .L2611 + ldr r2, [r3, #104] + ldr r3, .L2611 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2612: + .align 2 +.L2611: + .word GSU + .word GSU+56 + .size _Z6fx_hibv, .-_Z6fx_hibv + .align 2 + .type _Z8fx_or_r1v, %function +_Z8fx_or_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2617 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2617 + ldr r3, [r3, #4] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2617 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2617 + str r2, [r3, #60] + ldr r3, .L2617 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2617 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2617 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2617 + ldr r2, [r3, #100] + ldr r3, .L2617+4 + cmp r2, r3 + bne .L2614 + ldr r3, .L2617 + ldr r2, [r3, #468] + ldr r3, .L2617 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2617 + strb r3, [r2, #108] +.L2614: + ldr r3, .L2617 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2617 + str r2, [r3, #72] + ldr r2, .L2617 + ldr r3, .L2617 + str r3, [r2, #104] + ldr r3, .L2617 + ldr r2, [r3, #104] + ldr r3, .L2617 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2618: + .align 2 +.L2617: + .word GSU + .word GSU+56 + .size _Z8fx_or_r1v, .-_Z8fx_or_r1v + .align 2 + .type _Z8fx_or_r2v, %function +_Z8fx_or_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2623 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2623 + ldr r3, [r3, #8] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2623 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2623 + str r2, [r3, #60] + ldr r3, .L2623 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2623 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2623 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2623 + ldr r2, [r3, #100] + ldr r3, .L2623+4 + cmp r2, r3 + bne .L2620 + ldr r3, .L2623 + ldr r2, [r3, #468] + ldr r3, .L2623 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2623 + strb r3, [r2, #108] +.L2620: + ldr r3, .L2623 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2623 + str r2, [r3, #72] + ldr r2, .L2623 + ldr r3, .L2623 + str r3, [r2, #104] + ldr r3, .L2623 + ldr r2, [r3, #104] + ldr r3, .L2623 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2624: + .align 2 +.L2623: + .word GSU + .word GSU+56 + .size _Z8fx_or_r2v, .-_Z8fx_or_r2v + .align 2 + .type _Z8fx_or_r3v, %function +_Z8fx_or_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2629 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2629 + ldr r3, [r3, #12] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2629 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2629 + str r2, [r3, #60] + ldr r3, .L2629 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2629 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2629 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2629 + ldr r2, [r3, #100] + ldr r3, .L2629+4 + cmp r2, r3 + bne .L2626 + ldr r3, .L2629 + ldr r2, [r3, #468] + ldr r3, .L2629 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2629 + strb r3, [r2, #108] +.L2626: + ldr r3, .L2629 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2629 + str r2, [r3, #72] + ldr r2, .L2629 + ldr r3, .L2629 + str r3, [r2, #104] + ldr r3, .L2629 + ldr r2, [r3, #104] + ldr r3, .L2629 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2630: + .align 2 +.L2629: + .word GSU + .word GSU+56 + .size _Z8fx_or_r3v, .-_Z8fx_or_r3v + .align 2 + .type _Z8fx_or_r4v, %function +_Z8fx_or_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2635 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2635 + ldr r3, [r3, #16] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2635 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2635 + str r2, [r3, #60] + ldr r3, .L2635 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2635 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2635 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2635 + ldr r2, [r3, #100] + ldr r3, .L2635+4 + cmp r2, r3 + bne .L2632 + ldr r3, .L2635 + ldr r2, [r3, #468] + ldr r3, .L2635 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2635 + strb r3, [r2, #108] +.L2632: + ldr r3, .L2635 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2635 + str r2, [r3, #72] + ldr r2, .L2635 + ldr r3, .L2635 + str r3, [r2, #104] + ldr r3, .L2635 + ldr r2, [r3, #104] + ldr r3, .L2635 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2636: + .align 2 +.L2635: + .word GSU + .word GSU+56 + .size _Z8fx_or_r4v, .-_Z8fx_or_r4v + .align 2 + .type _Z8fx_or_r5v, %function +_Z8fx_or_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2641 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2641 + ldr r3, [r3, #20] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2641 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2641 + str r2, [r3, #60] + ldr r3, .L2641 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2641 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2641 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2641 + ldr r2, [r3, #100] + ldr r3, .L2641+4 + cmp r2, r3 + bne .L2638 + ldr r3, .L2641 + ldr r2, [r3, #468] + ldr r3, .L2641 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2641 + strb r3, [r2, #108] +.L2638: + ldr r3, .L2641 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2641 + str r2, [r3, #72] + ldr r2, .L2641 + ldr r3, .L2641 + str r3, [r2, #104] + ldr r3, .L2641 + ldr r2, [r3, #104] + ldr r3, .L2641 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2642: + .align 2 +.L2641: + .word GSU + .word GSU+56 + .size _Z8fx_or_r5v, .-_Z8fx_or_r5v + .align 2 + .type _Z8fx_or_r6v, %function +_Z8fx_or_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2647 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2647 + ldr r3, [r3, #24] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2647 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2647 + str r2, [r3, #60] + ldr r3, .L2647 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2647 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2647 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2647 + ldr r2, [r3, #100] + ldr r3, .L2647+4 + cmp r2, r3 + bne .L2644 + ldr r3, .L2647 + ldr r2, [r3, #468] + ldr r3, .L2647 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2647 + strb r3, [r2, #108] +.L2644: + ldr r3, .L2647 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2647 + str r2, [r3, #72] + ldr r2, .L2647 + ldr r3, .L2647 + str r3, [r2, #104] + ldr r3, .L2647 + ldr r2, [r3, #104] + ldr r3, .L2647 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2648: + .align 2 +.L2647: + .word GSU + .word GSU+56 + .size _Z8fx_or_r6v, .-_Z8fx_or_r6v + .align 2 + .type _Z8fx_or_r7v, %function +_Z8fx_or_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2653 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2653 + ldr r3, [r3, #28] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2653 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2653 + str r2, [r3, #60] + ldr r3, .L2653 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2653 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2653 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2653 + ldr r2, [r3, #100] + ldr r3, .L2653+4 + cmp r2, r3 + bne .L2650 + ldr r3, .L2653 + ldr r2, [r3, #468] + ldr r3, .L2653 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2653 + strb r3, [r2, #108] +.L2650: + ldr r3, .L2653 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2653 + str r2, [r3, #72] + ldr r2, .L2653 + ldr r3, .L2653 + str r3, [r2, #104] + ldr r3, .L2653 + ldr r2, [r3, #104] + ldr r3, .L2653 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2654: + .align 2 +.L2653: + .word GSU + .word GSU+56 + .size _Z8fx_or_r7v, .-_Z8fx_or_r7v + .align 2 + .type _Z8fx_or_r8v, %function +_Z8fx_or_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2659 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2659 + ldr r3, [r3, #32] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2659 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2659 + str r2, [r3, #60] + ldr r3, .L2659 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2659 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2659 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2659 + ldr r2, [r3, #100] + ldr r3, .L2659+4 + cmp r2, r3 + bne .L2656 + ldr r3, .L2659 + ldr r2, [r3, #468] + ldr r3, .L2659 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2659 + strb r3, [r2, #108] +.L2656: + ldr r3, .L2659 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2659 + str r2, [r3, #72] + ldr r2, .L2659 + ldr r3, .L2659 + str r3, [r2, #104] + ldr r3, .L2659 + ldr r2, [r3, #104] + ldr r3, .L2659 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2660: + .align 2 +.L2659: + .word GSU + .word GSU+56 + .size _Z8fx_or_r8v, .-_Z8fx_or_r8v + .align 2 + .type _Z8fx_or_r9v, %function +_Z8fx_or_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2665 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2665 + ldr r3, [r3, #36] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2665 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2665 + str r2, [r3, #60] + ldr r3, .L2665 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2665 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2665 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2665 + ldr r2, [r3, #100] + ldr r3, .L2665+4 + cmp r2, r3 + bne .L2662 + ldr r3, .L2665 + ldr r2, [r3, #468] + ldr r3, .L2665 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2665 + strb r3, [r2, #108] +.L2662: + ldr r3, .L2665 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2665 + str r2, [r3, #72] + ldr r2, .L2665 + ldr r3, .L2665 + str r3, [r2, #104] + ldr r3, .L2665 + ldr r2, [r3, #104] + ldr r3, .L2665 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2666: + .align 2 +.L2665: + .word GSU + .word GSU+56 + .size _Z8fx_or_r9v, .-_Z8fx_or_r9v + .align 2 + .type _Z9fx_or_r10v, %function +_Z9fx_or_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2671 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2671 + ldr r3, [r3, #40] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2671 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2671 + str r2, [r3, #60] + ldr r3, .L2671 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2671 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2671 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2671 + ldr r2, [r3, #100] + ldr r3, .L2671+4 + cmp r2, r3 + bne .L2668 + ldr r3, .L2671 + ldr r2, [r3, #468] + ldr r3, .L2671 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2671 + strb r3, [r2, #108] +.L2668: + ldr r3, .L2671 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2671 + str r2, [r3, #72] + ldr r2, .L2671 + ldr r3, .L2671 + str r3, [r2, #104] + ldr r3, .L2671 + ldr r2, [r3, #104] + ldr r3, .L2671 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2672: + .align 2 +.L2671: + .word GSU + .word GSU+56 + .size _Z9fx_or_r10v, .-_Z9fx_or_r10v + .align 2 + .type _Z9fx_or_r11v, %function +_Z9fx_or_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2677 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2677 + ldr r3, [r3, #44] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2677 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2677 + str r2, [r3, #60] + ldr r3, .L2677 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2677 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2677 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2677 + ldr r2, [r3, #100] + ldr r3, .L2677+4 + cmp r2, r3 + bne .L2674 + ldr r3, .L2677 + ldr r2, [r3, #468] + ldr r3, .L2677 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2677 + strb r3, [r2, #108] +.L2674: + ldr r3, .L2677 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2677 + str r2, [r3, #72] + ldr r2, .L2677 + ldr r3, .L2677 + str r3, [r2, #104] + ldr r3, .L2677 + ldr r2, [r3, #104] + ldr r3, .L2677 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2678: + .align 2 +.L2677: + .word GSU + .word GSU+56 + .size _Z9fx_or_r11v, .-_Z9fx_or_r11v + .align 2 + .type _Z9fx_or_r12v, %function +_Z9fx_or_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2683 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2683 + ldr r3, [r3, #48] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2683 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2683 + str r2, [r3, #60] + ldr r3, .L2683 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2683 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2683 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2683 + ldr r2, [r3, #100] + ldr r3, .L2683+4 + cmp r2, r3 + bne .L2680 + ldr r3, .L2683 + ldr r2, [r3, #468] + ldr r3, .L2683 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2683 + strb r3, [r2, #108] +.L2680: + ldr r3, .L2683 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2683 + str r2, [r3, #72] + ldr r2, .L2683 + ldr r3, .L2683 + str r3, [r2, #104] + ldr r3, .L2683 + ldr r2, [r3, #104] + ldr r3, .L2683 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2684: + .align 2 +.L2683: + .word GSU + .word GSU+56 + .size _Z9fx_or_r12v, .-_Z9fx_or_r12v + .align 2 + .type _Z9fx_or_r13v, %function +_Z9fx_or_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2689 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2689 + ldr r3, [r3, #52] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2689 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2689 + str r2, [r3, #60] + ldr r3, .L2689 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2689 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2689 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2689 + ldr r2, [r3, #100] + ldr r3, .L2689+4 + cmp r2, r3 + bne .L2686 + ldr r3, .L2689 + ldr r2, [r3, #468] + ldr r3, .L2689 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2689 + strb r3, [r2, #108] +.L2686: + ldr r3, .L2689 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2689 + str r2, [r3, #72] + ldr r2, .L2689 + ldr r3, .L2689 + str r3, [r2, #104] + ldr r3, .L2689 + ldr r2, [r3, #104] + ldr r3, .L2689 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2690: + .align 2 +.L2689: + .word GSU + .word GSU+56 + .size _Z9fx_or_r13v, .-_Z9fx_or_r13v + .align 2 + .type _Z9fx_or_r14v, %function +_Z9fx_or_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2695 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2695 + ldr r3, [r3, #56] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2695 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2695 + str r2, [r3, #60] + ldr r3, .L2695 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2695 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2695 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2695 + ldr r2, [r3, #100] + ldr r3, .L2695+4 + cmp r2, r3 + bne .L2692 + ldr r3, .L2695 + ldr r2, [r3, #468] + ldr r3, .L2695 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2695 + strb r3, [r2, #108] +.L2692: + ldr r3, .L2695 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2695 + str r2, [r3, #72] + ldr r2, .L2695 + ldr r3, .L2695 + str r3, [r2, #104] + ldr r3, .L2695 + ldr r2, [r3, #104] + ldr r3, .L2695 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2696: + .align 2 +.L2695: + .word GSU + .word GSU+56 + .size _Z9fx_or_r14v, .-_Z9fx_or_r14v + .align 2 + .type _Z9fx_or_r15v, %function +_Z9fx_or_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2701 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2701 + ldr r3, [r3, #60] + orr r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2701 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2701 + str r2, [r3, #60] + ldr r3, .L2701 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2701 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2701 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2701 + ldr r2, [r3, #100] + ldr r3, .L2701+4 + cmp r2, r3 + bne .L2698 + ldr r3, .L2701 + ldr r2, [r3, #468] + ldr r3, .L2701 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2701 + strb r3, [r2, #108] +.L2698: + ldr r3, .L2701 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2701 + str r2, [r3, #72] + ldr r2, .L2701 + ldr r3, .L2701 + str r3, [r2, #104] + ldr r3, .L2701 + ldr r2, [r3, #104] + ldr r3, .L2701 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2702: + .align 2 +.L2701: + .word GSU + .word GSU+56 + .size _Z9fx_or_r15v, .-_Z9fx_or_r15v + .align 2 + .type _Z9fx_xor_r1v, %function +_Z9fx_xor_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2707 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2707 + ldr r3, [r3, #4] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2707 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2707 + str r2, [r3, #60] + ldr r3, .L2707 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2707 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2707 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2707 + ldr r2, [r3, #100] + ldr r3, .L2707+4 + cmp r2, r3 + bne .L2704 + ldr r3, .L2707 + ldr r2, [r3, #468] + ldr r3, .L2707 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2707 + strb r3, [r2, #108] +.L2704: + ldr r3, .L2707 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2707 + str r2, [r3, #72] + ldr r2, .L2707 + ldr r3, .L2707 + str r3, [r2, #104] + ldr r3, .L2707 + ldr r2, [r3, #104] + ldr r3, .L2707 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2708: + .align 2 +.L2707: + .word GSU + .word GSU+56 + .size _Z9fx_xor_r1v, .-_Z9fx_xor_r1v + .align 2 + .type _Z9fx_xor_r2v, %function +_Z9fx_xor_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2713 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2713 + ldr r3, [r3, #8] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2713 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2713 + str r2, [r3, #60] + ldr r3, .L2713 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2713 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2713 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2713 + ldr r2, [r3, #100] + ldr r3, .L2713+4 + cmp r2, r3 + bne .L2710 + ldr r3, .L2713 + ldr r2, [r3, #468] + ldr r3, .L2713 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2713 + strb r3, [r2, #108] +.L2710: + ldr r3, .L2713 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2713 + str r2, [r3, #72] + ldr r2, .L2713 + ldr r3, .L2713 + str r3, [r2, #104] + ldr r3, .L2713 + ldr r2, [r3, #104] + ldr r3, .L2713 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2714: + .align 2 +.L2713: + .word GSU + .word GSU+56 + .size _Z9fx_xor_r2v, .-_Z9fx_xor_r2v + .align 2 + .type _Z9fx_xor_r3v, %function +_Z9fx_xor_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2719 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2719 + ldr r3, [r3, #12] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2719 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2719 + str r2, [r3, #60] + ldr r3, .L2719 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2719 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2719 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2719 + ldr r2, [r3, #100] + ldr r3, .L2719+4 + cmp r2, r3 + bne .L2716 + ldr r3, .L2719 + ldr r2, [r3, #468] + ldr r3, .L2719 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2719 + strb r3, [r2, #108] +.L2716: + ldr r3, .L2719 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2719 + str r2, [r3, #72] + ldr r2, .L2719 + ldr r3, .L2719 + str r3, [r2, #104] + ldr r3, .L2719 + ldr r2, [r3, #104] + ldr r3, .L2719 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2720: + .align 2 +.L2719: + .word GSU + .word GSU+56 + .size _Z9fx_xor_r3v, .-_Z9fx_xor_r3v + .align 2 + .type _Z9fx_xor_r4v, %function +_Z9fx_xor_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2725 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2725 + ldr r3, [r3, #16] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2725 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2725 + str r2, [r3, #60] + ldr r3, .L2725 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2725 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2725 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2725 + ldr r2, [r3, #100] + ldr r3, .L2725+4 + cmp r2, r3 + bne .L2722 + ldr r3, .L2725 + ldr r2, [r3, #468] + ldr r3, .L2725 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2725 + strb r3, [r2, #108] +.L2722: + ldr r3, .L2725 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2725 + str r2, [r3, #72] + ldr r2, .L2725 + ldr r3, .L2725 + str r3, [r2, #104] + ldr r3, .L2725 + ldr r2, [r3, #104] + ldr r3, .L2725 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2726: + .align 2 +.L2725: + .word GSU + .word GSU+56 + .size _Z9fx_xor_r4v, .-_Z9fx_xor_r4v + .align 2 + .type _Z9fx_xor_r5v, %function +_Z9fx_xor_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2731 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2731 + ldr r3, [r3, #20] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2731 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2731 + str r2, [r3, #60] + ldr r3, .L2731 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2731 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2731 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2731 + ldr r2, [r3, #100] + ldr r3, .L2731+4 + cmp r2, r3 + bne .L2728 + ldr r3, .L2731 + ldr r2, [r3, #468] + ldr r3, .L2731 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2731 + strb r3, [r2, #108] +.L2728: + ldr r3, .L2731 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2731 + str r2, [r3, #72] + ldr r2, .L2731 + ldr r3, .L2731 + str r3, [r2, #104] + ldr r3, .L2731 + ldr r2, [r3, #104] + ldr r3, .L2731 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2732: + .align 2 +.L2731: + .word GSU + .word GSU+56 + .size _Z9fx_xor_r5v, .-_Z9fx_xor_r5v + .align 2 + .type _Z9fx_xor_r6v, %function +_Z9fx_xor_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2737 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2737 + ldr r3, [r3, #24] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2737 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2737 + str r2, [r3, #60] + ldr r3, .L2737 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2737 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2737 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2737 + ldr r2, [r3, #100] + ldr r3, .L2737+4 + cmp r2, r3 + bne .L2734 + ldr r3, .L2737 + ldr r2, [r3, #468] + ldr r3, .L2737 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2737 + strb r3, [r2, #108] +.L2734: + ldr r3, .L2737 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2737 + str r2, [r3, #72] + ldr r2, .L2737 + ldr r3, .L2737 + str r3, [r2, #104] + ldr r3, .L2737 + ldr r2, [r3, #104] + ldr r3, .L2737 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2738: + .align 2 +.L2737: + .word GSU + .word GSU+56 + .size _Z9fx_xor_r6v, .-_Z9fx_xor_r6v + .align 2 + .type _Z9fx_xor_r7v, %function +_Z9fx_xor_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2743 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2743 + ldr r3, [r3, #28] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2743 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2743 + str r2, [r3, #60] + ldr r3, .L2743 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2743 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2743 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2743 + ldr r2, [r3, #100] + ldr r3, .L2743+4 + cmp r2, r3 + bne .L2740 + ldr r3, .L2743 + ldr r2, [r3, #468] + ldr r3, .L2743 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2743 + strb r3, [r2, #108] +.L2740: + ldr r3, .L2743 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2743 + str r2, [r3, #72] + ldr r2, .L2743 + ldr r3, .L2743 + str r3, [r2, #104] + ldr r3, .L2743 + ldr r2, [r3, #104] + ldr r3, .L2743 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2744: + .align 2 +.L2743: + .word GSU + .word GSU+56 + .size _Z9fx_xor_r7v, .-_Z9fx_xor_r7v + .align 2 + .type _Z9fx_xor_r8v, %function +_Z9fx_xor_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2749 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2749 + ldr r3, [r3, #32] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2749 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2749 + str r2, [r3, #60] + ldr r3, .L2749 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2749 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2749 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2749 + ldr r2, [r3, #100] + ldr r3, .L2749+4 + cmp r2, r3 + bne .L2746 + ldr r3, .L2749 + ldr r2, [r3, #468] + ldr r3, .L2749 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2749 + strb r3, [r2, #108] +.L2746: + ldr r3, .L2749 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2749 + str r2, [r3, #72] + ldr r2, .L2749 + ldr r3, .L2749 + str r3, [r2, #104] + ldr r3, .L2749 + ldr r2, [r3, #104] + ldr r3, .L2749 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2750: + .align 2 +.L2749: + .word GSU + .word GSU+56 + .size _Z9fx_xor_r8v, .-_Z9fx_xor_r8v + .align 2 + .type _Z9fx_xor_r9v, %function +_Z9fx_xor_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2755 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2755 + ldr r3, [r3, #36] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2755 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2755 + str r2, [r3, #60] + ldr r3, .L2755 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2755 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2755 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2755 + ldr r2, [r3, #100] + ldr r3, .L2755+4 + cmp r2, r3 + bne .L2752 + ldr r3, .L2755 + ldr r2, [r3, #468] + ldr r3, .L2755 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2755 + strb r3, [r2, #108] +.L2752: + ldr r3, .L2755 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2755 + str r2, [r3, #72] + ldr r2, .L2755 + ldr r3, .L2755 + str r3, [r2, #104] + ldr r3, .L2755 + ldr r2, [r3, #104] + ldr r3, .L2755 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2756: + .align 2 +.L2755: + .word GSU + .word GSU+56 + .size _Z9fx_xor_r9v, .-_Z9fx_xor_r9v + .align 2 + .type _Z10fx_xor_r10v, %function +_Z10fx_xor_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2761 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2761 + ldr r3, [r3, #40] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2761 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2761 + str r2, [r3, #60] + ldr r3, .L2761 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2761 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2761 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2761 + ldr r2, [r3, #100] + ldr r3, .L2761+4 + cmp r2, r3 + bne .L2758 + ldr r3, .L2761 + ldr r2, [r3, #468] + ldr r3, .L2761 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2761 + strb r3, [r2, #108] +.L2758: + ldr r3, .L2761 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2761 + str r2, [r3, #72] + ldr r2, .L2761 + ldr r3, .L2761 + str r3, [r2, #104] + ldr r3, .L2761 + ldr r2, [r3, #104] + ldr r3, .L2761 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2762: + .align 2 +.L2761: + .word GSU + .word GSU+56 + .size _Z10fx_xor_r10v, .-_Z10fx_xor_r10v + .align 2 + .type _Z10fx_xor_r11v, %function +_Z10fx_xor_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2767 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2767 + ldr r3, [r3, #44] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2767 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2767 + str r2, [r3, #60] + ldr r3, .L2767 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2767 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2767 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2767 + ldr r2, [r3, #100] + ldr r3, .L2767+4 + cmp r2, r3 + bne .L2764 + ldr r3, .L2767 + ldr r2, [r3, #468] + ldr r3, .L2767 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2767 + strb r3, [r2, #108] +.L2764: + ldr r3, .L2767 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2767 + str r2, [r3, #72] + ldr r2, .L2767 + ldr r3, .L2767 + str r3, [r2, #104] + ldr r3, .L2767 + ldr r2, [r3, #104] + ldr r3, .L2767 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2768: + .align 2 +.L2767: + .word GSU + .word GSU+56 + .size _Z10fx_xor_r11v, .-_Z10fx_xor_r11v + .align 2 + .type _Z10fx_xor_r12v, %function +_Z10fx_xor_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2773 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2773 + ldr r3, [r3, #48] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2773 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2773 + str r2, [r3, #60] + ldr r3, .L2773 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2773 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2773 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2773 + ldr r2, [r3, #100] + ldr r3, .L2773+4 + cmp r2, r3 + bne .L2770 + ldr r3, .L2773 + ldr r2, [r3, #468] + ldr r3, .L2773 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2773 + strb r3, [r2, #108] +.L2770: + ldr r3, .L2773 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2773 + str r2, [r3, #72] + ldr r2, .L2773 + ldr r3, .L2773 + str r3, [r2, #104] + ldr r3, .L2773 + ldr r2, [r3, #104] + ldr r3, .L2773 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2774: + .align 2 +.L2773: + .word GSU + .word GSU+56 + .size _Z10fx_xor_r12v, .-_Z10fx_xor_r12v + .align 2 + .type _Z10fx_xor_r13v, %function +_Z10fx_xor_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2779 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2779 + ldr r3, [r3, #52] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2779 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2779 + str r2, [r3, #60] + ldr r3, .L2779 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2779 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2779 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2779 + ldr r2, [r3, #100] + ldr r3, .L2779+4 + cmp r2, r3 + bne .L2776 + ldr r3, .L2779 + ldr r2, [r3, #468] + ldr r3, .L2779 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2779 + strb r3, [r2, #108] +.L2776: + ldr r3, .L2779 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2779 + str r2, [r3, #72] + ldr r2, .L2779 + ldr r3, .L2779 + str r3, [r2, #104] + ldr r3, .L2779 + ldr r2, [r3, #104] + ldr r3, .L2779 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2780: + .align 2 +.L2779: + .word GSU + .word GSU+56 + .size _Z10fx_xor_r13v, .-_Z10fx_xor_r13v + .align 2 + .type _Z10fx_xor_r14v, %function +_Z10fx_xor_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2785 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2785 + ldr r3, [r3, #56] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2785 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2785 + str r2, [r3, #60] + ldr r3, .L2785 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2785 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2785 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2785 + ldr r2, [r3, #100] + ldr r3, .L2785+4 + cmp r2, r3 + bne .L2782 + ldr r3, .L2785 + ldr r2, [r3, #468] + ldr r3, .L2785 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2785 + strb r3, [r2, #108] +.L2782: + ldr r3, .L2785 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2785 + str r2, [r3, #72] + ldr r2, .L2785 + ldr r3, .L2785 + str r3, [r2, #104] + ldr r3, .L2785 + ldr r2, [r3, #104] + ldr r3, .L2785 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2786: + .align 2 +.L2785: + .word GSU + .word GSU+56 + .size _Z10fx_xor_r14v, .-_Z10fx_xor_r14v + .align 2 + .type _Z10fx_xor_r15v, %function +_Z10fx_xor_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2791 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L2791 + ldr r3, [r3, #60] + eor r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L2791 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2791 + str r2, [r3, #60] + ldr r3, .L2791 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2791 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2791 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2791 + ldr r2, [r3, #100] + ldr r3, .L2791+4 + cmp r2, r3 + bne .L2788 + ldr r3, .L2791 + ldr r2, [r3, #468] + ldr r3, .L2791 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2791 + strb r3, [r2, #108] +.L2788: + ldr r3, .L2791 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2791 + str r2, [r3, #72] + ldr r2, .L2791 + ldr r3, .L2791 + str r3, [r2, #104] + ldr r3, .L2791 + ldr r2, [r3, #104] + ldr r3, .L2791 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2792: + .align 2 +.L2791: + .word GSU + .word GSU+56 + .size _Z10fx_xor_r15v, .-_Z10fx_xor_r15v + .align 2 + .type _Z8fx_or_i1v, %function +_Z8fx_or_i1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2797 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #1 + str r3, [fp, #-16] + ldr r3, .L2797 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2797 + str r2, [r3, #60] + ldr r3, .L2797 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2797 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2797 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2797 + ldr r2, [r3, #100] + ldr r3, .L2797+4 + cmp r2, r3 + bne .L2794 + ldr r3, .L2797 + ldr r2, [r3, #468] + ldr r3, .L2797 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2797 + strb r3, [r2, #108] +.L2794: + ldr r3, .L2797 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2797 + str r2, [r3, #72] + ldr r2, .L2797 + ldr r3, .L2797 + str r3, [r2, #104] + ldr r3, .L2797 + ldr r2, [r3, #104] + ldr r3, .L2797 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2798: + .align 2 +.L2797: + .word GSU + .word GSU+56 + .size _Z8fx_or_i1v, .-_Z8fx_or_i1v + .align 2 + .type _Z8fx_or_i2v, %function +_Z8fx_or_i2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2803 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #2 + str r3, [fp, #-16] + ldr r3, .L2803 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2803 + str r2, [r3, #60] + ldr r3, .L2803 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2803 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2803 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2803 + ldr r2, [r3, #100] + ldr r3, .L2803+4 + cmp r2, r3 + bne .L2800 + ldr r3, .L2803 + ldr r2, [r3, #468] + ldr r3, .L2803 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2803 + strb r3, [r2, #108] +.L2800: + ldr r3, .L2803 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2803 + str r2, [r3, #72] + ldr r2, .L2803 + ldr r3, .L2803 + str r3, [r2, #104] + ldr r3, .L2803 + ldr r2, [r3, #104] + ldr r3, .L2803 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2804: + .align 2 +.L2803: + .word GSU + .word GSU+56 + .size _Z8fx_or_i2v, .-_Z8fx_or_i2v + .align 2 + .type _Z8fx_or_i3v, %function +_Z8fx_or_i3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2809 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #3 + str r3, [fp, #-16] + ldr r3, .L2809 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2809 + str r2, [r3, #60] + ldr r3, .L2809 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2809 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2809 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2809 + ldr r2, [r3, #100] + ldr r3, .L2809+4 + cmp r2, r3 + bne .L2806 + ldr r3, .L2809 + ldr r2, [r3, #468] + ldr r3, .L2809 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2809 + strb r3, [r2, #108] +.L2806: + ldr r3, .L2809 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2809 + str r2, [r3, #72] + ldr r2, .L2809 + ldr r3, .L2809 + str r3, [r2, #104] + ldr r3, .L2809 + ldr r2, [r3, #104] + ldr r3, .L2809 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2810: + .align 2 +.L2809: + .word GSU + .word GSU+56 + .size _Z8fx_or_i3v, .-_Z8fx_or_i3v + .align 2 + .type _Z8fx_or_i4v, %function +_Z8fx_or_i4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2815 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #4 + str r3, [fp, #-16] + ldr r3, .L2815 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2815 + str r2, [r3, #60] + ldr r3, .L2815 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2815 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2815 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2815 + ldr r2, [r3, #100] + ldr r3, .L2815+4 + cmp r2, r3 + bne .L2812 + ldr r3, .L2815 + ldr r2, [r3, #468] + ldr r3, .L2815 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2815 + strb r3, [r2, #108] +.L2812: + ldr r3, .L2815 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2815 + str r2, [r3, #72] + ldr r2, .L2815 + ldr r3, .L2815 + str r3, [r2, #104] + ldr r3, .L2815 + ldr r2, [r3, #104] + ldr r3, .L2815 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2816: + .align 2 +.L2815: + .word GSU + .word GSU+56 + .size _Z8fx_or_i4v, .-_Z8fx_or_i4v + .align 2 + .type _Z8fx_or_i5v, %function +_Z8fx_or_i5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2821 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #5 + str r3, [fp, #-16] + ldr r3, .L2821 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2821 + str r2, [r3, #60] + ldr r3, .L2821 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2821 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2821 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2821 + ldr r2, [r3, #100] + ldr r3, .L2821+4 + cmp r2, r3 + bne .L2818 + ldr r3, .L2821 + ldr r2, [r3, #468] + ldr r3, .L2821 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2821 + strb r3, [r2, #108] +.L2818: + ldr r3, .L2821 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2821 + str r2, [r3, #72] + ldr r2, .L2821 + ldr r3, .L2821 + str r3, [r2, #104] + ldr r3, .L2821 + ldr r2, [r3, #104] + ldr r3, .L2821 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2822: + .align 2 +.L2821: + .word GSU + .word GSU+56 + .size _Z8fx_or_i5v, .-_Z8fx_or_i5v + .align 2 + .type _Z8fx_or_i6v, %function +_Z8fx_or_i6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2827 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #6 + str r3, [fp, #-16] + ldr r3, .L2827 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2827 + str r2, [r3, #60] + ldr r3, .L2827 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2827 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2827 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2827 + ldr r2, [r3, #100] + ldr r3, .L2827+4 + cmp r2, r3 + bne .L2824 + ldr r3, .L2827 + ldr r2, [r3, #468] + ldr r3, .L2827 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2827 + strb r3, [r2, #108] +.L2824: + ldr r3, .L2827 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2827 + str r2, [r3, #72] + ldr r2, .L2827 + ldr r3, .L2827 + str r3, [r2, #104] + ldr r3, .L2827 + ldr r2, [r3, #104] + ldr r3, .L2827 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2828: + .align 2 +.L2827: + .word GSU + .word GSU+56 + .size _Z8fx_or_i6v, .-_Z8fx_or_i6v + .align 2 + .type _Z8fx_or_i7v, %function +_Z8fx_or_i7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2833 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #7 + str r3, [fp, #-16] + ldr r3, .L2833 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2833 + str r2, [r3, #60] + ldr r3, .L2833 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2833 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2833 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2833 + ldr r2, [r3, #100] + ldr r3, .L2833+4 + cmp r2, r3 + bne .L2830 + ldr r3, .L2833 + ldr r2, [r3, #468] + ldr r3, .L2833 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2833 + strb r3, [r2, #108] +.L2830: + ldr r3, .L2833 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2833 + str r2, [r3, #72] + ldr r2, .L2833 + ldr r3, .L2833 + str r3, [r2, #104] + ldr r3, .L2833 + ldr r2, [r3, #104] + ldr r3, .L2833 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2834: + .align 2 +.L2833: + .word GSU + .word GSU+56 + .size _Z8fx_or_i7v, .-_Z8fx_or_i7v + .align 2 + .type _Z8fx_or_i8v, %function +_Z8fx_or_i8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2839 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #8 + str r3, [fp, #-16] + ldr r3, .L2839 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2839 + str r2, [r3, #60] + ldr r3, .L2839 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2839 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2839 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2839 + ldr r2, [r3, #100] + ldr r3, .L2839+4 + cmp r2, r3 + bne .L2836 + ldr r3, .L2839 + ldr r2, [r3, #468] + ldr r3, .L2839 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2839 + strb r3, [r2, #108] +.L2836: + ldr r3, .L2839 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2839 + str r2, [r3, #72] + ldr r2, .L2839 + ldr r3, .L2839 + str r3, [r2, #104] + ldr r3, .L2839 + ldr r2, [r3, #104] + ldr r3, .L2839 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2840: + .align 2 +.L2839: + .word GSU + .word GSU+56 + .size _Z8fx_or_i8v, .-_Z8fx_or_i8v + .align 2 + .type _Z8fx_or_i9v, %function +_Z8fx_or_i9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2845 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #9 + str r3, [fp, #-16] + ldr r3, .L2845 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2845 + str r2, [r3, #60] + ldr r3, .L2845 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2845 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2845 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2845 + ldr r2, [r3, #100] + ldr r3, .L2845+4 + cmp r2, r3 + bne .L2842 + ldr r3, .L2845 + ldr r2, [r3, #468] + ldr r3, .L2845 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2845 + strb r3, [r2, #108] +.L2842: + ldr r3, .L2845 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2845 + str r2, [r3, #72] + ldr r2, .L2845 + ldr r3, .L2845 + str r3, [r2, #104] + ldr r3, .L2845 + ldr r2, [r3, #104] + ldr r3, .L2845 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2846: + .align 2 +.L2845: + .word GSU + .word GSU+56 + .size _Z8fx_or_i9v, .-_Z8fx_or_i9v + .align 2 + .type _Z9fx_or_i10v, %function +_Z9fx_or_i10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2851 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #10 + str r3, [fp, #-16] + ldr r3, .L2851 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2851 + str r2, [r3, #60] + ldr r3, .L2851 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2851 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2851 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2851 + ldr r2, [r3, #100] + ldr r3, .L2851+4 + cmp r2, r3 + bne .L2848 + ldr r3, .L2851 + ldr r2, [r3, #468] + ldr r3, .L2851 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2851 + strb r3, [r2, #108] +.L2848: + ldr r3, .L2851 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2851 + str r2, [r3, #72] + ldr r2, .L2851 + ldr r3, .L2851 + str r3, [r2, #104] + ldr r3, .L2851 + ldr r2, [r3, #104] + ldr r3, .L2851 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2852: + .align 2 +.L2851: + .word GSU + .word GSU+56 + .size _Z9fx_or_i10v, .-_Z9fx_or_i10v + .align 2 + .type _Z9fx_or_i11v, %function +_Z9fx_or_i11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2857 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #11 + str r3, [fp, #-16] + ldr r3, .L2857 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2857 + str r2, [r3, #60] + ldr r3, .L2857 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2857 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2857 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2857 + ldr r2, [r3, #100] + ldr r3, .L2857+4 + cmp r2, r3 + bne .L2854 + ldr r3, .L2857 + ldr r2, [r3, #468] + ldr r3, .L2857 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2857 + strb r3, [r2, #108] +.L2854: + ldr r3, .L2857 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2857 + str r2, [r3, #72] + ldr r2, .L2857 + ldr r3, .L2857 + str r3, [r2, #104] + ldr r3, .L2857 + ldr r2, [r3, #104] + ldr r3, .L2857 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2858: + .align 2 +.L2857: + .word GSU + .word GSU+56 + .size _Z9fx_or_i11v, .-_Z9fx_or_i11v + .align 2 + .type _Z9fx_or_i12v, %function +_Z9fx_or_i12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2863 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #12 + str r3, [fp, #-16] + ldr r3, .L2863 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2863 + str r2, [r3, #60] + ldr r3, .L2863 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2863 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2863 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2863 + ldr r2, [r3, #100] + ldr r3, .L2863+4 + cmp r2, r3 + bne .L2860 + ldr r3, .L2863 + ldr r2, [r3, #468] + ldr r3, .L2863 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2863 + strb r3, [r2, #108] +.L2860: + ldr r3, .L2863 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2863 + str r2, [r3, #72] + ldr r2, .L2863 + ldr r3, .L2863 + str r3, [r2, #104] + ldr r3, .L2863 + ldr r2, [r3, #104] + ldr r3, .L2863 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2864: + .align 2 +.L2863: + .word GSU + .word GSU+56 + .size _Z9fx_or_i12v, .-_Z9fx_or_i12v + .align 2 + .type _Z9fx_or_i13v, %function +_Z9fx_or_i13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2869 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #13 + str r3, [fp, #-16] + ldr r3, .L2869 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2869 + str r2, [r3, #60] + ldr r3, .L2869 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2869 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2869 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2869 + ldr r2, [r3, #100] + ldr r3, .L2869+4 + cmp r2, r3 + bne .L2866 + ldr r3, .L2869 + ldr r2, [r3, #468] + ldr r3, .L2869 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2869 + strb r3, [r2, #108] +.L2866: + ldr r3, .L2869 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2869 + str r2, [r3, #72] + ldr r2, .L2869 + ldr r3, .L2869 + str r3, [r2, #104] + ldr r3, .L2869 + ldr r2, [r3, #104] + ldr r3, .L2869 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2870: + .align 2 +.L2869: + .word GSU + .word GSU+56 + .size _Z9fx_or_i13v, .-_Z9fx_or_i13v + .align 2 + .type _Z9fx_or_i14v, %function +_Z9fx_or_i14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2875 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #14 + str r3, [fp, #-16] + ldr r3, .L2875 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2875 + str r2, [r3, #60] + ldr r3, .L2875 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2875 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2875 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2875 + ldr r2, [r3, #100] + ldr r3, .L2875+4 + cmp r2, r3 + bne .L2872 + ldr r3, .L2875 + ldr r2, [r3, #468] + ldr r3, .L2875 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2875 + strb r3, [r2, #108] +.L2872: + ldr r3, .L2875 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2875 + str r2, [r3, #72] + ldr r2, .L2875 + ldr r3, .L2875 + str r3, [r2, #104] + ldr r3, .L2875 + ldr r2, [r3, #104] + ldr r3, .L2875 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2876: + .align 2 +.L2875: + .word GSU + .word GSU+56 + .size _Z9fx_or_i14v, .-_Z9fx_or_i14v + .align 2 + .type _Z9fx_or_i15v, %function +_Z9fx_or_i15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2881 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + orr r3, r3, #15 + str r3, [fp, #-16] + ldr r3, .L2881 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2881 + str r2, [r3, #60] + ldr r3, .L2881 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2881 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2881 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2881 + ldr r2, [r3, #100] + ldr r3, .L2881+4 + cmp r2, r3 + bne .L2878 + ldr r3, .L2881 + ldr r2, [r3, #468] + ldr r3, .L2881 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2881 + strb r3, [r2, #108] +.L2878: + ldr r3, .L2881 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2881 + str r2, [r3, #72] + ldr r2, .L2881 + ldr r3, .L2881 + str r3, [r2, #104] + ldr r3, .L2881 + ldr r2, [r3, #104] + ldr r3, .L2881 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2882: + .align 2 +.L2881: + .word GSU + .word GSU+56 + .size _Z9fx_or_i15v, .-_Z9fx_or_i15v + .align 2 + .type _Z9fx_xor_i1v, %function +_Z9fx_xor_i1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2887 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #1 + str r3, [fp, #-16] + ldr r3, .L2887 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2887 + str r2, [r3, #60] + ldr r3, .L2887 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2887 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2887 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2887 + ldr r2, [r3, #100] + ldr r3, .L2887+4 + cmp r2, r3 + bne .L2884 + ldr r3, .L2887 + ldr r2, [r3, #468] + ldr r3, .L2887 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2887 + strb r3, [r2, #108] +.L2884: + ldr r3, .L2887 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2887 + str r2, [r3, #72] + ldr r2, .L2887 + ldr r3, .L2887 + str r3, [r2, #104] + ldr r3, .L2887 + ldr r2, [r3, #104] + ldr r3, .L2887 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2888: + .align 2 +.L2887: + .word GSU + .word GSU+56 + .size _Z9fx_xor_i1v, .-_Z9fx_xor_i1v + .align 2 + .type _Z9fx_xor_i2v, %function +_Z9fx_xor_i2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2893 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #2 + str r3, [fp, #-16] + ldr r3, .L2893 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2893 + str r2, [r3, #60] + ldr r3, .L2893 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2893 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2893 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2893 + ldr r2, [r3, #100] + ldr r3, .L2893+4 + cmp r2, r3 + bne .L2890 + ldr r3, .L2893 + ldr r2, [r3, #468] + ldr r3, .L2893 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2893 + strb r3, [r2, #108] +.L2890: + ldr r3, .L2893 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2893 + str r2, [r3, #72] + ldr r2, .L2893 + ldr r3, .L2893 + str r3, [r2, #104] + ldr r3, .L2893 + ldr r2, [r3, #104] + ldr r3, .L2893 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2894: + .align 2 +.L2893: + .word GSU + .word GSU+56 + .size _Z9fx_xor_i2v, .-_Z9fx_xor_i2v + .align 2 + .type _Z9fx_xor_i3v, %function +_Z9fx_xor_i3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2899 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #3 + str r3, [fp, #-16] + ldr r3, .L2899 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2899 + str r2, [r3, #60] + ldr r3, .L2899 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2899 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2899 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2899 + ldr r2, [r3, #100] + ldr r3, .L2899+4 + cmp r2, r3 + bne .L2896 + ldr r3, .L2899 + ldr r2, [r3, #468] + ldr r3, .L2899 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2899 + strb r3, [r2, #108] +.L2896: + ldr r3, .L2899 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2899 + str r2, [r3, #72] + ldr r2, .L2899 + ldr r3, .L2899 + str r3, [r2, #104] + ldr r3, .L2899 + ldr r2, [r3, #104] + ldr r3, .L2899 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2900: + .align 2 +.L2899: + .word GSU + .word GSU+56 + .size _Z9fx_xor_i3v, .-_Z9fx_xor_i3v + .align 2 + .type _Z9fx_xor_i4v, %function +_Z9fx_xor_i4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2905 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #4 + str r3, [fp, #-16] + ldr r3, .L2905 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2905 + str r2, [r3, #60] + ldr r3, .L2905 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2905 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2905 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2905 + ldr r2, [r3, #100] + ldr r3, .L2905+4 + cmp r2, r3 + bne .L2902 + ldr r3, .L2905 + ldr r2, [r3, #468] + ldr r3, .L2905 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2905 + strb r3, [r2, #108] +.L2902: + ldr r3, .L2905 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2905 + str r2, [r3, #72] + ldr r2, .L2905 + ldr r3, .L2905 + str r3, [r2, #104] + ldr r3, .L2905 + ldr r2, [r3, #104] + ldr r3, .L2905 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2906: + .align 2 +.L2905: + .word GSU + .word GSU+56 + .size _Z9fx_xor_i4v, .-_Z9fx_xor_i4v + .align 2 + .type _Z9fx_xor_i5v, %function +_Z9fx_xor_i5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2911 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #5 + str r3, [fp, #-16] + ldr r3, .L2911 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2911 + str r2, [r3, #60] + ldr r3, .L2911 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2911 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2911 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2911 + ldr r2, [r3, #100] + ldr r3, .L2911+4 + cmp r2, r3 + bne .L2908 + ldr r3, .L2911 + ldr r2, [r3, #468] + ldr r3, .L2911 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2911 + strb r3, [r2, #108] +.L2908: + ldr r3, .L2911 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2911 + str r2, [r3, #72] + ldr r2, .L2911 + ldr r3, .L2911 + str r3, [r2, #104] + ldr r3, .L2911 + ldr r2, [r3, #104] + ldr r3, .L2911 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2912: + .align 2 +.L2911: + .word GSU + .word GSU+56 + .size _Z9fx_xor_i5v, .-_Z9fx_xor_i5v + .align 2 + .type _Z9fx_xor_i6v, %function +_Z9fx_xor_i6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2917 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #6 + str r3, [fp, #-16] + ldr r3, .L2917 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2917 + str r2, [r3, #60] + ldr r3, .L2917 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2917 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2917 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2917 + ldr r2, [r3, #100] + ldr r3, .L2917+4 + cmp r2, r3 + bne .L2914 + ldr r3, .L2917 + ldr r2, [r3, #468] + ldr r3, .L2917 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2917 + strb r3, [r2, #108] +.L2914: + ldr r3, .L2917 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2917 + str r2, [r3, #72] + ldr r2, .L2917 + ldr r3, .L2917 + str r3, [r2, #104] + ldr r3, .L2917 + ldr r2, [r3, #104] + ldr r3, .L2917 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2918: + .align 2 +.L2917: + .word GSU + .word GSU+56 + .size _Z9fx_xor_i6v, .-_Z9fx_xor_i6v + .align 2 + .type _Z9fx_xor_i7v, %function +_Z9fx_xor_i7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2923 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #7 + str r3, [fp, #-16] + ldr r3, .L2923 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2923 + str r2, [r3, #60] + ldr r3, .L2923 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2923 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2923 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2923 + ldr r2, [r3, #100] + ldr r3, .L2923+4 + cmp r2, r3 + bne .L2920 + ldr r3, .L2923 + ldr r2, [r3, #468] + ldr r3, .L2923 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2923 + strb r3, [r2, #108] +.L2920: + ldr r3, .L2923 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2923 + str r2, [r3, #72] + ldr r2, .L2923 + ldr r3, .L2923 + str r3, [r2, #104] + ldr r3, .L2923 + ldr r2, [r3, #104] + ldr r3, .L2923 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2924: + .align 2 +.L2923: + .word GSU + .word GSU+56 + .size _Z9fx_xor_i7v, .-_Z9fx_xor_i7v + .align 2 + .type _Z9fx_xor_i8v, %function +_Z9fx_xor_i8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2929 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #8 + str r3, [fp, #-16] + ldr r3, .L2929 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2929 + str r2, [r3, #60] + ldr r3, .L2929 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2929 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2929 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2929 + ldr r2, [r3, #100] + ldr r3, .L2929+4 + cmp r2, r3 + bne .L2926 + ldr r3, .L2929 + ldr r2, [r3, #468] + ldr r3, .L2929 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2929 + strb r3, [r2, #108] +.L2926: + ldr r3, .L2929 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2929 + str r2, [r3, #72] + ldr r2, .L2929 + ldr r3, .L2929 + str r3, [r2, #104] + ldr r3, .L2929 + ldr r2, [r3, #104] + ldr r3, .L2929 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2930: + .align 2 +.L2929: + .word GSU + .word GSU+56 + .size _Z9fx_xor_i8v, .-_Z9fx_xor_i8v + .align 2 + .type _Z9fx_xor_i9v, %function +_Z9fx_xor_i9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2935 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #9 + str r3, [fp, #-16] + ldr r3, .L2935 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2935 + str r2, [r3, #60] + ldr r3, .L2935 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2935 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2935 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2935 + ldr r2, [r3, #100] + ldr r3, .L2935+4 + cmp r2, r3 + bne .L2932 + ldr r3, .L2935 + ldr r2, [r3, #468] + ldr r3, .L2935 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2935 + strb r3, [r2, #108] +.L2932: + ldr r3, .L2935 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2935 + str r2, [r3, #72] + ldr r2, .L2935 + ldr r3, .L2935 + str r3, [r2, #104] + ldr r3, .L2935 + ldr r2, [r3, #104] + ldr r3, .L2935 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2936: + .align 2 +.L2935: + .word GSU + .word GSU+56 + .size _Z9fx_xor_i9v, .-_Z9fx_xor_i9v + .align 2 + .type _Z10fx_xor_i10v, %function +_Z10fx_xor_i10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2941 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #10 + str r3, [fp, #-16] + ldr r3, .L2941 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2941 + str r2, [r3, #60] + ldr r3, .L2941 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2941 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2941 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2941 + ldr r2, [r3, #100] + ldr r3, .L2941+4 + cmp r2, r3 + bne .L2938 + ldr r3, .L2941 + ldr r2, [r3, #468] + ldr r3, .L2941 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2941 + strb r3, [r2, #108] +.L2938: + ldr r3, .L2941 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2941 + str r2, [r3, #72] + ldr r2, .L2941 + ldr r3, .L2941 + str r3, [r2, #104] + ldr r3, .L2941 + ldr r2, [r3, #104] + ldr r3, .L2941 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2942: + .align 2 +.L2941: + .word GSU + .word GSU+56 + .size _Z10fx_xor_i10v, .-_Z10fx_xor_i10v + .align 2 + .type _Z10fx_xor_i11v, %function +_Z10fx_xor_i11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2947 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #11 + str r3, [fp, #-16] + ldr r3, .L2947 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2947 + str r2, [r3, #60] + ldr r3, .L2947 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2947 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2947 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2947 + ldr r2, [r3, #100] + ldr r3, .L2947+4 + cmp r2, r3 + bne .L2944 + ldr r3, .L2947 + ldr r2, [r3, #468] + ldr r3, .L2947 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2947 + strb r3, [r2, #108] +.L2944: + ldr r3, .L2947 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2947 + str r2, [r3, #72] + ldr r2, .L2947 + ldr r3, .L2947 + str r3, [r2, #104] + ldr r3, .L2947 + ldr r2, [r3, #104] + ldr r3, .L2947 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2948: + .align 2 +.L2947: + .word GSU + .word GSU+56 + .size _Z10fx_xor_i11v, .-_Z10fx_xor_i11v + .align 2 + .type _Z10fx_xor_i12v, %function +_Z10fx_xor_i12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2953 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #12 + str r3, [fp, #-16] + ldr r3, .L2953 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2953 + str r2, [r3, #60] + ldr r3, .L2953 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2953 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2953 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2953 + ldr r2, [r3, #100] + ldr r3, .L2953+4 + cmp r2, r3 + bne .L2950 + ldr r3, .L2953 + ldr r2, [r3, #468] + ldr r3, .L2953 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2953 + strb r3, [r2, #108] +.L2950: + ldr r3, .L2953 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2953 + str r2, [r3, #72] + ldr r2, .L2953 + ldr r3, .L2953 + str r3, [r2, #104] + ldr r3, .L2953 + ldr r2, [r3, #104] + ldr r3, .L2953 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2954: + .align 2 +.L2953: + .word GSU + .word GSU+56 + .size _Z10fx_xor_i12v, .-_Z10fx_xor_i12v + .align 2 + .type _Z10fx_xor_i13v, %function +_Z10fx_xor_i13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2959 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #13 + str r3, [fp, #-16] + ldr r3, .L2959 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2959 + str r2, [r3, #60] + ldr r3, .L2959 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2959 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2959 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2959 + ldr r2, [r3, #100] + ldr r3, .L2959+4 + cmp r2, r3 + bne .L2956 + ldr r3, .L2959 + ldr r2, [r3, #468] + ldr r3, .L2959 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2959 + strb r3, [r2, #108] +.L2956: + ldr r3, .L2959 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2959 + str r2, [r3, #72] + ldr r2, .L2959 + ldr r3, .L2959 + str r3, [r2, #104] + ldr r3, .L2959 + ldr r2, [r3, #104] + ldr r3, .L2959 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2960: + .align 2 +.L2959: + .word GSU + .word GSU+56 + .size _Z10fx_xor_i13v, .-_Z10fx_xor_i13v + .align 2 + .type _Z10fx_xor_i14v, %function +_Z10fx_xor_i14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2965 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #14 + str r3, [fp, #-16] + ldr r3, .L2965 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2965 + str r2, [r3, #60] + ldr r3, .L2965 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2965 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2965 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2965 + ldr r2, [r3, #100] + ldr r3, .L2965+4 + cmp r2, r3 + bne .L2962 + ldr r3, .L2965 + ldr r2, [r3, #468] + ldr r3, .L2965 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2965 + strb r3, [r2, #108] +.L2962: + ldr r3, .L2965 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2965 + str r2, [r3, #72] + ldr r2, .L2965 + ldr r3, .L2965 + str r3, [r2, #104] + ldr r3, .L2965 + ldr r2, [r3, #104] + ldr r3, .L2965 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2966: + .align 2 +.L2965: + .word GSU + .word GSU+56 + .size _Z10fx_xor_i14v, .-_Z10fx_xor_i14v + .align 2 + .type _Z10fx_xor_i15v, %function +_Z10fx_xor_i15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L2971 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + eor r3, r3, #15 + str r3, [fp, #-16] + ldr r3, .L2971 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2971 + str r2, [r3, #60] + ldr r3, .L2971 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r2, .L2971 + ldr r3, [fp, #-16] + str r3, [r2, #116] + ldr r2, .L2971 + ldr r3, [fp, #-16] + str r3, [r2, #120] + ldr r3, .L2971 + ldr r2, [r3, #100] + ldr r3, .L2971+4 + cmp r2, r3 + bne .L2968 + ldr r3, .L2971 + ldr r2, [r3, #468] + ldr r3, .L2971 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L2971 + strb r3, [r2, #108] +.L2968: + ldr r3, .L2971 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2971 + str r2, [r3, #72] + ldr r2, .L2971 + ldr r3, .L2971 + str r3, [r2, #104] + ldr r3, .L2971 + ldr r2, [r3, #104] + ldr r3, .L2971 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L2972: + .align 2 +.L2971: + .word GSU + .word GSU+56 + .size _Z10fx_xor_i15v, .-_Z10fx_xor_i15v + .align 2 + .type _Z9fx_inc_r0v, %function +_Z9fx_inc_r0v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2975 + ldr r3, [r3, #0] + add r2, r3, #1 + ldr r3, .L2975 + str r2, [r3, #0] + ldr r3, .L2975 + ldr r2, [r3, #0] + ldr r3, .L2975 + str r2, [r3, #116] + ldr r3, .L2975 + ldr r2, [r3, #0] + ldr r3, .L2975 + str r2, [r3, #120] + ldr r3, .L2975 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2975 + str r2, [r3, #72] + ldr r2, .L2975 + ldr r3, .L2975 + str r3, [r2, #104] + ldr r3, .L2975 + ldr r2, [r3, #104] + ldr r3, .L2975 + str r2, [r3, #100] + ldr r3, .L2975 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2975 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2976: + .align 2 +.L2975: + .word GSU + .size _Z9fx_inc_r0v, .-_Z9fx_inc_r0v + .align 2 + .type _Z9fx_inc_r1v, %function +_Z9fx_inc_r1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2979 + ldr r3, [r3, #4] + add r2, r3, #1 + ldr r3, .L2979 + str r2, [r3, #4] + ldr r3, .L2979 + ldr r2, [r3, #4] + ldr r3, .L2979 + str r2, [r3, #116] + ldr r3, .L2979 + ldr r2, [r3, #4] + ldr r3, .L2979 + str r2, [r3, #120] + ldr r3, .L2979 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2979 + str r2, [r3, #72] + ldr r2, .L2979 + ldr r3, .L2979 + str r3, [r2, #104] + ldr r3, .L2979 + ldr r2, [r3, #104] + ldr r3, .L2979 + str r2, [r3, #100] + ldr r3, .L2979 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2979 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2980: + .align 2 +.L2979: + .word GSU + .size _Z9fx_inc_r1v, .-_Z9fx_inc_r1v + .align 2 + .type _Z9fx_inc_r2v, %function +_Z9fx_inc_r2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2983 + ldr r3, [r3, #8] + add r2, r3, #1 + ldr r3, .L2983 + str r2, [r3, #8] + ldr r3, .L2983 + ldr r2, [r3, #8] + ldr r3, .L2983 + str r2, [r3, #116] + ldr r3, .L2983 + ldr r2, [r3, #8] + ldr r3, .L2983 + str r2, [r3, #120] + ldr r3, .L2983 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2983 + str r2, [r3, #72] + ldr r2, .L2983 + ldr r3, .L2983 + str r3, [r2, #104] + ldr r3, .L2983 + ldr r2, [r3, #104] + ldr r3, .L2983 + str r2, [r3, #100] + ldr r3, .L2983 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2983 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2984: + .align 2 +.L2983: + .word GSU + .size _Z9fx_inc_r2v, .-_Z9fx_inc_r2v + .align 2 + .type _Z9fx_inc_r3v, %function +_Z9fx_inc_r3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2987 + ldr r3, [r3, #12] + add r2, r3, #1 + ldr r3, .L2987 + str r2, [r3, #12] + ldr r3, .L2987 + ldr r2, [r3, #12] + ldr r3, .L2987 + str r2, [r3, #116] + ldr r3, .L2987 + ldr r2, [r3, #12] + ldr r3, .L2987 + str r2, [r3, #120] + ldr r3, .L2987 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2987 + str r2, [r3, #72] + ldr r2, .L2987 + ldr r3, .L2987 + str r3, [r2, #104] + ldr r3, .L2987 + ldr r2, [r3, #104] + ldr r3, .L2987 + str r2, [r3, #100] + ldr r3, .L2987 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2987 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2988: + .align 2 +.L2987: + .word GSU + .size _Z9fx_inc_r3v, .-_Z9fx_inc_r3v + .align 2 + .type _Z9fx_inc_r4v, %function +_Z9fx_inc_r4v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2991 + ldr r3, [r3, #16] + add r2, r3, #1 + ldr r3, .L2991 + str r2, [r3, #16] + ldr r3, .L2991 + ldr r2, [r3, #16] + ldr r3, .L2991 + str r2, [r3, #116] + ldr r3, .L2991 + ldr r2, [r3, #16] + ldr r3, .L2991 + str r2, [r3, #120] + ldr r3, .L2991 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2991 + str r2, [r3, #72] + ldr r2, .L2991 + ldr r3, .L2991 + str r3, [r2, #104] + ldr r3, .L2991 + ldr r2, [r3, #104] + ldr r3, .L2991 + str r2, [r3, #100] + ldr r3, .L2991 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2991 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2992: + .align 2 +.L2991: + .word GSU + .size _Z9fx_inc_r4v, .-_Z9fx_inc_r4v + .align 2 + .type _Z9fx_inc_r5v, %function +_Z9fx_inc_r5v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2995 + ldr r3, [r3, #20] + add r2, r3, #1 + ldr r3, .L2995 + str r2, [r3, #20] + ldr r3, .L2995 + ldr r2, [r3, #20] + ldr r3, .L2995 + str r2, [r3, #116] + ldr r3, .L2995 + ldr r2, [r3, #20] + ldr r3, .L2995 + str r2, [r3, #120] + ldr r3, .L2995 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2995 + str r2, [r3, #72] + ldr r2, .L2995 + ldr r3, .L2995 + str r3, [r2, #104] + ldr r3, .L2995 + ldr r2, [r3, #104] + ldr r3, .L2995 + str r2, [r3, #100] + ldr r3, .L2995 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2995 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L2996: + .align 2 +.L2995: + .word GSU + .size _Z9fx_inc_r5v, .-_Z9fx_inc_r5v + .align 2 + .type _Z9fx_inc_r6v, %function +_Z9fx_inc_r6v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L2999 + ldr r3, [r3, #24] + add r2, r3, #1 + ldr r3, .L2999 + str r2, [r3, #24] + ldr r3, .L2999 + ldr r2, [r3, #24] + ldr r3, .L2999 + str r2, [r3, #116] + ldr r3, .L2999 + ldr r2, [r3, #24] + ldr r3, .L2999 + str r2, [r3, #120] + ldr r3, .L2999 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L2999 + str r2, [r3, #72] + ldr r2, .L2999 + ldr r3, .L2999 + str r3, [r2, #104] + ldr r3, .L2999 + ldr r2, [r3, #104] + ldr r3, .L2999 + str r2, [r3, #100] + ldr r3, .L2999 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L2999 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3000: + .align 2 +.L2999: + .word GSU + .size _Z9fx_inc_r6v, .-_Z9fx_inc_r6v + .align 2 + .type _Z9fx_inc_r7v, %function +_Z9fx_inc_r7v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3003 + ldr r3, [r3, #28] + add r2, r3, #1 + ldr r3, .L3003 + str r2, [r3, #28] + ldr r3, .L3003 + ldr r2, [r3, #28] + ldr r3, .L3003 + str r2, [r3, #116] + ldr r3, .L3003 + ldr r2, [r3, #28] + ldr r3, .L3003 + str r2, [r3, #120] + ldr r3, .L3003 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3003 + str r2, [r3, #72] + ldr r2, .L3003 + ldr r3, .L3003 + str r3, [r2, #104] + ldr r3, .L3003 + ldr r2, [r3, #104] + ldr r3, .L3003 + str r2, [r3, #100] + ldr r3, .L3003 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3003 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3004: + .align 2 +.L3003: + .word GSU + .size _Z9fx_inc_r7v, .-_Z9fx_inc_r7v + .align 2 + .type _Z9fx_inc_r8v, %function +_Z9fx_inc_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3007 + ldr r3, [r3, #32] + add r2, r3, #1 + ldr r3, .L3007 + str r2, [r3, #32] + ldr r3, .L3007 + ldr r2, [r3, #32] + ldr r3, .L3007 + str r2, [r3, #116] + ldr r3, .L3007 + ldr r2, [r3, #32] + ldr r3, .L3007 + str r2, [r3, #120] + ldr r3, .L3007 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3007 + str r2, [r3, #72] + ldr r2, .L3007 + ldr r3, .L3007 + str r3, [r2, #104] + ldr r3, .L3007 + ldr r2, [r3, #104] + ldr r3, .L3007 + str r2, [r3, #100] + ldr r3, .L3007 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3007 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3008: + .align 2 +.L3007: + .word GSU + .size _Z9fx_inc_r8v, .-_Z9fx_inc_r8v + .align 2 + .type _Z9fx_inc_r9v, %function +_Z9fx_inc_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3011 + ldr r3, [r3, #36] + add r2, r3, #1 + ldr r3, .L3011 + str r2, [r3, #36] + ldr r3, .L3011 + ldr r2, [r3, #36] + ldr r3, .L3011 + str r2, [r3, #116] + ldr r3, .L3011 + ldr r2, [r3, #36] + ldr r3, .L3011 + str r2, [r3, #120] + ldr r3, .L3011 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3011 + str r2, [r3, #72] + ldr r2, .L3011 + ldr r3, .L3011 + str r3, [r2, #104] + ldr r3, .L3011 + ldr r2, [r3, #104] + ldr r3, .L3011 + str r2, [r3, #100] + ldr r3, .L3011 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3011 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3012: + .align 2 +.L3011: + .word GSU + .size _Z9fx_inc_r9v, .-_Z9fx_inc_r9v + .align 2 + .type _Z10fx_inc_r10v, %function +_Z10fx_inc_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3015 + ldr r3, [r3, #40] + add r2, r3, #1 + ldr r3, .L3015 + str r2, [r3, #40] + ldr r3, .L3015 + ldr r2, [r3, #40] + ldr r3, .L3015 + str r2, [r3, #116] + ldr r3, .L3015 + ldr r2, [r3, #40] + ldr r3, .L3015 + str r2, [r3, #120] + ldr r3, .L3015 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3015 + str r2, [r3, #72] + ldr r2, .L3015 + ldr r3, .L3015 + str r3, [r2, #104] + ldr r3, .L3015 + ldr r2, [r3, #104] + ldr r3, .L3015 + str r2, [r3, #100] + ldr r3, .L3015 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3015 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3016: + .align 2 +.L3015: + .word GSU + .size _Z10fx_inc_r10v, .-_Z10fx_inc_r10v + .align 2 + .type _Z10fx_inc_r11v, %function +_Z10fx_inc_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3019 + ldr r3, [r3, #44] + add r2, r3, #1 + ldr r3, .L3019 + str r2, [r3, #44] + ldr r3, .L3019 + ldr r2, [r3, #44] + ldr r3, .L3019 + str r2, [r3, #116] + ldr r3, .L3019 + ldr r2, [r3, #44] + ldr r3, .L3019 + str r2, [r3, #120] + ldr r3, .L3019 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3019 + str r2, [r3, #72] + ldr r2, .L3019 + ldr r3, .L3019 + str r3, [r2, #104] + ldr r3, .L3019 + ldr r2, [r3, #104] + ldr r3, .L3019 + str r2, [r3, #100] + ldr r3, .L3019 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3019 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3020: + .align 2 +.L3019: + .word GSU + .size _Z10fx_inc_r11v, .-_Z10fx_inc_r11v + .align 2 + .type _Z10fx_inc_r12v, %function +_Z10fx_inc_r12v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3023 + ldr r3, [r3, #48] + add r2, r3, #1 + ldr r3, .L3023 + str r2, [r3, #48] + ldr r3, .L3023 + ldr r2, [r3, #48] + ldr r3, .L3023 + str r2, [r3, #116] + ldr r3, .L3023 + ldr r2, [r3, #48] + ldr r3, .L3023 + str r2, [r3, #120] + ldr r3, .L3023 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3023 + str r2, [r3, #72] + ldr r2, .L3023 + ldr r3, .L3023 + str r3, [r2, #104] + ldr r3, .L3023 + ldr r2, [r3, #104] + ldr r3, .L3023 + str r2, [r3, #100] + ldr r3, .L3023 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3023 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3024: + .align 2 +.L3023: + .word GSU + .size _Z10fx_inc_r12v, .-_Z10fx_inc_r12v + .align 2 + .type _Z10fx_inc_r13v, %function +_Z10fx_inc_r13v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3027 + ldr r3, [r3, #52] + add r2, r3, #1 + ldr r3, .L3027 + str r2, [r3, #52] + ldr r3, .L3027 + ldr r2, [r3, #52] + ldr r3, .L3027 + str r2, [r3, #116] + ldr r3, .L3027 + ldr r2, [r3, #52] + ldr r3, .L3027 + str r2, [r3, #120] + ldr r3, .L3027 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3027 + str r2, [r3, #72] + ldr r2, .L3027 + ldr r3, .L3027 + str r3, [r2, #104] + ldr r3, .L3027 + ldr r2, [r3, #104] + ldr r3, .L3027 + str r2, [r3, #100] + ldr r3, .L3027 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3027 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3028: + .align 2 +.L3027: + .word GSU + .size _Z10fx_inc_r13v, .-_Z10fx_inc_r13v + .align 2 + .type _Z10fx_inc_r14v, %function +_Z10fx_inc_r14v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3031 + ldr r3, [r3, #56] + add r2, r3, #1 + ldr r3, .L3031 + str r2, [r3, #56] + ldr r3, .L3031 + ldr r2, [r3, #56] + ldr r3, .L3031 + str r2, [r3, #116] + ldr r3, .L3031 + ldr r2, [r3, #56] + ldr r3, .L3031 + str r2, [r3, #120] + ldr r3, .L3031 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3031 + str r2, [r3, #72] + ldr r2, .L3031 + ldr r3, .L3031 + str r3, [r2, #104] + ldr r3, .L3031 + ldr r2, [r3, #104] + ldr r3, .L3031 + str r2, [r3, #100] + ldr r3, .L3031 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3031 + str r2, [r3, #60] + ldr r3, .L3031 + ldr r2, [r3, #468] + ldr r3, .L3031 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3031 + strb r3, [r2, #108] + ldmfd sp, {fp, sp, pc} +.L3032: + .align 2 +.L3031: + .word GSU + .size _Z10fx_inc_r14v, .-_Z10fx_inc_r14v + .align 2 + .type _Z7fx_getcv, %function +_Z7fx_getcv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3040 + ldrb r3, [r3, #108] + strb r3, [fp, #-13] + ldr r3, .L3040 + ldr r3, [r3, #68] + and r3, r3, #4 + cmp r3, #0 + beq .L3034 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r2, r3, #255 + mov r3, #240 + and r2, r2, r3 + ldrb r3, [fp, #-13] @ zero_extendqisi2 + mov r3, r3, lsr #4 + and r3, r3, #255 + orr r3, r2, r3 + and r3, r3, #255 + strb r3, [fp, #-13] +.L3034: + ldr r3, .L3040 + ldr r3, [r3, #68] + and r3, r3, #8 + cmp r3, #0 + beq .L3036 + ldr r3, .L3040 + ldr r3, [r3, #64] + and r2, r3, #240 + ldr r3, .L3040 + str r2, [r3, #64] + ldr r3, .L3040 + ldr r2, [r3, #64] + ldrb r3, [fp, #-13] @ zero_extendqisi2 + and r3, r3, #15 + orr r2, r2, r3 + ldr r3, .L3040 + str r2, [r3, #64] + b .L3038 +.L3036: + ldrb r2, [fp, #-13] @ zero_extendqisi2 + ldr r3, .L3040 + str r2, [r3, #64] +.L3038: + ldr r3, .L3040 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3040 + str r2, [r3, #72] + ldr r2, .L3040 + ldr r3, .L3040 + str r3, [r2, #104] + ldr r3, .L3040 + ldr r2, [r3, #104] + ldr r3, .L3040 + str r2, [r3, #100] + ldr r3, .L3040 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3040 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3041: + .align 2 +.L3040: + .word GSU + .size _Z7fx_getcv, .-_Z7fx_getcv + .align 2 + .type _Z7fx_rambv, %function +_Z7fx_rambv: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3044 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r2, r3, #3 + ldr r3, .L3044 + str r2, [r3, #84] + ldr r3, .L3044 + ldr r3, [r3, #84] + and r3, r3, #3 + ldr r2, .L3044 + mov r1, #476 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r2, [r3, #0] + ldr r3, .L3044 + str r2, [r3, #464] + ldr r3, .L3044 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3044 + str r2, [r3, #72] + ldr r2, .L3044 + ldr r3, .L3044 + str r3, [r2, #104] + ldr r3, .L3044 + ldr r2, [r3, #104] + ldr r3, .L3044 + str r2, [r3, #100] + ldr r3, .L3044 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3044 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3045: + .align 2 +.L3044: + .word GSU + .size _Z7fx_rambv, .-_Z7fx_rambv + .align 2 + .type _Z7fx_rombv, %function +_Z7fx_rombv: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3048 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + and r2, r3, #127 + ldr r3, .L3048 + str r2, [r3, #80] + ldr r3, .L3048 + ldr r3, [r3, #80] + ldr r2, .L3048 + mov r1, #492 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r2, [r3, #0] + ldr r3, .L3048 + str r2, [r3, #468] + ldr r3, .L3048 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3048 + str r2, [r3, #72] + ldr r2, .L3048 + ldr r3, .L3048 + str r3, [r2, #104] + ldr r3, .L3048 + ldr r2, [r3, #104] + ldr r3, .L3048 + str r2, [r3, #100] + ldr r3, .L3048 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3048 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3049: + .align 2 +.L3048: + .word GSU + .size _Z7fx_rombv, .-_Z7fx_rombv + .align 2 + .type _Z9fx_dec_r0v, %function +_Z9fx_dec_r0v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3052 + ldr r3, [r3, #0] + sub r2, r3, #1 + ldr r3, .L3052 + str r2, [r3, #0] + ldr r3, .L3052 + ldr r2, [r3, #0] + ldr r3, .L3052 + str r2, [r3, #116] + ldr r3, .L3052 + ldr r2, [r3, #0] + ldr r3, .L3052 + str r2, [r3, #120] + ldr r3, .L3052 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3052 + str r2, [r3, #72] + ldr r2, .L3052 + ldr r3, .L3052 + str r3, [r2, #104] + ldr r3, .L3052 + ldr r2, [r3, #104] + ldr r3, .L3052 + str r2, [r3, #100] + ldr r3, .L3052 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3052 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3053: + .align 2 +.L3052: + .word GSU + .size _Z9fx_dec_r0v, .-_Z9fx_dec_r0v + .align 2 + .type _Z9fx_dec_r1v, %function +_Z9fx_dec_r1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3056 + ldr r3, [r3, #4] + sub r2, r3, #1 + ldr r3, .L3056 + str r2, [r3, #4] + ldr r3, .L3056 + ldr r2, [r3, #4] + ldr r3, .L3056 + str r2, [r3, #116] + ldr r3, .L3056 + ldr r2, [r3, #4] + ldr r3, .L3056 + str r2, [r3, #120] + ldr r3, .L3056 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3056 + str r2, [r3, #72] + ldr r2, .L3056 + ldr r3, .L3056 + str r3, [r2, #104] + ldr r3, .L3056 + ldr r2, [r3, #104] + ldr r3, .L3056 + str r2, [r3, #100] + ldr r3, .L3056 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3056 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3057: + .align 2 +.L3056: + .word GSU + .size _Z9fx_dec_r1v, .-_Z9fx_dec_r1v + .align 2 + .type _Z9fx_dec_r2v, %function +_Z9fx_dec_r2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3060 + ldr r3, [r3, #8] + sub r2, r3, #1 + ldr r3, .L3060 + str r2, [r3, #8] + ldr r3, .L3060 + ldr r2, [r3, #8] + ldr r3, .L3060 + str r2, [r3, #116] + ldr r3, .L3060 + ldr r2, [r3, #8] + ldr r3, .L3060 + str r2, [r3, #120] + ldr r3, .L3060 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3060 + str r2, [r3, #72] + ldr r2, .L3060 + ldr r3, .L3060 + str r3, [r2, #104] + ldr r3, .L3060 + ldr r2, [r3, #104] + ldr r3, .L3060 + str r2, [r3, #100] + ldr r3, .L3060 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3060 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3061: + .align 2 +.L3060: + .word GSU + .size _Z9fx_dec_r2v, .-_Z9fx_dec_r2v + .align 2 + .type _Z9fx_dec_r3v, %function +_Z9fx_dec_r3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3064 + ldr r3, [r3, #12] + sub r2, r3, #1 + ldr r3, .L3064 + str r2, [r3, #12] + ldr r3, .L3064 + ldr r2, [r3, #12] + ldr r3, .L3064 + str r2, [r3, #116] + ldr r3, .L3064 + ldr r2, [r3, #12] + ldr r3, .L3064 + str r2, [r3, #120] + ldr r3, .L3064 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3064 + str r2, [r3, #72] + ldr r2, .L3064 + ldr r3, .L3064 + str r3, [r2, #104] + ldr r3, .L3064 + ldr r2, [r3, #104] + ldr r3, .L3064 + str r2, [r3, #100] + ldr r3, .L3064 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3064 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3065: + .align 2 +.L3064: + .word GSU + .size _Z9fx_dec_r3v, .-_Z9fx_dec_r3v + .align 2 + .type _Z9fx_dec_r4v, %function +_Z9fx_dec_r4v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3068 + ldr r3, [r3, #16] + sub r2, r3, #1 + ldr r3, .L3068 + str r2, [r3, #16] + ldr r3, .L3068 + ldr r2, [r3, #16] + ldr r3, .L3068 + str r2, [r3, #116] + ldr r3, .L3068 + ldr r2, [r3, #16] + ldr r3, .L3068 + str r2, [r3, #120] + ldr r3, .L3068 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3068 + str r2, [r3, #72] + ldr r2, .L3068 + ldr r3, .L3068 + str r3, [r2, #104] + ldr r3, .L3068 + ldr r2, [r3, #104] + ldr r3, .L3068 + str r2, [r3, #100] + ldr r3, .L3068 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3068 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3069: + .align 2 +.L3068: + .word GSU + .size _Z9fx_dec_r4v, .-_Z9fx_dec_r4v + .align 2 + .type _Z9fx_dec_r5v, %function +_Z9fx_dec_r5v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3072 + ldr r3, [r3, #20] + sub r2, r3, #1 + ldr r3, .L3072 + str r2, [r3, #20] + ldr r3, .L3072 + ldr r2, [r3, #20] + ldr r3, .L3072 + str r2, [r3, #116] + ldr r3, .L3072 + ldr r2, [r3, #20] + ldr r3, .L3072 + str r2, [r3, #120] + ldr r3, .L3072 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3072 + str r2, [r3, #72] + ldr r2, .L3072 + ldr r3, .L3072 + str r3, [r2, #104] + ldr r3, .L3072 + ldr r2, [r3, #104] + ldr r3, .L3072 + str r2, [r3, #100] + ldr r3, .L3072 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3072 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3073: + .align 2 +.L3072: + .word GSU + .size _Z9fx_dec_r5v, .-_Z9fx_dec_r5v + .align 2 + .type _Z9fx_dec_r6v, %function +_Z9fx_dec_r6v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3076 + ldr r3, [r3, #24] + sub r2, r3, #1 + ldr r3, .L3076 + str r2, [r3, #24] + ldr r3, .L3076 + ldr r2, [r3, #24] + ldr r3, .L3076 + str r2, [r3, #116] + ldr r3, .L3076 + ldr r2, [r3, #24] + ldr r3, .L3076 + str r2, [r3, #120] + ldr r3, .L3076 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3076 + str r2, [r3, #72] + ldr r2, .L3076 + ldr r3, .L3076 + str r3, [r2, #104] + ldr r3, .L3076 + ldr r2, [r3, #104] + ldr r3, .L3076 + str r2, [r3, #100] + ldr r3, .L3076 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3076 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3077: + .align 2 +.L3076: + .word GSU + .size _Z9fx_dec_r6v, .-_Z9fx_dec_r6v + .align 2 + .type _Z9fx_dec_r7v, %function +_Z9fx_dec_r7v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3080 + ldr r3, [r3, #28] + sub r2, r3, #1 + ldr r3, .L3080 + str r2, [r3, #28] + ldr r3, .L3080 + ldr r2, [r3, #28] + ldr r3, .L3080 + str r2, [r3, #116] + ldr r3, .L3080 + ldr r2, [r3, #28] + ldr r3, .L3080 + str r2, [r3, #120] + ldr r3, .L3080 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3080 + str r2, [r3, #72] + ldr r2, .L3080 + ldr r3, .L3080 + str r3, [r2, #104] + ldr r3, .L3080 + ldr r2, [r3, #104] + ldr r3, .L3080 + str r2, [r3, #100] + ldr r3, .L3080 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3080 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3081: + .align 2 +.L3080: + .word GSU + .size _Z9fx_dec_r7v, .-_Z9fx_dec_r7v + .align 2 + .type _Z9fx_dec_r8v, %function +_Z9fx_dec_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3084 + ldr r3, [r3, #32] + sub r2, r3, #1 + ldr r3, .L3084 + str r2, [r3, #32] + ldr r3, .L3084 + ldr r2, [r3, #32] + ldr r3, .L3084 + str r2, [r3, #116] + ldr r3, .L3084 + ldr r2, [r3, #32] + ldr r3, .L3084 + str r2, [r3, #120] + ldr r3, .L3084 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3084 + str r2, [r3, #72] + ldr r2, .L3084 + ldr r3, .L3084 + str r3, [r2, #104] + ldr r3, .L3084 + ldr r2, [r3, #104] + ldr r3, .L3084 + str r2, [r3, #100] + ldr r3, .L3084 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3084 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3085: + .align 2 +.L3084: + .word GSU + .size _Z9fx_dec_r8v, .-_Z9fx_dec_r8v + .align 2 + .type _Z9fx_dec_r9v, %function +_Z9fx_dec_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3088 + ldr r3, [r3, #36] + sub r2, r3, #1 + ldr r3, .L3088 + str r2, [r3, #36] + ldr r3, .L3088 + ldr r2, [r3, #36] + ldr r3, .L3088 + str r2, [r3, #116] + ldr r3, .L3088 + ldr r2, [r3, #36] + ldr r3, .L3088 + str r2, [r3, #120] + ldr r3, .L3088 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3088 + str r2, [r3, #72] + ldr r2, .L3088 + ldr r3, .L3088 + str r3, [r2, #104] + ldr r3, .L3088 + ldr r2, [r3, #104] + ldr r3, .L3088 + str r2, [r3, #100] + ldr r3, .L3088 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3088 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3089: + .align 2 +.L3088: + .word GSU + .size _Z9fx_dec_r9v, .-_Z9fx_dec_r9v + .align 2 + .type _Z10fx_dec_r10v, %function +_Z10fx_dec_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3092 + ldr r3, [r3, #40] + sub r2, r3, #1 + ldr r3, .L3092 + str r2, [r3, #40] + ldr r3, .L3092 + ldr r2, [r3, #40] + ldr r3, .L3092 + str r2, [r3, #116] + ldr r3, .L3092 + ldr r2, [r3, #40] + ldr r3, .L3092 + str r2, [r3, #120] + ldr r3, .L3092 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3092 + str r2, [r3, #72] + ldr r2, .L3092 + ldr r3, .L3092 + str r3, [r2, #104] + ldr r3, .L3092 + ldr r2, [r3, #104] + ldr r3, .L3092 + str r2, [r3, #100] + ldr r3, .L3092 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3092 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3093: + .align 2 +.L3092: + .word GSU + .size _Z10fx_dec_r10v, .-_Z10fx_dec_r10v + .align 2 + .type _Z10fx_dec_r11v, %function +_Z10fx_dec_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3096 + ldr r3, [r3, #44] + sub r2, r3, #1 + ldr r3, .L3096 + str r2, [r3, #44] + ldr r3, .L3096 + ldr r2, [r3, #44] + ldr r3, .L3096 + str r2, [r3, #116] + ldr r3, .L3096 + ldr r2, [r3, #44] + ldr r3, .L3096 + str r2, [r3, #120] + ldr r3, .L3096 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3096 + str r2, [r3, #72] + ldr r2, .L3096 + ldr r3, .L3096 + str r3, [r2, #104] + ldr r3, .L3096 + ldr r2, [r3, #104] + ldr r3, .L3096 + str r2, [r3, #100] + ldr r3, .L3096 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3096 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3097: + .align 2 +.L3096: + .word GSU + .size _Z10fx_dec_r11v, .-_Z10fx_dec_r11v + .align 2 + .type _Z10fx_dec_r12v, %function +_Z10fx_dec_r12v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3100 + ldr r3, [r3, #48] + sub r2, r3, #1 + ldr r3, .L3100 + str r2, [r3, #48] + ldr r3, .L3100 + ldr r2, [r3, #48] + ldr r3, .L3100 + str r2, [r3, #116] + ldr r3, .L3100 + ldr r2, [r3, #48] + ldr r3, .L3100 + str r2, [r3, #120] + ldr r3, .L3100 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3100 + str r2, [r3, #72] + ldr r2, .L3100 + ldr r3, .L3100 + str r3, [r2, #104] + ldr r3, .L3100 + ldr r2, [r3, #104] + ldr r3, .L3100 + str r2, [r3, #100] + ldr r3, .L3100 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3100 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3101: + .align 2 +.L3100: + .word GSU + .size _Z10fx_dec_r12v, .-_Z10fx_dec_r12v + .align 2 + .type _Z10fx_dec_r13v, %function +_Z10fx_dec_r13v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3104 + ldr r3, [r3, #52] + sub r2, r3, #1 + ldr r3, .L3104 + str r2, [r3, #52] + ldr r3, .L3104 + ldr r2, [r3, #52] + ldr r3, .L3104 + str r2, [r3, #116] + ldr r3, .L3104 + ldr r2, [r3, #52] + ldr r3, .L3104 + str r2, [r3, #120] + ldr r3, .L3104 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3104 + str r2, [r3, #72] + ldr r2, .L3104 + ldr r3, .L3104 + str r3, [r2, #104] + ldr r3, .L3104 + ldr r2, [r3, #104] + ldr r3, .L3104 + str r2, [r3, #100] + ldr r3, .L3104 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3104 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3105: + .align 2 +.L3104: + .word GSU + .size _Z10fx_dec_r13v, .-_Z10fx_dec_r13v + .align 2 + .type _Z10fx_dec_r14v, %function +_Z10fx_dec_r14v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3108 + ldr r3, [r3, #56] + sub r2, r3, #1 + ldr r3, .L3108 + str r2, [r3, #56] + ldr r3, .L3108 + ldr r2, [r3, #56] + ldr r3, .L3108 + str r2, [r3, #116] + ldr r3, .L3108 + ldr r2, [r3, #56] + ldr r3, .L3108 + str r2, [r3, #120] + ldr r3, .L3108 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3108 + str r2, [r3, #72] + ldr r2, .L3108 + ldr r3, .L3108 + str r3, [r2, #104] + ldr r3, .L3108 + ldr r2, [r3, #104] + ldr r3, .L3108 + str r2, [r3, #100] + ldr r3, .L3108 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3108 + str r2, [r3, #60] + ldr r3, .L3108 + ldr r2, [r3, #468] + ldr r3, .L3108 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3108 + strb r3, [r2, #108] + ldmfd sp, {fp, sp, pc} +.L3109: + .align 2 +.L3108: + .word GSU + .size _Z10fx_dec_r14v, .-_Z10fx_dec_r14v + .align 2 + .type _Z7fx_getbv, %function +_Z7fx_getbv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3114 + ldrb r3, [r3, #108] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3114 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3114 + str r2, [r3, #60] + ldr r3, .L3114 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L3114 + ldr r2, [r3, #100] + ldr r3, .L3114+4 + cmp r2, r3 + bne .L3111 + ldr r3, .L3114 + ldr r2, [r3, #468] + ldr r3, .L3114 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3114 + strb r3, [r2, #108] +.L3111: + ldr r3, .L3114 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3114 + str r2, [r3, #72] + ldr r2, .L3114 + ldr r3, .L3114 + str r3, [r2, #104] + ldr r3, .L3114 + ldr r2, [r3, #104] + ldr r3, .L3114 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3115: + .align 2 +.L3114: + .word GSU + .word GSU+56 + .size _Z7fx_getbv, .-_Z7fx_getbv + .align 2 + .type _Z8fx_getbhv, %function +_Z8fx_getbhv: + @ args = 0, pretend = 0, frame = 8 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #8 + ldr r3, .L3120 + ldrb r3, [r3, #108] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3120 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r3, r3, #255 + mov r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, asl #8 + orr r3, r2, r3 + str r3, [fp, #-20] + ldr r3, .L3120 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3120 + str r2, [r3, #60] + ldr r3, .L3120 + ldr r2, [r3, #100] + ldr r3, [fp, #-20] + str r3, [r2, #0] + ldr r3, .L3120 + ldr r2, [r3, #100] + ldr r3, .L3120+4 + cmp r2, r3 + bne .L3117 + ldr r3, .L3120 + ldr r2, [r3, #468] + ldr r3, .L3120 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3120 + strb r3, [r2, #108] +.L3117: + ldr r3, .L3120 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3120 + str r2, [r3, #72] + ldr r2, .L3120 + ldr r3, .L3120 + str r3, [r2, #104] + ldr r3, .L3120 + ldr r2, [r3, #104] + ldr r3, .L3120 + str r2, [r3, #100] + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L3121: + .align 2 +.L3120: + .word GSU + .word GSU+56 + .size _Z8fx_getbhv, .-_Z8fx_getbhv + .align 2 + .type _Z8fx_getblv, %function +_Z8fx_getblv: + @ args = 0, pretend = 0, frame = 8 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #8 + ldr r3, .L3126 + ldrb r3, [r3, #108] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3126 + ldr r3, [r3, #104] + ldr r3, [r3, #0] + and r2, r3, #65280 + ldr r3, [fp, #-16] + orr r3, r2, r3 + str r3, [fp, #-20] + ldr r3, .L3126 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3126 + str r2, [r3, #60] + ldr r3, .L3126 + ldr r2, [r3, #100] + ldr r3, [fp, #-20] + str r3, [r2, #0] + ldr r3, .L3126 + ldr r2, [r3, #100] + ldr r3, .L3126+4 + cmp r2, r3 + bne .L3123 + ldr r3, .L3126 + ldr r2, [r3, #468] + ldr r3, .L3126 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3126 + strb r3, [r2, #108] +.L3123: + ldr r3, .L3126 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3126 + str r2, [r3, #72] + ldr r2, .L3126 + ldr r3, .L3126 + str r3, [r2, #104] + ldr r3, .L3126 + ldr r2, [r3, #104] + ldr r3, .L3126 + str r2, [r3, #100] + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L3127: + .align 2 +.L3126: + .word GSU + .word GSU+56 + .size _Z8fx_getblv, .-_Z8fx_getblv + .align 2 + .type _Z8fx_getbsv, %function +_Z8fx_getbsv: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3132 + ldrb r3, [r3, #108] @ zero_extendqisi2 + mov r3, r3, asl #24 + mov r3, r3, asr #24 + str r3, [fp, #-16] + ldr r3, .L3132 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3132 + str r2, [r3, #60] + ldr r3, .L3132 + ldr r2, [r3, #100] + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L3132 + ldr r2, [r3, #100] + ldr r3, .L3132+4 + cmp r2, r3 + bne .L3129 + ldr r3, .L3132 + ldr r2, [r3, #468] + ldr r3, .L3132 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3132 + strb r3, [r2, #108] +.L3129: + ldr r3, .L3132 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3132 + str r2, [r3, #72] + ldr r2, .L3132 + ldr r3, .L3132 + str r3, [r2, #104] + ldr r3, .L3132 + ldr r2, [r3, #104] + ldr r3, .L3132 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3133: + .align 2 +.L3132: + .word GSU + .word GSU+56 + .size _Z8fx_getbsv, .-_Z8fx_getbsv + .align 2 + .type _Z9fx_iwt_r0v, %function +_Z9fx_iwt_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3136 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3136 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3136 + str r2, [r3, #60] + ldr r3, .L3136 + ldr r2, [r3, #472] + ldr r3, .L3136 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3136 + strb r3, [r2, #109] + ldr r3, .L3136 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3136 + str r2, [r3, #60] + ldr r3, .L3136 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3136 + ldr r2, [r3, #472] + ldr r3, .L3136 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3136 + strb r3, [r2, #109] + ldr r3, .L3136 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3136 + str r2, [r3, #60] + ldr r2, .L3136 + ldr r3, [fp, #-16] + str r3, [r2, #0] + ldr r3, .L3136 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3136 + str r2, [r3, #72] + ldr r2, .L3136 + ldr r3, .L3136 + str r3, [r2, #104] + ldr r3, .L3136 + ldr r2, [r3, #104] + ldr r3, .L3136 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3137: + .align 2 +.L3136: + .word GSU + .size _Z9fx_iwt_r0v, .-_Z9fx_iwt_r0v + .align 2 + .type _Z9fx_iwt_r1v, %function +_Z9fx_iwt_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3140 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3140 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3140 + str r2, [r3, #60] + ldr r3, .L3140 + ldr r2, [r3, #472] + ldr r3, .L3140 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3140 + strb r3, [r2, #109] + ldr r3, .L3140 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3140 + str r2, [r3, #60] + ldr r3, .L3140 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3140 + ldr r2, [r3, #472] + ldr r3, .L3140 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3140 + strb r3, [r2, #109] + ldr r3, .L3140 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3140 + str r2, [r3, #60] + ldr r2, .L3140 + ldr r3, [fp, #-16] + str r3, [r2, #4] + ldr r3, .L3140 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3140 + str r2, [r3, #72] + ldr r2, .L3140 + ldr r3, .L3140 + str r3, [r2, #104] + ldr r3, .L3140 + ldr r2, [r3, #104] + ldr r3, .L3140 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3141: + .align 2 +.L3140: + .word GSU + .size _Z9fx_iwt_r1v, .-_Z9fx_iwt_r1v + .align 2 + .type _Z9fx_iwt_r2v, %function +_Z9fx_iwt_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3144 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3144 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3144 + str r2, [r3, #60] + ldr r3, .L3144 + ldr r2, [r3, #472] + ldr r3, .L3144 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3144 + strb r3, [r2, #109] + ldr r3, .L3144 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3144 + str r2, [r3, #60] + ldr r3, .L3144 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3144 + ldr r2, [r3, #472] + ldr r3, .L3144 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3144 + strb r3, [r2, #109] + ldr r3, .L3144 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3144 + str r2, [r3, #60] + ldr r2, .L3144 + ldr r3, [fp, #-16] + str r3, [r2, #8] + ldr r3, .L3144 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3144 + str r2, [r3, #72] + ldr r2, .L3144 + ldr r3, .L3144 + str r3, [r2, #104] + ldr r3, .L3144 + ldr r2, [r3, #104] + ldr r3, .L3144 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3145: + .align 2 +.L3144: + .word GSU + .size _Z9fx_iwt_r2v, .-_Z9fx_iwt_r2v + .align 2 + .type _Z9fx_iwt_r3v, %function +_Z9fx_iwt_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3148 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3148 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3148 + str r2, [r3, #60] + ldr r3, .L3148 + ldr r2, [r3, #472] + ldr r3, .L3148 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3148 + strb r3, [r2, #109] + ldr r3, .L3148 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3148 + str r2, [r3, #60] + ldr r3, .L3148 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3148 + ldr r2, [r3, #472] + ldr r3, .L3148 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3148 + strb r3, [r2, #109] + ldr r3, .L3148 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3148 + str r2, [r3, #60] + ldr r2, .L3148 + ldr r3, [fp, #-16] + str r3, [r2, #12] + ldr r3, .L3148 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3148 + str r2, [r3, #72] + ldr r2, .L3148 + ldr r3, .L3148 + str r3, [r2, #104] + ldr r3, .L3148 + ldr r2, [r3, #104] + ldr r3, .L3148 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3149: + .align 2 +.L3148: + .word GSU + .size _Z9fx_iwt_r3v, .-_Z9fx_iwt_r3v + .align 2 + .type _Z9fx_iwt_r4v, %function +_Z9fx_iwt_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3152 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3152 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3152 + str r2, [r3, #60] + ldr r3, .L3152 + ldr r2, [r3, #472] + ldr r3, .L3152 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3152 + strb r3, [r2, #109] + ldr r3, .L3152 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3152 + str r2, [r3, #60] + ldr r3, .L3152 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3152 + ldr r2, [r3, #472] + ldr r3, .L3152 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3152 + strb r3, [r2, #109] + ldr r3, .L3152 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3152 + str r2, [r3, #60] + ldr r2, .L3152 + ldr r3, [fp, #-16] + str r3, [r2, #16] + ldr r3, .L3152 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3152 + str r2, [r3, #72] + ldr r2, .L3152 + ldr r3, .L3152 + str r3, [r2, #104] + ldr r3, .L3152 + ldr r2, [r3, #104] + ldr r3, .L3152 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3153: + .align 2 +.L3152: + .word GSU + .size _Z9fx_iwt_r4v, .-_Z9fx_iwt_r4v + .align 2 + .type _Z9fx_iwt_r5v, %function +_Z9fx_iwt_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3156 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3156 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3156 + str r2, [r3, #60] + ldr r3, .L3156 + ldr r2, [r3, #472] + ldr r3, .L3156 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3156 + strb r3, [r2, #109] + ldr r3, .L3156 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3156 + str r2, [r3, #60] + ldr r3, .L3156 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3156 + ldr r2, [r3, #472] + ldr r3, .L3156 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3156 + strb r3, [r2, #109] + ldr r3, .L3156 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3156 + str r2, [r3, #60] + ldr r2, .L3156 + ldr r3, [fp, #-16] + str r3, [r2, #20] + ldr r3, .L3156 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3156 + str r2, [r3, #72] + ldr r2, .L3156 + ldr r3, .L3156 + str r3, [r2, #104] + ldr r3, .L3156 + ldr r2, [r3, #104] + ldr r3, .L3156 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3157: + .align 2 +.L3156: + .word GSU + .size _Z9fx_iwt_r5v, .-_Z9fx_iwt_r5v + .align 2 + .type _Z9fx_iwt_r6v, %function +_Z9fx_iwt_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3160 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3160 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3160 + str r2, [r3, #60] + ldr r3, .L3160 + ldr r2, [r3, #472] + ldr r3, .L3160 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3160 + strb r3, [r2, #109] + ldr r3, .L3160 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3160 + str r2, [r3, #60] + ldr r3, .L3160 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3160 + ldr r2, [r3, #472] + ldr r3, .L3160 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3160 + strb r3, [r2, #109] + ldr r3, .L3160 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3160 + str r2, [r3, #60] + ldr r2, .L3160 + ldr r3, [fp, #-16] + str r3, [r2, #24] + ldr r3, .L3160 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3160 + str r2, [r3, #72] + ldr r2, .L3160 + ldr r3, .L3160 + str r3, [r2, #104] + ldr r3, .L3160 + ldr r2, [r3, #104] + ldr r3, .L3160 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3161: + .align 2 +.L3160: + .word GSU + .size _Z9fx_iwt_r6v, .-_Z9fx_iwt_r6v + .align 2 + .type _Z9fx_iwt_r7v, %function +_Z9fx_iwt_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3164 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3164 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3164 + str r2, [r3, #60] + ldr r3, .L3164 + ldr r2, [r3, #472] + ldr r3, .L3164 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3164 + strb r3, [r2, #109] + ldr r3, .L3164 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3164 + str r2, [r3, #60] + ldr r3, .L3164 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3164 + ldr r2, [r3, #472] + ldr r3, .L3164 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3164 + strb r3, [r2, #109] + ldr r3, .L3164 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3164 + str r2, [r3, #60] + ldr r2, .L3164 + ldr r3, [fp, #-16] + str r3, [r2, #28] + ldr r3, .L3164 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3164 + str r2, [r3, #72] + ldr r2, .L3164 + ldr r3, .L3164 + str r3, [r2, #104] + ldr r3, .L3164 + ldr r2, [r3, #104] + ldr r3, .L3164 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3165: + .align 2 +.L3164: + .word GSU + .size _Z9fx_iwt_r7v, .-_Z9fx_iwt_r7v + .align 2 + .type _Z9fx_iwt_r8v, %function +_Z9fx_iwt_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3168 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3168 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3168 + str r2, [r3, #60] + ldr r3, .L3168 + ldr r2, [r3, #472] + ldr r3, .L3168 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3168 + strb r3, [r2, #109] + ldr r3, .L3168 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3168 + str r2, [r3, #60] + ldr r3, .L3168 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3168 + ldr r2, [r3, #472] + ldr r3, .L3168 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3168 + strb r3, [r2, #109] + ldr r3, .L3168 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3168 + str r2, [r3, #60] + ldr r2, .L3168 + ldr r3, [fp, #-16] + str r3, [r2, #32] + ldr r3, .L3168 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3168 + str r2, [r3, #72] + ldr r2, .L3168 + ldr r3, .L3168 + str r3, [r2, #104] + ldr r3, .L3168 + ldr r2, [r3, #104] + ldr r3, .L3168 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3169: + .align 2 +.L3168: + .word GSU + .size _Z9fx_iwt_r8v, .-_Z9fx_iwt_r8v + .align 2 + .type _Z9fx_iwt_r9v, %function +_Z9fx_iwt_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3172 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3172 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3172 + str r2, [r3, #60] + ldr r3, .L3172 + ldr r2, [r3, #472] + ldr r3, .L3172 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3172 + strb r3, [r2, #109] + ldr r3, .L3172 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3172 + str r2, [r3, #60] + ldr r3, .L3172 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3172 + ldr r2, [r3, #472] + ldr r3, .L3172 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3172 + strb r3, [r2, #109] + ldr r3, .L3172 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3172 + str r2, [r3, #60] + ldr r2, .L3172 + ldr r3, [fp, #-16] + str r3, [r2, #36] + ldr r3, .L3172 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3172 + str r2, [r3, #72] + ldr r2, .L3172 + ldr r3, .L3172 + str r3, [r2, #104] + ldr r3, .L3172 + ldr r2, [r3, #104] + ldr r3, .L3172 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3173: + .align 2 +.L3172: + .word GSU + .size _Z9fx_iwt_r9v, .-_Z9fx_iwt_r9v + .align 2 + .type _Z10fx_iwt_r10v, %function +_Z10fx_iwt_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3176 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3176 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3176 + str r2, [r3, #60] + ldr r3, .L3176 + ldr r2, [r3, #472] + ldr r3, .L3176 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3176 + strb r3, [r2, #109] + ldr r3, .L3176 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3176 + str r2, [r3, #60] + ldr r3, .L3176 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3176 + ldr r2, [r3, #472] + ldr r3, .L3176 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3176 + strb r3, [r2, #109] + ldr r3, .L3176 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3176 + str r2, [r3, #60] + ldr r2, .L3176 + ldr r3, [fp, #-16] + str r3, [r2, #40] + ldr r3, .L3176 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3176 + str r2, [r3, #72] + ldr r2, .L3176 + ldr r3, .L3176 + str r3, [r2, #104] + ldr r3, .L3176 + ldr r2, [r3, #104] + ldr r3, .L3176 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3177: + .align 2 +.L3176: + .word GSU + .size _Z10fx_iwt_r10v, .-_Z10fx_iwt_r10v + .align 2 + .type _Z10fx_iwt_r11v, %function +_Z10fx_iwt_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3180 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3180 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3180 + str r2, [r3, #60] + ldr r3, .L3180 + ldr r2, [r3, #472] + ldr r3, .L3180 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3180 + strb r3, [r2, #109] + ldr r3, .L3180 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3180 + str r2, [r3, #60] + ldr r3, .L3180 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3180 + ldr r2, [r3, #472] + ldr r3, .L3180 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3180 + strb r3, [r2, #109] + ldr r3, .L3180 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3180 + str r2, [r3, #60] + ldr r2, .L3180 + ldr r3, [fp, #-16] + str r3, [r2, #44] + ldr r3, .L3180 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3180 + str r2, [r3, #72] + ldr r2, .L3180 + ldr r3, .L3180 + str r3, [r2, #104] + ldr r3, .L3180 + ldr r2, [r3, #104] + ldr r3, .L3180 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3181: + .align 2 +.L3180: + .word GSU + .size _Z10fx_iwt_r11v, .-_Z10fx_iwt_r11v + .align 2 + .type _Z10fx_iwt_r12v, %function +_Z10fx_iwt_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3184 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3184 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3184 + str r2, [r3, #60] + ldr r3, .L3184 + ldr r2, [r3, #472] + ldr r3, .L3184 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3184 + strb r3, [r2, #109] + ldr r3, .L3184 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3184 + str r2, [r3, #60] + ldr r3, .L3184 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3184 + ldr r2, [r3, #472] + ldr r3, .L3184 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3184 + strb r3, [r2, #109] + ldr r3, .L3184 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3184 + str r2, [r3, #60] + ldr r2, .L3184 + ldr r3, [fp, #-16] + str r3, [r2, #48] + ldr r3, .L3184 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3184 + str r2, [r3, #72] + ldr r2, .L3184 + ldr r3, .L3184 + str r3, [r2, #104] + ldr r3, .L3184 + ldr r2, [r3, #104] + ldr r3, .L3184 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3185: + .align 2 +.L3184: + .word GSU + .size _Z10fx_iwt_r12v, .-_Z10fx_iwt_r12v + .align 2 + .type _Z10fx_iwt_r13v, %function +_Z10fx_iwt_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3188 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3188 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3188 + str r2, [r3, #60] + ldr r3, .L3188 + ldr r2, [r3, #472] + ldr r3, .L3188 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3188 + strb r3, [r2, #109] + ldr r3, .L3188 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3188 + str r2, [r3, #60] + ldr r3, .L3188 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3188 + ldr r2, [r3, #472] + ldr r3, .L3188 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3188 + strb r3, [r2, #109] + ldr r3, .L3188 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3188 + str r2, [r3, #60] + ldr r2, .L3188 + ldr r3, [fp, #-16] + str r3, [r2, #52] + ldr r3, .L3188 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3188 + str r2, [r3, #72] + ldr r2, .L3188 + ldr r3, .L3188 + str r3, [r2, #104] + ldr r3, .L3188 + ldr r2, [r3, #104] + ldr r3, .L3188 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3189: + .align 2 +.L3188: + .word GSU + .size _Z10fx_iwt_r13v, .-_Z10fx_iwt_r13v + .align 2 + .type _Z10fx_iwt_r14v, %function +_Z10fx_iwt_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3192 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3192 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3192 + str r2, [r3, #60] + ldr r3, .L3192 + ldr r2, [r3, #472] + ldr r3, .L3192 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3192 + strb r3, [r2, #109] + ldr r3, .L3192 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3192 + str r2, [r3, #60] + ldr r3, .L3192 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3192 + ldr r2, [r3, #472] + ldr r3, .L3192 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3192 + strb r3, [r2, #109] + ldr r3, .L3192 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3192 + str r2, [r3, #60] + ldr r2, .L3192 + ldr r3, [fp, #-16] + str r3, [r2, #56] + ldr r3, .L3192 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3192 + str r2, [r3, #72] + ldr r2, .L3192 + ldr r3, .L3192 + str r3, [r2, #104] + ldr r3, .L3192 + ldr r2, [r3, #104] + ldr r3, .L3192 + str r2, [r3, #100] + ldr r3, .L3192 + ldr r2, [r3, #468] + ldr r3, .L3192 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3192 + strb r3, [r2, #108] + ldmib sp, {fp, sp, pc} +.L3193: + .align 2 +.L3192: + .word GSU + .size _Z10fx_iwt_r14v, .-_Z10fx_iwt_r14v + .align 2 + .type _Z10fx_iwt_r15v, %function +_Z10fx_iwt_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3196 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3196 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3196 + str r2, [r3, #60] + ldr r3, .L3196 + ldr r2, [r3, #472] + ldr r3, .L3196 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3196 + strb r3, [r2, #109] + ldr r3, .L3196 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3196 + str r2, [r3, #60] + ldr r3, .L3196 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3, asl #8 + ldr r3, [fp, #-16] + orr r3, r3, r2 + str r3, [fp, #-16] + ldr r3, .L3196 + ldr r2, [r3, #472] + ldr r3, .L3196 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3196 + strb r3, [r2, #109] + ldr r3, .L3196 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3196 + str r2, [r3, #60] + ldr r2, .L3196 + ldr r3, [fp, #-16] + str r3, [r2, #60] + ldr r3, .L3196 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3196 + str r2, [r3, #72] + ldr r2, .L3196 + ldr r3, .L3196 + str r3, [r2, #104] + ldr r3, .L3196 + ldr r2, [r3, #104] + ldr r3, .L3196 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3197: + .align 2 +.L3196: + .word GSU + .size _Z10fx_iwt_r15v, .-_Z10fx_iwt_r15v + .align 2 + .type _Z8fx_lm_r0v, %function +_Z8fx_lm_r0v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3200 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3200 + str r2, [r3, #96] + ldr r3, .L3200 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3200 + str r2, [r3, #60] + ldr r3, .L3200 + ldr r2, [r3, #472] + ldr r3, .L3200 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3200 + strb r3, [r2, #109] + ldr r3, .L3200 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3200 + str r2, [r3, #60] + ldr r3, .L3200 + ldr r2, [r3, #96] + ldr r3, .L3200 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3200 + str r2, [r3, #96] + ldr r3, .L3200 + ldr r2, [r3, #472] + ldr r3, .L3200 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3200 + strb r3, [r2, #109] + ldr r3, .L3200 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3200 + str r2, [r3, #60] + ldr r3, .L3200 + ldr r2, [r3, #464] + ldr r3, .L3200 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3200 + str r2, [r3, #0] + ldr r3, .L3200 + ldr r1, [r3, #0] + ldr r3, .L3200 + ldr r2, [r3, #464] + ldr r3, .L3200 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3200 + str r2, [r3, #0] + ldr r3, .L3200 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3200 + str r2, [r3, #72] + ldr r2, .L3200 + ldr r3, .L3200 + str r3, [r2, #104] + ldr r3, .L3200 + ldr r2, [r3, #104] + ldr r3, .L3200 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3201: + .align 2 +.L3200: + .word GSU + .size _Z8fx_lm_r0v, .-_Z8fx_lm_r0v + .align 2 + .type _Z8fx_lm_r1v, %function +_Z8fx_lm_r1v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3204 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3204 + str r2, [r3, #96] + ldr r3, .L3204 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3204 + str r2, [r3, #60] + ldr r3, .L3204 + ldr r2, [r3, #472] + ldr r3, .L3204 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3204 + strb r3, [r2, #109] + ldr r3, .L3204 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3204 + str r2, [r3, #60] + ldr r3, .L3204 + ldr r2, [r3, #96] + ldr r3, .L3204 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3204 + str r2, [r3, #96] + ldr r3, .L3204 + ldr r2, [r3, #472] + ldr r3, .L3204 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3204 + strb r3, [r2, #109] + ldr r3, .L3204 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3204 + str r2, [r3, #60] + ldr r3, .L3204 + ldr r2, [r3, #464] + ldr r3, .L3204 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3204 + str r2, [r3, #4] + ldr r3, .L3204 + ldr r1, [r3, #4] + ldr r3, .L3204 + ldr r2, [r3, #464] + ldr r3, .L3204 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3204 + str r2, [r3, #4] + ldr r3, .L3204 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3204 + str r2, [r3, #72] + ldr r2, .L3204 + ldr r3, .L3204 + str r3, [r2, #104] + ldr r3, .L3204 + ldr r2, [r3, #104] + ldr r3, .L3204 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3205: + .align 2 +.L3204: + .word GSU + .size _Z8fx_lm_r1v, .-_Z8fx_lm_r1v + .align 2 + .type _Z8fx_lm_r2v, %function +_Z8fx_lm_r2v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3208 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3208 + str r2, [r3, #96] + ldr r3, .L3208 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3208 + str r2, [r3, #60] + ldr r3, .L3208 + ldr r2, [r3, #472] + ldr r3, .L3208 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3208 + strb r3, [r2, #109] + ldr r3, .L3208 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3208 + str r2, [r3, #60] + ldr r3, .L3208 + ldr r2, [r3, #96] + ldr r3, .L3208 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3208 + str r2, [r3, #96] + ldr r3, .L3208 + ldr r2, [r3, #472] + ldr r3, .L3208 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3208 + strb r3, [r2, #109] + ldr r3, .L3208 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3208 + str r2, [r3, #60] + ldr r3, .L3208 + ldr r2, [r3, #464] + ldr r3, .L3208 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3208 + str r2, [r3, #8] + ldr r3, .L3208 + ldr r1, [r3, #8] + ldr r3, .L3208 + ldr r2, [r3, #464] + ldr r3, .L3208 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3208 + str r2, [r3, #8] + ldr r3, .L3208 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3208 + str r2, [r3, #72] + ldr r2, .L3208 + ldr r3, .L3208 + str r3, [r2, #104] + ldr r3, .L3208 + ldr r2, [r3, #104] + ldr r3, .L3208 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3209: + .align 2 +.L3208: + .word GSU + .size _Z8fx_lm_r2v, .-_Z8fx_lm_r2v + .align 2 + .type _Z8fx_lm_r3v, %function +_Z8fx_lm_r3v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3212 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3212 + str r2, [r3, #96] + ldr r3, .L3212 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3212 + str r2, [r3, #60] + ldr r3, .L3212 + ldr r2, [r3, #472] + ldr r3, .L3212 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3212 + strb r3, [r2, #109] + ldr r3, .L3212 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3212 + str r2, [r3, #60] + ldr r3, .L3212 + ldr r2, [r3, #96] + ldr r3, .L3212 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3212 + str r2, [r3, #96] + ldr r3, .L3212 + ldr r2, [r3, #472] + ldr r3, .L3212 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3212 + strb r3, [r2, #109] + ldr r3, .L3212 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3212 + str r2, [r3, #60] + ldr r3, .L3212 + ldr r2, [r3, #464] + ldr r3, .L3212 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3212 + str r2, [r3, #12] + ldr r3, .L3212 + ldr r1, [r3, #12] + ldr r3, .L3212 + ldr r2, [r3, #464] + ldr r3, .L3212 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3212 + str r2, [r3, #12] + ldr r3, .L3212 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3212 + str r2, [r3, #72] + ldr r2, .L3212 + ldr r3, .L3212 + str r3, [r2, #104] + ldr r3, .L3212 + ldr r2, [r3, #104] + ldr r3, .L3212 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3213: + .align 2 +.L3212: + .word GSU + .size _Z8fx_lm_r3v, .-_Z8fx_lm_r3v + .align 2 + .type _Z8fx_lm_r4v, %function +_Z8fx_lm_r4v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3216 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3216 + str r2, [r3, #96] + ldr r3, .L3216 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3216 + str r2, [r3, #60] + ldr r3, .L3216 + ldr r2, [r3, #472] + ldr r3, .L3216 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3216 + strb r3, [r2, #109] + ldr r3, .L3216 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3216 + str r2, [r3, #60] + ldr r3, .L3216 + ldr r2, [r3, #96] + ldr r3, .L3216 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3216 + str r2, [r3, #96] + ldr r3, .L3216 + ldr r2, [r3, #472] + ldr r3, .L3216 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3216 + strb r3, [r2, #109] + ldr r3, .L3216 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3216 + str r2, [r3, #60] + ldr r3, .L3216 + ldr r2, [r3, #464] + ldr r3, .L3216 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3216 + str r2, [r3, #16] + ldr r3, .L3216 + ldr r1, [r3, #16] + ldr r3, .L3216 + ldr r2, [r3, #464] + ldr r3, .L3216 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3216 + str r2, [r3, #16] + ldr r3, .L3216 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3216 + str r2, [r3, #72] + ldr r2, .L3216 + ldr r3, .L3216 + str r3, [r2, #104] + ldr r3, .L3216 + ldr r2, [r3, #104] + ldr r3, .L3216 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3217: + .align 2 +.L3216: + .word GSU + .size _Z8fx_lm_r4v, .-_Z8fx_lm_r4v + .align 2 + .type _Z8fx_lm_r5v, %function +_Z8fx_lm_r5v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3220 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3220 + str r2, [r3, #96] + ldr r3, .L3220 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3220 + str r2, [r3, #60] + ldr r3, .L3220 + ldr r2, [r3, #472] + ldr r3, .L3220 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3220 + strb r3, [r2, #109] + ldr r3, .L3220 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3220 + str r2, [r3, #60] + ldr r3, .L3220 + ldr r2, [r3, #96] + ldr r3, .L3220 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3220 + str r2, [r3, #96] + ldr r3, .L3220 + ldr r2, [r3, #472] + ldr r3, .L3220 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3220 + strb r3, [r2, #109] + ldr r3, .L3220 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3220 + str r2, [r3, #60] + ldr r3, .L3220 + ldr r2, [r3, #464] + ldr r3, .L3220 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3220 + str r2, [r3, #20] + ldr r3, .L3220 + ldr r1, [r3, #20] + ldr r3, .L3220 + ldr r2, [r3, #464] + ldr r3, .L3220 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3220 + str r2, [r3, #20] + ldr r3, .L3220 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3220 + str r2, [r3, #72] + ldr r2, .L3220 + ldr r3, .L3220 + str r3, [r2, #104] + ldr r3, .L3220 + ldr r2, [r3, #104] + ldr r3, .L3220 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3221: + .align 2 +.L3220: + .word GSU + .size _Z8fx_lm_r5v, .-_Z8fx_lm_r5v + .align 2 + .type _Z8fx_lm_r6v, %function +_Z8fx_lm_r6v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3224 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3224 + str r2, [r3, #96] + ldr r3, .L3224 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3224 + str r2, [r3, #60] + ldr r3, .L3224 + ldr r2, [r3, #472] + ldr r3, .L3224 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3224 + strb r3, [r2, #109] + ldr r3, .L3224 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3224 + str r2, [r3, #60] + ldr r3, .L3224 + ldr r2, [r3, #96] + ldr r3, .L3224 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3224 + str r2, [r3, #96] + ldr r3, .L3224 + ldr r2, [r3, #472] + ldr r3, .L3224 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3224 + strb r3, [r2, #109] + ldr r3, .L3224 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3224 + str r2, [r3, #60] + ldr r3, .L3224 + ldr r2, [r3, #464] + ldr r3, .L3224 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3224 + str r2, [r3, #24] + ldr r3, .L3224 + ldr r1, [r3, #24] + ldr r3, .L3224 + ldr r2, [r3, #464] + ldr r3, .L3224 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3224 + str r2, [r3, #24] + ldr r3, .L3224 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3224 + str r2, [r3, #72] + ldr r2, .L3224 + ldr r3, .L3224 + str r3, [r2, #104] + ldr r3, .L3224 + ldr r2, [r3, #104] + ldr r3, .L3224 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3225: + .align 2 +.L3224: + .word GSU + .size _Z8fx_lm_r6v, .-_Z8fx_lm_r6v + .align 2 + .type _Z8fx_lm_r7v, %function +_Z8fx_lm_r7v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3228 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3228 + str r2, [r3, #96] + ldr r3, .L3228 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3228 + str r2, [r3, #60] + ldr r3, .L3228 + ldr r2, [r3, #472] + ldr r3, .L3228 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3228 + strb r3, [r2, #109] + ldr r3, .L3228 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3228 + str r2, [r3, #60] + ldr r3, .L3228 + ldr r2, [r3, #96] + ldr r3, .L3228 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3228 + str r2, [r3, #96] + ldr r3, .L3228 + ldr r2, [r3, #472] + ldr r3, .L3228 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3228 + strb r3, [r2, #109] + ldr r3, .L3228 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3228 + str r2, [r3, #60] + ldr r3, .L3228 + ldr r2, [r3, #464] + ldr r3, .L3228 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3228 + str r2, [r3, #28] + ldr r3, .L3228 + ldr r1, [r3, #28] + ldr r3, .L3228 + ldr r2, [r3, #464] + ldr r3, .L3228 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3228 + str r2, [r3, #28] + ldr r3, .L3228 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3228 + str r2, [r3, #72] + ldr r2, .L3228 + ldr r3, .L3228 + str r3, [r2, #104] + ldr r3, .L3228 + ldr r2, [r3, #104] + ldr r3, .L3228 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3229: + .align 2 +.L3228: + .word GSU + .size _Z8fx_lm_r7v, .-_Z8fx_lm_r7v + .align 2 + .type _Z8fx_lm_r8v, %function +_Z8fx_lm_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3232 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3232 + str r2, [r3, #96] + ldr r3, .L3232 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3232 + str r2, [r3, #60] + ldr r3, .L3232 + ldr r2, [r3, #472] + ldr r3, .L3232 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3232 + strb r3, [r2, #109] + ldr r3, .L3232 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3232 + str r2, [r3, #60] + ldr r3, .L3232 + ldr r2, [r3, #96] + ldr r3, .L3232 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3232 + str r2, [r3, #96] + ldr r3, .L3232 + ldr r2, [r3, #472] + ldr r3, .L3232 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3232 + strb r3, [r2, #109] + ldr r3, .L3232 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3232 + str r2, [r3, #60] + ldr r3, .L3232 + ldr r2, [r3, #464] + ldr r3, .L3232 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3232 + str r2, [r3, #32] + ldr r3, .L3232 + ldr r1, [r3, #32] + ldr r3, .L3232 + ldr r2, [r3, #464] + ldr r3, .L3232 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3232 + str r2, [r3, #32] + ldr r3, .L3232 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3232 + str r2, [r3, #72] + ldr r2, .L3232 + ldr r3, .L3232 + str r3, [r2, #104] + ldr r3, .L3232 + ldr r2, [r3, #104] + ldr r3, .L3232 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3233: + .align 2 +.L3232: + .word GSU + .size _Z8fx_lm_r8v, .-_Z8fx_lm_r8v + .align 2 + .type _Z8fx_lm_r9v, %function +_Z8fx_lm_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3236 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3236 + str r2, [r3, #96] + ldr r3, .L3236 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3236 + str r2, [r3, #60] + ldr r3, .L3236 + ldr r2, [r3, #472] + ldr r3, .L3236 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3236 + strb r3, [r2, #109] + ldr r3, .L3236 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3236 + str r2, [r3, #60] + ldr r3, .L3236 + ldr r2, [r3, #96] + ldr r3, .L3236 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3236 + str r2, [r3, #96] + ldr r3, .L3236 + ldr r2, [r3, #472] + ldr r3, .L3236 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3236 + strb r3, [r2, #109] + ldr r3, .L3236 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3236 + str r2, [r3, #60] + ldr r3, .L3236 + ldr r2, [r3, #464] + ldr r3, .L3236 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3236 + str r2, [r3, #36] + ldr r3, .L3236 + ldr r1, [r3, #36] + ldr r3, .L3236 + ldr r2, [r3, #464] + ldr r3, .L3236 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3236 + str r2, [r3, #36] + ldr r3, .L3236 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3236 + str r2, [r3, #72] + ldr r2, .L3236 + ldr r3, .L3236 + str r3, [r2, #104] + ldr r3, .L3236 + ldr r2, [r3, #104] + ldr r3, .L3236 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3237: + .align 2 +.L3236: + .word GSU + .size _Z8fx_lm_r9v, .-_Z8fx_lm_r9v + .align 2 + .type _Z9fx_lm_r10v, %function +_Z9fx_lm_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3240 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3240 + str r2, [r3, #96] + ldr r3, .L3240 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3240 + str r2, [r3, #60] + ldr r3, .L3240 + ldr r2, [r3, #472] + ldr r3, .L3240 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3240 + strb r3, [r2, #109] + ldr r3, .L3240 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3240 + str r2, [r3, #60] + ldr r3, .L3240 + ldr r2, [r3, #96] + ldr r3, .L3240 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3240 + str r2, [r3, #96] + ldr r3, .L3240 + ldr r2, [r3, #472] + ldr r3, .L3240 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3240 + strb r3, [r2, #109] + ldr r3, .L3240 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3240 + str r2, [r3, #60] + ldr r3, .L3240 + ldr r2, [r3, #464] + ldr r3, .L3240 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3240 + str r2, [r3, #40] + ldr r3, .L3240 + ldr r1, [r3, #40] + ldr r3, .L3240 + ldr r2, [r3, #464] + ldr r3, .L3240 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3240 + str r2, [r3, #40] + ldr r3, .L3240 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3240 + str r2, [r3, #72] + ldr r2, .L3240 + ldr r3, .L3240 + str r3, [r2, #104] + ldr r3, .L3240 + ldr r2, [r3, #104] + ldr r3, .L3240 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3241: + .align 2 +.L3240: + .word GSU + .size _Z9fx_lm_r10v, .-_Z9fx_lm_r10v + .align 2 + .type _Z9fx_lm_r11v, %function +_Z9fx_lm_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3244 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3244 + str r2, [r3, #96] + ldr r3, .L3244 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3244 + str r2, [r3, #60] + ldr r3, .L3244 + ldr r2, [r3, #472] + ldr r3, .L3244 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3244 + strb r3, [r2, #109] + ldr r3, .L3244 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3244 + str r2, [r3, #60] + ldr r3, .L3244 + ldr r2, [r3, #96] + ldr r3, .L3244 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3244 + str r2, [r3, #96] + ldr r3, .L3244 + ldr r2, [r3, #472] + ldr r3, .L3244 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3244 + strb r3, [r2, #109] + ldr r3, .L3244 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3244 + str r2, [r3, #60] + ldr r3, .L3244 + ldr r2, [r3, #464] + ldr r3, .L3244 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3244 + str r2, [r3, #44] + ldr r3, .L3244 + ldr r1, [r3, #44] + ldr r3, .L3244 + ldr r2, [r3, #464] + ldr r3, .L3244 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3244 + str r2, [r3, #44] + ldr r3, .L3244 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3244 + str r2, [r3, #72] + ldr r2, .L3244 + ldr r3, .L3244 + str r3, [r2, #104] + ldr r3, .L3244 + ldr r2, [r3, #104] + ldr r3, .L3244 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3245: + .align 2 +.L3244: + .word GSU + .size _Z9fx_lm_r11v, .-_Z9fx_lm_r11v + .align 2 + .type _Z9fx_lm_r12v, %function +_Z9fx_lm_r12v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3248 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3248 + str r2, [r3, #96] + ldr r3, .L3248 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3248 + str r2, [r3, #60] + ldr r3, .L3248 + ldr r2, [r3, #472] + ldr r3, .L3248 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3248 + strb r3, [r2, #109] + ldr r3, .L3248 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3248 + str r2, [r3, #60] + ldr r3, .L3248 + ldr r2, [r3, #96] + ldr r3, .L3248 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3248 + str r2, [r3, #96] + ldr r3, .L3248 + ldr r2, [r3, #472] + ldr r3, .L3248 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3248 + strb r3, [r2, #109] + ldr r3, .L3248 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3248 + str r2, [r3, #60] + ldr r3, .L3248 + ldr r2, [r3, #464] + ldr r3, .L3248 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3248 + str r2, [r3, #48] + ldr r3, .L3248 + ldr r1, [r3, #48] + ldr r3, .L3248 + ldr r2, [r3, #464] + ldr r3, .L3248 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3248 + str r2, [r3, #48] + ldr r3, .L3248 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3248 + str r2, [r3, #72] + ldr r2, .L3248 + ldr r3, .L3248 + str r3, [r2, #104] + ldr r3, .L3248 + ldr r2, [r3, #104] + ldr r3, .L3248 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3249: + .align 2 +.L3248: + .word GSU + .size _Z9fx_lm_r12v, .-_Z9fx_lm_r12v + .align 2 + .type _Z9fx_lm_r13v, %function +_Z9fx_lm_r13v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3252 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3252 + str r2, [r3, #96] + ldr r3, .L3252 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3252 + str r2, [r3, #60] + ldr r3, .L3252 + ldr r2, [r3, #472] + ldr r3, .L3252 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3252 + strb r3, [r2, #109] + ldr r3, .L3252 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3252 + str r2, [r3, #60] + ldr r3, .L3252 + ldr r2, [r3, #96] + ldr r3, .L3252 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3252 + str r2, [r3, #96] + ldr r3, .L3252 + ldr r2, [r3, #472] + ldr r3, .L3252 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3252 + strb r3, [r2, #109] + ldr r3, .L3252 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3252 + str r2, [r3, #60] + ldr r3, .L3252 + ldr r2, [r3, #464] + ldr r3, .L3252 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3252 + str r2, [r3, #52] + ldr r3, .L3252 + ldr r1, [r3, #52] + ldr r3, .L3252 + ldr r2, [r3, #464] + ldr r3, .L3252 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3252 + str r2, [r3, #52] + ldr r3, .L3252 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3252 + str r2, [r3, #72] + ldr r2, .L3252 + ldr r3, .L3252 + str r3, [r2, #104] + ldr r3, .L3252 + ldr r2, [r3, #104] + ldr r3, .L3252 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3253: + .align 2 +.L3252: + .word GSU + .size _Z9fx_lm_r13v, .-_Z9fx_lm_r13v + .align 2 + .type _Z9fx_lm_r14v, %function +_Z9fx_lm_r14v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3256 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3256 + str r2, [r3, #96] + ldr r3, .L3256 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3256 + str r2, [r3, #60] + ldr r3, .L3256 + ldr r2, [r3, #472] + ldr r3, .L3256 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3256 + strb r3, [r2, #109] + ldr r3, .L3256 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3256 + str r2, [r3, #60] + ldr r3, .L3256 + ldr r2, [r3, #96] + ldr r3, .L3256 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3256 + str r2, [r3, #96] + ldr r3, .L3256 + ldr r2, [r3, #472] + ldr r3, .L3256 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3256 + strb r3, [r2, #109] + ldr r3, .L3256 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3256 + str r2, [r3, #60] + ldr r3, .L3256 + ldr r2, [r3, #464] + ldr r3, .L3256 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3256 + str r2, [r3, #56] + ldr r3, .L3256 + ldr r1, [r3, #56] + ldr r3, .L3256 + ldr r2, [r3, #464] + ldr r3, .L3256 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3256 + str r2, [r3, #56] + ldr r3, .L3256 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3256 + str r2, [r3, #72] + ldr r2, .L3256 + ldr r3, .L3256 + str r3, [r2, #104] + ldr r3, .L3256 + ldr r2, [r3, #104] + ldr r3, .L3256 + str r2, [r3, #100] + ldr r3, .L3256 + ldr r2, [r3, #468] + ldr r3, .L3256 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3256 + strb r3, [r2, #108] + ldmfd sp, {fp, sp, pc} +.L3257: + .align 2 +.L3256: + .word GSU + .size _Z9fx_lm_r14v, .-_Z9fx_lm_r14v + .align 2 + .type _Z9fx_lm_r15v, %function +_Z9fx_lm_r15v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3260 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3260 + str r2, [r3, #96] + ldr r3, .L3260 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3260 + str r2, [r3, #60] + ldr r3, .L3260 + ldr r2, [r3, #472] + ldr r3, .L3260 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3260 + strb r3, [r2, #109] + ldr r3, .L3260 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3260 + str r2, [r3, #60] + ldr r3, .L3260 + ldr r2, [r3, #96] + ldr r3, .L3260 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3260 + str r2, [r3, #96] + ldr r3, .L3260 + ldr r2, [r3, #472] + ldr r3, .L3260 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3260 + strb r3, [r2, #109] + ldr r3, .L3260 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3260 + str r2, [r3, #60] + ldr r3, .L3260 + ldr r2, [r3, #464] + ldr r3, .L3260 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3260 + str r2, [r3, #60] + ldr r3, .L3260 + ldr r1, [r3, #60] + ldr r3, .L3260 + ldr r2, [r3, #464] + ldr r3, .L3260 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r1, r3 + ldr r3, .L3260 + str r2, [r3, #60] + ldr r3, .L3260 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3260 + str r2, [r3, #72] + ldr r2, .L3260 + ldr r3, .L3260 + str r3, [r2, #104] + ldr r3, .L3260 + ldr r2, [r3, #104] + ldr r3, .L3260 + str r2, [r3, #100] + ldmfd sp, {fp, sp, pc} +.L3261: + .align 2 +.L3260: + .word GSU + .size _Z9fx_lm_r15v, .-_Z9fx_lm_r15v + .align 2 + .type _Z8fx_sm_r0v, %function +_Z8fx_sm_r0v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3264 + ldr r3, [r3, #0] + str r3, [fp, #-16] + ldr r3, .L3264 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3264 + str r2, [r3, #96] + ldr r3, .L3264 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3264 + str r2, [r3, #60] + ldr r3, .L3264 + ldr r2, [r3, #472] + ldr r3, .L3264 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3264 + strb r3, [r2, #109] + ldr r3, .L3264 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3264 + str r2, [r3, #60] + ldr r3, .L3264 + ldr r2, [r3, #96] + ldr r3, .L3264 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3264 + str r2, [r3, #96] + ldr r3, .L3264 + ldr r2, [r3, #472] + ldr r3, .L3264 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3264 + strb r3, [r2, #109] + ldr r3, .L3264 + ldr r2, [r3, #464] + ldr r3, .L3264 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3264 + ldr r2, [r3, #464] + ldr r3, .L3264 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3264 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3264 + str r2, [r3, #72] + ldr r2, .L3264 + ldr r3, .L3264 + str r3, [r2, #104] + ldr r3, .L3264 + ldr r2, [r3, #104] + ldr r3, .L3264 + str r2, [r3, #100] + ldr r3, .L3264 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3264 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3265: + .align 2 +.L3264: + .word GSU + .size _Z8fx_sm_r0v, .-_Z8fx_sm_r0v + .align 2 + .type _Z8fx_sm_r1v, %function +_Z8fx_sm_r1v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3268 + ldr r3, [r3, #4] + str r3, [fp, #-16] + ldr r3, .L3268 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3268 + str r2, [r3, #96] + ldr r3, .L3268 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3268 + str r2, [r3, #60] + ldr r3, .L3268 + ldr r2, [r3, #472] + ldr r3, .L3268 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3268 + strb r3, [r2, #109] + ldr r3, .L3268 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3268 + str r2, [r3, #60] + ldr r3, .L3268 + ldr r2, [r3, #96] + ldr r3, .L3268 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3268 + str r2, [r3, #96] + ldr r3, .L3268 + ldr r2, [r3, #472] + ldr r3, .L3268 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3268 + strb r3, [r2, #109] + ldr r3, .L3268 + ldr r2, [r3, #464] + ldr r3, .L3268 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3268 + ldr r2, [r3, #464] + ldr r3, .L3268 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3268 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3268 + str r2, [r3, #72] + ldr r2, .L3268 + ldr r3, .L3268 + str r3, [r2, #104] + ldr r3, .L3268 + ldr r2, [r3, #104] + ldr r3, .L3268 + str r2, [r3, #100] + ldr r3, .L3268 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3268 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3269: + .align 2 +.L3268: + .word GSU + .size _Z8fx_sm_r1v, .-_Z8fx_sm_r1v + .align 2 + .type _Z8fx_sm_r2v, %function +_Z8fx_sm_r2v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3272 + ldr r3, [r3, #8] + str r3, [fp, #-16] + ldr r3, .L3272 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3272 + str r2, [r3, #96] + ldr r3, .L3272 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3272 + str r2, [r3, #60] + ldr r3, .L3272 + ldr r2, [r3, #472] + ldr r3, .L3272 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3272 + strb r3, [r2, #109] + ldr r3, .L3272 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3272 + str r2, [r3, #60] + ldr r3, .L3272 + ldr r2, [r3, #96] + ldr r3, .L3272 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3272 + str r2, [r3, #96] + ldr r3, .L3272 + ldr r2, [r3, #472] + ldr r3, .L3272 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3272 + strb r3, [r2, #109] + ldr r3, .L3272 + ldr r2, [r3, #464] + ldr r3, .L3272 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3272 + ldr r2, [r3, #464] + ldr r3, .L3272 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3272 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3272 + str r2, [r3, #72] + ldr r2, .L3272 + ldr r3, .L3272 + str r3, [r2, #104] + ldr r3, .L3272 + ldr r2, [r3, #104] + ldr r3, .L3272 + str r2, [r3, #100] + ldr r3, .L3272 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3272 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3273: + .align 2 +.L3272: + .word GSU + .size _Z8fx_sm_r2v, .-_Z8fx_sm_r2v + .align 2 + .type _Z8fx_sm_r3v, %function +_Z8fx_sm_r3v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3276 + ldr r3, [r3, #12] + str r3, [fp, #-16] + ldr r3, .L3276 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3276 + str r2, [r3, #96] + ldr r3, .L3276 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3276 + str r2, [r3, #60] + ldr r3, .L3276 + ldr r2, [r3, #472] + ldr r3, .L3276 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3276 + strb r3, [r2, #109] + ldr r3, .L3276 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3276 + str r2, [r3, #60] + ldr r3, .L3276 + ldr r2, [r3, #96] + ldr r3, .L3276 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3276 + str r2, [r3, #96] + ldr r3, .L3276 + ldr r2, [r3, #472] + ldr r3, .L3276 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3276 + strb r3, [r2, #109] + ldr r3, .L3276 + ldr r2, [r3, #464] + ldr r3, .L3276 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3276 + ldr r2, [r3, #464] + ldr r3, .L3276 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3276 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3276 + str r2, [r3, #72] + ldr r2, .L3276 + ldr r3, .L3276 + str r3, [r2, #104] + ldr r3, .L3276 + ldr r2, [r3, #104] + ldr r3, .L3276 + str r2, [r3, #100] + ldr r3, .L3276 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3276 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3277: + .align 2 +.L3276: + .word GSU + .size _Z8fx_sm_r3v, .-_Z8fx_sm_r3v + .align 2 + .type _Z8fx_sm_r4v, %function +_Z8fx_sm_r4v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3280 + ldr r3, [r3, #16] + str r3, [fp, #-16] + ldr r3, .L3280 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3280 + str r2, [r3, #96] + ldr r3, .L3280 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3280 + str r2, [r3, #60] + ldr r3, .L3280 + ldr r2, [r3, #472] + ldr r3, .L3280 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3280 + strb r3, [r2, #109] + ldr r3, .L3280 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3280 + str r2, [r3, #60] + ldr r3, .L3280 + ldr r2, [r3, #96] + ldr r3, .L3280 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3280 + str r2, [r3, #96] + ldr r3, .L3280 + ldr r2, [r3, #472] + ldr r3, .L3280 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3280 + strb r3, [r2, #109] + ldr r3, .L3280 + ldr r2, [r3, #464] + ldr r3, .L3280 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3280 + ldr r2, [r3, #464] + ldr r3, .L3280 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3280 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3280 + str r2, [r3, #72] + ldr r2, .L3280 + ldr r3, .L3280 + str r3, [r2, #104] + ldr r3, .L3280 + ldr r2, [r3, #104] + ldr r3, .L3280 + str r2, [r3, #100] + ldr r3, .L3280 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3280 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3281: + .align 2 +.L3280: + .word GSU + .size _Z8fx_sm_r4v, .-_Z8fx_sm_r4v + .align 2 + .type _Z8fx_sm_r5v, %function +_Z8fx_sm_r5v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3284 + ldr r3, [r3, #20] + str r3, [fp, #-16] + ldr r3, .L3284 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3284 + str r2, [r3, #96] + ldr r3, .L3284 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3284 + str r2, [r3, #60] + ldr r3, .L3284 + ldr r2, [r3, #472] + ldr r3, .L3284 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3284 + strb r3, [r2, #109] + ldr r3, .L3284 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3284 + str r2, [r3, #60] + ldr r3, .L3284 + ldr r2, [r3, #96] + ldr r3, .L3284 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3284 + str r2, [r3, #96] + ldr r3, .L3284 + ldr r2, [r3, #472] + ldr r3, .L3284 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3284 + strb r3, [r2, #109] + ldr r3, .L3284 + ldr r2, [r3, #464] + ldr r3, .L3284 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3284 + ldr r2, [r3, #464] + ldr r3, .L3284 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3284 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3284 + str r2, [r3, #72] + ldr r2, .L3284 + ldr r3, .L3284 + str r3, [r2, #104] + ldr r3, .L3284 + ldr r2, [r3, #104] + ldr r3, .L3284 + str r2, [r3, #100] + ldr r3, .L3284 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3284 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3285: + .align 2 +.L3284: + .word GSU + .size _Z8fx_sm_r5v, .-_Z8fx_sm_r5v + .align 2 + .type _Z8fx_sm_r6v, %function +_Z8fx_sm_r6v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3288 + ldr r3, [r3, #24] + str r3, [fp, #-16] + ldr r3, .L3288 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3288 + str r2, [r3, #96] + ldr r3, .L3288 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3288 + str r2, [r3, #60] + ldr r3, .L3288 + ldr r2, [r3, #472] + ldr r3, .L3288 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3288 + strb r3, [r2, #109] + ldr r3, .L3288 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3288 + str r2, [r3, #60] + ldr r3, .L3288 + ldr r2, [r3, #96] + ldr r3, .L3288 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3288 + str r2, [r3, #96] + ldr r3, .L3288 + ldr r2, [r3, #472] + ldr r3, .L3288 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3288 + strb r3, [r2, #109] + ldr r3, .L3288 + ldr r2, [r3, #464] + ldr r3, .L3288 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3288 + ldr r2, [r3, #464] + ldr r3, .L3288 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3288 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3288 + str r2, [r3, #72] + ldr r2, .L3288 + ldr r3, .L3288 + str r3, [r2, #104] + ldr r3, .L3288 + ldr r2, [r3, #104] + ldr r3, .L3288 + str r2, [r3, #100] + ldr r3, .L3288 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3288 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3289: + .align 2 +.L3288: + .word GSU + .size _Z8fx_sm_r6v, .-_Z8fx_sm_r6v + .align 2 + .type _Z8fx_sm_r7v, %function +_Z8fx_sm_r7v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3292 + ldr r3, [r3, #28] + str r3, [fp, #-16] + ldr r3, .L3292 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3292 + str r2, [r3, #96] + ldr r3, .L3292 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3292 + str r2, [r3, #60] + ldr r3, .L3292 + ldr r2, [r3, #472] + ldr r3, .L3292 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3292 + strb r3, [r2, #109] + ldr r3, .L3292 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3292 + str r2, [r3, #60] + ldr r3, .L3292 + ldr r2, [r3, #96] + ldr r3, .L3292 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3292 + str r2, [r3, #96] + ldr r3, .L3292 + ldr r2, [r3, #472] + ldr r3, .L3292 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3292 + strb r3, [r2, #109] + ldr r3, .L3292 + ldr r2, [r3, #464] + ldr r3, .L3292 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3292 + ldr r2, [r3, #464] + ldr r3, .L3292 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3292 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3292 + str r2, [r3, #72] + ldr r2, .L3292 + ldr r3, .L3292 + str r3, [r2, #104] + ldr r3, .L3292 + ldr r2, [r3, #104] + ldr r3, .L3292 + str r2, [r3, #100] + ldr r3, .L3292 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3292 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3293: + .align 2 +.L3292: + .word GSU + .size _Z8fx_sm_r7v, .-_Z8fx_sm_r7v + .align 2 + .type _Z8fx_sm_r8v, %function +_Z8fx_sm_r8v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3296 + ldr r3, [r3, #32] + str r3, [fp, #-16] + ldr r3, .L3296 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3296 + str r2, [r3, #96] + ldr r3, .L3296 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3296 + str r2, [r3, #60] + ldr r3, .L3296 + ldr r2, [r3, #472] + ldr r3, .L3296 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3296 + strb r3, [r2, #109] + ldr r3, .L3296 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3296 + str r2, [r3, #60] + ldr r3, .L3296 + ldr r2, [r3, #96] + ldr r3, .L3296 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3296 + str r2, [r3, #96] + ldr r3, .L3296 + ldr r2, [r3, #472] + ldr r3, .L3296 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3296 + strb r3, [r2, #109] + ldr r3, .L3296 + ldr r2, [r3, #464] + ldr r3, .L3296 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3296 + ldr r2, [r3, #464] + ldr r3, .L3296 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3296 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3296 + str r2, [r3, #72] + ldr r2, .L3296 + ldr r3, .L3296 + str r3, [r2, #104] + ldr r3, .L3296 + ldr r2, [r3, #104] + ldr r3, .L3296 + str r2, [r3, #100] + ldr r3, .L3296 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3296 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3297: + .align 2 +.L3296: + .word GSU + .size _Z8fx_sm_r8v, .-_Z8fx_sm_r8v + .align 2 + .type _Z8fx_sm_r9v, %function +_Z8fx_sm_r9v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3300 + ldr r3, [r3, #36] + str r3, [fp, #-16] + ldr r3, .L3300 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3300 + str r2, [r3, #96] + ldr r3, .L3300 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3300 + str r2, [r3, #60] + ldr r3, .L3300 + ldr r2, [r3, #472] + ldr r3, .L3300 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3300 + strb r3, [r2, #109] + ldr r3, .L3300 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3300 + str r2, [r3, #60] + ldr r3, .L3300 + ldr r2, [r3, #96] + ldr r3, .L3300 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3300 + str r2, [r3, #96] + ldr r3, .L3300 + ldr r2, [r3, #472] + ldr r3, .L3300 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3300 + strb r3, [r2, #109] + ldr r3, .L3300 + ldr r2, [r3, #464] + ldr r3, .L3300 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3300 + ldr r2, [r3, #464] + ldr r3, .L3300 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3300 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3300 + str r2, [r3, #72] + ldr r2, .L3300 + ldr r3, .L3300 + str r3, [r2, #104] + ldr r3, .L3300 + ldr r2, [r3, #104] + ldr r3, .L3300 + str r2, [r3, #100] + ldr r3, .L3300 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3300 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3301: + .align 2 +.L3300: + .word GSU + .size _Z8fx_sm_r9v, .-_Z8fx_sm_r9v + .align 2 + .type _Z9fx_sm_r10v, %function +_Z9fx_sm_r10v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3304 + ldr r3, [r3, #40] + str r3, [fp, #-16] + ldr r3, .L3304 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3304 + str r2, [r3, #96] + ldr r3, .L3304 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3304 + str r2, [r3, #60] + ldr r3, .L3304 + ldr r2, [r3, #472] + ldr r3, .L3304 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3304 + strb r3, [r2, #109] + ldr r3, .L3304 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3304 + str r2, [r3, #60] + ldr r3, .L3304 + ldr r2, [r3, #96] + ldr r3, .L3304 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3304 + str r2, [r3, #96] + ldr r3, .L3304 + ldr r2, [r3, #472] + ldr r3, .L3304 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3304 + strb r3, [r2, #109] + ldr r3, .L3304 + ldr r2, [r3, #464] + ldr r3, .L3304 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3304 + ldr r2, [r3, #464] + ldr r3, .L3304 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3304 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3304 + str r2, [r3, #72] + ldr r2, .L3304 + ldr r3, .L3304 + str r3, [r2, #104] + ldr r3, .L3304 + ldr r2, [r3, #104] + ldr r3, .L3304 + str r2, [r3, #100] + ldr r3, .L3304 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3304 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3305: + .align 2 +.L3304: + .word GSU + .size _Z9fx_sm_r10v, .-_Z9fx_sm_r10v + .align 2 + .type _Z9fx_sm_r11v, %function +_Z9fx_sm_r11v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3308 + ldr r3, [r3, #44] + str r3, [fp, #-16] + ldr r3, .L3308 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3308 + str r2, [r3, #96] + ldr r3, .L3308 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3308 + str r2, [r3, #60] + ldr r3, .L3308 + ldr r2, [r3, #472] + ldr r3, .L3308 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3308 + strb r3, [r2, #109] + ldr r3, .L3308 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3308 + str r2, [r3, #60] + ldr r3, .L3308 + ldr r2, [r3, #96] + ldr r3, .L3308 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3308 + str r2, [r3, #96] + ldr r3, .L3308 + ldr r2, [r3, #472] + ldr r3, .L3308 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3308 + strb r3, [r2, #109] + ldr r3, .L3308 + ldr r2, [r3, #464] + ldr r3, .L3308 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3308 + ldr r2, [r3, #464] + ldr r3, .L3308 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3308 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3308 + str r2, [r3, #72] + ldr r2, .L3308 + ldr r3, .L3308 + str r3, [r2, #104] + ldr r3, .L3308 + ldr r2, [r3, #104] + ldr r3, .L3308 + str r2, [r3, #100] + ldr r3, .L3308 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3308 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3309: + .align 2 +.L3308: + .word GSU + .size _Z9fx_sm_r11v, .-_Z9fx_sm_r11v + .align 2 + .type _Z9fx_sm_r12v, %function +_Z9fx_sm_r12v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3312 + ldr r3, [r3, #48] + str r3, [fp, #-16] + ldr r3, .L3312 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3312 + str r2, [r3, #96] + ldr r3, .L3312 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3312 + str r2, [r3, #60] + ldr r3, .L3312 + ldr r2, [r3, #472] + ldr r3, .L3312 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3312 + strb r3, [r2, #109] + ldr r3, .L3312 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3312 + str r2, [r3, #60] + ldr r3, .L3312 + ldr r2, [r3, #96] + ldr r3, .L3312 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3312 + str r2, [r3, #96] + ldr r3, .L3312 + ldr r2, [r3, #472] + ldr r3, .L3312 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3312 + strb r3, [r2, #109] + ldr r3, .L3312 + ldr r2, [r3, #464] + ldr r3, .L3312 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3312 + ldr r2, [r3, #464] + ldr r3, .L3312 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3312 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3312 + str r2, [r3, #72] + ldr r2, .L3312 + ldr r3, .L3312 + str r3, [r2, #104] + ldr r3, .L3312 + ldr r2, [r3, #104] + ldr r3, .L3312 + str r2, [r3, #100] + ldr r3, .L3312 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3312 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3313: + .align 2 +.L3312: + .word GSU + .size _Z9fx_sm_r12v, .-_Z9fx_sm_r12v + .align 2 + .type _Z9fx_sm_r13v, %function +_Z9fx_sm_r13v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3316 + ldr r3, [r3, #52] + str r3, [fp, #-16] + ldr r3, .L3316 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3316 + str r2, [r3, #96] + ldr r3, .L3316 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3316 + str r2, [r3, #60] + ldr r3, .L3316 + ldr r2, [r3, #472] + ldr r3, .L3316 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3316 + strb r3, [r2, #109] + ldr r3, .L3316 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3316 + str r2, [r3, #60] + ldr r3, .L3316 + ldr r2, [r3, #96] + ldr r3, .L3316 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3316 + str r2, [r3, #96] + ldr r3, .L3316 + ldr r2, [r3, #472] + ldr r3, .L3316 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3316 + strb r3, [r2, #109] + ldr r3, .L3316 + ldr r2, [r3, #464] + ldr r3, .L3316 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3316 + ldr r2, [r3, #464] + ldr r3, .L3316 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3316 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3316 + str r2, [r3, #72] + ldr r2, .L3316 + ldr r3, .L3316 + str r3, [r2, #104] + ldr r3, .L3316 + ldr r2, [r3, #104] + ldr r3, .L3316 + str r2, [r3, #100] + ldr r3, .L3316 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3316 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3317: + .align 2 +.L3316: + .word GSU + .size _Z9fx_sm_r13v, .-_Z9fx_sm_r13v + .align 2 + .type _Z9fx_sm_r14v, %function +_Z9fx_sm_r14v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3320 + ldr r3, [r3, #56] + str r3, [fp, #-16] + ldr r3, .L3320 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3320 + str r2, [r3, #96] + ldr r3, .L3320 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3320 + str r2, [r3, #60] + ldr r3, .L3320 + ldr r2, [r3, #472] + ldr r3, .L3320 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3320 + strb r3, [r2, #109] + ldr r3, .L3320 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3320 + str r2, [r3, #60] + ldr r3, .L3320 + ldr r2, [r3, #96] + ldr r3, .L3320 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3320 + str r2, [r3, #96] + ldr r3, .L3320 + ldr r2, [r3, #472] + ldr r3, .L3320 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3320 + strb r3, [r2, #109] + ldr r3, .L3320 + ldr r2, [r3, #464] + ldr r3, .L3320 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3320 + ldr r2, [r3, #464] + ldr r3, .L3320 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3320 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3320 + str r2, [r3, #72] + ldr r2, .L3320 + ldr r3, .L3320 + str r3, [r2, #104] + ldr r3, .L3320 + ldr r2, [r3, #104] + ldr r3, .L3320 + str r2, [r3, #100] + ldr r3, .L3320 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3320 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3321: + .align 2 +.L3320: + .word GSU + .size _Z9fx_sm_r14v, .-_Z9fx_sm_r14v + .align 2 + .type _Z9fx_sm_r15v, %function +_Z9fx_sm_r15v: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3324 + ldr r3, [r3, #60] + str r3, [fp, #-16] + ldr r3, .L3324 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r2, r3 + ldr r3, .L3324 + str r2, [r3, #96] + ldr r3, .L3324 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3324 + str r2, [r3, #60] + ldr r3, .L3324 + ldr r2, [r3, #472] + ldr r3, .L3324 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3324 + strb r3, [r2, #109] + ldr r3, .L3324 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3324 + str r2, [r3, #60] + ldr r3, .L3324 + ldr r2, [r3, #96] + ldr r3, .L3324 + ldrb r3, [r3, #109] @ zero_extendqisi2 + mov r3, r3, asl #8 + orr r2, r2, r3 + ldr r3, .L3324 + str r2, [r3, #96] + ldr r3, .L3324 + ldr r2, [r3, #472] + ldr r3, .L3324 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3324 + strb r3, [r2, #109] + ldr r3, .L3324 + ldr r2, [r3, #464] + ldr r3, .L3324 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3324 + ldr r2, [r3, #464] + ldr r3, .L3324 + ldr r3, [r3, #96] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + eor r3, r3, #1 + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r2, r2, r3 + ldr r3, [fp, #-16] + mov r3, r3, lsr #8 + and r3, r3, #255 + strb r3, [r2, #0] + ldr r3, .L3324 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3324 + str r2, [r3, #72] + ldr r2, .L3324 + ldr r3, .L3324 + str r3, [r2, #104] + ldr r3, .L3324 + ldr r2, [r3, #104] + ldr r3, .L3324 + str r2, [r3, #100] + ldr r3, .L3324 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3324 + str r2, [r3, #60] + ldmib sp, {fp, sp, pc} +.L3325: + .align 2 +.L3324: + .word GSU + .size _Z9fx_sm_r15v, .-_Z9fx_sm_r15v + .align 2 + .type _Z6fx_runj, %function +_Z6fx_runj: + @ args = 0, pretend = 0, frame = 12 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #12 + str r0, [fp, #-20] + ldr r2, .L3335 + ldr r3, [fp, #-20] + str r3, [r2, #2036] + ldr r3, .L3335 + ldr r2, [r3, #468] + ldr r3, .L3335 + ldr r3, [r3, #56] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3335 + strb r3, [r2, #108] + b .L3327 +.L3328: + ldr r3, .L3335 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3335 + ldr r2, [r3, #472] + ldr r3, .L3335 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3335 + strb r3, [r2, #109] + ldr r3, .L3335 + ldr r3, [r3, #72] + and r2, r3, #768 + ldr r3, [fp, #-16] + orr r3, r2, r3 + mov r3, r3, asl #2 + mov r2, r3 + ldr r3, .L3335+4 + ldr r3, [r3, #0] + add r3, r2, r3 + ldr r3, [r3, #0] + blx r3 +.L3327: + ldr r3, .L3335 + ldr r3, [r3, #72] + and r3, r3, #32 + cmp r3, #0 + beq .L3329 + ldr r3, .L3335 + ldr r3, [r3, #2036] + sub r2, r3, #1 + ldr r3, .L3335 + str r2, [r3, #2036] + ldr r3, .L3335 + ldr r3, [r3, #2036] + cmn r3, #1 + beq .L3329 + mov r3, #1 + str r3, [fp, #-24] + b .L3332 +.L3329: + mov r3, #0 + str r3, [fp, #-24] +.L3332: + ldr r3, [fp, #-24] + cmp r3, #0 + bne .L3328 + ldr r3, .L3335 + ldr r2, [r3, #2040] + ldr r3, [fp, #-20] + rsb r3, r2, r3 + mov r0, r3 + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L3336: + .align 2 +.L3335: + .word GSU + .word fx_ppfOpcodeTable + .size _Z6fx_runj, .-_Z6fx_runj + .align 2 + .type _Z20fx_run_to_breakpointj, %function +_Z20fx_run_to_breakpointj: + @ args = 0, pretend = 0, frame = 12 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #12 + str r0, [fp, #-24] + mov r3, #0 + str r3, [fp, #-20] + b .L3338 +.L3339: + ldr r3, [fp, #-20] + add r3, r3, #1 + str r3, [fp, #-20] + ldr r3, .L3344 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3344 + ldr r2, [r3, #472] + ldr r3, .L3344 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3344 + strb r3, [r2, #109] + ldr r3, .L3344 + ldr r3, [r3, #72] + and r2, r3, #768 + ldr r3, [fp, #-16] + orr r3, r2, r3 + mov r3, r3, asl #2 + mov r2, r3 + ldr r3, .L3344+4 + ldr r3, [r3, #0] + add r3, r2, r3 + ldr r3, [r3, #0] + blx r3 + ldr r3, .L3344 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L3344 + ldr r3, [r3, #144] + cmp r2, r3 + bne .L3338 + ldr r2, .L3344 + mvn r3, #0 + str r3, [r2, #132] + b .L3341 +.L3338: + ldr r3, .L3344 + ldr r3, [r3, #72] + and r3, r3, #32 + cmp r3, #0 + beq .L3341 + ldr r2, [fp, #-20] + ldr r3, [fp, #-24] + cmp r2, r3 + bcc .L3339 +.L3341: + ldr r3, [fp, #-20] + mov r0, r3 + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L3345: + .align 2 +.L3344: + .word GSU + .word fx_ppfOpcodeTable + .size _Z20fx_run_to_breakpointj, .-_Z20fx_run_to_breakpointj + .align 2 + .type _Z12fx_step_overj, %function +_Z12fx_step_overj: + @ args = 0, pretend = 0, frame = 12 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #12 + str r0, [fp, #-24] + mov r3, #0 + str r3, [fp, #-20] + b .L3347 +.L3348: + ldr r3, [fp, #-20] + add r3, r3, #1 + str r3, [fp, #-20] + ldr r3, .L3354 + ldrb r3, [r3, #109] @ zero_extendqisi2 + str r3, [fp, #-16] + ldr r3, .L3354 + ldr r2, [r3, #472] + ldr r3, .L3354 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + add r3, r2, r3 + ldrb r3, [r3, #0] @ zero_extendqisi2 + ldr r2, .L3354 + strb r3, [r2, #109] + ldr r3, .L3354 + ldr r3, [r3, #72] + and r2, r3, #768 + ldr r3, [fp, #-16] + orr r3, r2, r3 + mov r3, r3, asl #2 + mov r2, r3 + ldr r3, .L3354+4 + ldr r3, [r3, #0] + add r3, r2, r3 + ldr r3, [r3, #0] + blx r3 + ldr r3, .L3354 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L3354 + ldr r3, [r3, #144] + cmp r2, r3 + bne .L3349 + ldr r2, .L3354 + mvn r3, #0 + str r3, [r2, #132] + b .L3351 +.L3349: + ldr r3, .L3354 + ldr r3, [r3, #60] + mov r3, r3, asl #16 + mov r3, r3, lsr #16 + mov r2, r3 + ldr r3, .L3354 + ldr r3, [r3, #148] + cmp r2, r3 + beq .L3351 +.L3347: + ldr r3, .L3354 + ldr r3, [r3, #72] + and r3, r3, #32 + cmp r3, #0 + beq .L3351 + ldr r2, [fp, #-20] + ldr r3, [fp, #-24] + cmp r2, r3 + bcc .L3348 +.L3351: + ldr r3, [fp, #-20] + mov r0, r3 + sub sp, fp, #12 + ldmfd sp, {fp, sp, pc} +.L3355: + .align 2 +.L3354: + .word GSU + .word fx_ppfOpcodeTable + .size _Z12fx_step_overj, .-_Z12fx_step_overj + .align 2 + .type _Z8fx_cmodev, %function +_Z8fx_cmodev: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3361 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L3361 + str r2, [r3, #68] + ldr r3, .L3361 + ldr r3, [r3, #68] + and r3, r3, #16 + cmp r3, #0 + beq .L3357 + ldr r2, .L3361 + mov r3, #256 + str r3, [r2, #440] + b .L3359 +.L3357: + ldr r3, .L3361 + ldr r2, [r3, #444] + ldr r3, .L3361 + str r2, [r3, #440] +.L3359: + bl _Z24fx_computeScreenPointersv + ldr r3, .L3361 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3361 + str r2, [r3, #72] + ldr r2, .L3361 + ldr r3, .L3361 + str r3, [r2, #104] + ldr r3, .L3361 + ldr r2, [r3, #104] + ldr r3, .L3361 + str r2, [r3, #100] + ldr r3, .L3361 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3361 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3362: + .align 2 +.L3361: + .word GSU + .size _Z8fx_cmodev, .-_Z8fx_cmodev + .align 2 + .type _Z8fx_cachev, %function +_Z8fx_cachev: + @ args = 0, pretend = 0, frame = 4 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + sub sp, sp, #4 + ldr r3, .L3368 + ldr r2, [r3, #60] + ldr r3, .L3368+4 + and r3, r2, r3 + str r3, [fp, #-16] + ldr r3, .L3368 + ldr r2, [r3, #88] + ldr r3, [fp, #-16] + cmp r2, r3 + bne .L3364 + ldr r3, .L3368 + ldrb r3, [r3, #1516] @ zero_extendqisi2 + cmp r3, #0 + bne .L3366 +.L3364: + bl _Z13fx_flushCachev + ldr r2, .L3368 + ldr r3, [fp, #-16] + str r3, [r2, #88] + ldr r2, .L3368 + mov r3, #1 + strb r3, [r2, #1516] +.L3366: + ldr r3, .L3368 + ldr r3, [r3, #60] + add r2, r3, #1 + ldr r3, .L3368 + str r2, [r3, #60] + ldr r3, .L3368 + ldr r3, [r3, #72] + bic r2, r3, #4864 + ldr r3, .L3368 + str r2, [r3, #72] + ldr r2, .L3368 + ldr r3, .L3368 + str r3, [r2, #104] + ldr r3, .L3368 + ldr r2, [r3, #104] + ldr r3, .L3368 + str r2, [r3, #100] + ldmib sp, {fp, sp, pc} +.L3369: + .align 2 +.L3368: + .word GSU + .word 65520 + .size _Z8fx_cachev, .-_Z8fx_cachev + .align 2 + .type _Z11fx_ljmp_r13v, %function +_Z11fx_ljmp_r13v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3372 + ldr r3, [r3, #52] + and r2, r3, #127 + ldr r3, .L3372 + str r2, [r3, #76] + ldr r3, .L3372 + ldr r3, [r3, #76] + ldr r2, .L3372 + mov r1, #492 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r2, [r3, #0] + ldr r3, .L3372 + str r2, [r3, #472] + ldr r3, .L3372 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L3372 + str r2, [r3, #60] + ldr r2, .L3372 + mov r3, #0 + strb r3, [r2, #1516] + bl _Z8fx_cachev + ldr r3, .L3372 + ldr r3, [r3, #60] + sub r2, r3, #1 + ldr r3, .L3372 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3373: + .align 2 +.L3372: + .word GSU + .size _Z11fx_ljmp_r13v, .-_Z11fx_ljmp_r13v + .align 2 + .type _Z11fx_ljmp_r12v, %function +_Z11fx_ljmp_r12v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3376 + ldr r3, [r3, #48] + and r2, r3, #127 + ldr r3, .L3376 + str r2, [r3, #76] + ldr r3, .L3376 + ldr r3, [r3, #76] + ldr r2, .L3376 + mov r1, #492 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r2, [r3, #0] + ldr r3, .L3376 + str r2, [r3, #472] + ldr r3, .L3376 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L3376 + str r2, [r3, #60] + ldr r2, .L3376 + mov r3, #0 + strb r3, [r2, #1516] + bl _Z8fx_cachev + ldr r3, .L3376 + ldr r3, [r3, #60] + sub r2, r3, #1 + ldr r3, .L3376 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3377: + .align 2 +.L3376: + .word GSU + .size _Z11fx_ljmp_r12v, .-_Z11fx_ljmp_r12v + .align 2 + .type _Z11fx_ljmp_r11v, %function +_Z11fx_ljmp_r11v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3380 + ldr r3, [r3, #44] + and r2, r3, #127 + ldr r3, .L3380 + str r2, [r3, #76] + ldr r3, .L3380 + ldr r3, [r3, #76] + ldr r2, .L3380 + mov r1, #492 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r2, [r3, #0] + ldr r3, .L3380 + str r2, [r3, #472] + ldr r3, .L3380 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L3380 + str r2, [r3, #60] + ldr r2, .L3380 + mov r3, #0 + strb r3, [r2, #1516] + bl _Z8fx_cachev + ldr r3, .L3380 + ldr r3, [r3, #60] + sub r2, r3, #1 + ldr r3, .L3380 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3381: + .align 2 +.L3380: + .word GSU + .size _Z11fx_ljmp_r11v, .-_Z11fx_ljmp_r11v + .align 2 + .type _Z11fx_ljmp_r10v, %function +_Z11fx_ljmp_r10v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3384 + ldr r3, [r3, #40] + and r2, r3, #127 + ldr r3, .L3384 + str r2, [r3, #76] + ldr r3, .L3384 + ldr r3, [r3, #76] + ldr r2, .L3384 + mov r1, #492 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r2, [r3, #0] + ldr r3, .L3384 + str r2, [r3, #472] + ldr r3, .L3384 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L3384 + str r2, [r3, #60] + ldr r2, .L3384 + mov r3, #0 + strb r3, [r2, #1516] + bl _Z8fx_cachev + ldr r3, .L3384 + ldr r3, [r3, #60] + sub r2, r3, #1 + ldr r3, .L3384 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3385: + .align 2 +.L3384: + .word GSU + .size _Z11fx_ljmp_r10v, .-_Z11fx_ljmp_r10v + .align 2 + .type _Z10fx_ljmp_r9v, %function +_Z10fx_ljmp_r9v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3388 + ldr r3, [r3, #36] + and r2, r3, #127 + ldr r3, .L3388 + str r2, [r3, #76] + ldr r3, .L3388 + ldr r3, [r3, #76] + ldr r2, .L3388 + mov r1, #492 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r2, [r3, #0] + ldr r3, .L3388 + str r2, [r3, #472] + ldr r3, .L3388 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L3388 + str r2, [r3, #60] + ldr r2, .L3388 + mov r3, #0 + strb r3, [r2, #1516] + bl _Z8fx_cachev + ldr r3, .L3388 + ldr r3, [r3, #60] + sub r2, r3, #1 + ldr r3, .L3388 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3389: + .align 2 +.L3388: + .word GSU + .size _Z10fx_ljmp_r9v, .-_Z10fx_ljmp_r9v + .align 2 + .type _Z10fx_ljmp_r8v, %function +_Z10fx_ljmp_r8v: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r3, .L3392 + ldr r3, [r3, #32] + and r2, r3, #127 + ldr r3, .L3392 + str r2, [r3, #76] + ldr r3, .L3392 + ldr r3, [r3, #76] + ldr r2, .L3392 + mov r1, #492 + mov r3, r3, asl #2 + add r3, r3, r2 + add r3, r3, r1 + ldr r2, [r3, #0] + ldr r3, .L3392 + str r2, [r3, #472] + ldr r3, .L3392 + ldr r3, [r3, #104] + ldr r2, [r3, #0] + ldr r3, .L3392 + str r2, [r3, #60] + ldr r2, .L3392 + mov r3, #0 + strb r3, [r2, #1516] + bl _Z8fx_cachev + ldr r3, .L3392 + ldr r3, [r3, #60] + sub r2, r3, #1 + ldr r3, .L3392 + str r2, [r3, #60] + ldmfd sp, {fp, sp, pc} +.L3393: + .align 2 +.L3392: + .word GSU + .size _Z10fx_ljmp_r8v, .-_Z10fx_ljmp_r8v + .section .rodata + .align 2 +.LC0: + .ascii "ERROR fx_rpix_obj called\000" + .text + .align 2 + .type _Z11fx_rpix_objv, %function +_Z11fx_rpix_objv: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r0, .L3396 + bl puts + ldmfd sp, {fp, sp, pc} +.L3397: + .align 2 +.L3396: + .word .LC0 + .size _Z11fx_rpix_objv, .-_Z11fx_rpix_objv + .section .rodata + .align 2 +.LC1: + .ascii "ERROR fx_plot_obj called\000" + .text + .align 2 + .type _Z11fx_plot_objv, %function +_Z11fx_plot_objv: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + ldr r0, .L3400 + bl puts + ldmfd sp, {fp, sp, pc} +.L3401: + .align 2 +.L3400: + .word .LC1 + .size _Z11fx_plot_objv, .-_Z11fx_plot_objv + .global gsu_bank + .bss + .align 2 + .type gsu_bank, %object + .size gsu_bank, 2048 +gsu_bank: + .space 2048 + .global fx_apfFunctionTable + .data + .align 2 + .type fx_apfFunctionTable, %object + .size fx_apfFunctionTable, 12 +fx_apfFunctionTable: + .word _Z6fx_runj + .word _Z20fx_run_to_breakpointj + .word _Z12fx_step_overj + .global fx_apfPlotTable + .align 2 + .type fx_apfPlotTable, %object + .size fx_apfPlotTable, 40 +fx_apfPlotTable: + .word _Z12fx_plot_2bitv + .word _Z12fx_plot_4bitv + .word _Z12fx_plot_4bitv + .word _Z12fx_plot_8bitv + .word _Z11fx_plot_objv + .word _Z12fx_rpix_2bitv + .word _Z12fx_rpix_4bitv + .word _Z12fx_rpix_4bitv + .word _Z12fx_rpix_8bitv + .word _Z11fx_rpix_objv + .global fx_apfOpcodeTable + .align 2 + .type fx_apfOpcodeTable, %object + .size fx_apfOpcodeTable, 4096 +fx_apfOpcodeTable: + .word _Z7fx_stopv + .word _Z6fx_nopv + .word _Z8fx_cachev + .word _Z6fx_lsrv + .word _Z6fx_rolv + .word _Z6fx_brav + .word _Z6fx_bgev + .word _Z6fx_bltv + .word _Z6fx_bnev + .word _Z6fx_beqv + .word _Z6fx_bplv + .word _Z6fx_bmiv + .word _Z6fx_bccv + .word _Z6fx_bcsv + .word _Z6fx_bvcv + .word _Z6fx_bvsv + .word _Z8fx_to_r0v + .word _Z8fx_to_r1v + .word _Z8fx_to_r2v + .word _Z8fx_to_r3v + .word _Z8fx_to_r4v + .word _Z8fx_to_r5v + .word _Z8fx_to_r6v + .word _Z8fx_to_r7v + .word _Z8fx_to_r8v + .word _Z8fx_to_r9v + .word _Z9fx_to_r10v + .word _Z9fx_to_r11v + .word _Z9fx_to_r12v + .word _Z9fx_to_r13v + .word _Z9fx_to_r14v + .word _Z9fx_to_r15v + .word _Z10fx_with_r0v + .word _Z10fx_with_r1v + .word _Z10fx_with_r2v + .word _Z10fx_with_r3v + .word _Z10fx_with_r4v + .word _Z10fx_with_r5v + .word _Z10fx_with_r6v + .word _Z10fx_with_r7v + .word _Z10fx_with_r8v + .word _Z10fx_with_r9v + .word _Z11fx_with_r10v + .word _Z11fx_with_r11v + .word _Z11fx_with_r12v + .word _Z11fx_with_r13v + .word _Z11fx_with_r14v + .word _Z11fx_with_r15v + .word _Z9fx_stw_r0v + .word _Z9fx_stw_r1v + .word _Z9fx_stw_r2v + .word _Z9fx_stw_r3v + .word _Z9fx_stw_r4v + .word _Z9fx_stw_r5v + .word _Z9fx_stw_r6v + .word _Z9fx_stw_r7v + .word _Z9fx_stw_r8v + .word _Z9fx_stw_r9v + .word _Z10fx_stw_r10v + .word _Z10fx_stw_r11v + .word _Z7fx_loopv + .word _Z7fx_alt1v + .word _Z7fx_alt2v + .word _Z7fx_alt3v + .word _Z9fx_ldw_r0v + .word _Z9fx_ldw_r1v + .word _Z9fx_ldw_r2v + .word _Z9fx_ldw_r3v + .word _Z9fx_ldw_r4v + .word _Z9fx_ldw_r5v + .word _Z9fx_ldw_r6v + .word _Z9fx_ldw_r7v + .word _Z9fx_ldw_r8v + .word _Z9fx_ldw_r9v + .word _Z10fx_ldw_r10v + .word _Z10fx_ldw_r11v + .word _Z12fx_plot_2bitv + .word _Z7fx_swapv + .word _Z8fx_colorv + .word _Z6fx_notv + .word _Z9fx_add_r0v + .word _Z9fx_add_r1v + .word _Z9fx_add_r2v + .word _Z9fx_add_r3v + .word _Z9fx_add_r4v + .word _Z9fx_add_r5v + .word _Z9fx_add_r6v + .word _Z9fx_add_r7v + .word _Z9fx_add_r8v + .word _Z9fx_add_r9v + .word _Z10fx_add_r10v + .word _Z10fx_add_r11v + .word _Z10fx_add_r12v + .word _Z10fx_add_r13v + .word _Z10fx_add_r14v + .word _Z10fx_add_r15v + .word _Z9fx_sub_r0v + .word _Z9fx_sub_r1v + .word _Z9fx_sub_r2v + .word _Z9fx_sub_r3v + .word _Z9fx_sub_r4v + .word _Z9fx_sub_r5v + .word _Z9fx_sub_r6v + .word _Z9fx_sub_r7v + .word _Z9fx_sub_r8v + .word _Z9fx_sub_r9v + .word _Z10fx_sub_r10v + .word _Z10fx_sub_r11v + .word _Z10fx_sub_r12v + .word _Z10fx_sub_r13v + .word _Z10fx_sub_r14v + .word _Z10fx_sub_r15v + .word _Z8fx_mergev + .word _Z9fx_and_r1v + .word _Z9fx_and_r2v + .word _Z9fx_and_r3v + .word _Z9fx_and_r4v + .word _Z9fx_and_r5v + .word _Z9fx_and_r6v + .word _Z9fx_and_r7v + .word _Z9fx_and_r8v + .word _Z9fx_and_r9v + .word _Z10fx_and_r10v + .word _Z10fx_and_r11v + .word _Z10fx_and_r12v + .word _Z10fx_and_r13v + .word _Z10fx_and_r14v + .word _Z10fx_and_r15v + .word _Z10fx_mult_r0v + .word _Z10fx_mult_r1v + .word _Z10fx_mult_r2v + .word _Z10fx_mult_r3v + .word _Z10fx_mult_r4v + .word _Z10fx_mult_r5v + .word _Z10fx_mult_r6v + .word _Z10fx_mult_r7v + .word _Z10fx_mult_r8v + .word _Z10fx_mult_r9v + .word _Z11fx_mult_r10v + .word _Z11fx_mult_r11v + .word _Z11fx_mult_r12v + .word _Z11fx_mult_r13v + .word _Z11fx_mult_r14v + .word _Z11fx_mult_r15v + .word _Z6fx_sbkv + .word _Z10fx_link_i1v + .word _Z10fx_link_i2v + .word _Z10fx_link_i3v + .word _Z10fx_link_i4v + .word _Z6fx_sexv + .word _Z6fx_asrv + .word _Z6fx_rorv + .word _Z9fx_jmp_r8v + .word _Z9fx_jmp_r9v + .word _Z10fx_jmp_r10v + .word _Z10fx_jmp_r11v + .word _Z10fx_jmp_r12v + .word _Z10fx_jmp_r13v + .word _Z6fx_lobv + .word _Z8fx_fmultv + .word _Z9fx_ibt_r0v + .word _Z9fx_ibt_r1v + .word _Z9fx_ibt_r2v + .word _Z9fx_ibt_r3v + .word _Z9fx_ibt_r4v + .word _Z9fx_ibt_r5v + .word _Z9fx_ibt_r6v + .word _Z9fx_ibt_r7v + .word _Z9fx_ibt_r8v + .word _Z9fx_ibt_r9v + .word _Z10fx_ibt_r10v + .word _Z10fx_ibt_r11v + .word _Z10fx_ibt_r12v + .word _Z10fx_ibt_r13v + .word _Z10fx_ibt_r14v + .word _Z10fx_ibt_r15v + .word _Z10fx_from_r0v + .word _Z10fx_from_r1v + .word _Z10fx_from_r2v + .word _Z10fx_from_r3v + .word _Z10fx_from_r4v + .word _Z10fx_from_r5v + .word _Z10fx_from_r6v + .word _Z10fx_from_r7v + .word _Z10fx_from_r8v + .word _Z10fx_from_r9v + .word _Z11fx_from_r10v + .word _Z11fx_from_r11v + .word _Z11fx_from_r12v + .word _Z11fx_from_r13v + .word _Z11fx_from_r14v + .word _Z11fx_from_r15v + .word _Z6fx_hibv + .word _Z8fx_or_r1v + .word _Z8fx_or_r2v + .word _Z8fx_or_r3v + .word _Z8fx_or_r4v + .word _Z8fx_or_r5v + .word _Z8fx_or_r6v + .word _Z8fx_or_r7v + .word _Z8fx_or_r8v + .word _Z8fx_or_r9v + .word _Z9fx_or_r10v + .word _Z9fx_or_r11v + .word _Z9fx_or_r12v + .word _Z9fx_or_r13v + .word _Z9fx_or_r14v + .word _Z9fx_or_r15v + .word _Z9fx_inc_r0v + .word _Z9fx_inc_r1v + .word _Z9fx_inc_r2v + .word _Z9fx_inc_r3v + .word _Z9fx_inc_r4v + .word _Z9fx_inc_r5v + .word _Z9fx_inc_r6v + .word _Z9fx_inc_r7v + .word _Z9fx_inc_r8v + .word _Z9fx_inc_r9v + .word _Z10fx_inc_r10v + .word _Z10fx_inc_r11v + .word _Z10fx_inc_r12v + .word _Z10fx_inc_r13v + .word _Z10fx_inc_r14v + .word _Z7fx_getcv + .word _Z9fx_dec_r0v + .word _Z9fx_dec_r1v + .word _Z9fx_dec_r2v + .word _Z9fx_dec_r3v + .word _Z9fx_dec_r4v + .word _Z9fx_dec_r5v + .word _Z9fx_dec_r6v + .word _Z9fx_dec_r7v + .word _Z9fx_dec_r8v + .word _Z9fx_dec_r9v + .word _Z10fx_dec_r10v + .word _Z10fx_dec_r11v + .word _Z10fx_dec_r12v + .word _Z10fx_dec_r13v + .word _Z10fx_dec_r14v + .word _Z7fx_getbv + .word _Z9fx_iwt_r0v + .word _Z9fx_iwt_r1v + .word _Z9fx_iwt_r2v + .word _Z9fx_iwt_r3v + .word _Z9fx_iwt_r4v + .word _Z9fx_iwt_r5v + .word _Z9fx_iwt_r6v + .word _Z9fx_iwt_r7v + .word _Z9fx_iwt_r8v + .word _Z9fx_iwt_r9v + .word _Z10fx_iwt_r10v + .word _Z10fx_iwt_r11v + .word _Z10fx_iwt_r12v + .word _Z10fx_iwt_r13v + .word _Z10fx_iwt_r14v + .word _Z10fx_iwt_r15v + .word _Z7fx_stopv + .word _Z6fx_nopv + .word _Z8fx_cachev + .word _Z6fx_lsrv + .word _Z6fx_rolv + .word _Z6fx_brav + .word _Z6fx_bgev + .word _Z6fx_bltv + .word _Z6fx_bnev + .word _Z6fx_beqv + .word _Z6fx_bplv + .word _Z6fx_bmiv + .word _Z6fx_bccv + .word _Z6fx_bcsv + .word _Z6fx_bvcv + .word _Z6fx_bvsv + .word _Z8fx_to_r0v + .word _Z8fx_to_r1v + .word _Z8fx_to_r2v + .word _Z8fx_to_r3v + .word _Z8fx_to_r4v + .word _Z8fx_to_r5v + .word _Z8fx_to_r6v + .word _Z8fx_to_r7v + .word _Z8fx_to_r8v + .word _Z8fx_to_r9v + .word _Z9fx_to_r10v + .word _Z9fx_to_r11v + .word _Z9fx_to_r12v + .word _Z9fx_to_r13v + .word _Z9fx_to_r14v + .word _Z9fx_to_r15v + .word _Z10fx_with_r0v + .word _Z10fx_with_r1v + .word _Z10fx_with_r2v + .word _Z10fx_with_r3v + .word _Z10fx_with_r4v + .word _Z10fx_with_r5v + .word _Z10fx_with_r6v + .word _Z10fx_with_r7v + .word _Z10fx_with_r8v + .word _Z10fx_with_r9v + .word _Z11fx_with_r10v + .word _Z11fx_with_r11v + .word _Z11fx_with_r12v + .word _Z11fx_with_r13v + .word _Z11fx_with_r14v + .word _Z11fx_with_r15v + .word _Z9fx_stb_r0v + .word _Z9fx_stb_r1v + .word _Z9fx_stb_r2v + .word _Z9fx_stb_r3v + .word _Z9fx_stb_r4v + .word _Z9fx_stb_r5v + .word _Z9fx_stb_r6v + .word _Z9fx_stb_r7v + .word _Z9fx_stb_r8v + .word _Z9fx_stb_r9v + .word _Z10fx_stb_r10v + .word _Z10fx_stb_r11v + .word _Z7fx_loopv + .word _Z7fx_alt1v + .word _Z7fx_alt2v + .word _Z7fx_alt3v + .word _Z9fx_ldb_r0v + .word _Z9fx_ldb_r1v + .word _Z9fx_ldb_r2v + .word _Z9fx_ldb_r3v + .word _Z9fx_ldb_r4v + .word _Z9fx_ldb_r5v + .word _Z9fx_ldb_r6v + .word _Z9fx_ldb_r7v + .word _Z9fx_ldb_r8v + .word _Z9fx_ldb_r9v + .word _Z10fx_ldb_r10v + .word _Z10fx_ldb_r11v + .word _Z12fx_rpix_2bitv + .word _Z7fx_swapv + .word _Z8fx_cmodev + .word _Z6fx_notv + .word _Z9fx_adc_r0v + .word _Z9fx_adc_r1v + .word _Z9fx_adc_r2v + .word _Z9fx_adc_r3v + .word _Z9fx_adc_r4v + .word _Z9fx_adc_r5v + .word _Z9fx_adc_r6v + .word _Z9fx_adc_r7v + .word _Z9fx_adc_r8v + .word _Z9fx_adc_r9v + .word _Z10fx_adc_r10v + .word _Z10fx_adc_r11v + .word _Z10fx_adc_r12v + .word _Z10fx_adc_r13v + .word _Z10fx_adc_r14v + .word _Z10fx_adc_r15v + .word _Z9fx_sbc_r0v + .word _Z9fx_sbc_r1v + .word _Z9fx_sbc_r2v + .word _Z9fx_sbc_r3v + .word _Z9fx_sbc_r4v + .word _Z9fx_sbc_r5v + .word _Z9fx_sbc_r6v + .word _Z9fx_sbc_r7v + .word _Z9fx_sbc_r8v + .word _Z9fx_sbc_r9v + .word _Z10fx_sbc_r10v + .word _Z10fx_sbc_r11v + .word _Z10fx_sbc_r12v + .word _Z10fx_sbc_r13v + .word _Z10fx_sbc_r14v + .word _Z10fx_sbc_r15v + .word _Z8fx_mergev + .word _Z9fx_bic_r1v + .word _Z9fx_bic_r2v + .word _Z9fx_bic_r3v + .word _Z9fx_bic_r4v + .word _Z9fx_bic_r5v + .word _Z9fx_bic_r6v + .word _Z9fx_bic_r7v + .word _Z9fx_bic_r8v + .word _Z9fx_bic_r9v + .word _Z10fx_bic_r10v + .word _Z10fx_bic_r11v + .word _Z10fx_bic_r12v + .word _Z10fx_bic_r13v + .word _Z10fx_bic_r14v + .word _Z10fx_bic_r15v + .word _Z11fx_umult_r0v + .word _Z11fx_umult_r1v + .word _Z11fx_umult_r2v + .word _Z11fx_umult_r3v + .word _Z11fx_umult_r4v + .word _Z11fx_umult_r5v + .word _Z11fx_umult_r6v + .word _Z11fx_umult_r7v + .word _Z11fx_umult_r8v + .word _Z11fx_umult_r9v + .word _Z12fx_umult_r10v + .word _Z12fx_umult_r11v + .word _Z12fx_umult_r12v + .word _Z12fx_umult_r13v + .word _Z12fx_umult_r14v + .word _Z12fx_umult_r15v + .word _Z6fx_sbkv + .word _Z10fx_link_i1v + .word _Z10fx_link_i2v + .word _Z10fx_link_i3v + .word _Z10fx_link_i4v + .word _Z6fx_sexv + .word _Z7fx_div2v + .word _Z6fx_rorv + .word _Z10fx_ljmp_r8v + .word _Z10fx_ljmp_r9v + .word _Z11fx_ljmp_r10v + .word _Z11fx_ljmp_r11v + .word _Z11fx_ljmp_r12v + .word _Z11fx_ljmp_r13v + .word _Z6fx_lobv + .word _Z8fx_lmultv + .word _Z9fx_lms_r0v + .word _Z9fx_lms_r1v + .word _Z9fx_lms_r2v + .word _Z9fx_lms_r3v + .word _Z9fx_lms_r4v + .word _Z9fx_lms_r5v + .word _Z9fx_lms_r6v + .word _Z9fx_lms_r7v + .word _Z9fx_lms_r8v + .word _Z9fx_lms_r9v + .word _Z10fx_lms_r10v + .word _Z10fx_lms_r11v + .word _Z10fx_lms_r12v + .word _Z10fx_lms_r13v + .word _Z10fx_lms_r14v + .word _Z10fx_lms_r15v + .word _Z10fx_from_r0v + .word _Z10fx_from_r1v + .word _Z10fx_from_r2v + .word _Z10fx_from_r3v + .word _Z10fx_from_r4v + .word _Z10fx_from_r5v + .word _Z10fx_from_r6v + .word _Z10fx_from_r7v + .word _Z10fx_from_r8v + .word _Z10fx_from_r9v + .word _Z11fx_from_r10v + .word _Z11fx_from_r11v + .word _Z11fx_from_r12v + .word _Z11fx_from_r13v + .word _Z11fx_from_r14v + .word _Z11fx_from_r15v + .word _Z6fx_hibv + .word _Z9fx_xor_r1v + .word _Z9fx_xor_r2v + .word _Z9fx_xor_r3v + .word _Z9fx_xor_r4v + .word _Z9fx_xor_r5v + .word _Z9fx_xor_r6v + .word _Z9fx_xor_r7v + .word _Z9fx_xor_r8v + .word _Z9fx_xor_r9v + .word _Z10fx_xor_r10v + .word _Z10fx_xor_r11v + .word _Z10fx_xor_r12v + .word _Z10fx_xor_r13v + .word _Z10fx_xor_r14v + .word _Z10fx_xor_r15v + .word _Z9fx_inc_r0v + .word _Z9fx_inc_r1v + .word _Z9fx_inc_r2v + .word _Z9fx_inc_r3v + .word _Z9fx_inc_r4v + .word _Z9fx_inc_r5v + .word _Z9fx_inc_r6v + .word _Z9fx_inc_r7v + .word _Z9fx_inc_r8v + .word _Z9fx_inc_r9v + .word _Z10fx_inc_r10v + .word _Z10fx_inc_r11v + .word _Z10fx_inc_r12v + .word _Z10fx_inc_r13v + .word _Z10fx_inc_r14v + .word _Z7fx_getcv + .word _Z9fx_dec_r0v + .word _Z9fx_dec_r1v + .word _Z9fx_dec_r2v + .word _Z9fx_dec_r3v + .word _Z9fx_dec_r4v + .word _Z9fx_dec_r5v + .word _Z9fx_dec_r6v + .word _Z9fx_dec_r7v + .word _Z9fx_dec_r8v + .word _Z9fx_dec_r9v + .word _Z10fx_dec_r10v + .word _Z10fx_dec_r11v + .word _Z10fx_dec_r12v + .word _Z10fx_dec_r13v + .word _Z10fx_dec_r14v + .word _Z8fx_getbhv + .word _Z8fx_lm_r0v + .word _Z8fx_lm_r1v + .word _Z8fx_lm_r2v + .word _Z8fx_lm_r3v + .word _Z8fx_lm_r4v + .word _Z8fx_lm_r5v + .word _Z8fx_lm_r6v + .word _Z8fx_lm_r7v + .word _Z8fx_lm_r8v + .word _Z8fx_lm_r9v + .word _Z9fx_lm_r10v + .word _Z9fx_lm_r11v + .word _Z9fx_lm_r12v + .word _Z9fx_lm_r13v + .word _Z9fx_lm_r14v + .word _Z9fx_lm_r15v + .word _Z7fx_stopv + .word _Z6fx_nopv + .word _Z8fx_cachev + .word _Z6fx_lsrv + .word _Z6fx_rolv + .word _Z6fx_brav + .word _Z6fx_bgev + .word _Z6fx_bltv + .word _Z6fx_bnev + .word _Z6fx_beqv + .word _Z6fx_bplv + .word _Z6fx_bmiv + .word _Z6fx_bccv + .word _Z6fx_bcsv + .word _Z6fx_bvcv + .word _Z6fx_bvsv + .word _Z8fx_to_r0v + .word _Z8fx_to_r1v + .word _Z8fx_to_r2v + .word _Z8fx_to_r3v + .word _Z8fx_to_r4v + .word _Z8fx_to_r5v + .word _Z8fx_to_r6v + .word _Z8fx_to_r7v + .word _Z8fx_to_r8v + .word _Z8fx_to_r9v + .word _Z9fx_to_r10v + .word _Z9fx_to_r11v + .word _Z9fx_to_r12v + .word _Z9fx_to_r13v + .word _Z9fx_to_r14v + .word _Z9fx_to_r15v + .word _Z10fx_with_r0v + .word _Z10fx_with_r1v + .word _Z10fx_with_r2v + .word _Z10fx_with_r3v + .word _Z10fx_with_r4v + .word _Z10fx_with_r5v + .word _Z10fx_with_r6v + .word _Z10fx_with_r7v + .word _Z10fx_with_r8v + .word _Z10fx_with_r9v + .word _Z11fx_with_r10v + .word _Z11fx_with_r11v + .word _Z11fx_with_r12v + .word _Z11fx_with_r13v + .word _Z11fx_with_r14v + .word _Z11fx_with_r15v + .word _Z9fx_stw_r0v + .word _Z9fx_stw_r1v + .word _Z9fx_stw_r2v + .word _Z9fx_stw_r3v + .word _Z9fx_stw_r4v + .word _Z9fx_stw_r5v + .word _Z9fx_stw_r6v + .word _Z9fx_stw_r7v + .word _Z9fx_stw_r8v + .word _Z9fx_stw_r9v + .word _Z10fx_stw_r10v + .word _Z10fx_stw_r11v + .word _Z7fx_loopv + .word _Z7fx_alt1v + .word _Z7fx_alt2v + .word _Z7fx_alt3v + .word _Z9fx_ldw_r0v + .word _Z9fx_ldw_r1v + .word _Z9fx_ldw_r2v + .word _Z9fx_ldw_r3v + .word _Z9fx_ldw_r4v + .word _Z9fx_ldw_r5v + .word _Z9fx_ldw_r6v + .word _Z9fx_ldw_r7v + .word _Z9fx_ldw_r8v + .word _Z9fx_ldw_r9v + .word _Z10fx_ldw_r10v + .word _Z10fx_ldw_r11v + .word _Z12fx_plot_2bitv + .word _Z7fx_swapv + .word _Z8fx_colorv + .word _Z6fx_notv + .word _Z9fx_add_i0v + .word _Z9fx_add_i1v + .word _Z9fx_add_i2v + .word _Z9fx_add_i3v + .word _Z9fx_add_i4v + .word _Z9fx_add_i5v + .word _Z9fx_add_i6v + .word _Z9fx_add_i7v + .word _Z9fx_add_i8v + .word _Z9fx_add_i9v + .word _Z10fx_add_i10v + .word _Z10fx_add_i11v + .word _Z10fx_add_i12v + .word _Z10fx_add_i13v + .word _Z10fx_add_i14v + .word _Z10fx_add_i15v + .word _Z9fx_sub_i0v + .word _Z9fx_sub_i1v + .word _Z9fx_sub_i2v + .word _Z9fx_sub_i3v + .word _Z9fx_sub_i4v + .word _Z9fx_sub_i5v + .word _Z9fx_sub_i6v + .word _Z9fx_sub_i7v + .word _Z9fx_sub_i8v + .word _Z9fx_sub_i9v + .word _Z10fx_sub_i10v + .word _Z10fx_sub_i11v + .word _Z10fx_sub_i12v + .word _Z10fx_sub_i13v + .word _Z10fx_sub_i14v + .word _Z10fx_sub_i15v + .word _Z8fx_mergev + .word _Z9fx_and_i1v + .word _Z9fx_and_i2v + .word _Z9fx_and_i3v + .word _Z9fx_and_i4v + .word _Z9fx_and_i5v + .word _Z9fx_and_i6v + .word _Z9fx_and_i7v + .word _Z9fx_and_i8v + .word _Z9fx_and_i9v + .word _Z10fx_and_i10v + .word _Z10fx_and_i11v + .word _Z10fx_and_i12v + .word _Z10fx_and_i13v + .word _Z10fx_and_i14v + .word _Z10fx_and_i15v + .word _Z10fx_mult_i0v + .word _Z10fx_mult_i1v + .word _Z10fx_mult_i2v + .word _Z10fx_mult_i3v + .word _Z10fx_mult_i4v + .word _Z10fx_mult_i5v + .word _Z10fx_mult_i6v + .word _Z10fx_mult_i7v + .word _Z10fx_mult_i8v + .word _Z10fx_mult_i9v + .word _Z11fx_mult_i10v + .word _Z11fx_mult_i11v + .word _Z11fx_mult_i12v + .word _Z11fx_mult_i13v + .word _Z11fx_mult_i14v + .word _Z11fx_mult_i15v + .word _Z6fx_sbkv + .word _Z10fx_link_i1v + .word _Z10fx_link_i2v + .word _Z10fx_link_i3v + .word _Z10fx_link_i4v + .word _Z6fx_sexv + .word _Z6fx_asrv + .word _Z6fx_rorv + .word _Z9fx_jmp_r8v + .word _Z9fx_jmp_r9v + .word _Z10fx_jmp_r10v + .word _Z10fx_jmp_r11v + .word _Z10fx_jmp_r12v + .word _Z10fx_jmp_r13v + .word _Z6fx_lobv + .word _Z8fx_fmultv + .word _Z9fx_sms_r0v + .word _Z9fx_sms_r1v + .word _Z9fx_sms_r2v + .word _Z9fx_sms_r3v + .word _Z9fx_sms_r4v + .word _Z9fx_sms_r5v + .word _Z9fx_sms_r6v + .word _Z9fx_sms_r7v + .word _Z9fx_sms_r8v + .word _Z9fx_sms_r9v + .word _Z10fx_sms_r10v + .word _Z10fx_sms_r11v + .word _Z10fx_sms_r12v + .word _Z10fx_sms_r13v + .word _Z10fx_sms_r14v + .word _Z10fx_sms_r15v + .word _Z10fx_from_r0v + .word _Z10fx_from_r1v + .word _Z10fx_from_r2v + .word _Z10fx_from_r3v + .word _Z10fx_from_r4v + .word _Z10fx_from_r5v + .word _Z10fx_from_r6v + .word _Z10fx_from_r7v + .word _Z10fx_from_r8v + .word _Z10fx_from_r9v + .word _Z11fx_from_r10v + .word _Z11fx_from_r11v + .word _Z11fx_from_r12v + .word _Z11fx_from_r13v + .word _Z11fx_from_r14v + .word _Z11fx_from_r15v + .word _Z6fx_hibv + .word _Z8fx_or_i1v + .word _Z8fx_or_i2v + .word _Z8fx_or_i3v + .word _Z8fx_or_i4v + .word _Z8fx_or_i5v + .word _Z8fx_or_i6v + .word _Z8fx_or_i7v + .word _Z8fx_or_i8v + .word _Z8fx_or_i9v + .word _Z9fx_or_i10v + .word _Z9fx_or_i11v + .word _Z9fx_or_i12v + .word _Z9fx_or_i13v + .word _Z9fx_or_i14v + .word _Z9fx_or_i15v + .word _Z9fx_inc_r0v + .word _Z9fx_inc_r1v + .word _Z9fx_inc_r2v + .word _Z9fx_inc_r3v + .word _Z9fx_inc_r4v + .word _Z9fx_inc_r5v + .word _Z9fx_inc_r6v + .word _Z9fx_inc_r7v + .word _Z9fx_inc_r8v + .word _Z9fx_inc_r9v + .word _Z10fx_inc_r10v + .word _Z10fx_inc_r11v + .word _Z10fx_inc_r12v + .word _Z10fx_inc_r13v + .word _Z10fx_inc_r14v + .word _Z7fx_rambv + .word _Z9fx_dec_r0v + .word _Z9fx_dec_r1v + .word _Z9fx_dec_r2v + .word _Z9fx_dec_r3v + .word _Z9fx_dec_r4v + .word _Z9fx_dec_r5v + .word _Z9fx_dec_r6v + .word _Z9fx_dec_r7v + .word _Z9fx_dec_r8v + .word _Z9fx_dec_r9v + .word _Z10fx_dec_r10v + .word _Z10fx_dec_r11v + .word _Z10fx_dec_r12v + .word _Z10fx_dec_r13v + .word _Z10fx_dec_r14v + .word _Z8fx_getblv + .word _Z8fx_sm_r0v + .word _Z8fx_sm_r1v + .word _Z8fx_sm_r2v + .word _Z8fx_sm_r3v + .word _Z8fx_sm_r4v + .word _Z8fx_sm_r5v + .word _Z8fx_sm_r6v + .word _Z8fx_sm_r7v + .word _Z8fx_sm_r8v + .word _Z8fx_sm_r9v + .word _Z9fx_sm_r10v + .word _Z9fx_sm_r11v + .word _Z9fx_sm_r12v + .word _Z9fx_sm_r13v + .word _Z9fx_sm_r14v + .word _Z9fx_sm_r15v + .word _Z7fx_stopv + .word _Z6fx_nopv + .word _Z8fx_cachev + .word _Z6fx_lsrv + .word _Z6fx_rolv + .word _Z6fx_brav + .word _Z6fx_bgev + .word _Z6fx_bltv + .word _Z6fx_bnev + .word _Z6fx_beqv + .word _Z6fx_bplv + .word _Z6fx_bmiv + .word _Z6fx_bccv + .word _Z6fx_bcsv + .word _Z6fx_bvcv + .word _Z6fx_bvsv + .word _Z8fx_to_r0v + .word _Z8fx_to_r1v + .word _Z8fx_to_r2v + .word _Z8fx_to_r3v + .word _Z8fx_to_r4v + .word _Z8fx_to_r5v + .word _Z8fx_to_r6v + .word _Z8fx_to_r7v + .word _Z8fx_to_r8v + .word _Z8fx_to_r9v + .word _Z9fx_to_r10v + .word _Z9fx_to_r11v + .word _Z9fx_to_r12v + .word _Z9fx_to_r13v + .word _Z9fx_to_r14v + .word _Z9fx_to_r15v + .word _Z10fx_with_r0v + .word _Z10fx_with_r1v + .word _Z10fx_with_r2v + .word _Z10fx_with_r3v + .word _Z10fx_with_r4v + .word _Z10fx_with_r5v + .word _Z10fx_with_r6v + .word _Z10fx_with_r7v + .word _Z10fx_with_r8v + .word _Z10fx_with_r9v + .word _Z11fx_with_r10v + .word _Z11fx_with_r11v + .word _Z11fx_with_r12v + .word _Z11fx_with_r13v + .word _Z11fx_with_r14v + .word _Z11fx_with_r15v + .word _Z9fx_stb_r0v + .word _Z9fx_stb_r1v + .word _Z9fx_stb_r2v + .word _Z9fx_stb_r3v + .word _Z9fx_stb_r4v + .word _Z9fx_stb_r5v + .word _Z9fx_stb_r6v + .word _Z9fx_stb_r7v + .word _Z9fx_stb_r8v + .word _Z9fx_stb_r9v + .word _Z10fx_stb_r10v + .word _Z10fx_stb_r11v + .word _Z7fx_loopv + .word _Z7fx_alt1v + .word _Z7fx_alt2v + .word _Z7fx_alt3v + .word _Z9fx_ldb_r0v + .word _Z9fx_ldb_r1v + .word _Z9fx_ldb_r2v + .word _Z9fx_ldb_r3v + .word _Z9fx_ldb_r4v + .word _Z9fx_ldb_r5v + .word _Z9fx_ldb_r6v + .word _Z9fx_ldb_r7v + .word _Z9fx_ldb_r8v + .word _Z9fx_ldb_r9v + .word _Z10fx_ldb_r10v + .word _Z10fx_ldb_r11v + .word _Z12fx_rpix_2bitv + .word _Z7fx_swapv + .word _Z8fx_cmodev + .word _Z6fx_notv + .word _Z9fx_adc_i0v + .word _Z9fx_adc_i1v + .word _Z9fx_adc_i2v + .word _Z9fx_adc_i3v + .word _Z9fx_adc_i4v + .word _Z9fx_adc_i5v + .word _Z9fx_adc_i6v + .word _Z9fx_adc_i7v + .word _Z9fx_adc_i8v + .word _Z9fx_adc_i9v + .word _Z10fx_adc_i10v + .word _Z10fx_adc_i11v + .word _Z10fx_adc_i12v + .word _Z10fx_adc_i13v + .word _Z10fx_adc_i14v + .word _Z10fx_adc_i15v + .word _Z9fx_cmp_r0v + .word _Z9fx_cmp_r1v + .word _Z9fx_cmp_r2v + .word _Z9fx_cmp_r3v + .word _Z9fx_cmp_r4v + .word _Z9fx_cmp_r5v + .word _Z9fx_cmp_r6v + .word _Z9fx_cmp_r7v + .word _Z9fx_cmp_r8v + .word _Z9fx_cmp_r9v + .word _Z10fx_cmp_r10v + .word _Z10fx_cmp_r11v + .word _Z10fx_cmp_r12v + .word _Z10fx_cmp_r13v + .word _Z10fx_cmp_r14v + .word _Z10fx_cmp_r15v + .word _Z8fx_mergev + .word _Z9fx_bic_i1v + .word _Z9fx_bic_i2v + .word _Z9fx_bic_i3v + .word _Z9fx_bic_i4v + .word _Z9fx_bic_i5v + .word _Z9fx_bic_i6v + .word _Z9fx_bic_i7v + .word _Z9fx_bic_i8v + .word _Z9fx_bic_i9v + .word _Z10fx_bic_i10v + .word _Z10fx_bic_i11v + .word _Z10fx_bic_i12v + .word _Z10fx_bic_i13v + .word _Z10fx_bic_i14v + .word _Z10fx_bic_i15v + .word _Z11fx_umult_i0v + .word _Z11fx_umult_i1v + .word _Z11fx_umult_i2v + .word _Z11fx_umult_i3v + .word _Z11fx_umult_i4v + .word _Z11fx_umult_i5v + .word _Z11fx_umult_i6v + .word _Z11fx_umult_i7v + .word _Z11fx_umult_i8v + .word _Z11fx_umult_i9v + .word _Z12fx_umult_i10v + .word _Z12fx_umult_i11v + .word _Z12fx_umult_i12v + .word _Z12fx_umult_i13v + .word _Z12fx_umult_i14v + .word _Z12fx_umult_i15v + .word _Z6fx_sbkv + .word _Z10fx_link_i1v + .word _Z10fx_link_i2v + .word _Z10fx_link_i3v + .word _Z10fx_link_i4v + .word _Z6fx_sexv + .word _Z7fx_div2v + .word _Z6fx_rorv + .word _Z10fx_ljmp_r8v + .word _Z10fx_ljmp_r9v + .word _Z11fx_ljmp_r10v + .word _Z11fx_ljmp_r11v + .word _Z11fx_ljmp_r12v + .word _Z11fx_ljmp_r13v + .word _Z6fx_lobv + .word _Z8fx_lmultv + .word _Z9fx_lms_r0v + .word _Z9fx_lms_r1v + .word _Z9fx_lms_r2v + .word _Z9fx_lms_r3v + .word _Z9fx_lms_r4v + .word _Z9fx_lms_r5v + .word _Z9fx_lms_r6v + .word _Z9fx_lms_r7v + .word _Z9fx_lms_r8v + .word _Z9fx_lms_r9v + .word _Z10fx_lms_r10v + .word _Z10fx_lms_r11v + .word _Z10fx_lms_r12v + .word _Z10fx_lms_r13v + .word _Z10fx_lms_r14v + .word _Z10fx_lms_r15v + .word _Z10fx_from_r0v + .word _Z10fx_from_r1v + .word _Z10fx_from_r2v + .word _Z10fx_from_r3v + .word _Z10fx_from_r4v + .word _Z10fx_from_r5v + .word _Z10fx_from_r6v + .word _Z10fx_from_r7v + .word _Z10fx_from_r8v + .word _Z10fx_from_r9v + .word _Z11fx_from_r10v + .word _Z11fx_from_r11v + .word _Z11fx_from_r12v + .word _Z11fx_from_r13v + .word _Z11fx_from_r14v + .word _Z11fx_from_r15v + .word _Z6fx_hibv + .word _Z9fx_xor_i1v + .word _Z9fx_xor_i2v + .word _Z9fx_xor_i3v + .word _Z9fx_xor_i4v + .word _Z9fx_xor_i5v + .word _Z9fx_xor_i6v + .word _Z9fx_xor_i7v + .word _Z9fx_xor_i8v + .word _Z9fx_xor_i9v + .word _Z10fx_xor_i10v + .word _Z10fx_xor_i11v + .word _Z10fx_xor_i12v + .word _Z10fx_xor_i13v + .word _Z10fx_xor_i14v + .word _Z10fx_xor_i15v + .word _Z9fx_inc_r0v + .word _Z9fx_inc_r1v + .word _Z9fx_inc_r2v + .word _Z9fx_inc_r3v + .word _Z9fx_inc_r4v + .word _Z9fx_inc_r5v + .word _Z9fx_inc_r6v + .word _Z9fx_inc_r7v + .word _Z9fx_inc_r8v + .word _Z9fx_inc_r9v + .word _Z10fx_inc_r10v + .word _Z10fx_inc_r11v + .word _Z10fx_inc_r12v + .word _Z10fx_inc_r13v + .word _Z10fx_inc_r14v + .word _Z7fx_rombv + .word _Z9fx_dec_r0v + .word _Z9fx_dec_r1v + .word _Z9fx_dec_r2v + .word _Z9fx_dec_r3v + .word _Z9fx_dec_r4v + .word _Z9fx_dec_r5v + .word _Z9fx_dec_r6v + .word _Z9fx_dec_r7v + .word _Z9fx_dec_r8v + .word _Z9fx_dec_r9v + .word _Z10fx_dec_r10v + .word _Z10fx_dec_r11v + .word _Z10fx_dec_r12v + .word _Z10fx_dec_r13v + .word _Z10fx_dec_r14v + .word _Z8fx_getbsv + .word _Z8fx_lm_r0v + .word _Z8fx_lm_r1v + .word _Z8fx_lm_r2v + .word _Z8fx_lm_r3v + .word _Z8fx_lm_r4v + .word _Z8fx_lm_r5v + .word _Z8fx_lm_r6v + .word _Z8fx_lm_r7v + .word _Z8fx_lm_r8v + .word _Z8fx_lm_r9v + .word _Z9fx_lm_r10v + .word _Z9fx_lm_r11v + .word _Z9fx_lm_r12v + .word _Z9fx_lm_r13v + .word _Z9fx_lm_r14v + .word _Z9fx_lm_r15v + .ident "GCC: (GNU) 4.2.4" diff --git a/src/gammatab.h b/src/gammatab.h new file mode 100644 index 0000000..11f6f4c --- /dev/null +++ b/src/gammatab.h @@ -0,0 +1,22 @@ +unsigned char gammatab[10][32]={ + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F, + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F}, + {0x00,0x01,0x02,0x03,0x04,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10, + 0x11,0x12,0x13,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F}, + {0x00,0x01,0x03,0x04,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11, + 0x12,0x13,0x14,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F}, + {0x00,0x02,0x04,0x06,0x07,0x08,0x09,0x0A,0x0C,0x0D,0x0E,0x0F,0x0F,0x10,0x11,0x12, + 0x13,0x14,0x15,0x16,0x16,0x17,0x18,0x19,0x19,0x1A,0x1B,0x1C,0x1C,0x1D,0x1E,0x1F}, + {0x00,0x03,0x05,0x07,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14, + 0x14,0x15,0x16,0x17,0x17,0x18,0x19,0x19,0x1A,0x1B,0x1B,0x1C,0x1D,0x1D,0x1E,0x1F}, + {0x00,0x05,0x07,0x09,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14,0x14,0x15, + 0x16,0x16,0x17,0x18,0x18,0x19,0x1A,0x1A,0x1B,0x1B,0x1C,0x1C,0x1D,0x1D,0x1E,0x1F}, + {0x00,0x07,0x0A,0x0C,0x0D,0x0E,0x10,0x11,0x12,0x12,0x13,0x14,0x15,0x15,0x16,0x17, + 0x17,0x18,0x18,0x19,0x1A,0x1A,0x1B,0x1B,0x1B,0x1C,0x1C,0x1D,0x1D,0x1E,0x1E,0x1F}, + {0x00,0x0B,0x0D,0x0F,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x16,0x17,0x17,0x18,0x18, + 0x19,0x19,0x1A,0x1A,0x1B,0x1B,0x1B,0x1C,0x1C,0x1D,0x1D,0x1D,0x1E,0x1E,0x1E,0x1F}, + {0x00,0x0F,0x11,0x13,0x14,0x15,0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1A,0x1A,0x1A, + 0x1B,0x1B,0x1B,0x1C,0x1C,0x1C,0x1C,0x1D,0x1D,0x1D,0x1D,0x1E,0x1E,0x1E,0x1E,0x1F}, + {0x00,0x15,0x17,0x18,0x19,0x19,0x1A,0x1A,0x1B,0x1B,0x1B,0x1B,0x1C,0x1C,0x1C,0x1C, + 0x1D,0x1D,0x1D,0x1D,0x1D,0x1D,0x1D,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1F} +}; diff --git a/src/getset.h b/src/getset.h new file mode 100644 index 0000000..44759e8 --- /dev/null +++ b/src/getset.h @@ -0,0 +1,710 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#ifndef _GETSET_H_ +#define _GETSET_H_ + +#include "ppu.h" +#include "dsp1.h" +#include "cpuexec.h" +#include "sa1.h" + +//#define __memcheck__ +//#define __show_io__ +extern int oppause; +//extern uint16 mem_check; + +INLINE uint8 S9xGetByte (uint32 Address) +{ +#ifdef __show_io__ + char str[64]; + sprintf(str,"rd @ %04X",Address); + S9xMessage(0,0,str); + gp32_pause(); +#endif +#ifdef __memcheck__ + mem_check+=(Address>>16)+Address; +#endif +#if defined(VAR_CYCLES) || defined(CPU_SHUTDOWN) + int block; + uint8 *GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; +#else + uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; +#endif + if (GetAddress >= (uint8 *) CMemory::MAP_LAST) + { +#ifdef VAR_CYCLES + CPU.Cycles += Memory.MemorySpeed [block]; +#endif +#ifdef CPU_SHUTDOWN + if (Memory.BlockIsRAM [block]) + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + return (*(GetAddress + (Address & 0xffff))); + } + + switch ((int) GetAddress) + { + case CMemory::MAP_PPU: +#ifdef VAR_CYCLES + if (!CPU.InDMA) + CPU.Cycles += ONE_CYCLE; +#endif + return (S9xGetPPU (Address & 0xffff)); + case CMemory::MAP_CPU: +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + return (S9xGetCPU (Address & 0xffff)); + case CMemory::MAP_DSP: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + return (S9xGetDSP (Address & 0xffff)); + case CMemory::MAP_SA1RAM: + case CMemory::MAP_LOROM_SRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + return (*(Memory.SRAM + ((Address & CPU.Memory_SRAMMask)))); + + case CMemory::MAP_HIROM_SRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + return (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + + ((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask))); + + case CMemory::MAP_DEBUG: +#ifdef DEBUGGER + printf ("R(B) %06x\n", Address); +#endif + + case CMemory::MAP_BWRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + return (*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000))); +//#ifndef __GP32__ + case CMemory::MAP_C4: + return (S9xGetC4 (Address & 0xffff)); +//#endif + default: + case CMemory::MAP_NONE: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif +#ifdef DEBUGGER + printf ("R(B) %06x\n", Address); +#endif + return ((Address >> 8) & 0xff); + } +} + +INLINE uint16 S9xGetWord (uint32 Address) +{ +#ifdef __show_io__ + char str[64]; + sprintf(str,"rd @ %04X",Address); + S9xMessage(0,0,str); + gp32_pause(); +#endif +#ifdef __memcheck__ + mem_check+=(Address>>16)+Address; +#endif + if ((Address & 0x1fff) == 0x1fff) + { + return (S9xGetByte (Address) | (S9xGetByte (Address + 1) << 8)); + } +#if defined(VAR_CYCLES) || defined(CPU_SHUTDOWN) + int block; + uint8 *GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; +#else + uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; +#endif + if (GetAddress >= (uint8 *) CMemory::MAP_LAST) + { +#ifdef VAR_CYCLES + CPU.Cycles += Memory.MemorySpeed [block] << 1; +#endif +#ifdef CPU_SHUTDOWN + if (Memory.BlockIsRAM [block]) + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif +#ifdef FAST_LSB_WORD_ACCESS + return (*(uint16 *) (GetAddress + (Address & 0xffff))); +#else + return (*(GetAddress + (Address & 0xffff)) | + (*(GetAddress + (Address & 0xffff) + 1) << 8)); +#endif + } + + switch ((int) GetAddress) + { + case CMemory::MAP_PPU: +#ifdef VAR_CYCLES + if (!CPU.InDMA) + CPU.Cycles += TWO_CYCLES; +#endif + return (S9xGetPPU (Address & 0xffff) | + (S9xGetPPU ((Address + 1) & 0xffff) << 8)); + case CMemory::MAP_CPU: +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + return (S9xGetCPU (Address & 0xffff) | + (S9xGetCPU ((Address + 1) & 0xffff) << 8)); + case CMemory::MAP_DSP: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif + return (S9xGetDSP (Address & 0xffff) | + (S9xGetDSP ((Address + 1) & 0xffff) << 8)); + case CMemory::MAP_SA1RAM: + case CMemory::MAP_LOROM_SRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif + return (*(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) | + (*(Memory.SRAM + ((Address + 1) & CPU.Memory_SRAMMask)) << 8)); + + case CMemory::MAP_HIROM_SRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif + return (*(Memory.SRAM + + (((Address & 0x7fff) - 0x6000 + + ((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) | + (*(Memory.SRAM + + ((((Address + 1) & 0x7fff) - 0x6000 + + (((Address + 1) & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) << 8)); + + case CMemory::MAP_BWRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif + return (*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) | + (*(Memory.BWRAM + (((Address + 1) & 0x7fff) - 0x6000)) << 8)); + + case CMemory::MAP_DEBUG: +#ifdef DEBUGGER + printf ("R(W) %06x\n", Address); +#endif + +//#ifndef __GP32__ + case CMemory::MAP_C4: + return (S9xGetC4 (Address & 0xffff) | + (S9xGetC4 ((Address + 1) & 0xffff) << 8)); +//#endif + default: + case CMemory::MAP_NONE: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif +#ifdef DEBUGGER + printf ("R(W) %06x\n", Address); +#endif + return (((Address >> 8) | (Address & 0xff00)) & 0xffff); + } +} + +INLINE void S9xSetByte (uint8 Byte, uint32 Address) +{ +#ifdef __show_io__ + char str[64]; + sprintf(str,"wr @ %04X %02X",Address,Byte); + S9xMessage(0,0,str); + gp32_pause(); +#endif +#ifdef __memcheck__ + mem_check+=Byte; +#endif + +#if defined(CPU_SHUTDOWN) + CPU.WaitAddress = NULL; +#endif +#if defined(VAR_CYCLES) + int block; + uint8 *SetAddress = Memory.WriteMap [block = ((Address >> MEMMAP_SHIFT) & MEMMAP_MASK)]; +#else + uint8 *SetAddress = Memory.WriteMap [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; +#endif + + if (SetAddress >= (uint8 *) CMemory::MAP_LAST) + { +#ifdef VAR_CYCLES + CPU.Cycles += Memory.MemorySpeed [block]; +#endif +#ifdef CPU_SHUTDOWN + SetAddress += Address & 0xffff; +#ifdef USE_SA1 + if (SetAddress == SA1.WaitByteAddress1 || + SetAddress == SA1.WaitByteAddress2) + { + SA1.Executing = SA1.S9xOpcodes != NULL; + SA1.WaitCounter = 0; + } +#endif + *SetAddress = Byte; +#else + *(SetAddress + (Address & 0xffff)) = Byte; +#endif + return; + } + + switch ((int) SetAddress) + { + case CMemory::MAP_PPU: +#ifdef VAR_CYCLES + if (!CPU.InDMA) + CPU.Cycles += ONE_CYCLE; +#endif + S9xSetPPU (Byte, Address & 0xffff); + return; + + case CMemory::MAP_CPU: +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + S9xSetCPU (Byte, Address & 0xffff); + return; + + case CMemory::MAP_DSP: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + S9xSetDSP (Byte, Address & 0xffff); + return; + + case CMemory::MAP_LOROM_SRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + if (CPU.Memory_SRAMMask) + { + *(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) = Byte; + CPU.SRAMModified = TRUE; + } + return; + + case CMemory::MAP_HIROM_SRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + if (CPU.Memory_SRAMMask) + { + *(Memory.SRAM + (((Address & 0x7fff) - 0x6000 + + ((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) = Byte; + CPU.SRAMModified = TRUE; + } + return; + + case CMemory::MAP_BWRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = Byte; + CPU.SRAMModified = TRUE; + return; + + case CMemory::MAP_DEBUG: +#ifdef DEBUGGER + printf ("W(B) %06x\n", Address); +#endif + + case CMemory::MAP_SA1RAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + *(Memory.SRAM + (Address & 0xffff)) = Byte; +#ifdef USE_SA1 + SA1.Executing = !SA1.Waiting; +#endif + break; +//#ifndef __GP32__ + case CMemory::MAP_C4: + S9xSetC4 (Byte, Address & 0xffff); + return; +//#endif + default: + case CMemory::MAP_NONE: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif +#ifdef DEBUGGER + printf ("W(B) %06x\n", Address); +#endif + return; + } +} + +INLINE void S9xSetWord (uint16 Word, uint32 Address) +{ +#ifdef __show_io__ + char str[64]; + sprintf(str,"wr @ %04X %04X",Address,Word); + S9xMessage(0,0,str); + gp32_pause(); +#endif +#ifdef __memcheck__ + mem_check+=Word; +#endif +#if defined(CPU_SHUTDOWN) + CPU.WaitAddress = NULL; +#endif +#if defined (VAR_CYCLES) + int block; + uint8 *SetAddress = Memory.WriteMap [block = ((Address >> MEMMAP_SHIFT) & MEMMAP_MASK)]; +#else + uint8 *SetAddress = Memory.WriteMap [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; +#endif + + if (SetAddress >= (uint8 *) CMemory::MAP_LAST) + { +#ifdef VAR_CYCLES + CPU.Cycles += Memory.MemorySpeed [block] << 1; +#endif +#if defined(CPU_SHUTDOWN) && defined(USE_SA1) + SetAddress += Address & 0xffff; + if (SetAddress == SA1.WaitByteAddress1 || + SetAddress == SA1.WaitByteAddress2) + { + SA1.Executing = SA1.S9xOpcodes != NULL; + SA1.WaitCounter = 0; + } + SetAddress -= Address & 0xffff; +#ifdef FAST_LSB_WORD_ACCESS + *(uint16 *) SetAddress = Word; +#else + *(SetAddress + (Address & 0xffff)) = (uint8) Word; + *(SetAddress + ((Address + 1) & 0xffff)) = Word >> 8; +#endif +#else +#ifdef FAST_LSB_WORD_ACCESS + *(uint16 *) (SetAddress + (Address & 0xffff)) = Word; +#else + *(SetAddress + (Address & 0xffff)) = (uint8) Word; + *(SetAddress + ((Address + 1) & 0xffff)) = Word >> 8; +#endif +#endif + return; + } + + switch ((int) SetAddress) + { + case CMemory::MAP_PPU: +#ifdef VAR_CYCLES + if (!CPU.InDMA) + CPU.Cycles += TWO_CYCLES; +#endif + S9xSetPPU ((uint8) Word, Address & 0xffff); + S9xSetPPU (Word >> 8, (Address & 0xffff) + 1); + return; + + case CMemory::MAP_CPU: +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#endif + S9xSetCPU ((uint8) Word, (Address & 0xffff)); + S9xSetCPU (Word >> 8, (Address & 0xffff) + 1); + return; + + case CMemory::MAP_DSP: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif + S9xSetDSP ((uint8) Word, (Address & 0xffff)); + S9xSetDSP (Word >> 8, (Address & 0xffff) + 1); + return; + + case CMemory::MAP_LOROM_SRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif + if (CPU.Memory_SRAMMask) + { + *(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) = (uint8) Word; + *(Memory.SRAM + ((Address + 1) & CPU.Memory_SRAMMask)) = Word >> 8; + CPU.SRAMModified = TRUE; + } + return; + + case CMemory::MAP_HIROM_SRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif + if (CPU.Memory_SRAMMask) + { + *(Memory.SRAM + + (((Address & 0x7fff) - 0x6000 + + ((Address & 0xf0000) >> MEMMAP_SHIFT) & CPU.Memory_SRAMMask))) = (uint8) Word; + *(Memory.SRAM + + ((((Address + 1) & 0x7fff) - 0x6000 + + (((Address + 1) & 0xf0000) >> MEMMAP_SHIFT) & CPU.Memory_SRAMMask))) = (uint8) (Word >> 8); + CPU.SRAMModified = TRUE; + } + return; + + case CMemory::MAP_BWRAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif + *(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = (uint8) Word; + *(Memory.BWRAM + (((Address + 1) & 0x7fff) - 0x6000)) = (uint8) (Word >> 8); + CPU.SRAMModified = TRUE; + return; + + case CMemory::MAP_DEBUG: +#ifdef DEBUGGER + printf ("W(W) %06x\n", Address); +#endif + + case CMemory::MAP_SA1RAM: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE; +#endif + *(Memory.SRAM + (Address & 0xffff)) = (uint8) Word; + *(Memory.SRAM + ((Address + 1) & 0xffff)) = (uint8) (Word >> 8); +#ifdef USE_SA1 + SA1.Executing = !SA1.Waiting; +#endif + break; +//#ifndef __GP32__ + case CMemory::MAP_C4: + S9xSetC4 (Word & 0xff, Address & 0xffff); + S9xSetC4 ((uint8) (Word >> 8), (Address + 1) & 0xffff); + return; +//#endif + default: + case CMemory::MAP_NONE: +#ifdef VAR_CYCLES + CPU.Cycles += SLOW_ONE_CYCLE * 2; +#endif +#ifdef DEBUGGER + printf ("W(W) %06x\n", Address); +#endif + return; + } +} + +INLINE uint8 *GetBasePointer (uint32 Address) +{ + uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; + if (GetAddress >= (uint8 *) CMemory::MAP_LAST) + return (GetAddress); + + switch ((int) GetAddress) + { + case CMemory::MAP_PPU: + return (Memory.FillRAM - 0x2000); + case CMemory::MAP_CPU: + return (Memory.FillRAM - 0x4000); + case CMemory::MAP_DSP: + return (Memory.FillRAM - 0x6000); + case CMemory::MAP_SA1RAM: + case CMemory::MAP_LOROM_SRAM: + return (Memory.SRAM); + case CMemory::MAP_BWRAM: + return (Memory.BWRAM - 0x6000); + case CMemory::MAP_HIROM_SRAM: + return (Memory.SRAM - 0x6000); +//#ifndef __GP32__ + case CMemory::MAP_C4: + return (Memory.C4RAM - 0x6000); +//#endif + case CMemory::MAP_DEBUG: +#ifdef DEBUGGER + printf ("GBP %06x\n", Address); +#endif + + default: + case CMemory::MAP_NONE: +#ifdef DEBUGGER + printf ("GBP %06x\n", Address); +#endif + return (0); + } +} + +INLINE uint8 *S9xGetMemPointer (uint32 Address) +{ + uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; + if (GetAddress >= (uint8 *) CMemory::MAP_LAST) + return (GetAddress + (Address & 0xffff)); + + switch ((int) GetAddress) + { + case CMemory::MAP_PPU: + return (Memory.FillRAM - 0x2000 + (Address & 0xffff)); + case CMemory::MAP_CPU: + return (Memory.FillRAM - 0x4000 + (Address & 0xffff)); + case CMemory::MAP_DSP: + return (Memory.FillRAM - 0x6000 + (Address & 0xffff)); + case CMemory::MAP_SA1RAM: + case CMemory::MAP_LOROM_SRAM: + return (Memory.SRAM + (Address & 0xffff)); + case CMemory::MAP_BWRAM: + return (Memory.BWRAM - 0x6000 + (Address & 0xffff)); + case CMemory::MAP_HIROM_SRAM: + return (Memory.SRAM - 0x6000 + (Address & 0xffff)); +//#ifndef __GP32__ + case CMemory::MAP_C4: + return (Memory.C4RAM - 0x6000 + (Address & 0xffff)); +//#endif + case CMemory::MAP_DEBUG: +#ifdef DEBUGGER + printf ("GMP %06x\n", Address); +#endif + default: + case CMemory::MAP_NONE: +#ifdef DEBUGGER + printf ("GMP %06x\n", Address); +#endif + return (0); + } +} + +INLINE void S9xSetPCBase (uint32 Address) +{ +#ifdef VAR_CYCLES + int block; + uint8 *GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; +#else + uint8 *GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK]; +#endif + if (GetAddress >= (uint8 *) CMemory::MAP_LAST) + { +#ifdef VAR_CYCLES + CPU.MemSpeed = Memory.MemorySpeed [block]; + CPU.MemSpeedx2 = CPU.MemSpeed << 1; +#endif + CPU.PCBase = GetAddress; + CPU.PC = GetAddress + (Address & 0xffff); + return; + } + + switch ((int) GetAddress) + { + case CMemory::MAP_PPU: +#ifdef VAR_CYCLES + CPU.MemSpeed = ONE_CYCLE; + CPU.MemSpeedx2 = TWO_CYCLES; +#endif + CPU.PCBase = Memory.FillRAM - 0x2000; + CPU.PC = CPU.PCBase + (Address & 0xffff); + return; + + case CMemory::MAP_CPU: +#ifdef VAR_CYCLES + CPU.MemSpeed = ONE_CYCLE; + CPU.MemSpeedx2 = TWO_CYCLES; +#endif + CPU.PCBase = Memory.FillRAM - 0x4000; + CPU.PC = CPU.PCBase + (Address & 0xffff); + return; + + case CMemory::MAP_DSP: +#ifdef VAR_CYCLES + CPU.MemSpeed = SLOW_ONE_CYCLE; + CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; +#endif + CPU.PCBase = Memory.FillRAM - 0x6000; + CPU.PC = CPU.PCBase + (Address & 0xffff); + return; + + case CMemory::MAP_SA1RAM: + case CMemory::MAP_LOROM_SRAM: +#ifdef VAR_CYCLES + CPU.MemSpeed = SLOW_ONE_CYCLE; + CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; +#endif + CPU.PCBase = Memory.SRAM; + CPU.PC = CPU.PCBase + (Address & 0xffff); + return; + + case CMemory::MAP_BWRAM: +#ifdef VAR_CYCLES + CPU.MemSpeed = SLOW_ONE_CYCLE; + CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; +#endif + CPU.PCBase = Memory.BWRAM - 0x6000; + CPU.PC = CPU.PCBase + (Address & 0xffff); + return; + case CMemory::MAP_HIROM_SRAM: +#ifdef VAR_CYCLES + CPU.MemSpeed = SLOW_ONE_CYCLE; + CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; +#endif + CPU.PCBase = Memory.SRAM - 0x6000; + CPU.PC = CPU.PCBase + (Address & 0xffff); + return; +//#ifndef __GP32__ + case CMemory::MAP_C4: +#ifdef VAR_CYCLES + CPU.MemSpeed = SLOW_ONE_CYCLE; + CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; +#endif + CPU.PCBase = Memory.C4RAM - 0x6000; + CPU.PC = CPU.PCBase + (Address & 0xffff); + return; +//#endif + case CMemory::MAP_DEBUG: +#ifdef DEBUGGER + printf ("SBP %06x\n", Address); +#endif + + default: + case CMemory::MAP_NONE: +#ifdef VAR_CYCLES + CPU.MemSpeed = SLOW_ONE_CYCLE; + CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; +#endif +#ifdef DEBUGGER + printf ("SBP %06x\n", Address); +#endif + CPU.PCBase = Memory.SRAM; + CPU.PC = Memory.SRAM + (Address & 0xffff); + return; + } +} +#endif + + diff --git a/src/gfx.cpp b/src/gfx.cpp new file mode 100644 index 0000000..acb1294 --- /dev/null +++ b/src/gfx.cpp @@ -0,0 +1,3774 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" + +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" +#include "cheats.h" +#include +#include "asmmemfuncs.h" +uint32 TileBlank; + +const int tx_table[16] = { +// t1 = 16, t2 = 0 + // FLIP = 0x00 + 16 + 0, // 0x00 + 16 + 1, // 0x01 + + // FLIP = 0x01 + 16 + 1 - 0, // 0x02 + 16 + 1 - 1, // 0x03 + + // FLIP = 0x02 + 0 + 0, // 0x04 + 0 + 1, // 0x05 + + // FLIP = 0x03 + 0 + 1 - 0, // 0x06 + 0 + 1 - 1, // 0x07 + +// t1 = 0, t2 = 16 + // FLIP = 0x00 + 0 + 0, // 0x08 + 0 + 1, // 0x09 + + // FLIP = 0x01 + 0 + 1 - 0, // 0x0A + 0 + 1 - 1, // 0x0B + + // FLIP = 0x02 + 16 + 0, // 0x0C + 16 + 1, // 0x0D + + // FLIP = 0x03 + 16 + 1 - 0, // 0x0E + 16 + 1 - 1 // 0x0F +}; + +#define M7 19 +#define M8 19 + +void ComputeClipWindows (); +static void S9xDisplayFrameRate (); +static void S9xDisplayString (const char *string); + +extern uint8 BitShifts[8][4]; +extern uint8 TileShifts[8][4]; +extern uint8 PaletteShifts[8][4]; +extern uint8 PaletteMasks[8][4]; +extern uint8 Depths[8][4]; +extern uint8 BGSizes [2]; + +extern NormalTileRenderer DrawTilePtr; +extern ClippedTileRenderer DrawClippedTilePtr; +extern NormalTileRenderer DrawHiResTilePtr; +extern ClippedTileRenderer DrawHiResClippedTilePtr; +extern LargePixelRenderer DrawLargePixelPtr; + +extern struct SBG BG; + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; + +extern uint8 Mode7Depths [2]; + +#define CLIP_10_BIT_SIGNED(a) \ + ((a)%1023) +#define ON_MAIN(N) (GFX.r212c & (1 << (N))) + +#define SUB_OR_ADD(N) \ +(GFX.r2131 & (1 << (N))) + +#define ON_SUB(N) \ +((GFX.r2130 & 0x30) != 0x30 && \ + (GFX.r2130 & 2) && \ + (GFX.r212d & (1 << N))) + +#define ANYTHING_ON_SUB \ +((GFX.r2130 & 0x30) != 0x30 && \ + (GFX.r2130 & 2) && \ + (GFX.r212d & 0x1f)) + +#define ADD_OR_SUB_ON_ANYTHING \ +(GFX.r2131 & 0x3f) + +#define BLACK BUILD_PIXEL(0,0,0) + +void DrawTile (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTilex2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTilex2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTilex2x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTilex2x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawLargePixel (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawTile16_OBJ (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTile16x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTile16x2x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16x2x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawLargePixel16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawTile16Add (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16Add1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16Sub (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16Sub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16FixedSub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16FixedSub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawHiResClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawHiResTile16 (uint32 Tile, uint32 Offset, + uint32 StartLine, uint32 LineCount); + +bool8_32 S9xGraphicsInit () +{ + register uint32 PixelOdd = 1; + register uint32 PixelEven = 2; + +#ifdef GFX_MULTI_FORMAT + if (GFX.BuildPixel == NULL) + S9xSetRenderPixelFormat (RGB565); +#endif + + for (uint8 bitshift = 0; bitshift < 4; bitshift++) + { + for (register int i = 0; i < 16; i++) + { + register uint32 h = 0; + register uint32 l = 0; + +#if defined(LSB_FIRST) + if (i & 8) + h |= PixelOdd; + if (i & 4) + h |= PixelOdd << 8; + if (i & 2) + h |= PixelOdd << 16; + if (i & 1) + h |= PixelOdd << 24; + if (i & 8) + l |= PixelOdd; + if (i & 4) + l |= PixelOdd << 8; + if (i & 2) + l |= PixelOdd << 16; + if (i & 1) + l |= PixelOdd << 24; +#else + if (i & 8) + h |= (PixelOdd << 24); + if (i & 4) + h |= (PixelOdd << 16); + if (i & 2) + h |= (PixelOdd << 8); + if (i & 1) + h |= PixelOdd; + if (i & 8) + l |= (PixelOdd << 24); + if (i & 4) + l |= (PixelOdd << 16); + if (i & 2) + l |= (PixelOdd << 8); + if (i & 1) + l |= PixelOdd; +#endif + + odd_high[bitshift][i] = h; + odd_low[bitshift][i] = l; + h = l = 0; + +#if defined(LSB_FIRST) + if (i & 8) + h |= PixelEven; + if (i & 4) + h |= PixelEven << 8; + if (i & 2) + h |= PixelEven << 16; + if (i & 1) + h |= PixelEven << 24; + if (i & 8) + l |= PixelEven; + if (i & 4) + l |= PixelEven << 8; + if (i & 2) + l |= PixelEven << 16; + if (i & 1) + l |= PixelEven << 24; +#else + if (i & 8) + h |= (PixelEven << 24); + if (i & 4) + h |= (PixelEven << 16); + if (i & 2) + h |= (PixelEven << 8); + if (i & 1) + h |= PixelEven; + if (i & 8) + l |= (PixelEven << 24); + if (i & 4) + l |= (PixelEven << 16); + if (i & 2) + l |= (PixelEven << 8); + if (i & 1) + l |= PixelEven; +#endif + + even_high[bitshift][i] = h; + even_low[bitshift][i] = l; + } + PixelEven <<= 2; + PixelOdd <<= 2; + } + + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; + GFX.DepthDelta = GFX.SubZBuffer - GFX.ZBuffer; + //GFX.InfoStringTimeout = 0; + //GFX.InfoString = NULL; + + PPU.BG_Forced = 0; + IPPU.OBJChanged = TRUE; + + IPPU.DirectColourMapsNeedRebuild = TRUE; + DrawTilePtr = DrawTile16; + DrawClippedTilePtr = DrawClippedTile16; + DrawLargePixelPtr = DrawLargePixel16; + DrawHiResTilePtr= DrawHiResTile16; + DrawHiResClippedTilePtr = DrawHiResClippedTile16; + S9xFixColourBrightness (); + + if (!(GFX.X2 = (uint16 *) malloc (sizeof (uint16) * 0x10000))) + return (FALSE); + + if (!(GFX.ZERO_OR_X2 = (uint16 *) malloc (sizeof (uint16) * 0x10000)) || + !(GFX.ZERO = (uint16 *) malloc (sizeof (uint16) * 0x10000))) + { + if (GFX.ZERO_OR_X2) + { + free ((char *) GFX.ZERO_OR_X2); + GFX.ZERO_OR_X2 = NULL; + } + if (GFX.X2) + { + free ((char *) GFX.X2); + GFX.X2 = NULL; + } + return (FALSE); + } + uint32 r, g, b; + + // Build a lookup table that multiplies a packed RGB value by 2 with + // saturation. + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r << 1; + if (r2 > MAX_RED) + r2 = MAX_RED; + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g << 1; + if (g2 > MAX_GREEN) + g2 = MAX_GREEN; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b << 1; + if (b2 > MAX_BLUE) + b2 = MAX_BLUE; + GFX.X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } + ZeroMemory (GFX.ZERO, 0x10000 * sizeof (uint16)); + ZeroMemory (GFX.ZERO_OR_X2, 0x10000 * sizeof (uint16)); + // Build a lookup table that if the top bit of the color value is zero + // then the value is zero, otherwise multiply the value by 2. Used by + // the color subtraction code. + +#if defined(OLD_COLOUR_BLENDING) + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 = (r2 << 1) & MAX_RED; + + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 = (g2 << 1) & MAX_GREEN; + + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 = (b2 << 1) & MAX_BLUE; + + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } +#else + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 = (r2 << 1) & MAX_RED; + + if (r2 == 0) + r2 = 1; + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 = (g2 << 1) & MAX_GREEN; + + if (g2 == 0) + g2 = 1; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 = (b2 << 1) & MAX_BLUE; + + if (b2 == 0) + b2 = 1; + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } +#endif + + // Build a lookup table that if the top bit of the color value is zero + // then the value is zero, otherwise its just the value. + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 &= ~0x10; + + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 &= ~GREEN_HI_BIT; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 &= ~0x10; + + GFX.ZERO [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } + + return (TRUE); +} + +void S9xGraphicsDeinit (void) +{ + // Free any memory allocated in S9xGraphicsInit + if (GFX.X2) + { + free ((char *) GFX.X2); + GFX.X2 = NULL; + } + if (GFX.ZERO_OR_X2) + { + free ((char *) GFX.ZERO_OR_X2); + GFX.ZERO_OR_X2 = NULL; + } + if (GFX.ZERO) + { + free ((char *) GFX.ZERO); + GFX.ZERO = NULL; + } +} + +void S9xBuildDirectColourMaps () +{ + for (uint32 p = 0; p < 8; p++) + { + for (uint32 c = 0; c < 256; c++) + { +// XXX: Brightness + DirectColourMaps [p][c] = BUILD_PIXEL (((c & 7) << 2) | ((p & 1) << 1), + ((c & 0x38) >> 1) | (p & 2), + ((c & 0xc0) >> 3) | (p & 4)); + } + } + IPPU.DirectColourMapsNeedRebuild = FALSE; +} + +void S9xStartScreenRefresh () +{ + if (IPPU.RenderThisFrame) + { +#ifndef _SNESPPC + if (!S9xInitUpdate ()) + { + IPPU.RenderThisFrame = FALSE; + return; + } +#endif + IPPU.RenderedFramesCount++; + IPPU.PreviousLine = IPPU.CurrentLine = 0; + IPPU.MaxBrightness = PPU.Brightness; + IPPU.LatchedBlanking = PPU.ForcedBlanking; + IPPU.LatchedInterlace = (Memory.FillRAM[0x2133] & 1); + IPPU.RenderedScreenWidth = 256; + IPPU.RenderedScreenHeight = PPU.ScreenHeight; + IPPU.DoubleWidthPixels = FALSE; + + PPU.RecomputeClipWindows = TRUE; + GFX.DepthDelta = GFX.SubZBuffer - GFX.ZBuffer; + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; + } + if (++IPPU.FrameCount % Memory.ROMFramesPerSecond == 0) + { + IPPU.DisplayedRenderedFrameCount = IPPU.RenderedFramesCount; + IPPU.RenderedFramesCount = 0; + IPPU.FrameCount = 0; + } +} + +void RenderLine (uint8 C) +{ + if (IPPU.RenderThisFrame) + { + + LineData[C].BG[0].VOffset = PPU.BG[0].VOffset + 1; + LineData[C].BG[0].HOffset = PPU.BG[0].HOffset; + LineData[C].BG[1].VOffset = PPU.BG[1].VOffset + 1; + LineData[C].BG[1].HOffset = PPU.BG[1].HOffset; + + if (PPU.BGMode == 7) + { + struct SLineMatrixData *p = &LineMatrixData [C]; + p->MatrixA = PPU.MatrixA; + p->MatrixB = PPU.MatrixB; + p->MatrixC = PPU.MatrixC; + p->MatrixD = PPU.MatrixD; + p->CentreX = PPU.CentreX; + p->CentreY = PPU.CentreY; + } + else + { + if (Settings.StarfoxHack && PPU.BG[2].VOffset == 0 && + PPU.BG[2].HOffset == 0xe000) + { + LineData[C].BG[2].VOffset = 0xe1; + LineData[C].BG[2].HOffset = 0; + } + else + { + LineData[C].BG[2].VOffset = PPU.BG[2].VOffset + 1; + LineData[C].BG[2].HOffset = PPU.BG[2].HOffset; + LineData[C].BG[3].VOffset = PPU.BG[3].VOffset + 1; + LineData[C].BG[3].HOffset = PPU.BG[3].HOffset; + } + + } + IPPU.CurrentLine = C + 1; + } +} + + +void S9xEndScreenRefresh() +{ + IPPU.HDMAStarted = FALSE; + +//RC + if (IPPU.RenderThisFrame) + { + FLUSH_REDRAW (); + if (IPPU.ColorsChanged) + { + IPPU.ColorsChanged = FALSE; + } + + + S9xDeinitUpdate (IPPU.RenderedScreenWidth, IPPU.RenderedScreenHeight, + 1); + } +#ifndef RC_OPTIMIZED + S9xApplyCheats (); +#endif + + +#ifdef DEBUGGER + if (CPU.Flags & FRAME_ADVANCE_FLAG) + { + if (ICPU.FrameAdvanceCount) + { + ICPU.FrameAdvanceCount--; + IPPU.RenderThisFrame = TRUE; + IPPU.FrameSkip = 0; + } + else + { + CPU.Flags &= ~FRAME_ADVANCE_FLAG; + CPU.Flags |= DEBUG_MODE_FLAG; + } + } +#endif + +/* + if (CPU.SRAMModified) + { + if (!CPU.AutoSaveTimer) + { + if (!(CPU.AutoSaveTimer = Settings.AutoSaveDelay * Memory.ROMFramesPerSecond)) + CPU.SRAMModified = FALSE; + } + else + { + if (!--CPU.AutoSaveTimer) + { + S9xAutoSaveSRAM (); + CPU.SRAMModified = FALSE; + } + } + } +*/ +} + +void S9xSetInfoString (const char *string) +{ + } + +INLINE void SelectTileRenderer (bool8_32 normal) +{ + if (normal) + { + DrawTilePtr = DrawTile16; + DrawClippedTilePtr = DrawClippedTile16; + DrawLargePixelPtr = DrawLargePixel16; + } + else + { + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + if (GFX.r2130 & 2) + { + DrawTilePtr = DrawTile16Sub1_2; + DrawClippedTilePtr = DrawClippedTile16Sub1_2; + } + else + { + // Fixed colour substraction + DrawTilePtr = DrawTile16FixedSub1_2; + DrawClippedTilePtr = DrawClippedTile16FixedSub1_2; + } + DrawLargePixelPtr = DrawLargePixel16Sub1_2; + } + else + { + DrawTilePtr = DrawTile16Sub; + DrawClippedTilePtr = DrawClippedTile16Sub; + DrawLargePixelPtr = DrawLargePixel16Sub; + } + } + else + { + if (GFX.r2131 & 0x40) + { + if (GFX.r2130 & 2) + { + DrawTilePtr = DrawTile16Add1_2; + DrawClippedTilePtr = DrawClippedTile16Add1_2; + } + else + { + // Fixed colour addition + DrawTilePtr = DrawTile16FixedAdd1_2; + DrawClippedTilePtr = DrawClippedTile16FixedAdd1_2; + } + DrawLargePixelPtr = DrawLargePixel16Add1_2; + } + else + { + DrawTilePtr = DrawTile16Add; + DrawClippedTilePtr = DrawClippedTile16Add; + DrawLargePixelPtr = DrawLargePixel16Add; + } + } + } +} + +void S9xSetupOBJ () +{ + int SmallSize; + int LargeSize; + + switch (PPU.OBJSizeSelect) + { + case 0: + SmallSize = 8; + LargeSize = 16; + break; + case 1: + SmallSize = 8; + LargeSize = 32; + break; + case 2: + SmallSize = 8; + LargeSize = 64; + break; + case 3: + SmallSize = 16; + LargeSize = 32; + break; + case 4: + SmallSize = 16; + LargeSize = 64; + break; + case 5: + default: + SmallSize = 32; + LargeSize = 64; + break; + } + + int C = 0; + + int FirstSprite = PPU.FirstSprite & 0x7f; + int S = FirstSprite; + do + { + int Size; + if (PPU.OBJ [S].Size) + Size = LargeSize; + else + Size = SmallSize; + + long VPos = PPU.OBJ [S].VPos; + + if (VPos >= PPU.ScreenHeight) + VPos -= 256; + if (PPU.OBJ [S].HPos < 256 && PPU.OBJ [S].HPos > -Size && + VPos < PPU.ScreenHeight && VPos > -Size) + { + GFX.OBJList [C++] = S; + GFX.Sizes[S] = Size; + GFX.VPositions[S] = VPos; + } + S = (S + 1) & 0x7f; + } while (S != FirstSprite); + + // Terminate the list + GFX.OBJList [C] = -1; + IPPU.OBJChanged = FALSE; +} + +void DrawOBJS (bool8_32 OnMain = FALSE, uint8 D = 0) +{ + uint32 O; + uint32 BaseTile, Tile; + + CHECK_SOUND(); + + BG.BitShift = 4; + BG.TileShift = 5; + BG.TileAddress = PPU.OBJNameBase; + BG.StartPalette = 128; + BG.PaletteShift = 4; + BG.PaletteMask = 7; + BG.Buffer = IPPU.TileCache [TILE_4BIT]; + BG.Buffered = IPPU.TileCached [TILE_4BIT]; + BG.NameSelect = PPU.OBJNameSelect; + BG.DirectColourMode = FALSE; + + GFX.Z1 = D + 2; + + if ( DrawTilePtr == DrawTile16 ){ + DrawTilePtr = DrawTile16_OBJ; + } + int I = 0; + for (int S = GFX.OBJList [I++]; S >= 0; S = GFX.OBJList [I++]) + { + int VPos = GFX.VPositions [S]; + int Size = GFX.Sizes[S]; + int TileInc = 1; + int Offset; + + if (VPos + Size <= (int) GFX.StartY || VPos > (int) GFX.EndY) + continue; + + if (OnMain && SUB_OR_ADD(4)) + { + SelectTileRenderer (!GFX.Pseudo && PPU.OBJ [S].Palette < 4); + if ( DrawTilePtr == DrawTile16 ){ + DrawTilePtr = DrawTile16_OBJ; + } + } + + BaseTile = PPU.OBJ[S].Name | (PPU.OBJ[S].Palette << 10); + + if (PPU.OBJ[S].HFlip) + { + BaseTile += ((Size >> 3) - 1) | H_FLIP; + TileInc = -1; + } + if (PPU.OBJ[S].VFlip) + BaseTile |= V_FLIP; + + int clipcount = GFX.pCurrentClip->Count [4]; + if (!clipcount) + clipcount = 1; + + GFX.Z2 = (PPU.OBJ[S].Priority + 1) * 4 + D; + + for (int clip = 0; clip < clipcount; clip++) + { + int Left; + int Right; + if (!GFX.pCurrentClip->Count [4]) + { + Left = 0; + Right = 256; + } + else + { + Left = GFX.pCurrentClip->Left [clip][4]; + Right = GFX.pCurrentClip->Right [clip][4]; + } + + if (Right <= Left || PPU.OBJ[S].HPos + Size <= Left || + PPU.OBJ[S].HPos >= Right) + continue; + + for (int Y = 0; Y < Size; Y += 8) + { + if (VPos + Y + 7 >= (int) GFX.StartY && VPos + Y <= (int) GFX.EndY) + { + int StartLine; + int TileLine; + int LineCount; + int Last; + + if ((StartLine = VPos + Y) < (int) GFX.StartY) + { + StartLine = GFX.StartY - StartLine; + LineCount = 8 - StartLine; + } + else + { + StartLine = 0; + LineCount = 8; + } + if ((Last = VPos + Y + 7 - GFX.EndY) > 0) + if ((LineCount -= Last) <= 0) + break; + + TileLine = StartLine << 3; + O = (VPos + Y + StartLine) * GFX_PPL; + if (!PPU.OBJ[S].VFlip) + Tile = BaseTile + (Y << 1); + else + Tile = BaseTile + ((Size - Y - 8) << 1); + + int Middle = Size >> 3; + if (PPU.OBJ[S].HPos < Left) + { + Tile += ((Left - PPU.OBJ[S].HPos) >> 3) * TileInc; + Middle -= (Left - PPU.OBJ[S].HPos) >> 3; + O += Left * GFX_PIXSIZE; + if ((Offset = (Left - PPU.OBJ[S].HPos) & 7)) + { + O -= Offset * GFX_PIXSIZE; + int W = 8 - Offset; + int Width = Right - Left; + if (W > Width) + W = Width; + (*DrawClippedTilePtr) (Tile, O, Offset, W, + TileLine, LineCount); + + if (W >= Width) + continue; + Tile += TileInc; + Middle--; + O += 8 * GFX_PIXSIZE; + } + } + else + O += PPU.OBJ[S].HPos * GFX_PIXSIZE; + + if (PPU.OBJ[S].HPos + Size >= Right) + { + Middle -= ((PPU.OBJ[S].HPos + Size + 7) - + Right) >> 3; + Offset = (Right - (PPU.OBJ[S].HPos + Size)) & 7; + } + else + Offset = 0; + + for (int X = 0; X < Middle; X++, O += 8 * GFX_PIXSIZE, + Tile += TileInc) + { + (*DrawTilePtr) (Tile, O, TileLine, LineCount); + } + if (Offset) + { + (*DrawClippedTilePtr) (Tile, O, 0, Offset, + TileLine, LineCount); + } + } + } + } + } +} + +void DrawBackgroundMosaic (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ + CHECK_SOUND(); + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint8 depths [2] = {Z1, Z2}; + + if (BGMode == 0) + BG.StartPalette = bg << 5; + else + BG.StartPalette = 0; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(((uint8*)SC1-Memory.VRAM)>=0x10000) + SC1-=0x08000; + + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + uint32 Lines; + uint32 OffsetMask; + uint32 OffsetShift; + + if (BG.TileSize == 16) + { + OffsetMask = 0x3ff; + OffsetShift = 4; + } + else + { + OffsetMask = 0x1ff; + OffsetShift = 3; + } + + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines) + { + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + uint32 MosaicOffset = Y % PPU.Mosaic; + + for (Lines = 1; Lines < PPU.Mosaic - MosaicOffset; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + uint32 MosaicLine = VOffset + Y - MosaicOffset; + + if (Y + Lines > GFX.EndY) + Lines = GFX.EndY + 1 - Y; + uint32 VirtAlign = (MosaicLine & 7) << 3; + + uint16 *b1; + uint16 *b2; + + uint32 ScreenLine = MosaicLine >> OffsetShift; + uint32 Rem16 = MosaicLine & 15; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + uint16 *t; + uint32 Left = 0; + uint32 Right = 256; + + uint32 ClipCount = GFX.pCurrentClip->Count [bg]; + uint32 HPos = HOffset; + uint32 PixWidth = PPU.Mosaic; + + if (!ClipCount) + ClipCount = 1; + + for (uint32 clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [bg]) + { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + uint32 r = Left % PPU.Mosaic; + HPos = HOffset + Left; + PixWidth = PPU.Mosaic - r; + } + uint32 s = Y * GFX_PPL + Left * GFX_PIXSIZE; + for (uint32 x = Left; x < Right; x += PixWidth, + s += PixWidth * GFX_PIXSIZE, + HPos += PixWidth, PixWidth = PPU.Mosaic) + { + uint32 Quot = (HPos & OffsetMask) >> 3; + + if (x + PixWidth >= Right) + PixWidth = Right - x; + + if (BG.TileSize == 8) + { + if (Quot > 31) + t = b2 + (Quot & 0x1f); + else + t = b1 + Quot; + } + else + { + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + } + + Tile = READ_2BYTES (t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + // Draw tile... + if (BG.TileSize != 8) + { + if (Tile & H_FLIP) + { + // Horizontal flip, but what about vertical flip ? + if (Tile & V_FLIP) + { + // Both horzontal & vertical flip + if (Rem16 < 8) + { + (*DrawLargePixelPtr) (Tile + 17 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + 1 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + else + { + // Horizontal flip only + if (Rem16 > 7) + { + (*DrawLargePixelPtr) (Tile + 17 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + 1 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } + else + { + // No horizontal flip, but is there a vertical flip ? + if (Tile & V_FLIP) + { + // Vertical flip only + if (Rem16 < 8) + { + (*DrawLargePixelPtr) (Tile + 16 + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + else + { + // Normal unflipped + if (Rem16 > 7) + { + (*DrawLargePixelPtr) (Tile + 16 + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } + } + else + (*DrawLargePixelPtr) (Tile, s, HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } +} + +void DrawBackgroundOffset (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ + CHECK_SOUND(); + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint16 *BPS0; + uint16 *BPS1; + uint16 *BPS2; + uint16 *BPS3; + uint32 Width; + int VOffsetOffset = BGMode == 4 ? 0 : 32; + uint8 depths [2] = {Z1, Z2}; + + BG.StartPalette = 0; + + BPS0 = (uint16 *) &Memory.VRAM[PPU.BG[2].SCBase << 1]; + + if (PPU.BG[2].SCSize & 1) + BPS1 = BPS0 + 1024; + else + BPS1 = BPS0; + + if (PPU.BG[2].SCSize & 2) + BPS2 = BPS1 + 1024; + else + BPS2 = BPS0; + + if (PPU.BG[2].SCSize & 1) + BPS3 = BPS2 + 1024; + else + BPS3 = BPS2; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(((uint8*)SC1-Memory.VRAM)>=0x10000) + SC1-=0x08000; + + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + static const int Lines = 1; + int OffsetMask; + int OffsetShift; + int OffsetEnableMask = 1 << (bg + 13); + + if (BG.TileSize == 16) + { + OffsetMask = 0x3ff; + OffsetShift = 4; + } + else + { + OffsetMask = 0x1ff; + OffsetShift = 3; + } + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y++) + { + uint32 VOff = LineData [Y].BG[2].VOffset - 1; + uint32 HOff = LineData [Y].BG[2].HOffset; + int VirtAlign; + int ScreenLine = VOff >> 3; + uint16 *s0; + uint16 *s1; + uint16 *s2; + + if (ScreenLine & 0x20) + s1 = BPS2, s2 = BPS3; + else + s1 = BPS0, s2 = BPS1; + + s1 += (ScreenLine & 0x1f) << 5; + s2 += (ScreenLine & 0x1f) << 5; + + if(BGMode != 4) + { + if((ScreenLine & 0x1f) == 0x1f) + { + if(ScreenLine & 0x20) + VOffsetOffset = BPS0 - BPS2 - 0x1f*32; + else + VOffsetOffset = BPS2 - BPS0 - 0x1f*32; + } + else + { + VOffsetOffset = 32; + } + } + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + + for (int clip = 0; clip < clipcount; clip++) + { + uint32 Left; + uint32 Right; + + if (!GFX.pCurrentClip->Count [bg]) + { + Left = 0; + Right = 256; + } + else + { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) + continue; + } + + uint32 VOffset; + uint32 HOffset; + uint32 LineHOffset=LineData [Y].BG[bg].HOffset; + uint32 Offset; + uint32 HPos; + uint32 Quot; + uint32 Count; + uint16 *t; + uint32 Quot2; + uint32 VCellOffset; + uint32 HCellOffset; + uint16 *b1; + uint16 *b2; + uint32 TotalCount = 0; + uint32 MaxCount = 8; + + uint32 s = Left * GFX_PIXSIZE + Y * GFX_PPL; + bool8_32 left_hand_edge = (Left == 0); + Width = Right - Left; + + if (Left & 7) + MaxCount = 8 - (Left & 7); + + while (Left < Right) + { + if (left_hand_edge) + { + // The SNES offset-per-tile background mode has a + // hardware limitation that the offsets cannot be set + // for the tile at the left-hand edge of the screen. + VOffset = LineData [Y].BG[bg].VOffset; + HOffset = LineHOffset; + left_hand_edge = FALSE; + } + else + { + // All subsequent offset tile data is shifted left by one, + // hence the - 1 below. + Quot2 = ((HOff + Left - 1) & OffsetMask) >> 3; + + if (Quot2 > 31) + s0 = s2 + (Quot2 & 0x1f); + else + s0 = s1 + Quot2; + + HCellOffset = READ_2BYTES (s0); + + if (BGMode == 4) + { + VOffset = LineData [Y].BG[bg].VOffset; + HOffset=LineHOffset; + if ((HCellOffset & OffsetEnableMask)) + { + if (HCellOffset & 0x8000) + VOffset = HCellOffset + 1; + else + HOffset = HCellOffset; + } + } + else + { + VCellOffset = READ_2BYTES (s0 + VOffsetOffset); + if ((VCellOffset & OffsetEnableMask)) + VOffset = VCellOffset + 1; + else + VOffset = LineData [Y].BG[bg].VOffset; + + if ((HCellOffset & OffsetEnableMask)) + HOffset = (HCellOffset & ~7)|(LineHOffset&7); + else + HOffset=LineHOffset; + } + } + VirtAlign = ((Y + VOffset) & 7) << 3; + ScreenLine = (VOffset + Y) >> OffsetShift; + + int tx_index; + tx_index = ( ((VOffset + Y) & 15) <= 7 ) << 3; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + HPos = (HOffset + Left) & OffsetMask; + + Quot = HPos >> 3; + + if (BG.TileSize == 8) + { + if (Quot > 31) + t = b2 + (Quot & 0x1f); + else + t = b1 + Quot; + } + else + { + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + } + + if (MaxCount + TotalCount > Width) + MaxCount = Width - TotalCount; + + Offset = HPos & 7; + + Count = 8 - Offset; + if (Count > MaxCount) + Count = MaxCount; + + s -= Offset * GFX_PIXSIZE; + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + if (Tile != TileBlank) + if (BG.TileSize == 8) + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + else + { + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + } + + Left += Count; + TotalCount += Count; + s += (Offset + Count) * GFX_PIXSIZE; + MaxCount = 8; + } + } + } +} + +void DrawBackgroundMode5 (uint32 /* BGMODE */, uint32 bg, uint8 Z1, uint8 Z2) +{ + CHECK_SOUND(); + + uint8 depths [2] = {Z1, Z2}; + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 Width; + + BG.StartPalette = 0; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if ((PPU.BG[bg].SCSize & 1)) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if((SC1-(unsigned short*)Memory.VRAM)>0x10000) + SC1=(uint16*)&Memory.VRAM[(((uint8*)SC1)-Memory.VRAM)%0x10000]; + + if ((PPU.BG[bg].SCSize & 2)) + SC2 = SC1 + 1024; + else SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + if ((PPU.BG[bg].SCSize & 1)) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + int Lines; + int VOffsetMask; + int VOffsetShift; + + if (BG.TileSize == 16) + { + VOffsetMask = 0x3ff; + VOffsetShift = 4; + } + else + { + VOffsetMask = 0x1ff; + VOffsetShift = 3; + } + int endy = GFX.EndY; + + for (int Y = GFX.StartY; Y <= endy; Y += Lines) + { + int y = Y; + uint32 VOffset = LineData [y].BG[bg].VOffset; + uint32 HOffset = LineData [y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + for (Lines = 1; Lines < 8 - VirtAlign; Lines++) + if ((VOffset != LineData [y + Lines].BG[bg].VOffset) || + (HOffset != LineData [y + Lines].BG[bg].HOffset)) + break; + + HOffset <<= 1; + if (Y + Lines > endy) + Lines = endy + 1 - Y; + + int ScreenLine = (VOffset + Y) >> VOffsetShift; + int t1; + int t2; + if (((VOffset + Y) & 15) > 7) + { + t1 = 16; + t2 = 0; + } + else + { + t1 = 0; + t2 = 16; + } + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + for (int clip = 0; clip < clipcount; clip++) + { + int Left; + int Right; + + if (!GFX.pCurrentClip->Count [bg]) + { + Left = 0; + Right = 512; + } + else + { + Left = GFX.pCurrentClip->Left [clip][bg] * 2; + Right = GFX.pCurrentClip->Right [clip][bg] * 2; + + if (Right <= Left) + continue; + } + + uint32 s = (Left>>1) * GFX_PIXSIZE + Y * GFX_PPL; + uint32 HPos = (HOffset + Left * GFX_PIXSIZE) & 0x3ff; + + uint32 Quot = HPos >> 3; + uint32 Count = 0; + + uint16 *t; + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + + Width = Right - Left; + // Left hand edge clipped tile + if (HPos & 7) + { + int Offset = (HPos & 7); + Count = 8 - Offset; + if (Count > Width) + Count = Width; + s -= (Offset>>1); + Tile = READ_2BYTES (t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResClippedTilePtr) (Tile + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + t1 + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResClippedTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResClippedTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResClippedTilePtr) (Tile + t2 + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + + t += Quot & 1; + if (Quot == 63) + t = b2; + else if (Quot == 127) + t = b1; + Quot++; + s += 4; + } + + // Middle, unclipped tiles + Count = Width - Count; + int Middle = Count >> 3; + Count &= 7; + for (int C = Middle; C > 0; s += 4, Quot++, C--) + { + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResTilePtr) (Tile + (Quot & 1), + s, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResTilePtr) (Tile + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResTilePtr) (Tile + t1 + (Quot & 1), + s, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResTilePtr) (Tile + t2 + (Quot & 1), + s, VirtAlign, Lines); + } + } + + t += Quot & 1; + if (Quot == 63) + t = b2; + else + if (Quot == 127) + t = b1; + } + + // Right-hand edge clipped tiles + if (Count) + { + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResClippedTilePtr) (Tile + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + t1 + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResClippedTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResClippedTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResClippedTilePtr) (Tile + t2 + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + } + } + } +} + +void DrawBackground_8 (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 Width; + uint8 depths [2] = {Z1, Z2}; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(SC1>=(unsigned short*)(Memory.VRAM+0x10000)) + SC1=(uint16*)&Memory.VRAM[((uint8*)SC1-&Memory.VRAM[0])%0x10000]; + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + int Lines; + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines){ + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + for (Lines = 1; Lines < 8 - VirtAlign; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + if (Y + Lines > GFX.EndY) + Lines = GFX.EndY + 1 - Y; + + VirtAlign <<= 3; + + uint32 ScreenLine = (VOffset + Y) >> 3; + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + for (int clip = 0; clip < clipcount; clip++){ + uint32 Left; + uint32 Right; + + if (!GFX.pCurrentClip->Count [bg]){ + Left = 0; + Right = 256; + } else { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) + continue; + } + + uint32 s = Left + Y * GFX_PPL; + uint32 HPos = (HOffset + Left) & 0x1ff; + uint32 Quot = HPos >> 3; + uint32 Count = 0; + uint16 *t; + + if (Quot > 31) t = b2 + (Quot & 0x1f); else t = b1 + Quot; + + Width = Right - Left; + + // Left hand edge clipped tile + if (HPos & 7){ + uint32 Offset = (HPos & 7); + Count = 8 - Offset; + if (Count > Width) Count = Width; + s -= Offset; + Tile = READ_2BYTES(t); + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + t++; + if (Quot == 31) t = b2; else if (Quot == 63) t = b1; + Quot++; + s += 8; + } + + // Middle, unclipped tiles + Count = Width - Count; + for (int C = Count >> 3; C > 0; s += 8, Quot++, C--){ + Tile = READ_2BYTES(t); + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawTilePtr) (Tile, s, VirtAlign, Lines); + } + + t++; + if (Quot == 31) t = b2; else if (Quot == 63) t = b1; + } + + // Right-hand edge clipped tiles + if (Count){ + Tile = READ_2BYTES(t); + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, 0, Count & 7, VirtAlign, Lines); + } + } + } + } + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; +} + +void DrawBackground_16 (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 Width; + uint8 depths [2] = {Z1, Z2}; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(SC1>=(unsigned short*)(Memory.VRAM+0x10000)) + SC1=(uint16*)&Memory.VRAM[((uint8*)SC1-&Memory.VRAM[0])%0x10000]; + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + int Lines; + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines){ + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + for (Lines = 1; Lines < 8 - VirtAlign; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + if (Y + Lines > GFX.EndY) + Lines = GFX.EndY + 1 - Y; + + VirtAlign <<= 3; + + uint32 ScreenLine = (VOffset + Y) >> 4; + int tx_index = ( ((VOffset + Y) & 15) <= 7 ) << 3; + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + for (int clip = 0; clip < clipcount; clip++){ + uint32 Left; + uint32 Right; + + if (!GFX.pCurrentClip->Count [bg]){ + Left = 0; + Right = 256; + } else { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) + continue; + } + + uint32 s = Left + Y * GFX_PPL; + uint32 HPos = (HOffset + Left) & 0x3ff; + uint32 Quot = HPos >> 3; + uint32 Count = 0; + uint16 *t; + + if (Quot > 63) t = b2 + ((Quot >> 1) & 0x1f); else t = b1 + (Quot >> 1); + + Width = Right - Left; + + // Left hand edge clipped tile + if (HPos & 7){ + uint32 Offset = (HPos & 7); + Count = 8 - Offset; + if (Count > Width) Count = Width; + s -= Offset; + Tile = READ_2BYTES(t); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + + t += Quot & 1; + if (Quot == 63) t = b2; else if (Quot == 127) t = b1; + Quot++; + s += 8; + } + + // Middle, unclipped tiles + Count = Width - Count; + for (int C = Count >> 3; C > 0; s += 8, Quot++, C--){ + Tile = READ_2BYTES(t); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawTilePtr) (Tile, s, VirtAlign, Lines); + } + + t += Quot & 1; + if (Quot == 63) t = b2; else if (Quot == 127) t = b1; + } + + // Right-hand edge clipped tiles + if (Count){ + Tile = READ_2BYTES(t); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, 0, Count & 7, VirtAlign, Lines); + } + } + } + } + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; +} + +inline void DrawBackground (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +//StartAnalyze(); + + BG.TileSize = BGSizes [PPU.BG[bg].BGSize]; + BG.BitShift = BitShifts[BGMode][bg]; + BG.TileShift = TileShifts[BGMode][bg]; + BG.TileAddress = PPU.BG[bg].NameBase << 1; + BG.NameSelect = 0; + BG.Buffer = IPPU.TileCache [Depths [BGMode][bg]]; + BG.Buffered = IPPU.TileCached [Depths [BGMode][bg]]; + BG.PaletteShift = PaletteShifts[BGMode][bg]; + BG.PaletteMask = PaletteMasks[BGMode][bg]; + BG.DirectColourMode = (BGMode == 3 || BGMode == 4) && bg == 0 && + (GFX.r2130 & 1); + + if ( DrawTilePtr == DrawTile16_OBJ ){ + DrawTilePtr = DrawTile16; + } + + if (PPU.BGMosaic [bg] && PPU.Mosaic > 1){ + DrawBackgroundMosaic (BGMode, bg, Z1, Z2); + return; + + } + switch (BGMode) + { + case 2: + case 4: // Used by Puzzle Bobble + DrawBackgroundOffset (BGMode, bg, Z1, Z2); + return; + + case 5: + case 6: // XXX: is also offset per tile. + DrawBackgroundMode5 (BGMode, bg, Z1, Z2); + return; + } + CHECK_SOUND(); + + if (BGMode == 0) + BG.StartPalette = bg << 5; + else BG.StartPalette = 0; + + if (BG.TileSize == 8){ + DrawBackground_8 (BGMode, bg, Z1, Z2); + } else { + DrawBackground_16 (BGMode, bg, Z1, Z2); + } +} + +#define RENDER_BACKGROUND_MODE7(FUNC) \ + CHECK_SOUND(); \ +\ + uint8 *VRAM1 = Memory.VRAM + 1; \ + if (GFX.r2130 & 1) \ + { \ + if (IPPU.DirectColourMapsNeedRebuild) \ + S9xBuildDirectColourMaps (); \ + GFX.ScreenColors = DirectColourMaps [0]; \ + } \ + else \ + GFX.ScreenColors = IPPU.ScreenColors; \ +\ + int aa, cc; \ + int dir; \ + int startx, endx; \ + uint32 Left = 0; \ + uint32 Right = 256; \ + uint32 ClipCount = GFX.pCurrentClip->Count [bg]; \ +\ + if (!ClipCount) \ + ClipCount = 1; \ +\ + Screen += GFX.StartY * GFX_PITCH; \ + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; \ +\ + for (uint32 Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, l++) \ + { \ + int yy; \ +\ + int32 HOffset = ((int32) LineData [Line].BG[0].HOffset << M7) >> M7; \ + int32 VOffset = ((int32) LineData [Line].BG[0].VOffset << M7) >> M7; \ +\ + int32 CentreX = ((int32) l->CentreX << M7) >> M7; \ + int32 CentreY = ((int32) l->CentreY << M7) >> M7; \ +\ + if (PPU.Mode7VFlip) \ + yy = 255 - (int) Line; \ + else \ + yy = Line; \ +\ + if (PPU.Mode7Repeat == 0) \ + yy += (VOffset - CentreY) % 1023; \ + else \ + yy += VOffset - CentreY; \ + int BB = l->MatrixB * yy + (CentreX << 8); \ + int DD = l->MatrixD * yy + (CentreY << 8); \ +\ + for (uint32 clip = 0; clip < ClipCount; clip++) \ + { \ + if (GFX.pCurrentClip->Count [bg]) \ + { \ + Left = GFX.pCurrentClip->Left [clip][bg]; \ + Right = GFX.pCurrentClip->Right [clip][bg]; \ + if (Right <= Left) \ + continue; \ + } \ + uint16 *p = (uint16 *) Screen + Left; \ +\ + if (PPU.Mode7HFlip) \ + { \ + startx = Right - 1; \ + endx = Left - 1; \ + dir = -1; \ + aa = -l->MatrixA; \ + cc = -l->MatrixC; \ + } \ + else \ + { \ + startx = Left; \ + endx = Right; \ + dir = 1; \ + aa = l->MatrixA; \ + cc = l->MatrixC; \ + } \ + int xx; \ + if (PPU.Mode7Repeat == 0) \ + xx = startx + (HOffset - CentreX) % 1023; \ + else \ + xx = startx + HOffset - CentreX; \ + int AA = l->MatrixA * xx; \ + int CC = l->MatrixC * xx; \ +\ + if (!PPU.Mode7Repeat) \ + { \ + for (int x = startx; x != endx; x += dir, AA += aa, CC += cc, p++) \ + { \ + register int X = ((AA + BB) >> 8) & 0x3ff; \ + register int Y = ((CC + DD) >> 8) & 0x3ff; \ + uint8 *TileData = VRAM1 + (Memory.VRAM[((Y & ~7) << 5) + ((X >> 2) & ~1)] << 7); \ + uint32 b = *(TileData + ((Y & 7) << 4) + ((X & 7) << 1)); \ + if (b) \ + { \ + *p = (FUNC); \ + } \ + } \ + } \ + else \ + { \ + for (int x = startx; x != endx; x += dir, AA += aa, CC += cc, p++) \ + { \ + int X = ((AA + BB) >> 8); \ + int Y = ((CC + DD) >> 8); \ +\ + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) \ + { \ + X &= 0x7ff; \ + Y &= 0x7ff; \ + } \ +\ + if (((X | Y) & ~0x3ff) == 0) \ + { \ + uint8 *TileData = VRAM1 + (Memory.VRAM[((Y & ~7) << 5) + ((X >> 2) & ~1)] << 7); \ + uint32 b = *(TileData + ((Y & 7) << 4) + ((X & 7) << 1)); \ + if (b) \ + { \ + *p = (FUNC); \ + } \ + } \ + else \ + { \ + if (PPU.Mode7Repeat == 3) \ + { \ + X = (x + HOffset) & 7; \ + Y = (yy + CentreY) & 7; \ + uint32 b = *(VRAM1 + ((Y & 7) << 4) + ((X & 7) << 1)); \ + if (b ) \ + { \ + *p = (FUNC); \ + } \ + } \ + } \ + } \ + } \ + } \ + } + +#define RENDER_BACKGROUND_MODE7ADDSUB(DEPTH, FUNC) \ + CHECK_SOUND(); \ +\ + uint8 *VRAM1 = Memory.VRAM + 1; \ + if (GFX.r2130 & 1) \ + { \ + if (IPPU.DirectColourMapsNeedRebuild) \ + S9xBuildDirectColourMaps (); \ + GFX.ScreenColors = DirectColourMaps [0]; \ + } \ + else \ + GFX.ScreenColors = IPPU.ScreenColors; \ +\ + int aa, cc; \ + int dir; \ + int startx, endx; \ + uint32 Left = 0; \ + uint32 Right = 256; \ + uint32 ClipCount = GFX.pCurrentClip->Count [bg]; \ +\ + if (!ClipCount) \ + ClipCount = 1; \ +\ + Screen += GFX.StartY * GFX_PITCH; \ + uint8 *Depth = GFX.DB + GFX.StartY * GFX_PPL; \ + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; \ +\ + for (uint32 Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) \ + { \ + int yy; \ +\ + int32 HOffset = ((int32) LineData [Line].BG[0].HOffset << M7) >> M7; \ + int32 VOffset = ((int32) LineData [Line].BG[0].VOffset << M7) >> M7; \ +\ + int32 CentreX = ((int32) l->CentreX << M7) >> M7; \ + int32 CentreY = ((int32) l->CentreY << M7) >> M7; \ +\ + if (PPU.Mode7VFlip) \ + yy = 255 - (int) Line; \ + else \ + yy = Line; \ +\ + if (PPU.Mode7Repeat == 0) \ + yy += (VOffset - CentreY) % 1023; \ + else \ + yy += VOffset - CentreY; \ + int BB = l->MatrixB * yy + (CentreX << 8); \ + int DD = l->MatrixD * yy + (CentreY << 8); \ +\ + for (uint32 clip = 0; clip < ClipCount; clip++) \ + { \ + if (GFX.pCurrentClip->Count [bg]) \ + { \ + Left = GFX.pCurrentClip->Left [clip][bg]; \ + Right = GFX.pCurrentClip->Right [clip][bg]; \ + if (Right <= Left) \ + continue; \ + } \ + uint16 *p = (uint16 *) Screen + Left; \ + uint8 *d = Depth + Left; \ +\ + if (PPU.Mode7HFlip) \ + { \ + startx = Right - 1; \ + endx = Left - 1; \ + dir = -1; \ + aa = -l->MatrixA; \ + cc = -l->MatrixC; \ + } \ + else \ + { \ + startx = Left; \ + endx = Right; \ + dir = 1; \ + aa = l->MatrixA; \ + cc = l->MatrixC; \ + } \ + int xx; \ + if (PPU.Mode7Repeat == 0) \ + xx = startx + (HOffset - CentreX) % 1023; \ + else \ + xx = startx + HOffset - CentreX; \ + int AA = l->MatrixA * xx; \ + int CC = l->MatrixC * xx; \ +\ + if (!PPU.Mode7Repeat) \ + { \ + for (int x = startx; x != endx; x += dir, AA += aa, CC += cc, p++, d++) \ + { \ + int X = ((AA + BB) >> 8) & 0x3ff; \ + int Y = ((CC + DD) >> 8) & 0x3ff; \ + uint8 *TileData = VRAM1 + (Memory.VRAM[((Y & ~7) << 5) + ((X >> 2) & ~1)] << 7); \ + uint32 b = *(TileData + ((Y & 7) << 4) + ((X & 7) << 1)); \ + if (DEPTH > *d && (b) ) \ + { \ + *p = (FUNC); \ + *d = DEPTH; \ + } \ + } \ + } \ + else \ + { \ + for (int x = startx; x != endx; x += dir, AA += aa, CC += cc, p++, d++) \ + { \ + int X = ((AA + BB) >> 8); \ + int Y = ((CC + DD) >> 8); \ +\ + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) \ + { \ + X &= 0x7ff; \ + Y &= 0x7ff; \ + } \ +\ + if (((X | Y) & ~0x3ff) == 0) \ + { \ + uint8 *TileData = VRAM1 + (Memory.VRAM[((Y & ~7) << 5) + ((X >> 2) & ~1)] << 7); \ + uint32 b = *(TileData + ((Y & 7) << 4) + ((X & 7) << 1)); \ + if (DEPTH > *d && (b) ) \ + { \ + *p = (FUNC); \ + *d = DEPTH; \ + } \ + } \ + else \ + { \ + if (PPU.Mode7Repeat == 3) \ + { \ + X = (x + HOffset) & 7; \ + Y = (yy + CentreY) & 7; \ + uint32 b = *(VRAM1 + ((Y & 7) << 4) + ((X & 7) << 1)); \ + if (DEPTH > *d && (b) ) \ + { \ + *p = (FUNC); \ + *d = DEPTH; \ + } \ + } \ + } \ + } \ + } \ + } \ + } + +#define RENDER_BACKGROUND_MODE7PRIO(FUNC) \ + CHECK_SOUND(); \ +\ + uint8 *VRAM1 = Memory.VRAM + 1; \ + if (GFX.r2130 & 1) \ + { \ + if (IPPU.DirectColourMapsNeedRebuild) \ + S9xBuildDirectColourMaps (); \ + GFX.ScreenColors = DirectColourMaps [0]; \ + } \ + else \ + GFX.ScreenColors = IPPU.ScreenColors; \ +\ + int aa, cc; \ + int dir; \ + int startx, endx; \ + uint32 Left = 0; \ + uint32 Right = 256; \ + uint32 ClipCount = GFX.pCurrentClip->Count [bg]; \ +\ + if (!ClipCount) \ + ClipCount = 1; \ +\ + Screen += GFX.StartY * GFX_PITCH; \ + uint8 *Depth = GFX.DB + GFX.StartY * GFX_PPL; \ + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; \ +\ + for (uint32 Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) \ + { \ + int yy; \ +\ + int32 HOffset = ((int32) LineData [Line].BG[0].HOffset << M7) >> M7; \ + int32 VOffset = ((int32) LineData [Line].BG[0].VOffset << M7) >> M7; \ +\ + int32 CentreX = ((int32) l->CentreX << M7) >> M7; \ + int32 CentreY = ((int32) l->CentreY << M7) >> M7; \ +\ + if (PPU.Mode7VFlip) \ + yy = 255 - (int) Line; \ + else \ + yy = Line; \ +\ + if (PPU.Mode7Repeat == 0) \ + yy += (VOffset - CentreY) % 1023; \ + else \ + yy += VOffset - CentreY; \ + int BB = l->MatrixB * yy + (CentreX << 8); \ + int DD = l->MatrixD * yy + (CentreY << 8); \ +\ + for (uint32 clip = 0; clip < ClipCount; clip++) \ + { \ + if (GFX.pCurrentClip->Count [bg]) \ + { \ + Left = GFX.pCurrentClip->Left [clip][bg]; \ + Right = GFX.pCurrentClip->Right [clip][bg]; \ + if (Right <= Left) \ + continue; \ + } \ + uint16 *p = (uint16 *) Screen + Left; \ + uint8 *d = Depth + Left; \ +\ + if (PPU.Mode7HFlip) \ + { \ + startx = Right - 1; \ + endx = Left - 1; \ + dir = -1; \ + aa = -l->MatrixA; \ + cc = -l->MatrixC; \ + } \ + else \ + { \ + startx = Left; \ + endx = Right; \ + dir = 1; \ + aa = l->MatrixA; \ + cc = l->MatrixC; \ + } \ + int xx; \ + if (PPU.Mode7Repeat == 0) \ + xx = startx + (HOffset - CentreX) % 1023; \ + else \ + xx = startx + HOffset - CentreX; \ + int AA = l->MatrixA * xx; \ + int CC = l->MatrixC * xx; \ +\ + if (!PPU.Mode7Repeat) \ + { \ + for (int x = startx; x != endx; x += dir, AA += aa, CC += cc, p++, d++) \ + { \ + int X = ((AA + BB) >> 8) & 0x3ff; \ + int Y = ((CC + DD) >> 8) & 0x3ff; \ + uint8 *TileData = VRAM1 + (Memory.VRAM[((Y & ~7) << 5) + ((X >> 2) & ~1)] << 7); \ + uint32 b = *(TileData + ((Y & 7) << 4) + ((X & 7) << 1)); \ + GFX.Z1 = Mode7Depths [(b & 0x80) >> 7]; \ + if (GFX.Z1 > *d && (b & 0x7f) ) \ + { \ + *p = (FUNC); \ + *d = GFX.Z1; \ + } \ + } \ + } \ + else \ + { \ + for (int x = startx; x != endx; x += dir, AA += aa, CC += cc, p++, d++) \ + { \ + int X = ((AA + BB) >> 8); \ + int Y = ((CC + DD) >> 8); \ +\ + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) \ + { \ + X &= 0x7ff; \ + Y &= 0x7ff; \ + } \ +\ + if (((X | Y) & ~0x3ff) == 0) \ + { \ + uint8 *TileData = VRAM1 + (Memory.VRAM[((Y & ~7) << 5) + ((X >> 2) & ~1)] << 7); \ + uint32 b = *(TileData + ((Y & 7) << 4) + ((X & 7) << 1)); \ + GFX.Z1 = Mode7Depths [(b & 0x80) >> 7]; \ + if (GFX.Z1 > *d && (b & 0x7f) ) \ + { \ + *p = (FUNC); \ + *d = GFX.Z1; \ + } \ + } \ + else \ + { \ + if (PPU.Mode7Repeat == 3) \ + { \ + X = (x + HOffset) & 7; \ + Y = (yy + CentreY) & 7; \ + uint32 b = *(VRAM1 + ((Y & 7) << 4) + ((X & 7) << 1)); \ + GFX.Z1 = Mode7Depths [(b & 0x80) >> 7]; \ + if (GFX.Z1 > *d && (b & 0x7f) ) \ + { \ + *p = (FUNC); \ + *d = GFX.Z1; \ + } \ + } \ + } \ + } \ + } \ + } \ + } + +void DrawBGMode7Background16New (uint8 *Screen, int bg) +{ + RENDER_BACKGROUND_MODE7 (GFX.ScreenColors [b & 0xff]); +} + +void DrawBGMode7Background16 (uint8 *Screen, int bg, int depth) +{ + RENDER_BACKGROUND_MODE7ADDSUB (depth, GFX.ScreenColors [b & 0xff]); +} + +void DrawBGMode7Background16Add (uint8 *Screen, int bg, int depth) +{ + RENDER_BACKGROUND_MODE7ADDSUB (depth, *(d + GFX.DepthDelta) ? + (*(d + GFX.DepthDelta) != 1 ? + COLOR_ADD (GFX.ScreenColors [b & 0xff], + p [GFX.Delta]) : + COLOR_ADD (GFX.ScreenColors [b & 0xff], + GFX.FixedColour)) : + GFX.ScreenColors [b & 0xff]); + +} + +void DrawBGMode7Background16Add1_2 (uint8 *Screen, int bg, int depth) +{ + RENDER_BACKGROUND_MODE7ADDSUB (depth, *(d + GFX.DepthDelta) ? + (*(d + GFX.DepthDelta) != 1 ? + COLOR_ADD1_2 (GFX.ScreenColors [b & 0xff], + p [GFX.Delta]) : + COLOR_ADD (GFX.ScreenColors [b & 0xff], + GFX.FixedColour)) : + GFX.ScreenColors [b & 0xff]); +} + +void DrawBGMode7Background16Sub (uint8 *Screen, int bg, int depth) +{ + RENDER_BACKGROUND_MODE7ADDSUB (depth, *(d + GFX.DepthDelta) ? + (*(d + GFX.DepthDelta) != 1 ? + COLOR_SUB (GFX.ScreenColors [b & 0xff], + p [GFX.Delta]) : + COLOR_SUB (GFX.ScreenColors [b & 0xff], + GFX.FixedColour)) : + GFX.ScreenColors [b & 0xff]); +} + +void DrawBGMode7Background16Sub1_2 (uint8 *Screen, int bg, int depth) +{ + RENDER_BACKGROUND_MODE7ADDSUB (depth, *(d + GFX.DepthDelta) ? + (*(d + GFX.DepthDelta) != 1 ? + COLOR_SUB1_2 (GFX.ScreenColors [b & 0xff], + p [GFX.Delta]) : + COLOR_SUB (GFX.ScreenColors [b & 0xff], + GFX.FixedColour)) : + GFX.ScreenColors [b & 0xff]); +} + +void DrawBGMode7Background16Prio (uint8 *Screen, int bg) +{ + RENDER_BACKGROUND_MODE7PRIO (GFX.ScreenColors [b & 0x7f]); +} + +void DrawBGMode7Background16AddPrio (uint8 *Screen, int bg) +{ + RENDER_BACKGROUND_MODE7PRIO (*(d + GFX.DepthDelta) ? + (*(d + GFX.DepthDelta) != 1 ? + COLOR_ADD (GFX.ScreenColors [b & 0x7f], + p [GFX.Delta]) : + COLOR_ADD (GFX.ScreenColors [b & 0x7f], + GFX.FixedColour)) : + GFX.ScreenColors [b & 0x7f]); +} + +void DrawBGMode7Background16Add1_2Prio (uint8 *Screen, int bg) +{ + RENDER_BACKGROUND_MODE7PRIO (*(d + GFX.DepthDelta) ? + (*(d + GFX.DepthDelta) != 1 ? + COLOR_ADD1_2 (GFX.ScreenColors [b & 0x7f], + p [GFX.Delta]) : + COLOR_ADD (GFX.ScreenColors [b & 0x7f], + GFX.FixedColour)) : + GFX.ScreenColors [b & 0x7f]); +} + +void DrawBGMode7Background16SubPrio (uint8 *Screen, int bg) +{ + RENDER_BACKGROUND_MODE7PRIO (*(d + GFX.DepthDelta) ? + (*(d + GFX.DepthDelta) != 1 ? + COLOR_SUB (GFX.ScreenColors [b & 0x7f], + p [GFX.Delta]) : + COLOR_SUB (GFX.ScreenColors [b & 0x7f], + GFX.FixedColour)) : + GFX.ScreenColors [b & 0x7f]); +} + +void DrawBGMode7Background16Sub1_2Prio (uint8 *Screen, int bg) +{ + RENDER_BACKGROUND_MODE7PRIO (*(d + GFX.DepthDelta) ? + (*(d + GFX.DepthDelta) != 1 ? + COLOR_SUB1_2 (GFX.ScreenColors [b & 0x7f], + p [GFX.Delta]) : + COLOR_SUB (GFX.ScreenColors [b & 0x7f], + GFX.FixedColour)) : + GFX.ScreenColors [b & 0x7f]); +} + +#define _BUILD_SETUP(F) \ +GFX.BuildPixel = BuildPixel##F; \ +GFX.BuildPixel2 = BuildPixel2##F; \ +GFX.DecomposePixel = DecomposePixel##F; \ +RED_LOW_BIT_MASK = RED_LOW_BIT_MASK_##F; \ +GREEN_LOW_BIT_MASK = GREEN_LOW_BIT_MASK_##F; \ +BLUE_LOW_BIT_MASK = BLUE_LOW_BIT_MASK_##F; \ +RED_HI_BIT_MASK = RED_HI_BIT_MASK_##F; \ +GREEN_HI_BIT_MASK = GREEN_HI_BIT_MASK_##F; \ +BLUE_HI_BIT_MASK = BLUE_HI_BIT_MASK_##F; \ +MAX_RED = MAX_RED_##F; \ +MAX_GREEN = MAX_GREEN_##F; \ +MAX_BLUE = MAX_BLUE_##F; \ +GREEN_HI_BIT = ((MAX_GREEN_##F + 1) >> 1); \ +SPARE_RGB_BIT_MASK = SPARE_RGB_BIT_MASK_##F; \ +RGB_LOW_BITS_MASK = (RED_LOW_BIT_MASK_##F | \ + GREEN_LOW_BIT_MASK_##F | \ + BLUE_LOW_BIT_MASK_##F); \ +RGB_HI_BITS_MASK = (RED_HI_BIT_MASK_##F | \ + GREEN_HI_BIT_MASK_##F | \ + BLUE_HI_BIT_MASK_##F); \ +RGB_HI_BITS_MASKx2 = ((RED_HI_BIT_MASK_##F | \ + GREEN_HI_BIT_MASK_##F | \ + BLUE_HI_BIT_MASK_##F) << 1); \ +RGB_REMOVE_LOW_BITS_MASK = ~RGB_LOW_BITS_MASK; \ +FIRST_COLOR_MASK = FIRST_COLOR_MASK_##F; \ +SECOND_COLOR_MASK = SECOND_COLOR_MASK_##F; \ +THIRD_COLOR_MASK = THIRD_COLOR_MASK_##F; \ +ALPHA_BITS_MASK = ALPHA_BITS_MASK_##F; \ +FIRST_THIRD_COLOR_MASK = FIRST_COLOR_MASK | THIRD_COLOR_MASK; \ +TWO_LOW_BITS_MASK = RGB_LOW_BITS_MASK | (RGB_LOW_BITS_MASK << 1); \ +HIGH_BITS_SHIFTED_TWO_MASK = (( (FIRST_COLOR_MASK | SECOND_COLOR_MASK | THIRD_COLOR_MASK) & \ + ~TWO_LOW_BITS_MASK ) >> 2); + +void RenderScreen (uint8 *Screen, bool8_32 sub, bool8_32 force_no_add, uint8 D) +{ + bool8_32 BG0; + bool8_32 BG1; + bool8_32 BG2; + bool8_32 BG3; + bool8_32 OB; + + GFX.S = Screen; + + if (!sub) + { + GFX.pCurrentClip = &IPPU.Clip [0]; + BG0 = ON_MAIN (0) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + BG1 = ON_MAIN (1) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + BG2 = ON_MAIN (2) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + BG3 = ON_MAIN (3) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + OB = ON_MAIN (4) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + } + else + { + GFX.pCurrentClip = &IPPU.Clip [1]; + BG0 = ON_SUB (0) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + BG1 = ON_SUB (1) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + BG2 = ON_SUB (2) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + BG3 = ON_SUB (3) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + OB = ON_SUB (4) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + } + + sub |= force_no_add; + + if (PPU.BGMode <= 1) + { + if (OB) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4)); + DrawOBJS (!sub, D); + } + if (BG0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(0)); + DrawBackground (PPU.BGMode, 0, D + 10, D + 14); + } + if (BG1) + { + SelectTileRenderer (sub || !SUB_OR_ADD(1)); + DrawBackground (PPU.BGMode, 1, D + 9, D + 13); + } + if (BG2) + { + SelectTileRenderer (sub || !SUB_OR_ADD(2)); + DrawBackground (PPU.BGMode, 2, D + 3, + PPU.BG3Priority ? D + 17 : D + 6); + } + if (BG3 && PPU.BGMode == 0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(3)); + DrawBackground (PPU.BGMode, 3, D + 2, D + 5); + } + } + else if (PPU.BGMode != 7) + { + if (OB) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4)); + DrawOBJS (!sub, D); + } + if (BG0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(0)); + DrawBackground (PPU.BGMode, 0, D + 5, D + 13); + } + if (PPU.BGMode != 6 && BG1) + { + SelectTileRenderer (sub || !SUB_OR_ADD(1)); + DrawBackground (PPU.BGMode, 1, D + 2, D + 9); + } + } + else + { + if (OB && ((SNESGameFixes.Mode7Hack && D) || !SNESGameFixes.Mode7Hack)) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4)); + DrawOBJS (!sub, D); + } + if (BG0 || ((Memory.FillRAM [0x2133] & 0x40) && BG1)) + { + int bg; + + if ((Memory.FillRAM [0x2133] & 0x40)&&BG1) + { + Mode7Depths [0] = (BG0?5:1) + D; + Mode7Depths [1] = 9 + D; + bg = 1; + if (sub || !SUB_OR_ADD(0)) + { + DrawBGMode7Background16Prio (Screen, bg); + } + else + { + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Sub1_2Prio (Screen, bg); + } + else + { + DrawBGMode7Background16SubPrio (Screen, bg); + } + } + else + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Add1_2Prio (Screen, bg); + } + else + { + DrawBGMode7Background16AddPrio (Screen, bg); + } + } + } + } + else + { + bg = 0; + if (sub || !SUB_OR_ADD(0)) + { + if (D || !SNESGameFixes.Mode7Hack) + DrawBGMode7Background16 (Screen, bg, D+5); + else + DrawBGMode7Background16New (Screen, bg); + } + else + { + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Sub1_2 (Screen, bg, D+5); + } + else + { + DrawBGMode7Background16Sub (Screen, bg, D+5); + } + } + else + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Add1_2 (Screen, bg, D+5); + } + else + { + DrawBGMode7Background16Add (Screen, bg, D+5); + } + } + } + } + } + if (OB && SNESGameFixes.Mode7Hack && D==0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4)); + DrawOBJS (!sub, D); + } + + } +} + +#include "font.h" + +void DisplayChar (uint8 *Screen, uint8 c) +{ + int line = (((c & 0x7f) - 32) >> 4) * font_height; + int offset = (((c & 0x7f) - 32) & 15) * font_width; + int h, w; + uint16 *s = (uint16 *) Screen; + for (h = 0; h < font_height; h++, line++, + s += GFX_PPL - font_width) + { + for (w = 0; w < font_width; w++, s++) + { + uint8 p = font [line][offset + w]; + + if (p == '#') + *s = 0xffff; + else + if (p == '.') + *s = BLACK; + } + } +} + +static void S9xDisplayFrameRate () +{ + uint8 *Screen = GFX.Screen + 2 + + (IPPU.RenderedScreenHeight - font_height - 1) * GFX_PITCH; + char string [10]; + int len = 5; + + sprintf (string, "%02d/%02d", IPPU.DisplayedRenderedFrameCount, + (int) Memory.ROMFramesPerSecond); + + int i; + for (i = 0; i < len; i++) + { + DisplayChar (Screen, string [i]); + Screen += (font_width - 1) * sizeof (uint16); + } +} + +static void S9xDisplayString (const char *string) +{ + uint8 *Screen = GFX.Screen + 2 + + (IPPU.RenderedScreenHeight - font_height * 5) * GFX_PITCH; + int len = strlen (string); + int max_chars = IPPU.RenderedScreenWidth / (font_width - 1); + int char_count = 0; + int i; + + for (i = 0; i < len; i++, char_count++) + { + if (char_count >= max_chars || string [i] < 32) + { + Screen -= (font_width - 1) * sizeof (uint16) * max_chars; + Screen += font_height * GFX_PITCH; + if (Screen >= GFX.Screen + GFX_PITCH * IPPU.RenderedScreenHeight) + break; + char_count -= max_chars; + } + if (string [i] < 32) + continue; + DisplayChar (Screen, string [i]); + Screen += (font_width - 1) * sizeof (uint16); + } +} + +void S9xUpdateScreen () // ~30-50ms! (called from FLUSH_REDRAW()) +{ + int32 x2 = 1; + + GFX.S = GFX.Screen; + + unsigned char *memoryfillram = Memory.FillRAM; + + // get local copies of vid registers to be used later + GFX.r2131 = memoryfillram [0x2131]; // ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN + GFX.r212c = memoryfillram [0x212c]; // MAIN SCREEN, DESIGNATION - used to enable BGS + GFX.r212d = memoryfillram [0x212d]; // SUB SCREEN DESIGNATION - used to enable sub BGS + GFX.r2130 = memoryfillram [0x2130]; // INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION + + // If external sync is off and + // main screens have not been configured the same as the sub screen and + // color addition and subtraction has been diabled then + // Pseudo is 1 + // anything else it is 0 + GFX.Pseudo = (memoryfillram [0x2133] & 8) != 0 && // Use EXTERNAL SYNCHRONIZATION? + (GFX.r212c & 15) != (GFX.r212d & 15) && // Are the main screens different from the sub screens? + (GFX.r2131 & 0x3f) == 0; // Is colour data addition/subtraction disabled on all BGS? + + // If sprite data has been changed then go through and + // refresh the sprites. + if (IPPU.OBJChanged) + { + S9xSetupOBJ (); + } + + if (PPU.RecomputeClipWindows) + { + ComputeClipWindows (); + PPU.RecomputeClipWindows = FALSE; + } + + GFX.StartY = IPPU.PreviousLine; + if ((GFX.EndY = IPPU.CurrentLine - 1) >= PPU.ScreenHeight) + GFX.EndY = PPU.ScreenHeight - 1; + + uint32 starty = GFX.StartY; + uint32 endy = GFX.EndY; + + if (Settings.SupportHiRes && + (PPU.BGMode == 5 || PPU.BGMode == 6 || IPPU.LatchedInterlace)) + { + if (PPU.BGMode == 5 || PPU.BGMode == 6) + { + IPPU.RenderedScreenWidth = 512; + x2 = 2; + } + if (IPPU.LatchedInterlace) + { + starty = GFX.StartY * 2; + endy = GFX.EndY * 2 + 1; + } + if (!IPPU.DoubleWidthPixels) + { + // The game has switched from lo-res to hi-res mode part way down + // the screen. Scale any existing lo-res pixels on screen + for (register uint32 y = 0; y < GFX.StartY; y++) + { + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH) + 255; + register uint16 *q = (uint16 *) (GFX.Screen + y * GFX_PITCH) + 510; + for (register int x = 255; x >= 0; x--, p--, q -= 2) + *q = *(q + 1) = *p; + } + IPPU.DoubleWidthPixels = TRUE; + } + } + + uint32 black = BLACK | (BLACK << 16); + + // Are we worrying about transparencies? + if (Settings.Transparency) + { + if (GFX.Pseudo) + { + GFX.r2131 = 0x5f; //0101 1111 - enable addition/subtraction on all BGS and sprites and "1/2 OF COLOR DATA" DESIGNATION + GFX.r212c &= (Memory.FillRAM [0x212d] | 0xf0); + GFX.r212d |= (Memory.FillRAM [0x212c] & 0x0f); + GFX.r2130 |= 2; // enable ADDITION/SUBTRACTION FOR SUB SCREEN + } + + // Check to see if any transparency effects are currently in use + if (!PPU.ForcedBlanking && ADD_OR_SUB_ON_ANYTHING && + (GFX.r2130 & 0x30) != 0x30 && + !((GFX.r2130 & 0x30) == 0x10 && IPPU.Clip[1].Count[5] == 0)) + { + // transparency effects in use, so lets get busy! + struct ClipData *pClip; + uint32 fixedColour; + GFX.FixedColour = BUILD_PIXEL (IPPU.XB [PPU.FixedColourRed], + IPPU.XB [PPU.FixedColourGreen], + IPPU.XB [PPU.FixedColourBlue]); + fixedColour = (GFX.FixedColour<<16|GFX.FixedColour); + // Clear the z-buffer, marking areas 'covered' by the fixed + // colour as depth 1. + pClip = &IPPU.Clip [1]; + + // Clear the z-buffer + + if (pClip->Count [5]) + { + + // Colour window enabled. + +#ifdef RC_OPTIMIZED + for (uint32 y = starty; y <= endy; y++) + { + + ZeroMemory (GFX.SubZBuffer + y * GFX_ZPITCH, + IPPU.RenderedScreenWidth); + ZeroMemory (GFX.ZBuffer + y * GFX_ZPITCH, + IPPU.RenderedScreenWidth); + + if (IPPU.Clip [0].Count [5]) + { + memset ((GFX.SubScreen + y * GFX_PITCH), black, IPPU.RenderedScreenWidth); + } + for (uint32 c = 0; c < pClip->Count [5]; c++) + { + if (pClip->Right [c][5] > pClip->Left [c][5]) + { + memset (GFX.SubZBuffer + y * GFX_ZPITCH + pClip->Left [c][5] * x2, + 1, (pClip->Right [c][5] - pClip->Left [c][5]) * x2); + if (IPPU.Clip [0].Count [5]) + { + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + memset ((GFX.SubScreen + y * GFX_PITCH) + pClip->Left [c][5] * x2, + GFX.FixedColour, + pClip->Right[c][5]*x2 - pClip->Left [c][5] * x2); + } + } + } + } + +#else // NOT RC_OPTIMIZED + // loop around all of the lines being updated + for (uint32 y = starty; y <= endy; y++) + { + // Clear the subZbuffer + memset32 ((uint32_t*)(GFX.SubZBuffer + y * GFX_ZPITCH),0, + IPPU.RenderedScreenWidth>>2); + // Clear the Zbuffer + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH),0, + IPPU.RenderedScreenWidth>>2); + + // if there is clipping then clear subscreen to a black color + if (IPPU.Clip [0].Count [5]) + { + memset32 ((uint32_t*)(GFX.SubScreen + y * GFX_PITCH), black, IPPU.RenderedScreenWidth>>1); + } + + // loop through all window clippings + for (uint32 c = 0; c < pClip->Count [5]; c++) + { + if (pClip->Right [c][5] > pClip->Left [c][5]) + { + memset (GFX.SubZBuffer + y * GFX_ZPITCH + pClip->Left [c][5] * x2, + 1, (pClip->Right [c][5] - pClip->Left [c][5]) * x2); + if (IPPU.Clip [0].Count [5]) + { + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + + register uint16 *p = (uint16 *) (GFX.SubScreen + y * GFX_PITCH); + register uint16 *q = p + pClip->Right [c][5] * x2; + p += pClip->Left [c][5] * x2; + + while (p < q) + *p++ = (uint16) GFX.FixedColour; + } + } + } + } +#endif +//#undef RC_OPTIMIZED + + } + else + { + // No windows are clipping the main screen + // this simplifies the screen clearing process +#ifdef RC_OPTIMIZED + + if (GFX_ZPITCH == (uint32)IPPU.RenderedScreenWidth) + { + + memset (GFX.ZBuffer + starty * GFX_ZPITCH, 0, GFX_ZPITCH * (endy - starty - 1)); + memset (GFX.SubZBuffer + starty * GFX_ZPITCH, 1, GFX_ZPITCH * (endy - starty - 1)); + } + else + { + for (uint32 y = starty; y <= endy; y++) + { + ZeroMemory (GFX.ZBuffer + y * GFX_ZPITCH, + IPPU.RenderedScreenWidth); + memset (GFX.SubZBuffer + y * GFX_ZPITCH, 1, + IPPU.RenderedScreenWidth); + } + } + + if (IPPU.Clip [0].Count [5]) + { + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + if (GFX_PITCH == (uint32)IPPU.RenderedScreenWidth) + { + memset ((GFX.SubScreen + starty * GFX_PITCH), + GFX.FixedColour | (GFX.FixedColour << 16), + GFX_PITCH * (endy - starty - 1)); + } + else + { + for (uint32 y = starty; y <= endy; y++) + { + memset ((GFX.SubScreen + y * GFX_PITCH), + GFX.FixedColour | (GFX.FixedColour << 16), + IPPU.RenderedScreenWidth); + } + } + } + +#else // NOT RC_OPTIMIZED + // loop through all of the lines to be updated + for (uint32 y = starty; y <= endy; y++) + { + // Clear the Zbuffer + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH),0, + IPPU.RenderedScreenWidth>>2); + // clear the sub Zbuffer to 1 + memset32 ((uint32_t*)(GFX.SubZBuffer + y * GFX_ZPITCH), 0x01010101, + IPPU.RenderedScreenWidth>>2); + if (IPPU.Clip [0].Count [5]) + { + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + + + memset32 ((uint32_t*)(GFX.SubScreen + y * GFX_PITCH), fixedColour, + IPPU.RenderedScreenWidth>>1); + } + } +#endif + + } + + if (ANYTHING_ON_SUB) + { + GFX.DB = GFX.SubZBuffer; + RenderScreen (GFX.SubScreen, TRUE, TRUE, SUB_SCREEN_DEPTH); + } + + if (IPPU.Clip [0].Count [5]) + { + for (uint32 y = starty; y <= endy; y++) + { + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH); + register uint8 *d = GFX.SubZBuffer + y * GFX_ZPITCH ; + register uint8 *e = d + IPPU.RenderedScreenWidth; + + while (d < e) + { + if (*d > 1) + *p = *(p + GFX.Delta); + else + *p = BLACK; + d++; + p++; + } + } + } + + GFX.DB = GFX.ZBuffer; + RenderScreen (GFX.Screen, FALSE, FALSE, MAIN_SCREEN_DEPTH); + if (SUB_OR_ADD(5)) + { + uint32 back = IPPU.ScreenColors [0]; + uint32 Left = 0; + uint32 Right = 256; + uint32 Count; + + pClip = &IPPU.Clip [0]; + + for (uint32 y = starty; y <= endy; y++) + { + if (!(Count = pClip->Count [5])) + { + Left = 0; + Right = 256 * x2; + Count = 1; + } + + for (uint32 b = 0; b < Count; b++) + { + if (pClip->Count [5]) + { + Left = pClip->Left [b][5] * x2; + Right = pClip->Right [b][5] * x2; + if (Right <= Left) + continue; + } + + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + // Subtract, halving the result. + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH) + Left; + register uint8 *d = GFX.ZBuffer + y * GFX_ZPITCH; + register uint8 *s = GFX.SubZBuffer + y * GFX_ZPITCH + Left; + register uint8 *e = d + Right; + uint16 back_fixed = COLOR_SUB (back, GFX.FixedColour); + + d += Left; + while (d < e) + { + if (*d == 0) + { + if (*s) + { + if (*s != 1) + *p = COLOR_SUB1_2 (back, *(p + GFX.Delta)); + else + *p = back_fixed; + } + else + *p = (uint16) back; + } + d++; + p++; + s++; + } + } + else + { + // Subtract + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH) + Left; + register uint8 *s = GFX.SubZBuffer + y * GFX_ZPITCH + Left; + register uint8 *d = GFX.ZBuffer + y * GFX_ZPITCH; + register uint8 *e = d + Right; + uint16 back_fixed = COLOR_SUB (back, GFX.FixedColour); + + d += Left; + while (d < e) + { + if (*d == 0) + { + if (*s) + { + if (*s != 1) + *p = COLOR_SUB (back, *(p + GFX.Delta)); + else + *p = back_fixed; + } + else + *p = (uint16) back; + } + d++; + p++; + s++; + } + } + } + else + if (GFX.r2131 & 0x40) + { + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH) + Left; + register uint8 *d = GFX.ZBuffer + y * GFX_ZPITCH; + register uint8 *s = GFX.SubZBuffer + y * GFX_ZPITCH + Left; + register uint8 *e = d + Right; + uint16 back_fixed = COLOR_ADD (back, GFX.FixedColour); + d += Left; + while (d < e) + { + if (*d == 0) + { + if (*s) + { + if (*s != 1) + *p = COLOR_ADD1_2 (back, *(p + GFX.Delta)); + else + *p = back_fixed; + } + else + *p = (uint16) back; + } + d++; + p++; + s++; + } + } + else + if (back != 0) + { + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH) + Left; + register uint8 *d = GFX.ZBuffer + y * GFX_ZPITCH; + register uint8 *s = GFX.SubZBuffer + y * GFX_ZPITCH + Left; + register uint8 *e = d + Right; + uint16 back_fixed = COLOR_ADD (back, GFX.FixedColour); + d += Left; + while (d < e) + { + if (*d == 0) + { + if (*s) + { + if (*s != 1) + *p = COLOR_ADD (back, *(p + GFX.Delta)); + else + *p = back_fixed; + } + else + *p = (uint16) back; + } + d++; + p++; + s++; + } + } + else + { + if (!pClip->Count [5]) + { + // The backdrop has not been cleared yet - so + // copy the sub-screen to the main screen + // or fill it with the back-drop colour if the + // sub-screen is clear. + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH) + Left; + register uint8 *d = GFX.ZBuffer + y * GFX_ZPITCH; + register uint8 *s = GFX.SubZBuffer + y * GFX_ZPITCH + Left; + register uint8 *e = d + Right; + d += Left; + while (d < e) + { + if (*d == 0) + { + if (*s) + { + if (*s != 1) + *p = *(p + GFX.Delta); + else + *p = GFX.FixedColour; + } + else + *p = (uint16) back; + } + d++; + p++; + s++; + } + } + } + } + } + + } + else + { + // Subscreen not being added to back + uint32 back = IPPU.ScreenColors [0] | (IPPU.ScreenColors [0] << 16); + pClip = &IPPU.Clip [0]; + + if (pClip->Count [5]) + { + for (uint32 y = starty; y <= endy; y++) + { + for (uint32 b = 0; b < pClip->Count [5]; b++) + { + uint32 Left = pClip->Left [b][5] * x2; + uint32 Right = pClip->Right [b][5] * x2; + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH) + Left; + register uint8 *d = GFX.ZBuffer + y * GFX_ZPITCH; + register uint8 *e = d + Right; + d += Left; + + while (d < e) + { + if (*d++ == 0) + *p = (int16) back; + p++; + } + } + } + } + else + { + for (uint32 y = starty; y <= endy; y++) + { + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH); + register uint8 *d = GFX.ZBuffer + y * GFX_ZPITCH; + register uint8 *e = d + 256 * x2; + + while (d < e) + { + if (*d == 0) +#ifdef RC_OPTIMIZED + *p++ = back; + d++; +#else + *p = (int16) back; + d++; + p++; +#endif + } + } + } + } + } + else + { + // 16bit and transparency but currently no transparency effects in + // operation. + + // get the back colour of the current screen + uint32 back = IPPU.ScreenColors [0] | + (IPPU.ScreenColors [0] << 16); + + // if forceblanking in use then use black instead of the back color + if (PPU.ForcedBlanking) + back = black; + + // not sure what Clip is used for yet + // could be a check to see if there is any clipping present? + if (IPPU.Clip [0].Count[5]) + { + +#ifdef RC_OPTIMIZED + if (GFX_PITCH == (uint32)IPPU.RenderedScreenWidth) + { + memset (GFX.Screen + starty * GFX_PITCH, black, + GFX_PITCH * (endy - starty - 1)); + } + else + { + for (uint32 y = starty; y <= endy; y++) + { + memset (GFX.Screen + y * GFX_PITCH, black, + GFX_PITCH); + } + } + for (uint32 y = starty; y <= endy; y++) + { + for (uint32 c = 0; c < IPPU.Clip [0].Count [5]; c++) + { + if (IPPU.Clip [0].Right [c][5] > IPPU.Clip [0].Left [c][5]) + { + + memset ((GFX.Screen + y * GFX_PITCH) + IPPU.Clip [0].Left [c][5] * x2, + back, + IPPU.Clip [0].Right [c][5] * x2 - IPPU.Clip [0].Left [c][5] * x2); + } + } + } +#else + // loop through all of the lines that are going to be updated as part of this screen update + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), black, + IPPU.RenderedScreenWidth>>1); + + if (black!=back) + { + for (uint32 c = 0; c < IPPU.Clip [0].Count [5]; c++) + { + if (IPPU.Clip [0].Right [c][5] > IPPU.Clip [0].Left [c][5]) + { + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH); // get pointer to current line in screen buffer + register uint16 *q = p + IPPU.Clip [0].Right [c][5] * x2; // get pointer to end of line + p += IPPU.Clip [0].Left [c][5] * x2; + + while (p < q) + *p++ = (uint16) back; // fill all pixels in clipped section with the back colour + } + } + } + } +#endif + } + else + { +#ifdef RC_OPTIMIZED + if (GFX_PITCH == (uint32)IPPU.RenderedScreenWidth) + { + memset (GFX.Screen + starty * GFX_PITCH, back, + GFX_PITCH * (endy - starty - 1)); + } + else + { + for (uint32 y = starty; y <= endy; y++) + { + memset (GFX.Screen + y * GFX_PITCH, back, + GFX_PITCH); + } + } +#else + // there is no clipping to worry about so just fill with the back colour + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), back, + IPPU.RenderedScreenWidth>>1); + } +#endif + } + + // If Forced blanking is not in effect + if (!PPU.ForcedBlanking) + { +#ifdef RC_OPTIMIZED + if (GFX_ZPITCH == (uint32)IPPU.RenderedScreenWidth) + { + memset (GFX.ZBuffer + starty * GFX_ZPITCH, 0, + GFX_ZPITCH * (endy - starty - 1)); + } + else + { + for (uint32 y = starty; y <= endy; y++) + { + memset (GFX.ZBuffer + y * GFX_ZPITCH, 0, + GFX_ZPITCH); + } + } +#else + // Clear the Zbuffer for each of the lines which are going to be updated + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH), 0, + IPPU.RenderedScreenWidth>>2); + } +#endif + GFX.DB = GFX.ZBuffer; // save pointer to Zbuffer in GFX object + RenderScreen (GFX.Screen, FALSE, TRUE, SUB_SCREEN_DEPTH); + } + } + } + else // Transparencys are disabled, ahh lovely ... nice and easy. + { + // get back colour to be used in clearing the screen + register uint32 back; + if (!(Memory.FillRAM [0x2131] & 0x80) &&(Memory.FillRAM[0x2131] & 0x20) && + (PPU.FixedColourRed || PPU.FixedColourGreen || PPU.FixedColourBlue)) + { + back = (IPPU.XB[PPU.FixedColourRed]<<11) | + (IPPU.XB[PPU.FixedColourGreen] << 6) | + (IPPU.XB[PPU.FixedColourBlue] << 1) | 1; + back = (back << 16) | back; + } + else + { + back = IPPU.ScreenColors [0] | (IPPU.ScreenColors [0] << 16); + } + + // if Forcedblanking in use then back colour becomes black + if (PPU.ForcedBlanking) + back = black; + else + { + SelectTileRenderer (TRUE); //selects the tile renderers to be used + // TRUE means to use the default + // FALSE means use best renderer based on current + // graphics register settings + } + + // now clear all graphics lines which are being updated using the back colour + for (register uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), back, + IPPU.RenderedScreenWidth>>1); + } + + if (!PPU.ForcedBlanking) + { + // Loop through all lines being updated and clear the + // zbuffer for each of the lines + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH), 0, + IPPU.RenderedScreenWidth>>2); + } + GFX.DB = GFX.ZBuffer; // save pointer to Zbuffer in GFX object + GFX.pCurrentClip = &IPPU.Clip [0]; + +// Define an inline function to handle clipping +#define FIXCLIP(n) \ +if (GFX.r212c & (1 << (n))) \ + GFX.pCurrentClip = &IPPU.Clip [0]; \ +else \ + GFX.pCurrentClip = &IPPU.Clip [1] + +// Define an inline function to handle which BGs are being displayed +#define DISPLAY(n) ((GFX.r212c & n) || ((GFX.r212d & n) && subadd)) + + uint8 subadd = GFX.r2131 & 0x3f; + + // go through all BGS are check if they need to be displayed + bool8_32 BG0 = DISPLAY(1) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + bool8_32 BG1 = DISPLAY(2) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + bool8_32 BG2 = DISPLAY(4) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + bool8_32 BG3 = DISPLAY(8) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + bool8_32 OB = DISPLAY(16) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + + if (PPU.BGMode <= 1) + { + // screen modes 0 and 1 + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + if (BG0) + { + FIXCLIP(0); + DrawBackground (PPU.BGMode, 0, 10, 14); + } + if (BG1) + { + FIXCLIP(1); + DrawBackground (PPU.BGMode, 1, 9, 13); + } + if (BG2) + { + FIXCLIP(2); + DrawBackground (PPU.BGMode, 2, 3, + PPU.BG3Priority ? 17 : 6); + } + if (BG3 && PPU.BGMode == 0) + { + FIXCLIP(3); + DrawBackground (PPU.BGMode, 3, 2, 5); + } + } + else if (PPU.BGMode != 7) + { + // screen modes 2 and up but not mode 7 + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + if (BG0) + { + FIXCLIP(0); + DrawBackground (PPU.BGMode, 0, 5, 13); + } + if (BG1 && PPU.BGMode != 6) + { + FIXCLIP(1); + DrawBackground (PPU.BGMode, 1, 2, 9); + } + } + else + { + // screen mode 7 + GFX.Mode7Mask = 0xff; + GFX.Mode7PriorityMask = 0; + int bg = 0; + DrawBGMode7Background16New (GFX.Screen, bg); + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + } + } + } +#ifndef RC_OPTIMIZE // no hi res + if (Settings.SupportHiRes && PPU.BGMode != 5 && PPU.BGMode != 6) + { + if (IPPU.DoubleWidthPixels) + { + // Mixure of background modes used on screen - scale width + // of all non-mode 5 and 6 pixels. + for (register uint32 y = GFX.StartY; y <= GFX.EndY; y++) + { + register uint16 *p = (uint16 *) (GFX.Screen + y * GFX_PITCH) + 255; + register uint16 *q = (uint16 *) (GFX.Screen + y * GFX_PITCH) + 510; + for (register int x = 255; x >= 0; x--, p--, q -= 2) + *q = *(q + 1) = *p; + } + + } + + if (IPPU.LatchedInterlace) + { + // Interlace is enabled - double the height of all non-mode 5 and 6 + // pixels. + for (uint32 y = GFX.StartY; y <= GFX.EndY; y++) + { + memcpy32 ((uint32_t*)(GFX.Screen + (y * 2 + 1) * GFX_PITCH), + (uint32_t*)(GFX.Screen + y * 2 * GFX_PITCH), + GFX_PITCH>>2); + } + } + } +#endif + IPPU.PreviousLine = IPPU.CurrentLine; +} + +#ifdef GFX_MULTI_FORMAT + +#define _BUILD_PIXEL(F) \ +uint32 BuildPixel##F(uint32 R, uint32 G, uint32 B) \ +{ \ + return (BUILD_PIXEL_##F(R,G,B)); \ +}\ +uint32 BuildPixel2##F(uint32 R, uint32 G, uint32 B) \ +{ \ + return (BUILD_PIXEL2_##F(R,G,B)); \ +} \ +void DecomposePixel##F(uint32 pixel, uint32 &R, uint32 &G, uint32 &B) \ +{ \ + DECOMPOSE_PIXEL_##F(pixel,R,G,B); \ +} + +_BUILD_PIXEL(RGB565) +_BUILD_PIXEL(RGB555) +_BUILD_PIXEL(BGR565) +_BUILD_PIXEL(BGR555) +_BUILD_PIXEL(GBR565) +_BUILD_PIXEL(GBR555) +_BUILD_PIXEL(RGB5551) + +bool8_32 S9xSetRenderPixelFormat (int format) +{ + extern uint32 current_graphic_format; + + current_graphic_format = format; + + switch (format) + { + case RGB565: + _BUILD_SETUP(RGB565) + return (TRUE); + case RGB555: + _BUILD_SETUP(RGB555) + return (TRUE); + case BGR565: + _BUILD_SETUP(BGR565) + return (TRUE); + case BGR555: + _BUILD_SETUP(BGR555) + return (TRUE); + case GBR565: + _BUILD_SETUP(GBR565) + return (TRUE); + case GBR555: + _BUILD_SETUP(GBR555) + return (TRUE); + case RGB5551: + _BUILD_SETUP(RGB5551) + return (TRUE); + default: + break; + } + return (FALSE); +} +#endif diff --git a/src/gfx.h b/src/gfx.h new file mode 100644 index 0000000..55f5a56 --- /dev/null +++ b/src/gfx.h @@ -0,0 +1,270 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _GFX_H_ +#define _GFX_H_ + +#include "port.h" + +#define GFX_PIXSIZE 1 +#define GFX_PITCH 640 +#define GFX_ZPITCH 320 +#define GFX_PPL 320 + +struct SGFX{ + // Initialize these variables + uint8 *Screen; + uint8 *SubScreen; + uint8 *ZBuffer; + uint8 *SubZBuffer; + uint32 Pitch; + + // Setup in call to S9xGraphicsInit() + int Delta; + uint16 *X2; + uint16 *ZERO_OR_X2; + uint16 *ZERO; + uint8 *S; + uint8 *DB; + uint32 *ScreenColors; + uint32 *ScreenColorsPre; + uint32 PaletteMask; + uint32 PaletteShift; + uint32 DepthDelta; + uint8 Z1; + uint8 Z2; + uint32 FixedColour; + uint32 StartY; + uint32 EndY; + struct ClipData *pCurrentClip; + uint32 Mode7Mask; + uint32 Mode7PriorityMask; + + uint8 r212c; + uint8 r212c_s; + uint8 r212d; + uint8 r212d_s; + uint8 r212e_s; + uint8 r212f_s; + uint8 r2130; + uint8 r2130_s; + uint8 r2131; + uint8 r2131_s; + bool8 Pseudo; + + int OBJList [129]; + uint32 Sizes [129]; + int VPositions [129]; + +#ifdef GFX_MULTI_FORMAT + uint32 PixelFormat; + uint32 (*BuildPixel) (uint32 R, uint32 G, uint32 B); + uint32 (*BuildPixel2) (uint32 R, uint32 G, uint32 B); + void (*DecomposePixel) (uint32 Pixel, uint32 &R, uint32 &G, uint32 &B); +#endif +}; + +struct SLineData { + struct { + uint16 VOffset; + uint16 HOffset; + } BG [4]; +}; + +#define H_FLIP 0x4000 +#define V_FLIP 0x8000 +#define BLANK_TILE 2 + +struct SBG +{ + uint32 TileSize; + uint32 BitShift; + uint32 TileShift; + uint32 TileAddress; + uint32 NameSelect; + uint32 SCBase; + + uint32 StartPalette; + uint32 PaletteShift; + uint32 PaletteMask; + + uint8 *Buffer; + uint8 *Buffered; + bool8 DirectColourMode; +}; + +struct SLineMatrixData +{ + short MatrixA; + short MatrixB; + short MatrixC; + short MatrixD; + short CentreX; + short CentreY; +}; + +extern uint32 odd_high [4][16]; +extern uint32 odd_low [4][16]; +extern uint32 even_high [4][16]; +extern uint32 even_low [4][16]; +extern SBG BG; +extern uint32 DirectColourMaps [8][256]; + +//extern uint8 add32_32 [32][32]; +//extern uint8 add32_32_half [32][32]; +//extern uint8 sub32_32 [32][32]; +//extern uint8 sub32_32_half [32][32]; +extern uint8 mul_brightness [16][32]; + +// Could use BSWAP instruction on Intel port... +//#define SWAP_DWORD(dw) dw = ((dw & 0xff) << 24) | ((dw & 0xff00) << 8) | \ +// ((dw & 0xff0000) >> 8) | ((dw & 0xff000000) >> 24) +// by Harald Kipp, from http://www.ethernut.de/en/documents/arm-inline-asm.html +#define SWAP_DWORD(val) \ + __asm__ __volatile__ ( \ + "eor r3, %1, %1, ror #16\n\t" \ + "bic r3, r3, #0x00FF0000\n\t" \ + "mov %0, %1, ror #8\n\t" \ + "eor %0, %0, r3, lsr #8" \ + : "=r" (val) \ + : "0"(val) \ + : "r3", "cc" \ + ); + + +#ifdef FAST_LSB_WORD_ACCESS +#define READ_2BYTES(s) (*(uint16 *) (s)) +#define WRITE_2BYTES(s, d) *(uint16 *) (s) = (d) +#else +#ifdef LSB_FIRST +#define READ_2BYTES(s) (*(uint16 *) (s)) +#define WRITE_2BYTES(s, d) *(uint16 *) (s) = (d) + +//#define READ_2BYTES(s) (*(uint8 *) (s) | (*((uint8 *) (s) + 1) << 8)) +//#define WRITE_2BYTES(s, d) *(uint8 *) (s) = (d), \ +// *((uint8 *) (s) + 1) = (d) >> 8 +#else // else MSB_FISRT +#define READ_2BYTES(s) (*(uint8 *) (s) | (*((uint8 *) (s) + 1) << 8)) +#define WRITE_2BYTES(s, d) *(uint8 *) (s) = (d), \ + *((uint8 *) (s) + 1) = (d) >> 8 +#endif // LSB_FIRST +#endif // i386 + +#define SUB_SCREEN_DEPTH 0 +#define MAIN_SCREEN_DEPTH 32 + +#if defined(OLD_COLOUR_BLENDING) +#define COLOR_ADD(C1, C2) \ +GFX.X2 [((((C1) & RGB_REMOVE_LOW_BITS_MASK) + \ + ((C2) & RGB_REMOVE_LOW_BITS_MASK)) >> 1) + \ + ((C1) & (C2) & RGB_LOW_BITS_MASK)] +#else +#define COLOR_ADD(C1, C2) \ +(GFX.X2 [((((C1) & RGB_REMOVE_LOW_BITS_MASK) + \ + ((C2) & RGB_REMOVE_LOW_BITS_MASK)) >> 1) + \ + ((C1) & (C2) & RGB_LOW_BITS_MASK)] | \ + (((C1) ^ (C2)) & RGB_LOW_BITS_MASK)) +#endif + +#define COLOR_ADD1_2(C1, C2) \ +(((((C1) & RGB_REMOVE_LOW_BITS_MASK) + \ + ((C2) & RGB_REMOVE_LOW_BITS_MASK)) >> 1) + \ + ((C1) & (C2) & RGB_LOW_BITS_MASK) | ALPHA_BITS_MASK) + +#if defined(OLD_COLOUR_BLENDING) +#define COLOR_SUB(C1, C2) \ +GFX.ZERO_OR_X2 [(((C1) | RGB_HI_BITS_MASKx2) - \ + ((C2) & RGB_REMOVE_LOW_BITS_MASK)) >> 1] +#else +#define COLOR_SUB(C1, C2) \ +(GFX.ZERO_OR_X2 [(((C1) | RGB_HI_BITS_MASKx2) - \ + ((C2) & RGB_REMOVE_LOW_BITS_MASK)) >> 1] + \ +((C1) & RGB_LOW_BITS_MASK) - ((C2) & RGB_LOW_BITS_MASK)) +#endif + +#define COLOR_SUB1_2(C1, C2) \ +GFX.ZERO [(((C1) | RGB_HI_BITS_MASKx2) - \ + ((C2) & RGB_REMOVE_LOW_BITS_MASK)) >> 1] + +typedef void (*NormalTileRenderer) (uint32 Tile, uint32 Offset, + uint32 StartLine, uint32 LineCount); +typedef void (*ClippedTileRenderer) (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +typedef void (*LargePixelRenderer) (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + + +typedef struct { + NormalTileRenderer Normal; + ClippedTileRenderer Clipped; + LargePixelRenderer Large; +} TileRendererSet; + +START_EXTERN_C +void S9xStartScreenRefresh (); +void S9xDrawScanLine (uint8 Line); +void S9xEndScreenRefresh (); +void S9xSetupOBJ (struct SOBJ *); +void S9xUpdateScreen (); +//extern void (*S9xUpdateScreen)(); +//void SelectUpdateScreen(); +void RenderLine (uint8 line); +void S9xBuildDirectColourMaps (); + +// External port interface which must be implemented or initialised for each +// port. +extern struct SGFX GFX; + +bool8_32 S9xGraphicsInit (); +void S9xGraphicsDeinit(); +bool8_32 S9xInitUpdate (void); +bool8_32 S9xDeinitUpdate (int Width, int Height, bool8_32 sixteen_bit); +void S9xSetPalette (); +void S9xSyncSpeed (); + +#ifdef GFX_MULTI_FORMAT +bool8_32 S9xSetRenderPixelFormat (int format); +#endif + +END_EXTERN_C + +#endif diff --git a/src/gfx16.cpp b/src/gfx16.cpp new file mode 100644 index 0000000..a05e335 --- /dev/null +++ b/src/gfx16.cpp @@ -0,0 +1,3445 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" + +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" +#include "cheats.h" +#include +#include "asmmemfuncs.h" +#include "mode7.h" +#include "rops.h" +#include "tile16.h" +uint32 TileBlank; + +//#define __DEBUG__ + +#ifdef __DEBUG__ + #define DBG(b) printf(b) +#else + #define DBG(b) +#endif + + +const int tx_table[16] = { +// t1 = 16, t2 = 0 + // FLIP = 0x00 + 16 + 0, // 0x00 + 16 + 1, // 0x01 + + // FLIP = 0x01 + 16 + 1 - 0, // 0x02 + 16 + 1 - 1, // 0x03 + + // FLIP = 0x02 + 0 + 0, // 0x04 + 0 + 1, // 0x05 + + // FLIP = 0x03 + 0 + 1 - 0, // 0x06 + 0 + 1 - 1, // 0x07 + +// t1 = 0, t2 = 16 + // FLIP = 0x00 + 0 + 0, // 0x08 + 0 + 1, // 0x09 + + // FLIP = 0x01 + 0 + 1 - 0, // 0x0A + 0 + 1 - 1, // 0x0B + + // FLIP = 0x02 + 16 + 0, // 0x0C + 16 + 1, // 0x0D + + // FLIP = 0x03 + 16 + 1 - 0, // 0x0E + 16 + 1 - 1 // 0x0F +}; + +#define M7 19 +#define M8 19 + +void ComputeClipWindows (); +static void S9xDisplayFrameRate (); +static void S9xDisplayString (const char *string); + +extern uint8 BitShifts[8][4]; +extern uint8 TileShifts[8][4]; +extern uint8 PaletteShifts[8][4]; +extern uint8 PaletteMasks[8][4]; +extern uint8 Depths[8][4]; +extern uint8 BGSizes [2]; + +extern NormalTileRenderer DrawTilePtr; +extern ClippedTileRenderer DrawClippedTilePtr; +extern NormalTileRenderer DrawHiResTilePtr; +extern ClippedTileRenderer DrawHiResClippedTilePtr; +extern LargePixelRenderer DrawLargePixelPtr; + +extern struct SBG BG; + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; + +extern uint8 Mode7Depths [2]; + +#define ON_MAIN(N) (GFX.r212c & (1 << (N))) + +#define SUB_OR_ADD(N) \ +(GFX.r2131 & (1 << (N))) + +#define ON_SUB(N) \ +((GFX.r2130 & 0x30) != 0x30 && \ + (GFX.r2130 & 2) && \ + (GFX.r212d & (1 << N))) + +#define ANYTHING_ON_SUB \ +((GFX.r2130 & 0x30) != 0x30 && \ + (GFX.r2130 & 2) && \ + (GFX.r212d & 0x1f)) + +#define ADD_OR_SUB_ON_ANYTHING \ +(GFX.r2131 & 0x3f) + +#define BLACK BUILD_PIXEL(0,0,0) + +void DrawNoZTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount); +void DrawTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTile16x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTile16x2x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16x2x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawLargePixel16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Add (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawTile16Add (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Add1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawTile16Add1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Sub (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + + +void DrawTile16Sub (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Sub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + + +void DrawTile16Sub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16FixedSub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16FixedSub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawHiResClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawHiResTile16 (uint32 Tile, uint32 Offset, + uint32 StartLine, uint32 LineCount); + +bool8_32 S9xGraphicsInit () +{ + register uint32 PixelOdd = 1; + register uint32 PixelEven = 2; + +#ifdef GFX_MULTI_FORMAT + if (GFX.BuildPixel == NULL) + S9xSetRenderPixelFormat (RGB565); +#endif + + for (uint8 bitshift = 0; bitshift < 4; bitshift++) + { + for (register int i = 0; i < 16; i++) + { + register uint32 h = 0; + register uint32 l = 0; + +#if defined(LSB_FIRST) +// Wiz usa LSB_FIRST + if (i & 8) + h |= PixelOdd; + if (i & 4) + h |= PixelOdd << 8; + if (i & 2) + h |= PixelOdd << 16; + if (i & 1) + h |= PixelOdd << 24; + if (i & 8) + l |= PixelOdd; + if (i & 4) + l |= PixelOdd << 8; + if (i & 2) + l |= PixelOdd << 16; + if (i & 1) + l |= PixelOdd << 24; +#else + if (i & 8) + h |= (PixelOdd << 24); + if (i & 4) + h |= (PixelOdd << 16); + if (i & 2) + h |= (PixelOdd << 8); + if (i & 1) + h |= PixelOdd; + if (i & 8) + l |= (PixelOdd << 24); + if (i & 4) + l |= (PixelOdd << 16); + if (i & 2) + l |= (PixelOdd << 8); + if (i & 1) + l |= PixelOdd; +#endif + + odd_high[bitshift][i] = h; + odd_low[bitshift][i] = l; + h = l = 0; + +#if defined(LSB_FIRST) + if (i & 8) + h |= PixelEven; + if (i & 4) + h |= PixelEven << 8; + if (i & 2) + h |= PixelEven << 16; + if (i & 1) + h |= PixelEven << 24; + if (i & 8) + l |= PixelEven; + if (i & 4) + l |= PixelEven << 8; + if (i & 2) + l |= PixelEven << 16; + if (i & 1) + l |= PixelEven << 24; +#else + if (i & 8) + h |= (PixelEven << 24); + if (i & 4) + h |= (PixelEven << 16); + if (i & 2) + h |= (PixelEven << 8); + if (i & 1) + h |= PixelEven; + if (i & 8) + l |= (PixelEven << 24); + if (i & 4) + l |= (PixelEven << 16); + if (i & 2) + l |= (PixelEven << 8); + if (i & 1) + l |= PixelEven; +#endif + + even_high[bitshift][i] = h; + even_low[bitshift][i] = l; + } + PixelEven <<= 2; + PixelOdd <<= 2; + } + + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; + GFX.DepthDelta = GFX.SubZBuffer - GFX.ZBuffer; + //GFX.InfoStringTimeout = 0; + //GFX.InfoString = NULL; + + PPU.BG_Forced = 0; + IPPU.OBJChanged = TRUE; + + IPPU.DirectColourMapsNeedRebuild = TRUE; + DrawTilePtr = DrawTile16; + DrawClippedTilePtr = DrawClippedTile16; + DrawLargePixelPtr = DrawLargePixel16; + DrawHiResTilePtr= DrawHiResTile16; + DrawHiResClippedTilePtr = DrawHiResClippedTile16; + S9xFixColourBrightness (); + + if (!(GFX.X2 = (uint16 *) malloc (sizeof (uint16) * 0x10000))) + return (FALSE); + + if (!(GFX.ZERO_OR_X2 = (uint16 *) malloc (sizeof (uint16) * 0x10000)) || + !(GFX.ZERO = (uint16 *) malloc (sizeof (uint16) * 0x10000))) + { + if (GFX.ZERO_OR_X2) + { + free ((char *) GFX.ZERO_OR_X2); + GFX.ZERO_OR_X2 = NULL; + } + if (GFX.X2) + { + free ((char *) GFX.X2); + GFX.X2 = NULL; + } + return (FALSE); + } + uint32 r, g, b; + + // Build a lookup table that multiplies a packed RGB value by 2 with + // saturation. + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r << 1; + if (r2 > MAX_RED) + r2 = MAX_RED; + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g << 1; + if (g2 > MAX_GREEN) + g2 = MAX_GREEN; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b << 1; + if (b2 > MAX_BLUE) + b2 = MAX_BLUE; + GFX.X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } + ZeroMemory (GFX.ZERO, 0x10000 * sizeof (uint16)); + ZeroMemory (GFX.ZERO_OR_X2, 0x10000 * sizeof (uint16)); + // Build a lookup table that if the top bit of the color value is zero + // then the value is zero, otherwise multiply the value by 2. Used by + // the color subtraction code. + +#if defined(OLD_COLOUR_BLENDING) + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 = (r2 << 1) & MAX_RED; + + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 = (g2 << 1) & MAX_GREEN; + + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 = (b2 << 1) & MAX_BLUE; + + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } +#else + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 = (r2 << 1) & MAX_RED; + + if (r2 == 0) + r2 = 1; + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 = (g2 << 1) & MAX_GREEN; + + if (g2 == 0) + g2 = 1; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 = (b2 << 1) & MAX_BLUE; + + if (b2 == 0) + b2 = 1; + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } +#endif + + // Build a lookup table that if the top bit of the color value is zero + // then the value is zero, otherwise its just the value. + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 &= ~0x10; + + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 &= ~GREEN_HI_BIT; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 &= ~0x10; + + GFX.ZERO [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } + + return (TRUE); +} + +void S9xGraphicsDeinit (void) +{ + // Free any memory allocated in S9xGraphicsInit + if (GFX.X2) + { + free ((char *) GFX.X2); + GFX.X2 = NULL; + } + if (GFX.ZERO_OR_X2) + { + free ((char *) GFX.ZERO_OR_X2); + GFX.ZERO_OR_X2 = NULL; + } + if (GFX.ZERO) + { + free ((char *) GFX.ZERO); + GFX.ZERO = NULL; + } +} + +void S9xBuildDirectColourMaps () +{ + for (uint32 p = 0; p < 8; p++) + { + for (uint32 c = 0; c < 256; c++) + { +// XXX: Brightness + /* + DirectColourMaps [p][c] = BUILD_PIXEL (IPPU.XB[((c & 7) << 2) | ((p & 1) << 1)], + IPPU.XB[((c & 0x38) >> 1) | (p & 2)], + IPPU.XB[((c & 0xc0) >> 3) | (p & 4)]); + */ + DirectColourMaps [p][c] = BUILD_PIXEL (((c & 7) << 2) | ((p & 1) << 1), + ((c & 0x38) >> 1) | (p & 2), + ((c & 0xc0) >> 3) | (p & 4)); + + } + } + IPPU.DirectColourMapsNeedRebuild = FALSE; +} + +void S9xStartScreenRefresh () +{ + RESET_ROPS(0); + + if (IPPU.RenderThisFrame) + { +#ifndef _SNESPPC + if (!S9xInitUpdate ()) + { + IPPU.RenderThisFrame = FALSE; + return; + } +#endif + IPPU.RenderedFramesCount++; + IPPU.PreviousLine = IPPU.CurrentLine = 0; + IPPU.MaxBrightness = PPU.Brightness; + IPPU.LatchedBlanking = PPU.ForcedBlanking; + IPPU.LatchedInterlace = (Memory.FillRAM[0x2133] & 1); + IPPU.RenderedScreenWidth = 256; + IPPU.RenderedScreenHeight = PPU.ScreenHeight; + IPPU.DoubleWidthPixels = FALSE; + + PPU.RecomputeClipWindows = TRUE; + PPU.BG[0].OffsetsChanged = 0; + PPU.BG[1].OffsetsChanged = 0; + PPU.BG[2].OffsetsChanged = 0; + PPU.BG[3].OffsetsChanged = 0; + GFX.DepthDelta = GFX.SubZBuffer - GFX.ZBuffer; + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; + } + + if (++IPPU.FrameCount % Memory.ROMFramesPerSecond == 0) + { + IPPU.DisplayedRenderedFrameCount = IPPU.RenderedFramesCount; + IPPU.RenderedFramesCount = 0; + IPPU.FrameCount = 0; + } +} + +void RenderLine (uint8 C) +{ + if (IPPU.RenderThisFrame) + { + + LineData[C].BG[0].VOffset = PPU.BG[0].VOffset + 1; + LineData[C].BG[0].HOffset = PPU.BG[0].HOffset; + LineData[C].BG[1].VOffset = PPU.BG[1].VOffset + 1; + LineData[C].BG[1].HOffset = PPU.BG[1].HOffset; + + //if (PPU.BGMode == 7) + if ((Memory.FillRAM[0x2105] & 7) == 7) + { + struct SLineMatrixData *p = &LineMatrixData [C]; + p->MatrixA = PPU.MatrixA; + p->MatrixB = PPU.MatrixB; + p->MatrixC = PPU.MatrixC; + p->MatrixD = PPU.MatrixD; + p->CentreX = PPU.CentreX; + p->CentreY = PPU.CentreY; + } + else + { + if (Settings.StarfoxHack && PPU.BG[2].VOffset == 0 && + PPU.BG[2].HOffset == 0xe000) + { + LineData[C].BG[2].VOffset = 0xe1; + LineData[C].BG[2].HOffset = 0; + } + else + { + LineData[C].BG[2].VOffset = PPU.BG[2].VOffset + 1; + LineData[C].BG[2].HOffset = PPU.BG[2].HOffset; + LineData[C].BG[3].VOffset = PPU.BG[3].VOffset + 1; + LineData[C].BG[3].HOffset = PPU.BG[3].HOffset; + } + + } + IPPU.CurrentLine = C + 1; + } +} + + +void S9xEndScreenRefresh() +{ + IPPU.HDMAStarted = FALSE; + +//RC + if (IPPU.RenderThisFrame) + { + FLUSH_REDRAW (); + //if (IPPU.ColorsChanged) + //{ + IPPU.ColorsChanged = FALSE; + //} + + S9xDeinitUpdate (IPPU.RenderedScreenWidth, IPPU.RenderedScreenHeight, + 1); + } +#ifndef RC_OPTIMIZED + S9xApplyCheats (); +#endif + + +#ifdef DEBUGGER + if (CPU.Flags & FRAME_ADVANCE_FLAG) + { + if (ICPU.FrameAdvanceCount) + { + ICPU.FrameAdvanceCount--; + IPPU.RenderThisFrame = TRUE; + IPPU.FrameSkip = 0; + } + else + { + CPU.Flags &= ~FRAME_ADVANCE_FLAG; + CPU.Flags |= DEBUG_MODE_FLAG; + } + } +#endif + +/* + if (CPU.SRAMModified) + { + if (!CPU.AutoSaveTimer) + { + if (!(CPU.AutoSaveTimer = Settings.AutoSaveDelay * Memory.ROMFramesPerSecond)) + CPU.SRAMModified = FALSE; + } + else + { + if (!--CPU.AutoSaveTimer) + { + S9xAutoSaveSRAM (); + CPU.SRAMModified = FALSE; + } + } + } +*/ +} + +void S9xSetInfoString (const char *string) +{ + } + + + +int TileRenderer; +TileRendererSet TileRenderers[] = { + {DrawTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 0 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 1 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedAdd1_2, DrawClippedTile16FixedAdd1_2, DrawLargePixel16Add1_2}, // 2 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawTile16Add1_2, DrawClippedTile16Add1_2, DrawLargePixel16Add1_2}, // 3 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 4 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 5 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedSub1_2, DrawClippedTile16FixedSub1_2, DrawLargePixel16Sub1_2}, // 6 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawTile16Sub1_2, DrawClippedTile16Sub1_2, DrawLargePixel16Sub1_2}, // 7 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawTile16, DrawClippedTile16, DrawLargePixel16} // 8 -> normal + }; +#ifdef __FAST_OBJS__ +TileRendererSet TileRenderersNoZ[] = { + {DrawNoZTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 0 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawNoZTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 1 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedAdd1_2, DrawClippedTile16FixedAdd1_2, DrawLargePixel16Add1_2}, // 2 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawNoZTile16Add1_2, DrawClippedTile16Add1_2, DrawLargePixel16Add1_2}, // 3 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawNoZTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 4 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawNoZTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 5 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedSub1_2, DrawClippedTile16FixedSub1_2, DrawLargePixel16Sub1_2}, // 6 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawNoZTile16Sub1_2, DrawClippedTile16Sub1_2, DrawLargePixel16Sub1_2}, // 7 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawNoZTile16, DrawClippedTile16, DrawLargePixel16} // 8 -> normal + }; +#endif +INLINE void SelectTileRenderer (bool8_32 normal, bool NoZ = false) +{ + if (normal) { + TileRenderer = 8; + } + else { + TileRenderer = (((GFX.r2131 >> 5) & 0x06) | ((GFX.r2130 >> 1) & 1)); + } + +#ifdef __DEBUG__ + char *TRName[] = { + "Add", "Add", "FixedAdd1_2", "Add1_2", + "Sub", "Sub", "FixedSub1_2", "Sub1_2", + "Normal" + }; + printf("SelectTileRenderer: %s\n", TRName[TileRenderer]); +#endif + +#ifdef __FAST_OBJS__ + if (NoZ) { + DrawTilePtr = TileRenderersNoZ[TileRenderer].Normal; + DrawClippedTilePtr = TileRenderersNoZ[TileRenderer].Clipped; + DrawLargePixelPtr = TileRenderersNoZ[TileRenderer].Large; + } + else { +#endif + DrawTilePtr = TileRenderers[TileRenderer].Normal; + DrawClippedTilePtr = TileRenderers[TileRenderer].Clipped; + DrawLargePixelPtr = TileRenderers[TileRenderer].Large; +#ifdef __FAST_OBJS__ + } +#endif +} + +void S9xSetupOBJ () +{ + int SmallSize; + int LargeSize; + + switch (PPU.OBJSizeSelect) + { + case 0: + SmallSize = 8; + LargeSize = 16; + break; + case 1: + SmallSize = 8; + LargeSize = 32; + break; + case 2: + SmallSize = 8; + LargeSize = 64; + break; + case 3: + SmallSize = 16; + LargeSize = 32; + break; + case 4: + SmallSize = 16; + LargeSize = 64; + break; + case 5: + default: + SmallSize = 32; + LargeSize = 64; + break; + } + + int C = 0; + + int FirstSprite = PPU.FirstSprite & 0x7f; + int S = FirstSprite; + do + { + int Size; + if (PPU.OBJ [S].Size) + Size = LargeSize; + else + Size = SmallSize; + + long VPos = PPU.OBJ [S].VPos; + + if (VPos >= PPU.ScreenHeight) + VPos -= 256; + if (PPU.OBJ [S].HPos < 256 && PPU.OBJ [S].HPos > -Size && + VPos < PPU.ScreenHeight && VPos > -Size) + { +#ifndef __FAST_OBJS__ + GFX.OBJList[C++] = S; +#else + int x = 0; + int a, b; + // -- Sort objects (from low to high priority) + while (x < C) { + a = GFX.OBJList[x]; + if (PPU.OBJ[a].Priority >= PPU.OBJ[S].Priority) break; + x++; + } + + GFX.OBJList[x] = S; + x++; C++; + + while (x < C) { + b = GFX.OBJList[x]; + GFX.OBJList[x] = a; + a = b; + x++; + } +#endif + // -- + GFX.Sizes[S] = Size; + GFX.VPositions[S] = VPos; + } + S = (S + 1) & 0x7f; + } while (S != FirstSprite); + + // Terminate the list + GFX.OBJList [C] = -1; + IPPU.OBJChanged = FALSE; +} + +void DrawOBJS (bool8_32 OnMain = FALSE, uint8 D = 0) +{ + int bg_ta_ns; + int bg_ta; + uint32 O; + uint32 BaseTile, Tile; + + CHECK_SOUND(); + + BG.BitShift = 4; + SelectConvertTile(); + BG.TileShift = 5; + //BG.TileAddress = PPU.OBJNameBase; + BG.StartPalette = 128; + BG.PaletteShift = 4; + BG.PaletteMask = 7; + BG.Buffer = IPPU.TileCache [TILE_4BIT]; + BG.Buffered = IPPU.TileCached [TILE_4BIT]; + //BG.NameSelect = PPU.OBJNameSelect; + BG.DirectColourMode = FALSE; + + SelectPalette(); + bg_ta = PPU.OBJNameBase; + bg_ta_ns = bg_ta + PPU.OBJNameSelect; + + GFX.Z1 = D + 2; + + DBG("Draw Objects.\n"); + + int I = 0; + for (int S = GFX.OBJList [I++]; S >= 0; S = GFX.OBJList [I++]) + { + int VPos = GFX.VPositions [S]; + int Size = GFX.Sizes[S]; + int TileInc = 1; + int Offset; + + if (VPos + Size <= (int) GFX.StartY || VPos > (int) GFX.EndY) + continue; + + if (OnMain && SUB_OR_ADD(4)) + { +#ifndef __FAST_OBJS__ + SelectTileRenderer (!GFX.Pseudo && PPU.OBJ [S].Palette < 4, false); +#else + SelectTileRenderer (!GFX.Pseudo && PPU.OBJ [S].Palette < 4, true); +#endif + } + + BaseTile = PPU.OBJ[S].Name | (PPU.OBJ[S].Palette << 10); + + if (PPU.OBJ[S].HFlip) + { + BaseTile += ((Size >> 3) - 1) | H_FLIP; + TileInc = -1; + } + + if (PPU.OBJ[S].VFlip) BaseTile |= V_FLIP; + //BaseTile |= PPU.OBJ[S].VFlip << 15; + + int clipcount = GFX.pCurrentClip->Count [4]; + if (!clipcount) clipcount = 1; + + GFX.Z2 = (PPU.OBJ[S].Priority + 1) * 4 + D; + + for (int clip = 0; clip < clipcount; clip++) + { + int Left; + int Right; + if (!GFX.pCurrentClip->Count [4]) + { + Left = 0; + Right = 256; + } + else + { + Left = GFX.pCurrentClip->Left [clip][4]; + Right = GFX.pCurrentClip->Right [clip][4]; + } + + if (Right <= Left || PPU.OBJ[S].HPos + Size <= Left || + PPU.OBJ[S].HPos >= Right) + continue; + + for (int Y = 0; Y < Size; Y += 8) + { + if (VPos + Y + 7 >= (int) GFX.StartY && VPos + Y <= (int) GFX.EndY) + { + int StartLine; + int TileLine; + int LineCount; + int Last; + + if ((StartLine = VPos + Y) < (int) GFX.StartY) + { + StartLine = GFX.StartY - StartLine; + LineCount = 8 - StartLine; + } + else + { + StartLine = 0; + LineCount = 8; + } + if ((Last = VPos + Y + 7 - GFX.EndY) > 0) + if ((LineCount -= Last) <= 0) + break; + + TileLine = StartLine << 3; + + O = (VPos + Y + StartLine) * GFX_PPL; + if (!PPU.OBJ[S].VFlip) Tile = BaseTile + (Y << 1); + else Tile = BaseTile + ((Size - Y - 8) << 1); + + if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + else BG.TileAddress = bg_ta; + + int Middle = Size >> 3; + if (PPU.OBJ[S].HPos < Left) + { + Tile += ((Left - PPU.OBJ[S].HPos) >> 3) * TileInc; + Middle -= (Left - PPU.OBJ[S].HPos) >> 3; + O += Left * GFX_PIXSIZE; + if ((Offset = (Left - PPU.OBJ[S].HPos) & 7)) + { + O -= Offset * GFX_PIXSIZE; + int W = 8 - Offset; + int Width = Right - Left; + if (W > Width) W = Width; + //if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + //else BG.TileAddress = bg_ta; + (*DrawClippedTilePtr) (Tile, O, Offset, W, TileLine, LineCount); + + if (W >= Width) + continue; + Tile += TileInc; + Middle--; + O += 8 * GFX_PIXSIZE; + } + } + else + O += PPU.OBJ[S].HPos * GFX_PIXSIZE; + + if (PPU.OBJ[S].HPos + Size >= Right) + { + Middle -= ((PPU.OBJ[S].HPos + Size + 7) - + Right) >> 3; + Offset = (Right - (PPU.OBJ[S].HPos + Size)) & 7; + } + else + Offset = 0; + + for (int X = 0; X < Middle; X++, O += 8 * GFX_PIXSIZE, + Tile += TileInc) + { + //if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + //else BG.TileAddress = bg_ta; + (*DrawTilePtr) (Tile, O, TileLine, LineCount); + } + if (Offset) + { + //if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + //else BG.TileAddress = bg_ta; + (*DrawClippedTilePtr) (Tile, O, 0, Offset, TileLine, LineCount); + } + } + } + } + } +} +void DrawBackgroundMosaic (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackgroundMosaic(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + CHECK_SOUND(); + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint8 depths [2] = {Z1, Z2}; + + if (BGMode == 0) + BG.StartPalette = bg << 5; + else + BG.StartPalette = 0; + SelectPalette(); + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(((uint8*)SC1-Memory.VRAM)>=0x10000) + SC1-=0x08000; + + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + uint32 Lines; + uint32 OffsetMask; + uint32 OffsetShift; + + if (BG.TileSize == 16) + { + OffsetMask = 0x3ff; + OffsetShift = 4; + } + else + { + OffsetMask = 0x1ff; + OffsetShift = 3; + } + + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines) + { + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + uint32 MosaicOffset = Y % PPU.Mosaic; + + for (Lines = 1; Lines < PPU.Mosaic - MosaicOffset; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + uint32 MosaicLine = VOffset + Y - MosaicOffset; + + if (Y + Lines > GFX.EndY) + Lines = GFX.EndY + 1 - Y; + uint32 VirtAlign = (MosaicLine & 7) << 3; + + uint16 *b1; + uint16 *b2; + + uint32 ScreenLine = MosaicLine >> OffsetShift; + uint32 Rem16 = MosaicLine & 15; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + uint16 *t; + uint32 Left = 0; + uint32 Right = 256; + + uint32 ClipCount = GFX.pCurrentClip->Count [bg]; + uint32 HPos = HOffset; + uint32 PixWidth = PPU.Mosaic; + + if (!ClipCount) + ClipCount = 1; + + for (uint32 clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [bg]) + { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + uint32 r = Left % PPU.Mosaic; + HPos = HOffset + Left; + PixWidth = PPU.Mosaic - r; + } + uint32 s = Y * GFX_PPL + Left * GFX_PIXSIZE; + for (uint32 x = Left; x < Right; x += PixWidth, + s += PixWidth * GFX_PIXSIZE, + HPos += PixWidth, PixWidth = PPU.Mosaic) + { + uint32 Quot = (HPos & OffsetMask) >> 3; + + if (x + PixWidth >= Right) + PixWidth = Right - x; + + if (BG.TileSize == 8) + { + if (Quot > 31) + t = b2 + (Quot & 0x1f); + else + t = b1 + Quot; + } + else + { + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + } + + Tile = READ_2BYTES (t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + // Draw tile... + if (BG.TileSize != 8) + { + if (Tile & H_FLIP) + { + // Horizontal flip, but what about vertical flip ? + if (Tile & V_FLIP) + { + // Both horzontal & vertical flip + if (Rem16 < 8) + { + (*DrawLargePixelPtr) (Tile + 17 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + 1 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + else + { + // Horizontal flip only + if (Rem16 > 7) + { + (*DrawLargePixelPtr) (Tile + 17 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + 1 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } + else + { + // No horizontal flip, but is there a vertical flip ? + if (Tile & V_FLIP) + { + // Vertical flip only + if (Rem16 < 8) + { + (*DrawLargePixelPtr) (Tile + 16 + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + else + { + // Normal unflipped + if (Rem16 > 7) + { + (*DrawLargePixelPtr) (Tile + 16 + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } + } + else + (*DrawLargePixelPtr) (Tile, s, HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } +} + +void DrawBackgroundOffset (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackgroundOffset(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + + CHECK_SOUND(); + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint16 *BPS0; + uint16 *BPS1; + uint16 *BPS2; + uint16 *BPS3; + uint32 Width; + int VOffsetOffset = BGMode == 4 ? 0 : 32; + uint8 depths [2] = {Z1, Z2}; + + BG.StartPalette = 0; + SelectPalette(); + + BPS0 = (uint16 *) &Memory.VRAM[PPU.BG[2].SCBase << 1]; + + if (PPU.BG[2].SCSize & 1) + BPS1 = BPS0 + 1024; + else + BPS1 = BPS0; + + if (PPU.BG[2].SCSize & 2) + BPS2 = BPS1 + 1024; + else + BPS2 = BPS0; + + if (PPU.BG[2].SCSize & 1) + BPS3 = BPS2 + 1024; + else + BPS3 = BPS2; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(((uint8*)SC1-Memory.VRAM)>=0x10000) + SC1-=0x08000; + + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + static const int Lines = 1; + int OffsetMask; + int OffsetShift; + int OffsetEnableMask = 1 << (bg + 13); + + if (BG.TileSize == 16) + { + OffsetMask = 0x3ff; + OffsetShift = 4; + } + else + { + OffsetMask = 0x1ff; + OffsetShift = 3; + } + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y++) + { + uint32 VOff = LineData [Y].BG[2].VOffset - 1; + uint32 HOff = LineData [Y].BG[2].HOffset; + int VirtAlign; + int ScreenLine = VOff >> 3; + uint16 *s0; + uint16 *s1; + uint16 *s2; +#ifdef __DEBUG__ + printf("Processing line: %d\n", Y); +#endif + if (ScreenLine & 0x20) + s1 = BPS2, s2 = BPS3; + else + s1 = BPS0, s2 = BPS1; + + s1 += (ScreenLine & 0x1f) << 5; + s2 += (ScreenLine & 0x1f) << 5; + + if(BGMode != 4) + { + if((ScreenLine & 0x1f) == 0x1f) + { + if(ScreenLine & 0x20) + VOffsetOffset = BPS0 - BPS2 - 0x1f*32; + else + VOffsetOffset = BPS2 - BPS0 - 0x1f*32; + } + else + { + VOffsetOffset = 32; + } + } + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + + for (int clip = 0; clip < clipcount; clip++) + { + uint32 Left; + uint32 Right; +#ifdef __DEBUG__ + printf("Processing clip: %d/%d\n", clip, clipcount); +#endif + + if (!GFX.pCurrentClip->Count [bg]) + { + Left = 0; + Right = 256; + } + else + { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) + continue; + } + + uint32 VOffset; + uint32 HOffset; + uint32 LineHOffset=LineData [Y].BG[bg].HOffset; + uint32 Offset; + uint32 HPos; + uint32 Quot; + uint32 Count; + uint16 *t; + uint32 Quot2; + uint32 VCellOffset; + uint32 HCellOffset; + uint16 *b1; + uint16 *b2; + uint32 TotalCount = 0; + uint32 MaxCount = 8; + + uint32 s = Left * GFX_PIXSIZE + Y * GFX_PPL; + bool8_32 left_hand_edge = (Left == 0); + Width = Right - Left; + + if (Left & 7) + MaxCount = 8 - (Left & 7); + + while (Left < Right) + { +#ifdef __DEBUG__ + printf("Left: %d, Right: %d\n", Left, Right); +#endif + if (left_hand_edge) + { + // The SNES offset-per-tile background mode has a + // hardware limitation that the offsets cannot be set + // for the tile at the left-hand edge of the screen. + VOffset = LineData [Y].BG[bg].VOffset; + HOffset = LineHOffset; + left_hand_edge = FALSE; + } + else + { + // All subsequent offset tile data is shifted left by one, + // hence the - 1 below. + Quot2 = ((HOff + Left - 1) & OffsetMask) >> 3; + + if (Quot2 > 31) + s0 = s2 + (Quot2 & 0x1f); + else + s0 = s1 + Quot2; + + HCellOffset = READ_2BYTES (s0); + + if (BGMode == 4) + { + VOffset = LineData [Y].BG[bg].VOffset; + HOffset=LineHOffset; + if ((HCellOffset & OffsetEnableMask)) + { + if (HCellOffset & 0x8000) + VOffset = HCellOffset + 1; + else + HOffset = HCellOffset; + } + } + else + { + VCellOffset = READ_2BYTES (s0 + VOffsetOffset); + if ((VCellOffset & OffsetEnableMask)) + VOffset = VCellOffset + 1; + else + VOffset = LineData [Y].BG[bg].VOffset; + + if ((HCellOffset & OffsetEnableMask)) + HOffset = (HCellOffset & ~7)|(LineHOffset&7); + else + HOffset=LineHOffset; + } + } + VirtAlign = ((Y + VOffset) & 7) << 3; + ScreenLine = (VOffset + Y) >> OffsetShift; + + int tx_index; + tx_index = ( ((VOffset + Y) & 15) <= 7 ) << 3; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + HPos = (HOffset + Left) & OffsetMask; + + Quot = HPos >> 3; + + if (BG.TileSize == 8) + { + if (Quot > 31) + t = b2 + (Quot & 0x1f); + else + t = b1 + Quot; + } + else + { + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + } + + if (MaxCount + TotalCount > Width) + MaxCount = Width - TotalCount; + + Offset = HPos & 7; + + Count = 8 - Offset; + if (Count > MaxCount) + Count = MaxCount; + + s -= Offset * GFX_PIXSIZE; + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + if (Tile != TileBlank) + if (BG.TileSize == 8) + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + else + { + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + } + + Left += Count; + TotalCount += Count; + s += (Offset + Count) * GFX_PIXSIZE; + MaxCount = 8; + } + } + } +} + +void DrawBackgroundMode5 (uint32 /* BGMODE */, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackgroundMode5(?, %i, %i, %i)\n", bg, Z1, Z2); +#endif + + CHECK_SOUND(); + + uint8 depths [2] = {Z1, Z2}; + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 Width; + + BG.StartPalette = 0; + SelectPalette(); + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if ((PPU.BG[bg].SCSize & 1)) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if((SC1-(unsigned short*)Memory.VRAM)>0x10000) + SC1=(uint16*)&Memory.VRAM[(((uint8*)SC1)-Memory.VRAM)%0x10000]; + + if ((PPU.BG[bg].SCSize & 2)) + SC2 = SC1 + 1024; + else SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + if ((PPU.BG[bg].SCSize & 1)) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + int Lines; + int VOffsetMask; + int VOffsetShift; + + if (BG.TileSize == 16) + { + VOffsetMask = 0x3ff; + VOffsetShift = 4; + } + else + { + VOffsetMask = 0x1ff; + VOffsetShift = 3; + } + int endy = GFX.EndY; + + for (int Y = GFX.StartY; Y <= endy; Y += Lines) + { + //int y = Y; + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + for (Lines = 1; Lines < 8 - VirtAlign; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + HOffset <<= 1; + if (Y + Lines > endy) + Lines = endy + 1 - Y; + + int ScreenLine = (VOffset + Y) >> VOffsetShift; + int t1; + int t2; + if (((VOffset + Y) & 15) > 7) + { + t1 = 16; + t2 = 0; + } + else + { + t1 = 0; + t2 = 16; + } + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + for (int clip = 0; clip < clipcount; clip++) + { + int Left; + int Right; + + if (!GFX.pCurrentClip->Count [bg]) + { + Left = 0; + Right = 512; + } + else + { + Left = GFX.pCurrentClip->Left [clip][bg] * 2; + Right = GFX.pCurrentClip->Right [clip][bg] * 2; + + if (Right <= Left) + continue; + } + + uint32 s = (Left>>1) * GFX_PIXSIZE + Y * GFX_PPL; + uint32 HPos = (HOffset + Left * GFX_PIXSIZE) & 0x3ff; + + uint32 Quot = HPos >> 3; + uint32 Count = 0; + + uint16 *t; + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + + Width = Right - Left; + // Left hand edge clipped tile + if (HPos & 7) + { + int Offset = (HPos & 7); + Count = 8 - Offset; + if (Count > Width) + Count = Width; + s -= (Offset>>1); + Tile = READ_2BYTES (t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResClippedTilePtr) (Tile + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + t1 + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResClippedTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResClippedTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResClippedTilePtr) (Tile + t2 + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + + t += Quot & 1; + if (Quot == 63) + t = b2; + else if (Quot == 127) + t = b1; + Quot++; + s += 4; + } + + // Middle, unclipped tiles + Count = Width - Count; + int Middle = Count >> 3; + Count &= 7; + for (int C = Middle; C > 0; s += 4, Quot++, C--) + { + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResTilePtr) (Tile + (Quot & 1), + s, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResTilePtr) (Tile + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResTilePtr) (Tile + t1 + (Quot & 1), + s, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResTilePtr) (Tile + t2 + (Quot & 1), + s, VirtAlign, Lines); + } + } + + t += Quot & 1; + if (Quot == 63) + t = b2; + else + if (Quot == 127) + t = b1; + } + + // Right-hand edge clipped tiles + if (Count) + { + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResClippedTilePtr) (Tile + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + t1 + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResClippedTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResClippedTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResClippedTilePtr) (Tile + t2 + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + } + } + } +} + +void DrawBackground_8(uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackground_8(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + //uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 depths [2] = {Z1, Z2}; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + SC1 = SC0 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(SC1 >= (unsigned short*)(Memory.VRAM+0x10000)) SC1 = (uint16*)&Memory.VRAM[((uint8*)SC1-&Memory.VRAM[0]) & 0xffff]; + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) SC2 -= 0x08000; + + SC3 = SC2 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) SC3 -= 0x08000; + + int Lines; + + int oc = PPU.BG[bg].OffsetsChanged; + uint32 VOffset, HOffset; + if (!oc) { + VOffset = LineData [GFX.StartY].BG[bg].VOffset; + HOffset = LineData [GFX.StartY].BG[bg].HOffset; + } + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines){ + int y_ppl = Y * GFX_PPL; + if (oc) { + VOffset = LineData [Y].BG[bg].VOffset; + HOffset = LineData [Y].BG[bg].HOffset; + } + int VirtAlign = (Y + VOffset) & 7; + + int maxLines = GFX.EndY - Y + 1; + if ((8 - VirtAlign) < maxLines) maxLines = (8 - VirtAlign); + + if (oc) { + for (Lines = 1; Lines < maxLines; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + } else Lines = maxLines; + + VirtAlign <<= 3; + + uint32 ScreenLine = (VOffset + Y) >> 3; + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + uint32 Left; + uint32 Right; + int clip = 0; + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) { + Left = 0; + Right = 256; + } + + do { + if (clipcount) { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) {clip++; continue;} + } + + uint32 s = Left + y_ppl; + uint32 HPos = (HOffset + Left) & 0x1ff; + uint32 Quot = HPos >> 3; + uint32 Count = 0; + uint16 *t; + uint16 *b; + + if (Quot > 31) { + t = b2 + (Quot & 0x1f); + b = b1; + Quot -= 32; + } + else { + t = b1 + Quot; + b = b2; + } + + uint32 Width = Right - Left; + + // Left hand edge clipped tile + uint32 Offset = (HPos & 7); + if (Offset){ + Count = 8 - Offset; + if (Count > Width) Count = Width; + s -= Offset; + //uint32 Tile = READ_2BYTES(t); + register uint32 Tile = *(t++); + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + //t++; + if (Quot == 31) t = b; + //else if (Quot == 63) t = b1; + Quot++; + s += 8; + } + + // Middle, unclipped tiles + Count = Width - Count; + for (int C = Count >> 3; C > 0; s += 8, Quot++, C--){ + //uint32 Tile = READ_2BYTES(t); + register uint32 Tile = *(t++); + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawTilePtr) (Tile, s, VirtAlign, Lines); + } + + //t++; + if (Quot == 31) t = b; + //else if (Quot == 63) t = b1; + } + + // Right-hand edge clipped tiles + if (Count & 7){ + //uint32 Tile = READ_2BYTES(t); + register uint32 Tile = *t; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, 0, Count & 7, VirtAlign, Lines); + } + } + clip ++; + } while (clip < clipcount); + } +} + +void DrawBackground_16 (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackground_16(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + //uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 depths [2] = {Z1, Z2}; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + SC1 = SC0 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(SC1 >= (unsigned short*)(Memory.VRAM+0x10000)) SC1 = (uint16*)&Memory.VRAM[((uint8*)SC1-&Memory.VRAM[0]) & 0xffff]; + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) SC2 -= 0x08000; + + SC3 = SC2 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) SC3 -= 0x08000; + + int Lines; + + int oc = PPU.BG[bg].OffsetsChanged; + uint32 VOffset, HOffset; + if (!oc) { + VOffset = LineData [GFX.StartY].BG[bg].VOffset; + HOffset = LineData [GFX.StartY].BG[bg].HOffset; + } + + TileBlank = 0xFFFFFFFF; + unsigned int tb1 = 0xffffffff; + unsigned int tb2 = 0xffffffff; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines){ + int y_ppl = Y * GFX_PPL; + if (oc) { + VOffset = LineData [Y].BG[bg].VOffset; + HOffset = LineData [Y].BG[bg].HOffset; + } + int VirtAlign = (Y + VOffset) & 7; + + int maxLines = GFX.EndY - Y + 1; + if ((8 - VirtAlign) < maxLines) maxLines = (8 - VirtAlign); + + if (oc) { + for (Lines = 1; Lines < maxLines; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + } else Lines = maxLines; + + VirtAlign <<= 3; + + uint32 ScreenLine = (VOffset + Y) >> 4; + int tx_index = ( ((VOffset + Y) & 15) <= 7 ) << 3; + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + uint32 Left; + uint32 Right; + int clip = 0; + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) { + Left = 0; + Right = 256; + } + + do { + if (clipcount) { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) {clip++; continue;} + } + + uint32 s = Left + y_ppl; + uint32 HPos = (HOffset + Left) & 0x3ff; + uint32 Quot = HPos >> 3; + uint32 Count = 0; + uint16 *t; + uint16 *b; + + if (Quot > 63) { + t = b2 + ((Quot >> 1) & 0x1f); + b = b1; + Quot -= 64; + } + else { + t = b1 + (Quot >> 1); + b = b2; + } + + + uint32 Width = Right - Left; + + register uint32 Tile; + if (Quot & 1) { + Tile = *(t++); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13)]; + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + } + + // Left hand edge clipped tile + uint32 Offset = (HPos & 7); + if (Offset){ + Count = 8 - Offset; + if (Count > Width) Count = Width; + s -= Offset; + if (!(Quot & 1)) { + Tile = *(t++); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13)]; + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (Tile != tb1) { + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + tb1 = TileBlank; + } + } + else { + if (Tile & H_FLIP) Tile--; + else Tile++; + if (Quot == 63) t = b; + if (Tile != tb2) { + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + tb2 = TileBlank; + } + } + Quot++; + s += 8; + } + + // Middle, unclipped tiles + Count = Width - Count; + for (int C = Count >> 3; C > 0; s += 8, Quot++, C--){ + if (!(Quot & 1)) { + Tile = *(t++); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13)]; + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (Tile != tb1){ + (*DrawTilePtr) (Tile, s, VirtAlign, Lines); + tb1 = TileBlank; + } + } + else { + if (Tile & H_FLIP) Tile--; + else Tile++; + if (Quot == 63) t = b; + if (Tile != tb2){ + (*DrawTilePtr) (Tile, s, VirtAlign, Lines); + tb2 = TileBlank; + } + } + } + + // Right-hand edge clipped tiles + if (Count & 7){ + if (!(Quot & 1)) { + Tile = *(t++); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13)]; + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (Tile != tb1) (*DrawClippedTilePtr) (Tile, s, 0, Count & 7, VirtAlign, Lines); + } + else { + if (Tile & H_FLIP) Tile--; + else Tile++; + if (Tile != tb2) (*DrawClippedTilePtr) (Tile, s, 0, Count & 7, VirtAlign, Lines); + } + } + clip ++; + } while (clip < clipcount); + } +} + + +inline void DrawBackground (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +//StartAnalyze(); + + BG.TileSize = BGSizes [PPU.BG[bg].BGSize]; + BG.BitShift = BitShifts[BGMode][bg]; + SelectConvertTile(); + BG.TileShift = TileShifts[BGMode][bg]; + BG.TileAddress = PPU.BG[bg].NameBase << 1; + //BG.NameSelect = 0; + BG.Buffer = IPPU.TileCache [Depths [BGMode][bg]]; + BG.Buffered = IPPU.TileCached [Depths [BGMode][bg]]; + BG.PaletteShift = PaletteShifts[BGMode][bg]; + BG.PaletteMask = PaletteMasks[BGMode][bg]; + BG.DirectColourMode = (BGMode == 3 || BGMode == 4) && bg == 0 && (GFX.r2130 & 1); + + DBG("Draw Background.\n"); + + if (IPPU.DirectColourMapsNeedRebuild && BG.DirectColourMode) S9xBuildDirectColourMaps (); + + if (PPU.BGMosaic [bg] && PPU.Mosaic > 1){ + DrawBackgroundMosaic (BGMode, bg, Z1, Z2); + return; + + } + switch (BGMode) + { + case 2: + case 4: // Used by Puzzle Bobble + DrawBackgroundOffset (BGMode, bg, Z1, Z2); + break; + + case 5: + case 6: // XXX: is also offset per tile. + DrawBackgroundMode5 (BGMode, bg, Z1, Z2); + break; + case 0: + case 1: + case 3: + CHECK_SOUND(); + + if (BGMode == 0) BG.StartPalette = bg << 5; + else BG.StartPalette = 0; + SelectPalette(); + + if (BG.TileSize == 8) DrawBackground_8 (BGMode, bg, Z1, Z2); + else DrawBackground_16 (BGMode, bg, Z1, Z2); + break; + } +} + +#define _BUILD_SETUP(F) \ +GFX.BuildPixel = BuildPixel##F; \ +GFX.BuildPixel2 = BuildPixel2##F; \ +GFX.DecomposePixel = DecomposePixel##F; \ +RED_LOW_BIT_MASK = RED_LOW_BIT_MASK_##F; \ +GREEN_LOW_BIT_MASK = GREEN_LOW_BIT_MASK_##F; \ +BLUE_LOW_BIT_MASK = BLUE_LOW_BIT_MASK_##F; \ +RED_HI_BIT_MASK = RED_HI_BIT_MASK_##F; \ +GREEN_HI_BIT_MASK = GREEN_HI_BIT_MASK_##F; \ +BLUE_HI_BIT_MASK = BLUE_HI_BIT_MASK_##F; \ +MAX_RED = MAX_RED_##F; \ +MAX_GREEN = MAX_GREEN_##F; \ +MAX_BLUE = MAX_BLUE_##F; \ +GREEN_HI_BIT = ((MAX_GREEN_##F + 1) >> 1); \ +SPARE_RGB_BIT_MASK = SPARE_RGB_BIT_MASK_##F; \ +RGB_LOW_BITS_MASK = (RED_LOW_BIT_MASK_##F | \ + GREEN_LOW_BIT_MASK_##F | \ + BLUE_LOW_BIT_MASK_##F); \ +RGB_HI_BITS_MASK = (RED_HI_BIT_MASK_##F | \ + GREEN_HI_BIT_MASK_##F | \ + BLUE_HI_BIT_MASK_##F); \ +RGB_HI_BITS_MASKx2 = ((RED_HI_BIT_MASK_##F | \ + GREEN_HI_BIT_MASK_##F | \ + BLUE_HI_BIT_MASK_##F) << 1); \ +RGB_REMOVE_LOW_BITS_MASK = ~RGB_LOW_BITS_MASK; \ +FIRST_COLOR_MASK = FIRST_COLOR_MASK_##F; \ +SECOND_COLOR_MASK = SECOND_COLOR_MASK_##F; \ +THIRD_COLOR_MASK = THIRD_COLOR_MASK_##F; \ +ALPHA_BITS_MASK = ALPHA_BITS_MASK_##F; \ +FIRST_THIRD_COLOR_MASK = FIRST_COLOR_MASK | THIRD_COLOR_MASK; \ +TWO_LOW_BITS_MASK = RGB_LOW_BITS_MASK | (RGB_LOW_BITS_MASK << 1); \ +HIGH_BITS_SHIFTED_TWO_MASK = (( (FIRST_COLOR_MASK | SECOND_COLOR_MASK | THIRD_COLOR_MASK) & \ + ~TWO_LOW_BITS_MASK ) >> 2); + +void RenderScreen (uint8 *Screen, bool8_32 sub, bool8_32 force_no_add, uint8 D) +{ + bool8_32 BG0; + bool8_32 BG1; + bool8_32 BG2; + bool8_32 BG3; + bool8_32 OB; + + GFX.S = Screen; + + if (!sub) + { + GFX.pCurrentClip = &IPPU.Clip [0]; + BG0 = ON_MAIN (0) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + BG1 = ON_MAIN (1) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + BG2 = ON_MAIN (2) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + BG3 = ON_MAIN (3) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + OB = ON_MAIN (4) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + } + else + { + GFX.pCurrentClip = &IPPU.Clip [1]; + BG0 = ON_SUB (0) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + BG1 = ON_SUB (1) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + BG2 = ON_SUB (2) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + BG3 = ON_SUB (3) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + OB = ON_SUB (4) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + } + +#ifdef __DEBUG__ + printf("Screen[y1,y2]:[%i,%i],Mode:%i, BG0:%i,BG1:%i,BG2:%i,BG3:%i,OBJ:%i\n", GFX.StartY, GFX.EndY, PPU.BGMode, BG0, BG1, BG2, BG3, OB); +#endif + + sub |= force_no_add; + + if (PPU.BGMode <= 1) + { + if (OB) + { +#ifndef __FAST_OBJS__ + SelectTileRenderer (sub || !SUB_OR_ADD(4), false); +#else + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); +#endif + DrawOBJS (!sub, D); + } + if (BG0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(0), false); + DrawBackground (PPU.BGMode, 0, D + 10, D + 14); + } + if (BG1) + { + SelectTileRenderer (sub || !SUB_OR_ADD(1), false); + DrawBackground (PPU.BGMode, 1, D + 9, D + 13); + } + if (BG2) + { + SelectTileRenderer (sub || !SUB_OR_ADD(2), false); + DrawBackground (PPU.BGMode, 2, D + 3, + PPU.BG3Priority ? D + 17 : D + 6); + } + if (BG3 && PPU.BGMode == 0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(3), false); + DrawBackground (PPU.BGMode, 3, D + 2, D + 5); + } + } + else if (PPU.BGMode != 7) + { + if (OB) + { +#ifndef __FAST_OBJS__ + SelectTileRenderer (sub || !SUB_OR_ADD(4), false); +#else + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); +#endif + DrawOBJS (!sub, D); + } + if (BG0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(0), false); + DrawBackground (PPU.BGMode, 0, D + 5, D + 13); + } + if (PPU.BGMode != 6 && BG1) + { + SelectTileRenderer (sub || !SUB_OR_ADD(1), false); + DrawBackground (PPU.BGMode, 1, D + 2, D + 9); + } + } + else + { + if (OB && ((SNESGameFixes.Mode7Hack && D) || !SNESGameFixes.Mode7Hack)) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); + DrawOBJS (!sub, D); + } + if (BG0 || ((Memory.FillRAM [0x2133] & 0x40) && BG1)) + { + int bg; + + if ((Memory.FillRAM [0x2133] & 0x40)&&BG1) + { + Mode7Depths [0] = (BG0?5:1) + D; + Mode7Depths [1] = 9 + D; + bg = 1; + if (sub || !SUB_OR_ADD(0)) + { + DrawBGMode7Background16Prio (Screen, bg); + } + else + { + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16PrioSub1_2 (Screen, bg); + } + else + { + DrawBGMode7Background16PrioSub (Screen, bg); + } + } + else + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16PrioAdd1_2 (Screen, bg); + } + else + { + DrawBGMode7Background16PrioAdd (Screen, bg); + } + } + } + } + else + { + bg = 0; + if (sub || !SUB_OR_ADD(0)) + { + if (D || !SNESGameFixes.Mode7Hack) DrawBGMode7Background16 (Screen, bg, D+5); + else DrawBGMode7Background16New (Screen); + } + else + { + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Sub1_2 (Screen, bg, D+5); + } + else + { + DrawBGMode7Background16Sub (Screen, bg, D+5); + } + } + else + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Add1_2 (Screen, bg, D+5); + } + else + { + DrawBGMode7Background16Add (Screen, bg, D+5); + } + } + } + } + } + if (OB && SNESGameFixes.Mode7Hack && D==0) + { +#ifndef __FAST_OBJS__ + SelectTileRenderer (sub || !SUB_OR_ADD(4), false); +#else + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); +#endif + DrawOBJS (!sub, D); + } + } +} + +#include "font.h" + +void DisplayChar (uint8 *Screen, uint8 c) +{ + int line = (((c & 0x7f) - 32) >> 4) * font_height; + int offset = (((c & 0x7f) - 32) & 15) * font_width; + int h, w; + uint16 *s = (uint16 *) Screen; + for (h = 0; h < font_height; h++, line++, + s += GFX_PPL - font_width) + { + for (w = 0; w < font_width; w++, s++) + { + uint8 p = font [line][offset + w]; + + if (p == '#') + *s = 0xffff; + else + if (p == '.') + *s = BLACK; + } + } +} + +static void S9xDisplayFrameRate () +{ + uint8 *Screen = GFX.Screen + 2 + + (IPPU.RenderedScreenHeight - font_height - 1) * GFX_PITCH; + char string [10]; + int len = 5; + + sprintf (string, "%02d/%02d", IPPU.DisplayedRenderedFrameCount, + (int) Memory.ROMFramesPerSecond); + + int i; + for (i = 0; i < len; i++) + { + DisplayChar (Screen, string [i]); + Screen += (font_width - 1) * sizeof (uint16); + } +} + +static void S9xDisplayString (const char *string) +{ + uint8 *Screen = GFX.Screen + 2 + + (IPPU.RenderedScreenHeight - font_height * 5) * GFX_PITCH; + int len = strlen (string); + int max_chars = IPPU.RenderedScreenWidth / (font_width - 1); + int char_count = 0; + int i; + + for (i = 0; i < len; i++, char_count++) + { + if (char_count >= max_chars || string [i] < 32) + { + Screen -= (font_width - 1) * sizeof (uint16) * max_chars; + Screen += font_height * GFX_PITCH; + if (Screen >= GFX.Screen + GFX_PITCH * IPPU.RenderedScreenHeight) + break; + char_count -= max_chars; + } + if (string [i] < 32) + continue; + DisplayChar (Screen, string [i]); + Screen += (font_width - 1) * sizeof (uint16); + } +} + +// -x- + +static void S9xUpdateScreenTransparency () // ~30-50ms! (called from FLUSH_REDRAW()) +{ + uint32 starty = GFX.StartY; + uint32 endy = GFX.EndY; + uint32 black = BLACK | (BLACK << 16); + + + if (GFX.Pseudo) + { + GFX.r2131 = 0x5f; //0101 1111 - enable addition/subtraction on all BGS and sprites and "1/2 OF COLOR DATA" DESIGNATION + GFX.r212c &= (GFX.r212d_s | 0xf0); + GFX.r212d |= (GFX.r212c_s & 0x0f); + GFX.r2130 |= 2; // enable ADDITION/SUBTRACTION FOR SUB SCREEN + } + + // Check to see if any transparency effects are currently in use + if (!PPU.ForcedBlanking && ADD_OR_SUB_ON_ANYTHING && + (GFX.r2130 & 0x30) != 0x30 && + !((GFX.r2130 & 0x30) == 0x10 && IPPU.Clip[1].Count[5] == 0)) + { + DBG("Transparency in use\n"); + // transparency effects in use, so lets get busy! + struct ClipData *pClip; + uint32 fixedColour; + GFX.FixedColour = BUILD_PIXEL (IPPU.XB[PPU.FixedColourRed], IPPU.XB[PPU.FixedColourGreen] , IPPU.XB[PPU.FixedColourBlue]); + fixedColour = (GFX.FixedColour<<16|GFX.FixedColour); + // Clear the z-buffer, marking areas 'covered' by the fixed + // colour as depth 1. + pClip = &IPPU.Clip [1]; + + // Clear the z-buffer + + if (pClip->Count [5]) + { + + DBG("Colour window enabled. Clearing...\n"); + + // Colour window enabled. + // loop around all of the lines being updated + for (uint32 y = starty; y <= endy; y++) + { + // Clear the subZbuffer + memset32 ((uint32_t*)(GFX.SubZBuffer + y * GFX_ZPITCH),0, (256>>2)); + // Clear the Zbuffer + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH),0, (256>>2)); + if (IPPU.Clip[0].Count [5]) { + // if there is clipping then clear subscreen to a black color + memset32 ((uint32_t*)(GFX.SubScreen + y * GFX_PITCH), black, (256>>1)); + } + + // loop through all window clippings + for (uint32 c = 0; c < pClip->Count [5]; c++) + { + int width = pClip->Right [c][5] - pClip->Left [c][5]; + if (width > 0) { + + //if (pClip->Right [c][5] > pClip->Left [c][5]) + //{ + memset (GFX.SubZBuffer + y * GFX_ZPITCH + pClip->Left [c][5], + 1, width); //pClip->Right [c][5] - pClip->Left [c][5]); + + if (IPPU.Clip [0].Count [5]) + { + DBG("Clearing sub-screen. Clipping effects in use.\n"); + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + + asm volatile ( + " mov r0, %[fixedcolour] \n" + " subs %[width], %[width], #8 \n" + " bmi 2f \n" + " mov r1, r0 \n" + " mov r2, r0 \n" + + "1: \n" + " subs %[width], %[width], #8 \n" + " stmia %[p]!, {r0, r1, r2, %[fixedcolour]}\n" + " bpl 1b \n" + + "2: \n" + " tst %[width], #1 \n" + " strneh %[fixedcolour], [%[p]], #2 \n" + + " tst %[width], #2 \n" + " strne %[fixedcolour], [%[p]], #4 \n" + + " tst %[width], #4 \n" + " stmia %[p]!, {r0, %[fixedcolour]}\n" + + : [width] "+r" (width) + : [fixedcolour] "r" (fixedColour), + [p] "r" (((uint16 *) (GFX.SubScreen + y * GFX_PITCH)) + pClip->Left [c][5]) + : "r0", "r1", "r2", "cc" + ); + //} + } + } + } + } + + } + else + { + DBG("No windows clipping the main screen.\n"); + + // No windows are clipping the main screen + // this simplifies the screen clearing process + // loop through all of the lines to be updated + for (uint32 y = starty; y <= endy; y++) { + // Clear the Zbuffer + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH),0, (256>>2)); + // clear the sub Zbuffer to 1 + memset32 ((uint32_t*)(GFX.SubZBuffer + y * GFX_ZPITCH), 0x01010101, (256>>2)); + + if (IPPU.Clip [0].Count [5]) { + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + memset32 ((uint32_t*)(GFX.SubScreen + y * GFX_PITCH), fixedColour, (256>>1)); + } + } + } + + if (ANYTHING_ON_SUB) + { + DBG("Rendering SubScreen...\n"); + GFX.DB = GFX.SubZBuffer; + RenderScreen (GFX.SubScreen, TRUE, TRUE, SUB_SCREEN_DEPTH); + } + + if (IPPU.Clip [0].Count [5]) + { + DBG("Copying from SubScreen to the Main Screen\n"); + + asm volatile ( + "1: \n" + " mov r1, #(256 >> 2) \n" + + "2: \n" + // four pixels at once + " ldrb r0, [%[d]], #1 \n" + " ldrb r3, [%[d]], #1 \n" + + " bics r0, r0, #1 \n" + " ldrneh r0, [%[p], %[delta]] \n" + + " bics r3, r3, #1 \n" + " ldrneh r3, [%[p], %[delta2]] \n" + + " strh r0, [%[p]], #2 \n" + " ldrb r0, [%[d]], #1 \n" + " strh r3, [%[p]], #2 \n" + " ldrb r3, [%[d]], #1 \n" + + " bics r0, r0, #1 \n" + " ldrneh r0, [%[p], %[delta]] \n" + + " bics r3, r3, #1 \n" + " ldrneh r3, [%[p], %[delta2]] \n" + + " strh r0, [%[p]], #2 \n" + " strh r3, [%[p]], #2 \n" + + " subs r1, r1, #1 \n" + " bne 2b \n" + "3: \n" + " subs %[lines], %[lines], #1 \n" + " addne %[p], %[p], #(640 - 512) \n" + " addne %[d], %[d], #(320 - 256) \n" + " bne 1b \n" + "4: \n" + + : + : [p] "r" ((uint16 *) (GFX.Screen + starty * GFX_PITCH)), + [d] "r" (GFX.SubZBuffer + starty * GFX_ZPITCH), + [delta] "r" (GFX.Delta << 1), + [delta2] "r" ((GFX.Delta << 1) + 2), + [lines] "r" (endy - starty + 1) + : "r0", "r1", "r3", "cc" + ); + } + + DBG("Rendering the Main Screen...\n"); + + GFX.DB = GFX.ZBuffer; + RenderScreen (GFX.Screen, FALSE, FALSE, MAIN_SCREEN_DEPTH); + + if (SUB_OR_ADD(5)) + { + uint32 back = IPPU.ScreenColors [0]; + uint32 Left = 0; + uint32 Right = 256; + uint32 Count; + + DBG("Addition/Substraction in use...\n"); + + pClip = &IPPU.Clip [0]; + + // some initial values + unsigned int fixedcolour_c; + if (GFX.r2131 & 0x80) { + fixedcolour_c = COLOR_SUB(back, GFX.FixedColour); + } else { + fixedcolour_c = COLOR_ADD(back, GFX.FixedColour); + } + + if (!(Count = pClip->Count [5])) Count = 1; + for (uint32 y = starty; y <= endy; y++) + { + + for (uint32 b = 0; b < Count; b++) + { + if (pClip->Count [5]) + { + Left = pClip->Left [b][5]; + Right = pClip->Right [b][5]; + if (Right <= Left) + continue; + } +#define _ROP_ADD1_2 \ + " mov r0, %[back] \n"\ + ROP_ADD1_2(r0, r1) \ + " strh r0, [%[p]] \n" + +// Arguments can be exchanged on addition, so early exit on back == 0 is possible +#define _ROP_ADD \ + ROP_ADD(r1, %[back]) \ + " strh r1, [%[p]] \n" + + +#define _ROP_SUB1_2 \ + " mov r0, %[back] \n"\ + ROP_SUB1_2(r0, r1) \ + " strh r0, [%[p]] \n" + +#define _ROP_SUB \ +" mov r0, %[back] \n"\ + ROP_SUB(r0, r1) \ + " strh r0, [%[p]] \n" + +#define SUBSCREEN_BG(rop, half) \ +\ +asm volatile (\ +" ldrb r0, [%[d]] \n"\ +"71: \n"\ +\ +" movs r0, r0 \n"\ +" ldreqb r1, [%[d], %[zdelta]] \n"\ +" bne 72f \n"\ +\ +" cmp r1, #1 \n"\ +" ldrhih r1, [%[p], %[delta]] \n"\ +" bls 74f \n"\ +\ +_ROP_##rop##half \ +\ +"72: \n"\ +" add %[p], %[p], #2 \n"\ +" subs %[c], %[c], #1 \n"\ +" ldrneb r0, [%[d], #1]! \n"\ +" bne 71b \n"\ +" b 75f \n"\ +"74: \n"\ +" streqh %[fixedcolour], [%[p]], #2 \n"\ +" strloh %[back], [%[p]], #2 \n"\ +" subs %[c], %[c], #1 \n"\ +" ldrneb r0, [%[d], #1]! \n"\ +" bne 71b \n"\ +"75: \n"\ +:\ +:[p] "r" ((uint16 *) (GFX.Screen + y * GFX_PITCH) + Left),\ + [d] "r" (GFX.ZBuffer + y * GFX_ZPITCH + Left),\ + [zdelta] "r" (GFX.DepthDelta),\ + [back] "r" (back),\ + [delta] "r" (GFX.Delta << 1),\ + [fixedcolour] "r" (fixedcolour_c),\ + [c] "r" (Right - Left) \ +: "r0", "r1", "cc"\ +); + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + SUBSCREEN_BG(SUB, 1_2) + } + else + { + SUBSCREEN_BG(SUB, ) + + } + } + else + if (GFX.r2131 & 0x40) + { + SUBSCREEN_BG(ADD, 1_2) + } + else if (back != 0) { + SUBSCREEN_BG(ADD, ) + } + else + { + + if (!pClip->Count [5]) + { + DBG("Copying line with no effect...\n"); + // The backdrop has not been cleared yet - so + // copy the sub-screen to the main screen + // or fill it with the back-drop colour if the + // sub-screen is clear. + asm volatile ( + " ldrb r0, [%[d]] \n" + "31: \n" + + " movs r0, r0 \n" + " ldreqb r1, [%[d], %[zdelta]] \n" + " bne 32f \n" + + " cmp r1, #1 \n" + " ldrhih r0, [%[p], %[delta]] \n" + " strloh %[back], [%[p]] \n" + " streqh %[fixedcolour], [%[p]] \n" + " strhih r0, [%[p]] \n" + + "32: \n" + " subs %[c], %[c], #1 \n" + " add %[p], %[p], #2 \n" + " ldrneb r0, [%[d], #1]! \n" + " bne 31b \n" + " \n" + : + :[p] "r" ((uint16 *) (GFX.Screen + y * GFX_PITCH) + Left), + [d] "r" (GFX.ZBuffer + y * GFX_ZPITCH + Left), + [zdelta] "r" (GFX.DepthDelta), + [back] "r" (back), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [c] "r" (Right - Left) + : "r0", "r1", "cc" + + ); + + } + } + } + } + + } + else + { + + // Subscreen not being added to back + DBG("No addition/substraction in use...\n"); + uint32 back = IPPU.ScreenColors [0] | (IPPU.ScreenColors [0] << 16); + pClip = &IPPU.Clip [0]; + + if (pClip->Count [5]) + { + + DBG("Copying subscreen with clipping...\n"); + + for (uint32 y = starty; y <= endy; y++) + { + for (uint32 b = 0; b < pClip->Count [5]; b++) + { + uint32 Left = pClip->Left [b][5]; + uint32 Right = pClip->Right [b][5]; + if (Left >= Right) continue; + asm volatile ( + + " tst %[c], #1 \n" + " bne 21f \n" + + " ldrb r0, [%[d]], #1 \n" + " add %[p], %[p], #2 \n" + " movs r0, r0 \n" + " streqh %[back], [%[p], #-2] \n" + " subs %[c], %[c], #1 \n" + " beq 22f \n" + + "21: \n" + + " ldrb r0, [%[d]], #1 \n" + " ldrb r1, [%[d]], #1 \n" + " add %[p], %[p], #4 \n" + + " movs r0, r0 \n" + " streqh %[back], [%[p], #-4] \n" + + " movs r1, r1 \n" + " streqh %[back], [%[p], #-2] \n" + + " subs %[c], %[c], #2 \n" + " bhi 21b \n" + "22: \n" + : + :[p] "r" ((uint16 *) (GFX.Screen + y * GFX_PITCH) + Left), + [d] "r" (GFX.ZBuffer + y * GFX_ZPITCH + Left), + [back] "r" (back), + [c] "r" (Right - Left) + : "r0", "r1", "cc" + + ); + } + } + } + else + { + DBG("Copying SubScreen with no clipping...\n"); + + asm volatile ( + "@ -- SubScreen clear \n" + "1113: \n" + " mov r1, #(256/8) \n" + "1112: \n" + " ldr r0, [%[d]], #4 \n" + + " add %[p], %[p], #8 \n" + + " tst r0, #0x0ff \n" + " streqh %[back], [%[p], #-8] \n" + + " tst r0, #0x0ff00 \n" + " streqh %[back], [%[p], #-6] \n" + + " tst r0, #0x0ff0000 \n" + " streqh %[back], [%[p], #-4] \n" + + " tst r0, #0x0ff000000 \n" + " streqh %[back], [%[p], #-2] \n" + + " ldr r0, [%[d]], #4 \n" + + " add %[p], %[p], #8 \n" + + " tst r0, #0x0ff \n" + " streqh %[back], [%[p], #-8] \n" + + " tst r0, #0x0ff00 \n" + " streqh %[back], [%[p], #-6] \n" + + " tst r0, #0x0ff0000 \n" + " streqh %[back], [%[p], #-4] \n" + + " tst r0, #0x0ff000000 \n" + " streqh %[back], [%[p], #-2] \n" + + " subs r1, r1, #1 \n" + " bne 1112b \n" + + " subs %[lines], %[lines], #1 \n" + " add %[p], %[p], #(640-512) \n" + " add %[d], %[d], #(320-256) \n" + " bne 1113b \n" + "1114:" + : + :[p] "r" (GFX.Screen + starty * GFX_PITCH), + [d] "r" (GFX.ZBuffer + starty * GFX_ZPITCH), + [back] "r" (back), + [lines] "r" (endy - starty + 1) + : "r0", "r1", "cc" + ); + } + } + + } + else + { + DBG("No transparency effects in use.\n"); + + // 16bit and transparency but currently no transparency effects in + // operation. + + // get the back colour of the current screen + uint32 back = IPPU.ScreenColors [0] | + (IPPU.ScreenColors [0] << 16); + + // if forceblanking in use then use black instead of the back color + if (PPU.ForcedBlanking) + back = black; + + // not sure what Clip is used for yet + // could be a check to see if there is any clipping present? + if (IPPU.Clip [0].Count[5]) + { + DBG("Clearing background with clipping...\n"); + + // loop through all of the lines that are going to be updated as part of this screen update + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), black, + IPPU.RenderedScreenWidth>>1); + + if (black!=back) + { + for (uint32 c = 0; c < IPPU.Clip [0].Count [5]; c++) + { + //if (IPPU.Clip [0].Right [c][5] > IPPU.Clip [0].Left [c][5]) + //{ + register int width = IPPU.Clip [0].Right [c][5] - IPPU.Clip [0].Left [c][5]; + if (width <= 0) continue; + + asm volatile ( + " mov r0, %[back] \n" + " subs %[width], %[width], #8 \n" + " bmi 2f \n" + " mov r1, r0 \n" + " mov r2, r0 \n" + + "1: \n" + " subs %[width], %[width], #8 \n" + " stmia %[p]!, {r0, r1, r2, %[back]}\n" + " bpl 1b \n" + + "2: \n" + " tst %[width], #1 \n" + " strneh %[back], [%[p]], #2 \n" + + " tst %[width], #2 \n" + " strne %[back], [%[p]], #4 \n" + + " tst %[width], #4 \n" + " stmia %[p]!, {r0, %[back]}\n" + + : [width] "+r" (width) + : [back] "r" (back | (back << 16)), + [p] "r" (((uint16 *) (GFX.SubScreen + y * GFX_PITCH)) + IPPU.Clip [0].Left [c][5]) + : "r0", "r1", "r2", "cc" + ); + //} + } + } + } + + } + else + { + DBG("Clearing background with no clipping...\n"); + + // there is no clipping to worry about so just fill with the back colour + for (uint32 y = starty; y <= endy; y++) { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), back, (256>>1)); + } + + } + + // If Forced blanking is not in effect + if (!PPU.ForcedBlanking) + { + DBG("Forced Blanking not in use. Clearing ZBuffer ... !!\n"); + // Clear the Zbuffer for each of the lines which are going to be updated + for (uint32 y = starty; y <= endy; y++) { + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH), 0, (256>>2)); + } + DBG("Rendering screen !!\n"); + GFX.DB = GFX.ZBuffer; // save pointer to Zbuffer in GFX object + RenderScreen (GFX.Screen, FALSE, TRUE, SUB_SCREEN_DEPTH); + + } + } + IPPU.PreviousLine = IPPU.CurrentLine; +} + +static void S9xUpdateScreenNoTransparency () // ~30-50ms! (called from FLUSH_REDRAW()) +{ + uint32 starty = GFX.StartY; + uint32 endy = GFX.EndY; + + uint32 black = BLACK | (BLACK << 16); + + // get back colour to be used in clearing the screen + register uint32 back; + if (!(GFX.r2131 & 0x80) && (GFX.r2131 & 0x20) && + (PPU.FixedColourRed || PPU.FixedColourGreen || PPU.FixedColourBlue)) + { + back = (PPU.FixedColourRed << 11) | (PPU.FixedColourGreen << 6) | (1 << 5) | (PPU.FixedColourBlue); + back = (back << 16) | back; + } + else + { + back = IPPU.ScreenColors [0] | (IPPU.ScreenColors [0] << 16); + } + + // if Forcedblanking in use then back colour becomes black + if (PPU.ForcedBlanking) + back = black; + else + { + SelectTileRenderer (TRUE, false); //selects the tile renderers to be used + // TRUE means to use the default + // FALSE means use best renderer based on current + // graphics register settings + } + + // now clear all graphics lines which are being updated using the back colour + for (register uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), back, + IPPU.RenderedScreenWidth>>1); + } + + if (!PPU.ForcedBlanking) + { + // Loop through all lines being updated and clear the + // zbuffer for each of the lines + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH), 0, + IPPU.RenderedScreenWidth>>2); + } + GFX.DB = GFX.ZBuffer; // save pointer to Zbuffer in GFX object + GFX.pCurrentClip = &IPPU.Clip [0]; + +// Define an inline function to handle clipping +#define FIXCLIP(n) \ +if (GFX.r212c & (1 << (n))) \ + GFX.pCurrentClip = &IPPU.Clip [0]; \ +else \ + GFX.pCurrentClip = &IPPU.Clip [1] + +// Define an inline function to handle which BGs are being displayed +#define DISPLAY(n) ((GFX.r212c & n) || ((GFX.r212d & n) && subadd)) + + uint8 subadd = GFX.r2131 & 0x3f; + + // go through all BGS are check if they need to be displayed + bool8_32 BG0 = DISPLAY(1) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + bool8_32 BG1 = DISPLAY(2) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + bool8_32 BG2 = DISPLAY(4) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + bool8_32 BG3 = DISPLAY(8) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + bool8_32 OB = DISPLAY(16) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + + if (PPU.BGMode <= 1) + { + // screen modes 0 and 1 + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + if (BG0) + { + FIXCLIP(0); + DrawBackground (PPU.BGMode, 0, 10, 14); + } + if (BG1) + { + FIXCLIP(1); + DrawBackground (PPU.BGMode, 1, 9, 13); + } + if (BG2) + { + FIXCLIP(2); + DrawBackground (PPU.BGMode, 2, 3, + PPU.BG3Priority ? 17 : 6); + } + if (BG3 && PPU.BGMode == 0) + { + FIXCLIP(3); + DrawBackground (PPU.BGMode, 3, 2, 5); + } + } + else if (PPU.BGMode != 7) + { + // screen modes 2 and up but not mode 7 + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + if (BG0) + { + FIXCLIP(0); + DrawBackground (PPU.BGMode, 0, 5, 13); + } + if (BG1 && PPU.BGMode != 6) + { + FIXCLIP(1); + DrawBackground (PPU.BGMode, 1, 2, 9); + } + } + else + { + // screen mode 7 + DrawBGMode7Background16New (GFX.Screen); + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + } + } + IPPU.PreviousLine = IPPU.CurrentLine; +} + +#ifdef __OLD_RASTER_FX__ +static void S9xUpdateScreen_delayedRasterFx () // ~30-50ms! (called from FLUSH_REDRAW()) +#else +void S9xUpdateScreen () // ~30-50ms! (called from FLUSH_REDRAW()) +#endif +{ + int StartY, EndY, CurrentLine, CurrentROp; + + StartY = IPPU.PreviousLine; + if ((EndY = IPPU.CurrentLine - 1) >= PPU.ScreenHeight) EndY = PPU.ScreenHeight - 1; + + GFX.S = GFX.Screen; + + CurrentROp = 0; + CurrentLine = StartY; +#ifdef __DEBUG__ + printf("Start screen update. ROPCount: %d, StartY: %d, EndY: %d\n", ROpCount, StartY, EndY); +#endif + do { + while ((CurrentROp < ROpCount) && ((rops[CurrentROp].line == CurrentLine) || (!wouldRasterAlterStatus(&rops[CurrentROp])))) { + #ifdef __DEBUG__ + printf("Processing ROP %d/%d. Line: %d\n", CurrentROp, ROpCount, CurrentLine); + #endif + doRaster(&rops[CurrentROp]); + CurrentROp++; + } + + GFX.StartY = CurrentLine; + if ((CurrentROp < ROpCount) && ((rops[CurrentROp].line - 1) <= EndY)) GFX.EndY = rops[CurrentROp].line - 1; + else GFX.EndY = EndY; + + #ifdef __DEBUG__ + printf("Partial screen update. ROPCount: %d, StartY: %d, EndY: %d\n", ROpCount, GFX.StartY, GFX.EndY); + #endif + + // get local copies of vid registers to be used later + GFX.r2131 = GFX.r2131_s; // ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN + GFX.r212c = GFX.r212c_s; // MAIN SCREEN, DESIGNATION - used to enable BGS + GFX.r212d = GFX.r212d_s; // SUB SCREEN DESIGNATION - used to enable sub BGS + GFX.r2130 = GFX.r2130_s; // INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION + + // If external sync is off and + // main screens have not been configured the same as the sub screen and + // color addition and subtraction has been disabled then + // Pseudo is 1 + // anything else it is 0 + GFX.Pseudo = (Memory.FillRAM[0x2133] & 8) != 0 && // Use EXTERNAL SYNCHRONIZATION? + (GFX.r212c & 15) != (GFX.r212d & 15) && // Are the main screens different from the sub screens? + (GFX.r2131 & 0x3f) == 0; // Is colour data addition/subtraction disabled on all BGS? + + // If sprite data has been changed then go through and + // refresh the sprites. + if (IPPU.OBJChanged) { + #ifdef __DEBUG__ + printf("Objects changed !! setting up Objects...\n"); + #endif + S9xSetupOBJ(); + } + + if (PPU.RecomputeClipWindows) { + #ifdef __DEBUG__ + printf("Clipping changed !! recalculating clipping...\n"); + #endif + ComputeClipWindows(); + } + + if (Settings.Transparency) S9xUpdateScreenTransparency(); + else S9xUpdateScreenNoTransparency(); + CurrentLine = GFX.EndY + 1; + + #ifdef __DEBUG__ + printf("Finished partial screen update.\n", ROpCount, StartY, EndY); + #endif + + + } while ((CurrentROp < ROpCount) && (CurrentLine <= EndY)); + +#ifdef __DEBUG__ + printf("End screen update. ROPCount: %d, CurrentROp: %d, StartY: %d, EndY: %d\n", ROpCount, CurrentROp, StartY, EndY); +#endif + + RESET_ROPS(CurrentROp); + +#ifdef __DEBUG__ + printf("ROps cleaned\n"); +#endif + + PPU.BG[0].OffsetsChanged = 0; + PPU.BG[1].OffsetsChanged = 0; + PPU.BG[2].OffsetsChanged = 0; + PPU.BG[3].OffsetsChanged = 0; +} + +#ifdef __OLD_RASTER_FX__ + +static void S9xUpdateScreen_normalRasterFx () // ~30-50ms! (called from FLUSH_REDRAW()) +{ + GFX.StartY = IPPU.PreviousLine; + if ((GFX.EndY = IPPU.CurrentLine - 1) >= PPU.ScreenHeight) GFX.EndY = PPU.ScreenHeight - 1; + + GFX.S = GFX.Screen; + +#ifdef __DEBUG__ + printf("Start screen update. StartY: %d, EndY: %d\n", GFX.StartY, GFX.EndY); +#endif + // get local copies of vid registers to be used later + GFX.r2131 = GFX.r2131_s; // ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN + GFX.r212c = GFX.r212c_s; // MAIN SCREEN, DESIGNATION - used to enable BGS + GFX.r212d = GFX.r212d_s; // SUB SCREEN DESIGNATION - used to enable sub BGS + GFX.r2130 = GFX.r2130_s; // INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION + + // If external sync is off and + // main screens have not been configured the same as the sub screen and + // color addition and subtraction has been disabled then + // Pseudo is 1 + // anything else it is 0 + GFX.Pseudo = (Memory.FillRAM[0x2133] & 8) != 0 && // Use EXTERNAL SYNCHRONIZATION? + (GFX.r212c & 15) != (GFX.r212d & 15) && // Are the main screens different from the sub screens? + (GFX.r2131 & 0x3f) == 0; // Is colour data addition/subtraction disabled on all BGS? + + // If sprite data has been changed then go through and + // refresh the sprites. + if (IPPU.OBJChanged) { + #ifdef __DEBUG__ + printf("Objects changed !! setting up Objects...\n"); + #endif + S9xSetupOBJ(); + } + + if (PPU.RecomputeClipWindows) { + #ifdef __DEBUG__ + printf("Clipping changed !! recalculating clipping...\n"); + #endif + ComputeClipWindows(); + } + + if (Settings.Transparency) S9xUpdateScreenTransparency(); + else S9xUpdateScreenNoTransparency(); + +#ifdef __DEBUG__ + printf("End screen update. StartY: %d, EndY: %d\n", GFX.StartY, GFX.EndY); +#endif + PPU.BG[0].OffsetsChanged = 0; + PPU.BG[1].OffsetsChanged = 0; + PPU.BG[2].OffsetsChanged = 0; + PPU.BG[3].OffsetsChanged = 0; +} + +void S9xUpdateScreen() +{ + if (snesMenuOptions.delayedRasterFX) S9xUpdateScreen_delayedRasterFx(); + else S9xUpdateScreen_normalRasterFx (); +} +#endif + +// -x- + +#ifdef GFX_MULTI_FORMAT + +#define _BUILD_PIXEL(F) \ +uint32 BuildPixel##F(uint32 R, uint32 G, uint32 B) \ +{ \ + return (BUILD_PIXEL_##F(R,G,B)); \ +}\ +uint32 BuildPixel2##F(uint32 R, uint32 G, uint32 B) \ +{ \ + return (BUILD_PIXEL2_##F(R,G,B)); \ +} \ +void DecomposePixel##F(uint32 pixel, uint32 &R, uint32 &G, uint32 &B) \ +{ \ + DECOMPOSE_PIXEL_##F(pixel,R,G,B); \ +} + +_BUILD_PIXEL(RGB565) +_BUILD_PIXEL(RGB555) +_BUILD_PIXEL(BGR565) +_BUILD_PIXEL(BGR555) +_BUILD_PIXEL(GBR565) +_BUILD_PIXEL(GBR555) +_BUILD_PIXEL(RGB5551) + +bool8_32 S9xSetRenderPixelFormat (int format) +{ + extern uint32 current_graphic_format; + + current_graphic_format = format; + + switch (format) + { + case RGB565: + _BUILD_SETUP(RGB565) + return (TRUE); + case RGB555: + _BUILD_SETUP(RGB555) + return (TRUE); + case BGR565: + _BUILD_SETUP(BGR565) + return (TRUE); + case BGR555: + _BUILD_SETUP(BGR555) + return (TRUE); + case GBR565: + _BUILD_SETUP(GBR565) + return (TRUE); + case GBR555: + _BUILD_SETUP(GBR555) + return (TRUE); + case RGB5551: + _BUILD_SETUP(RGB5551) + return (TRUE); + default: + break; + } + return (FALSE); +} +#endif diff --git a/src/gfx16.cpp.last b/src/gfx16.cpp.last new file mode 100644 index 0000000..24e004b --- /dev/null +++ b/src/gfx16.cpp.last @@ -0,0 +1,3185 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" + +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" +#include "cheats.h" +#include +#include "asmmemfuncs.h" +#include "mode7.h" +#include "rops.h" +#include "tile16.h" +uint32 TileBlank; + +const int tx_table[16] = { +// t1 = 16, t2 = 0 + // FLIP = 0x00 + 16 + 0, // 0x00 + 16 + 1, // 0x01 + + // FLIP = 0x01 + 16 + 1 - 0, // 0x02 + 16 + 1 - 1, // 0x03 + + // FLIP = 0x02 + 0 + 0, // 0x04 + 0 + 1, // 0x05 + + // FLIP = 0x03 + 0 + 1 - 0, // 0x06 + 0 + 1 - 1, // 0x07 + +// t1 = 0, t2 = 16 + // FLIP = 0x00 + 0 + 0, // 0x08 + 0 + 1, // 0x09 + + // FLIP = 0x01 + 0 + 1 - 0, // 0x0A + 0 + 1 - 1, // 0x0B + + // FLIP = 0x02 + 16 + 0, // 0x0C + 16 + 1, // 0x0D + + // FLIP = 0x03 + 16 + 1 - 0, // 0x0E + 16 + 1 - 1 // 0x0F +}; + +#define M7 19 +#define M8 19 + +void ComputeClipWindows (); +static void S9xDisplayFrameRate (); +static void S9xDisplayString (const char *string); + +extern uint8 BitShifts[8][4]; +extern uint8 TileShifts[8][4]; +extern uint8 PaletteShifts[8][4]; +extern uint8 PaletteMasks[8][4]; +extern uint8 Depths[8][4]; +extern uint8 BGSizes [2]; + +extern NormalTileRenderer DrawTilePtr; +extern ClippedTileRenderer DrawClippedTilePtr; +extern NormalTileRenderer DrawHiResTilePtr; +extern ClippedTileRenderer DrawHiResClippedTilePtr; +extern LargePixelRenderer DrawLargePixelPtr; + +extern struct SBG BG; + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; + +extern uint8 Mode7Depths [2]; + +#define ON_MAIN(N) (GFX.r212c & (1 << (N))) + +#define SUB_OR_ADD(N) \ +(GFX.r2131 & (1 << (N))) + +#define ON_SUB(N) \ +((GFX.r2130 & 0x30) != 0x30 && \ + (GFX.r2130 & 2) && \ + (GFX.r212d & (1 << N))) + +#define ANYTHING_ON_SUB \ +((GFX.r2130 & 0x30) != 0x30 && \ + (GFX.r2130 & 2) && \ + (GFX.r212d & 0x1f)) + +#define ADD_OR_SUB_ON_ANYTHING \ +(GFX.r2131 & 0x3f) + +#define BLACK BUILD_PIXEL(0,0,0) + +void DrawNoZTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount); +void DrawTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTile16x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTile16x2x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16x2x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawLargePixel16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Add (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawTile16Add (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Add1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawTile16Add1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Sub (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + + +void DrawTile16Sub (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Sub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + + +void DrawTile16Sub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16FixedSub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16FixedSub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawHiResClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawHiResTile16 (uint32 Tile, uint32 Offset, + uint32 StartLine, uint32 LineCount); + +bool8_32 S9xGraphicsInit () +{ + register uint32 PixelOdd = 1; + register uint32 PixelEven = 2; + +#ifdef GFX_MULTI_FORMAT + if (GFX.BuildPixel == NULL) + S9xSetRenderPixelFormat (RGB565); +#endif + + for (uint8 bitshift = 0; bitshift < 4; bitshift++) + { + for (register int i = 0; i < 16; i++) + { + register uint32 h = 0; + register uint32 l = 0; + +#if defined(LSB_FIRST) +// Wiz usa LSB_FIRST + if (i & 8) + h |= PixelOdd; + if (i & 4) + h |= PixelOdd << 8; + if (i & 2) + h |= PixelOdd << 16; + if (i & 1) + h |= PixelOdd << 24; + if (i & 8) + l |= PixelOdd; + if (i & 4) + l |= PixelOdd << 8; + if (i & 2) + l |= PixelOdd << 16; + if (i & 1) + l |= PixelOdd << 24; +#else + if (i & 8) + h |= (PixelOdd << 24); + if (i & 4) + h |= (PixelOdd << 16); + if (i & 2) + h |= (PixelOdd << 8); + if (i & 1) + h |= PixelOdd; + if (i & 8) + l |= (PixelOdd << 24); + if (i & 4) + l |= (PixelOdd << 16); + if (i & 2) + l |= (PixelOdd << 8); + if (i & 1) + l |= PixelOdd; +#endif + + odd_high[bitshift][i] = h; + odd_low[bitshift][i] = l; + h = l = 0; + +#if defined(LSB_FIRST) + if (i & 8) + h |= PixelEven; + if (i & 4) + h |= PixelEven << 8; + if (i & 2) + h |= PixelEven << 16; + if (i & 1) + h |= PixelEven << 24; + if (i & 8) + l |= PixelEven; + if (i & 4) + l |= PixelEven << 8; + if (i & 2) + l |= PixelEven << 16; + if (i & 1) + l |= PixelEven << 24; +#else + if (i & 8) + h |= (PixelEven << 24); + if (i & 4) + h |= (PixelEven << 16); + if (i & 2) + h |= (PixelEven << 8); + if (i & 1) + h |= PixelEven; + if (i & 8) + l |= (PixelEven << 24); + if (i & 4) + l |= (PixelEven << 16); + if (i & 2) + l |= (PixelEven << 8); + if (i & 1) + l |= PixelEven; +#endif + + even_high[bitshift][i] = h; + even_low[bitshift][i] = l; + } + PixelEven <<= 2; + PixelOdd <<= 2; + } + + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; + GFX.DepthDelta = GFX.SubZBuffer - GFX.ZBuffer; + //GFX.InfoStringTimeout = 0; + //GFX.InfoString = NULL; + + PPU.BG_Forced = 0; + IPPU.OBJChanged = TRUE; + + IPPU.DirectColourMapsNeedRebuild = TRUE; + DrawTilePtr = DrawTile16; + DrawClippedTilePtr = DrawClippedTile16; + DrawLargePixelPtr = DrawLargePixel16; + DrawHiResTilePtr= DrawHiResTile16; + DrawHiResClippedTilePtr = DrawHiResClippedTile16; + S9xFixColourBrightness (); + + if (!(GFX.X2 = (uint16 *) malloc (sizeof (uint16) * 0x10000))) + return (FALSE); + + if (!(GFX.ZERO_OR_X2 = (uint16 *) malloc (sizeof (uint16) * 0x10000)) || + !(GFX.ZERO = (uint16 *) malloc (sizeof (uint16) * 0x10000))) + { + if (GFX.ZERO_OR_X2) + { + free ((char *) GFX.ZERO_OR_X2); + GFX.ZERO_OR_X2 = NULL; + } + if (GFX.X2) + { + free ((char *) GFX.X2); + GFX.X2 = NULL; + } + return (FALSE); + } + uint32 r, g, b; + + // Build a lookup table that multiplies a packed RGB value by 2 with + // saturation. + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r << 1; + if (r2 > MAX_RED) + r2 = MAX_RED; + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g << 1; + if (g2 > MAX_GREEN) + g2 = MAX_GREEN; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b << 1; + if (b2 > MAX_BLUE) + b2 = MAX_BLUE; + GFX.X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } + ZeroMemory (GFX.ZERO, 0x10000 * sizeof (uint16)); + ZeroMemory (GFX.ZERO_OR_X2, 0x10000 * sizeof (uint16)); + // Build a lookup table that if the top bit of the color value is zero + // then the value is zero, otherwise multiply the value by 2. Used by + // the color subtraction code. + +#if defined(OLD_COLOUR_BLENDING) + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 = (r2 << 1) & MAX_RED; + + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 = (g2 << 1) & MAX_GREEN; + + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 = (b2 << 1) & MAX_BLUE; + + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } +#else + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 = (r2 << 1) & MAX_RED; + + if (r2 == 0) + r2 = 1; + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 = (g2 << 1) & MAX_GREEN; + + if (g2 == 0) + g2 = 1; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 = (b2 << 1) & MAX_BLUE; + + if (b2 == 0) + b2 = 1; + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } +#endif + + // Build a lookup table that if the top bit of the color value is zero + // then the value is zero, otherwise its just the value. + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 &= ~0x10; + + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 &= ~GREEN_HI_BIT; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 &= ~0x10; + + GFX.ZERO [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } + + return (TRUE); +} + +void S9xGraphicsDeinit (void) +{ + // Free any memory allocated in S9xGraphicsInit + if (GFX.X2) + { + free ((char *) GFX.X2); + GFX.X2 = NULL; + } + if (GFX.ZERO_OR_X2) + { + free ((char *) GFX.ZERO_OR_X2); + GFX.ZERO_OR_X2 = NULL; + } + if (GFX.ZERO) + { + free ((char *) GFX.ZERO); + GFX.ZERO = NULL; + } +} + +void S9xBuildDirectColourMaps () +{ + for (uint32 p = 0; p < 8; p++) + { + for (uint32 c = 0; c < 256; c++) + { +// XXX: Brightness + DirectColourMaps [p][c] = BUILD_PIXEL (((c & 7) << 2) | ((p & 1) << 1), + ((c & 0x38) >> 1) | (p & 2), + ((c & 0xc0) >> 3) | (p & 4)); + } + } + IPPU.DirectColourMapsNeedRebuild = FALSE; +} + +void S9xStartScreenRefresh () +{ + if (IPPU.RenderThisFrame) + { +#ifndef _SNESPPC + if (!S9xInitUpdate ()) + { + IPPU.RenderThisFrame = FALSE; + return; + } +#endif + IPPU.RenderedFramesCount++; + IPPU.PreviousLine = IPPU.CurrentLine = 0; + IPPU.MaxBrightness = PPU.Brightness; + IPPU.LatchedBlanking = PPU.ForcedBlanking; + IPPU.LatchedInterlace = (Memory.FillRAM[0x2133] & 1); + IPPU.RenderedScreenWidth = 256; + IPPU.RenderedScreenHeight = PPU.ScreenHeight; + IPPU.DoubleWidthPixels = FALSE; + + PPU.RecomputeClipWindows = TRUE; + GFX.DepthDelta = GFX.SubZBuffer - GFX.ZBuffer; + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; + + } + if (++IPPU.FrameCount % Memory.ROMFramesPerSecond == 0) + { + IPPU.DisplayedRenderedFrameCount = IPPU.RenderedFramesCount; + IPPU.RenderedFramesCount = 0; + IPPU.FrameCount = 0; + } +} + +void RenderLine (uint8 C) +{ + if (IPPU.RenderThisFrame) + { + + LineData[C].BG[0].VOffset = PPU.BG[0].VOffset + 1; + LineData[C].BG[0].HOffset = PPU.BG[0].HOffset; + LineData[C].BG[1].VOffset = PPU.BG[1].VOffset + 1; + LineData[C].BG[1].HOffset = PPU.BG[1].HOffset; + + if (PPU.BGMode == 7) + { + struct SLineMatrixData *p = &LineMatrixData [C]; + p->MatrixA = PPU.MatrixA; + p->MatrixB = PPU.MatrixB; + p->MatrixC = PPU.MatrixC; + p->MatrixD = PPU.MatrixD; + p->CentreX = PPU.CentreX; + p->CentreY = PPU.CentreY; + } + else + { + if (Settings.StarfoxHack && PPU.BG[2].VOffset == 0 && + PPU.BG[2].HOffset == 0xe000) + { + LineData[C].BG[2].VOffset = 0xe1; + LineData[C].BG[2].HOffset = 0; + } + else + { + LineData[C].BG[2].VOffset = PPU.BG[2].VOffset + 1; + LineData[C].BG[2].HOffset = PPU.BG[2].HOffset; + LineData[C].BG[3].VOffset = PPU.BG[3].VOffset + 1; + LineData[C].BG[3].HOffset = PPU.BG[3].HOffset; + } + + } + IPPU.CurrentLine = C + 1; + } +} + + +void S9xEndScreenRefresh() +{ + IPPU.HDMAStarted = FALSE; + +//RC + if (IPPU.RenderThisFrame) + { + FLUSH_REDRAW (); + //if (IPPU.ColorsChanged) + //{ + IPPU.ColorsChanged = FALSE; + //} + + + S9xDeinitUpdate (IPPU.RenderedScreenWidth, IPPU.RenderedScreenHeight, + 1); + } +#ifndef RC_OPTIMIZED + S9xApplyCheats (); +#endif + + +#ifdef DEBUGGER + if (CPU.Flags & FRAME_ADVANCE_FLAG) + { + if (ICPU.FrameAdvanceCount) + { + ICPU.FrameAdvanceCount--; + IPPU.RenderThisFrame = TRUE; + IPPU.FrameSkip = 0; + } + else + { + CPU.Flags &= ~FRAME_ADVANCE_FLAG; + CPU.Flags |= DEBUG_MODE_FLAG; + } + } +#endif + +/* + if (CPU.SRAMModified) + { + if (!CPU.AutoSaveTimer) + { + if (!(CPU.AutoSaveTimer = Settings.AutoSaveDelay * Memory.ROMFramesPerSecond)) + CPU.SRAMModified = FALSE; + } + else + { + if (!--CPU.AutoSaveTimer) + { + S9xAutoSaveSRAM (); + CPU.SRAMModified = FALSE; + } + } + } +*/ +} + +void S9xSetInfoString (const char *string) +{ + } + + + +int TileRenderer; +TileRendererSet TileRenderers[] = { + {DrawTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 0 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 1 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedAdd1_2, DrawClippedTile16FixedAdd1_2, DrawLargePixel16Add1_2}, // 2 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawTile16Add1_2, DrawClippedTile16Add1_2, DrawLargePixel16Add1_2}, // 3 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 4 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 5 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedSub1_2, DrawClippedTile16FixedSub1_2, DrawLargePixel16Sub1_2}, // 6 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawTile16Sub1_2, DrawClippedTile16Sub1_2, DrawLargePixel16Sub1_2}, // 7 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawTile16, DrawClippedTile16, DrawLargePixel16} // 8 -> normal + }; +TileRendererSet TileRenderersNoZ[] = { + {DrawNoZTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 0 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawNoZTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 1 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedAdd1_2, DrawClippedTile16FixedAdd1_2, DrawLargePixel16Add1_2}, // 2 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawNoZTile16Add1_2, DrawClippedTile16Add1_2, DrawLargePixel16Add1_2}, // 3 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawNoZTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 4 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawNoZTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 5 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedSub1_2, DrawClippedTile16FixedSub1_2, DrawLargePixel16Sub1_2}, // 6 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawNoZTile16Sub1_2, DrawClippedTile16Sub1_2, DrawLargePixel16Sub1_2}, // 7 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawNoZTile16, DrawClippedTile16, DrawLargePixel16} // 8 -> normal + }; +INLINE void SelectTileRenderer (bool8_32 normal, bool NoZ = false) +{ + if (normal) { + TileRenderer = 8; + } + else { + TileRenderer = (((GFX.r2131 >> 5) & 0x06) | ((GFX.r2130 >> 1) & 1)); + } + +#ifdef __DEBUG__ + char *TRName[] = { + "Add", "Add", "FixedAdd1_2", "Add1_2", + "Sub", "Sub", "FixedSub1_2", "Sub1_2", + "Normal" + }; + printf("SelectTileRenderer: %s\n", TRName[TileRenderer]); +#endif + + if (NoZ) { + DrawTilePtr = TileRenderersNoZ[TileRenderer].Normal; + DrawClippedTilePtr = TileRenderersNoZ[TileRenderer].Clipped; + DrawLargePixelPtr = TileRenderersNoZ[TileRenderer].Large; + } + else { + DrawTilePtr = TileRenderers[TileRenderer].Normal; + DrawClippedTilePtr = TileRenderers[TileRenderer].Clipped; + DrawLargePixelPtr = TileRenderers[TileRenderer].Large; + } +} + +void S9xSetupOBJ () +{ + int SmallSize; + int LargeSize; + + switch (PPU.OBJSizeSelect) + { + case 0: + SmallSize = 8; + LargeSize = 16; + break; + case 1: + SmallSize = 8; + LargeSize = 32; + break; + case 2: + SmallSize = 8; + LargeSize = 64; + break; + case 3: + SmallSize = 16; + LargeSize = 32; + break; + case 4: + SmallSize = 16; + LargeSize = 64; + break; + case 5: + default: + SmallSize = 32; + LargeSize = 64; + break; + } + + int C = 0; + + int FirstSprite = PPU.FirstSprite & 0x7f; + int S = FirstSprite; + do + { + int Size; + if (PPU.OBJ [S].Size) + Size = LargeSize; + else + Size = SmallSize; + + long VPos = PPU.OBJ [S].VPos; + + if (VPos >= PPU.ScreenHeight) + VPos -= 256; + if (PPU.OBJ [S].HPos < 256 && PPU.OBJ [S].HPos > -Size && + VPos < PPU.ScreenHeight && VPos > -Size) + { + int x = 0; + int a, b; + //GFX.OBJList[C++] = S; + // -- Sort objects (from low to high priority) + while (x < C) { + a = GFX.OBJList[x]; + if (PPU.OBJ[a].Priority >= PPU.OBJ[S].Priority) break; + x++; + } + + GFX.OBJList[x] = S; + x++; C++; + + while (x < C) { + b = GFX.OBJList[x]; + GFX.OBJList[x] = a; + a = b; + x++; + } + // -- + GFX.Sizes[S] = Size; + GFX.VPositions[S] = VPos; + } + S = (S + 1) & 0x7f; + } while (S != FirstSprite); + + // Terminate the list + GFX.OBJList [C] = -1; + IPPU.OBJChanged = FALSE; +} + +void DrawOBJS (bool8_32 OnMain = FALSE, uint8 D = 0) +{ + int bg_ta_ns; + int bg_ta; + uint32 O; + uint32 BaseTile, Tile; + + CHECK_SOUND(); + + BG.BitShift = 4; + SelectConvertTile(); + BG.TileShift = 5; + //BG.TileAddress = PPU.OBJNameBase; + BG.StartPalette = 128; + BG.PaletteShift = 4; + BG.PaletteMask = 7; + BG.Buffer = IPPU.TileCache [TILE_4BIT]; + BG.Buffered = IPPU.TileCached [TILE_4BIT]; + //BG.NameSelect = PPU.OBJNameSelect; + BG.DirectColourMode = FALSE; + + SelectPalette(); + bg_ta = PPU.OBJNameBase; + bg_ta_ns = bg_ta + PPU.OBJNameSelect; + + GFX.Z1 = D + 2; + + int I = 0; + for (int S = GFX.OBJList [I++]; S >= 0; S = GFX.OBJList [I++]) + { + int VPos = GFX.VPositions [S]; + int Size = GFX.Sizes[S]; + int TileInc = 1; + int Offset; + + if (VPos + Size <= (int) GFX.StartY || VPos > (int) GFX.EndY) + continue; + + if (OnMain && SUB_OR_ADD(4)) + { + SelectTileRenderer (!GFX.Pseudo && PPU.OBJ [S].Palette < 4, true); + } + + BaseTile = PPU.OBJ[S].Name | (PPU.OBJ[S].Palette << 10); + + if (PPU.OBJ[S].HFlip) + { + BaseTile += ((Size >> 3) - 1) | H_FLIP; + TileInc = -1; + } + + if (PPU.OBJ[S].VFlip) BaseTile |= V_FLIP; + //BaseTile |= PPU.OBJ[S].VFlip << 15; + + int clipcount = GFX.pCurrentClip->Count [4]; + if (!clipcount) clipcount = 1; + + GFX.Z2 = (PPU.OBJ[S].Priority + 1) * 4 + D; + + for (int clip = 0; clip < clipcount; clip++) + { + int Left; + int Right; + if (!GFX.pCurrentClip->Count [4]) + { + Left = 0; + Right = 256; + } + else + { + Left = GFX.pCurrentClip->Left [clip][4]; + Right = GFX.pCurrentClip->Right [clip][4]; + } + + if (Right <= Left || PPU.OBJ[S].HPos + Size <= Left || + PPU.OBJ[S].HPos >= Right) + continue; + + for (int Y = 0; Y < Size; Y += 8) + { + if (VPos + Y + 7 >= (int) GFX.StartY && VPos + Y <= (int) GFX.EndY) + { + int StartLine; + int TileLine; + int LineCount; + int Last; + + if ((StartLine = VPos + Y) < (int) GFX.StartY) + { + StartLine = GFX.StartY - StartLine; + LineCount = 8 - StartLine; + } + else + { + StartLine = 0; + LineCount = 8; + } + if ((Last = VPos + Y + 7 - GFX.EndY) > 0) + if ((LineCount -= Last) <= 0) + break; + + TileLine = StartLine << 3; + + O = (VPos + Y + StartLine) * GFX_PPL; + if (!PPU.OBJ[S].VFlip) Tile = BaseTile + (Y << 1); + else Tile = BaseTile + ((Size - Y - 8) << 1); + + if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + else BG.TileAddress = bg_ta; + + int Middle = Size >> 3; + if (PPU.OBJ[S].HPos < Left) + { + Tile += ((Left - PPU.OBJ[S].HPos) >> 3) * TileInc; + Middle -= (Left - PPU.OBJ[S].HPos) >> 3; + O += Left * GFX_PIXSIZE; + if ((Offset = (Left - PPU.OBJ[S].HPos) & 7)) + { + O -= Offset * GFX_PIXSIZE; + int W = 8 - Offset; + int Width = Right - Left; + if (W > Width) W = Width; + //if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + //else BG.TileAddress = bg_ta; + (*DrawClippedTilePtr) (Tile, O, Offset, W, TileLine, LineCount); + + if (W >= Width) + continue; + Tile += TileInc; + Middle--; + O += 8 * GFX_PIXSIZE; + } + } + else + O += PPU.OBJ[S].HPos * GFX_PIXSIZE; + + if (PPU.OBJ[S].HPos + Size >= Right) + { + Middle -= ((PPU.OBJ[S].HPos + Size + 7) - + Right) >> 3; + Offset = (Right - (PPU.OBJ[S].HPos + Size)) & 7; + } + else + Offset = 0; + + for (int X = 0; X < Middle; X++, O += 8 * GFX_PIXSIZE, + Tile += TileInc) + { + //if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + //else BG.TileAddress = bg_ta; + (*DrawTilePtr) (Tile, O, TileLine, LineCount); + } + if (Offset) + { + //if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + //else BG.TileAddress = bg_ta; + (*DrawClippedTilePtr) (Tile, O, 0, Offset, TileLine, LineCount); + } + } + } + } + } +} +void DrawBackgroundMosaic (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackgroundMosaic(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + CHECK_SOUND(); + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint8 depths [2] = {Z1, Z2}; + + if (BGMode == 0) + BG.StartPalette = bg << 5; + else + BG.StartPalette = 0; + SelectPalette(); + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(((uint8*)SC1-Memory.VRAM)>=0x10000) + SC1-=0x08000; + + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + uint32 Lines; + uint32 OffsetMask; + uint32 OffsetShift; + + if (BG.TileSize == 16) + { + OffsetMask = 0x3ff; + OffsetShift = 4; + } + else + { + OffsetMask = 0x1ff; + OffsetShift = 3; + } + + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines) + { + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + uint32 MosaicOffset = Y % PPU.Mosaic; + + for (Lines = 1; Lines < PPU.Mosaic - MosaicOffset; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + uint32 MosaicLine = VOffset + Y - MosaicOffset; + + if (Y + Lines > GFX.EndY) + Lines = GFX.EndY + 1 - Y; + uint32 VirtAlign = (MosaicLine & 7) << 3; + + uint16 *b1; + uint16 *b2; + + uint32 ScreenLine = MosaicLine >> OffsetShift; + uint32 Rem16 = MosaicLine & 15; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + uint16 *t; + uint32 Left = 0; + uint32 Right = 256; + + uint32 ClipCount = GFX.pCurrentClip->Count [bg]; + uint32 HPos = HOffset; + uint32 PixWidth = PPU.Mosaic; + + if (!ClipCount) + ClipCount = 1; + + for (uint32 clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [bg]) + { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + uint32 r = Left % PPU.Mosaic; + HPos = HOffset + Left; + PixWidth = PPU.Mosaic - r; + } + uint32 s = Y * GFX_PPL + Left * GFX_PIXSIZE; + for (uint32 x = Left; x < Right; x += PixWidth, + s += PixWidth * GFX_PIXSIZE, + HPos += PixWidth, PixWidth = PPU.Mosaic) + { + uint32 Quot = (HPos & OffsetMask) >> 3; + + if (x + PixWidth >= Right) + PixWidth = Right - x; + + if (BG.TileSize == 8) + { + if (Quot > 31) + t = b2 + (Quot & 0x1f); + else + t = b1 + Quot; + } + else + { + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + } + + Tile = READ_2BYTES (t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + // Draw tile... + if (BG.TileSize != 8) + { + if (Tile & H_FLIP) + { + // Horizontal flip, but what about vertical flip ? + if (Tile & V_FLIP) + { + // Both horzontal & vertical flip + if (Rem16 < 8) + { + (*DrawLargePixelPtr) (Tile + 17 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + 1 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + else + { + // Horizontal flip only + if (Rem16 > 7) + { + (*DrawLargePixelPtr) (Tile + 17 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + 1 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } + else + { + // No horizontal flip, but is there a vertical flip ? + if (Tile & V_FLIP) + { + // Vertical flip only + if (Rem16 < 8) + { + (*DrawLargePixelPtr) (Tile + 16 + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + else + { + // Normal unflipped + if (Rem16 > 7) + { + (*DrawLargePixelPtr) (Tile + 16 + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } + } + else + (*DrawLargePixelPtr) (Tile, s, HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } +} + +void DrawBackgroundOffset (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackgroundOffse(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + + CHECK_SOUND(); + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint16 *BPS0; + uint16 *BPS1; + uint16 *BPS2; + uint16 *BPS3; + uint32 Width; + int VOffsetOffset = BGMode == 4 ? 0 : 32; + uint8 depths [2] = {Z1, Z2}; + + BG.StartPalette = 0; + SelectPalette(); + + BPS0 = (uint16 *) &Memory.VRAM[PPU.BG[2].SCBase << 1]; + + if (PPU.BG[2].SCSize & 1) + BPS1 = BPS0 + 1024; + else + BPS1 = BPS0; + + if (PPU.BG[2].SCSize & 2) + BPS2 = BPS1 + 1024; + else + BPS2 = BPS0; + + if (PPU.BG[2].SCSize & 1) + BPS3 = BPS2 + 1024; + else + BPS3 = BPS2; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(((uint8*)SC1-Memory.VRAM)>=0x10000) + SC1-=0x08000; + + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + static const int Lines = 1; + int OffsetMask; + int OffsetShift; + int OffsetEnableMask = 1 << (bg + 13); + + if (BG.TileSize == 16) + { + OffsetMask = 0x3ff; + OffsetShift = 4; + } + else + { + OffsetMask = 0x1ff; + OffsetShift = 3; + } + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y++) + { + uint32 VOff = LineData [Y].BG[2].VOffset - 1; + uint32 HOff = LineData [Y].BG[2].HOffset; + int VirtAlign; + int ScreenLine = VOff >> 3; + uint16 *s0; + uint16 *s1; + uint16 *s2; + + if (ScreenLine & 0x20) + s1 = BPS2, s2 = BPS3; + else + s1 = BPS0, s2 = BPS1; + + s1 += (ScreenLine & 0x1f) << 5; + s2 += (ScreenLine & 0x1f) << 5; + + if(BGMode != 4) + { + if((ScreenLine & 0x1f) == 0x1f) + { + if(ScreenLine & 0x20) + VOffsetOffset = BPS0 - BPS2 - 0x1f*32; + else + VOffsetOffset = BPS2 - BPS0 - 0x1f*32; + } + else + { + VOffsetOffset = 32; + } + } + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + + for (int clip = 0; clip < clipcount; clip++) + { + uint32 Left; + uint32 Right; + + if (!GFX.pCurrentClip->Count [bg]) + { + Left = 0; + Right = 256; + } + else + { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) + continue; + } + + uint32 VOffset; + uint32 HOffset; + uint32 LineHOffset=LineData [Y].BG[bg].HOffset; + uint32 Offset; + uint32 HPos; + uint32 Quot; + uint32 Count; + uint16 *t; + uint32 Quot2; + uint32 VCellOffset; + uint32 HCellOffset; + uint16 *b1; + uint16 *b2; + uint32 TotalCount = 0; + uint32 MaxCount = 8; + + uint32 s = Left * GFX_PIXSIZE + Y * GFX_PPL; + bool8_32 left_hand_edge = (Left == 0); + Width = Right - Left; + + if (Left & 7) + MaxCount = 8 - (Left & 7); + + while (Left < Right) + { + if (left_hand_edge) + { + // The SNES offset-per-tile background mode has a + // hardware limitation that the offsets cannot be set + // for the tile at the left-hand edge of the screen. + VOffset = LineData [Y].BG[bg].VOffset; + HOffset = LineHOffset; + left_hand_edge = FALSE; + } + else + { + // All subsequent offset tile data is shifted left by one, + // hence the - 1 below. + Quot2 = ((HOff + Left - 1) & OffsetMask) >> 3; + + if (Quot2 > 31) + s0 = s2 + (Quot2 & 0x1f); + else + s0 = s1 + Quot2; + + HCellOffset = READ_2BYTES (s0); + + if (BGMode == 4) + { + VOffset = LineData [Y].BG[bg].VOffset; + HOffset=LineHOffset; + if ((HCellOffset & OffsetEnableMask)) + { + if (HCellOffset & 0x8000) + VOffset = HCellOffset + 1; + else + HOffset = HCellOffset; + } + } + else + { + VCellOffset = READ_2BYTES (s0 + VOffsetOffset); + if ((VCellOffset & OffsetEnableMask)) + VOffset = VCellOffset + 1; + else + VOffset = LineData [Y].BG[bg].VOffset; + + if ((HCellOffset & OffsetEnableMask)) + HOffset = (HCellOffset & ~7)|(LineHOffset&7); + else + HOffset=LineHOffset; + } + } + VirtAlign = ((Y + VOffset) & 7) << 3; + ScreenLine = (VOffset + Y) >> OffsetShift; + + int tx_index; + tx_index = ( ((VOffset + Y) & 15) <= 7 ) << 3; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + HPos = (HOffset + Left) & OffsetMask; + + Quot = HPos >> 3; + + if (BG.TileSize == 8) + { + if (Quot > 31) + t = b2 + (Quot & 0x1f); + else + t = b1 + Quot; + } + else + { + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + } + + if (MaxCount + TotalCount > Width) + MaxCount = Width - TotalCount; + + Offset = HPos & 7; + + Count = 8 - Offset; + if (Count > MaxCount) + Count = MaxCount; + + s -= Offset * GFX_PIXSIZE; + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + if (Tile != TileBlank) + if (BG.TileSize == 8) + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + else + { + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + } + + Left += Count; + TotalCount += Count; + s += (Offset + Count) * GFX_PIXSIZE; + MaxCount = 8; + } + } + } +} + +void DrawBackgroundMode5 (uint32 /* BGMODE */, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackgroundMode5(?, %i, %i, %i)\n", bg, Z1, Z2); +#endif + + CHECK_SOUND(); + + uint8 depths [2] = {Z1, Z2}; + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 Width; + + BG.StartPalette = 0; + SelectPalette(); + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if ((PPU.BG[bg].SCSize & 1)) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if((SC1-(unsigned short*)Memory.VRAM)>0x10000) + SC1=(uint16*)&Memory.VRAM[(((uint8*)SC1)-Memory.VRAM)%0x10000]; + + if ((PPU.BG[bg].SCSize & 2)) + SC2 = SC1 + 1024; + else SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + if ((PPU.BG[bg].SCSize & 1)) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + int Lines; + int VOffsetMask; + int VOffsetShift; + + if (BG.TileSize == 16) + { + VOffsetMask = 0x3ff; + VOffsetShift = 4; + } + else + { + VOffsetMask = 0x1ff; + VOffsetShift = 3; + } + int endy = GFX.EndY; + + for (int Y = GFX.StartY; Y <= endy; Y += Lines) + { + //int y = Y; + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + for (Lines = 1; Lines < 8 - VirtAlign; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + HOffset <<= 1; + if (Y + Lines > endy) + Lines = endy + 1 - Y; + + int ScreenLine = (VOffset + Y) >> VOffsetShift; + int t1; + int t2; + if (((VOffset + Y) & 15) > 7) + { + t1 = 16; + t2 = 0; + } + else + { + t1 = 0; + t2 = 16; + } + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + for (int clip = 0; clip < clipcount; clip++) + { + int Left; + int Right; + + if (!GFX.pCurrentClip->Count [bg]) + { + Left = 0; + Right = 512; + } + else + { + Left = GFX.pCurrentClip->Left [clip][bg] * 2; + Right = GFX.pCurrentClip->Right [clip][bg] * 2; + + if (Right <= Left) + continue; + } + + uint32 s = (Left>>1) * GFX_PIXSIZE + Y * GFX_PPL; + uint32 HPos = (HOffset + Left * GFX_PIXSIZE) & 0x3ff; + + uint32 Quot = HPos >> 3; + uint32 Count = 0; + + uint16 *t; + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + + Width = Right - Left; + // Left hand edge clipped tile + if (HPos & 7) + { + int Offset = (HPos & 7); + Count = 8 - Offset; + if (Count > Width) + Count = Width; + s -= (Offset>>1); + Tile = READ_2BYTES (t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResClippedTilePtr) (Tile + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + t1 + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResClippedTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResClippedTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResClippedTilePtr) (Tile + t2 + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + + t += Quot & 1; + if (Quot == 63) + t = b2; + else if (Quot == 127) + t = b1; + Quot++; + s += 4; + } + + // Middle, unclipped tiles + Count = Width - Count; + int Middle = Count >> 3; + Count &= 7; + for (int C = Middle; C > 0; s += 4, Quot++, C--) + { + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResTilePtr) (Tile + (Quot & 1), + s, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResTilePtr) (Tile + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResTilePtr) (Tile + t1 + (Quot & 1), + s, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResTilePtr) (Tile + t2 + (Quot & 1), + s, VirtAlign, Lines); + } + } + + t += Quot & 1; + if (Quot == 63) + t = b2; + else + if (Quot == 127) + t = b1; + } + + // Right-hand edge clipped tiles + if (Count) + { + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResClippedTilePtr) (Tile + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + t1 + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResClippedTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResClippedTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResClippedTilePtr) (Tile + t2 + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + } + } + } +} + +void DrawBackground_8(uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackground_8(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + //uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 depths [2] = {Z1, Z2}; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + SC1 = SC0 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(SC1 >= (unsigned short*)(Memory.VRAM+0x10000)) SC1 = (uint16*)&Memory.VRAM[((uint8*)SC1-&Memory.VRAM[0]) & 0xffff]; + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) SC2 -= 0x08000; + + SC3 = SC2 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) SC3 -= 0x08000; + + int Lines; + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines){ + int y_ppl = Y * GFX_PPL; + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + int maxLines = GFX.EndY - Y + 1; + if ((8 - VirtAlign) < maxLines) maxLines = (8 - VirtAlign); + + for (Lines = 1; Lines < maxLines; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + + VirtAlign <<= 3; + + uint32 ScreenLine = (VOffset + Y) >> 3; + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + uint32 Left; + uint32 Right; + int clip = 0; + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) { + Left = 0; + Right = 256; + } + + do { + if (clipcount) { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) {clip++; continue;} + } + + uint32 s = Left + y_ppl; + uint32 HPos = (HOffset + Left) & 0x1ff; + uint32 Quot = HPos >> 3; + uint32 Count = 0; + uint16 *t; + uint16 *b; + + if (Quot > 31) { + t = b2 + (Quot & 0x1f); + b = b1; + Quot -= 32; + } + else { + t = b1 + Quot; + b = b2; + } + + uint32 Width = Right - Left; + + // Left hand edge clipped tile + uint32 Offset = (HPos & 7); + if (Offset){ + Count = 8 - Offset; + if (Count > Width) Count = Width; + s -= Offset; + //Tile = READ_2BYTES(t); + register uint32 Tile = *(t++); + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + //t++; + if (Quot == 31) t = b; + //else if (Quot == 63) t = b1; + Quot++; + s += 8; + } + + // Middle, unclipped tiles + Count = Width - Count; + for (int C = Count >> 3; C > 0; s += 8, Quot++, C--){ + //Tile = READ_2BYTES(t); + register uint32 Tile = *(t++); + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawTilePtr) (Tile, s, VirtAlign, Lines); + } + + //t++; + if (Quot == 31) t = b; + //else if (Quot == 63) t = b1; + } + + // Right-hand edge clipped tiles + if (Count & 7){ + //Tile = READ_2BYTES(t); + register uint32 Tile = *t; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, 0, Count & 7, VirtAlign, Lines); + } + } + clip ++; + } while (clip < clipcount); + } +} + +void DrawBackground_16 (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackground_16(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + //uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 depths [2] = {Z1, Z2}; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + SC1 = SC0 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(SC1 >= (unsigned short*)(Memory.VRAM+0x10000)) SC1 = (uint16*)&Memory.VRAM[((uint8*)SC1-&Memory.VRAM[0]) & 0xffff]; + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) SC2 -= 0x08000; + + SC3 = SC2 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) SC3 -= 0x08000; + + int Lines; + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines){ + int y_ppl = Y * GFX_PPL; + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + int maxLines = GFX.EndY - Y + 1; + if ((8 - VirtAlign) < maxLines) maxLines = (8 - VirtAlign); + + for (Lines = 1; Lines < maxLines; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + + VirtAlign <<= 3; + + uint32 ScreenLine = (VOffset + Y) >> 4; + int tx_index = ( ((VOffset + Y) & 15) <= 7 ) << 3; + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + uint32 Left; + uint32 Right; + int clip = 0; + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) { + Left = 0; + Right = 256; + } + + do { + if (clipcount) { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) {clip++; continue;} + } + + uint32 s = Left + y_ppl; + uint32 HPos = (HOffset + Left) & 0x3ff; + uint32 Quot = HPos >> 3; + uint32 Count = 0; + uint16 *t; + uint16 *b; + + if (Quot > 63) { + t = b2 + ((Quot >> 1) & 0x1f); + b = b1; + Quot -= 64; + } + else { + t = b1 + (Quot >> 1); + b = b2; + } + + + uint32 Width = Right - Left; + + // Left hand edge clipped tile + uint32 Offset = (HPos & 7); + if (Offset){ + Count = 8 - Offset; + if (Count > Width) Count = Width; + s -= Offset; + //Tile = READ_2BYTES(t); + uint32 Tile = *(t); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + //t++; + t += Quot & 1; + if (Quot == 63) t = b; + Quot++; + s += 8; + } + + // Middle, unclipped tiles + Count = Width - Count; + for (int C = Count >> 3; C > 0; s += 8, Quot++, C--){ + //Tile = READ_2BYTES(t); + uint32 Tile = *(t); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + //(*DrawTilePtr) (Tile, s, VirtAlign, Lines); + } + + //t++; + t += Quot & 1; + if (Quot == 63) t = b; + } + + // Right-hand edge clipped tiles + if (Count & 7){ + //Tile = READ_2BYTES(t); + uint32 Tile = *(t); + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, 0, Count & 7, VirtAlign, Lines); + } + } + clip ++; + } while (clip < clipcount); + } +} + + +inline void DrawBackground (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +//StartAnalyze(); + + BG.TileSize = BGSizes [PPU.BG[bg].BGSize]; + BG.BitShift = BitShifts[BGMode][bg]; + SelectConvertTile(); + BG.TileShift = TileShifts[BGMode][bg]; + BG.TileAddress = PPU.BG[bg].NameBase << 1; + BG.NameSelect = 0; + BG.Buffer = IPPU.TileCache [Depths [BGMode][bg]]; + BG.Buffered = IPPU.TileCached [Depths [BGMode][bg]]; + BG.PaletteShift = PaletteShifts[BGMode][bg]; + BG.PaletteMask = PaletteMasks[BGMode][bg]; + BG.DirectColourMode = (BGMode == 3 || BGMode == 4) && bg == 0 && (GFX.r2130 & 1); + + if (IPPU.DirectColourMapsNeedRebuild && BG.DirectColourMode) S9xBuildDirectColourMaps (); + + if (PPU.BGMosaic [bg] && PPU.Mosaic > 1){ + DrawBackgroundMosaic (BGMode, bg, Z1, Z2); + return; + + } + switch (BGMode) + { + case 2: + case 4: // Used by Puzzle Bobble + DrawBackgroundOffset (BGMode, bg, Z1, Z2); + break; + + case 5: + case 6: // XXX: is also offset per tile. + DrawBackgroundMode5 (BGMode, bg, Z1, Z2); + break; + case 0: + case 1: + case 3: + CHECK_SOUND(); + + if (BGMode == 0) BG.StartPalette = bg << 5; + else BG.StartPalette = 0; + SelectPalette(); + + if (BG.TileSize == 8) DrawBackground_8 (BGMode, bg, Z1, Z2); + else DrawBackground_16 (BGMode, bg, Z1, Z2); + break; + } +} + +#define _BUILD_SETUP(F) \ +GFX.BuildPixel = BuildPixel##F; \ +GFX.BuildPixel2 = BuildPixel2##F; \ +GFX.DecomposePixel = DecomposePixel##F; \ +RED_LOW_BIT_MASK = RED_LOW_BIT_MASK_##F; \ +GREEN_LOW_BIT_MASK = GREEN_LOW_BIT_MASK_##F; \ +BLUE_LOW_BIT_MASK = BLUE_LOW_BIT_MASK_##F; \ +RED_HI_BIT_MASK = RED_HI_BIT_MASK_##F; \ +GREEN_HI_BIT_MASK = GREEN_HI_BIT_MASK_##F; \ +BLUE_HI_BIT_MASK = BLUE_HI_BIT_MASK_##F; \ +MAX_RED = MAX_RED_##F; \ +MAX_GREEN = MAX_GREEN_##F; \ +MAX_BLUE = MAX_BLUE_##F; \ +GREEN_HI_BIT = ((MAX_GREEN_##F + 1) >> 1); \ +SPARE_RGB_BIT_MASK = SPARE_RGB_BIT_MASK_##F; \ +RGB_LOW_BITS_MASK = (RED_LOW_BIT_MASK_##F | \ + GREEN_LOW_BIT_MASK_##F | \ + BLUE_LOW_BIT_MASK_##F); \ +RGB_HI_BITS_MASK = (RED_HI_BIT_MASK_##F | \ + GREEN_HI_BIT_MASK_##F | \ + BLUE_HI_BIT_MASK_##F); \ +RGB_HI_BITS_MASKx2 = ((RED_HI_BIT_MASK_##F | \ + GREEN_HI_BIT_MASK_##F | \ + BLUE_HI_BIT_MASK_##F) << 1); \ +RGB_REMOVE_LOW_BITS_MASK = ~RGB_LOW_BITS_MASK; \ +FIRST_COLOR_MASK = FIRST_COLOR_MASK_##F; \ +SECOND_COLOR_MASK = SECOND_COLOR_MASK_##F; \ +THIRD_COLOR_MASK = THIRD_COLOR_MASK_##F; \ +ALPHA_BITS_MASK = ALPHA_BITS_MASK_##F; \ +FIRST_THIRD_COLOR_MASK = FIRST_COLOR_MASK | THIRD_COLOR_MASK; \ +TWO_LOW_BITS_MASK = RGB_LOW_BITS_MASK | (RGB_LOW_BITS_MASK << 1); \ +HIGH_BITS_SHIFTED_TWO_MASK = (( (FIRST_COLOR_MASK | SECOND_COLOR_MASK | THIRD_COLOR_MASK) & \ + ~TWO_LOW_BITS_MASK ) >> 2); + +void RenderScreen (uint8 *Screen, bool8_32 sub, bool8_32 force_no_add, uint8 D) +{ + bool8_32 BG0; + bool8_32 BG1; + bool8_32 BG2; + bool8_32 BG3; + bool8_32 OB; + + GFX.S = Screen; + + if (!sub) + { + GFX.pCurrentClip = &IPPU.Clip [0]; + BG0 = ON_MAIN (0) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + BG1 = ON_MAIN (1) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + BG2 = ON_MAIN (2) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + BG3 = ON_MAIN (3) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + OB = ON_MAIN (4) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + } + else + { + GFX.pCurrentClip = &IPPU.Clip [1]; + BG0 = ON_SUB (0) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + BG1 = ON_SUB (1) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + BG2 = ON_SUB (2) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + BG3 = ON_SUB (3) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + OB = ON_SUB (4) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + } + +#ifdef __DEBUG__ + printf("Screen[y1,y2]:[%i,%i],Mode:%i, BG0:%i,BG1:%i,BG2:%i,BG3:%i,OBJ:%i\n", GFX.StartY, GFX.EndY, PPU.BGMode, BG0, BG1, BG2, BG3, OB); +#endif + + sub |= force_no_add; + + if (PPU.BGMode <= 1) + { + if (OB) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); + DrawOBJS (!sub, D); + } + if (BG0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(0)); + DrawBackground (PPU.BGMode, 0, D + 10, D + 14); + } + if (BG1) + { + SelectTileRenderer (sub || !SUB_OR_ADD(1)); + DrawBackground (PPU.BGMode, 1, D + 9, D + 13); + } + if (BG2) + { + SelectTileRenderer (sub || !SUB_OR_ADD(2)); + DrawBackground (PPU.BGMode, 2, D + 3, + PPU.BG3Priority ? D + 17 : D + 6); + } + if (BG3 && PPU.BGMode == 0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(3)); + DrawBackground (PPU.BGMode, 3, D + 2, D + 5); + } + } + else if (PPU.BGMode != 7) + { + if (OB) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); + DrawOBJS (!sub, D); + } + if (BG0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(0)); + DrawBackground (PPU.BGMode, 0, D + 5, D + 13); + } + if (PPU.BGMode != 6 && BG1) + { + SelectTileRenderer (sub || !SUB_OR_ADD(1)); + DrawBackground (PPU.BGMode, 1, D + 2, D + 9); + } + } + else + { + if (OB && ((SNESGameFixes.Mode7Hack && D) || !SNESGameFixes.Mode7Hack)) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); + DrawOBJS (!sub, D); + } + if (BG0 || ((Memory.FillRAM [0x2133] & 0x40) && BG1)) + { + int bg; + + if ((Memory.FillRAM [0x2133] & 0x40)&&BG1) + { + Mode7Depths [0] = (BG0?5:1) + D; + Mode7Depths [1] = 9 + D; + bg = 1; + if (sub || !SUB_OR_ADD(0)) + { + DrawBGMode7Background16Prio (Screen, bg); + } + else + { + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16PrioSub1_2 (Screen, bg); + } + else + { + DrawBGMode7Background16PrioSub (Screen, bg); + } + } + else + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16PrioAdd1_2 (Screen, bg); + } + else + { + DrawBGMode7Background16PrioAdd (Screen, bg); + } + } + } + } + else + { + bg = 0; + if (sub || !SUB_OR_ADD(0)) + { + if (D || !SNESGameFixes.Mode7Hack) DrawBGMode7Background16 (Screen, bg, D+5); + else DrawBGMode7Background16New (Screen); + } + else + { + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Sub1_2 (Screen, bg, D+5); + } + else + { + DrawBGMode7Background16Sub (Screen, bg, D+5); + } + } + else + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Add1_2 (Screen, bg, D+5); + } + else + { + DrawBGMode7Background16Add (Screen, bg, D+5); + } + } + } + } + } + if (OB && SNESGameFixes.Mode7Hack && D==0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); + DrawOBJS (!sub, D); + } + } +} + +#include "font.h" + +void DisplayChar (uint8 *Screen, uint8 c) +{ + int line = (((c & 0x7f) - 32) >> 4) * font_height; + int offset = (((c & 0x7f) - 32) & 15) * font_width; + int h, w; + uint16 *s = (uint16 *) Screen; + for (h = 0; h < font_height; h++, line++, + s += GFX_PPL - font_width) + { + for (w = 0; w < font_width; w++, s++) + { + uint8 p = font [line][offset + w]; + + if (p == '#') + *s = 0xffff; + else + if (p == '.') + *s = BLACK; + } + } +} + +static void S9xDisplayFrameRate () +{ + uint8 *Screen = GFX.Screen + 2 + + (IPPU.RenderedScreenHeight - font_height - 1) * GFX_PITCH; + char string [10]; + int len = 5; + + sprintf (string, "%02d/%02d", IPPU.DisplayedRenderedFrameCount, + (int) Memory.ROMFramesPerSecond); + + int i; + for (i = 0; i < len; i++) + { + DisplayChar (Screen, string [i]); + Screen += (font_width - 1) * sizeof (uint16); + } +} + +static void S9xDisplayString (const char *string) +{ + uint8 *Screen = GFX.Screen + 2 + + (IPPU.RenderedScreenHeight - font_height * 5) * GFX_PITCH; + int len = strlen (string); + int max_chars = IPPU.RenderedScreenWidth / (font_width - 1); + int char_count = 0; + int i; + + for (i = 0; i < len; i++, char_count++) + { + if (char_count >= max_chars || string [i] < 32) + { + Screen -= (font_width - 1) * sizeof (uint16) * max_chars; + Screen += font_height * GFX_PITCH; + if (Screen >= GFX.Screen + GFX_PITCH * IPPU.RenderedScreenHeight) + break; + char_count -= max_chars; + } + if (string [i] < 32) + continue; + DisplayChar (Screen, string [i]); + Screen += (font_width - 1) * sizeof (uint16); + } +} + + +void S9xUpdateScreen () // ~30-50ms! (called from FLUSH_REDRAW()) +{ + GFX.S = GFX.Screen; + + unsigned char *memoryfillram = Memory.FillRAM; + + // get local copies of vid registers to be used later + GFX.r2131 = memoryfillram [0x2131]; // ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN + GFX.r212c = memoryfillram [0x212c]; // MAIN SCREEN, DESIGNATION - used to enable BGS + GFX.r212d = memoryfillram [0x212d]; // SUB SCREEN DESIGNATION - used to enable sub BGS + GFX.r2130 = memoryfillram [0x2130]; // INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION + + // If external sync is off and + // main screens have not been configured the same as the sub screen and + // color addition and subtraction has been diabled then + // Pseudo is 1 + // anything else it is 0 + GFX.Pseudo = (memoryfillram [0x2133] & 8) != 0 && // Use EXTERNAL SYNCHRONIZATION? + (GFX.r212c & 15) != (GFX.r212d & 15) && // Are the main screens different from the sub screens? + (GFX.r2131 & 0x3f) == 0; // Is colour data addition/subtraction disabled on all BGS? + + // If sprite data has been changed then go through and + // refresh the sprites. + if (IPPU.OBJChanged) S9xSetupOBJ (); + + if (PPU.RecomputeClipWindows) ComputeClipWindows (); + + GFX.StartY = IPPU.PreviousLine; + if ((GFX.EndY = IPPU.CurrentLine - 1) >= PPU.ScreenHeight) + GFX.EndY = PPU.ScreenHeight - 1; + + uint32 starty = GFX.StartY; + uint32 endy = GFX.EndY; + uint32 black = BLACK | (BLACK << 16); + + + if (GFX.Pseudo) + { + GFX.r2131 = 0x5f; //0101 1111 - enable addition/subtraction on all BGS and sprites and "1/2 OF COLOR DATA" DESIGNATION + GFX.r212c &= (Memory.FillRAM [0x212d] | 0xf0); + GFX.r212d |= (Memory.FillRAM [0x212c] & 0x0f); + GFX.r2130 |= 2; // enable ADDITION/SUBTRACTION FOR SUB SCREEN + } + + // Check to see if any transparency effects are currently in use + if (!PPU.ForcedBlanking && ADD_OR_SUB_ON_ANYTHING && + (GFX.r2130 & 0x30) != 0x30 && + !((GFX.r2130 & 0x30) == 0x10 && IPPU.Clip[1].Count[5] == 0)) + { + // transparency effects in use, so lets get busy! + struct ClipData *pClip; + uint32 fixedColour; + GFX.FixedColour = BUILD_PIXEL (IPPU.XB [PPU.FixedColourRed], + IPPU.XB [PPU.FixedColourGreen], + IPPU.XB [PPU.FixedColourBlue]); + fixedColour = (GFX.FixedColour<<16|GFX.FixedColour); + // Clear the z-buffer, marking areas 'covered' by the fixed + // colour as depth 1. + pClip = &IPPU.Clip [1]; + + // Clear the z-buffer + + if (pClip->Count [5]) + { + + // Colour window enabled. + // loop around all of the lines being updated + for (uint32 y = starty; y <= endy; y++) + { + // Clear the subZbuffer + memset32 ((uint32_t*)(GFX.SubZBuffer + y * GFX_ZPITCH),0, (256>>2)); + // Clear the Zbuffer + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH),0, (256>>2)); + if (IPPU.Clip[0].Count [5]) { + // if there is clipping then clear subscreen to a black color + memset32 ((uint32_t*)(GFX.SubScreen + y * GFX_PITCH), black, (256>>1)); + } + + // loop through all window clippings + for (uint32 c = 0; c < pClip->Count [5]; c++) + { + if (pClip->Right [c][5] > pClip->Left [c][5]) + { + memset (GFX.SubZBuffer + y * GFX_ZPITCH + pClip->Left [c][5], + 1, pClip->Right [c][5] - pClip->Left [c][5]); + + if (IPPU.Clip [0].Count [5]) + { + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + + register unsigned int width = pClip->Right [c][5] - pClip->Left [c][5]; + if (width > 0) { + asm volatile ( + " mov r0, %[fixedcolour] \n" + " subs %[width], %[width], #4 \n" + " bmi 2f \n" + + "1: \n" + " subs %[width], %[width], #4 \n" + " stmia %[p]!, {r0, %[fixedcolour]}\n" + " bpl 1b \n" + + "2: \n" + " tst %[width], #1 \n" + " strneh %[fixedcolour], [%[p]], #2 \n" + + " tst %[width], #2 \n" + " strne %[fixedcolour], [%[p]], #4 \n" + + : [width] "+r" (width) + : [fixedcolour] "r" (fixedColour), + [p] "r" (((uint16 *) (GFX.SubScreen + y * GFX_PITCH)) + pClip->Left [c][5]) + : "r0", "cc" + ); + } + } + } + } + } + + } + else + { + // No windows are clipping the main screen + // this simplifies the screen clearing process + // loop through all of the lines to be updated + for (uint32 y = starty; y <= endy; y++) { + // Clear the Zbuffer + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH),0, (256>>2)); + // clear the sub Zbuffer to 1 + memset32 ((uint32_t*)(GFX.SubZBuffer + y * GFX_ZPITCH), 0x01010101, (256>>2)); + + if (IPPU.Clip [0].Count [5]) { + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + + memset32 ((uint32_t*)(GFX.SubScreen + y * GFX_PITCH), fixedColour, (256>>1)); + } + } + } + if (ANYTHING_ON_SUB) + { + GFX.DB = GFX.SubZBuffer; + RenderScreen (GFX.SubScreen, TRUE, TRUE, SUB_SCREEN_DEPTH); + } + + if (IPPU.Clip [0].Count [5]) + { + asm volatile ( + "1: \n" + " mov r1, #(256 >> 2) \n" + + "2: \n" + // four pixels at once + " ldrb r0, [%[d]], #1 \n" + " ldrb r4, [%[d]], #1 \n" + + " bics r0, r0, #1 \n" + " ldrneh r0, [%[p], %[delta]] \n" + + " bics r4, r4, #1 \n" + " ldrneh r4, [%[p], %[delta2]] \n" + + " strh r0, [%[p]], #2 \n" + " strh r4, [%[p]], #2 \n" + + " ldrb r0, [%[d]], #1 \n" + " ldrb r4, [%[d]], #1 \n" + + " bics r0, r0, #1 \n" + " ldrneh r0, [%[p], %[delta]] \n" + + " bics r4, r4, #1 \n" + " ldrneh r4, [%[p], %[delta2]] \n" + + " strh r0, [%[p]], #2 \n" + " strh r4, [%[p]], #2 \n" + + " subs r1, r1, #1 \n" + " bne 2b \n" + "3: \n" + " subs %[lines], %[lines], #1 \n" + " add %[p], %[p], #(640 - 512) \n" + " add %[d], %[d], #(320 - 256) \n" + " bne 1b \n" + "4: \n" + + : + : [p] "r" ((uint16 *) (GFX.Screen + starty * GFX_PITCH)), + [d] "r" (GFX.SubZBuffer + starty * GFX_ZPITCH), + [delta] "r" (GFX.Delta << 1), + [delta2] "r" ((GFX.Delta << 1) + 2), + [lines] "r" (endy - starty + 1) + : "r0", "r1", "r3", "r4", "cc" + ); + } + + GFX.DB = GFX.ZBuffer; + RenderScreen (GFX.Screen, FALSE, FALSE, MAIN_SCREEN_DEPTH); + if (SUB_OR_ADD(5)) + { + uint32 back = IPPU.ScreenColors [0]; + uint32 Left = 0; + uint32 Right = 256; + uint32 Count; + + pClip = &IPPU.Clip [0]; + + for (uint32 y = starty; y <= endy; y++) + { + if (!(Count = pClip->Count [5])) + { + Left = 0; + Right = 256; + Count = 1; + } + + for (uint32 b = 0; b < Count; b++) + { + if (pClip->Count [5]) + { + Left = pClip->Left [b][5]; + Right = pClip->Right [b][5]; + if (Right <= Left) + continue; + } +#define SUBSCREEN_BG(rop, half) \ +\ +asm volatile (\ +" ldrb r0, [%[d]], #1 \n"\ +"71: \n"\ +\ +" movs r0, r0 \n"\ +" ldreqb r1, [%[d], %[zdelta]] \n"\ +" bne 72f \n"\ +\ +" cmp r1, #1 \n"\ +" beq 74f \n"\ +" ldrh r1, [%[p], %[delta]] \n"\ +" mov r0, %[back] \n"\ +\ +ROP_##rop##half (r0, r1)\ +\ +" strh r0, [%[p]] \n"\ +"72: \n"\ +" add %[p], %[p], #2 \n"\ +" subs %[c], %[c], #1 \n"\ +" ldrneb r0, [%[d]], #1 \n"\ +" bne 71b \n"\ +" b 75f \n"\ +"74: \n"\ +" streqh %[fixedcolour], [%[p]], #2 \n"\ +" strloh %[back], [%[p]], #2 \n"\ +" subs %[c], %[c], #1 \n"\ +" ldrneb r0, [%[d]], #1 \n"\ +" bne 71b \n"\ +"75: \n"\ +:\ +:[p] "r" ((uint16 *) (GFX.Screen + y * GFX_PITCH) + Left),\ + [d] "r" (GFX.ZBuffer + y * GFX_ZPITCH + Left),\ + [zdelta] "r" (GFX.DepthDelta),\ + [back] "r" (back),\ + [delta] "r" (GFX.Delta << 1),\ + [fixedcolour] "r" (COLOR_##rop (back, GFX.FixedColour)),\ + [c] "r" (Right - Left) \ +: "r0", "r1", "cc"\ +); + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + SUBSCREEN_BG(SUB, 1_2) + } + else + { + SUBSCREEN_BG(SUB, ) + + } + } + else + if (GFX.r2131 & 0x40) + { + SUBSCREEN_BG(ADD, 1_2) + } + else if (back != 0) { + SUBSCREEN_BG(ADD, ) + } + else + { + if (!pClip->Count [5]) + { + // The backdrop has not been cleared yet - so + // copy the sub-screen to the main screen + // or fill it with the back-drop colour if the + // sub-screen is clear. + asm volatile ( + " ldrb r0, [%[d]], #1 \n" + "31: \n" + + " movs r0, r0 \n" + " ldreqb r1, [%[d], %[zdelta]] \n" + " bne 32f \n" + + " cmp r1, #1 \n" + " ldrhih r0, [%[p], %[delta]] \n" + " strloh %[back], [%[p]] \n" + " streqh %[fixedcolour], [%[p]] \n" + " strhih r0, [%[p]] \n" + + "32: \n" + " subs %[c], %[c], #1 \n" + " add %[p], %[p], #2 \n" + " ldrneb r0, [%[d]], #1 \n" + " bne 31b \n" + " \n" + : + :[p] "r" ((uint16 *) (GFX.Screen + y * GFX_PITCH) + Left), + [d] "r" (GFX.ZBuffer + y * GFX_ZPITCH + Left), + [zdelta] "r" (GFX.DepthDelta), + [back] "r" (back), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [c] "r" (Right - Left) + : "r0", "r1", "cc" + + ); + + } + } + } + } + + } + else + { + // Subscreen not being added to back + uint32 back = IPPU.ScreenColors [0] | (IPPU.ScreenColors [0] << 16); + pClip = &IPPU.Clip [0]; + + if (pClip->Count [5]) + { + for (uint32 y = starty; y <= endy; y++) + { + for (uint32 b = 0; b < pClip->Count [5]; b++) + { + uint32 Left = pClip->Left [b][5]; + uint32 Right = pClip->Right [b][5]; + if (Left >= Right) continue; + asm volatile ( + + " tst %[c], #1 \n" + " bne 21f \n" + + " ldrb r0, [%[d]], #1 \n" + " add %[p], %[p], #2 \n" + " movs r0, r0 \n" + " streqh %[back], [%[p], #-2] \n" + " subs %[c], %[c], #1 \n" + " beq 22f \n" + + "21: \n" + + " ldrb r0, [%[d]], #1 \n" + " ldrb r1, [%[d]], #1 \n" + " add %[p], %[p], #4 \n" + + " movs r0, r0 \n" + " streqh %[back], [%[p], #-4] \n" + + " movs r1, r1 \n" + " streqh %[back], [%[p], #-2] \n" + + " subs %[c], %[c], #2 \n" + " bhi 21b \n" + "22: \n" + : + :[p] "r" ((uint16 *) (GFX.Screen + y * GFX_PITCH) + Left), + [d] "r" (GFX.ZBuffer + y * GFX_ZPITCH + Left), + [back] "r" (back), + [c] "r" (Right - Left) + : "r0", "r1", "cc" + + ); + } + } + } + else + { + asm volatile ( + "@ -- SubScreen clear \n" + "1113: \n" + " mov r1, #(256/8) \n" + "1112: \n" + " ldr r0, [%[d]], #4 \n" + + " add %[p], %[p], #8 \n" + + " tst r0, #0x0ff \n" + " streqh %[back], [%[p], #-8] \n" + + " tst r0, #0x0ff00 \n" + " streqh %[back], [%[p], #-6] \n" + + " tst r0, #0x0ff0000 \n" + " streqh %[back], [%[p], #-4] \n" + + " tst r0, #0x0ff000000 \n" + " streqh %[back], [%[p], #-2] \n" + + " ldr r0, [%[d]], #4 \n" + + " add %[p], %[p], #8 \n" + + " tst r0, #0x0ff \n" + " streqh %[back], [%[p], #-8] \n" + + " tst r0, #0x0ff00 \n" + " streqh %[back], [%[p], #-6] \n" + + " tst r0, #0x0ff0000 \n" + " streqh %[back], [%[p], #-4] \n" + + " tst r0, #0x0ff000000 \n" + " streqh %[back], [%[p], #-2] \n" + + " subs r1, r1, #1 \n" + " bne 1112b \n" + + " subs %[lines], %[lines], #1 \n" + " add %[p], %[p], #(640-512) \n" + " add %[d], %[d], #(320-256) \n" + " bne 1113b \n" + "1114:" + : + :[p] "r" (GFX.Screen + starty * GFX_PITCH), + [d] "r" (GFX.ZBuffer + starty * GFX_ZPITCH), + [back] "r" (back), + [lines] "r" (endy - starty + 1) + : "r0", "r1", "cc" + ); + } + } + } + else + { + // 16bit and transparency but currently no transparency effects in + // operation. + + // get the back colour of the current screen + uint32 back = IPPU.ScreenColors [0] | + (IPPU.ScreenColors [0] << 16); + + // if forceblanking in use then use black instead of the back color + if (PPU.ForcedBlanking) + back = black; + + // not sure what Clip is used for yet + // could be a check to see if there is any clipping present? + if (IPPU.Clip [0].Count[5]) + { + + // loop through all of the lines that are going to be updated as part of this screen update + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), black, + IPPU.RenderedScreenWidth>>1); + + if (black!=back) + { + for (uint32 c = 0; c < IPPU.Clip [0].Count [5]; c++) + { + if (IPPU.Clip [0].Right [c][5] > IPPU.Clip [0].Left [c][5]) + { + register unsigned int width = IPPU.Clip [0].Right [c][5] - IPPU.Clip [0].Left [c][5]; + if (width > 0) { + asm volatile ( + " mov r0, %[back] \n" + " subs %[width], %[width], #4 \n" + " bmi 2f \n" + + "1: \n" + " subs %[width], %[width], #4 \n" + " stmia %[p]!, {r0, %[back]} \n" + " bpl 1b \n" + + "2: \n" + " tst %[width], #1 \n" + " strneh %[back], [%[p]], #2 \n" + + " tst %[width], #2 \n" + " strne %[back], [%[p]], #4 \n" + : [width] "+r" (width) + : [back] "r" (back | (back << 16)), + [p] "r" (((uint16 *) (GFX.SubScreen + y * GFX_PITCH)) + IPPU.Clip [0].Left [c][5]) + : "r0", "cc" + ); + } + + } + } + } + } + } + else + { + // there is no clipping to worry about so just fill with the back colour + for (uint32 y = starty; y <= endy; y++) { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), back, (256>>1)); + } + + } + + // If Forced blanking is not in effect + if (!PPU.ForcedBlanking) + { + // Clear the Zbuffer for each of the lines which are going to be updated + for (uint32 y = starty; y <= endy; y++) { + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH), 0, (256>>2)); + } + GFX.DB = GFX.ZBuffer; // save pointer to Zbuffer in GFX object + RenderScreen (GFX.Screen, FALSE, TRUE, SUB_SCREEN_DEPTH); + } + } + IPPU.PreviousLine = IPPU.CurrentLine; +} + +// -x- +void S9xUpdateScreenNoTransparency () // ~30-50ms! (called from FLUSH_REDRAW()) +{ + GFX.S = GFX.Screen; + + unsigned char *memoryfillram = Memory.FillRAM; + + // get local copies of vid registers to be used later + GFX.r2131 = memoryfillram [0x2131]; // ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN + GFX.r212c = memoryfillram [0x212c]; // MAIN SCREEN, DESIGNATION - used to enable BGS + GFX.r212d = memoryfillram [0x212d]; // SUB SCREEN DESIGNATION - used to enable sub BGS + GFX.r2130 = memoryfillram [0x2130]; // INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION + + // If external sync is off and + // main screens have not been configured the same as the sub screen and + // color addition and subtraction has been diabled then + // Pseudo is 1 + // anything else it is 0 + GFX.Pseudo = (memoryfillram [0x2133] & 8) != 0 && // Use EXTERNAL SYNCHRONIZATION? + (GFX.r212c & 15) != (GFX.r212d & 15) && // Are the main screens different from the sub screens? + (GFX.r2131 & 0x3f) == 0; // Is colour data addition/subtraction disabled on all BGS? + + // If sprite data has been changed then go through and + // refresh the sprites. + if (IPPU.OBJChanged) + { + S9xSetupOBJ (); + } + + if (PPU.RecomputeClipWindows) ComputeClipWindows(); + + GFX.StartY = IPPU.PreviousLine; + if ((GFX.EndY = IPPU.CurrentLine - 1) >= PPU.ScreenHeight) + GFX.EndY = PPU.ScreenHeight - 1; + + uint32 starty = GFX.StartY; + uint32 endy = GFX.EndY; + + uint32 black = BLACK | (BLACK << 16); + + // get back colour to be used in clearing the screen + register uint32 back; + if (!(Memory.FillRAM [0x2131] & 0x80) &&(Memory.FillRAM[0x2131] & 0x20) && + (PPU.FixedColourRed || PPU.FixedColourGreen || PPU.FixedColourBlue)) + { + back = (IPPU.XB[PPU.FixedColourRed]<<11) | + (IPPU.XB[PPU.FixedColourGreen] << 6) | + (IPPU.XB[PPU.FixedColourBlue] << 1) | 1; + back = (back << 16) | back; + } + else + { + back = IPPU.ScreenColors [0] | (IPPU.ScreenColors [0] << 16); + } + + // if Forcedblanking in use then back colour becomes black + if (PPU.ForcedBlanking) + back = black; + else + { + SelectTileRenderer (TRUE); //selects the tile renderers to be used + // TRUE means to use the default + // FALSE means use best renderer based on current + // graphics register settings + } + + // now clear all graphics lines which are being updated using the back colour + for (register uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), back, + IPPU.RenderedScreenWidth>>1); + } + + if (!PPU.ForcedBlanking) + { + // Loop through all lines being updated and clear the + // zbuffer for each of the lines + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH), 0, + IPPU.RenderedScreenWidth>>2); + } + GFX.DB = GFX.ZBuffer; // save pointer to Zbuffer in GFX object + GFX.pCurrentClip = &IPPU.Clip [0]; + +// Define an inline function to handle clipping +#define FIXCLIP(n) \ +if (GFX.r212c & (1 << (n))) \ + GFX.pCurrentClip = &IPPU.Clip [0]; \ +else \ + GFX.pCurrentClip = &IPPU.Clip [1] + +// Define an inline function to handle which BGs are being displayed +#define DISPLAY(n) ((GFX.r212c & n) || ((GFX.r212d & n) && subadd)) + + uint8 subadd = GFX.r2131 & 0x3f; + + // go through all BGS are check if they need to be displayed + bool8_32 BG0 = DISPLAY(1) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + bool8_32 BG1 = DISPLAY(2) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + bool8_32 BG2 = DISPLAY(4) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + bool8_32 BG3 = DISPLAY(8) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + bool8_32 OB = DISPLAY(16) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + + if (PPU.BGMode <= 1) + { + // screen modes 0 and 1 + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + if (BG0) + { + FIXCLIP(0); + DrawBackground (PPU.BGMode, 0, 10, 14); + } + if (BG1) + { + FIXCLIP(1); + DrawBackground (PPU.BGMode, 1, 9, 13); + } + if (BG2) + { + FIXCLIP(2); + DrawBackground (PPU.BGMode, 2, 3, + PPU.BG3Priority ? 17 : 6); + } + if (BG3 && PPU.BGMode == 0) + { + FIXCLIP(3); + DrawBackground (PPU.BGMode, 3, 2, 5); + } + } + else if (PPU.BGMode != 7) + { + // screen modes 2 and up but not mode 7 + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + if (BG0) + { + FIXCLIP(0); + DrawBackground (PPU.BGMode, 0, 5, 13); + } + if (BG1 && PPU.BGMode != 6) + { + FIXCLIP(1); + DrawBackground (PPU.BGMode, 1, 2, 9); + } + } + else + { + // screen mode 7 + DrawBGMode7Background16New (GFX.Screen); + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + } + } + IPPU.PreviousLine = IPPU.CurrentLine; +} + +// -x- + +#ifdef GFX_MULTI_FORMAT + +#define _BUILD_PIXEL(F) \ +uint32 BuildPixel##F(uint32 R, uint32 G, uint32 B) \ +{ \ + return (BUILD_PIXEL_##F(R,G,B)); \ +}\ +uint32 BuildPixel2##F(uint32 R, uint32 G, uint32 B) \ +{ \ + return (BUILD_PIXEL2_##F(R,G,B)); \ +} \ +void DecomposePixel##F(uint32 pixel, uint32 &R, uint32 &G, uint32 &B) \ +{ \ + DECOMPOSE_PIXEL_##F(pixel,R,G,B); \ +} + +_BUILD_PIXEL(RGB565) +_BUILD_PIXEL(RGB555) +_BUILD_PIXEL(BGR565) +_BUILD_PIXEL(BGR555) +_BUILD_PIXEL(GBR565) +_BUILD_PIXEL(GBR555) +_BUILD_PIXEL(RGB5551) + +bool8_32 S9xSetRenderPixelFormat (int format) +{ + extern uint32 current_graphic_format; + + current_graphic_format = format; + + switch (format) + { + case RGB565: + _BUILD_SETUP(RGB565) + return (TRUE); + case RGB555: + _BUILD_SETUP(RGB555) + return (TRUE); + case BGR565: + _BUILD_SETUP(BGR565) + return (TRUE); + case BGR555: + _BUILD_SETUP(BGR555) + return (TRUE); + case GBR565: + _BUILD_SETUP(GBR565) + return (TRUE); + case GBR555: + _BUILD_SETUP(GBR555) + return (TRUE); + case RGB5551: + _BUILD_SETUP(RGB5551) + return (TRUE); + default: + break; + } + return (FALSE); +} +#endif diff --git a/src/gfx16.cpp.old2 b/src/gfx16.cpp.old2 new file mode 100644 index 0000000..5a9fcb8 --- /dev/null +++ b/src/gfx16.cpp.old2 @@ -0,0 +1,3201 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" + +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" +#include "cheats.h" +#include +#include "asmmemfuncs.h" +#include "mode7.h" +#include "rops.h" +#include "tile16.h" +uint32 TileBlank; +// V_FLIP 0x8000 +// H_FLIP 0x4000 +//Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; +// (((Tile & H_FLIP) >> 14) ^ (Quot & 1)) + (((Tile & V_FLIP) >> 11) ^ (16) ^ tx_index) + + +const int tx_table[16] = { +// t1 = 16, t2 = 0 + // FLIP = 0x00 + 16 + 0, // 0x00 + 16 + 1, // 0x01 + + // FLIP = 0x01 + 16 + 1 - 0, // 0x02 + 16 + 1 - 1, // 0x03 + + // FLIP = 0x02 + 0 + 0, // 0x04 + 0 + 1, // 0x05 + + // FLIP = 0x03 + 0 + 1 - 0, // 0x06 + 0 + 1 - 1, // 0x07 + +// t1 = 0, t2 = 16 + // FLIP = 0x00 + 0 + 0, // 0x08 + 0 + 1, // 0x09 + + // FLIP = 0x01 + 0 + 1 - 0, // 0x0A + 0 + 1 - 1, // 0x0B + + // FLIP = 0x02 + 16 + 0, // 0x0C + 16 + 1, // 0x0D + + // FLIP = 0x03 + 16 + 1 - 0, // 0x0E + 16 + 1 - 1 // 0x0F +}; + +#define M7 19 +#define M8 19 + +void ComputeClipWindows (); +static void S9xDisplayFrameRate (); +static void S9xDisplayString (const char *string); + +extern uint8 BitShifts[8][4]; +extern uint8 TileShifts[8][4]; +extern uint8 PaletteShifts[8][4]; +extern uint8 PaletteMasks[8][4]; +extern uint8 Depths[8][4]; +extern uint8 BGSizes [2]; + +extern NormalTileRenderer DrawTilePtr; +extern ClippedTileRenderer DrawClippedTilePtr; +extern NormalTileRenderer DrawHiResTilePtr; +extern ClippedTileRenderer DrawHiResClippedTilePtr; +extern LargePixelRenderer DrawLargePixelPtr; + +extern struct SBG BG; + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; + +extern uint8 Mode7Depths [2]; + +#define ON_MAIN(N) (GFX.r212c & (1 << (N))) + +#define SUB_OR_ADD(N) \ +(GFX.r2131 & (1 << (N))) + +#define ON_SUB(N) \ +((GFX.r2130 & 0x30) != 0x30 && \ + (GFX.r2130 & 2) && \ + (GFX.r212d & (1 << N))) + +#define ANYTHING_ON_SUB \ +((GFX.r2130 & 0x30) != 0x30 && \ + (GFX.r2130 & 2) && \ + (GFX.r212d & 0x1f)) + +#define ADD_OR_SUB_ON_ANYTHING \ +(GFX.r2131 & 0x3f) + +#define BLACK BUILD_PIXEL(0,0,0) + +void DrawNoZTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount); +void DrawTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTile16x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawTile16x2x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); +void DrawClippedTile16x2x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); +void DrawLargePixel16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Add (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawTile16Add (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Add1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawTile16Add1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Sub (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + + +void DrawTile16Sub (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawNoZTile16Sub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + + +void DrawTile16Sub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawTile16FixedSub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount); + +void DrawClippedTile16FixedSub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawLargePixel16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount); + +void DrawHiResClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount); + +void DrawHiResTile16 (uint32 Tile, uint32 Offset, + uint32 StartLine, uint32 LineCount); + +bool8_32 S9xGraphicsInit () +{ + register uint32 PixelOdd = 1; + register uint32 PixelEven = 2; + +#ifdef GFX_MULTI_FORMAT + if (GFX.BuildPixel == NULL) + S9xSetRenderPixelFormat (RGB565); +#endif + + for (uint8 bitshift = 0; bitshift < 4; bitshift++) + { + for (register int i = 0; i < 16; i++) + { + register uint32 h = 0; + register uint32 l = 0; + +#if defined(LSB_FIRST) +// Wiz usa LSB_FIRST + if (i & 8) + h |= PixelOdd; + if (i & 4) + h |= PixelOdd << 8; + if (i & 2) + h |= PixelOdd << 16; + if (i & 1) + h |= PixelOdd << 24; + if (i & 8) + l |= PixelOdd; + if (i & 4) + l |= PixelOdd << 8; + if (i & 2) + l |= PixelOdd << 16; + if (i & 1) + l |= PixelOdd << 24; +#else + if (i & 8) + h |= (PixelOdd << 24); + if (i & 4) + h |= (PixelOdd << 16); + if (i & 2) + h |= (PixelOdd << 8); + if (i & 1) + h |= PixelOdd; + if (i & 8) + l |= (PixelOdd << 24); + if (i & 4) + l |= (PixelOdd << 16); + if (i & 2) + l |= (PixelOdd << 8); + if (i & 1) + l |= PixelOdd; +#endif + + odd_high[bitshift][i] = h; + odd_low[bitshift][i] = l; + h = l = 0; + +#if defined(LSB_FIRST) + if (i & 8) + h |= PixelEven; + if (i & 4) + h |= PixelEven << 8; + if (i & 2) + h |= PixelEven << 16; + if (i & 1) + h |= PixelEven << 24; + if (i & 8) + l |= PixelEven; + if (i & 4) + l |= PixelEven << 8; + if (i & 2) + l |= PixelEven << 16; + if (i & 1) + l |= PixelEven << 24; +#else + if (i & 8) + h |= (PixelEven << 24); + if (i & 4) + h |= (PixelEven << 16); + if (i & 2) + h |= (PixelEven << 8); + if (i & 1) + h |= PixelEven; + if (i & 8) + l |= (PixelEven << 24); + if (i & 4) + l |= (PixelEven << 16); + if (i & 2) + l |= (PixelEven << 8); + if (i & 1) + l |= PixelEven; +#endif + + even_high[bitshift][i] = h; + even_low[bitshift][i] = l; + } + PixelEven <<= 2; + PixelOdd <<= 2; + } + + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; + GFX.DepthDelta = GFX.SubZBuffer - GFX.ZBuffer; + //GFX.InfoStringTimeout = 0; + //GFX.InfoString = NULL; + + PPU.BG_Forced = 0; + IPPU.OBJChanged = TRUE; + + IPPU.DirectColourMapsNeedRebuild = TRUE; + DrawTilePtr = DrawTile16; + DrawClippedTilePtr = DrawClippedTile16; + DrawLargePixelPtr = DrawLargePixel16; + DrawHiResTilePtr= DrawHiResTile16; + DrawHiResClippedTilePtr = DrawHiResClippedTile16; + S9xFixColourBrightness (); + + if (!(GFX.X2 = (uint16 *) malloc (sizeof (uint16) * 0x10000))) + return (FALSE); + + if (!(GFX.ZERO_OR_X2 = (uint16 *) malloc (sizeof (uint16) * 0x10000)) || + !(GFX.ZERO = (uint16 *) malloc (sizeof (uint16) * 0x10000))) + { + if (GFX.ZERO_OR_X2) + { + free ((char *) GFX.ZERO_OR_X2); + GFX.ZERO_OR_X2 = NULL; + } + if (GFX.X2) + { + free ((char *) GFX.X2); + GFX.X2 = NULL; + } + return (FALSE); + } + uint32 r, g, b; + + // Build a lookup table that multiplies a packed RGB value by 2 with + // saturation. + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r << 1; + if (r2 > MAX_RED) + r2 = MAX_RED; + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g << 1; + if (g2 > MAX_GREEN) + g2 = MAX_GREEN; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b << 1; + if (b2 > MAX_BLUE) + b2 = MAX_BLUE; + GFX.X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } + ZeroMemory (GFX.ZERO, 0x10000 * sizeof (uint16)); + ZeroMemory (GFX.ZERO_OR_X2, 0x10000 * sizeof (uint16)); + // Build a lookup table that if the top bit of the color value is zero + // then the value is zero, otherwise multiply the value by 2. Used by + // the color subtraction code. + +#if defined(OLD_COLOUR_BLENDING) + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 = (r2 << 1) & MAX_RED; + + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 = (g2 << 1) & MAX_GREEN; + + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 = (b2 << 1) & MAX_BLUE; + + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } +#else + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 = (r2 << 1) & MAX_RED; + + if (r2 == 0) + r2 = 1; + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 = (g2 << 1) & MAX_GREEN; + + if (g2 == 0) + g2 = 1; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 = (b2 << 1) & MAX_BLUE; + + if (b2 == 0) + b2 = 1; + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO_OR_X2 [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } +#endif + + // Build a lookup table that if the top bit of the color value is zero + // then the value is zero, otherwise its just the value. + for (r = 0; r <= MAX_RED; r++) + { + uint32 r2 = r; + if ((r2 & 0x10) == 0) + r2 = 0; + else + r2 &= ~0x10; + + for (g = 0; g <= MAX_GREEN; g++) + { + uint32 g2 = g; + if ((g2 & GREEN_HI_BIT) == 0) + g2 = 0; + else + g2 &= ~GREEN_HI_BIT; + for (b = 0; b <= MAX_BLUE; b++) + { + uint32 b2 = b; + if ((b2 & 0x10) == 0) + b2 = 0; + else + b2 &= ~0x10; + + GFX.ZERO [BUILD_PIXEL2 (r, g, b)] = BUILD_PIXEL2 (r2, g2, b2); + GFX.ZERO [BUILD_PIXEL2 (r, g, b) & ~ALPHA_BITS_MASK] = BUILD_PIXEL2 (r2, g2, b2); + } + } + } + + return (TRUE); +} + +void S9xGraphicsDeinit (void) +{ + // Free any memory allocated in S9xGraphicsInit + if (GFX.X2) + { + free ((char *) GFX.X2); + GFX.X2 = NULL; + } + if (GFX.ZERO_OR_X2) + { + free ((char *) GFX.ZERO_OR_X2); + GFX.ZERO_OR_X2 = NULL; + } + if (GFX.ZERO) + { + free ((char *) GFX.ZERO); + GFX.ZERO = NULL; + } +} + +void S9xBuildDirectColourMaps () +{ + for (uint32 p = 0; p < 8; p++) + { + for (uint32 c = 0; c < 256; c++) + { +// XXX: Brightness + DirectColourMaps [p][c] = BUILD_PIXEL (((c & 7) << 2) | ((p & 1) << 1), + ((c & 0x38) >> 1) | (p & 2), + ((c & 0xc0) >> 3) | (p & 4)); + } + } + IPPU.DirectColourMapsNeedRebuild = FALSE; +} + +void S9xStartScreenRefresh () +{ + if (IPPU.RenderThisFrame) + { +#ifndef _SNESPPC + if (!S9xInitUpdate ()) + { + IPPU.RenderThisFrame = FALSE; + return; + } +#endif + IPPU.RenderedFramesCount++; + IPPU.PreviousLine = IPPU.CurrentLine = 0; + IPPU.MaxBrightness = PPU.Brightness; + IPPU.LatchedBlanking = PPU.ForcedBlanking; + IPPU.LatchedInterlace = (Memory.FillRAM[0x2133] & 1); + IPPU.RenderedScreenWidth = 256; + IPPU.RenderedScreenHeight = PPU.ScreenHeight; + IPPU.DoubleWidthPixels = FALSE; + + PPU.RecomputeClipWindows = TRUE; + GFX.DepthDelta = GFX.SubZBuffer - GFX.ZBuffer; + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; + + } + if (++IPPU.FrameCount % Memory.ROMFramesPerSecond == 0) + { + IPPU.DisplayedRenderedFrameCount = IPPU.RenderedFramesCount; + IPPU.RenderedFramesCount = 0; + IPPU.FrameCount = 0; + } +} + +void RenderLine (uint8 C) +{ + if (IPPU.RenderThisFrame) + { + + LineData[C].BG[0].VOffset = PPU.BG[0].VOffset + 1; + LineData[C].BG[0].HOffset = PPU.BG[0].HOffset; + LineData[C].BG[1].VOffset = PPU.BG[1].VOffset + 1; + LineData[C].BG[1].HOffset = PPU.BG[1].HOffset; + + if (PPU.BGMode == 7) + { + struct SLineMatrixData *p = &LineMatrixData [C]; + p->MatrixA = PPU.MatrixA; + p->MatrixB = PPU.MatrixB; + p->MatrixC = PPU.MatrixC; + p->MatrixD = PPU.MatrixD; + p->CentreX = PPU.CentreX; + p->CentreY = PPU.CentreY; + } + else + { + if (Settings.StarfoxHack && PPU.BG[2].VOffset == 0 && + PPU.BG[2].HOffset == 0xe000) + { + LineData[C].BG[2].VOffset = 0xe1; + LineData[C].BG[2].HOffset = 0; + } + else + { + LineData[C].BG[2].VOffset = PPU.BG[2].VOffset + 1; + LineData[C].BG[2].HOffset = PPU.BG[2].HOffset; + LineData[C].BG[3].VOffset = PPU.BG[3].VOffset + 1; + LineData[C].BG[3].HOffset = PPU.BG[3].HOffset; + } + + } + IPPU.CurrentLine = C + 1; + } +} + + +void S9xEndScreenRefresh() +{ + IPPU.HDMAStarted = FALSE; + +//RC + if (IPPU.RenderThisFrame) + { + FLUSH_REDRAW (); + //if (IPPU.ColorsChanged) + //{ + IPPU.ColorsChanged = FALSE; + //} + + + S9xDeinitUpdate (IPPU.RenderedScreenWidth, IPPU.RenderedScreenHeight, + 1); + } +#ifndef RC_OPTIMIZED + S9xApplyCheats (); +#endif + + +#ifdef DEBUGGER + if (CPU.Flags & FRAME_ADVANCE_FLAG) + { + if (ICPU.FrameAdvanceCount) + { + ICPU.FrameAdvanceCount--; + IPPU.RenderThisFrame = TRUE; + IPPU.FrameSkip = 0; + } + else + { + CPU.Flags &= ~FRAME_ADVANCE_FLAG; + CPU.Flags |= DEBUG_MODE_FLAG; + } + } +#endif + +/* + if (CPU.SRAMModified) + { + if (!CPU.AutoSaveTimer) + { + if (!(CPU.AutoSaveTimer = Settings.AutoSaveDelay * Memory.ROMFramesPerSecond)) + CPU.SRAMModified = FALSE; + } + else + { + if (!--CPU.AutoSaveTimer) + { + S9xAutoSaveSRAM (); + CPU.SRAMModified = FALSE; + } + } + } +*/ +} + +void S9xSetInfoString (const char *string) +{ + } + + + +int TileRenderer; +TileRendererSet TileRenderers[] = { + {DrawTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 0 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 1 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedAdd1_2, DrawClippedTile16FixedAdd1_2, DrawLargePixel16Add1_2}, // 2 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawTile16Add1_2, DrawClippedTile16Add1_2, DrawLargePixel16Add1_2}, // 3 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 4 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 5 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedSub1_2, DrawClippedTile16FixedSub1_2, DrawLargePixel16Sub1_2}, // 6 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawTile16Sub1_2, DrawClippedTile16Sub1_2, DrawLargePixel16Sub1_2}, // 7 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawTile16, DrawClippedTile16, DrawLargePixel16} // 8 -> normal + }; +TileRendererSet TileRenderersNoZ[] = { + {DrawNoZTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 0 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawNoZTile16Add, DrawClippedTile16Add, DrawLargePixel16Add}, // 1 -> GFX.r2131:7 = 0, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedAdd1_2, DrawClippedTile16FixedAdd1_2, DrawLargePixel16Add1_2}, // 2 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawNoZTile16Add1_2, DrawClippedTile16Add1_2, DrawLargePixel16Add1_2}, // 3 -> GFX.r2131:7 = 0, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawNoZTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 4 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 0 + {DrawNoZTile16Sub, DrawClippedTile16Sub, DrawLargePixel16Sub}, // 5 -> GFX.r2131:7 = 1, GFX.r2131:6 = 0, GFX.r2130:1 = 1 + {DrawTile16FixedSub1_2, DrawClippedTile16FixedSub1_2, DrawLargePixel16Sub1_2}, // 6 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 0 + {DrawNoZTile16Sub1_2, DrawClippedTile16Sub1_2, DrawLargePixel16Sub1_2}, // 7 -> GFX.r2131:7 = 1, GFX.r2131:6 = 1, GFX.r2130:1 = 1 + {DrawNoZTile16, DrawClippedTile16, DrawLargePixel16} // 8 -> normal + }; +INLINE void SelectTileRenderer (bool8_32 normal, bool NoZ = false) +{ + if (normal) { + TileRenderer = 8; + } + else { + TileRenderer = (((GFX.r2131 >> 5) & 0x06) | ((GFX.r2130 >> 1) & 1)); + } + +#ifdef __DEBUG__ + char *TRName[] = { + "Add", "Add", "FixedAdd1_2", "Add1_2", + "Sub", "Sub", "FixedSub1_2", "Sub1_2", + "Normal" + }; + printf("SelectTileRenderer: %s\n", TRName[TileRenderer]); +#endif + + if (NoZ) { + DrawTilePtr = TileRenderersNoZ[TileRenderer].Normal; + DrawClippedTilePtr = TileRenderersNoZ[TileRenderer].Clipped; + DrawLargePixelPtr = TileRenderersNoZ[TileRenderer].Large; + } + else { + DrawTilePtr = TileRenderers[TileRenderer].Normal; + DrawClippedTilePtr = TileRenderers[TileRenderer].Clipped; + DrawLargePixelPtr = TileRenderers[TileRenderer].Large; + } +} + +void S9xSetupOBJ () +{ + int SmallSize; + int LargeSize; + + switch (PPU.OBJSizeSelect) + { + case 0: + SmallSize = 8; + LargeSize = 16; + break; + case 1: + SmallSize = 8; + LargeSize = 32; + break; + case 2: + SmallSize = 8; + LargeSize = 64; + break; + case 3: + SmallSize = 16; + LargeSize = 32; + break; + case 4: + SmallSize = 16; + LargeSize = 64; + break; + case 5: + default: + SmallSize = 32; + LargeSize = 64; + break; + } + + int C = 0; + + int FirstSprite = PPU.FirstSprite & 0x7f; + int S = FirstSprite; + do + { + int Size; + if (PPU.OBJ [S].Size) + Size = LargeSize; + else + Size = SmallSize; + + long VPos = PPU.OBJ [S].VPos; + + if (VPos >= PPU.ScreenHeight) + VPos -= 256; + if (PPU.OBJ [S].HPos < 256 && PPU.OBJ [S].HPos > -Size && + VPos < PPU.ScreenHeight && VPos > -Size) + { + int x = 0; + int a, b; + //GFX.OBJList[C++] = S; + // -- Sort objects (from low to high priority) + + while (x < C) { + a = GFX.OBJList[x]; + if (PPU.OBJ[a].Priority >= PPU.OBJ[S].Priority) break; + x++; + } + + GFX.OBJList[x] = S; + x++; C++; + + while (x < C) { + b = GFX.OBJList[x]; + GFX.OBJList[x] = a; + a = b; + x++; + } + // -- + GFX.Sizes[S] = Size; + GFX.VPositions[S] = VPos; + } + S = (S + 1) & 0x7f; + } while (S != FirstSprite); + + // Terminate the list + GFX.OBJList [C] = -1; + IPPU.OBJChanged = FALSE; +} + +void DrawOBJS (bool8_32 OnMain = FALSE, uint8 D = 0) +{ + int bg_ta_ns; + int bg_ta; + uint32 O; + uint32 BaseTile, Tile; + + CHECK_SOUND(); + + BG.BitShift = 4; + SelectConvertTile(); + BG.TileShift = 5; + //BG.TileAddress = PPU.OBJNameBase; + BG.StartPalette = 128; + BG.PaletteShift = 4; + BG.PaletteMask = 7; + BG.Buffer = IPPU.TileCache [TILE_4BIT]; + BG.Buffered = IPPU.TileCached [TILE_4BIT]; + //BG.NameSelect = PPU.OBJNameSelect; + BG.DirectColourMode = FALSE; + + SelectPalette(); + bg_ta = PPU.OBJNameBase; + bg_ta_ns = bg_ta + PPU.OBJNameSelect; + + GFX.Z1 = D + 2; + + int I = 0; + for (int S = GFX.OBJList [I++]; S >= 0; S = GFX.OBJList [I++]) + { + int VPos = GFX.VPositions [S]; + int Size = GFX.Sizes[S]; + int TileInc = 1; + int Offset; + + if (VPos + Size <= (int) GFX.StartY || VPos > (int) GFX.EndY) + continue; + + if (OnMain && SUB_OR_ADD(4)) + { + SelectTileRenderer (!GFX.Pseudo && PPU.OBJ [S].Palette < 4, true); + } + + BaseTile = PPU.OBJ[S].Name | (PPU.OBJ[S].Palette << 10); + + if (PPU.OBJ[S].HFlip) + { + BaseTile += ((Size >> 3) - 1) | H_FLIP; + TileInc = -1; + } + + if (PPU.OBJ[S].VFlip) BaseTile |= V_FLIP; + //BaseTile |= PPU.OBJ[S].VFlip << 15; + + int clipcount = GFX.pCurrentClip->Count [4]; + if (!clipcount) clipcount = 1; + + GFX.Z2 = (PPU.OBJ[S].Priority + 1) * 4 + D; + + for (int clip = 0; clip < clipcount; clip++) + { + int Left; + int Right; + if (!GFX.pCurrentClip->Count [4]) + { + Left = 0; + Right = 256; + } + else + { + Left = GFX.pCurrentClip->Left [clip][4]; + Right = GFX.pCurrentClip->Right [clip][4]; + } + + if (Right <= Left || PPU.OBJ[S].HPos + Size <= Left || + PPU.OBJ[S].HPos >= Right) + continue; + + for (int Y = 0; Y < Size; Y += 8) + { + if (VPos + Y + 7 >= (int) GFX.StartY && VPos + Y <= (int) GFX.EndY) + { + int StartLine; + int TileLine; + int LineCount; + int Last; + + if ((StartLine = VPos + Y) < (int) GFX.StartY) + { + StartLine = GFX.StartY - StartLine; + LineCount = 8 - StartLine; + } + else + { + StartLine = 0; + LineCount = 8; + } + if ((Last = VPos + Y + 7 - GFX.EndY) > 0) + if ((LineCount -= Last) <= 0) + break; + + TileLine = StartLine << 3; + + //-NoZ----- + //CheckNoZ(VPos + Y + StartLine, LineCount); + //-NoZ----- + + O = (VPos + Y + StartLine) * GFX_PPL; + if (!PPU.OBJ[S].VFlip) Tile = BaseTile + (Y << 1); + else Tile = BaseTile + ((Size - Y - 8) << 1); + + if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + else BG.TileAddress = bg_ta; + + int Middle = Size >> 3; + if (PPU.OBJ[S].HPos < Left) + { + Tile += ((Left - PPU.OBJ[S].HPos) >> 3) * TileInc; + Middle -= (Left - PPU.OBJ[S].HPos) >> 3; + O += Left * GFX_PIXSIZE; + if ((Offset = (Left - PPU.OBJ[S].HPos) & 7)) + { + O -= Offset * GFX_PIXSIZE; + int W = 8 - Offset; + int Width = Right - Left; + if (W > Width) W = Width; + //if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + //else BG.TileAddress = bg_ta; + (*DrawClippedTilePtr) (Tile, O, Offset, W, TileLine, LineCount); + + if (W >= Width) + continue; + Tile += TileInc; + Middle--; + O += 8 * GFX_PIXSIZE; + } + } + else + O += PPU.OBJ[S].HPos * GFX_PIXSIZE; + + if (PPU.OBJ[S].HPos + Size >= Right) + { + Middle -= ((PPU.OBJ[S].HPos + Size + 7) - + Right) >> 3; + Offset = (Right - (PPU.OBJ[S].HPos + Size)) & 7; + } + else + Offset = 0; + + for (int X = 0; X < Middle; X++, O += 8 * GFX_PIXSIZE, + Tile += TileInc) + { + //if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + //else BG.TileAddress = bg_ta; + (*DrawTilePtr) (Tile, O, TileLine, LineCount); + } + if (Offset) + { + //if (Tile & 0x100) BG.TileAddress = bg_ta_ns; + //else BG.TileAddress = bg_ta; + (*DrawClippedTilePtr) (Tile, O, 0, Offset, TileLine, LineCount); + } + } + } + } + } +} +void DrawBackgroundMosaic (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackgroundMosaic(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + CHECK_SOUND(); + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint8 depths [2] = {Z1, Z2}; + + if (BGMode == 0) + BG.StartPalette = bg << 5; + else + BG.StartPalette = 0; + SelectPalette(); + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(((uint8*)SC1-Memory.VRAM)>=0x10000) + SC1-=0x08000; + + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + uint32 Lines; + uint32 OffsetMask; + uint32 OffsetShift; + + if (BG.TileSize == 16) + { + OffsetMask = 0x3ff; + OffsetShift = 4; + } + else + { + OffsetMask = 0x1ff; + OffsetShift = 3; + } + + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines) + { + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + uint32 MosaicOffset = Y % PPU.Mosaic; + + for (Lines = 1; Lines < PPU.Mosaic - MosaicOffset; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + uint32 MosaicLine = VOffset + Y - MosaicOffset; + + if (Y + Lines > GFX.EndY) + Lines = GFX.EndY + 1 - Y; + uint32 VirtAlign = (MosaicLine & 7) << 3; + + uint16 *b1; + uint16 *b2; + + uint32 ScreenLine = MosaicLine >> OffsetShift; + uint32 Rem16 = MosaicLine & 15; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + uint16 *t; + uint32 Left = 0; + uint32 Right = 256; + + uint32 ClipCount = GFX.pCurrentClip->Count [bg]; + uint32 HPos = HOffset; + uint32 PixWidth = PPU.Mosaic; + + if (!ClipCount) + ClipCount = 1; + + for (uint32 clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [bg]) + { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + uint32 r = Left % PPU.Mosaic; + HPos = HOffset + Left; + PixWidth = PPU.Mosaic - r; + } + uint32 s = Y * GFX_PPL + Left * GFX_PIXSIZE; + for (uint32 x = Left; x < Right; x += PixWidth, + s += PixWidth * GFX_PIXSIZE, + HPos += PixWidth, PixWidth = PPU.Mosaic) + { + uint32 Quot = (HPos & OffsetMask) >> 3; + + if (x + PixWidth >= Right) + PixWidth = Right - x; + + if (BG.TileSize == 8) + { + if (Quot > 31) + t = b2 + (Quot & 0x1f); + else + t = b1 + Quot; + } + else + { + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + } + + Tile = READ_2BYTES (t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + // Draw tile... + if (BG.TileSize != 8) + { + if (Tile & H_FLIP) + { + // Horizontal flip, but what about vertical flip ? + if (Tile & V_FLIP) + { + // Both horzontal & vertical flip + if (Rem16 < 8) + { + (*DrawLargePixelPtr) (Tile + 17 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + 1 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + else + { + // Horizontal flip only + if (Rem16 > 7) + { + (*DrawLargePixelPtr) (Tile + 17 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + 1 - (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } + else + { + // No horizontal flip, but is there a vertical flip ? + if (Tile & V_FLIP) + { + // Vertical flip only + if (Rem16 < 8) + { + (*DrawLargePixelPtr) (Tile + 16 + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + else + { + // Normal unflipped + if (Rem16 > 7) + { + (*DrawLargePixelPtr) (Tile + 16 + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + else + { + (*DrawLargePixelPtr) (Tile + (Quot & 1), s, + HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } + } + else + (*DrawLargePixelPtr) (Tile, s, HPos & 7, PixWidth, + VirtAlign, Lines); + } + } + } +} + +void DrawBackgroundOffset (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackgroundOffse(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + + CHECK_SOUND(); + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint16 *BPS0; + uint16 *BPS1; + uint16 *BPS2; + uint16 *BPS3; + uint32 Width; + int VOffsetOffset = BGMode == 4 ? 0 : 32; + uint8 depths [2] = {Z1, Z2}; + + BG.StartPalette = 0; + SelectPalette(); + + BPS0 = (uint16 *) &Memory.VRAM[PPU.BG[2].SCBase << 1]; + + if (PPU.BG[2].SCSize & 1) + BPS1 = BPS0 + 1024; + else + BPS1 = BPS0; + + if (PPU.BG[2].SCSize & 2) + BPS2 = BPS1 + 1024; + else + BPS2 = BPS0; + + if (PPU.BG[2].SCSize & 1) + BPS3 = BPS2 + 1024; + else + BPS3 = BPS2; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if (PPU.BG[bg].SCSize & 1) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if(((uint8*)SC1-Memory.VRAM)>=0x10000) + SC1-=0x08000; + + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + + if (PPU.BG[bg].SCSize & 1) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + + static const int Lines = 1; + int OffsetMask; + int OffsetShift; + int OffsetEnableMask = 1 << (bg + 13); + + if (BG.TileSize == 16) + { + OffsetMask = 0x3ff; + OffsetShift = 4; + } + else + { + OffsetMask = 0x1ff; + OffsetShift = 3; + } + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y++) + { + uint32 VOff = LineData [Y].BG[2].VOffset - 1; + uint32 HOff = LineData [Y].BG[2].HOffset; + int VirtAlign; + int ScreenLine = VOff >> 3; + uint16 *s0; + uint16 *s1; + uint16 *s2; + + if (ScreenLine & 0x20) + s1 = BPS2, s2 = BPS3; + else + s1 = BPS0, s2 = BPS1; + + s1 += (ScreenLine & 0x1f) << 5; + s2 += (ScreenLine & 0x1f) << 5; + + if(BGMode != 4) + { + if((ScreenLine & 0x1f) == 0x1f) + { + if(ScreenLine & 0x20) + VOffsetOffset = BPS0 - BPS2 - 0x1f*32; + else + VOffsetOffset = BPS2 - BPS0 - 0x1f*32; + } + else + { + VOffsetOffset = 32; + } + } + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + + for (int clip = 0; clip < clipcount; clip++) + { + uint32 Left; + uint32 Right; + + if (!GFX.pCurrentClip->Count [bg]) + { + Left = 0; + Right = 256; + } + else + { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) + continue; + } + + uint32 VOffset; + uint32 HOffset; + uint32 LineHOffset=LineData [Y].BG[bg].HOffset; + uint32 Offset; + uint32 HPos; + uint32 Quot; + uint32 Count; + uint16 *t; + uint32 Quot2; + uint32 VCellOffset; + uint32 HCellOffset; + uint16 *b1; + uint16 *b2; + uint32 TotalCount = 0; + uint32 MaxCount = 8; + + uint32 s = Left * GFX_PIXSIZE + Y * GFX_PPL; + bool8_32 left_hand_edge = (Left == 0); + Width = Right - Left; + + if (Left & 7) + MaxCount = 8 - (Left & 7); + + while (Left < Right) + { + if (left_hand_edge) + { + // The SNES offset-per-tile background mode has a + // hardware limitation that the offsets cannot be set + // for the tile at the left-hand edge of the screen. + VOffset = LineData [Y].BG[bg].VOffset; + HOffset = LineHOffset; + left_hand_edge = FALSE; + } + else + { + // All subsequent offset tile data is shifted left by one, + // hence the - 1 below. + Quot2 = ((HOff + Left - 1) & OffsetMask) >> 3; + + if (Quot2 > 31) + s0 = s2 + (Quot2 & 0x1f); + else + s0 = s1 + Quot2; + + HCellOffset = READ_2BYTES (s0); + + if (BGMode == 4) + { + VOffset = LineData [Y].BG[bg].VOffset; + HOffset=LineHOffset; + if ((HCellOffset & OffsetEnableMask)) + { + if (HCellOffset & 0x8000) + VOffset = HCellOffset + 1; + else + HOffset = HCellOffset; + } + } + else + { + VCellOffset = READ_2BYTES (s0 + VOffsetOffset); + if ((VCellOffset & OffsetEnableMask)) + VOffset = VCellOffset + 1; + else + VOffset = LineData [Y].BG[bg].VOffset; + + if ((HCellOffset & OffsetEnableMask)) + HOffset = (HCellOffset & ~7)|(LineHOffset&7); + else + HOffset=LineHOffset; + } + } + VirtAlign = ((Y + VOffset) & 7) << 3; + ScreenLine = (VOffset + Y) >> OffsetShift; + + int tx_index; + tx_index = ( ((VOffset + Y) & 15) <= 7 ) << 3; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + HPos = (HOffset + Left) & OffsetMask; + + Quot = HPos >> 3; + + if (BG.TileSize == 8) + { + if (Quot > 31) + t = b2 + (Quot & 0x1f); + else + t = b1 + Quot; + } + else + { + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + } + + if (MaxCount + TotalCount > Width) + MaxCount = Width - TotalCount; + + Offset = HPos & 7; + + Count = 8 - Offset; + if (Count > MaxCount) + Count = MaxCount; + + s -= Offset * GFX_PIXSIZE; + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + if (Tile != TileBlank) + if (BG.TileSize == 8) + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + else + { + Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + } + + Left += Count; + TotalCount += Count; + s += (Offset + Count) * GFX_PIXSIZE; + MaxCount = 8; + } + } + } +} + +void DrawBackgroundMode5 (uint32 /* BGMODE */, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackgroundMode5(?, %i, %i, %i)\n", bg, Z1, Z2); +#endif + + CHECK_SOUND(); + + uint8 depths [2] = {Z1, Z2}; + + uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 Width; + + BG.StartPalette = 0; + SelectPalette(); + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + if ((PPU.BG[bg].SCSize & 1)) + SC1 = SC0 + 1024; + else + SC1 = SC0; + + if((SC1-(unsigned short*)Memory.VRAM)>0x10000) + SC1=(uint16*)&Memory.VRAM[(((uint8*)SC1)-Memory.VRAM)%0x10000]; + + if ((PPU.BG[bg].SCSize & 2)) + SC2 = SC1 + 1024; + else SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) + SC2-=0x08000; + + if ((PPU.BG[bg].SCSize & 1)) + SC3 = SC2 + 1024; + else + SC3 = SC2; + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) + SC3-=0x08000; + int Lines; + int VOffsetMask; + int VOffsetShift; + + if (BG.TileSize == 16) + { + VOffsetMask = 0x3ff; + VOffsetShift = 4; + } + else + { + VOffsetMask = 0x1ff; + VOffsetShift = 3; + } + int endy = GFX.EndY; + + for (int Y = GFX.StartY; Y <= endy; Y += Lines) + { + //int y = Y; + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + for (Lines = 1; Lines < 8 - VirtAlign; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + HOffset <<= 1; + if (Y + Lines > endy) + Lines = endy + 1 - Y; + + int ScreenLine = (VOffset + Y) >> VOffsetShift; + int t1; + int t2; + if (((VOffset + Y) & 15) > 7) + { + t1 = 16; + t2 = 0; + } + else + { + t1 = 0; + t2 = 16; + } + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) + clipcount = 1; + for (int clip = 0; clip < clipcount; clip++) + { + int Left; + int Right; + + if (!GFX.pCurrentClip->Count [bg]) + { + Left = 0; + Right = 512; + } + else + { + Left = GFX.pCurrentClip->Left [clip][bg] * 2; + Right = GFX.pCurrentClip->Right [clip][bg] * 2; + + if (Right <= Left) + continue; + } + + uint32 s = (Left>>1) * GFX_PIXSIZE + Y * GFX_PPL; + uint32 HPos = (HOffset + Left * GFX_PIXSIZE) & 0x3ff; + + uint32 Quot = HPos >> 3; + uint32 Count = 0; + + uint16 *t; + if (Quot > 63) + t = b2 + ((Quot >> 1) & 0x1f); + else + t = b1 + (Quot >> 1); + + Width = Right - Left; + // Left hand edge clipped tile + if (HPos & 7) + { + int Offset = (HPos & 7); + Count = 8 - Offset; + if (Count > Width) + Count = Width; + s -= (Offset>>1); + Tile = READ_2BYTES (t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResClippedTilePtr) (Tile + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + t1 + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResClippedTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResClippedTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResClippedTilePtr) (Tile + t2 + (Quot & 1), + s, Offset, Count, VirtAlign, Lines); + } + } + + t += Quot & 1; + if (Quot == 63) + t = b2; + else if (Quot == 127) + t = b1; + Quot++; + s += 4; + } + + // Middle, unclipped tiles + Count = Width - Count; + int Middle = Count >> 3; + Count &= 7; + for (int C = Middle; C > 0; s += 4, Quot++, C--) + { + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResTilePtr) (Tile + (Quot & 1), + s, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResTilePtr) (Tile + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResTilePtr) (Tile + t1 + (Quot & 1), + s, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResTilePtr) (Tile + t2 + (Quot & 1), + s, VirtAlign, Lines); + } + } + + t += Quot & 1; + if (Quot == 63) + t = b2; + else + if (Quot == 127) + t = b1; + } + + // Right-hand edge clipped tiles + if (Count) + { + Tile = READ_2BYTES(t); + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + if (BG.TileSize == 8) + { + if (!(Tile & H_FLIP)) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + { + // H flip + (*DrawHiResClippedTilePtr) (Tile + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + else + { + if (!(Tile & (V_FLIP | H_FLIP))) + { + // Normal, unflipped + (*DrawHiResClippedTilePtr) (Tile + t1 + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + if (Tile & H_FLIP) + { + if (Tile & V_FLIP) + { + // H & V flip + (*DrawHiResClippedTilePtr) (Tile + t2 + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + else + { + // H flip only + (*DrawHiResClippedTilePtr) (Tile + t1 + 1 - (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + else + { + // V flip only + (*DrawHiResClippedTilePtr) (Tile + t2 + (Quot & 1), + s, 0, Count, VirtAlign, Lines); + } + } + } + } + } +} + +void DrawBackground_8 (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackground_8(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + //uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 depths [2] = {Z1, Z2}; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + SC1 = (uint16 *) &Memory.VRAM[((PPU.BG[bg].SCBase << 1) + ((PPU.BG[bg].SCSize & 1) << 10)) & 0xffff]; + //SC1 = SC0 + ((PPU.BG[bg].SCSize & 1) << 10); + + //if(SC1 >= (unsigned short*)(Memory.VRAM+0x10000)) SC1 = (uint16*)&Memory.VRAM[((uint8*)SC1-&Memory.VRAM[0]) & 0xffff]; + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) SC2 -= 0x08000; + + SC3 = SC2 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) SC3 -= 0x08000; + + int Lines; + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines){ + int y_ppl = Y * GFX_PPL; + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + int maxLines = GFX.EndY - Y + 1; + if ((8 - VirtAlign) < maxLines) maxLines = (8 - VirtAlign); + + for (Lines = 1; Lines < maxLines; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + + VirtAlign <<= 3; + + uint32 ScreenLine = (VOffset + Y) >> 3; + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + uint32 Left; + uint32 Right; + int clip = 0; + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) { + Left = 0; + Right = 256; + } + + do { + if (clipcount) { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) {clip++; continue;} + } + + uint32 s = Left + y_ppl; + uint32 HPos = (HOffset + Left) & 0x1ff; + uint32 Quot = HPos >> 3; + uint32 Count = 0; + uint16 *t; + uint16 *b; + + if (Quot > 31) { + t = b2 + (Quot & 0x1f); + b = b1; + Quot -= 32; + } + else { + t = b1 + Quot; + b = b2; + } + + uint32 Width = Right - Left; + + // Left hand edge clipped tile + uint32 Offset = (HPos & 7); + if (Offset){ + Count = 8 - Offset; + if (Count > Width) Count = Width; + s -= Offset; + //Tile = READ_2BYTES(t); + register uint32 Tile = *(t++); + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + //t++; + if (Quot == 31) t = b; + //else if (Quot == 63) t = b1; + Quot++; + s += 8; + } + + // Middle, unclipped tiles + Count = Width - Count; + for (int C = Count >> 3; C > 0; s += 8, Quot++, C--){ + //Tile = READ_2BYTES(t); + register uint32 Tile = *(t++); + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawTilePtr) (Tile, s, VirtAlign, Lines); + } + + //t++; + if (Quot == 31) t = b; + //else if (Quot == 63) t = b1; + } + + // Right-hand edge clipped tiles + if (Count & 7){ + //Tile = READ_2BYTES(t); + register uint32 Tile = *t; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, 0, Count & 7, VirtAlign, Lines); + } + } + clip ++; + } while (clip < clipcount); + } +} + +void DrawBackground_16 (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +#ifdef __DEBUG__ + printf("DrawBackground_16(%i, %i, %i, %i)\n", BGMode, bg, Z1, Z2); +#endif + //uint32 Tile; + uint16 *SC0; + uint16 *SC1; + uint16 *SC2; + uint16 *SC3; + uint32 depths [2] = {Z1, Z2}; + + SC0 = (uint16 *) &Memory.VRAM[PPU.BG[bg].SCBase << 1]; + + SC1 = (uint16 *) &Memory.VRAM[((PPU.BG[bg].SCBase << 1) + ((PPU.BG[bg].SCSize & 1) << 10)) & 0xffff]; + //SC1 = SC0 + ((PPU.BG[bg].SCSize & 1) << 10); + + //if(SC1 >= (unsigned short*)(Memory.VRAM+0x10000)) SC1 = (uint16*)&Memory.VRAM[((uint8*)SC1-&Memory.VRAM[0]) & 0xffff]; + + if (PPU.BG[bg].SCSize & 2) + SC2 = SC1 + 1024; + else + SC2 = SC0; + + if(((uint8*)SC2-Memory.VRAM)>=0x10000) SC2 -= 0x08000; + + SC3 = SC2 + ((PPU.BG[bg].SCSize & 1) << 10); + + if(((uint8*)SC3-Memory.VRAM)>=0x10000) SC3 -= 0x08000; + + int Lines; + + TileBlank = 0xFFFFFFFF; + for (uint32 Y = GFX.StartY; Y <= GFX.EndY; Y += Lines){ + int y_ppl = Y * GFX_PPL; + uint32 VOffset = LineData [Y].BG[bg].VOffset; + uint32 HOffset = LineData [Y].BG[bg].HOffset; + int VirtAlign = (Y + VOffset) & 7; + + int maxLines = GFX.EndY - Y + 1; + if ((8 - VirtAlign) < maxLines) maxLines = (8 - VirtAlign); + + for (Lines = 1; Lines < maxLines; Lines++) + if ((VOffset != LineData [Y + Lines].BG[bg].VOffset) || + (HOffset != LineData [Y + Lines].BG[bg].HOffset)) + break; + + + VirtAlign <<= 3; + + uint32 ScreenLine = (VOffset + Y) >> 4; + //int tx_index = ( ((VOffset + Y) & 15) <= 7 ) << 3; + int tx_index = ((((VOffset + Y) & 15) <= 7 ) << 4) ^ (16); + uint16 *b1; + uint16 *b2; + + if (ScreenLine & 0x20) + b1 = SC2, b2 = SC3; + else + b1 = SC0, b2 = SC1; + + b1 += (ScreenLine & 0x1f) << 5; + b2 += (ScreenLine & 0x1f) << 5; + + uint32 Left; + uint32 Right; + int clip = 0; + int clipcount = GFX.pCurrentClip->Count [bg]; + if (!clipcount) { + Left = 0; + Right = 256; + } + + do { + if (clipcount) { + Left = GFX.pCurrentClip->Left [clip][bg]; + Right = GFX.pCurrentClip->Right [clip][bg]; + + if (Right <= Left) {clip++; continue;} + } + + uint32 s = Left + y_ppl; + uint32 HPos = (HOffset + Left) & 0x3ff; + uint32 Quot = HPos >> 3; + uint32 Count = 0; + uint16 *t; + uint16 *b; + + if (Quot > 63) { + t = b2 + ((Quot >> 1) & 0x1f); + b = b1; + Quot -= 64; + } + else { + t = b1 + (Quot >> 1); + b = b2; + } + + + uint32 Width = Right - Left; + + // Left hand edge clipped tile + uint32 Offset = (HPos & 7); + if (Offset){ + Count = 8 - Offset; + if (Count > Width) Count = Width; + s -= Offset; + //Tile = READ_2BYTES(t); + uint32 Tile = *(t); + t += Quot & 1; + Tile += (((Tile & H_FLIP) >> 14) ^ (Quot & 1)) + (((Tile & V_FLIP) >> 11) ^ tx_index); + //Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, Offset, Count, VirtAlign, Lines); + } + //t++; + if (Quot == 63) t = b; + Quot++; + s += 8; + } + + + // Middle, unclipped tiles + Count = Width - Count; + for (int C = Count >> 3; C > 0; s += 8, Quot++, C--){ + //Tile = READ_2BYTES(t); + uint32 Tile = *(t); + t += Quot & 1; + Tile += (((Tile & H_FLIP) >> 14) ^ (Quot & 1)) + (((Tile & V_FLIP) >> 11) ^ tx_index); + //Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawTilePtr) (Tile, s, VirtAlign, Lines); + } + + //t++; + if (Quot == 63) t = b; + } + + // Right-hand edge clipped tiles + if (Count & 7){ + //Tile = READ_2BYTES(t); + uint32 Tile = *(t); + Tile += (((Tile & H_FLIP) >> 14) ^ (Quot & 1)) + (((Tile & V_FLIP) >> 11) ^ tx_index); + //Tile += tx_table[tx_index + ((Tile & (H_FLIP | V_FLIP)) >> 13) + (Quot & 1)]; + if (Tile != TileBlank){ + GFX.Z1 = GFX.Z2 = depths [(Tile & 0x2000) >> 13]; + (*DrawClippedTilePtr) (Tile, s, 0, Count & 7, VirtAlign, Lines); + } + } + clip ++; + } while (clip < clipcount); + } +} + +inline void DrawBackground (uint32 BGMode, uint32 bg, uint8 Z1, uint8 Z2) +{ +//StartAnalyze(); + + BG.TileSize = BGSizes [PPU.BG[bg].BGSize]; + BG.BitShift = BitShifts[BGMode][bg]; + SelectConvertTile(); + BG.TileShift = TileShifts[BGMode][bg]; + BG.TileAddress = PPU.BG[bg].NameBase << 1; + BG.NameSelect = 0; + BG.Buffer = IPPU.TileCache [Depths [BGMode][bg]]; + BG.Buffered = IPPU.TileCached [Depths [BGMode][bg]]; + BG.PaletteShift = PaletteShifts[BGMode][bg]; + BG.PaletteMask = PaletteMasks[BGMode][bg]; + BG.DirectColourMode = (BGMode == 3 || BGMode == 4) && bg == 0 && (GFX.r2130 & 1); + + if (IPPU.DirectColourMapsNeedRebuild && BG.DirectColourMode) S9xBuildDirectColourMaps (); + + if (PPU.BGMosaic [bg] && PPU.Mosaic > 1){ + DrawBackgroundMosaic (BGMode, bg, Z1, Z2); + return; + + } + switch (BGMode) + { + case 2: + case 4: // Used by Puzzle Bobble + DrawBackgroundOffset (BGMode, bg, Z1, Z2); + break; + + case 5: + case 6: // XXX: is also offset per tile. + DrawBackgroundMode5 (BGMode, bg, Z1, Z2); + break; + case 0: + case 1: + case 3: + CHECK_SOUND(); + + if (BGMode == 0) BG.StartPalette = bg << 5; + else BG.StartPalette = 0; + SelectPalette(); + + if (BG.TileSize == 8) DrawBackground_8 (BGMode, bg, Z1, Z2); + else DrawBackground_16 (BGMode, bg, Z1, Z2); + break; + } +} + +#define _BUILD_SETUP(F) \ +GFX.BuildPixel = BuildPixel##F; \ +GFX.BuildPixel2 = BuildPixel2##F; \ +GFX.DecomposePixel = DecomposePixel##F; \ +RED_LOW_BIT_MASK = RED_LOW_BIT_MASK_##F; \ +GREEN_LOW_BIT_MASK = GREEN_LOW_BIT_MASK_##F; \ +BLUE_LOW_BIT_MASK = BLUE_LOW_BIT_MASK_##F; \ +RED_HI_BIT_MASK = RED_HI_BIT_MASK_##F; \ +GREEN_HI_BIT_MASK = GREEN_HI_BIT_MASK_##F; \ +BLUE_HI_BIT_MASK = BLUE_HI_BIT_MASK_##F; \ +MAX_RED = MAX_RED_##F; \ +MAX_GREEN = MAX_GREEN_##F; \ +MAX_BLUE = MAX_BLUE_##F; \ +GREEN_HI_BIT = ((MAX_GREEN_##F + 1) >> 1); \ +SPARE_RGB_BIT_MASK = SPARE_RGB_BIT_MASK_##F; \ +RGB_LOW_BITS_MASK = (RED_LOW_BIT_MASK_##F | \ + GREEN_LOW_BIT_MASK_##F | \ + BLUE_LOW_BIT_MASK_##F); \ +RGB_HI_BITS_MASK = (RED_HI_BIT_MASK_##F | \ + GREEN_HI_BIT_MASK_##F | \ + BLUE_HI_BIT_MASK_##F); \ +RGB_HI_BITS_MASKx2 = ((RED_HI_BIT_MASK_##F | \ + GREEN_HI_BIT_MASK_##F | \ + BLUE_HI_BIT_MASK_##F) << 1); \ +RGB_REMOVE_LOW_BITS_MASK = ~RGB_LOW_BITS_MASK; \ +FIRST_COLOR_MASK = FIRST_COLOR_MASK_##F; \ +SECOND_COLOR_MASK = SECOND_COLOR_MASK_##F; \ +THIRD_COLOR_MASK = THIRD_COLOR_MASK_##F; \ +ALPHA_BITS_MASK = ALPHA_BITS_MASK_##F; \ +FIRST_THIRD_COLOR_MASK = FIRST_COLOR_MASK | THIRD_COLOR_MASK; \ +TWO_LOW_BITS_MASK = RGB_LOW_BITS_MASK | (RGB_LOW_BITS_MASK << 1); \ +HIGH_BITS_SHIFTED_TWO_MASK = (( (FIRST_COLOR_MASK | SECOND_COLOR_MASK | THIRD_COLOR_MASK) & \ + ~TWO_LOW_BITS_MASK ) >> 2); + +void RenderScreen (uint8 *Screen, bool8_32 sub, bool8_32 force_no_add, uint8 D) +{ + bool8_32 BG0; + bool8_32 BG1; + bool8_32 BG2; + bool8_32 BG3; + bool8_32 OB; + + GFX.S = Screen; + + if (!sub) + { + GFX.pCurrentClip = &IPPU.Clip [0]; + BG0 = ON_MAIN (0) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + BG1 = ON_MAIN (1) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + BG2 = ON_MAIN (2) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + BG3 = ON_MAIN (3) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + OB = ON_MAIN (4) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + } + else + { + GFX.pCurrentClip = &IPPU.Clip [1]; + BG0 = ON_SUB (0) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + BG1 = ON_SUB (1) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + BG2 = ON_SUB (2) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + BG3 = ON_SUB (3) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + OB = ON_SUB (4) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + } + +#ifdef __DEBUG__ + printf("Screen[y1,y2]:[%i,%i],Mode:%i, BG0:%i,BG1:%i,BG2:%i,BG3:%i,OBJ:%i\n", GFX.StartY, GFX.EndY, PPU.BGMode, BG0, BG1, BG2, BG3, OB); +#endif + + sub |= force_no_add; + + if (PPU.BGMode <= 1) + { + if (OB) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); + DrawOBJS (!sub, D); + } + if (BG0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(0)); + DrawBackground (PPU.BGMode, 0, D + 10, D + 14); + } + if (BG1) + { + SelectTileRenderer (sub || !SUB_OR_ADD(1)); + DrawBackground (PPU.BGMode, 1, D + 9, D + 13); + } + if (BG2) + { + SelectTileRenderer (sub || !SUB_OR_ADD(2)); + DrawBackground (PPU.BGMode, 2, D + 3, + PPU.BG3Priority ? D + 17 : D + 6); + } + if (BG3 && PPU.BGMode == 0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(3)); + DrawBackground (PPU.BGMode, 3, D + 2, D + 5); + } + } + else if (PPU.BGMode != 7) + { + if (OB) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); + DrawOBJS (!sub, D); + } + if (BG0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(0)); + DrawBackground (PPU.BGMode, 0, D + 5, D + 13); + } + if (PPU.BGMode != 6 && BG1) + { + SelectTileRenderer (sub || !SUB_OR_ADD(1)); + DrawBackground (PPU.BGMode, 1, D + 2, D + 9); + } + } + else + { + if (OB && ((SNESGameFixes.Mode7Hack && D) || !SNESGameFixes.Mode7Hack)) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); + DrawOBJS (!sub, D); + } + if (BG0 || ((Memory.FillRAM [0x2133] & 0x40) && BG1)) + { + int bg; + + if ((Memory.FillRAM [0x2133] & 0x40)&&BG1) + { + Mode7Depths [0] = (BG0?5:1) + D; + Mode7Depths [1] = 9 + D; + bg = 1; + if (sub || !SUB_OR_ADD(0)) + { + DrawBGMode7Background16Prio (Screen, bg); + } + else + { + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16PrioSub1_2 (Screen, bg); + } + else + { + DrawBGMode7Background16PrioSub (Screen, bg); + } + } + else + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16PrioAdd1_2 (Screen, bg); + } + else + { + DrawBGMode7Background16PrioAdd (Screen, bg); + } + } + } + } + else + { + bg = 0; + if (sub || !SUB_OR_ADD(0)) + { + if (D || !SNESGameFixes.Mode7Hack) DrawBGMode7Background16 (Screen, bg, D+5); + else DrawBGMode7Background16New (Screen); + } + else + { + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Sub1_2 (Screen, bg, D+5); + } + else + { + DrawBGMode7Background16Sub (Screen, bg, D+5); + } + } + else + { + if (GFX.r2131 & 0x40) + { + DrawBGMode7Background16Add1_2 (Screen, bg, D+5); + } + else + { + DrawBGMode7Background16Add (Screen, bg, D+5); + } + } + } + } + } + if (OB && SNESGameFixes.Mode7Hack && D==0) + { + SelectTileRenderer (sub || !SUB_OR_ADD(4), true); + DrawOBJS (!sub, D); + } + } +} + +#include "font.h" + +void DisplayChar (uint8 *Screen, uint8 c) +{ + int line = (((c & 0x7f) - 32) >> 4) * font_height; + int offset = (((c & 0x7f) - 32) & 15) * font_width; + int h, w; + uint16 *s = (uint16 *) Screen; + for (h = 0; h < font_height; h++, line++, + s += GFX_PPL - font_width) + { + for (w = 0; w < font_width; w++, s++) + { + uint8 p = font [line][offset + w]; + + if (p == '#') + *s = 0xffff; + else + if (p == '.') + *s = BLACK; + } + } +} + +static void S9xDisplayFrameRate () +{ + uint8 *Screen = GFX.Screen + 2 + + (IPPU.RenderedScreenHeight - font_height - 1) * GFX_PITCH; + char string [10]; + int len = 5; + + sprintf (string, "%02d/%02d", IPPU.DisplayedRenderedFrameCount, + (int) Memory.ROMFramesPerSecond); + + int i; + for (i = 0; i < len; i++) + { + DisplayChar (Screen, string [i]); + Screen += (font_width - 1) * sizeof (uint16); + } +} + +static void S9xDisplayString (const char *string) +{ + uint8 *Screen = GFX.Screen + 2 + + (IPPU.RenderedScreenHeight - font_height * 5) * GFX_PITCH; + int len = strlen (string); + int max_chars = IPPU.RenderedScreenWidth / (font_width - 1); + int char_count = 0; + int i; + + for (i = 0; i < len; i++, char_count++) + { + if (char_count >= max_chars || string [i] < 32) + { + Screen -= (font_width - 1) * sizeof (uint16) * max_chars; + Screen += font_height * GFX_PITCH; + if (Screen >= GFX.Screen + GFX_PITCH * IPPU.RenderedScreenHeight) + break; + char_count -= max_chars; + } + if (string [i] < 32) + continue; + DisplayChar (Screen, string [i]); + Screen += (font_width - 1) * sizeof (uint16); + } +} + + +void S9xUpdateScreen () // ~30-50ms! (called from FLUSH_REDRAW()) +{ + GFX.S = GFX.Screen; + + unsigned char *memoryfillram = Memory.FillRAM; + + // get local copies of vid registers to be used later + GFX.r2131 = memoryfillram [0x2131]; // ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN + GFX.r212c = memoryfillram [0x212c]; // MAIN SCREEN, DESIGNATION - used to enable BGS + GFX.r212d = memoryfillram [0x212d]; // SUB SCREEN DESIGNATION - used to enable sub BGS + GFX.r2130 = memoryfillram [0x2130]; // INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION + + // If external sync is off and + // main screens have not been configured the same as the sub screen and + // color addition and subtraction has been diabled then + // Pseudo is 1 + // anything else it is 0 + GFX.Pseudo = (memoryfillram [0x2133] & 8) != 0 && // Use EXTERNAL SYNCHRONIZATION? + (GFX.r212c & 15) != (GFX.r212d & 15) && // Are the main screens different from the sub screens? + (GFX.r2131 & 0x3f) == 0; // Is colour data addition/subtraction disabled on all BGS? + + // If sprite data has been changed then go through and + // refresh the sprites. + if (IPPU.OBJChanged) S9xSetupOBJ (); + + if (PPU.RecomputeClipWindows) ComputeClipWindows (); + + GFX.StartY = IPPU.PreviousLine; + if ((GFX.EndY = IPPU.CurrentLine - 1) >= PPU.ScreenHeight) + GFX.EndY = PPU.ScreenHeight - 1; + + uint32 starty = GFX.StartY; + uint32 endy = GFX.EndY; + uint32 black = BLACK | (BLACK << 16); + + + if (GFX.Pseudo) + { + GFX.r2131 = 0x5f; //0101 1111 - enable addition/subtraction on all BGS and sprites and "1/2 OF COLOR DATA" DESIGNATION + GFX.r212c &= (Memory.FillRAM [0x212d] | 0xf0); + GFX.r212d |= (Memory.FillRAM [0x212c] & 0x0f); + GFX.r2130 |= 2; // enable ADDITION/SUBTRACTION FOR SUB SCREEN + } + + // Check to see if any transparency effects are currently in use + if (!PPU.ForcedBlanking && ADD_OR_SUB_ON_ANYTHING && + (GFX.r2130 & 0x30) != 0x30 && + !((GFX.r2130 & 0x30) == 0x10 && IPPU.Clip[1].Count[5] == 0)) + { + // transparency effects in use, so lets get busy! + struct ClipData *pClip; + uint32 fixedColour; + GFX.FixedColour = BUILD_PIXEL (IPPU.XB [PPU.FixedColourRed], + IPPU.XB [PPU.FixedColourGreen], + IPPU.XB [PPU.FixedColourBlue]); + fixedColour = (GFX.FixedColour<<16|GFX.FixedColour); + // Clear the z-buffer, marking areas 'covered' by the fixed + // colour as depth 1. + pClip = &IPPU.Clip [1]; + + // Clear the z-buffer + + if (pClip->Count [5]) + { + + // Colour window enabled. + // loop around all of the lines being updated + for (uint32 y = starty; y <= endy; y++) + { + // Clear the subZbuffer + memset32 ((uint32_t*)(GFX.SubZBuffer + y * GFX_ZPITCH),0, (256>>2)); + // Clear the Zbuffer + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH),0, (256>>2)); + if (IPPU.Clip[0].Count [5]) { + // if there is clipping then clear subscreen to a black color + memset32 ((uint32_t*)(GFX.SubScreen + y * GFX_PITCH), black, (256>>1)); + } + + // loop through all window clippings + for (uint32 c = 0; c < pClip->Count [5]; c++) + { + if (pClip->Right [c][5] > pClip->Left [c][5]) + { + memset (GFX.SubZBuffer + y * GFX_ZPITCH + pClip->Left [c][5], + 1, pClip->Right [c][5] - pClip->Left [c][5]); + + if (IPPU.Clip [0].Count [5]) + { + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + + register unsigned int width = pClip->Right [c][5] - pClip->Left [c][5]; + if (width > 0) { + asm volatile ( + " mov r0, %[fixedcolour] \n" + " subs %[width], %[width], #4 \n" + " bmi 2f \n" + + "1: \n" + " subs %[width], %[width], #4 \n" + " stmia %[p]!, {r0, %[fixedcolour]}\n" + " bpl 1b \n" + + "2: \n" + " tst %[width], #1 \n" + " strneh %[fixedcolour], [%[p]], #2 \n" + + " tst %[width], #2 \n" + " strne %[fixedcolour], [%[p]], #4 \n" + + : [width] "+r" (width) + : [fixedcolour] "r" (fixedColour), + [p] "r" (((uint16 *) (GFX.SubScreen + y * GFX_PITCH)) + pClip->Left [c][5]) + : "r0", "cc" + ); + } + } + } + } + } + + } + else + { + // No windows are clipping the main screen + // this simplifies the screen clearing process + // loop through all of the lines to be updated + for (uint32 y = starty; y <= endy; y++) { + // Clear the Zbuffer + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH),0, (256>>2)); + // clear the sub Zbuffer to 1 + memset32 ((uint32_t*)(GFX.SubZBuffer + y * GFX_ZPITCH), 0x01010101, (256>>2)); + + if (IPPU.Clip [0].Count [5]) { + // Blast, have to clear the sub-screen to the fixed-colour + // because there is a colour window in effect clipping + // the main screen that will allow the sub-screen + // 'underneath' to show through. + + memset32 ((uint32_t*)(GFX.SubScreen + y * GFX_PITCH), fixedColour, (256>>1)); + } + } + } + if (ANYTHING_ON_SUB) + { + GFX.DB = GFX.SubZBuffer; + RenderScreen (GFX.SubScreen, TRUE, TRUE, SUB_SCREEN_DEPTH); + } + + if (IPPU.Clip [0].Count [5]) + { + asm volatile ( + "1: \n" + " mov r1, #(256 >> 2) \n" + + "2: \n" + // four pixels at once + " ldrb r0, [%[d]], #1 \n" + " ldrb r4, [%[d]], #1 \n" + + " bics r0, r0, #1 \n" + " ldrneh r0, [%[p], %[delta]] \n" + + " bics r4, r4, #1 \n" + " ldrneh r4, [%[p], %[delta2]] \n" + + " strh r0, [%[p]], #2 \n" + " strh r4, [%[p]], #2 \n" + + " ldrb r0, [%[d]], #1 \n" + " ldrb r4, [%[d]], #1 \n" + + " bics r0, r0, #1 \n" + " ldrneh r0, [%[p], %[delta]] \n" + + " bics r4, r4, #1 \n" + " ldrneh r4, [%[p], %[delta2]] \n" + + " strh r0, [%[p]], #2 \n" + " strh r4, [%[p]], #2 \n" + + " subs r1, r1, #1 \n" + " bne 2b \n" + "3: \n" + " subs %[lines], %[lines], #1 \n" + " add %[p], %[p], #(640 - 512) \n" + " add %[d], %[d], #(320 - 256) \n" + " bne 1b \n" + "4: \n" + + : + : [p] "r" ((uint16 *) (GFX.Screen + starty * GFX_PITCH)), + [d] "r" (GFX.SubZBuffer + starty * GFX_ZPITCH), + [delta] "r" (GFX.Delta << 1), + [delta2] "r" ((GFX.Delta << 1) + 2), + [lines] "r" (endy - starty + 1) + : "r0", "r1", "r3", "r4", "cc" + ); + } + + GFX.DB = GFX.ZBuffer; + RenderScreen (GFX.Screen, FALSE, FALSE, MAIN_SCREEN_DEPTH); + if (SUB_OR_ADD(5)) + { + uint32 back = IPPU.ScreenColors [0]; + uint32 Left = 0; + uint32 Right = 256; + uint32 Count; + + pClip = &IPPU.Clip [0]; + + for (uint32 y = starty; y <= endy; y++) + { + if (!(Count = pClip->Count [5])) + { + Left = 0; + Right = 256; + Count = 1; + } + + for (uint32 b = 0; b < Count; b++) + { + if (pClip->Count [5]) + { + Left = pClip->Left [b][5]; + Right = pClip->Right [b][5]; + if (Right <= Left) + continue; + } +#define SUBSCREEN_BG(rop, half) \ +\ +asm volatile (\ +" ldrb r0, [%[d]], #1 \n"\ +"71: \n"\ +\ +" movs r0, r0 \n"\ +" ldreqb r1, [%[d], %[zdelta]] \n"\ +" bne 72f \n"\ +\ +" cmp r1, #1 \n"\ +" beq 74f \n"\ +" ldrh r1, [%[p], %[delta]] \n"\ +" mov r0, %[back] \n"\ +\ +ROP_##rop##half (r0, r1)\ +\ +" strh r0, [%[p]] \n"\ +"72: \n"\ +" add %[p], %[p], #2 \n"\ +" subs %[c], %[c], #1 \n"\ +" ldrneb r0, [%[d]], #1 \n"\ +" bne 71b \n"\ +" b 75f \n"\ +"74: \n"\ +" streqh %[fixedcolour], [%[p]], #2 \n"\ +" strloh %[back], [%[p]], #2 \n"\ +" subs %[c], %[c], #1 \n"\ +" ldrneb r0, [%[d]], #1 \n"\ +" bne 71b \n"\ +"75: \n"\ +:\ +:[p] "r" ((uint16 *) (GFX.Screen + y * GFX_PITCH) + Left),\ + [d] "r" (GFX.ZBuffer + y * GFX_ZPITCH + Left),\ + [zdelta] "r" (GFX.DepthDelta),\ + [back] "r" (back),\ + [delta] "r" (GFX.Delta << 1),\ + [fixedcolour] "r" (COLOR_##rop (back, GFX.FixedColour)),\ + [c] "r" (Right - Left) \ +: "r0", "r1", "cc"\ +); + if (GFX.r2131 & 0x80) + { + if (GFX.r2131 & 0x40) + { + SUBSCREEN_BG(SUB, 1_2) + } + else + { + SUBSCREEN_BG(SUB, ) + + } + } + else + if (GFX.r2131 & 0x40) + { + SUBSCREEN_BG(ADD, 1_2) + } + else if (back != 0) { + SUBSCREEN_BG(ADD, ) + } + else + { + if (!pClip->Count [5]) + { + // The backdrop has not been cleared yet - so + // copy the sub-screen to the main screen + // or fill it with the back-drop colour if the + // sub-screen is clear. + asm volatile ( + " ldrb r0, [%[d]], #1 \n" + "31: \n" + + " movs r0, r0 \n" + " ldreqb r1, [%[d], %[zdelta]] \n" + " bne 32f \n" + + " cmp r1, #1 \n" + " ldrhih r0, [%[p], %[delta]] \n" + " strloh %[back], [%[p]] \n" + " streqh %[fixedcolour], [%[p]] \n" + " strhih r0, [%[p]] \n" + + "32: \n" + " subs %[c], %[c], #1 \n" + " add %[p], %[p], #2 \n" + " ldrneb r0, [%[d]], #1 \n" + " bne 31b \n" + " \n" + : + :[p] "r" ((uint16 *) (GFX.Screen + y * GFX_PITCH) + Left), + [d] "r" (GFX.ZBuffer + y * GFX_ZPITCH + Left), + [zdelta] "r" (GFX.DepthDelta), + [back] "r" (back), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [c] "r" (Right - Left) + : "r0", "r1", "cc" + + ); + + } + } + } + } + + } + else + { + // Subscreen not being added to back + uint32 back = IPPU.ScreenColors [0] | (IPPU.ScreenColors [0] << 16); + pClip = &IPPU.Clip [0]; + + if (pClip->Count [5]) + { + for (uint32 y = starty; y <= endy; y++) + { + for (uint32 b = 0; b < pClip->Count [5]; b++) + { + uint32 Left = pClip->Left [b][5]; + uint32 Right = pClip->Right [b][5]; + if (Left >= Right) continue; + asm volatile ( + + " tst %[c], #1 \n" + " bne 21f \n" + + " ldrb r0, [%[d]], #1 \n" + " add %[p], %[p], #2 \n" + " movs r0, r0 \n" + " streqh %[back], [%[p], #-2] \n" + " subs %[c], %[c], #1 \n" + " beq 22f \n" + + "21: \n" + + " ldrb r0, [%[d]], #1 \n" + " ldrb r1, [%[d]], #1 \n" + " add %[p], %[p], #4 \n" + + " movs r0, r0 \n" + " streqh %[back], [%[p], #-4] \n" + + " movs r1, r1 \n" + " streqh %[back], [%[p], #-2] \n" + + " subs %[c], %[c], #2 \n" + " bhi 21b \n" + "22: \n" + : + :[p] "r" ((uint16 *) (GFX.Screen + y * GFX_PITCH) + Left), + [d] "r" (GFX.ZBuffer + y * GFX_ZPITCH + Left), + [back] "r" (back), + [c] "r" (Right - Left) + : "r0", "r1", "cc" + + ); + } + } + } + else + { + asm volatile ( + "@ -- SubScreen clear \n" + "1113: \n" + " mov r1, #(256/8) \n" + "1112: \n" + " ldr r0, [%[d]], #4 \n" + + " add %[p], %[p], #8 \n" + + " tst r0, #0x0ff \n" + " streqh %[back], [%[p], #-8] \n" + + " tst r0, #0x0ff00 \n" + " streqh %[back], [%[p], #-6] \n" + + " tst r0, #0x0ff0000 \n" + " streqh %[back], [%[p], #-4] \n" + + " tst r0, #0x0ff000000 \n" + " streqh %[back], [%[p], #-2] \n" + + " ldr r0, [%[d]], #4 \n" + + " add %[p], %[p], #8 \n" + + " tst r0, #0x0ff \n" + " streqh %[back], [%[p], #-8] \n" + + " tst r0, #0x0ff00 \n" + " streqh %[back], [%[p], #-6] \n" + + " tst r0, #0x0ff0000 \n" + " streqh %[back], [%[p], #-4] \n" + + " tst r0, #0x0ff000000 \n" + " streqh %[back], [%[p], #-2] \n" + + " subs r1, r1, #1 \n" + " bne 1112b \n" + + " subs %[lines], %[lines], #1 \n" + " add %[p], %[p], #(640-512) \n" + " add %[d], %[d], #(320-256) \n" + " bne 1113b \n" + "1114:" + : + :[p] "r" (GFX.Screen + starty * GFX_PITCH), + [d] "r" (GFX.ZBuffer + starty * GFX_ZPITCH), + [back] "r" (back), + [lines] "r" (endy - starty + 1) + : "r0", "r1", "cc" + ); + } + } + } + else + { + // 16bit and transparency but currently no transparency effects in + // operation. + + // get the back colour of the current screen + uint32 back = IPPU.ScreenColors [0] | + (IPPU.ScreenColors [0] << 16); + + // if forceblanking in use then use black instead of the back color + if (PPU.ForcedBlanking) + back = black; + + // not sure what Clip is used for yet + // could be a check to see if there is any clipping present? + if (IPPU.Clip [0].Count[5]) + { + + // loop through all of the lines that are going to be updated as part of this screen update + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), black, + IPPU.RenderedScreenWidth>>1); + + if (black!=back) + { + for (uint32 c = 0; c < IPPU.Clip [0].Count [5]; c++) + { + if (IPPU.Clip [0].Right [c][5] > IPPU.Clip [0].Left [c][5]) + { + register unsigned int width = IPPU.Clip [0].Right [c][5] - IPPU.Clip [0].Left [c][5]; + if (width > 0) { + asm volatile ( + " mov r0, %[back] \n" + " subs %[width], %[width], #4 \n" + " bmi 2f \n" + + "1: \n" + " subs %[width], %[width], #4 \n" + " stmia %[p]!, {r0, %[back]} \n" + " bpl 1b \n" + + "2: \n" + " tst %[width], #1 \n" + " strneh %[back], [%[p]], #2 \n" + + " tst %[width], #2 \n" + " strne %[back], [%[p]], #4 \n" + : [width] "+r" (width) + : [back] "r" (back | (back << 16)), + [p] "r" (((uint16 *) (GFX.SubScreen + y * GFX_PITCH)) + IPPU.Clip [0].Left [c][5]) + : "r0", "cc" + ); + } + + } + } + } + } + } + else + { + // there is no clipping to worry about so just fill with the back colour + for (uint32 y = starty; y <= endy; y++) { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), back, (256>>1)); + } + + } + + // If Forced blanking is not in effect + if (!PPU.ForcedBlanking) + { + // Clear the Zbuffer for each of the lines which are going to be updated + for (uint32 y = starty; y <= endy; y++) { + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH), 0, (256>>2)); + } + GFX.DB = GFX.ZBuffer; // save pointer to Zbuffer in GFX object + RenderScreen (GFX.Screen, FALSE, TRUE, SUB_SCREEN_DEPTH); + } + } + IPPU.PreviousLine = IPPU.CurrentLine; +} + +// -x- +void S9xUpdateScreenNoTransparency () // ~30-50ms! (called from FLUSH_REDRAW()) +{ + GFX.S = GFX.Screen; + + unsigned char *memoryfillram = Memory.FillRAM; + + // get local copies of vid registers to be used later + GFX.r2131 = memoryfillram [0x2131]; // ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN + GFX.r212c = memoryfillram [0x212c]; // MAIN SCREEN, DESIGNATION - used to enable BGS + GFX.r212d = memoryfillram [0x212d]; // SUB SCREEN DESIGNATION - used to enable sub BGS + GFX.r2130 = memoryfillram [0x2130]; // INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION + + // If external sync is off and + // main screens have not been configured the same as the sub screen and + // color addition and subtraction has been diabled then + // Pseudo is 1 + // anything else it is 0 + GFX.Pseudo = (memoryfillram [0x2133] & 8) != 0 && // Use EXTERNAL SYNCHRONIZATION? + (GFX.r212c & 15) != (GFX.r212d & 15) && // Are the main screens different from the sub screens? + (GFX.r2131 & 0x3f) == 0; // Is colour data addition/subtraction disabled on all BGS? + + // If sprite data has been changed then go through and + // refresh the sprites. + if (IPPU.OBJChanged) + { + S9xSetupOBJ (); + } + + if (PPU.RecomputeClipWindows) ComputeClipWindows(); + + GFX.StartY = IPPU.PreviousLine; + if ((GFX.EndY = IPPU.CurrentLine - 1) >= PPU.ScreenHeight) + GFX.EndY = PPU.ScreenHeight - 1; + + uint32 starty = GFX.StartY; + uint32 endy = GFX.EndY; + + uint32 black = BLACK | (BLACK << 16); + + // get back colour to be used in clearing the screen + register uint32 back; + if (!(Memory.FillRAM [0x2131] & 0x80) &&(Memory.FillRAM[0x2131] & 0x20) && + (PPU.FixedColourRed || PPU.FixedColourGreen || PPU.FixedColourBlue)) + { + back = (IPPU.XB[PPU.FixedColourRed]<<11) | + (IPPU.XB[PPU.FixedColourGreen] << 6) | + (IPPU.XB[PPU.FixedColourBlue] << 1) | 1; + back = (back << 16) | back; + } + else + { + back = IPPU.ScreenColors [0] | (IPPU.ScreenColors [0] << 16); + } + + // if Forcedblanking in use then back colour becomes black + if (PPU.ForcedBlanking) + back = black; + else + { + SelectTileRenderer (TRUE); //selects the tile renderers to be used + // TRUE means to use the default + // FALSE means use best renderer based on current + // graphics register settings + } + + // now clear all graphics lines which are being updated using the back colour + for (register uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.Screen + y * GFX_PITCH), back, + IPPU.RenderedScreenWidth>>1); + } + + if (!PPU.ForcedBlanking) + { + // Loop through all lines being updated and clear the + // zbuffer for each of the lines + for (uint32 y = starty; y <= endy; y++) + { + memset32 ((uint32_t*)(GFX.ZBuffer + y * GFX_ZPITCH), 0, + IPPU.RenderedScreenWidth>>2); + } + GFX.DB = GFX.ZBuffer; // save pointer to Zbuffer in GFX object + GFX.pCurrentClip = &IPPU.Clip [0]; + +// Define an inline function to handle clipping +#define FIXCLIP(n) \ +if (GFX.r212c & (1 << (n))) \ + GFX.pCurrentClip = &IPPU.Clip [0]; \ +else \ + GFX.pCurrentClip = &IPPU.Clip [1] + +// Define an inline function to handle which BGs are being displayed +#define DISPLAY(n) ((GFX.r212c & n) || ((GFX.r212d & n) && subadd)) + + uint8 subadd = GFX.r2131 & 0x3f; + + // go through all BGS are check if they need to be displayed + bool8_32 BG0 = DISPLAY(1) && !(Settings.os9x_hack & GFX_IGNORE_BG0); + bool8_32 BG1 = DISPLAY(2) && !(Settings.os9x_hack & GFX_IGNORE_BG1); + bool8_32 BG2 = DISPLAY(4) && !(Settings.os9x_hack & GFX_IGNORE_BG2); + bool8_32 BG3 = DISPLAY(8) && !(Settings.os9x_hack & GFX_IGNORE_BG3); + bool8_32 OB = DISPLAY(16) && !(Settings.os9x_hack & GFX_IGNORE_OBJ); + + if (PPU.BGMode <= 1) + { + // screen modes 0 and 1 + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + if (BG0) + { + FIXCLIP(0); + DrawBackground (PPU.BGMode, 0, 10, 14); + } + if (BG1) + { + FIXCLIP(1); + DrawBackground (PPU.BGMode, 1, 9, 13); + } + if (BG2) + { + FIXCLIP(2); + DrawBackground (PPU.BGMode, 2, 3, + PPU.BG3Priority ? 17 : 6); + } + if (BG3 && PPU.BGMode == 0) + { + FIXCLIP(3); + DrawBackground (PPU.BGMode, 3, 2, 5); + } + } + else if (PPU.BGMode != 7) + { + // screen modes 2 and up but not mode 7 + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + if (BG0) + { + FIXCLIP(0); + DrawBackground (PPU.BGMode, 0, 5, 13); + } + if (BG1 && PPU.BGMode != 6) + { + FIXCLIP(1); + DrawBackground (PPU.BGMode, 1, 2, 9); + } + } + else + { + // screen mode 7 + DrawBGMode7Background16New (GFX.Screen); + if (OB) + { + FIXCLIP(4); + DrawOBJS (); + } + } + } + IPPU.PreviousLine = IPPU.CurrentLine; +} + +// -x- + +#ifdef GFX_MULTI_FORMAT + +#define _BUILD_PIXEL(F) \ +uint32 BuildPixel##F(uint32 R, uint32 G, uint32 B) \ +{ \ + return (BUILD_PIXEL_##F(R,G,B)); \ +}\ +uint32 BuildPixel2##F(uint32 R, uint32 G, uint32 B) \ +{ \ + return (BUILD_PIXEL2_##F(R,G,B)); \ +} \ +void DecomposePixel##F(uint32 pixel, uint32 &R, uint32 &G, uint32 &B) \ +{ \ + DECOMPOSE_PIXEL_##F(pixel,R,G,B); \ +} + +_BUILD_PIXEL(RGB565) +_BUILD_PIXEL(RGB555) +_BUILD_PIXEL(BGR565) +_BUILD_PIXEL(BGR555) +_BUILD_PIXEL(GBR565) +_BUILD_PIXEL(GBR555) +_BUILD_PIXEL(RGB5551) + +bool8_32 S9xSetRenderPixelFormat (int format) +{ + extern uint32 current_graphic_format; + + current_graphic_format = format; + + switch (format) + { + case RGB565: + _BUILD_SETUP(RGB565) + return (TRUE); + case RGB555: + _BUILD_SETUP(RGB555) + return (TRUE); + case BGR565: + _BUILD_SETUP(BGR565) + return (TRUE); + case BGR555: + _BUILD_SETUP(BGR555) + return (TRUE); + case GBR565: + _BUILD_SETUP(GBR565) + return (TRUE); + case GBR555: + _BUILD_SETUP(GBR555) + return (TRUE); + case RGB5551: + _BUILD_SETUP(RGB5551) + return (TRUE); + default: + break; + } + return (FALSE); +} +#endif diff --git a/src/giz_kgsdk.c b/src/giz_kgsdk.c new file mode 100644 index 0000000..2bfa6b4 --- /dev/null +++ b/src/giz_kgsdk.c @@ -0,0 +1,343 @@ + +#include +#include "giz_kgsdk.h" +#include + +unsigned short *framebuffer16[4]={0,0,0,0}; +unsigned char *framebuffer8[4]; +void *GizPrimaryFrameBuffer=NULL; +volatile unsigned short gp2x_palette[512][2]; +int Timer=0; +static int bppMode = 16; +static unsigned int padValues[2]={0,0}; + +//Temp framebuffer +unsigned short frameBufferMemory[320*250]; + +// 1024x8 8x8 font, i love it :) +const unsigned int font8x8[]= {0x0,0x0,0xc3663c18,0x3c2424e7,0xe724243c,0x183c66c3,0xc16f3818,0x18386fc1,0x83f61c18,0x181cf683,0xe7c3993c,0x3c99c3,0x3f7fffff,0xe7cf9f,0x3c99c3e7,0xe7c399,0x3160c080,0x40e1b,0xcbcbc37e, +0x7ec3c3db,0x3c3c3c18,0x81c087e,0x8683818,0x60f0e08,0x81422418,0x18244281,0xbd5a2418,0x18245abd,0x818181ff,0xff8181,0xa1c181ff,0xff8995,0x63633e,0x3e6363,0x606060,0x606060,0x3e60603e,0x3e0303,0x3e60603e,0x3e6060,0x3e636363, +0x606060,0x3e03033e,0x3e6060,0x3e03033e,0x3e6363,0x60603e,0x606060,0x3e63633e,0x3e6363,0x3e63633e,0x3e6060,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x18181818,0x180018,0x666666,0x0,0x367f3600,0x367f36,0x3c067c18, +0x183e60,0x18366600,0x62660c,0xe1c361c,0x6e337b,0x181818,0x0,0x18183870,0x703818,0x18181c0e,0xe1c18,0xff3c6600,0x663c,0x7e181800,0x1818,0x0,0x60c0c00,0x7e000000,0x0,0x0,0x181800,0x18306040,0x2060c,0x6e76663c,0x3c6666,0x18181c18, +0x7e1818,0x3060663c,0x7e0c18,0x3018307e,0x3c6660,0x363c3830,0x30307e,0x603e067e,0x3c6660,0x3e06063c,0x3c6666,0x1830607e,0xc0c0c,0x3c66663c,0x3c6666,0x7c66663c,0x1c3060,0x181800,0x1818,0x181800,0xc1818,0xc183060,0x603018,0x7e0000, +0x7e00,0x30180c06,0x60c18,0x3060663c,0x180018,0x5676663c,0x7c0676,0x66663c18,0x66667e,0x3e66663e,0x3e6666,0x606663c,0x3c6606,0x6666361e,0x1e3666,0x3e06067e,0x7e0606,0x3e06067e,0x60606,0x7606067c,0x7c6666,0x7e666666,0x666666,0x1818183c, +0x3c1818,0x60606060,0x3c6660,0xe1e3666,0x66361e,0x6060606,0x7e0606,0x6b7f7763,0x636363,0x7e7e6e66,0x666676,0x6666663c,0x3c6666,0x3e66663e,0x60606,0x6666663c,0x6c366e,0x3e66663e,0x666636,0x3c06663c,0x3c6660,0x1818187e,0x181818,0x66666666, +0x7c6666,0x66666666,0x183c66,0x6b636363,0x63777f,0x183c6666,0x66663c,0x3c666666,0x181818,0x1830607e,0x7e060c,0x18181878,0x781818,0x180c0602,0x406030,0x1818181e,0x1e1818,0x63361c08,0x0,0x0,0x7f0000,0xc060300,0x0,0x603c0000,0x7c667c,0x663e0606, +0x3e6666,0x63c0000,0x3c0606,0x667c6060,0x7c6666,0x663c0000,0x3c067e,0xc3e0c38,0xc0c0c,0x667c0000,0x3e607c66,0x663e0606,0x666666,0x181c0018,0x3c1818,0x18180018,0xe181818,0x36660606,0x66361e,0x1818181c,0x3c1818,0x7f370000,0x63636b,0x663e0000, +0x666666,0x663c0000,0x3c6666,0x663e0000,0x63e6666,0x667c0000,0x607c6666,0x663e0000,0x60606,0x67c0000,0x3e603c,0x187e1800,0x701818,0x66660000,0x7c6666,0x66660000,0x183c66,0x63630000,0x363e6b,0x3c660000,0x663c18,0x66660000,0x3e607c66,0x307e0000, +0x7e0c18,0xc181870,0x701818,0x18181818,0x18181818,0x3018180e,0xe1818,0x794f0600,0x30}; + +/* +######################## +Graphics functions +######################## + */ + +static __inline__ +void gp_drawPixel8 ( int x, int y, unsigned char c, unsigned char *framebuffer ) +{ + *(framebuffer +(320*y)+x ) = c; +} + +static __inline__ +void gp_drawPixel16 ( int x, int y, unsigned short c, unsigned short *framebuffer ) +{ + *(framebuffer +(320*y)+x ) = c; +} + +static +void set_char8x8_16bpp (int xx,int yy,int offset,unsigned short mode,unsigned short *framebuffer) +{ + unsigned int y, pixel; + offset *= 2; + pixel = font8x8[0 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y, mode, framebuffer); + } + pixel = font8x8[1 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y+4, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y+4, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y+4, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y+4, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y+4, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y+4, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y+4, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y+4, mode, framebuffer); + + } +} + +static +void set_char8x8_8bpp (int xx,int yy,int offset,unsigned char mode,unsigned char *framebuffer) +{ + unsigned int y, pixel; + offset *= 2; + pixel = font8x8[0 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel8(xx+0, yy+y, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel8(xx+1, yy+y, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel8(xx+2, yy+y, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel8(xx+3, yy+y, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel8(xx+4, yy+y, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel8(xx+5, yy+y, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel8(xx+6, yy+y, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel8(xx+7, yy+y, mode, framebuffer); + } + pixel = font8x8[1 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel8(xx+0, yy+y+4, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel8(xx+1, yy+y+4, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel8(xx+2, yy+y+4, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel8(xx+3, yy+y+4, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel8(xx+4, yy+y+4, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel8(xx+5, yy+y+4, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel8(xx+6, yy+y+4, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel8(xx+7, yy+y+4, mode, framebuffer); + + } +} + +void gp_drawString (int x,int y,int len,char *buffer,unsigned short color,void *framebuffer) +{ + int l,base=0; + + for (l=0;l>1 +1: + ;@ first line is perfectly aligned + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + ldmia r0!,{r2-r11} + stmia r1!,{r2-r11} + + add r1,r1,#2 + + ldmia r0!,{r2-r6} + strh r2,[r1],#2 + mov lr,#15 +2: + mov r2,r2,lsr#16 + orr r2,r2,r3,lsl#16 + mov r3,r3,lsr#16 + orr r3,r3,r4,lsl#16 + mov r4,r4,lsr#16 + orr r4,r4,r5,lsl#16 + mov r5,r5,lsr#16 + orr r5,r5,r6,lsl#16 + mov r6,r6,lsr#16 + ldmia r0!,{r7-r11} + orr r6,r6,r7,lsl#16 + stmia r1!,{r2-r6} + mov r7,r7,lsr#16 + orr r7,r7,r8,lsl#16 + mov r8,r8,lsr#16 + orr r8,r8,r9,lsl#16 + mov r9,r9,lsr#16 + orr r9,r9,r10,lsl#16 + mov r10,r10,lsr#16 + orr r10,r10,r11,lsl#16 + mov r11,r11,lsr#16 + ldmia r0!,{r2-r6} + orr r11,r11,r2,lsl#16 + stmia r1!,{r7-r11} + subs lr,lr,#1 + bne 2b + + mov r2,r2,lsr#16 + orr r2,r2,r3,lsl#16 + mov r3,r3,lsr#16 + orr r3,r3,r4,lsl#16 + mov r4,r4,lsr#16 + orr r4,r4,r5,lsl#16 + mov r5,r5,lsr#16 + orr r5,r5,r6,lsl#16 + mov r6,r6,lsr#16 + ldmia r0!,{r7-r11} + orr r6,r6,r7,lsl#16 + stmia r1!,{r2-r6} + mov r7,r7,lsr#16 + orr r7,r7,r8,lsl#16 + mov r8,r8,lsr#16 + orr r8,r8,r9,lsl#16 + mov r9,r9,lsr#16 + orr r9,r9,r10,lsl#16 + mov r10,r10,lsr#16 + orr r10,r10,r11,lsl#16 + mov r11,r11,lsr#16 + stmia r1!,{r7-r11} + + subs r12,r12,#1 + bne 1b + + ldmfd sp!,{r4-r12,pc} + + + diff --git a/src/giz_sdk_kgsdk.c b/src/giz_sdk_kgsdk.c new file mode 100644 index 0000000..3cd7ccd --- /dev/null +++ b/src/giz_sdk_kgsdk.c @@ -0,0 +1,343 @@ + +#define DEBUG + +#include +#include +#include +#include "giz_sdk_kgsdk.h" +#include + + +#define SYS_CLK_FREQ 7372800 +unsigned long gp2x_ticks_per_second=7372800/1000; +unsigned long gp2x_dev[5]={0,0,0,0,0}; +unsigned long gp2x_physvram[4]={0,0,0,0}; +unsigned short *framebuffer16[4]={0,0,0,0}; +static unsigned short *framebuffer_mmap[4]={0,0,0,0}; +static int fb_size=(320*240*2)+(16*2); +unsigned short *gp2x_logvram15[2], gp2x_sound_buffer[4+((44100*2)*8)]; //*2=stereo, *4=max buffers +volatile unsigned short *gp2x_memregs; +volatile unsigned long *gp2x_memregl; +volatile unsigned long *gp2x_blitter = NULL; +unsigned int *gp2x_intVectors; +volatile unsigned short gp2x_palette[512][2]; +unsigned char *framebuffer8[4], *gp2x_screen8prev, *gp2x_logvram8[2]; +//pthread_t gp2x_sound_thread=0, gp2x_sound_thread_exit=0; +volatile short *pOutput[8]; +unsigned char InitFramebuffer=0; +int Timer=0; +volatile int SoundThreadFlag=0; +volatile int CurrentSoundBank=0; +int CurrentFrameBuffer=0; +int CurrentFrag=0; +unsigned short frameBufferMemory[320*250]; + +//Global SDL objects + +// 1024x8 8x8 font, i love it :) +const unsigned int font8x8[]= {0x0,0x0,0xc3663c18,0x3c2424e7,0xe724243c,0x183c66c3,0xc16f3818,0x18386fc1,0x83f61c18,0x181cf683,0xe7c3993c,0x3c99c3,0x3f7fffff,0xe7cf9f,0x3c99c3e7,0xe7c399,0x3160c080,0x40e1b,0xcbcbc37e, +0x7ec3c3db,0x3c3c3c18,0x81c087e,0x8683818,0x60f0e08,0x81422418,0x18244281,0xbd5a2418,0x18245abd,0x818181ff,0xff8181,0xa1c181ff,0xff8995,0x63633e,0x3e6363,0x606060,0x606060,0x3e60603e,0x3e0303,0x3e60603e,0x3e6060,0x3e636363, +0x606060,0x3e03033e,0x3e6060,0x3e03033e,0x3e6363,0x60603e,0x606060,0x3e63633e,0x3e6363,0x3e63633e,0x3e6060,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x18181818,0x180018,0x666666,0x0,0x367f3600,0x367f36,0x3c067c18, +0x183e60,0x18366600,0x62660c,0xe1c361c,0x6e337b,0x181818,0x0,0x18183870,0x703818,0x18181c0e,0xe1c18,0xff3c6600,0x663c,0x7e181800,0x1818,0x0,0x60c0c00,0x7e000000,0x0,0x0,0x181800,0x18306040,0x2060c,0x6e76663c,0x3c6666,0x18181c18, +0x7e1818,0x3060663c,0x7e0c18,0x3018307e,0x3c6660,0x363c3830,0x30307e,0x603e067e,0x3c6660,0x3e06063c,0x3c6666,0x1830607e,0xc0c0c,0x3c66663c,0x3c6666,0x7c66663c,0x1c3060,0x181800,0x1818,0x181800,0xc1818,0xc183060,0x603018,0x7e0000, +0x7e00,0x30180c06,0x60c18,0x3060663c,0x180018,0x5676663c,0x7c0676,0x66663c18,0x66667e,0x3e66663e,0x3e6666,0x606663c,0x3c6606,0x6666361e,0x1e3666,0x3e06067e,0x7e0606,0x3e06067e,0x60606,0x7606067c,0x7c6666,0x7e666666,0x666666,0x1818183c, +0x3c1818,0x60606060,0x3c6660,0xe1e3666,0x66361e,0x6060606,0x7e0606,0x6b7f7763,0x636363,0x7e7e6e66,0x666676,0x6666663c,0x3c6666,0x3e66663e,0x60606,0x6666663c,0x6c366e,0x3e66663e,0x666636,0x3c06663c,0x3c6660,0x1818187e,0x181818,0x66666666, +0x7c6666,0x66666666,0x183c66,0x6b636363,0x63777f,0x183c6666,0x66663c,0x3c666666,0x181818,0x1830607e,0x7e060c,0x18181878,0x781818,0x180c0602,0x406030,0x1818181e,0x1e1818,0x63361c08,0x0,0x0,0x7f0000,0xc060300,0x0,0x603c0000,0x7c667c,0x663e0606, +0x3e6666,0x63c0000,0x3c0606,0x667c6060,0x7c6666,0x663c0000,0x3c067e,0xc3e0c38,0xc0c0c,0x667c0000,0x3e607c66,0x663e0606,0x666666,0x181c0018,0x3c1818,0x18180018,0xe181818,0x36660606,0x66361e,0x1818181c,0x3c1818,0x7f370000,0x63636b,0x663e0000, +0x666666,0x663c0000,0x3c6666,0x663e0000,0x63e6666,0x667c0000,0x607c6666,0x663e0000,0x60606,0x67c0000,0x3e603c,0x187e1800,0x701818,0x66660000,0x7c6666,0x66660000,0x183c66,0x63630000,0x363e6b,0x3c660000,0x663c18,0x66660000,0x3e607c66,0x307e0000, +0x7e0c18,0xc181870,0x701818,0x18181818,0x18181818,0x3018180e,0xe1818,0x794f0600,0x30}; + +static int bppMode = 16; +static unsigned int padValues[2]={0,0}; +unsigned int ExistingIntHandler; + + +//SDL_Surface *sdlwrapper_screen; +/* +######################## +Graphics functions +######################## + */ + +static __inline__ +void gp_drawPixel8 ( int x, int y, unsigned char c, unsigned char *framebuffer ) +{ + *(framebuffer +(320*y)+x ) = c; +} + +static __inline__ +void gp_drawPixel16 ( int x, int y, unsigned short c, unsigned short *framebuffer ) +{ + *(framebuffer +(320*y)+x ) = c; +} + +static +void set_char8x8_16bpp (int xx,int yy,int offset,unsigned short mode,unsigned short *framebuffer) +{ + unsigned int y, pixel; + offset *= 2; + pixel = font8x8[0 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y, mode, framebuffer); + } + pixel = font8x8[1 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y+4, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y+4, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y+4, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y+4, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y+4, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y+4, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y+4, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y+4, mode, framebuffer); + + } +} + +static +void set_char8x8_8bpp (int xx,int yy,int offset,unsigned char mode,unsigned char *framebuffer) +{ + unsigned int y, pixel; + offset *= 2; + pixel = font8x8[0 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel8(xx+0, yy+y, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel8(xx+1, yy+y, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel8(xx+2, yy+y, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel8(xx+3, yy+y, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel8(xx+4, yy+y, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel8(xx+5, yy+y, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel8(xx+6, yy+y, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel8(xx+7, yy+y, mode, framebuffer); + } + pixel = font8x8[1 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel8(xx+0, yy+y+4, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel8(xx+1, yy+y+4, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel8(xx+2, yy+y+4, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel8(xx+3, yy+y+4, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel8(xx+4, yy+y+4, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel8(xx+5, yy+y+4, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel8(xx+6, yy+y+4, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel8(xx+7, yy+y+4, mode, framebuffer); + + } +} + +void gp_drawString (int x,int y,int len,char *buffer,unsigned short color,void *framebuffer) +{ +#if 1 + int l,base=0; + + for (l=0;l> 1; +uint32 RGB_LOW_BITS_MASK = (RED_LOW_BIT_MASK_RGB565 | + GREEN_LOW_BIT_MASK_RGB565 | + BLUE_LOW_BIT_MASK_RGB565); +uint32 RGB_HI_BITS_MASK = (RED_HI_BIT_MASK_RGB565 | + GREEN_HI_BIT_MASK_RGB565 | + BLUE_HI_BIT_MASK_RGB565); +uint32 RGB_HI_BITS_MASKx2 = (RED_HI_BIT_MASK_RGB565 | + GREEN_HI_BIT_MASK_RGB565 | + BLUE_HI_BIT_MASK_RGB565) << 1; +uint32 RGB_REMOVE_LOW_BITS_MASK = ~RGB_LOW_BITS_MASK; +uint32 FIRST_COLOR_MASK = FIRST_COLOR_MASK_RGB565; +uint32 SECOND_COLOR_MASK = SECOND_COLOR_MASK_RGB565; +uint32 THIRD_COLOR_MASK = THIRD_COLOR_MASK_RGB565; +uint32 ALPHA_BITS_MASK = ALPHA_BITS_MASK_RGB565; +uint32 FIRST_THIRD_COLOR_MASK = 0; +uint32 TWO_LOW_BITS_MASK = 0; +uint32 HIGH_BITS_SHIFTED_TWO_MASK = 0; + +uint32 current_graphic_format = RGB565; +#endif + +uint8 GetBank = 0; +struct SCheatData Cheat; + +SoundStatus so; +SSoundData SoundData; +int Echo [24000]; +int DummyEchoBuffer [SOUND_BUFFER_SIZE]; +int MixBuffer [SOUND_BUFFER_SIZE]; +int EchoBuffer [SOUND_BUFFER_SIZE]; +int FilterTaps [8]; +unsigned long Z = 0; +int Loop [16]; + +uint16 SignExtend [2] = { + 0x00, 0xff00 +}; + +int HDMA_ModeByteCounts [8] = { + 1, 2, 2, 4, 4, 0, 0, 0 +}; + +uint8 BitShifts[8][4] = +{ + {2, 2, 2, 2}, // 0 + {4, 4, 2, 0}, // 1 + {4, 4, 0, 0}, // 2 + {8, 4, 0, 0}, // 3 + {8, 2, 0, 0}, // 4 + {4, 2, 0, 0}, // 5 + {4, 0, 0, 0}, // 6 + {8, 0, 0, 0} // 7 +}; +uint8 TileShifts[8][4] = +{ + {4, 4, 4, 4}, // 0 + {5, 5, 4, 0}, // 1 + {5, 5, 0, 0}, // 2 + {6, 5, 0, 0}, // 3 + {6, 4, 0, 0}, // 4 + {5, 4, 0, 0}, // 5 + {5, 0, 0, 0}, // 6 + {6, 0, 0, 0} // 7 +}; +uint8 PaletteShifts[8][4] = +{ + {2, 2, 2, 2}, // 0 + {4, 4, 2, 0}, // 1 + {4, 4, 0, 0}, // 2 + {0, 4, 0, 0}, // 3 + {0, 2, 0, 0}, // 4 + {4, 2, 0, 0}, // 5 + {4, 0, 0, 0}, // 6 + {0, 0, 0, 0} // 7 +}; +uint8 PaletteMasks[8][4] = +{ + {7, 7, 7, 7}, // 0 + {7, 7, 7, 0}, // 1 + {7, 7, 0, 0}, // 2 + {0, 7, 0, 0}, // 3 + {0, 7, 0, 0}, // 4 + {7, 7, 0, 0}, // 5 + {7, 0, 0, 0}, // 6 + {0, 0, 0, 0} // 7 +}; +uint8 Depths[8][4] = +{ + {TILE_2BIT, TILE_2BIT, TILE_2BIT, TILE_2BIT}, // 0 + {TILE_4BIT, TILE_4BIT, TILE_2BIT, 0}, // 1 + {TILE_4BIT, TILE_4BIT, 0, 0}, // 2 + {TILE_8BIT, TILE_4BIT, 0, 0}, // 3 + {TILE_8BIT, TILE_2BIT, 0, 0}, // 4 + {TILE_4BIT, TILE_2BIT, 0, 0}, // 5 + {TILE_8BIT, 0, 0, 0}, // 6 + {0, 0, 0, 0} // 7 +}; +uint8 BGSizes [2] = { + 8, 16 +}; +uint32 DirectColourMaps [8][256]; + +long FilterValues[4][2] = +{ + {0, 0}, + {240, 0}, + {488, -240}, + {460, -208} +}; + +int NoiseFreq [32] = { + 0, 16, 21, 25, 31, 42, 50, 63, 84, 100, 125, 167, 200, 250, 333, + 400, 500, 667, 800, 1000, 1300, 1600, 2000, 2700, 3200, 4000, + 5300, 6400, 8000, 10700, 16000, 32000 +}; + +uint32 HeadMask [4] = { +#ifdef LSB_FIRST + 0xffffffff, 0xffffff00, 0xffff0000, 0xff000000 +#else + 0xffffffff, 0x00ffffff, 0x0000ffff, 0x000000ff +#endif +}; + +uint32 TailMask [5] = { +#ifdef LSB_FIRST + 0x00000000, 0x000000ff, 0x0000ffff, 0x00ffffff, 0xffffffff +#else + 0x00000000, 0xff000000, 0xffff0000, 0xffffff00, 0xffffffff +#endif +}; + +START_EXTERN_C +uint8 APUROM [64] = +{ + 0xCD,0xEF,0xBD,0xE8,0x00,0xC6,0x1D,0xD0,0xFC,0x8F,0xAA,0xF4,0x8F, + 0xBB,0xF5,0x78,0xCC,0xF4,0xD0,0xFB,0x2F,0x19,0xEB,0xF4,0xD0,0xFC, + 0x7E,0xF4,0xD0,0x0B,0xE4,0xF5,0xCB,0xF4,0xD7,0x00,0xFC,0xD0,0xF3, + 0xAB,0x01,0x10,0xEF,0x7E,0xF4,0x10,0xEB,0xBA,0xF6,0xDA,0x00,0xBA, + 0xF4,0xC4,0xF4,0xDD,0x5D,0xD0,0xDB,0x1F,0x00,0x00,0xC0,0xFF +}; + +#ifdef NETPLAY_SUPPORT +struct SNetPlay NetPlay; +#endif + +// Raw SPC700 instruction cycle lengths +int32 S9xAPUCycleLengths [256] = +{ + /* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f, */ + /* 00 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 5, 4, 5, 4, 6, 8, + /* 10 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 6, 5, 2, 2, 4, 6, + /* 20 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 5, 4, 5, 4, 5, 4, + /* 30 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 6, 5, 2, 2, 3, 8, + /* 40 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 4, 4, 5, 4, 6, 6, + /* 50 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 4, 5, 2, 2, 4, 3, + /* 60 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 4, 4, 5, 4, 5, 5, + /* 70 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 5, 5, 2, 2, 3, 6, + /* 80 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 5, 4, 5, 2, 4, 5, + /* 90 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 5, 5, 2, 2,12, 5, + /* a0 */ 3, 8, 4, 5, 3, 4, 3, 6, 2, 6, 4, 4, 5, 2, 4, 4, + /* b0 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 5, 5, 2, 2, 3, 4, + /* c0 */ 3, 8, 4, 5, 4, 5, 4, 7, 2, 5, 6, 4, 5, 2, 4, 9, + /* d0 */ 2, 8, 4, 5, 5, 6, 6, 7, 4, 5, 4, 5, 2, 2, 6, 3, + /* e0 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 4, 5, 3, 4, 3, 4, 3, + /* f0 */ 2, 8, 4, 5, 4, 5, 5, 6, 3, 4, 5, 4, 2, 2, 4, 3 +}; + +// Actual data used by CPU emulation, will be scaled by APUReset routine +// to be relative to the 65c816 instruction lengths. +int32 S9xAPUCycles [256] = +{ + /* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f, */ + /* 00 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 5, 4, 5, 4, 6, 8, + /* 10 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 6, 5, 2, 2, 4, 6, + /* 20 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 5, 4, 5, 4, 5, 4, + /* 30 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 6, 5, 2, 2, 3, 8, + /* 40 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 4, 4, 5, 4, 6, 6, + /* 50 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 4, 5, 2, 2, 4, 3, + /* 60 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 4, 4, 5, 4, 5, 5, + /* 70 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 5, 5, 2, 2, 3, 6, + /* 80 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 5, 4, 5, 2, 4, 5, + /* 90 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 5, 5, 2, 2,12, 5, + /* a0 */ 3, 8, 4, 5, 3, 4, 3, 6, 2, 6, 4, 4, 5, 2, 4, 4, + /* b0 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 5, 5, 2, 2, 3, 4, + /* c0 */ 3, 8, 4, 5, 4, 5, 4, 7, 2, 5, 6, 4, 5, 2, 4, 9, + /* d0 */ 2, 8, 4, 5, 5, 6, 6, 7, 4, 5, 4, 5, 2, 2, 6, 3, + /* e0 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 4, 5, 3, 4, 3, 4, 3, + /* f0 */ 2, 8, 4, 5, 4, 5, 5, 6, 3, 4, 5, 4, 2, 2, 4, 3 +}; + +#ifndef VAR_CYCLES +uint8 S9xE1M1X1 [256] = { + 8, 6, 8, 4, 5, 3, 5, 6, 3, 2, 2, 4, 6, 4, 6, 5, /* e=1, m=1, x=1 */ + 2, 5, 5, 7, 5, 4, 6, 6, 2, 4, 2, 2, 6, 4, 7, 5, + 6, 6, 8, 4, 3, 3, 5, 6, 4, 2, 2, 5, 4, 4, 6, 5, + 2, 5, 5, 7, 4, 4, 6, 6, 2, 4, 2, 2, 4, 4, 7, 5, + 7, 6, 2, 4, 0, 3, 5, 6, 3, 2, 2, 3, 3, 4, 6, 5, + 2, 5, 5, 7, 0, 4, 6, 6, 2, 4, 3, 2, 4, 4, 7, 5, + 6, 6, 6, 4, 3, 3, 5, 6, 4, 2, 2, 6, 5, 4, 6, 5, + 2, 5, 5, 7, 4, 4, 6, 6, 2, 4, 4, 2, 6, 4, 7, 5, + 2, 6, 3, 4, 3, 3, 3, 6, 2, 2, 2, 3, 4, 4, 4, 5, + 2, 5, 5, 7, 4, 4, 4, 6, 2, 4, 2, 2, 4, 4, 4, 5, + 2, 6, 2, 4, 3, 3, 3, 6, 2, 2, 2, 4, 4, 4, 4, 5, + 2, 5, 5, 7, 4, 4, 4, 6, 2, 4, 2, 2, 4, 4, 4, 5, + 2, 6, 3, 4, 3, 3, 5, 6, 2, 2, 2, 3, 4, 4, 6, 5, + 2, 5, 5, 7, 6, 4, 6, 6, 2, 4, 3, 3, 6, 4, 7, 5, + 2, 6, 3, 4, 3, 3, 5, 6, 2, 2, 2, 3, 4, 4, 6, 5, + 2, 5, 5, 7, 5, 4, 6, 6, 2, 4, 4, 2, 6, 4, 7, 5 +}; + +uint8 S9xE0M1X1 [256] = { + 8, 6, 8, 4, 5, 3, 5, 6, 3, 2, 2, 4, 6, 4, 6, 5, /* e=0, m=1, x=1 */ + 2, 5, 5, 7, 5, 4, 6, 6, 2, 4, 2, 2, 6, 4, 7, 5, + 6, 6, 8, 4, 3, 3, 5, 6, 4, 2, 2, 5, 4, 4, 6, 5, + 2, 5, 5, 7, 4, 4, 6, 6, 2, 4, 2, 2, 4, 4, 7, 5, + 7, 6, 2, 4, 0, 3, 5, 6, 3, 2, 2, 3, 3, 4, 6, 5, + 2, 5, 5, 7, 0, 4, 6, 6, 2, 4, 3, 2, 4, 4, 7, 5, + 6, 6, 6, 4, 3, 3, 5, 6, 4, 2, 2, 6, 5, 4, 6, 5, + 2, 5, 5, 7, 4, 4, 6, 6, 2, 4, 4, 2, 6, 4, 7, 5, + 2, 6, 3, 4, 3, 3, 3, 6, 2, 2, 2, 3, 4, 4, 4, 5, + 2, 5, 5, 7, 4, 4, 4, 6, 2, 4, 2, 2, 4, 4, 4, 5, + 2, 6, 2, 4, 3, 3, 3, 6, 2, 2, 2, 4, 4, 4, 4, 5, + 2, 5, 5, 7, 4, 4, 4, 6, 2, 4, 2, 2, 4, 4, 4, 5, + 2, 6, 3, 4, 3, 3, 5, 6, 2, 2, 2, 3, 4, 4, 6, 5, + 2, 5, 5, 7, 6, 4, 6, 6, 2, 4, 3, 3, 6, 4, 7, 5, + 2, 6, 3, 4, 3, 3, 5, 6, 2, 2, 2, 3, 4, 4, 6, 5, + 2, 5, 5, 7, 5, 4, 6, 6, 2, 4, 4, 2, 6, 4, 7, 5 +}; + +uint8 S9xE0M0X1 [256] = { + 8, 7, 8, 5, 7, 4, 7, 7, 3, 3, 2, 4, 8, 5, 8, 6, /* e=0, m=0, x=1 */ + 2, 6, 6, 8, 7, 5, 8, 7, 2, 5, 2, 2, 8, 5, 9, 6, + 6, 7, 8, 5, 4, 4, 7, 7, 4, 3, 2, 5, 5, 5, 8, 6, + 2, 6, 6, 8, 5, 5, 8, 7, 2, 5, 2, 2, 5, 5, 9, 6, + 7, 7, 2, 5, 0, 4, 7, 7, 4, 3, 2, 3, 3, 5, 8, 6, + 2, 6, 6, 8, 0, 5, 8, 7, 2, 5, 3, 2, 4, 5, 9, 6, + 6, 7, 6, 5, 4, 4, 7, 7, 5, 3, 2, 6, 5, 5, 8, 6, + 2, 6, 6, 8, 5, 5, 8, 7, 2, 5, 4, 2, 6, 5, 9, 6, + 2, 7, 3, 5, 3, 4, 3, 7, 2, 3, 2, 3, 4, 5, 4, 6, + 2, 6, 6, 8, 4, 5, 4, 7, 2, 5, 2, 2, 5, 5, 5, 6, + 2, 7, 2, 5, 3, 4, 3, 7, 2, 3, 2, 4, 4, 5, 4, 6, + 2, 6, 6, 8, 4, 5, 4, 7, 2, 5, 2, 2, 4, 5, 4, 6, + 2, 7, 3, 5, 3, 4, 7, 7, 2, 3, 2, 3, 4, 5, 8, 6, + 2, 6, 6, 8, 6, 5, 8, 7, 2, 5, 3, 3, 6, 5, 9, 6, + 2, 7, 3, 5, 3, 4, 7, 7, 2, 3, 2, 3, 4, 5, 8, 6, + 2, 6, 6, 8, 5, 5, 8, 7, 2, 5, 4, 2, 6, 5, 9, 6 +}; + +uint8 S9xE0M1X0 [256] = { + 8, 6, 8, 4, 5, 3, 5, 6, 3, 2, 2, 4, 6, 4, 6, 5, /* e=0, m=1, x=0 */ + 2, 6, 5, 7, 5, 4, 6, 6, 2, 5, 2, 2, 6, 5, 7, 5, + 6, 6, 8, 4, 3, 3, 5, 6, 4, 2, 2, 5, 4, 4, 6, 5, + 2, 6, 5, 7, 4, 4, 6, 6, 2, 5, 2, 2, 5, 5, 7, 5, + 7, 6, 2, 4, 0, 3, 5, 6, 4, 2, 2, 3, 3, 4, 6, 5, + 2, 6, 5, 7, 0, 4, 6, 6, 2, 5, 4, 2, 4, 5, 7, 5, + 6, 6, 6, 4, 3, 3, 5, 6, 5, 2, 2, 6, 5, 4, 6, 5, + 2, 6, 5, 7, 4, 4, 6, 6, 2, 5, 5, 2, 6, 5, 7, 5, + 2, 6, 3, 4, 4, 3, 4, 6, 2, 2, 2, 3, 5, 4, 5, 5, + 2, 6, 5, 7, 5, 4, 5, 6, 2, 5, 2, 2, 4, 5, 5, 5, + 3, 6, 3, 4, 4, 3, 4, 6, 2, 2, 2, 4, 5, 4, 5, 5, + 2, 6, 5, 7, 5, 4, 5, 6, 2, 5, 2, 2, 5, 5, 5, 5, + 3, 6, 3, 4, 4, 3, 6, 6, 2, 2, 2, 3, 5, 4, 6, 5, + 2, 6, 5, 7, 6, 4, 8, 6, 2, 5, 4, 3, 6, 5, 7, 5, + 3, 6, 3, 4, 4, 3, 6, 6, 2, 2, 2, 3, 5, 4, 6, 5, + 2, 6, 5, 7, 5, 4, 8, 6, 2, 5, 5, 2, 6, 5, 7, 5 +}; + +uint8 S9xE0M0X0 [256] = { + 8, 7, 8, 5, 7, 4, 7, 7, 3, 3, 2, 4, 8, 5, 8, 6, /* e=0, m=0, x=0 */ + 2, 7, 6, 8, 7, 5, 8, 7, 2, 6, 2, 2, 8, 6, 9, 6, + 6, 7, 8, 5, 4, 4, 7, 7, 4, 3, 2, 5, 5, 5, 8, 6, + 2, 7, 6, 8, 5, 5, 8, 7, 2, 6, 2, 2, 6, 6, 9, 6, + 7, 7, 2, 5, 0, 4, 7, 7, 3, 3, 2, 3, 3, 5, 8, 6, + 2, 7, 6, 8, 0, 5, 8, 7, 2, 6, 4, 2, 4, 6, 9, 6, + 6, 7, 6, 5, 4, 4, 7, 7, 4, 3, 2, 6, 5, 5, 8, 6, + 2, 7, 6, 8, 5, 5, 8, 7, 2, 6, 5, 2, 6, 6, 9, 6, + 2, 7, 3, 5, 4, 4, 4, 7, 2, 3, 2, 3, 5, 5, 5, 6, + 2, 7, 6, 8, 5, 5, 5, 7, 2, 6, 2, 2, 5, 6, 6, 6, + 3, 7, 3, 5, 4, 4, 4, 7, 2, 3, 2, 4, 5, 5, 5, 6, + 2, 7, 6, 8, 5, 5, 5, 7, 2, 6, 2, 2, 5, 6, 5, 6, + 3, 7, 3, 5, 4, 4, 7, 7, 2, 3, 2, 3, 5, 5, 8, 6, + 2, 7, 6, 8, 6, 5, 8, 7, 2, 6, 4, 3, 6, 6, 9, 6, + 3, 7, 3, 5, 4, 4, 7, 7, 2, 3, 2, 3, 5, 5, 8, 6, + 2, 7, 6, 8, 5, 5, 8, 7, 2, 6, 5, 2, 6, 6, 9, 6 +}; +#endif + +END_EXTERN_C diff --git a/src/gp2x_highlightbar.c b/src/gp2x_highlightbar.c new file mode 100644 index 0000000..5ef8da8 --- /dev/null +++ b/src/gp2x_highlightbar.c @@ -0,0 +1,341 @@ +///////////////////////////////////////// +// +// Header file for GP32 +// +// convertion of highlightbar.bmp file : +// Width = 16 +// Heigth = 320 +// GP32 Mode = 16 Bits per Pixel +// +// with GP32Converter coded by Edorul : +// http://www.ifrance.com/edorul/ +// edorul@free.fr +// +///////////////////////////////////////// + +#define highlightbar_width 320 +#define highlightbar_height 16 +unsigned short highLightBar[5120]; +unsigned short highLightBarOrig[5120] = { + 0xFFCA, 0xFFCA, 0xFFCA, 0xFFCC, 0xFFCC, 0xFFCC, 0xFFCC, 0xFFCC, 0xFFCC, 0xFFCC, 0xFF8C, 0xFF8C, 0xFF8C, 0xFF8C, 0xFF8C, 0xFF8C, + 0xFF8C, 0xFF8C, 0xFF4C, 0xFF4C, 0xFF4C, 0xFF4E, 0xFF4E, 0xFF4E, 0xFF4E, 0xFF4E, 0xFF4E, 0xFF0E, 0xFF0E, 0xFF0E, 0xFF0E, 0xFF0E, + 0xFF0E, 0xFF0E, 0xFF0E, 0xFF0E, 0xFF0E, 0xFECE, 0xFECE, 0xFED0, 0xFED0, 0xFED0, 0xFED0, 0xFED0, 0xFED0, 0xFED0, 0xFE90, 0xFE90, + 0xFE90, 0xFE90, 0xFE90, 0xFE90, 0xFE90, 0xFE90, 0xFE90, 0xFE50, 0xFE50, 0xFE52, 0xFE52, 0xFE52, 0xFE52, 0xFE52, 0xFE52, 0xFE52, + 0xFE12, 0xFE12, 0xFE12, 0xFE12, 0xFE12, 0xFE12, 0xFE12, 0xFE12, 0xFE12, 0xFE14, 0xFDD4, 0xFDD4, 0xFDD4, 0xFDD4, 0xFDD4, 0xFDD4, + 0xFDD4, 0xFDD4, 0xFDD4, 0xFD94, 0xFD94, 0xFD94, 0xFD94, 0xFD94, 0xFD94, 0xFD94, 0xFD94, 0xFD96, 0xFD56, 0xFD56, 0xFD56, 0xFD56, + 0xFD56, 0xFD56, 0xFD56, 0xFD56, 0xFD56, 0xFD16, 0xFD16, 0xFD16, 0xFD16, 0xFD16, 0xFD16, 0xFD16, 0xFD16, 0xFD18, 0xFD18, 0xFCD8, + 0xFCD8, 0xFCD8, 0xFCD8, 0xFCD8, 0xFCD8, 0xFCD8, 0xFCD8, 0xFCD8, 0xFC98, 0xFC98, 0xFC96, 0xFC96, 0xFC96, 0xFC96, 0xFC96, 0xFC96, + 0xFC56, 0xFC56, 0xFC56, 0xFC56, 0xFC56, 0xFC56, 0xFC56, 0xFC56, 0xFC16, 0xFC16, 0xFC16, 0xFC16, 0xFC14, 0xFC14, 0xFC14, 0xFC14, + 0xFC14, 0xFBD4, 0xFBD4, 0xFBD4, 0xFBD4, 0xFBD4, 0xFBD4, 0xFBD4, 0xFBD4, 0xFB94, 0xFB94, 0xFB94, 0xFB94, 0xFB94, 0xFB92, 0xFB92, + 0xFB92, 0xFB92, 0xFB52, 0xFB52, 0xFB52, 0xFB52, 0xFB52, 0xFB52, 0xFB52, 0xFB52, 0xFB12, 0xFB12, 0xFB12, 0xFB12, 0xFB10, 0xFB10, + 0xFB10, 0xFB10, 0xFAD0, 0xFAD0, 0xFAD0, 0xFAD0, 0xFAD0, 0xFAD0, 0xFAD0, 0xFAD0, 0xFAD0, 0xFA90, 0xFA90, 0xFA90, 0xFA90, 0xFA90, + 0xFA8E, 0xFA8E, 0xFA8E, 0xFA8E, 0xFA4E, 0xFA4E, 0xFA4E, 0xFA4E, 0xFA4E, 0xFA4E, 0xFA4E, 0xFA4E, 0xFA0E, 0xFA0E, 0xFA0E, 0xFA0E, + 0xFA0E, 0xFA0E, 0xFA0C, 0xFA0C, 0xF9CC, 0xF9CC, 0xF9CC, 0xF9CC, 0xF9CC, 0xF9CC, 0xF9CC, 0xF9CC, 0xF9CC, 0xF98C, 0xF98C, 0xF98C, + 0xF98C, 0xF98C, 0xF98C, 0xF98C, 0xF98A, 0xF98A, 0xF94A, 0xF94A, 0xF94A, 0xF94A, 0xF94A, 0xF94A, 0xF94A, 0xF94A, 0xF14A, 0xF14A, + 0xF14A, 0xF14A, 0xF14A, 0xF14A, 0xF14A, 0xF14A, 0xE94A, 0xE94A, 0xE94A, 0xE94A, 0xE94A, 0xE94A, 0xE94A, 0xE94A, 0xE14A, 0xE14A, + 0xE14A, 0xE14A, 0xE14A, 0xE14A, 0xE14A, 0xE14A, 0xD94A, 0xD94A, 0xD94A, 0xD94A, 0xD94A, 0xD94A, 0xD94A, 0xD14A, 0xD14A, 0xD14A, + 0xD14A, 0xD14A, 0xD14A, 0xD14A, 0xD14A, 0xC94A, 0xC94A, 0xC94A, 0xC94A, 0xC94A, 0xC94A, 0xC94A, 0xC94A, 0xC14A, 0xC14A, 0xC14A, + 0xC14A, 0xC14A, 0xC14A, 0xC14A, 0xC14A, 0xC14A, 0xB94A, 0xB94A, 0xB94A, 0xB94A, 0xB94A, 0xB94A, 0xB94A, 0xB94A, 0xB94A, 0xB14A, + 0xB14A, 0xB14A, 0xB14A, 0xB14A, 0xB14A, 0xB14A, 0xB14A, 0xB14A, 0xA94A, 0xA94A, 0xA94A, 0xA94A, 0xA94A, 0xA94A, 0xA94A, 0xA94A, + 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF82, 0xFF42, + 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF04, 0xFF04, 0xFEC4, 0xFEC4, + 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE86, 0xFE86, 0xFE46, 0xFE46, 0xFE46, + 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE06, 0xFE06, 0xFE06, 0xFE06, 0xFE08, 0xFE08, 0xFE08, 0xFE08, 0xFDC8, 0xFDC8, 0xFDC8, + 0xFDC8, 0xFDC8, 0xFDC8, 0xFDC8, 0xFD88, 0xFD88, 0xFD88, 0xFD88, 0xFD8A, 0xFD8A, 0xFD8A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, + 0xFD4A, 0xFD4A, 0xFD4A, 0xFD0A, 0xFD0A, 0xFD0A, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, + 0xFCCC, 0xFCCC, 0xFC8C, 0xFC8C, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, + 0xFC4E, 0xFC0E, 0xFC0E, 0xFC10, 0xFC10, 0xFC0E, 0xFC0E, 0xFC0E, 0xFC0E, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFB8E, + 0xFB8E, 0xFB8E, 0xFB8E, 0xFB8C, 0xFB8C, 0xFB8C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB0C, 0xFB0C, 0xFB0C, + 0xFB0C, 0xFB0A, 0xFB0A, 0xFB0A, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, + 0xFA88, 0xFA88, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA06, 0xFA06, + 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF984, 0xF944, 0xF944, + 0xF944, 0xF944, 0xF944, 0xF944, 0xF944, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF902, 0xF8C2, 0xF8C2, 0xF8C2, 0xF8C2, + 0xF8C2, 0xF8C2, 0xF8C2, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, + 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF000, 0xF000, 0xF000, + 0xF000, 0xF000, 0xF000, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, + 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xC800, 0xC800, 0xC800, + 0xC800, 0xC800, 0xC800, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, + 0xB800, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA000, + 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9000, 0x9000, + 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF82, 0xFF42, + 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF04, 0xFF04, 0xFEC4, 0xFEC4, + 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE86, 0xFE86, 0xFE46, 0xFE46, 0xFE46, + 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE06, 0xFE06, 0xFE06, 0xFE06, 0xFE08, 0xFE08, 0xFE08, 0xFE08, 0xFDC8, 0xFDC8, 0xFDC8, + 0xFDC8, 0xFDC8, 0xFDC8, 0xFDC8, 0xFD88, 0xFD88, 0xFD88, 0xFD88, 0xFD8A, 0xFD8A, 0xFD8A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, + 0xFD4A, 0xFD4A, 0xFD4A, 0xFD0A, 0xFD0A, 0xFD0A, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, + 0xFCCC, 0xFCCC, 0xFC8C, 0xFC8C, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, + 0xFC4E, 0xFC0E, 0xFC0E, 0xFC10, 0xFC10, 0xFC0E, 0xFC0E, 0xFC0E, 0xFC0E, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFB8E, + 0xFB8E, 0xFB8E, 0xFB8E, 0xFB8C, 0xFB8C, 0xFB8C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB0C, 0xFB0C, 0xFB0C, + 0xFB0C, 0xFB0A, 0xFB0A, 0xFB0A, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, + 0xFA88, 0xFA88, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA06, 0xFA06, + 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF984, 0xF944, 0xF944, + 0xF944, 0xF944, 0xF944, 0xF944, 0xF944, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF902, 0xF8C2, 0xF8C2, 0xF8C2, 0xF8C2, + 0xF8C2, 0xF8C2, 0xF8C2, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, + 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF000, 0xF000, 0xF000, + 0xF000, 0xF000, 0xF000, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, + 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xC800, 0xC800, 0xC800, + 0xC800, 0xC800, 0xC800, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, + 0xB800, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA000, + 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9000, 0x9000, + 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF82, 0xFF42, + 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF04, 0xFF04, 0xFEC4, 0xFEC4, + 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE86, 0xFE86, 0xFE46, 0xFE46, 0xFE46, + 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE06, 0xFE06, 0xFE06, 0xFE06, 0xFE08, 0xFE08, 0xFE08, 0xFE08, 0xFDC8, 0xFDC8, 0xFDC8, + 0xFDC8, 0xFDC8, 0xFDC8, 0xFDC8, 0xFD88, 0xFD88, 0xFD88, 0xFD88, 0xFD8A, 0xFD8A, 0xFD8A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, + 0xFD4A, 0xFD4A, 0xFD4A, 0xFD0A, 0xFD0A, 0xFD0A, 0xFD0C, 0xFD0C, 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0xF800, 0xF800, 0xF800, 0xF000, 0xF000, 0xF000, + 0xF000, 0xF000, 0xF000, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, + 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xC800, 0xC800, 0xC800, + 0xC800, 0xC800, 0xC800, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, + 0xB800, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA000, + 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9000, 0x9000, + 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF82, 0xFF42, + 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF04, 0xFF04, 0xFEC4, 0xFEC4, + 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE86, 0xFE86, 0xFE46, 0xFE46, 0xFE46, + 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE06, 0xFE06, 0xFE06, 0xFE06, 0xFE08, 0xFE08, 0xFE08, 0xFE08, 0xFDC8, 0xFDC8, 0xFDC8, + 0xFDC8, 0xFDC8, 0xFDC8, 0xFDC8, 0xFD88, 0xFD88, 0xFD88, 0xFD88, 0xFD8A, 0xFD8A, 0xFD8A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, + 0xFD4A, 0xFD4A, 0xFD4A, 0xFD0A, 0xFD0A, 0xFD0A, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, + 0xFCCC, 0xFCCC, 0xFC8C, 0xFC8C, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, + 0xFC4E, 0xFC0E, 0xFC0E, 0xFC10, 0xFC10, 0xFC0E, 0xFC0E, 0xFC0E, 0xFC0E, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFB8E, + 0xFB8E, 0xFB8E, 0xFB8E, 0xFB8C, 0xFB8C, 0xFB8C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB0C, 0xFB0C, 0xFB0C, + 0xFB0C, 0xFB0A, 0xFB0A, 0xFB0A, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, + 0xFA88, 0xFA88, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA06, 0xFA06, + 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF984, 0xF944, 0xF944, + 0xF944, 0xF944, 0xF944, 0xF944, 0xF944, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF902, 0xF8C2, 0xF8C2, 0xF8C2, 0xF8C2, + 0xF8C2, 0xF8C2, 0xF8C2, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, + 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF000, 0xF000, 0xF000, + 0xF000, 0xF000, 0xF000, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, + 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xC800, 0xC800, 0xC800, + 0xC800, 0xC800, 0xC800, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, + 0xB800, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA000, + 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9000, 0x9000, + 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF82, 0xFF42, + 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF04, 0xFF04, 0xFEC4, 0xFEC4, + 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE86, 0xFE86, 0xFE46, 0xFE46, 0xFE46, + 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE06, 0xFE06, 0xFE06, 0xFE06, 0xFE08, 0xFE08, 0xFE08, 0xFE08, 0xFDC8, 0xFDC8, 0xFDC8, + 0xFDC8, 0xFDC8, 0xFDC8, 0xFDC8, 0xFD88, 0xFD88, 0xFD88, 0xFD88, 0xFD8A, 0xFD8A, 0xFD8A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, + 0xFD4A, 0xFD4A, 0xFD4A, 0xFD0A, 0xFD0A, 0xFD0A, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, + 0xFCCC, 0xFCCC, 0xFC8C, 0xFC8C, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, + 0xFC4E, 0xFC0E, 0xFC0E, 0xFC10, 0xFC10, 0xFC0E, 0xFC0E, 0xFC0E, 0xFC0E, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFB8E, + 0xFB8E, 0xFB8E, 0xFB8E, 0xFB8C, 0xFB8C, 0xFB8C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB0C, 0xFB0C, 0xFB0C, + 0xFB0C, 0xFB0A, 0xFB0A, 0xFB0A, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, + 0xFA88, 0xFA88, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA06, 0xFA06, + 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF984, 0xF944, 0xF944, + 0xF944, 0xF944, 0xF944, 0xF944, 0xF944, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF902, 0xF8C2, 0xF8C2, 0xF8C2, 0xF8C2, + 0xF8C2, 0xF8C2, 0xF8C2, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, + 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF000, 0xF000, 0xF000, + 0xF000, 0xF000, 0xF000, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, + 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xC800, 0xC800, 0xC800, + 0xC800, 0xC800, 0xC800, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, + 0xB800, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA000, + 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9000, 0x9000, + 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFFC0, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF80, 0xFF82, 0xFF42, + 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF42, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF02, 0xFF04, 0xFF04, 0xFEC4, 0xFEC4, + 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFEC4, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE84, 0xFE86, 0xFE86, 0xFE46, 0xFE46, 0xFE46, + 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE46, 0xFE06, 0xFE06, 0xFE06, 0xFE06, 0xFE08, 0xFE08, 0xFE08, 0xFE08, 0xFDC8, 0xFDC8, 0xFDC8, + 0xFDC8, 0xFDC8, 0xFDC8, 0xFDC8, 0xFD88, 0xFD88, 0xFD88, 0xFD88, 0xFD8A, 0xFD8A, 0xFD8A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, 0xFD4A, + 0xFD4A, 0xFD4A, 0xFD4A, 0xFD0A, 0xFD0A, 0xFD0A, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFD0C, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, 0xFCCC, + 0xFCCC, 0xFCCC, 0xFC8C, 0xFC8C, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC8E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, 0xFC4E, + 0xFC4E, 0xFC0E, 0xFC0E, 0xFC10, 0xFC10, 0xFC0E, 0xFC0E, 0xFC0E, 0xFC0E, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFBCE, 0xFB8E, + 0xFB8E, 0xFB8E, 0xFB8E, 0xFB8C, 0xFB8C, 0xFB8C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB4C, 0xFB0C, 0xFB0C, 0xFB0C, + 0xFB0C, 0xFB0A, 0xFB0A, 0xFB0A, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFACA, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, 0xFA8A, + 0xFA88, 0xFA88, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA48, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA08, 0xFA06, 0xFA06, + 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF9C6, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF986, 0xF984, 0xF944, 0xF944, + 0xF944, 0xF944, 0xF944, 0xF944, 0xF944, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF904, 0xF902, 0xF8C2, 0xF8C2, 0xF8C2, 0xF8C2, + 0xF8C2, 0xF8C2, 0xF8C2, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF882, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, 0xF840, + 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF800, 0xF000, 0xF000, 0xF000, + 0xF000, 0xF000, 0xF000, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE800, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, 0xE000, + 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD800, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xC800, 0xC800, 0xC800, + 0xC800, 0xC800, 0xC800, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, + 0xB800, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA000, + 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9000, 0x9000, + 0xD680, 0xD680, 0xD640, 0xD640, 0xD640, 0xD640, 0xD640, 0xD640, 0xD640, 0xD640, 0xD640, 0xD600, 0xD600, 0xD600, 0xD600, 0xD600, + 0xD600, 0xD600, 0xD602, 0xD602, 0xD602, 0xD5C2, 0xD5C2, 0xD5C2, 0xD5C2, 0xD5C2, 0xD5C2, 0xD5C2, 0xD5C2, 0xD5C2, 0xD582, 0xD582, + 0xD582, 0xD582, 0xD584, 0xD584, 0xD584, 0xD584, 0xD584, 0xD544, 0xD544, 0xD544, 0xD544, 0xD544, 0xD544, 0xD544, 0xD544, 0xD544, + 0xD504, 0xD504, 0xD504, 0xD504, 0xD506, 0xD506, 0xD506, 0xD506, 0xD506, 0xD506, 0xD4C6, 0xD4C6, 0xD4C6, 0xD4C6, 0xD4C6, 0xD4C6, + 0xD4C6, 0xD4C6, 0xD4C6, 0xD486, 0xD486, 0xD486, 0xD488, 0xD488, 0xD488, 0xD488, 0xD488, 0xD448, 0xD448, 0xD448, 0xD448, 0xD448, + 0xD448, 0xD448, 0xD448, 0xD448, 0xD448, 0xD408, 0xD408, 0xD408, 0xD40A, 0xD40A, 0xD40A, 0xD40A, 0xD40A, 0xD40A, 0xD3CA, 0xD3CA, + 0xD3CA, 0xD3CA, 0xD3CA, 0xD3CA, 0xD3CA, 0xD3CA, 0xD3CA, 0xD3CA, 0xD38C, 0xD38C, 0xD38C, 0xD38C, 0xD38C, 0xD38C, 0xD38C, 0xD38C, + 0xD38C, 0xD34C, 0xD34C, 0xD34C, 0xD34C, 0xD34C, 0xD34C, 0xD34C, 0xD34C, 0xD34C, 0xD30C, 0xD30C, 0xD30C, 0xD30C, 0xD30C, 0xD30A, + 0xD30A, 0xD30A, 0xD2CA, 0xD2CA, 0xD2CA, 0xD2CA, 0xD2CA, 0xD2CA, 0xD2CA, 0xD2CA, 0xD2CA, 0xD28A, 0xD28A, 0xD28A, 0xD28A, 0xD28A, + 0xD288, 0xD288, 0xD288, 0xD248, 0xD248, 0xD248, 0xD248, 0xD248, 0xD248, 0xD248, 0xD248, 0xD208, 0xD208, 0xD208, 0xD208, 0xD208, + 0xD208, 0xD208, 0xD206, 0xD206, 0xD1C6, 0xD1C6, 0xD1C6, 0xD1C6, 0xD1C6, 0xD1C6, 0xD1C6, 0xD1C6, 0xD186, 0xD186, 0xD186, 0xD186, + 0xD186, 0xD186, 0xD186, 0xD186, 0xD184, 0xD144, 0xD144, 0xD144, 0xD144, 0xD144, 0xD144, 0xD144, 0xD144, 0xD104, 0xD104, 0xD104, + 0xD104, 0xD104, 0xD104, 0xD104, 0xD104, 0xD104, 0xD0C2, 0xD0C2, 0xD0C2, 0xD0C2, 0xD0C2, 0xD0C2, 0xD0C2, 0xD0C2, 0xD082, 0xD082, + 0xD082, 0xD082, 0xD082, 0xD082, 0xD082, 0xD082, 0xD080, 0xD040, 0xD040, 0xD040, 0xD040, 0xD040, 0xD040, 0xD040, 0xD040, 0xD000, + 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xD000, 0xC800, 0xC800, 0xC800, 0xC800, 0xC800, 0xC800, 0xC800, 0xC800, + 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xC000, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, 0xB800, + 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xB000, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA800, 0xA000, + 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0xA000, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, 0x9800, + 0x9000, 0x9000, 0x9000, 0x9000, 0x9000, 0x9000, 0x9000, 0x9000, 0x8800, 0x8800, 0x8800, 0x8800, 0x8800, 0x8800, 0x8800, 0x8800, + 0x8800, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x7800, 0x7800, 0x7800, 0x7800, 0x7800 + +}; diff --git a/src/gp2x_menu_header.c b/src/gp2x_menu_header.c new file mode 100644 index 0000000..cd2a6cb --- /dev/null +++ b/src/gp2x_menu_header.c @@ -0,0 +1,983 @@ +///////////////////////////////////////// +// +// Header file for GP32 +// +// convertion of menu_header.bmp file : +// Width = 320 +// Heigth = 48 +// GP32 Mode = 16 Bits per Pixel +// +// with GP32Converter coded by Edorul : +// http://www.ifrance.com/edorul/ +// edorul@free.fr +// +///////////////////////////////////////// + +#define menu_header_width 320 +#define menu_header_height 48 +unsigned short menuHeader[15360]; +unsigned short menuHeaderOrig[15360] = { + 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, + 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 0x2124, 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16 Bits per Pixel +// +// with GP32Converter coded by Edorul : +// http://www.ifrance.com/edorul/ +// edorul@free.fr +// +///////////////////////////////////////// + +#define menutile_width 64 +#define menutile_height 64 +unsigned short menuTile[4096]; +unsigned short menuTileOrig[4096] = { + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 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fb_size=(320*240*2)+(16*2); +static int mmuHackStatus=0; + +//unsigned long gp2x_ticks_per_second=7372800/1000; +unsigned long gp2x_dev[5]={0,0,0,0,0}; +unsigned long gp2x_physvram[4]={0,0,0,0}; + +unsigned short *framebuffer16[4]={0,0,0,0}; +static unsigned short *framebuffer_mmap[4]={0,0,0,0}; +unsigned short *gp2x_logvram15[2], gp2x_sound_buffer[4+((44100*2)*8)]; //*2=stereo, *4=max buffers +volatile unsigned short *gp2x_memregs; +volatile unsigned long *gp2x_memregl; +volatile unsigned long *gp2x_blitter = NULL; +unsigned int *gp2x_intVectors; +unsigned char *framebuffer8[4], *gp2x_screen8prev, *gp2x_logvram8[2]; + +volatile short *pOutput[8]; +int InitFramebuffer=0; +int Timer=0; +volatile int SoundThreadFlag=0; +volatile int CurrentSoundBank=0; +int CurrentFrameBuffer=0; +int CurrentFrag=0; +unsigned int ExistingIntHandler; + +// 1024x8 8x8 font, i love it :) +const unsigned int font8x8[]= {0x0,0x0,0xc3663c18,0x3c2424e7,0xe724243c,0x183c66c3,0xc16f3818,0x18386fc1,0x83f61c18,0x181cf683,0xe7c3993c,0x3c99c3,0x3f7fffff,0xe7cf9f,0x3c99c3e7,0xe7c399,0x3160c080,0x40e1b,0xcbcbc37e,0x7ec3c3db,0x3c3c3c18,0x81c087e,0x8683818,0x60f0e08,0x81422418,0x18244281,0xbd5a2418,0x18245abd,0x818181ff,0xff8181,0xa1c181ff,0xff8995,0x63633e,0x3e6363,0x606060,0x606060,0x3e60603e,0x3e0303,0x3e60603e,0x3e6060,0x3e636363,0x606060,0x3e03033e,0x3e6060,0x3e03033e,0x3e6363,0x60603e,0x606060,0x3e63633e,0x3e6363,0x3e63633e,0x3e6060,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x18181818,0x180018,0x666666,0x0,0x367f3600,0x367f36,0x3c067c18,0x183e60,0x18366600,0x62660c,0xe1c361c,0x6e337b,0x181818,0x0,0x18183870,0x703818,0x18181c0e,0xe1c18,0xff3c6600,0x663c,0x7e181800,0x1818,0x0,0x60c0c00,0x7e000000,0x0,0x0,0x181800,0x18306040,0x2060c,0x6e76663c,0x3c6666,0x18181c18,0x7e1818,0x3060663c,0x7e0c18,0x3018307e,0x3c6660,0x363c3830,0x30307e,0x603e067e,0x3c6660,0x3e06063c,0x3c6666,0x1830607e,0xc0c0c,0x3c66663c,0x3c6666,0x7c66663c,0x1c3060,0x181800,0x1818,0x181800,0xc1818,0xc183060,0x603018,0x7e0000,0x7e00,0x30180c06,0x60c18,0x3060663c,0x180018,0x5676663c,0x7c0676,0x66663c18,0x66667e,0x3e66663e,0x3e6666,0x606663c,0x3c6606,0x6666361e,0x1e3666,0x3e06067e,0x7e0606,0x3e06067e,0x60606,0x7606067c,0x7c6666,0x7e666666,0x666666,0x1818183c,0x3c1818,0x60606060,0x3c6660,0xe1e3666,0x66361e,0x6060606,0x7e0606,0x6b7f7763,0x636363,0x7e7e6e66,0x666676,0x6666663c,0x3c6666,0x3e66663e,0x60606,0x6666663c,0x6c366e,0x3e66663e,0x666636,0x3c06663c,0x3c6660,0x1818187e,0x181818,0x66666666,0x7c6666,0x66666666,0x183c66,0x6b636363,0x63777f,0x183c6666,0x66663c,0x3c666666,0x181818,0x1830607e,0x7e060c,0x18181878,0x781818,0x180c0602,0x406030,0x1818181e,0x1e1818,0x63361c08,0x0,0x0,0x7f0000,0xc060300,0x0,0x603c0000,0x7c667c,0x663e0606,0x3e6666,0x63c0000,0x3c0606,0x667c6060,0x7c6666,0x663c0000,0x3c067e,0xc3e0c38,0xc0c0c,0x667c0000,0x3e607c66,0x663e0606,0x666666,0x181c0018,0x3c1818,0x18180018,0xe181818,0x36660606,0x66361e,0x1818181c,0x3c1818,0x7f370000,0x63636b,0x663e0000,0x666666,0x663c0000,0x3c6666,0x663e0000,0x63e6666,0x667c0000,0x607c6666,0x663e0000,0x60606,0x67c0000,0x3e603c,0x187e1800,0x701818,0x66660000,0x7c6666,0x66660000,0x183c66,0x63630000,0x363e6b,0x3c660000,0x663c18,0x66660000,0x3e607c66,0x307e0000,0x7e0c18,0xc181870,0x701818,0x18181818,0x18181818,0x3018180e,0xe1818,0x794f0600,0x30}; + +pthread_t gp2x_sound_thread=0, gp2x_sound_thread_exit=0; +struct fb_fix_screeninfo fb0_fixed_info; +struct fb_fix_screeninfo fb1_fixed_info; + +int altVolumeCtrl = 0; + +/* +######################## +Graphics functions +######################## + */ + +static void debug(char *text, int pause) +{ + unsigned short bppmode; + bppmode=gp2x_memregs[0x28DA>>1]; + bppmode>>=9; + bppmode<<=3; + + if(bppmode==8) + { + gp_clearFramebuffer8(framebuffer8[currFB],0); + gp_drawString(0,0,strlen(text),text,0x51,framebuffer16[currFB]); + } + else + { + gp_clearFramebuffer8(framebuffer16[currFB],0); + gp_drawString(0,0,strlen(text),text,(unsigned short)MENU_RGB(31,31,31),framebuffer16[currFB]); + } + MenuFlip(); + if(pause) MenuPause(); + +} + +static int clipping_x1 = 0; +static int clipping_x2 = 319; +static int clipping_y1 = 0; +static int clipping_y2 = 239; + +void gp_setClipping(int x1, int y1, int x2, int y2) { + if (x1 < 0) x1 = 0; + if (x1 > 319) x1 = 319; + if (x2 < 0) x2 = 0; + if (x2 > 319) x2 = 319; + if (y1 < 0) y1 = 0; + if (y1 > 239) y1 = 239; + if (y2 < 0) y2 = 0; + if (y2 > 239) y2 = 239; + + if (x1 < x2) { + clipping_x1 = x1; + clipping_x2 = x2; + } else { + clipping_x2 = x1; + clipping_x1 = x2; + } + + if (y1 < y2) { + clipping_y1 = y1; + clipping_y2 = y2; + } else { + clipping_y2 = y1; + clipping_y1 = y2; + } +} + +static __inline__ +void gp_drawPixel8 ( int x, int y, unsigned char c, unsigned char *framebuffer ) +{ + if ((x < clipping_x1) || (x > clipping_x2) || (y < clipping_y1) || (y > clipping_y2)) return; + *(framebuffer +(320*y)+x ) = c; +} + +static __inline__ +void gp_drawPixel16 ( int x, int y, unsigned short c, unsigned short *framebuffer ) +{ + if ((x < clipping_x1) || (x > clipping_x2) || (y < clipping_y1) || (y > clipping_y2)) return; + *(framebuffer +(320*y)+x ) = c; +} + +static +void set_char8x8_16bpp (int xx,int yy,int offset,unsigned short mode,unsigned short *framebuffer) +{ + unsigned int y, pixel; + offset *= 2; + pixel = font8x8[0 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y, mode, framebuffer); + } + pixel = font8x8[1 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y+4, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y+4, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y+4, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y+4, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y+4, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y+4, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y+4, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y+4, mode, framebuffer); + + } +} + +static +void set_char8x8_8bpp (int xx,int yy,int offset,unsigned char mode,unsigned char *framebuffer) +{ + unsigned int y, pixel; + offset *= 2; + pixel = font8x8[0 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel8(xx+0, yy+y, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel8(xx+1, yy+y, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel8(xx+2, yy+y, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel8(xx+3, yy+y, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel8(xx+4, yy+y, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel8(xx+5, yy+y, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel8(xx+6, yy+y, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel8(xx+7, yy+y, mode, framebuffer); + } + pixel = font8x8[1 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel8(xx+0, yy+y+4, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel8(xx+1, yy+y+4, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel8(xx+2, yy+y+4, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel8(xx+3, yy+y+4, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel8(xx+4, yy+y+4, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel8(xx+5, yy+y+4, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel8(xx+6, yy+y+4, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel8(xx+7, yy+y+4, mode, framebuffer); + + } +} + +void gp_drawString (int x,int y,int len,char *buffer,unsigned short color,void *framebuffer) +{ + int l,base=0; + unsigned short bppmode; + bppmode=gp2x_memregs[0x28DA>>1]; + bppmode>>=9; + bppmode<<=3; + + for (l=0;l>1]; + bppmode>>=9; + bppmode<<=3; + if(bppmode==8) gp_clearFramebuffer8((unsigned char*)framebuffer,(unsigned char)pal); + else gp_clearFramebuffer16((unsigned short*)framebuffer,(unsigned short)pal); +} + + + + +unsigned int gp_getButton(unsigned char enable_diagnals) +{ + unsigned int value=(gp2x_memregs[0x1198>>1] & 0x00FF); + //gp2x_memregs[0x1198>>1] + /* + 0x1FE = UP 1 1111 1110 + 0x17E 1 0111 1110 + 0x17F 1 0111 1111 + 0X13F 1 0011 1111 + 0x1BF = RIGHT 1 1011 1111 + 0X19F 1 1001 1111 + 0X1DF 1 1101 1111 + 0X1CF 1 1100 1111 + 0x1EF = DOWN 1 1110 1111 + 0x1E7 1 1110 0111 + 0x1F7 1 1111 0111 + 0x1F3 1 1111 0011 + 0x1FB = LEFT 1 1111 1011 + 0x1F9 1 1111 1001 + 0x1FD 1 1111 1101 + 0x1FC 1 1111 1100 + + */ + switch(value) + { + //UP + case 0x7E: + case 0xFC: + value = 0xFE; + break; + + //RIGHT + case 0x3F: + case 0x9F: + value = 0xBF; + break; + + //DOWN + case 0xCF: + case 0xE7: + value = 0xEF; + break; + + //LEFT + case 0xF3: + case 0xF9: + value = 0xFB; + break; + } + + if (enable_diagnals) + { + + if(value==0xFD) value=0xFA; + if(value==0xF7) value=0xEB; + if(value==0xDF) value=0xAF; + if(value==0x7F) value=0xBE; + } + + + return ~((gp2x_memregs[0x1184>>1] & 0xFF00) | value | (gp2x_memregs[0x1186>>1] << 16)); +} + +void gp_initGraphics(unsigned short bpp, int flip, int applyMmuHack) +{ + + int x = 0; + unsigned int key = 0; + unsigned int offset = 0; + char buf[256]; + + +#ifdef DEBUG + printf("Entering gp_initGraphics....\r\n"); +#endif + /* + First check that frame buffer memory has not already been setup + */ + if (!InitFramebuffer) + { +#ifdef DEBUG + sprintf(buf, "Initing buffer\r\n"); + printf(buf); +#endif + gp2x_dev[0] = open("/dev/fb0", O_RDWR); + gp2x_dev[1] = open("/dev/fb1", O_RDWR); + gp2x_dev[2] = open("/dev/mem", O_RDWR); + +#ifdef DEBUG + sprintf(buf, "Devices opened\r\n"); + printf(buf); + sprintf(buf, "/dev/fb0: %x \r\n", gp2x_dev[0]); + printf(buf); + sprintf(buf, "/dev/fb1: %x \r\n", gp2x_dev[1]); + printf(buf); + sprintf(buf, "/dev/mem: %x \r\n", gp2x_dev[2]); + printf(buf); +#endif + + gp2x_memregs=(unsigned short *)mmap(0, 0x10000, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], 0xc0000000); + gp2x_memregl=(unsigned long *)gp2x_memregs; + if (!gp2x_blitter) gp2x_blitter=(unsigned long *)mmap(0, 0x100, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], 0xe0020000); + + if (!framebuffer_mmap[0]) framebuffer_mmap[0]=(void *)mmap(0, fb_size, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], (gp2x_physvram[0]=0x04000000-(0x26000*4) )); + if (!framebuffer_mmap[1]) framebuffer_mmap[1]=(void *)mmap(0, fb_size, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], (gp2x_physvram[1]=0x04000000-(0x26000*3) )); + if (!framebuffer_mmap[2]) framebuffer_mmap[2]=(void *)mmap(0, fb_size, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], (gp2x_physvram[2]=0x04000000-(0x26000*2) )); + if (!framebuffer_mmap[3]) framebuffer_mmap[3]=(void *)mmap(0, fb_size, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], (gp2x_physvram[3]=0x04000000-(0x26000*1) )); + + if (applyMmuHack) + { + printf("Applying MMUHACK..."); fflush(stdout); + mmuHackStatus = mmuhack(); + sprintf(buf, "Done\r\n. MMUHACK returned: %x\r\n", mmuHackStatus); + printf(buf); fflush(stdout); + } + + // offset externally visible buffers by 8 + // this allows DrMD to not worry about clipping + framebuffer16[0]=framebuffer_mmap[0]+8; + framebuffer16[1]=framebuffer_mmap[1]+8; + framebuffer16[2]=framebuffer_mmap[2]+8; + framebuffer16[3]=framebuffer_mmap[3]+8; + //ofset physical buffer as well + gp2x_physvram[0]+=16; + gp2x_physvram[1]+=16; + gp2x_physvram[2]+=16; + gp2x_physvram[3]+=16; + // clear all the framebuffers to black + // otherwise you get crap displayed on the screen the first time + // you start + framebuffer8[0]=(unsigned char*)framebuffer16[0]; + framebuffer8[1]=(unsigned char*)framebuffer16[1]; + framebuffer8[2]=(unsigned char*)framebuffer16[2]; + framebuffer8[3]=(unsigned char*)framebuffer16[3]; + + // Clear the frame buffers + memset(framebuffer16[0],0,320*240*2); + memset(framebuffer16[1],0,320*240*2); + memset(framebuffer16[2],0,320*240*2); + memset(framebuffer16[3],0,320*240*2); + + InitFramebuffer=1; + + //gp2x_memregs[0x0F16>>1] = 0x830a; + //usleep(1000000); + //gp2x_memregs[0x0F58>>1] = 0x100c; + //usleep(1000000); + + + } + + + // Set graphics mode + gp2x_memregs[0x28DA>>1]=(((bpp+1)/8)<<9)|0xAB; /*8/15/16/24bpp...*/ + gp2x_memregs[0x290C>>1]=320*((bpp+1)/8); + + //TV out fix + gp_video_RGB_setscaling(320,240); + + // 2d accel + //gp2x_memregs[0x904 >> 1] |= 1<<10; //SYSCLKENREG (System Clock Enable Register) maybe bit 10 is 2d accer + //gp2x_memregs[0x90a >> 1] = 0xffff; // Reset clock timings for all devices + + gp_setFramebuffer(flip,1); + +#ifdef DEBUG + printf("Leaving gp_initGraphics....\r\n"); +#endif +} + +void gp_setFramebuffer(int flip, int sync) +{ + CurrentFrameBuffer=flip; + unsigned int address=(unsigned int)gp2x_physvram[flip]; + unsigned short x=0; + /*switch(sync) + { + case 0: + // No sync + break; + + case 1: + // VSync + while(1) + { + x=gp2x_memregs[0x1182>>1]; + if((x&(1<<4)) == 0) + { + break; + } + } + break; + case 2: + // HSync + while(1) + { + x=gp2x_memregs[0x1182>>1]; + if((x&(1<<5)) == 0) + { + break; + } + } + break; + }*/ + + gp2x_memregs[0x290E>>1]=(unsigned short)(address & 0xffff); + gp2x_memregs[0x2910>>1]=(unsigned short)(address >> 16); + gp2x_memregs[0x2912>>1]=(unsigned short)(address & 0xffff); + gp2x_memregs[0x2914>>1]=(unsigned short)(address >> 16); +} + +void gp2x_video_setpalette(void) +{ + unsigned short *g=(unsigned short *)gp2x_palette; int i=512; + gp2x_memregs[0x2958>>1]=0; + while(i--) gp2x_memregs[0x295A>>1]=*g++; +} + +/* +######################## +Sound functions +######################## + */ +static +void *gp2x_sound_play(void) +{ + //struct timespec ts; ts.tv_sec=0, ts.tv_nsec=1000; + while(! gp2x_sound_thread_exit) + { + Timer++; + CurrentSoundBank++; + + if (CurrentSoundBank >= 8) CurrentSoundBank = 0; + + if (SoundThreadFlag==SOUND_THREAD_SOUND_ON) + { + write(gp2x_dev[3], (void *)pOutput[CurrentSoundBank], gp2x_sound_buffer[1]); + ioctl(gp2x_dev[3], SOUND_PCM_SYNC, 0); + //ts.tv_sec=0, ts.tv_nsec=(gp2x_sound_buffer[3]<<16)|gp2x_sound_buffer[2]; + //nanosleep(&ts, NULL); + } + else + { + write(gp2x_dev[3], (void *)&gp2x_sound_buffer[4], gp2x_sound_buffer[1]); + ioctl(gp2x_dev[3], SOUND_PCM_SYNC, 0); + //ts.tv_sec=0, ts.tv_nsec=(gp2x_sound_buffer[3]<<16)|gp2x_sound_buffer[2]; + //nanosleep(&ts, NULL); + } + } + + return NULL; +} + +void gp2x_sound_play_bank(int bank) +{ + write(gp2x_dev[3], (void *)(&gp2x_sound_buffer[4+(bank*gp2x_sound_buffer[1])]), gp2x_sound_buffer[1]); +} + +void gp2x_sound_sync(void) +{ + ioctl(gp2x_dev[3], SOUND_PCM_SYNC, 0); +} + +void gp_sound_volume(int l, int r) +{ + if(!gp2x_dev[4]) + { + gp2x_dev[4] = open("/dev/mixer", O_WRONLY); + } + + l=((l<<8)|r); + if (altVolumeCtrl) //For FW >= 4.0 + { + ioctl(gp2x_dev[4], SOUND_MIXER_WRITE_VOLUME, &l); + } + ioctl(gp2x_dev[4], SOUND_MIXER_WRITE_PCM, &l); +} + +unsigned long gp_timer_read(void) +{ + // Once again another peice of direct hardware access bites the dust + // the code below is broken in firmware 2.1.1 so I've replaced it with a + // to a linux function which seems to work + //return gp2x_memregl[0x0A00>>2]/gp2x_ticks_per_second; + struct timeval tval; // timing + + gettimeofday(&tval, 0); + //tval.tv_usec + //tval.tv_sec + return (tval.tv_sec*1000000)+tval.tv_usec; +} + +int gp_initSound(int rate, int bits, int stereo, int Hz, int frag) +{ + int status; + int i=0; + int nonblocking=1; + unsigned int bufferStart=0; + int result; + char text[256]; + + //Check if firmware version > 4 + FILE *fVersion = fopen("/usr/gp2x/version","r"); + if (fVersion) + { + if (fgetc(fVersion) == '4') + { + altVolumeCtrl = 1; + } + fclose(fVersion); + } + + //int frag=0x00020010; // double buffer - frag size = 1<<0xf = 32768 + + //8 = 256 = 2 fps loss = good sound + //9 = 512 = 1 fps loss = good sound + //A = 1024 = + //f = 32768 = 0 fps loss = bad sound + if ((frag!= CurrentFrag)&&(gp2x_dev[3]!=0)) + { + // Different frag config required + // close device in order to re-adjust + close(gp2x_dev[3]); + gp2x_dev[3]=0; + } + + if (gp2x_dev[3]==0) + { + gp2x_dev[3] = open("/dev/dsp", O_WRONLY); + printf("Opening sound device: %x\r\n",gp2x_dev[3]); + ioctl(gp2x_dev[3], SNDCTL_DSP_SETFRAGMENT, &frag); + CurrentFrag=frag; // save frag config + } + + //ioctl(gp2x_dev[3], SNDCTL_DSP_RESET, 0); + result=ioctl(gp2x_dev[3], SNDCTL_DSP_SPEED, &rate); + if(result==-1) + { + debug("Error setting DSP Speed",1); + return(-1); + } + + result=ioctl(gp2x_dev[3], SNDCTL_DSP_SETFMT, &bits); + if(result==-1) + { + debug("Error setting DSP format",1); + return(-1); + } + + result=ioctl(gp2x_dev[3], SNDCTL_DSP_STEREO, &stereo); + if(result==-1) + { + debug("Error setting DSP format",1); + return(-1); + } + //printf("Disable Blocking: %x\r\n",ioctl(gp2x_dev[3], 0x5421, &nonblocking)); + + gp2x_sound_buffer[1]=(gp2x_sound_buffer[0]=(rate/Hz)) << (stereo + (bits==16)); + gp2x_sound_buffer[2]=(1000000000/Hz)&0xFFFF; + gp2x_sound_buffer[3]=(1000000000/Hz)>>16; + + bufferStart= &gp2x_sound_buffer[4]; + pOutput[0] = (short*)bufferStart+(0*gp2x_sound_buffer[1]); + pOutput[1] = (short*)bufferStart+(1*gp2x_sound_buffer[1]); + pOutput[2] = (short*)bufferStart+(2*gp2x_sound_buffer[1]); + pOutput[3] = (short*)bufferStart+(3*gp2x_sound_buffer[1]); + pOutput[4] = (short*)bufferStart+(4*gp2x_sound_buffer[1]); + pOutput[5] = (short*)bufferStart+(5*gp2x_sound_buffer[1]); + pOutput[6] = (short*)bufferStart+(6*gp2x_sound_buffer[1]); + pOutput[7] = (short*)bufferStart+(7*gp2x_sound_buffer[1]); + + if(!gp2x_sound_thread) + { + pthread_create( &gp2x_sound_thread, NULL, gp2x_sound_play, NULL); + //atexit(gp_Reset); + } + + for(i=0;i<(gp2x_sound_buffer[1]*8);i++) + { + gp2x_sound_buffer[4+i] = 0; + } + + return(0); +} + +void gp_stopSound(void) +{ + unsigned int i=0; + gp2x_sound_thread_exit=1; + printf("Killing Thread\r\n"); + for(i=0;i<(gp2x_sound_buffer[1]*8);i++) + { + gp2x_sound_buffer[4+i] = 0; + } + usleep(100000); + printf("Thread is dead\r\n"); + gp2x_sound_thread=0; + gp2x_sound_thread_exit=0; + CurrentSoundBank=0; +} + + +/* +######################## +System functions +######################## + */ +void gp_Reset(void) +{ + unsigned int i=0; + + + if( gp2x_sound_thread) + { + gp2x_sound_thread_exit=1; + usleep(500); + } + + gp2x_memregs[0x28DA>>1]=0x4AB; + gp2x_memregs[0x290C>>1]=640; + munmap((void *)gp2x_memregs, 0x10000); + + munmap(framebuffer_mmap[0], fb_size); + munmap(framebuffer_mmap[1], fb_size); + munmap(framebuffer_mmap[2], fb_size); + munmap(framebuffer_mmap[3], fb_size); + + if (gp2x_dev[0]) close(gp2x_dev[0]); + if (gp2x_dev[1]) close(gp2x_dev[1]); + if (gp2x_dev[2]) close(gp2x_dev[2]); + if (gp2x_dev[3]) close(gp2x_dev[3]); + if (gp2x_dev[4]) close(gp2x_dev[4]); + + fcloseall(); + + // If MMUHACK was applied succesfully then remove it + if (mmuHackStatus) mmuunhack(); + + chdir("/usr/gp2x"); + execl("gp2xmenu",NULL); +} + +void gp_video_RGB_setscaling(int W, int H) +{ + float escalaw,escalah; + int bpp=(gp2x_memregs[0x28DA>>1]>>9)&0x3; + + if(gp2x_memregs[0x2800>>1]&0x100) //TV-Out + { + escalaw=489.0; //RGB Horiz TV (PAL, NTSC) + if (gp2x_memregs[0x2818>>1] == 287) //PAL + escalah=274.0; //RGB Vert TV PAL + else if (gp2x_memregs[0x2818>>1] == 239) //NTSC + escalah=331.0; //RGB Vert TV NTSC + } + else //LCD + { + escalaw=1024.0; //RGB Horiz LCD + escalah=320.0; //RGB Vert LCD + } + + // scale horizontal + gp2x_memregs[0x2906>>1]=(unsigned short)((float)escalaw *(W/320.0)); + // scale vertical + gp2x_memregl[0x2908>>2]=(unsigned long)((float)escalah *bpp *(H/240.0)); +} + +void gp_setCpuspeed(unsigned int MHZ) +{ + unsigned v; + unsigned mdiv,pdiv=3,scale=0; + + MHZ*=1000000; + mdiv=(MHZ*pdiv)/SYS_CLK_FREQ; + mdiv=((mdiv-8)<<8) & 0xff00; + pdiv=((pdiv-2)<<2) & 0xfc; + scale&=3; + v=mdiv | pdiv | scale; + gp2x_memregs[0x910>>1]=v; + +} + +// craigix: --trc 6 --tras 4 --twr 1 --tmrd 1 --trfc 1 --trp 2 --trcd 2 +// set_RAM_Timings(6, 4, 1, 1, 1, 2, 2); +void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD) +{ + tRC -= 1; tRAS -= 1; tWR -= 1; tMRD -= 1; tRFC -= 1; tRP -= 1; tRCD -= 1; // ??? + gp2x_memregs[0x3802>>1] = ((tMRD & 0xF) << 12) | ((tRFC & 0xF) << 8) | ((tRP & 0xF) << 4) | (tRCD & 0xF); + gp2x_memregs[0x3804>>1] = /*0x9000 |*/ ((tRC & 0xF) << 8) | ((tRAS & 0xF) << 4) | (tWR & 0xF); +} + +void set_gamma(int g100) +{ + float gamma = (float) g100 / 100; + int i; + gamma = 1/gamma; + + //enable gamma + gp2x_memregs[0x2880>>1]&=~(1<<12); + + gp2x_memregs[0x295C>>1]=0; + for(i=0; i<256; i++) + { + unsigned char g; + unsigned short s; + g =(unsigned char)(255.0*pow(i/255.0,gamma)); + s = (g<<8) | g; + gp2x_memregs[0x295E>>1]= s; + gp2x_memregs[0x295E>>1]= g; + } +} + + + + + diff --git a/src/gp2x_sdk.h b/src/gp2x_sdk.h new file mode 100644 index 0000000..1ae2c3d --- /dev/null +++ b/src/gp2x_sdk.h @@ -0,0 +1,68 @@ +#ifndef _GP2X_SDK_H_ +#define _GP2X_SDK_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOUND_THREAD_SOUND_ON 1 +#define SOUND_THREAD_SOUND_OFF 2 +#define SOUND_THREAD_PAUSE 3 + +#define INP_BUTTON_UP (0) +#define INP_BUTTON_LEFT (2) +#define INP_BUTTON_DOWN (4) +#define INP_BUTTON_RIGHT (6) +#define INP_BUTTON_START (8) +#define INP_BUTTON_SELECT (9) +#define INP_BUTTON_L (10) +#define INP_BUTTON_R (11) +#define INP_BUTTON_A (12) +#define INP_BUTTON_B (13) +#define INP_BUTTON_X (14) +#define INP_BUTTON_Y (15) +#define INP_BUTTON_VOL_UP (23) +#define INP_BUTTON_VOL_DOWN (22) +#define INP_BUTTON_STICK_PUSH (27) + +void gp_setClipping(int x1, int y1, int x2, int y2); +void gp_drawString (int x,int y,int len,char *buffer,unsigned short color,void *framebuffer); +void gp_clearFramebuffer16(unsigned short *framebuffer, unsigned short pal); +void gp_clearFramebuffer8(unsigned char *framebuffer, unsigned char pal); +void gp_clearFramebuffer(void *framebuffer, unsigned int pal); +void gp_setCpuspeed(unsigned int cpuspeed); +void gp_initGraphics(unsigned short bpp, int flip, int applyMmuHack); +void gp_setFramebuffer(int flip, int sync); +void gp2x_video_setpalette(void); +int gp_initSound(int rate, int bits, int stereo, int Hz, int frag); +void gp_stopSound(void); +void gp_Reset(void); +void gp2x_enableIRQ(void); +void gp2x_disableIRQ(void); +void gp_sound_volume(int l, int r); +unsigned long gp_timer_read(void); +unsigned int gp_getButton(unsigned char enable_diagnals); +void gp_video_RGB_setscaling(int W, int H); +void gp2x_sound_play_bank(int bank); +void gp2x_sound_sync(void); +void set_gamma(int g100); +void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD); + +extern volatile int SoundThreadFlag; +extern volatile int CurrentSoundBank; +extern int CurrentFrameBuffer; +extern volatile short *pOutput[]; +extern unsigned short *framebuffer16[]; +extern unsigned long gp2x_physvram[]; +extern unsigned char *framebuffer8[]; +extern volatile unsigned short gp2x_palette[512][2]; +extern volatile unsigned short *gp2x_memregs; +extern volatile unsigned long *gp2x_memregl; +extern volatile unsigned long *gp2x_blitter; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/gp32_func.h b/src/gp32_func.h new file mode 100644 index 0000000..8ee461d --- /dev/null +++ b/src/gp32_func.h @@ -0,0 +1,13 @@ +#ifndef __gp32_func_h__ +#define __gp32_func_h__ + +extern "C" int funcSADDMULT1616(int a,int b,int c,int d); + +#define SADDMULT1616(res,a,b,c,d) {\ + res=funcSADDMULT1616(a,b,c,d);\ + } +#define SMULT1616(res,a,b) {\ + res=funcSADDMULT1616(a,b,0,0);\ + } + +#endif diff --git a/src/graphics.c b/src/graphics.c new file mode 100644 index 0000000..50cb0ce --- /dev/null +++ b/src/graphics.c @@ -0,0 +1,316 @@ +/* + Simple graphic handling library + Under GPL v2 License + 2011 by bitrider +*/ +#include +#include + +#include "graphics.h" + +static int clipping_x1 = 0; +static int clipping_x2 = SCREEN_WIDTH - 1; +static int clipping_y1 = 0; +static int clipping_y2 = SCREEN_HEIGHT - 1; + +void gSetClipping(int x1, int y1, int x2, int y2) { + if (x1 < 0) x1 = 0; + if (x1 > (SCREEN_WIDTH -1)) x1 = (SCREEN_WIDTH -1); + if (x2 < 0) x2 = 0; + if (x2 > (SCREEN_WIDTH -1)) x2 = (SCREEN_WIDTH -1); + if (y1 < 0) y1 = 0; + if (y1 > (SCREEN_HEIGHT - 1)) y1 = (SCREEN_HEIGHT - 1); + if (y2 < 0) y2 = 0; + if (y2 > (SCREEN_HEIGHT - 1)) y2 = (SCREEN_HEIGHT - 1); + + if (x1 < x2) { + clipping_x1 = x1; + clipping_x2 = x2; + } else { + clipping_x2 = x1; + clipping_x1 = x2; + } + + if (y1 < y2) { + clipping_y1 = y1; + clipping_y2 = y2; + } else { + clipping_y2 = y1; + clipping_y1 = y2; + } +} + +void gClearClipping() { + clipping_x1 = 0; + clipping_y1 = 0; + clipping_x2 = SCREEN_WIDTH - 1; + clipping_y2 = SCREEN_HEIGHT - 1; +} + +void gDestroyBitmap(gBITMAP *img) { + if (img) { + free(img->data); + free(img); + } +} + +gBITMAP *gCreateBitmap(unsigned int width, unsigned int height, unsigned char bpp) { + gBITMAP *img; + + if (bpp != 32) return NULL; // supported BPPs + if ((!width) || (!height)) return NULL; + + img = malloc(sizeof(gBITMAP)); + if (!img) return NULL; + img->bpp = bpp; + img->w = width; + img->h = height; + img->data = malloc(width * height * (bpp >> 3)); + if (!img->data) { + free(img); + return NULL; + } + return img; +} + +void gDrawPixel16(unsigned short *screen, int x, int y, unsigned char r, unsigned char g, unsigned char b) { + unsigned int sr, sg, sb; + unsigned short pixel; + + if ((x < clipping_x1) || (x > clipping_x2) || (y < clipping_y1) || (y > clipping_y2)) return; + + // blend + screen[y * SCREEN_WIDTH + x] = RGB16(r, g, b); +} + +void gBlendPixel16(unsigned short *screen, int x, int y, unsigned char r, unsigned char g, unsigned char b, unsigned char a) { + unsigned int sr, sg, sb; + unsigned short pixel; + + if ((x < clipping_x1) || (x > clipping_x2) || (y < clipping_y1) || (y > clipping_y2)) return; + + // get screen pixel + pixel = screen[y * SCREEN_WIDTH + x]; + sr = PIXEL16_R(pixel); //((pixel >> 11) << 3); + sg = PIXEL16_G(pixel); //((pixel >> 5) & 63) << 2; + sb = PIXEL16_B(pixel); //(pixel & 31) << 3; + // blend + screen[y * SCREEN_WIDTH + x] = RGB16(BLEND(r, a, sr), BLEND(g, a, sg), BLEND(b, a, sb)); +} + +void gBlendBitmap16(unsigned short *screen, int sx, int sy, gBITMAP *img, unsigned int ix, unsigned int iy, unsigned int iw, unsigned int ih) { + int ssx; + unsigned int sw, ijmp, sjmp; + unsigned char *iaddr; + unsigned int pixel; + + if ((!img) || (!img->data)) return; // sanity check + if (img->bpp != 32) return; // supported BPPs + if ((sx > clipping_x2) || (sy > clipping_y2) || + ((sx + iw - 1) < clipping_x1) || ((sy + ih - 1) < clipping_y1)) return; // Out of screen + + // Image dimensions + if ((iw + ix) > img->w) iw = img->w - ix; + if ((ih + iy) > img->h) ih = img->h - iy; + + // Clipping + if (sx < clipping_x1) { + iw -= clipping_x1 - sx; + sx = clipping_x1; + } + if (sy < clipping_y1) { + ih -= clipping_y1 - sy; + sy = clipping_y1; + } + if ((sx + iw - 1) > clipping_x2) iw -= (sx + iw - 1) - clipping_x2; + if ((sy + ih - 1) > clipping_y2) ih -= (sy + ih - 1) - clipping_y2; + + ssx = sx; + sw = iw; + + ijmp = (img->w - iw) * (img->bpp >> 3); + iaddr = &img->data[(iy * img->w + ix) * 4 + 0]; + sjmp = SCREEN_WIDTH - iw; + screen = &screen[sy * SCREEN_WIDTH + sx]; + + for (; (ih > 0); ih--, iaddr += ijmp, screen += sjmp) { + for (iw = sw; (iw > 0); iw--, iaddr += 4, screen++) { + // blend + pixel = *((unsigned int *)iaddr); + /* + *screen = RGB16(BLEND(iaddr[0], iaddr[3], PIXEL16_R(*screen)), + BLEND(iaddr[1], iaddr[3], PIXEL16_G(*screen)), + BLEND(iaddr[2], iaddr[3], PIXEL16_B(*screen))); + */ + *screen = RGB16(BLEND(PIXEL32_R(pixel), PIXEL32_A(pixel), PIXEL16_R(*screen)), + BLEND(PIXEL32_G(pixel), PIXEL32_A(pixel), PIXEL16_G(*screen)), + BLEND(PIXEL32_B(pixel), PIXEL32_A(pixel), PIXEL16_B(*screen))); + } + } +} + +void gDrawBitmap16(unsigned short *screen, int sx, int sy, gBITMAP *img, unsigned int ix, unsigned int iy, unsigned int iw, unsigned int ih) { + int ssx; + unsigned int sw, ijmp, sjmp; + unsigned char *iaddr; + unsigned short pixel; + + if ((!img) || (!img->data)) return; // sanity check + if ((img->bpp != 32) || (img->bpp != 32)) return; // supported BPPs + if ((sx > clipping_x2) || (sy > clipping_y2) || + ((sx + iw - 1) < clipping_x1) || ((sy + ih - 1) < clipping_y1)) return; // Out of screen + + // Image dimensions + if ((iw + ix) > img->w) iw = img->w - ix; + if ((ih + iy) > img->h) ih = img->h - iy; + + // Clipping + if (sx < clipping_x1) { + iw -= clipping_x1 - sx; + sx = clipping_x1; + } + if (sy < clipping_y1) { + ih -= clipping_y1 - sy; + sy = clipping_y1; + } + if ((sx + iw - 1) > clipping_x2) iw -= (sx + iw - 1) - clipping_x2; + if ((sy + ih - 1) > clipping_y2) ih -= (sy + ih - 1) - clipping_y2; + + ssx = sx; + sw = iw; + + ijmp = (img->w - iw) * (img->bpp >> 3); + iaddr = &img->data[(iy * img->w + ix) * (img->bpp >> 3) + 0]; + sjmp = SCREEN_WIDTH - iw; + screen = &screen[sy * SCREEN_WIDTH + sx]; + + switch (img->bpp) { + case 32: + for (; (ih > 0); ih--, iaddr += ijmp, screen += sjmp) { + for (iw = sw; (iw > 0); iw--, iaddr += 4, screen++) { + *screen = RGB16(iaddr[0], iaddr[1], iaddr[2]); + } + } + break; + case 16: + for (; (ih > 0); ih--, iaddr += ijmp, screen += sjmp) { + for (iw = sw; (iw > 0); iw--, iaddr += 2) { + *screen++ = *(unsigned short *)iaddr; + } + } + break; + } +} + +void gDrawScaledBitmap16(unsigned short *screen, int sx, int sy, gBITMAP *img, unsigned int iw, unsigned int ih) { + int dx, dy; + int x , y, fp_x, w, h; + unsigned int *addr; + unsigned int pixel; + + if ((!img) || (!img->data)) return; // sanity check + if ((img->bpp != 32) || (img->bpp != 32)) return; // supported BPPs + + #define FP 10 + dx = (img->w << FP) / iw; + dy = (img->h << FP) / ih; + + w = SCREEN_WIDTH; + if (w > iw) w = iw; + h = SCREEN_HEIGHT; + if (h > ih) h = ih; + + for (y = 0; y < h; y++) { + addr = &((unsigned int *)img->data)[img->w * ((y * dy) >> FP)]; + for (x = 0, fp_x = 0; x < w ; x++, fp_x += dx) { + pixel = addr[fp_x >> FP]; + gDrawPixel16(screen, sx+x, sy+y, PIXEL32_R(pixel), PIXEL32_G(pixel), PIXEL32_B(pixel)); + } + } +} + +gBITMAP *gStretchBitmap(gBITMAP *img, unsigned int iw, unsigned int ih) { + int dx, dy; + int x , y, fp_x, fx, w, h; + unsigned int *srcCurLineAddr, *srcPrevLineAddr, *srcNextLineAddr; + unsigned int *dstAddr; + unsigned int pixel, r, g, b, a, div; + gBITMAP *toBmp; + + if ((!img) || (!img->data)) return NULL; // sanity check + if ((img->bpp != 32) || (img->bpp != 32)) return NULL; // supported BPPs + + toBmp = gCreateBitmap(iw, ih, img->bpp); + if (!toBmp) return NULL; + + #define FP 10 + dx = (img->w << FP) / iw; + dy = (img->h << FP) / ih; + + w = img->w; + if (w > iw) w = iw; + h = img->h; + if (h > ih) h = ih; + + for (y = 0; y < ih; y++) { + // Current line + srcCurLineAddr = &((unsigned int *)img->data)[img->w * ((y * dy) >> FP)]; + // Previous line + if (y == 0) srcPrevLineAddr = NULL; + else srcPrevLineAddr = &((unsigned int *)img->data)[img->w * (((y * dy) - 1) >> FP)]; + // Next line + if ((((y * dy) + 1) >> FP) >= img->h) srcNextLineAddr = NULL; + else srcNextLineAddr = &((unsigned int *)img->data)[img->w * (((y * dy) + 1) >> FP)]; + // Destination + dstAddr = &((unsigned int*)toBmp->data)[toBmp->w * y]; + for (x = 0, fp_x = 0; x < iw ; x++, fp_x += dx) { + // Current line + div = 4; + fx = fp_x >> FP; + pixel = srcCurLineAddr[fx]; + r = PIXEL32_R(pixel) * 4; + g = PIXEL32_G(pixel) * 4; + b = PIXEL32_B(pixel) * 4; + a = PIXEL32_A(pixel) * 4; +#define INCLUDE_PIXEL(p) \ + {\ + pixel = p;\ + r += PIXEL32_R(pixel);\ + g += PIXEL32_G(pixel);\ + b += PIXEL32_B(pixel);\ + a += PIXEL32_A(pixel);\ + div++;\ + } + + if (fx > 0) INCLUDE_PIXEL(srcCurLineAddr[fx - 1]); + if ((fx + 1) < img->w) INCLUDE_PIXEL(srcCurLineAddr[fx + 1]); + // Previous line + if (srcPrevLineAddr) { + INCLUDE_PIXEL(srcPrevLineAddr[fx]); + if (fx > 0) INCLUDE_PIXEL(srcPrevLineAddr[fx - 1]); + if ((fx + 1) < img->w) INCLUDE_PIXEL(srcPrevLineAddr[fx + 1]); + } + // Next line + if (srcNextLineAddr) { + INCLUDE_PIXEL(srcNextLineAddr[fx]); + if (fx > 0) INCLUDE_PIXEL(srcNextLineAddr[fx - 1]); + if ((fx + 1) < img->w) INCLUDE_PIXEL(srcNextLineAddr[fx + 1]); + } +#undef INCLUDE_PIXEL + dstAddr[x] = RGB32(r/div, g/div, b/div, a/div); + } + } + + return toBmp; +} + + + +void gClearScreen(unsigned short *screen, unsigned short color) { + int x, y; + + for (y = 0; y < SCREEN_HEIGHT; y++) + for (x = 0; x < SCREEN_WIDTH; x++) { + screen[y * SCREEN_WIDTH + x] = color; + } +} diff --git a/src/graphics.h b/src/graphics.h new file mode 100644 index 0000000..2927110 --- /dev/null +++ b/src/graphics.h @@ -0,0 +1,57 @@ +#ifndef __GRAPHICS_H__ +#define __GRAPHICS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define SCREEN_WIDTH 320 +#define SCREEN_HEIGHT 240 + +#define PIXEL32_A(p) (p >> 24) +#define PIXEL32_B(p) ((p >> 16) & 0xff) +#define PIXEL32_G(p) ((p >> 8) & 0xff) +#define PIXEL32_R(p) (p & 0xff) +#define RGB32(r, g, b, a) ((a << 24) | (b << 16) | (g << 8) | r) + +#define RGB16(r, g, b) (((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3)) +#define PIXEL16_R(p) ((p >> 11) << 3) +#define PIXEL16_G(p) (((p >> 5) & 63) << 2) +#define PIXEL16_B(p) ((p & 31) << 3) +//#define BLEND(c1, a, c2) (((((unsigned int)c1) * ((unsigned int)a)) + (((unsigned int)c2) * (0x100 - ((unsigned char)a)))) >> 8) +#define BLEND(c1, a, c2) ((((int)a * ((int)c1 - (int)c2)) + ((int)c2 << 8)) >> 8) +#ifndef MIN + #define MIN(a, b) (((a) < (b))? (a) : (b)) +#endif +#ifndef MIN + #define MAX(a, b) (((a) > (b))? (a) : (b)) +#endif + + +typedef struct { + unsigned int w; + unsigned int h; + unsigned int bpp; + unsigned char *data; + } gBITMAP; + +void gSetClipping(int x1, int y1, int x2, int y2); +void gClearClipping(); + +void gClearScreen(unsigned short *screen, unsigned short color); + +void gBlendPixel16(unsigned short *screen, int x, int y, unsigned char r, unsigned char g, unsigned char b, unsigned char a); +void gDrawPixel16(unsigned short *screen, int x, int y, unsigned char r, unsigned char g, unsigned char b); +void gBlendBitmap16(unsigned short *screen, int sx, int sy, gBITMAP *img, unsigned int ix, unsigned int iy, unsigned int iw, unsigned int ih); +void gDrawBitmap16(unsigned short *screen, int sx, int sy, gBITMAP *img, unsigned int ix, unsigned int iy, unsigned int iw, unsigned int ih); +void gDrawScaledBitmap16(unsigned short *screen, int sx, int sy, gBITMAP *img, unsigned int iw, unsigned int ih); + +void gDestroyBitmap(gBITMAP *img); +gBITMAP *gCreateBitmap(unsigned int width, unsigned int height, unsigned char bpp); +gBITMAP *gStretchBitmap(gBITMAP *img, unsigned int iw, unsigned int ih); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/gx.h b/src/gx.h new file mode 100644 index 0000000..0547d30 --- /dev/null +++ b/src/gx.h @@ -0,0 +1,83 @@ + +// The following ifdef block is the standard way of creating macros which make exporting +// from a DLL simpler. All files within this DLL are compiled with the GXDLL_EXPORTS +// symbol defined on the command line. this symbol should not be defined on any project +// that uses this DLL. This way any other project whose source files include this file see +// GXDLL_API functions as being imported from a DLL, wheras this DLL sees symbols +// defined with this macro as being exported. + +#ifdef GXDLL_EXPORTS +#define GXDLL_API __declspec(dllexport) +#else +#define GXDLL_API __declspec(dllimport) +#endif + +struct GXDisplayProperties { + DWORD cxWidth; + DWORD cyHeight; // notice lack of 'th' in the word height. + long cbxPitch; // number of bytes to move right one x pixel - can be negative. + long cbyPitch; // number of bytes to move down one y pixel - can be negative. + long cBPP; // # of bits in each pixel + DWORD ffFormat; // format flags. +}; + +struct GXKeyList { + short vkUp; // key for up + POINT ptUp; // x,y position of key/button. Not on screen but in screen coordinates. + short vkDown; + POINT ptDown; + short vkLeft; + POINT ptLeft; + short vkRight; + POINT ptRight; + short vkA; + POINT ptA; + short vkB; + POINT ptB; + short vkC; + POINT ptC; + short vkStart; + POINT ptStart; +}; + +struct GXScreenRect { + DWORD dwTop; + DWORD dwLeft; + DWORD dwWidth; + DWORD dwHeight; +}; + +GXDLL_API int GXOpenDisplay(HWND hWnd, DWORD dwFlags); +GXDLL_API int GXCloseDisplay(); +GXDLL_API void * GXBeginDraw(); +GXDLL_API int GXEndDraw(); +GXDLL_API int GXOpenInput(); +GXDLL_API int GXCloseInput(); +//The following two lines modified by Dan East to make this header C compatible: +//Added "struct" to the following two prototypes: +GXDLL_API struct GXDisplayProperties GXGetDisplayProperties(); +GXDLL_API struct GXKeyList GXGetDefaultKeys(int iOptions); +GXDLL_API int GXSuspend(); +GXDLL_API int GXResume(); +GXDLL_API int GXSetViewport( DWORD dwTop, DWORD dwHeight, DWORD dwReserved1, DWORD dwReserved2 ); +GXDLL_API BOOL GXIsDisplayDRAMBuffer(); + + +// Although these flags can be unrelated they still +// have unique values. + +#define GX_FULLSCREEN 0x01 // for OpenDisplay() +#define GX_NORMALKEYS 0x02 +#define GX_LANDSCAPEKEYS 0x03 + +#ifndef kfLandscape + #define kfLandscape 0x8 // Screen is rotated 270 degrees + #define kfPalette 0x10 // Pixel values are indexes into a palette + #define kfDirect 0x20 // Pixel values contain actual level information + #define kfDirect555 0x40 // 5 bits each for red, green and blue values in a pixel. + #define kfDirect565 0x80 // 5 red bits, 6 green bits and 5 blue bits per pixel + #define kfDirect888 0x100 // 8 bits each for red, green and blue values in a pixel. + #define kfDirect444 0x200 // 4 red, 4 green, 4 blue + #define kfDirectInverted 0x400 +#endif + diff --git a/src/imgdecmp.h b/src/imgdecmp.h new file mode 100644 index 0000000..d323647 --- /dev/null +++ b/src/imgdecmp.h @@ -0,0 +1,58 @@ +/*---------------------------------------------------------------------------*\ + * + * (c) Copyright Microsoft Corp. 1997-98 All Rights Reserved + * + * module: imgdecmp.h + * date: + * author: jaym + * + * purpose: + * +\*---------------------------------------------------------------------------*/ +#ifndef __IMGDECMP_H__ +#define __IMGDECMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "imgrendr.h" + +typedef void (CALLBACK *PROGRESSFUNC)(IImageRender *pRender, BOOL bComplete, LPARAM lParam); +typedef DWORD (CALLBACK *GETDATAFUNC)(LPSTR szBuffer, DWORD dwBufferMax, LPARAM lParam); + +typedef struct tagDecompressImageInfo { + DWORD dwSize; // Size of this structure + LPBYTE pbBuffer; // Pointer to the buffer to use for data + DWORD dwBufferMax; // Size of the buffer + DWORD dwBufferCurrent; // The amount of data which is current in the buffer + HBITMAP * phBM; // Pointer to the bitmap returned (can be NULL) + IImageRender ** ppImageRender; // Pointer to an IImageRender object (can be NULL) + int iBitDepth; // Bit depth of the output image + LPARAM lParam; // User parameter for callback functions + HDC hdc; // HDC to use for retrieving palettes + int iScale; // Scale factor (1 - 100) + int iMaxWidth; // Maximum width of the output image + int iMaxHeight; // Maxumum height of the output image + GETDATAFUNC pfnGetData; // Callback function to get more data + PROGRESSFUNC pfnImageProgress; // Callback function to notify caller of progress decoding the image + COLORREF crTransparentOverride; // If this color is not (UINT)-1, it will override the + // transparent color in the image with this color. (GIF ONLY) +} DecompressImageInfo; + +#define IMGDECOMP_E_NOIMAGE 0x800b0100 + +COLORREF * +GetHalftonePalette(); + +COLORREF * +Get332Palette(); + +HRESULT +DecompressImageIndirect(DecompressImageInfo *pParams); + +#ifdef __cplusplus +}; +#endif // __cplusplus + +#endif // !__IMGDECMP_H__ diff --git a/src/imgrendr.h b/src/imgrendr.h new file mode 100644 index 0000000..5b05752 --- /dev/null +++ b/src/imgrendr.h @@ -0,0 +1,270 @@ +/* this ALWAYS GENERATED file contains the definitions for the interfaces */ + + +/* File created by MIDL compiler version 3.01.75 */ +/* at Tue Feb 10 13:46:55 1998 + */ +/* Compiler settings for .\imgrendr.idl: + Oicf (OptLev=i2), W1, Zp8, env=Win32, ms_ext, c_ext + error checks: none +*/ +//@@MIDL_FILE_HEADING( ) +#include "rpc.h" +#include "rpcndr.h" +#ifndef COM_NO_WINDOWS_H +#include "windows.h" +#include "ole2.h" +#endif /*COM_NO_WINDOWS_H*/ + +#ifndef __imgrendr_h__ +#define __imgrendr_h__ + +#ifdef __cplusplus +extern "C"{ +#endif + +/* Forward Declarations */ + +#ifndef __IImageRender_FWD_DEFINED__ +#define __IImageRender_FWD_DEFINED__ +typedef interface IImageRender IImageRender; +#endif /* __IImageRender_FWD_DEFINED__ */ + + +/* header files for imported files */ +#include "oaidl.h" +#include "ocidl.h" + +void __RPC_FAR * __RPC_USER MIDL_user_allocate(size_t); +void __RPC_USER MIDL_user_free( void __RPC_FAR * ); + +#ifndef __IImageRender_INTERFACE_DEFINED__ +#define __IImageRender_INTERFACE_DEFINED__ + +/**************************************** + * Generated header for interface: IImageRender + * at Tue Feb 10 13:46:55 1998 + * using MIDL 3.01.75 + ****************************************/ +/* [unique][helpstring][uuid][object] */ + + + +EXTERN_C const IID IID_IImageRender; + +#if defined(__cplusplus) && !defined(CINTERFACE) + + interface DECLSPEC_UUID("59032090-154B-11d1-A9BF-006097DE299B") + IImageRender : public IUnknown + { + public: + virtual /* [helpstring] */ HRESULT STDMETHODCALLTYPE Draw( + HDC hdc, + RECT __RPC_FAR *lpRect) = 0; + + virtual /* [helpstring] */ HRESULT STDMETHODCALLTYPE GetBitmap( + HBITMAP __RPC_FAR *phBitmap, + BOOL fTake) = 0; + + virtual /* [helpstring] */ HRESULT STDMETHODCALLTYPE GetOrigWidth( + int __RPC_FAR *piWidth) = 0; + + virtual /* [helpstring] */ HRESULT STDMETHODCALLTYPE GetOrigHeight( + int __RPC_FAR *piHeight) = 0; + + virtual /* [helpstring] */ HRESULT STDMETHODCALLTYPE GetBits( + unsigned char __RPC_FAR *__RPC_FAR *ppbBits) = 0; + + virtual /* [helpstring] */ HRESULT STDMETHODCALLTYPE ImageFail( + BOOL __RPC_FAR *pbFail) = 0; + + }; + +#else /* C style interface */ + + typedef struct IImageRenderVtbl + { + BEGIN_INTERFACE + + HRESULT ( STDMETHODCALLTYPE __RPC_FAR *QueryInterface )( + IImageRender __RPC_FAR * This, + /* [in] */ REFIID riid, + /* [iid_is][out] */ void __RPC_FAR *__RPC_FAR *ppvObject); + + ULONG ( STDMETHODCALLTYPE __RPC_FAR *AddRef )( + IImageRender __RPC_FAR * This); + + ULONG ( STDMETHODCALLTYPE __RPC_FAR *Release )( + IImageRender __RPC_FAR * This); + + /* [helpstring] */ HRESULT ( STDMETHODCALLTYPE __RPC_FAR *Draw )( + IImageRender __RPC_FAR * This, + HDC hdc, + RECT __RPC_FAR *lpRect); + + /* [helpstring] */ HRESULT ( STDMETHODCALLTYPE __RPC_FAR *GetBitmap )( + IImageRender __RPC_FAR * This, + HBITMAP __RPC_FAR *phBitmap, + BOOL fTake); + + /* [helpstring] */ HRESULT ( STDMETHODCALLTYPE __RPC_FAR *GetOrigWidth )( + IImageRender __RPC_FAR * This, + int __RPC_FAR *piWidth); + + /* [helpstring] */ HRESULT ( STDMETHODCALLTYPE __RPC_FAR *GetOrigHeight )( + IImageRender __RPC_FAR * This, + int __RPC_FAR *piHeight); + + /* [helpstring] */ HRESULT ( STDMETHODCALLTYPE __RPC_FAR *GetBits )( + IImageRender __RPC_FAR * This, + unsigned char __RPC_FAR *__RPC_FAR *ppbBits); + + /* [helpstring] */ HRESULT ( STDMETHODCALLTYPE __RPC_FAR *ImageFail )( + IImageRender __RPC_FAR * This, + BOOL __RPC_FAR *pbFail); + + END_INTERFACE + } IImageRenderVtbl; + + interface IImageRender + { + CONST_VTBL struct IImageRenderVtbl __RPC_FAR *lpVtbl; + }; + + + +#ifdef COBJMACROS + + +#define IImageRender_QueryInterface(This,riid,ppvObject) \ + (This)->lpVtbl -> QueryInterface(This,riid,ppvObject) + +#define IImageRender_AddRef(This) \ + (This)->lpVtbl -> AddRef(This) + +#define IImageRender_Release(This) \ + (This)->lpVtbl -> Release(This) + + +#define IImageRender_Draw(This,hdc,lpRect) \ + (This)->lpVtbl -> Draw(This,hdc,lpRect) + +#define IImageRender_GetBitmap(This,phBitmap,fTake) \ + (This)->lpVtbl -> GetBitmap(This,phBitmap,fTake) + +#define IImageRender_GetOrigWidth(This,piWidth) \ + (This)->lpVtbl -> GetOrigWidth(This,piWidth) + +#define IImageRender_GetOrigHeight(This,piHeight) \ + (This)->lpVtbl -> GetOrigHeight(This,piHeight) + +#define IImageRender_GetBits(This,ppbBits) \ + (This)->lpVtbl -> GetBits(This,ppbBits) + +#define IImageRender_ImageFail(This,pbFail) \ + (This)->lpVtbl -> ImageFail(This,pbFail) + +#endif /* COBJMACROS */ + + +#endif /* C style interface */ + + + +/* [helpstring] */ HRESULT STDMETHODCALLTYPE IImageRender_Draw_Proxy( + IImageRender __RPC_FAR * This, + HDC hdc, + RECT __RPC_FAR *lpRect); + + +void __RPC_STUB IImageRender_Draw_Stub( + IRpcStubBuffer *This, + IRpcChannelBuffer *_pRpcChannelBuffer, + PRPC_MESSAGE _pRpcMessage, + DWORD *_pdwStubPhase); + + +/* [helpstring] */ HRESULT STDMETHODCALLTYPE IImageRender_GetBitmap_Proxy( + IImageRender __RPC_FAR * This, + HBITMAP __RPC_FAR *phBitmap, + BOOL fTake); + + +void __RPC_STUB IImageRender_GetBitmap_Stub( + IRpcStubBuffer *This, + IRpcChannelBuffer *_pRpcChannelBuffer, + PRPC_MESSAGE _pRpcMessage, + DWORD *_pdwStubPhase); + + +/* [helpstring] */ HRESULT STDMETHODCALLTYPE IImageRender_GetOrigWidth_Proxy( + IImageRender __RPC_FAR * This, + int __RPC_FAR *piWidth); + + +void __RPC_STUB IImageRender_GetOrigWidth_Stub( + IRpcStubBuffer *This, + IRpcChannelBuffer *_pRpcChannelBuffer, + PRPC_MESSAGE _pRpcMessage, + DWORD *_pdwStubPhase); + + +/* [helpstring] */ HRESULT STDMETHODCALLTYPE IImageRender_GetOrigHeight_Proxy( + IImageRender __RPC_FAR * This, + int __RPC_FAR *piHeight); + + +void __RPC_STUB IImageRender_GetOrigHeight_Stub( + IRpcStubBuffer *This, + IRpcChannelBuffer *_pRpcChannelBuffer, + PRPC_MESSAGE _pRpcMessage, + DWORD *_pdwStubPhase); + + +/* [helpstring] */ HRESULT STDMETHODCALLTYPE IImageRender_GetBits_Proxy( + IImageRender __RPC_FAR * This, + unsigned char __RPC_FAR *__RPC_FAR *ppbBits); + + +void __RPC_STUB IImageRender_GetBits_Stub( + IRpcStubBuffer *This, + IRpcChannelBuffer *_pRpcChannelBuffer, + PRPC_MESSAGE _pRpcMessage, + DWORD *_pdwStubPhase); + + +/* [helpstring] */ HRESULT STDMETHODCALLTYPE IImageRender_ImageFail_Proxy( + IImageRender __RPC_FAR * This, + BOOL __RPC_FAR *pbFail); + + +void __RPC_STUB IImageRender_ImageFail_Stub( + IRpcStubBuffer *This, + IRpcChannelBuffer *_pRpcChannelBuffer, + PRPC_MESSAGE _pRpcMessage, + DWORD *_pdwStubPhase); + + + +#endif /* __IImageRender_INTERFACE_DEFINED__ */ + + +/* Additional Prototypes for ALL interfaces */ + +unsigned long __RPC_USER HBITMAP_UserSize( unsigned long __RPC_FAR *, unsigned long , HBITMAP __RPC_FAR * ); +unsigned char __RPC_FAR * __RPC_USER HBITMAP_UserMarshal( unsigned long __RPC_FAR *, unsigned char __RPC_FAR *, HBITMAP __RPC_FAR * ); +unsigned char __RPC_FAR * __RPC_USER HBITMAP_UserUnmarshal(unsigned long __RPC_FAR *, unsigned char __RPC_FAR *, HBITMAP __RPC_FAR * ); +void __RPC_USER HBITMAP_UserFree( unsigned long __RPC_FAR *, HBITMAP __RPC_FAR * ); + +unsigned long __RPC_USER HDC_UserSize( unsigned long __RPC_FAR *, unsigned long , HDC __RPC_FAR * ); +unsigned char __RPC_FAR * __RPC_USER HDC_UserMarshal( unsigned long __RPC_FAR *, unsigned char __RPC_FAR *, HDC __RPC_FAR * ); +unsigned char __RPC_FAR * __RPC_USER HDC_UserUnmarshal(unsigned long __RPC_FAR *, unsigned char __RPC_FAR *, HDC __RPC_FAR * ); +void __RPC_USER HDC_UserFree( unsigned long __RPC_FAR *, HDC __RPC_FAR * ); + +/* end of Additional Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/input.c b/src/input.c new file mode 100644 index 0000000..07063ce --- /dev/null +++ b/src/input.c @@ -0,0 +1,191 @@ + +#include "menu.h" + +#if defined(__GP2X__) +#include "usbjoy.h" +static struct usbjoy *joys[4]; +static char joyCount = 0; +static int buttonMap[4][32]; +#endif + +struct INPUT Inp; +static int repeatCounter = 0; +int InputInit() +{ + memset(&Inp,0,sizeof(Inp)); +#if defined(__GP2X__) +int i; + for (i=1; i<5; i++) + { + struct usbjoy *joy = joy_open(i); + if(joy != NULL) + { + joys[joyCount] = joy; + memset(buttonMap[joyCount],0,sizeof(buttonMap[joyCount])); + buttonMap[joyCount][0] = (1<numbuttons<10) + { + buttonMap[joyCount][6] = (1<=0x80) held&=0xbf; // Keep looping around + + Inp.held[i]=held; + } + + // Work out some key repeat values: + for (i=0;i<32;i++) + { + char rep=0; + int held=Inp.held[i]; + + if (held==1) + { + // Key has just been pressed again, so set repeat by default + rep=1; + } + else + { + // Now make sure key has been held for a period of time + // before auto toggling the repeat flag + if (held>=0x20) + { + repeatCounter++; + if(repeatCounter>15) + { + rep=1; + repeatCounter=0; + } + } + } + + Inp.repeat[i]=rep; + } + + return 0; +} diff --git a/src/ioapi.c b/src/ioapi.c new file mode 100644 index 0000000..7f20c18 --- /dev/null +++ b/src/ioapi.c @@ -0,0 +1,177 @@ +/* ioapi.c -- IO base function header for compress/uncompress .zip + files using zlib + zip or unzip API + + Version 1.01e, February 12th, 2005 + + Copyright (C) 1998-2005 Gilles Vollant +*/ + +#include +#include +#include + +#include "zlib.h" +#include "ioapi.h" + + + +/* I've found an old Unix (a SunOS 4.1.3_U1) without all SEEK_* defined.... */ + +#ifndef SEEK_CUR +#define SEEK_CUR 1 +#endif + +#ifndef SEEK_END +#define SEEK_END 2 +#endif + +#ifndef SEEK_SET +#define SEEK_SET 0 +#endif + +voidpf ZCALLBACK fopen_file_func OF(( + voidpf opaque, + const char* filename, + int mode)); + +uLong ZCALLBACK fread_file_func OF(( + voidpf opaque, + voidpf stream, + void* buf, + uLong size)); + +uLong ZCALLBACK fwrite_file_func OF(( + voidpf opaque, + voidpf stream, + const void* buf, + uLong size)); + +long ZCALLBACK ftell_file_func OF(( + voidpf opaque, + voidpf stream)); + +long ZCALLBACK fseek_file_func OF(( + voidpf opaque, + voidpf stream, + uLong offset, + int origin)); + +int ZCALLBACK fclose_file_func OF(( + voidpf opaque, + voidpf stream)); + +int ZCALLBACK ferror_file_func OF(( + voidpf opaque, + voidpf stream)); + + +voidpf ZCALLBACK fopen_file_func (opaque, filename, mode) + voidpf opaque; + const char* filename; + int mode; +{ + FILE* file = NULL; + const char* mode_fopen = NULL; + if ((mode & ZLIB_FILEFUNC_MODE_READWRITEFILTER)==ZLIB_FILEFUNC_MODE_READ) + mode_fopen = "rb"; + else + if (mode & ZLIB_FILEFUNC_MODE_EXISTING) + mode_fopen = "r+b"; + else + if (mode & ZLIB_FILEFUNC_MODE_CREATE) + mode_fopen = "wb"; + + if ((filename!=NULL) && (mode_fopen != NULL)) + file = fopen(filename, mode_fopen); + return file; +} + + +uLong ZCALLBACK fread_file_func (opaque, stream, buf, size) + voidpf opaque; + voidpf stream; + void* buf; + uLong size; +{ + uLong ret; + ret = (uLong)fread(buf, 1, (size_t)size, (FILE *)stream); + return ret; +} + + +uLong ZCALLBACK fwrite_file_func (opaque, stream, buf, size) + voidpf opaque; + voidpf stream; + const void* buf; + uLong size; +{ + uLong ret; + ret = (uLong)fwrite(buf, 1, (size_t)size, (FILE *)stream); + return ret; +} + +long ZCALLBACK ftell_file_func (opaque, stream) + voidpf opaque; + voidpf stream; +{ + long ret; + ret = ftell((FILE *)stream); + return ret; +} + +long ZCALLBACK fseek_file_func (opaque, stream, offset, origin) + voidpf opaque; + voidpf stream; + uLong offset; + int origin; +{ + int fseek_origin=0; + long ret; + switch (origin) + { + case ZLIB_FILEFUNC_SEEK_CUR : + fseek_origin = SEEK_CUR; + break; + case ZLIB_FILEFUNC_SEEK_END : + fseek_origin = SEEK_END; + break; + case ZLIB_FILEFUNC_SEEK_SET : + fseek_origin = SEEK_SET; + break; + default: return -1; + } + ret = 0; + fseek((FILE *)stream, offset, fseek_origin); + return ret; +} + +int ZCALLBACK fclose_file_func (opaque, stream) + voidpf opaque; + voidpf stream; +{ + int ret; + ret = fclose((FILE *)stream); + return ret; +} + +int ZCALLBACK ferror_file_func (opaque, stream) + voidpf opaque; + voidpf stream; +{ + int ret; + ret = ferror((FILE *)stream); + return ret; +} + +void fill_fopen_filefunc (pzlib_filefunc_def) + zlib_filefunc_def* pzlib_filefunc_def; +{ + pzlib_filefunc_def->zopen_file = fopen_file_func; + pzlib_filefunc_def->zread_file = fread_file_func; + pzlib_filefunc_def->zwrite_file = fwrite_file_func; + pzlib_filefunc_def->ztell_file = ftell_file_func; + pzlib_filefunc_def->zseek_file = fseek_file_func; + pzlib_filefunc_def->zclose_file = fclose_file_func; + pzlib_filefunc_def->zerror_file = ferror_file_func; + pzlib_filefunc_def->opaque = NULL; +} diff --git a/src/ioapi.h b/src/ioapi.h new file mode 100644 index 0000000..e73a3b2 --- /dev/null +++ b/src/ioapi.h @@ -0,0 +1,75 @@ +/* ioapi.h -- IO base function header for compress/uncompress .zip + files using zlib + zip or unzip API + + Version 1.01e, February 12th, 2005 + + Copyright (C) 1998-2005 Gilles Vollant +*/ + +#ifndef _ZLIBIOAPI_H +#define _ZLIBIOAPI_H + + +#define ZLIB_FILEFUNC_SEEK_CUR (1) +#define ZLIB_FILEFUNC_SEEK_END (2) +#define ZLIB_FILEFUNC_SEEK_SET (0) + +#define ZLIB_FILEFUNC_MODE_READ (1) +#define ZLIB_FILEFUNC_MODE_WRITE (2) +#define ZLIB_FILEFUNC_MODE_READWRITEFILTER (3) + +#define ZLIB_FILEFUNC_MODE_EXISTING (4) +#define ZLIB_FILEFUNC_MODE_CREATE (8) + + +#ifndef ZCALLBACK + +#if (defined(WIN32) || defined (WINDOWS) || defined (_WINDOWS)) && defined(CALLBACK) && defined (USEWINDOWS_CALLBACK) +#define ZCALLBACK CALLBACK +#else +#define ZCALLBACK +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +typedef voidpf (ZCALLBACK *open_file_func) OF((voidpf opaque, const char* filename, int mode)); +typedef uLong (ZCALLBACK *read_file_func) OF((voidpf opaque, voidpf stream, void* buf, uLong size)); +typedef uLong (ZCALLBACK *write_file_func) OF((voidpf opaque, voidpf stream, const void* buf, uLong size)); +typedef long (ZCALLBACK *tell_file_func) OF((voidpf opaque, voidpf stream)); +typedef long (ZCALLBACK *seek_file_func) OF((voidpf opaque, voidpf stream, uLong offset, int origin)); +typedef int (ZCALLBACK *close_file_func) OF((voidpf opaque, voidpf stream)); +typedef int (ZCALLBACK *testerror_file_func) OF((voidpf opaque, voidpf stream)); + +typedef struct zlib_filefunc_def_s +{ + open_file_func zopen_file; + read_file_func zread_file; + write_file_func zwrite_file; + tell_file_func ztell_file; + seek_file_func zseek_file; + close_file_func zclose_file; + testerror_file_func zerror_file; + voidpf opaque; +} zlib_filefunc_def; + + + +void fill_fopen_filefunc OF((zlib_filefunc_def* pzlib_filefunc_def)); + +#define ZREAD(filefunc,filestream,buf,size) ((*((filefunc).zread_file))((filefunc).opaque,filestream,buf,size)) +#define ZWRITE(filefunc,filestream,buf,size) ((*((filefunc).zwrite_file))((filefunc).opaque,filestream,buf,size)) +#define ZTELL(filefunc,filestream) ((*((filefunc).ztell_file))((filefunc).opaque,filestream)) +#define ZSEEK(filefunc,filestream,pos,mode) ((*((filefunc).zseek_file))((filefunc).opaque,filestream,pos,mode)) +#define ZCLOSE(filefunc,filestream) ((*((filefunc).zclose_file))((filefunc).opaque,filestream)) +#define ZERROR(filefunc,filestream) ((*((filefunc).zerror_file))((filefunc).opaque,filestream)) + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/keycodes.h b/src/keycodes.h new file mode 100644 index 0000000..c721dd6 --- /dev/null +++ b/src/keycodes.h @@ -0,0 +1,108 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#define SCANCODE_K 167 +#define SCANCODE_ESC 197 +#define SCANCODE_CURSORBLOCKRIGHT 175 +#define SCANCODE_CURSORBLOCKLEFT 173 +#define SCANCODE_CURSORBLOCKUP 190 +#define SCANCODE_CURSORBLOCKDOWN 158 +#define SCANCODE_H 165 +#define SCANCODE_N 182 +#define SCANCODE_J 166 +#define SCANCODE_U 150 +#define SCANCODE_ENTER 196 +#define SCANCODE_SPACE 192 +#define SCANCODE_A 160 +#define SCANCODE_V 180 +#define SCANCODE_Q 144 +#define SCANCODE_Z 149 +#define SCANCODE_B 181 +#define SCANCODE_W 145 +#define SCANCODE_S 161 +#define SCANCODE_M 183 +#define SCANCODE_E 146 +#define SCANCODE_X 178 +#define SCANCODE_COMMA 184 +#define SCANCODE_R 147 +#define SCANCODE_D 162 +#define SCANCODE_PERIOD 185 +#define SCANCODE_T 148 +#define SCANCODE_C 179 +#define SCANCODE_SLASH 186 +#define SCANCODE_Y 177 +#define SCANCODE_CURSORRIGHT 206 +#define SCANCODE_CURSORLEFT 207 +#define SCANCODE_CURSORDOWN 205 +#define SCANCODE_CURSORUP 204 +#define SCANCODE_KEYPADENTER 195 +#define SCANCODE_KEYPADPLUS 222 +#define SCANCODE_INSERT 143 +#define SCANCODE_REMOVE 188 +#define SCANCODE_HOME 189 +#define SCANCODE_END 157 +#define SCANCODE_PAGEUP 191 +#define SCANCODE_PAGEDOWN 159 +#define SCANCODE_0 138 +#define SCANCODE_1 129 +#define SCANCODE_2 130 +#define SCANCODE_3 131 +#define SCANCODE_4 132 +#define SCANCODE_5 133 +#define SCANCODE_6 134 +#define SCANCODE_7 135 +#define SCANCODE_8 136 +#define SCANCODE_9 137 +#define SCANCODE_BACKSPACE 193 +#define SCANCODE_F1 208 +#define SCANCODE_F2 209 +#define SCANCODE_F3 210 +#define SCANCODE_F4 211 +#define SCANCODE_F5 212 +#define SCANCODE_F6 213 +#define SCANCODE_F7 214 +#define SCANCODE_F8 215 +#define SCANCODE_F9 216 +#define SCANCODE_F10 217 +#define SCANCODE_F11 198 +#define SCANCODE_F12 223 +#define SCANCODE_P 153 +#define SCANCODE_LESSER 176 +#define SCANCODE_PLUS 155 diff --git a/src/language.h b/src/language.h new file mode 100644 index 0000000..d798c6c --- /dev/null +++ b/src/language.h @@ -0,0 +1,328 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ + +/* This is where all the GUI text strings will eventually end up */ + +#define WINDOW_TITLE "Snes9X v%s for Windows(NK Custom)" + +#define MY_REG_KEY "Software\\Emulators\\Snes9X" + +#define REG_KEY_VER "1.31" + +#define DISCLAIMER_TEXT "Snes9X v%s for Windows.\r\n" \ + "(c) Copyright 1996 - 2002 Gary Henderson and Jerremy Koot.\r\n" \ + "(c) Copyright 2001- 2004 John Weidman.\r\n" \ + "(c) Copyright 2002 - 2004 blip, Brad Jorsch, funkyass, Joel Yliluoma, Kris Bleakley, Matthew Kendora, Nach, Peter Bortas, zones.\r\n\r\n" \ + "Snes9X is a Super Nintendo Entertainment System\r\n" \ + "emulator that allows you to play most games designed\r\n" \ + "for the SNES on your PC.\r\n\r\n" \ + "Please visit http://www.snes9x.com for\r\n" \ + "up-to-the-minute information and help on Snes9X.\r\n\r\n" \ + "Nintendo is a trade mark." + + +#define APP_NAME "Snes9x" +/* possible global strings */ +#define SNES9X_INFO "Snes9x: Information" +#define SNES9X_WARN "Snes9x: WARNING!" +#define SNES9X_DXS "Snes9X: DirectSound" +#define SNES9X_SNDQ "Snes9X: Sound CPU Question" +#define SNES9X_NP_ERROR "Snes9X: NetPlay Error" +#define BUTTON_OK "&OK" +#define BUTTON_CANCEL "&Cancel" + +/* Gamepad Dialog Strings */ +#define INPUTCONFIG_TITLE "Input Configuration" +#define INPUTCONFIG_JPTOGGLE "Enable" +#define INPUTCONFIG_DIAGTOGGLE "Toggle Diagonals" +/* #define INPUTCONFIG_OK "&OK" */ +/* #define INPUTCONFIG_CANCEL "&Cancel" */ +#define INPUTCONFIG_JPCOMBO "Joypad #%d" +#define INPUTCONFIG_LABEL_UP "Up" +#define INPUTCONFIG_LABEL_DOWN "Down" +#define INPUTCONFIG_LABEL_LEFT "Left" +#define INPUTCONFIG_LABEL_RIGHT "Right" +#define INPUTCONFIG_LABEL_A "A" +#define INPUTCONFIG_LABEL_B "B" +#define INPUTCONFIG_LABEL_X "X" +#define INPUTCONFIG_LABEL_Y "Y" +#define INPUTCONFIG_LABEL_L "L" +#define INPUTCONFIG_LABEL_R "R" +#define INPUTCONFIG_LABEL_START "Start" +#define INPUTCONFIG_LABEL_SELECT "Select" +#define INPUTCONFIG_LABEL_UPLEFT "Up Left" +#define INPUTCONFIG_LABEL_UPRIGHT "Up Right" +#define INPUTCONFIG_LABEL_DOWNRIGHT "Down Right" +#define INPUTCONFIG_LABEL_DOWNLEFT "Down Left" +#define INPUTCONFIG_LABEL_BLUE "Blue means the current key/button is already mapped; Red means it's a Snes9x/Windows reserved key." + +/* gaming buttons and axises */ +#define GAMEDEVICE_JOYNUMPREFIX "(J%d)" +#define GAMEDEVICE_JOYBUTPREFIX "#[%d]" +#define GAMEDEVICE_XNEG "Left" +#define GAMEDEVICE_XPOS "Right" +#define GAMEDEVICE_YPOS "Up" +#define GAMEDEVICE_YNEG "Down" +#define GAMEDEVICE_POVLEFT "POV Left" +#define GAMEDEVICE_POVRIGHT "POV Right" +#define GAMEDEVICE_POVUP "POV Up" +#define GAMEDEVICE_POVDOWN "POV Down" +#define GAMEDEVICE_POVDNLEFT "POV Dn Left" +#define GAMEDEVICE_POVDNRIGHT "POV Dn Right" +#define GAMEDEVICE_POVUPLEFT "POV Up Left" +#define GAMEDEVICE_POVUPRIGHT "POV Up Right" +#define GAMEDEVICE_ZPOS "Z Up" +#define GAMEDEVICE_ZNEG "Z Down" +#define GAMEDEVICE_RPOS "R Up" +#define GAMEDEVICE_RNEG "R Down" +#define GAMEDEVICE_UPOS "U Up" +#define GAMEDEVICE_UNEG "U Down" +#define GAMEDEVICE_VPOS "V Up" +#define GAMEDEVICE_VNEG "V Down" +#define GAMEDEVICE_BUTTON "Button %d" + +/* gaming general */ +#define GAMEDEVICE_DISABLED "Disabled" + +/* gaming keys */ +#define GAMEDEVICE_KEY "#%d" +#define GAMEDEVICE_NUMPADPREFIX "Numpad-%c" +#define GAMEDEVICE_VK_TAB "Tab" +#define GAMEDEVICE_VK_BACK "Backspace" +#define GAMEDEVICE_VK_CLEAR "Delete" +#define GAMEDEVICE_VK_RETURN "Enter" +#define GAMEDEVICE_VK_LSHIFT "LShift" +#define GAMEDEVICE_VK_RSHIFT "RShift" +#define GAMEDEVICE_VK_LCONTROL "LCTRL" +#define GAMEDEVICE_VK_RCONTROL "RCTRL" +#define GAMEDEVICE_VK_LMENU "LAlt" +#define GAMEDEVICE_VK_RMENU "RAlt" +#define GAMEDEVICE_VK_PAUSE "Pause" +#define GAMEDEVICE_VK_CAPITAL "Capslock" +#define GAMEDEVICE_VK_ESCAPE "Disabled" +#define GAMEDEVICE_VK_SPACE "Space" +#define GAMEDEVICE_VK_PRIOR "PgUp" +#define GAMEDEVICE_VK_NEXT "PgDn" +#define GAMEDEVICE_VK_HOME "Home" +#define GAMEDEVICE_VK_END "End" +#define GAMEDEVICE_VK_LEFT "Left" +#define GAMEDEVICE_VK_RIGHT "Right" +#define GAMEDEVICE_VK_UP "Up" +#define GAMEDEVICE_VK_DOWN "Down" +#define GAMEDEVICE_VK_SELECT "Select" +#define GAMEDEVICE_VK_PRINT "Print" +#define GAMEDEVICE_VK_EXECUTE "Execute" +#define GAMEDEVICE_VK_SNAPSHOT "SnapShot" +#define GAMEDEVICE_VK_INSERT "Insert" +#define GAMEDEVICE_VK_DELETE "Delete" +#define GAMEDEVICE_VK_HELP "Help" +#define GAMEDEVICE_VK_LWIN "LWinKey" +#define GAMEDEVICE_VK_RWIN "RWinKey" +#define GAMEDEVICE_VK_APPS "AppKey" +#define GAMEDEVICE_VK_MULTIPLY "Numpad *" +#define GAMEDEVICE_VK_ADD "Numpad +" +#define GAMEDEVICE_VK_SEPARATOR "\\" +#define GAMEDEVICE_VK_OEM_1 "Semi-Colon" +#define GAMEDEVICE_VK_OEM_7 "Apostrophe" +#define GAMEDEVICE_VK_OEM_COMMA "Comma" +#define GAMEDEVICE_VK_OEM_PERIOD "Period" +#define GAMEDEVICE_VK_SUBTRACT "Numpad -" +#define GAMEDEVICE_VK_DECIMAL "Numpad ." +#define GAMEDEVICE_VK_DIVIDE "Numpad /" +#define GAMEDEVICE_VK_NUMLOCK "Num-lock" +#define GAMEDEVICE_VK_SCROLL "Scroll-lock" + +/* evil things I found in WinProc */ + +#define WINPROC_TURBOMODE_ON "Turbo Mode Activated" +#define WINPROC_TURBOMODE_OFF "Turbo Mode Deactivated" +#define WINPROC_TURBOMODE_TEXT "Turbo Mode" +#define WINPROC_HDMA_TEXT "HDMA emulation" +#define WINPROC_BG1 "BG#1" /* Background Layers */ +#define WINPROC_BG2 "BG#2" +#define WINPROC_BG3 "BG#3" +#define WINPROC_BG4 "BG#4" +#define WINPROC_SPRITES "Sprites" +#define WINPROC_PADSWAP "Joypad swapping" +#define WINPROC_CONTROLERS0 "Multiplayer 5 on #0" +#define WINPROC_CONTROLERS1 "Joypad on #0" +#define WINPROC_CONTROLERS2 "Mouse on #1" +#define WINPROC_CONTROLERS3 "Mouse on #0" +#define WINPROC_CONTROLERS4 "Superscope on #1" +#define WINPROC_CONTROLERS5 "Justifier 1 on #1" +#define WINPROC_CONTROLERS6 "Justifier 2 on #1" +#define WINPROC_BGHACK "Background layering hack" +#define WINPROC_MODE7INTER "Mode 7 Interpolation" +#define WINPROC_TRANSPARENCY "Transparency effects" +#define WINPROC_CLIPWIN "Graphic clip windows" +#define WINPROC_PAUSE "Pause" +#define WINPROC_EMUFRAMETIME "Emulated frame time: %dms" +#define WINPROC_AUTOSKIP "Auto Frame Skip" +#define WINPROC_FRAMESKIP "Frame skip: %d" +#define WINPROC_TURBO_R_ON "Turbo R Activated" +#define WINPROC_TURBO_R_OFF "Turbo R Deactivated" +#define WINPROC_TURBO_L_ON "Turbo L Activated" +#define WINPROC_TURBO_L_OFF "Turbo L Deactivated" +#define WINPROC_TURBO_X_ON "Turbo X Activated" +#define WINPROC_TURBO_X_OFF "Turbo X Deactivated" +#define WINPROC_TURBO_Y_ON "Turbo Y Activated" +#define WINPROC_TURBO_Y_OFF "Turbo Y Deactivated" +#define WINPROC_TURBO_A_ON "Turbo A Activated" +#define WINPROC_TURBO_A_OFF "Turbo A Deactivated" +#define WINPROC_TURBO_B_ON "Turbo B Activated" +#define WINPROC_TURBO_B_OFF "Turbo B Deactivated" +#define WINPROC_TURBO_SEL_ON "Turbo Select Activated" +#define WINPROC_TURBO_SEL_OFF "Turbo Select Deactivated" +#define WINPROC_TURBO_START_ON "Turbo Start Activated" +#define WINPROC_TURBO_START_OFF "Turbo Start Deactivated" +#define WINPROC_FILTER_RESTART "You will need to restart Snes9x before the output image\nprocessing option change will take effect." +#define WINPROC_DISCONNECT "Disconnect from the NetPlay server first." +#define WINPROC_NET_RESTART "Your game will be reset after the ROM has been sent due to\nyour 'Sync Using Reset Game' setting.\n\n" +#define WINPROC_INTERPOLATED_SND "Interpolated sound" +#define WINPROC_SYNC_SND "Sync sound" +#define WINPROC_SND_OFF "Disabling the sound CPU emulation will help to improve\nemulation speed but you will not hear any sound effects\nor music. If you later want to re-enable the sound CPU\nemulation you will need to reset your game before it will\ntake effect.\n\nAre you sure this is what you want?" +#define WINPROC_SND_RESTART "You will need to reset your game or load another one\nbefore enabling the sound CPU will take effect." + +/* Emulator Settings */ + +#define EMUSET_TITLE "Emulation Settings" +#define EMUSET_LABEL_FREEZE "Freeze Folder Directory" +#define EMUSET_BROWSE "&Browse..." +#define EMUSET_LABEL_ASRAM "Auto-Save S-RAM" +#define EMUSET_LABEL_ASRAM_TEXT "seconds after last change (0 disables auto-save)" +#define EMUSET_LABEL_SMAX "Skip at most" +#define EMUSET_LABEL_SMAX_TEXT "frames in auto-frame rate mode" +#define EMUSET_LABEL_STURBO "Skip Rendering" +#define EMUSET_LABEL_STURBO_TEXT "frames in Turbo mode" +#define EMUSET_TOGGLE_TURBO "Tab Toggles Turbo" + +/* Netplay Options */ + +#define NPOPT_TITLE "Netplay Options" +#define NPOPT_LABEL_PORTNUM "Socket Port Number" +#define NPOPT_LABEL_PAUSEINTERVAL "Ask Server to Pause when" +#define NPOPT_LABEL_PAUSEINTERVAL_TEXT "frames behind" +#define NPOPT_LABEL_MAXSKIP "Maximum Frame Rate Skip" +#define NPOPT_SYNCBYRESET "Sync By Reset" +#define NPOPT_SENDROM "Send ROM Image to Client on Connect" +#define NPOPT_ACTASSERVER "Act As Server" +#define NPOPT_PORTNUMBLOCK "Port Settings" +#define NPOPT_CLIENTSETTINGSBLOCK "Client Settings" +#define NPOPT_SERVERSETTINGSBLOCK "Server Settings" + +/* Netplay Connect */ + + +#define NPCON_TITLE "Connect to Server" +#define NPCON_LABEL_SERVERADDY "Server Address" +#define NPCON_LABEL_PORTNUM "Port Number" +#define NPCON_CLEARHISTORY "Clear History" + + +/* Movie Messages */ + +#define MOVIE_INFO_REPLAY "Movie replay" +#define MOVIE_INFO_RECORD "Movie record" +#define MOVIE_INFO_RERECORD "Movie re-record" +#define MOVIE_INFO_REWIND "Movie rewind" +#define MOVIE_INFO_STOP "Movie stop" +#define MOVIE_INFO_END "Movie end" +#define MOVIE_INFO_RECORDING_ENABLED "Recording enabled" +#define MOVIE_INFO_RECORDING_DISABLED "Recording disabled" +#define MOVIE_ERR_SNAPSHOT_WRONG_MOVIE "Snapshot not from this movie" +#define MOVIE_ERR_SNAPSHOT_NOT_MOVIE "Not a movie snapshot" +#define MOVIE_ERR_COULD_NOT_OPEN "Could not open movie file." +#define MOVIE_ERR_NOT_FOUND "File not found." +#define MOVIE_ERR_WRONG_FORMAT "File is wrong format." +#define MOVIE_ERR_WRONG_VERSION "File is wrong version." + + +/* AVI Messages */ + +#define AVI_CONFIGURATION_CHANGED "AVI recording stopped (configuration settings changed)." diff --git a/src/loadzip.cpp b/src/loadzip.cpp new file mode 100644 index 0000000..1bbcaac --- /dev/null +++ b/src/loadzip.cpp @@ -0,0 +1,220 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#include "port.h" + +#ifdef UNZIP_SUPPORT +/**********************************************************************************************/ +/* Loadzip.CPP */ +/* This file contains a function for loading a SNES ROM image from a zip file */ +/**********************************************************************************************/ + +#include +#include + +#ifndef NO_INLINE_SET_GET +#define NO_INLINE_SET_GET +#endif + +#include "snes9x.h" +#include "memmap.h" + +#include "unzip.h" +//#include +#include +#include + +bool8 LoadZip(const char* zipname, + int32 *TotalFileSize, + int32 *headers) +{ + *TotalFileSize = 0; + *headers = 0; + + unzFile file = unzOpen(zipname); + if(file == NULL) + return (FALSE); + + // find largest file in zip file (under MAX_ROM_SIZE) + // or a file with extension .1 + char filename[132]; + int filesize = 0; + int port = unzGoToFirstFile(file); + unz_file_info info; + while(port == UNZ_OK) + { + char name[132]; + unzGetCurrentFileInfo(file, &info, name,128, NULL,0, NULL,0); + +#if 0 + int calc_size = info.uncompressed_size / 0x2000; + calc_size *= 0x2000; + if(!(info.uncompressed_size - calc_size == 512 || info.uncompressed_size == calc_size)) + { + port = unzGoToNextFile(file); + continue; + } +#endif + + if(info.uncompressed_size > (CMemory::MAX_ROM_SIZE + 512)) + { + port = unzGoToNextFile(file); + continue; + } + + if ((int) info.uncompressed_size > filesize) + { + strcpy(filename,name); + filesize = info.uncompressed_size; + } + int len = strlen(name); + if(name[len-2] == '.' && name[len-1] == '1') + { + strcpy(filename,name); + filesize = info.uncompressed_size; + break; + } + port = unzGoToNextFile(file); + } + if( !(port == UNZ_END_OF_LIST_OF_FILE || port == UNZ_OK) || filesize == 0) + { + unzClose(file); + return (FALSE); + } + + // Find extension + char tmp[2]; + tmp[0] = tmp[1] = 0; + char *ext = strrchr(filename,'.'); + if(ext) ext++; + else ext = tmp; + + uint8 *ptr = Memory.ROM; + bool8 more = FALSE; + + unzLocateFile(file,filename,1); + unzGetCurrentFileInfo(file, &info, filename,128, NULL,0, NULL,0); + + if( unzOpenCurrentFile(file) != UNZ_OK ) + { + unzClose(file); + return (FALSE); + } + + do + { +// assert(info.uncompressed_size <= CMemory::MAX_ROM_SIZE + 512); + int FileSize = info.uncompressed_size; + + int calc_size = FileSize / 0x2000; + calc_size *= 0x2000; + + int l = unzReadCurrentFile(file,ptr,FileSize); + if(unzCloseCurrentFile(file) == UNZ_CRCERROR) + { + unzClose(file); + return (FALSE); + } + + if(l <= 0 || l != FileSize) + { + unzClose(file); + switch(l) + { + case UNZ_ERRNO: + break; + case UNZ_EOF: + break; + case UNZ_PARAMERROR: + break; + case UNZ_BADZIPFILE: + break; + case UNZ_INTERNALERROR: + break; + case UNZ_CRCERROR: + break; + } + return (FALSE); + } + + if ((FileSize - calc_size == 512 && !Settings.ForceNoHeader) || + Settings.ForceHeader) + { + memmove (ptr, ptr + 512, calc_size); + (*headers)++; + FileSize -= 512; + } + ptr += FileSize; + (*TotalFileSize) += FileSize; + + int len; + if (ptr - Memory.ROM < CMemory::MAX_ROM_SIZE + 0x200 && + (isdigit (ext [0]) && ext [1] == 0 && ext [0] < '9')) + { + more = TRUE; + ext [0]++; + } + else if (ptr - Memory.ROM < CMemory::MAX_ROM_SIZE + 0x200 && + (((len = strlen (filename)) == 7 || len == 8) && + strncasecmp (filename, "sf", 2) == 0 && + isdigit (filename [2]) && isdigit (filename [3]) && isdigit (filename [4]) && + isdigit (filename [5]) && isalpha (filename [len - 1]))) + { + more = TRUE; + filename [len - 1]++; + } + else + more = FALSE; + + if(more) + { + if( unzLocateFile(file,filename,1) != UNZ_OK || + unzGetCurrentFileInfo(file, &info, filename,128, NULL,0, NULL,0) != UNZ_OK || + unzOpenCurrentFile(file) != UNZ_OK) + break; + } + + } while(more); + + unzClose(file); + return (TRUE); +} +#endif diff --git a/src/lodepng.c b/src/lodepng.c new file mode 100644 index 0000000..4aade60 --- /dev/null +++ b/src/lodepng.c @@ -0,0 +1,5271 @@ +/* +LodePNG version 20110221 + +Copyright (c) 2005-2011 Lode Vandevenne + +This software is provided 'as-is', without any express or implied +warranty. In no event will the authors be held liable for any damages +arising from the use of this software. + +Permission is granted to anyone to use this software for any purpose, +including commercial applications, and to alter it and redistribute it +freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + + 3. This notice may not be removed or altered from any source + distribution. +*/ + +/* +The manual and changelog can be found in the header file "lodepng.h" +Rename this file to lodepng.cpp to use it for C++, or to lodepng.c to use it for C. +*/ + +#include "lodepng.h" + +#include +#include + +#ifdef __cplusplus +#include +#endif /*__cplusplus*/ + +#define VERSION_STRING "20110221" + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Tools For C / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +About these tools (vector, uivector, ucvector and string): +-LodePNG was originally written in C++. The vectors replace the std::vectors that were used in the C++ version. +-The string tools are made to avoid problems with compilers that declare things like strncat as deprecated. +-They're not used in the interface, only internally in this file, so all their functions are made static. +*/ + +#ifdef LODEPNG_COMPILE_ZLIB +#ifdef LODEPNG_COMPILE_ENCODER + +typedef struct vector /*dynamic vector of void* pointers. This one is used only by the deflate compressor*/ +{ + void* data; + size_t size; /*in groups of bytes depending on type*/ + size_t allocsize; /*in bytes*/ + unsigned typesize; /*sizeof the type you store in data*/ +} vector; + +static unsigned vector_resize(vector* p, size_t size) /*returns 1 if success, 0 if failure ==> nothing done*/ +{ + if(size * p->typesize > p->allocsize) + { + size_t newsize = size * p->typesize * 2; + void* data = realloc(p->data, newsize); + if(data) + { + p->allocsize = newsize; + p->data = data; + p->size = size; + } + else return 0; + } + else p->size = size; + return 1; +} + +static unsigned vector_resized(vector* p, size_t size, void dtor(void*)) /*resize and use destructor on elements if it gets smaller*/ +{ + size_t i; + if(size < p->size) + { + for(i = size; i < p->size; i++) + { + dtor(&((char*)(p->data))[i * p->typesize]); + } + } + return vector_resize(p, size); +} + +static void vector_cleanup(void* p) +{ + ((vector*)p)->size = ((vector*)p)->allocsize = 0; + free(((vector*)p)->data); + ((vector*)p)->data = NULL; +} + +static void vector_cleanupd(vector* p, void dtor(void*)) /*clear and use destructor on elements*/ +{ + vector_resized(p, 0, dtor); + vector_cleanup(p); +} + +static void vector_init(vector* p, unsigned typesize) +{ + p->data = NULL; + p->size = p->allocsize = 0; + p->typesize = typesize; +} + +static void vector_swap(vector* p, vector* q) /*they're supposed to have the same typesize*/ +{ + size_t tmp; + void* tmpp; + tmp = p->size; p->size = q->size; q->size = tmp; + tmp = p->allocsize; p->allocsize = q->allocsize; q->allocsize = tmp; + tmpp = p->data; p->data = q->data; q->data = tmpp; +} + +static void* vector_get(vector* p, size_t index) +{ + return &((char*)p->data)[index * p->typesize]; +} + +#endif /*LODEPNG_COMPILE_ENCODER*/ +#endif /*LODEPNG_COMPILE_ZLIB*/ + +/* /////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_ZLIB +typedef struct uivector /*dynamic vector of unsigned ints*/ +{ + unsigned* data; + size_t size; /*size in number of unsigned longs*/ + size_t allocsize; /*allocated size in bytes*/ +} uivector; + +static void uivector_cleanup(void* p) +{ + ((uivector*)p)->size = ((uivector*)p)->allocsize = 0; + free(((uivector*)p)->data); + ((uivector*)p)->data = NULL; +} + +static unsigned uivector_resize(uivector* p, size_t size) /*returns 1 if success, 0 if failure ==> nothing done*/ +{ + if(size * sizeof(unsigned) > p->allocsize) + { + size_t newsize = size * sizeof(unsigned) * 2; + void* data = realloc(p->data, newsize); + if(data) + { + p->allocsize = newsize; + p->data = (unsigned*)data; + p->size = size; + } + else return 0; + } + else p->size = size; + return 1; +} + +static unsigned uivector_resizev(uivector* p, size_t size, unsigned value) /*resize and give all new elements the value*/ +{ + size_t oldsize = p->size, i; + if(!uivector_resize(p, size)) return 0; + for(i = oldsize; i < size; i++) p->data[i] = value; + return 1; +} + +static void uivector_init(uivector* p) +{ + p->data = NULL; + p->size = p->allocsize = 0; +} + +#ifdef LODEPNG_COMPILE_ENCODER +static unsigned uivector_push_back(uivector* p, unsigned c) /*returns 1 if success, 0 if failure ==> nothing done*/ +{ + if(!uivector_resize(p, p->size + 1)) return 0; + p->data[p->size - 1] = c; + return 1; +} + +static unsigned uivector_copy(uivector* p, const uivector* q) /*copy q to p, returns 1 if success, 0 if failure ==> nothing done*/ +{ + size_t i; + if(!uivector_resize(p, q->size)) return 0; + for(i = 0; i < q->size; i++) p->data[i] = q->data[i]; + return 1; +} + +static void uivector_swap(uivector* p, uivector* q) +{ + size_t tmp; + unsigned* tmpp; + tmp = p->size; p->size = q->size; q->size = tmp; + tmp = p->allocsize; p->allocsize = q->allocsize; q->allocsize = tmp; + tmpp = p->data; p->data = q->data; q->data = tmpp; +} +#endif /*LODEPNG_COMPILE_ENCODER*/ +#endif /*LODEPNG_COMPILE_ZLIB*/ + +/* /////////////////////////////////////////////////////////////////////////// */ + +typedef struct ucvector /*dynamic vector of unsigned chars*/ +{ + unsigned char* data; + size_t size; /*used size*/ + size_t allocsize; /*allocated size*/ +} ucvector; + +static void ucvector_cleanup(void* p) +{ + ((ucvector*)p)->size = ((ucvector*)p)->allocsize = 0; + free(((ucvector*)p)->data); + ((ucvector*)p)->data = NULL; +} + +static unsigned ucvector_resize(ucvector* p, size_t size) /*returns 1 if success, 0 if failure ==> nothing done*/ +{ + if(size * sizeof(unsigned char) > p->allocsize) + { + size_t newsize = size * sizeof(unsigned char) * 2; + void* data = realloc(p->data, newsize); + if(data) + { + p->allocsize = newsize; + p->data = (unsigned char*)data; + p->size = size; + } + else return 0; /*error: not enough memory*/ + } + else p->size = size; + return 1; +} + +#ifdef LODEPNG_COMPILE_DECODER +#ifdef LODEPNG_COMPILE_PNG +static unsigned ucvector_resizev(ucvector* p, size_t size, unsigned char value) /*resize and give all new elements the value*/ +{ + size_t oldsize = p->size, i; + if(!ucvector_resize(p, size)) return 0; + for(i = oldsize; i < size; i++) p->data[i] = value; + return 1; +} +#endif /*LODEPNG_COMPILE_PNG*/ +#endif /*LODEPNG_COMPILE_DECODER*/ + +static void ucvector_init(ucvector* p) +{ + p->data = NULL; + p->size = p->allocsize = 0; +} + +#ifdef LODEPNG_COMPILE_ZLIB +/*you can both convert from vector to buffer&size and vica versa*/ +static void ucvector_init_buffer(ucvector* p, unsigned char* buffer, size_t size) +{ + p->data = buffer; + p->allocsize = p->size = size; +} +#endif /*LODEPNG_COMPILE_ZLIB*/ + +static unsigned ucvector_push_back(ucvector* p, unsigned char c) /*returns 1 if success, 0 if failure ==> nothing done*/ +{ + if(!ucvector_resize(p, p->size + 1)) return 0; + p->data[p->size - 1] = c; + return 1; +} + +/* /////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_PNG +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS +static unsigned string_resize(char** out, size_t size) /*returns 1 if success, 0 if failure ==> nothing done*/ +{ + char* data = (char*)realloc(*out, size + 1); + if(data) + { + data[size] = 0; /*null termination char*/ + *out = data; + } + return data != 0; +} + +static void string_init(char** out) /*init a {char*, size_t} pair for use as string*/ +{ + *out = NULL; + string_resize(out, 0); +} + +static void string_cleanup(char** out) /*free the above pair again*/ +{ + free(*out); + *out = NULL; +} + +static void string_set(char** out, const char* in) +{ + size_t insize = strlen(in), i = 0; + if(string_resize(out, insize)) + { + for(i = 0; i < insize; i++) + { + (*out)[i] = in[i]; + } + } +} +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ +#endif /*LODEPNG_COMPILE_PNG*/ + +#ifdef LODEPNG_COMPILE_ZLIB + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Reading and writing single bits and bytes from/to stream for Deflate / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_ENCODER +static void addBitToStream(size_t* bitpointer, ucvector* bitstream, unsigned char bit) +{ + if((*bitpointer) % 8 == 0) ucvector_push_back(bitstream, (unsigned char)0); /*add a new byte at the end*/ + (bitstream->data[bitstream->size - 1]) |= (bit << ((*bitpointer) & 0x7)); /*earlier bit of huffman code is in a lesser significant bit of an earlier byte*/ + (*bitpointer)++; +} + +static void addBitsToStream(size_t* bitpointer, ucvector* bitstream, unsigned value, size_t nbits) +{ + size_t i; + for(i = 0; i < nbits; i++) addBitToStream(bitpointer, bitstream, (unsigned char)((value >> i) & 1)); +} + +static void addBitsToStreamReversed(size_t* bitpointer, ucvector* bitstream, unsigned value, size_t nbits) +{ + size_t i; + for(i = 0; i < nbits; i++) addBitToStream(bitpointer, bitstream, (unsigned char)((value >> (nbits - 1 - i)) & 1)); +} +#endif /*LODEPNG_COMPILE_ENCODER*/ + +#ifdef LODEPNG_COMPILE_DECODER + +#define READBIT(bitpointer, bitstream) ((bitstream[bitpointer >> 3] >> (bitpointer & 0x7)) & (unsigned char)1) + +static unsigned char readBitFromStream(size_t* bitpointer, const unsigned char* bitstream) +{ + unsigned char result = (unsigned char)(READBIT(*bitpointer, bitstream)); + (*bitpointer)++; + return result; +} + +static unsigned readBitsFromStream(size_t* bitpointer, const unsigned char* bitstream, size_t nbits) +{ + unsigned result = 0, i; + for(i = 0; i < nbits; i++) + { + result += ((unsigned)READBIT(*bitpointer, bitstream)) << i; + (*bitpointer)++; + } + return result; +} +#endif /*LODEPNG_COMPILE_DECODER*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Deflate - Huffman / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +#define FIRST_LENGTH_CODE_INDEX 257 +#define LAST_LENGTH_CODE_INDEX 285 +#define NUM_DEFLATE_CODE_SYMBOLS 288 /*256 literals, the end code, some length codes, and 2 unused codes*/ +#define NUM_DISTANCE_SYMBOLS 32 /*the distance codes have their own symbols, 30 used, 2 unused*/ +#define NUM_CODE_LENGTH_CODES 19 /*the code length codes. 0-15: code lengths, 16: copy previous 3-6 times, 17: 3-10 zeros, 18: 11-138 zeros*/ + +static const unsigned LENGTHBASE[29] /*the base lengths represented by codes 257-285*/ + = {3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31, 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258}; +static const unsigned LENGTHEXTRA[29] /*the extra bits used by codes 257-285 (added to base length)*/ + = {0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0}; +static const unsigned DISTANCEBASE[30] /*the base backwards distances (the bits of distance codes appear after length codes and use their own huffman tree)*/ + = {1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193, 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145, 8193, 12289, 16385, 24577}; +static const unsigned DISTANCEEXTRA[30] /*the extra bits of backwards distances (added to base)*/ + = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13}; +static const unsigned CLCL[NUM_CODE_LENGTH_CODES] /*the order in which "code length alphabet code lengths" are stored, out of this the huffman tree of the dynamic huffman tree lengths is generated*/ + = {16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15}; + +/* /////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_ENCODER +/* +A coin, this is the terminology used for the package-merge algorithm and the +coin collector's problem. This is used to generate the huffman tree. +A coin can be multiple coins (when they're merged) +*/ +typedef struct Coin +{ + uivector symbols; + float weight; /*the sum of all weights in this coin*/ +} Coin; + +static void Coin_init(Coin* c) +{ + uivector_init(&c->symbols); +} + +static void Coin_cleanup(void* c) /*void* so that this dtor can be given as function pointer to the vector resize function*/ +{ + uivector_cleanup(&((Coin*)c)->symbols); +} + +static void Coin_copy(Coin* c1, const Coin* c2) +{ + c1->weight = c2->weight; + uivector_copy(&c1->symbols, &c2->symbols); +} + +static void addCoins(Coin* c1, const Coin* c2) +{ + size_t i; + for(i = 0; i < c2->symbols.size; i++) uivector_push_back(&c1->symbols, c2->symbols.data[i]); + c1->weight += c2->weight; +} + +/* +Coin_sort: This uses a simple combsort to sort the data. This function is not critical for +overall encoding speed and the data amount isn't that large. +*/ +static void Coin_sort(Coin* data, size_t amount) +{ + size_t gap = amount; + unsigned char swapped = 0; + while((gap > 1) || swapped) + { + size_t i; + gap = (gap * 10) / 13; /*shrink factor 1.3*/ + if(gap == 9 || gap == 10) gap = 11; /*combsort11*/ + if(gap < 1) gap = 1; + swapped = 0; + for(i = 0; i < amount - gap; i++) + { + size_t j = i + gap; + if(data[j].weight < data[i].weight) + { + float temp = data[j].weight; data[j].weight = data[i].weight; data[i].weight = temp; + uivector_swap(&data[i].symbols, &data[j].symbols); + swapped = 1; + } + } + } +} +#endif /*LODEPNG_COMPILE_ENCODER*/ + +/* +Huffman tree struct, containing multiple representations of the tree +*/ +typedef struct HuffmanTree +{ + uivector tree2d; + uivector tree1d; + uivector lengths; /*the lengths of the codes of the 1d-tree*/ + unsigned maxbitlen; /*maximum number of bits a single code can get*/ + unsigned numcodes; /*number of symbols in the alphabet = number of codes*/ +} HuffmanTree; + +/*function used for debug purposes*/ +/*#include +static void HuffmanTree_draw(HuffmanTree* tree) +{ + std::cout << "tree. length: " << tree->numcodes << " maxbitlen: " << tree->maxbitlen << std::endl; + for(size_t i = 0; i < tree->tree1d.size; i++) + { + if(tree->lengths.data[i]) + std::cout << i << " " << tree->tree1d.data[i] << " " << tree->lengths.data[i] << std::endl; + } + std::cout << std::endl; +}*/ + +static void HuffmanTree_init(HuffmanTree* tree) +{ + uivector_init(&tree->tree2d); + uivector_init(&tree->tree1d); + uivector_init(&tree->lengths); +} + +static void HuffmanTree_cleanup(HuffmanTree* tree) +{ + uivector_cleanup(&tree->tree2d); + uivector_cleanup(&tree->tree1d); + uivector_cleanup(&tree->lengths); +} + +/*the tree representation used by the decoder. return value is error*/ +static unsigned HuffmanTree_make2DTree(HuffmanTree* tree) +{ + unsigned nodefilled = 0; /*up to which node it is filled*/ + unsigned treepos = 0; /*position in the tree (1 of the numcodes columns)*/ + unsigned n, i; + + if(!uivector_resize(&tree->tree2d, tree->numcodes * 2)) return 9901; + /*convert tree1d[] to tree2d[][]. In the 2D array, a value of 32767 means uninited, a value >= numcodes is an address to another bit, a value < numcodes is a code. The 2 rows are the 2 possible bit values (0 or 1), there are as many columns as codes - 1 + a good huffmann tree has N * 2 - 1 nodes, of which N - 1 are internal nodes. Here, the internal nodes are stored (what their 0 and 1 option point to). There is only memory for such good tree currently, if there are more nodes (due to too long length codes), error 55 will happen*/ + for(n = 0; n < tree->numcodes * 2; n++) tree->tree2d.data[n] = 32767; /*32767 here means the tree2d isn't filled there yet*/ + + for(n = 0; n < tree->numcodes; n++) /*the codes*/ + { + for(i = 0; i < tree->lengths.data[n]; i++) /*the bits for this code*/ + { + unsigned char bit = (unsigned char)((tree->tree1d.data[n] >> (tree->lengths.data[n] - i - 1)) & 1); + if(treepos > tree->numcodes - 2) return 55; /*error 55: oversubscribed; see description in header*/ + if(tree->tree2d.data[2 * treepos + bit] == 32767) /*not yet filled in*/ + { + if(i + 1 == tree->lengths.data[n]) /*last bit*/ + { + tree->tree2d.data[2 * treepos + bit] = n; /*put the current code in it*/ + treepos = 0; + } + else /*put address of the next step in here, first that address has to be found of course (it's just nodefilled + 1)...*/ + { + nodefilled++; + tree->tree2d.data[2 * treepos + bit] = nodefilled + tree->numcodes; /*addresses encoded with numcodes added to it*/ + treepos = nodefilled; + } + } + else treepos = tree->tree2d.data[2 * treepos + bit] - tree->numcodes; + } + } + + for(n = 0; n < tree->numcodes * 2; n++) + { + if(tree->tree2d.data[n] == 32767) tree->tree2d.data[n] = 0; /*remove possible remaining 32767's*/ + } + + return 0; +} + +/* +HuffmanTree_makeFromLengths2 +numcodes, lengths and maxbitlen must already be filled in correctly. +return value is error. +*/ +static unsigned HuffmanTree_makeFromLengths2(HuffmanTree* tree) +{ + uivector blcount; + uivector nextcode; + unsigned bits, n, error = 0; + + uivector_init(&blcount); + uivector_init(&nextcode); + if(!uivector_resize(&tree->tree1d, tree->numcodes) + || !uivector_resizev(&blcount, tree->maxbitlen + 1, 0) + || !uivector_resizev(&nextcode, tree->maxbitlen + 1, 0)) + error = 9902; /*memory allocation failed*/ + + if(!error) + { + /*step 1: count number of instances of each code length*/ + for(bits = 0; bits < tree->numcodes; bits++) blcount.data[tree->lengths.data[bits]]++; + /*step 2: generate the nextcode values*/ + for(bits = 1; bits <= tree->maxbitlen; bits++) nextcode.data[bits] = (nextcode.data[bits - 1] + blcount.data[bits - 1]) << 1; + /*step 3: generate all the codes*/ + for(n = 0; n < tree->numcodes; n++) if(tree->lengths.data[n] != 0) tree->tree1d.data[n] = nextcode.data[tree->lengths.data[n]]++; + } + + uivector_cleanup(&blcount); + uivector_cleanup(&nextcode); + + if(!error) return HuffmanTree_make2DTree(tree); + else return error; +} + +/* +HuffmanTree_makeFromLengths +given the code lengths (as stored in the PNG file), generate the tree as defined +by Deflate. maxbitlen is the maximum bits that a code in the tree can have. +return value is error. +*/ +static unsigned HuffmanTree_makeFromLengths(HuffmanTree* tree, const unsigned* bitlen, size_t numcodes, unsigned maxbitlen) +{ + unsigned i; + if(!uivector_resize(&tree->lengths, numcodes)) return 9903; + for(i = 0; i < numcodes; i++) tree->lengths.data[i] = bitlen[i]; + tree->numcodes = (unsigned)numcodes; /*number of symbols*/ + tree->maxbitlen = maxbitlen; + return HuffmanTree_makeFromLengths2(tree); +} + +#ifdef LODEPNG_COMPILE_ENCODER +static unsigned HuffmanTree_fillInCoins(vector* coins, const unsigned* frequencies, unsigned numcodes, size_t sum) +{ + unsigned i; + for(i = 0; i < numcodes; i++) + { + Coin* coin; + if(frequencies[i] == 0) continue; /*it's important to exclude symbols that aren't present*/ + if(!vector_resize(coins, coins->size + 1)) + { + vector_cleanup(coins); + return 9904; /*memory allocation failed*/ + } + coin = (Coin*)(vector_get(coins, coins->size - 1)); + Coin_init(coin); + coin->weight = frequencies[i] / (float)sum; + uivector_push_back(&coin->symbols, i); + } + if(coins->size) Coin_sort((Coin*)coins->data, coins->size); + return 0; +} + +/* +HuffmanTree_makeFromFrequencies +Create the Huffman tree given the symbol frequencies +*/ +static unsigned HuffmanTree_makeFromFrequencies(HuffmanTree* tree, const unsigned* frequencies, size_t numcodes, unsigned maxbitlen) +{ + unsigned i, j; + size_t sum = 0, numpresent = 0; + unsigned error = 0; + + vector prev_row; /*type Coin, the previous row of coins*/ + vector coins; /*type Coin, the coins of the currently calculated row*/ + + tree->maxbitlen = maxbitlen; + + for(i = 0; i < numcodes; i++) + { + if(frequencies[i] > 0) + { + numpresent++; + sum += frequencies[i]; + } + } + + if(numcodes == 0) return 80; /*error: a tree of 0 symbols is not supposed to be made*/ + tree->numcodes = (unsigned)numcodes; /*number of symbols*/ + uivector_resize(&tree->lengths, 0); + if(!uivector_resizev(&tree->lengths, tree->numcodes, 0)) return 9905; + + if(numpresent == 0) /*there are no symbols at all, in that case add one symbol of value 0 to the tree (see RFC 1951 section 3.2.7) */ + { + tree->lengths.data[0] = 1; + return HuffmanTree_makeFromLengths2(tree); + } + else if(numpresent == 1) /*the package merge algorithm gives wrong results if there's only one symbol (theoretically 0 bits would then suffice, but we need a proper symbol for zlib)*/ + { + for(i = 0; i < numcodes; i++) if(frequencies[i]) tree->lengths.data[i] = 1; + return HuffmanTree_makeFromLengths2(tree); + } + + vector_init(&coins, sizeof(Coin)); + vector_init(&prev_row, sizeof(Coin)); + + /*Package-Merge algorithm represented by coin collector's problem + For every symbol, maxbitlen coins will be created*/ + + /*first row, lowest denominator*/ + error = HuffmanTree_fillInCoins(&coins, frequencies, tree->numcodes, sum); + if(!error) + { + for(j = 1; j <= maxbitlen && !error; j++) /*each of the remaining rows*/ + { + vector_swap(&coins, &prev_row); /*swap instead of copying*/ + if(!vector_resized(&coins, 0, Coin_cleanup)) + { + error = 9906; /*memory allocation failed*/ + break; + } + + for(i = 0; i + 1 < prev_row.size; i += 2) + { + if(!vector_resize(&coins, coins.size + 1)) + { + error = 9907; /*memory allocation failed*/ + break; + } + Coin_init((Coin*)vector_get(&coins, coins.size - 1)); + Coin_copy((Coin*)vector_get(&coins, coins.size - 1), (Coin*)vector_get(&prev_row, i)); + addCoins((Coin*)vector_get(&coins, coins.size - 1), (Coin*)vector_get(&prev_row, i + 1)); /*merge the coins into packages*/ + } + if(j < maxbitlen) + { + error = HuffmanTree_fillInCoins(&coins, frequencies, tree->numcodes, sum); + } + } + } + + if(!error) + { + /*keep the coins with lowest weight, so that they add up to the amount of symbols - 1*/ + vector_resized(&coins, numpresent - 1, Coin_cleanup); + + /*calculate the lenghts of each symbol, as the amount of times a coin of each symbol is used*/ + for(i = 0; i < coins.size; i++) + { + Coin* coin = (Coin*)vector_get(&coins, i); + for(j = 0; j < coin->symbols.size; j++) tree->lengths.data[coin->symbols.data[j]]++; + } + + error = HuffmanTree_makeFromLengths2(tree); + } + + vector_cleanupd(&coins, Coin_cleanup); + vector_cleanupd(&prev_row, Coin_cleanup); + + return error; +} + +static unsigned HuffmanTree_getCode(const HuffmanTree* tree, unsigned index) +{ + return tree->tree1d.data[index]; +} + +static unsigned HuffmanTree_getLength(const HuffmanTree* tree, unsigned index) +{ + return tree->lengths.data[index]; +} +#endif /*LODEPNG_COMPILE_ENCODER*/ + +/*get the tree of a deflated block with fixed tree, as specified in the deflate specification*/ +static unsigned generateFixedTree(HuffmanTree* tree) +{ + unsigned i, error = 0; + uivector bitlen; + uivector_init(&bitlen); + if(!uivector_resize(&bitlen, NUM_DEFLATE_CODE_SYMBOLS)) error = 9909; + + if(!error) + { + /*288 possible codes: 0-255=literals, 256=endcode, 257-285=lengthcodes, 286-287=unused*/ + for(i = 0; i <= 143; i++) bitlen.data[i] = 8; + for(i = 144; i <= 255; i++) bitlen.data[i] = 9; + for(i = 256; i <= 279; i++) bitlen.data[i] = 7; + for(i = 280; i <= 287; i++) bitlen.data[i] = 8; + + error = HuffmanTree_makeFromLengths(tree, bitlen.data, NUM_DEFLATE_CODE_SYMBOLS, 15); + } + + uivector_cleanup(&bitlen); + return error; +} + +static unsigned generateDistanceTree(HuffmanTree* tree) +{ + unsigned i, error = 0; + uivector bitlen; + uivector_init(&bitlen); + if(!uivector_resize(&bitlen, NUM_DISTANCE_SYMBOLS)) error = 9910; + + /*there are 32 distance codes, but 30-31 are unused*/ + if(!error) + { + for(i = 0; i < NUM_DISTANCE_SYMBOLS; i++) bitlen.data[i] = 5; + error = HuffmanTree_makeFromLengths(tree, bitlen.data, NUM_DISTANCE_SYMBOLS, 15); + } + uivector_cleanup(&bitlen); + return error; +} + +#ifdef LODEPNG_COMPILE_DECODER + +/* +returns the code, or (unsigned)(-1) if error happened +inbitlength is the length of the complete buffer, in bits (so its byte length times 8) +*/ +static unsigned huffmanDecodeSymbol(const unsigned char* in, size_t* bp, + const HuffmanTree* codetree, size_t inbitlength) +{ + unsigned treepos = 0, ct; + for(;;) + { + if(*bp > inbitlength) return (unsigned)(-1); /*error: end of input memory reached without endcode*/ + + /* + decode the symbol from the tree + the "readBitFromStream" code is inlined in the expression below because this is the biggest bottleneck while decoding + */ + ct = codetree->tree2d.data[(treepos << 1) + READBIT(*bp, in)]; + (*bp)++; + if(ct < codetree->numcodes) return ct; /*the symbol is decoded, return it*/ + else treepos = ct - codetree->numcodes; /*symbol not yet decoded, instead move tree position*/ + + if(treepos >= codetree->numcodes) return (unsigned)(-1); /*error: it appeared outside the codetree*/ + } +} +#endif /*LODEPNG_COMPILE_DECODER*/ + +#ifdef LODEPNG_COMPILE_DECODER + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Inflator / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/*get the tree of a deflated block with fixed tree, as specified in the deflate specification*/ +static void getTreeInflateFixed(HuffmanTree* tree, HuffmanTree* treeD) +{ + /*error checking not done, this is fixed stuff, it works, it doesn't depend on the image*/ + generateFixedTree(tree); + generateDistanceTree(treeD); +} + +/*get the tree of a deflated block with dynamic tree, the tree itself is also Huffman compressed with a known tree*/ +static unsigned getTreeInflateDynamic(HuffmanTree* codetree, HuffmanTree* codetreeD, HuffmanTree* codelengthcodetree, + const unsigned char* in, size_t* bp, size_t inlength) +{ + /*make sure that length values that aren't filled in will be 0, or a wrong tree will be generated*/ + /*C-code note: use no "return" between ctor and dtor of an uivector!*/ + unsigned error = 0; + unsigned n, HLIT, HDIST, HCLEN, i; + uivector bitlen; + uivector bitlenD; + uivector codelengthcode; + size_t inbitlength = inlength * 8; + + if((*bp) >> 3 >= inlength - 2) return 49; /*the bit pointer is or will go past the memory*/ + + HLIT = readBitsFromStream(bp, in, 5) + 257; /*number of literal/length codes + 257. Unlike the spec, the value 257 is added to it here already*/ + HDIST = readBitsFromStream(bp, in, 5) + 1; /*number of distance codes. Unlike the spec, the value 1 is added to it here already*/ + HCLEN = readBitsFromStream(bp, in, 4) + 4; /*number of code length codes. Unlike the spec, the value 4 is added to it here already*/ + + /*read the code length codes out of 3 * (amount of code length codes) bits*/ + uivector_init(&codelengthcode); + if(!uivector_resize(&codelengthcode, NUM_CODE_LENGTH_CODES)) error = 9911; + + if(!error) + { + for(i = 0; i < NUM_CODE_LENGTH_CODES; i++) + { + if(i < HCLEN) codelengthcode.data[CLCL[i]] = readBitsFromStream(bp, in, 3); + else codelengthcode.data[CLCL[i]] = 0; /*if not, it must stay 0*/ + } + + error = HuffmanTree_makeFromLengths(codelengthcodetree, codelengthcode.data, codelengthcode.size, 7); + } + + uivector_cleanup(&codelengthcode); + if(error) return error; + + /*now we can use this tree to read the lengths for the tree that this function will return*/ + uivector_init(&bitlen); + uivector_resizev(&bitlen, NUM_DEFLATE_CODE_SYMBOLS, 0); + uivector_init(&bitlenD); + uivector_resizev(&bitlenD, NUM_DISTANCE_SYMBOLS, 0); + i = 0; + if(!bitlen.data || !bitlenD.data) + { + error = 9912; /*memory allocation failed*/ + } + else while(i < HLIT + HDIST) /*i is the current symbol we're reading in the part that contains the code lengths of lit/len codes and dist codes*/ + { + unsigned code = huffmanDecodeSymbol(in, bp, codelengthcodetree, inbitlength); + if(code <= 15) /*a length code*/ + { + if(i < HLIT) bitlen.data[i] = code; + else bitlenD.data[i - HLIT] = code; + i++; + } + else if(code == 16) /*repeat previous*/ + { + unsigned replength = 3; /*read in the 2 bits that indicate repeat length (3-6)*/ + unsigned value; /*set value to the previous code*/ + + if((*bp) >> 3 >= inlength) + { + error = 50; /*error, bit pointer jumps past memory*/ + break; + } + + replength += readBitsFromStream(bp, in, 2); + + if((i - 1) < HLIT) value = bitlen.data[i - 1]; + else value = bitlenD.data[i - HLIT - 1]; + /*repeat this value in the next lengths*/ + for(n = 0; n < replength; n++) + { + if(i >= HLIT + HDIST) + { + error = 13; /*error: i is larger than the amount of codes*/ + break; + } + if(i < HLIT) bitlen.data[i] = value; + else bitlenD.data[i - HLIT] = value; + i++; + } + } + else if(code == 17) /*repeat "0" 3-10 times*/ + { + unsigned replength = 3; /*read in the bits that indicate repeat length*/ + if((*bp) >> 3 >= inlength) + { + error = 50; /*error, bit pointer jumps past memory*/ + break; + } + + replength += readBitsFromStream(bp, in, 3); + + /*repeat this value in the next lengths*/ + for(n = 0; n < replength; n++) + { + if(i >= HLIT + HDIST) + { + error = 14; /*error: i is larger than the amount of codes*/ + break; + } + if(i < HLIT) bitlen.data[i] = 0; + else bitlenD.data[i - HLIT] = 0; + i++; + } + } + else if(code == 18) /*repeat "0" 11-138 times*/ + { + unsigned replength = 11; /*read in the bits that indicate repeat length*/ + if((*bp) >> 3 >= inlength) + { + error = 50; /*error, bit pointer jumps past memory*/ + break; + } + replength += readBitsFromStream(bp, in, 7); + + /*repeat this value in the next lengths*/ + for(n = 0; n < replength; n++) + { + if(i >= HLIT + HDIST) + { + error = 15; /*error: i is larger than the amount of codes*/ + break; + } + if(i < HLIT) bitlen.data[i] = 0; + else bitlenD.data[i - HLIT] = 0; + i++; + } + } + else /*if(code == (unsigned)(-1))*/ /*huffmanDecodeSymbol returns (unsigned)(-1) in case of error*/ + { + if(code == (unsigned)(-1)) + { + error = (*bp) > inlength * 8 ? 10 : 11; /*return error code 10 or 11 depending on the situation that happened in huffmanDecodeSymbol (10=no endcode, 11=wrong jump outside of tree)*/ + } + else error = 16; /*unexisting code, this can never happen*/ + break; + } + } + + if(!error && bitlen.data[256] == 0) error = 64; /*the length of the end code 256 must be larger than 0*/ + + /*now we've finally got HLIT and HDIST, so generate the code trees, and the function is done*/ + if(!error) error = HuffmanTree_makeFromLengths(codetree, &bitlen.data[0], bitlen.size, 15); + if(!error) error = HuffmanTree_makeFromLengths(codetreeD, &bitlenD.data[0], bitlenD.size, 15); + + uivector_cleanup(&bitlen); + uivector_cleanup(&bitlenD); + + return error; +} + +/*inflate a block with dynamic of fixed Huffman tree*/ +static unsigned inflateHuffmanBlock(ucvector* out, const unsigned char* in, size_t* bp, size_t* pos, size_t inlength, unsigned btype) +{ + unsigned error = 0; + HuffmanTree codetree; /*287, the code tree for Huffman codes*/ + HuffmanTree codetreeD; /*31, the code tree for distance codes*/ + size_t inbitlength = inlength * 8; + + HuffmanTree_init(&codetree); + HuffmanTree_init(&codetreeD); + + if(btype == 1) getTreeInflateFixed(&codetree, &codetreeD); + else if(btype == 2) + { + HuffmanTree codelengthcodetree; /*18, the code tree for code length codes*/ + HuffmanTree_init(&codelengthcodetree); + error = getTreeInflateDynamic(&codetree, &codetreeD, &codelengthcodetree, in, bp, inlength); + HuffmanTree_cleanup(&codelengthcodetree); + } + + for(;;) + { + unsigned code = huffmanDecodeSymbol(in, bp, &codetree, inbitlength); + if(code <= 255) /*literal symbol*/ + { + if((*pos) >= out->size) + { + if(!ucvector_resize(out, ((*pos) + 1) * 2)) /*reserve more room at once*/ + { + error = 9913; /*memory allocation failed*/ + break; + } + } + out->data[(*pos)] = (unsigned char)(code); + (*pos)++; + } + else if(code >= FIRST_LENGTH_CODE_INDEX && code <= LAST_LENGTH_CODE_INDEX) /*length code*/ + { + /*part 1: get length base*/ + size_t length = LENGTHBASE[code - FIRST_LENGTH_CODE_INDEX]; + unsigned codeD, distance, numextrabitsD; + size_t start, forward, backward, numextrabits; + + /*part 2: get extra bits and add the value of that to length*/ + numextrabits = LENGTHEXTRA[code - FIRST_LENGTH_CODE_INDEX]; + if(((*bp) >> 3) >= inlength) + { + error = 51; /*error, bit pointer will jump past memory*/ + break; + } + length += readBitsFromStream(bp, in, numextrabits); + + /*part 3: get distance code*/ + codeD = huffmanDecodeSymbol(in, bp, &codetreeD, inbitlength); + if(codeD > 29) + { + if(code == (unsigned)(-1)) /*huffmanDecodeSymbol returns (unsigned)(-1) in case of error*/ + { + error = (*bp) > inlength * 8 ? 10 : 11; /*return error code 10 or 11 depending on the situation that happened in huffmanDecodeSymbol (10=no endcode, 11=wrong jump outside of tree)*/ + } + else error = 18; /*error: invalid distance code (30-31 are never used)*/ + break; + } + distance = DISTANCEBASE[codeD]; + + /*part 4: get extra bits from distance*/ + numextrabitsD = DISTANCEEXTRA[codeD]; + if(((*bp) >> 3) >= inlength) + { + error = 51; /*error, bit pointer will jump past memory*/ + break; + } + distance += readBitsFromStream(bp, in, numextrabitsD); + + /*part 5: fill in all the out[n] values based on the length and dist*/ + start = (*pos); + backward = start - distance; + if((*pos) + length >= out->size) + { + if(!ucvector_resize(out, ((*pos) + length) * 2)) /*reserve more room at once*/ + { + error = 9914; /*memory allocation failed*/ + break; + } + } + + for(forward = 0; forward < length; forward++) + { + out->data[(*pos)] = out->data[backward]; + (*pos)++; + backward++; + if(backward >= start) backward = start - distance; + } + } + else if(code == 256) break; /*end code, break the loop*/ + else /*if(code == (unsigned)(-1))*/ /*huffmanDecodeSymbol returns (unsigned)(-1) in case of error*/ + { + error = (*bp) > inlength * 8 ? 10 : 11; /*return error code 10 or 11 depending on the situation that happened in huffmanDecodeSymbol (10=no endcode, 11=wrong jump outside of tree)*/ + break; + } + } + + HuffmanTree_cleanup(&codetree); + HuffmanTree_cleanup(&codetreeD); + + return error; +} + +static unsigned inflateNoCompression(ucvector* out, const unsigned char* in, size_t* bp, size_t* pos, size_t inlength) +{ + /*go to first boundary of byte*/ + size_t p; + unsigned LEN, NLEN, n, error = 0; + while(((*bp) & 0x7) != 0) (*bp)++; + p = (*bp) / 8; /*byte position*/ + + /*read LEN (2 bytes) and NLEN (2 bytes)*/ + if(p >= inlength - 4) return 52; /*error, bit pointer will jump past memory*/ + LEN = in[p] + 256 * in[p + 1]; p += 2; + NLEN = in[p] + 256 * in[p + 1]; p += 2; + + /*check if 16-bit NLEN is really the one's complement of LEN*/ + if(LEN + NLEN != 65535) return 21; /*error: NLEN is not one's complement of LEN*/ + + if((*pos) + LEN >= out->size) + { + if(!ucvector_resize(out, (*pos) + LEN)) return 9915; + } + + /*read the literal data: LEN bytes are now stored in the out buffer*/ + if(p + LEN > inlength) return 23; /*error: reading outside of in buffer*/ + for(n = 0; n < LEN; n++) out->data[(*pos)++] = in[p++]; + + (*bp) = p * 8; + + return error; +} + +/*inflate the deflated data (cfr. deflate spec); return value is the error*/ +unsigned LodeFlate_inflate(ucvector* out, const unsigned char* in, size_t insize, size_t inpos) +{ + size_t bp = 0; /*bit pointer in the "in" data, current byte is bp >> 3, current bit is bp & 0x7 (from lsb to msb of the byte)*/ + unsigned BFINAL = 0; + size_t pos = 0; /*byte position in the out buffer*/ + + unsigned error = 0; + + while(!BFINAL) + { + unsigned BTYPE; + if(bp + 2 >= insize * 8) return 52; /*error, bit pointer will jump past memory*/ + BFINAL = readBitFromStream(&bp, &in[inpos]); + BTYPE = 1 * readBitFromStream(&bp, &in[inpos]); + BTYPE += 2 * readBitFromStream(&bp, &in[inpos]); + + if(BTYPE == 3) return 20; /*error: invalid BTYPE*/ + else if(BTYPE == 0) error = inflateNoCompression(out, &in[inpos], &bp, &pos, insize); /*no compression*/ + else error = inflateHuffmanBlock(out, &in[inpos], &bp, &pos, insize, BTYPE); /*compression, BTYPE 01 or 10*/ + + if(error) return error; + } + + if(!ucvector_resize(out, pos)) error = 9916; /*Only now we know the true size of out, resize it to that*/ + + return error; +} + +#endif /*LODEPNG_COMPILE_DECODER*/ + +#ifdef LODEPNG_COMPILE_ENCODER + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Deflator / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +static const size_t MAX_SUPPORTED_DEFLATE_LENGTH = 258; + +/*bitlen is the size in bits of the code*/ +static void addHuffmanSymbol(size_t* bp, ucvector* compressed, unsigned code, unsigned bitlen) +{ + addBitsToStreamReversed(bp, compressed, code, bitlen); +} + +/*search the index in the array, that has the largest value smaller than or equal to the given value, given array must be sorted (if no value is smaller, it returns the size of the given array)*/ +static size_t searchCodeIndex(const unsigned* array, size_t array_size, size_t value) +{ + /*linear search implementation*/ + /*for(size_t i = 1; i < array_size; i++) if(array[i] > value) return i - 1; + return array_size - 1;*/ + + /*binary search implementation (not that much faster) (precondition: array_size > 0)*/ + size_t left = 1; + size_t right = array_size - 1; + while(left <= right) + { + size_t mid = (left + right) / 2; + if(array[mid] <= value) left = mid + 1; /*the value to find is more to the right*/ + else if(array[mid - 1] > value) right = mid - 1; /*the value to find is more to the left*/ + else return mid - 1; + } + return array_size - 1; +} + +static void addLengthDistance(uivector* values, size_t length, size_t distance) +{ + /*values in encoded vector are those used by deflate: + 0-255: literal bytes + 256: end + 257-285: length/distance pair (length code, followed by extra length bits, distance code, extra distance bits) + 286-287: invalid*/ + + unsigned length_code = (unsigned)searchCodeIndex(LENGTHBASE, 29, length); + unsigned extra_length = (unsigned)(length - LENGTHBASE[length_code]); + unsigned dist_code = (unsigned)searchCodeIndex(DISTANCEBASE, 30, distance); + unsigned extra_distance = (unsigned)(distance - DISTANCEBASE[dist_code]); + + uivector_push_back(values, length_code + FIRST_LENGTH_CODE_INDEX); + uivector_push_back(values, extra_length); + uivector_push_back(values, dist_code); + uivector_push_back(values, extra_distance); +} + +#if 0 +/*the "brute force" version of the encodeLZ7 algorithm, not used anymore, kept here for reference*/ +static void encodeLZ77_brute(uivector* out, const unsigned char* in, size_t insize, unsigned windowSize) +{ + size_t pos; + /*using pointer instead of vector for input makes it faster when NOT using optimization when compiling; no influence if optimization is used*/ + for(pos = 0; pos < insize; pos++) + { + size_t length = 0, offset = 0; /*the length and offset found for the current position*/ + size_t max_offset = pos < windowSize ? pos : windowSize; /*how far back to test*/ + size_t current_offset; + + /**search for the longest string**/ + for(current_offset = 1; current_offset < max_offset; current_offset++) /*search backwards through all possible distances (=offsets)*/ + { + size_t backpos = pos - current_offset; + if(in[backpos] == in[pos]) + { + /*test the next characters*/ + size_t current_length = 1; + size_t backtest = backpos + 1; + size_t foretest = pos + 1; + while(foretest < insize && in[backtest] == in[foretest] && current_length < MAX_SUPPORTED_DEFLATE_LENGTH) /*maximum supporte length by deflate is max length*/ + { + if(backpos >= pos) backpos -= current_offset; /*continue as if we work on the decoded bytes after pos by jumping back before pos*/ + current_length++; + backtest++; + foretest++; + } + if(current_length > length) + { + length = current_length; /*the longest length*/ + offset = current_offset; /*the offset that is related to this longest length*/ + if(current_length == MAX_SUPPORTED_DEFLATE_LENGTH) break; /*you can jump out of this for loop once a length of max length is found (gives significant speed gain)*/ + } + } + } + + /**encode it as length/distance pair or literal value**/ + if(length < 3) /*only lengths of 3 or higher are supported as length/distance pair*/ + { + uivector_push_back(out, in[pos]); + } + else + { + addLengthDistance(out, length, offset); + pos += (length - 1); + } + } /*end of the loop through each character of input*/ +} +#endif + +static const unsigned HASH_NUM_VALUES = 65536; +static const unsigned HASH_NUM_CHARACTERS = 6; +static const unsigned HASH_SHIFT = 2; +/* +Good and fast values: HASH_NUM_VALUES=65536, HASH_NUM_CHARACTERS=6, HASH_SHIFT=2 +making HASH_NUM_CHARACTERS larger (like 8), makes the file size larger but is a bit faster +making HASH_NUM_CHARACTERS smaller (like 3), makes the file size smaller but is slower +*/ + +static unsigned getHash(const unsigned char* data, size_t size, size_t pos) +{ + unsigned result = 0; + size_t amount, i; + if(pos >= size) return 0; + amount = HASH_NUM_CHARACTERS; + if(pos + amount >= size) amount = size - pos; + for(i = 0; i < amount; i++) result ^= (data[pos + i] << (i * HASH_SHIFT)); + return result % HASH_NUM_VALUES; +} + +static unsigned countInitialZeros(const unsigned char* data, size_t size, size_t pos) +{ + size_t max_count = MAX_SUPPORTED_DEFLATE_LENGTH; + size_t i; + if(max_count > size - pos) max_count = size - pos; + for(i = 0; i < max_count; i++) + { + if(data[pos + i] != 0) + return i; + } + return max_count; +} + +/*LZ77-encode the data using a hash table technique to let it encode faster. Return value is error code*/ +static unsigned encodeLZ77(uivector* out, const unsigned char* in, size_t insize, unsigned windowSize) +{ + /**generate hash table**/ + vector table; /*HASH_NUM_VALUES uivectors; this represents what would be an std::vector > in C++*/ + uivector tablepos1, tablepos2; + uivector initialZerosTable; /*hash == 0 indicates a possible common case of a long sequence of zeros, store and use the amount here for a speedup*/ + unsigned pos, i, error = 0; + + vector_init(&table, sizeof(uivector)); + if(!vector_resize(&table, HASH_NUM_VALUES)) return 9917; + for(i = 0; i < HASH_NUM_VALUES; i++) + { + uivector* v = (uivector*)vector_get(&table, i); + uivector_init(v); + } + + /*remember start and end positions in the tables to search in*/ + uivector_init(&tablepos1); + uivector_init(&tablepos2); + uivector_init(&initialZerosTable); + + if(!uivector_resizev(&tablepos1, HASH_NUM_VALUES, 0)) error = 9918; + if(!uivector_resizev(&tablepos2, HASH_NUM_VALUES, 0)) error = 9919; + + if(!error) + { + unsigned length, offset, tablepos, max_offset; + unsigned hash, initialZeros; + unsigned backpos, current_offset, t1, t2, skip, current_length; + const unsigned char *lastptr, *foreptr, *backptr; + + for(pos = 0; pos < insize; pos++) + { + length = 0, offset = 0; /*the length and offset found for the current position*/ + max_offset = pos < windowSize ? pos : windowSize; /*how far back to test*/ + + /*/search for the longest string*/ + /*first find out where in the table to start (the first value that is in the range from "pos - max_offset" to "pos")*/ + hash = getHash(in, insize, pos); + initialZeros = countInitialZeros(in, insize, pos); + if(!uivector_push_back((uivector*)vector_get(&table, hash), pos)) + { + error = 9920; /*memory allocation failed*/ + break; + } + if(hash == 0 && !uivector_push_back(&initialZerosTable, initialZeros)) + { + error = 9920; /*memory allocation failed*/ + break; + } + + while(((uivector*)vector_get(&table, hash))->data[tablepos1.data[hash]] < pos - max_offset) + { + tablepos1.data[hash]++; /*it now points to the first value in the table for which the index is larger than or equal to pos - max_offset*/ + } + while(((uivector*)vector_get(&table, hash))->data[tablepos2.data[hash]] < pos) + { + tablepos2.data[hash]++; /*it now points to the first value in the table for which the index is larger than or equal to pos*/ + } + + t1 = tablepos1.data[hash]; + t2 = tablepos2.data[hash]; + + lastptr = &in[insize < pos + MAX_SUPPORTED_DEFLATE_LENGTH ? insize : pos + MAX_SUPPORTED_DEFLATE_LENGTH]; + + for(tablepos = tablepos2.data[hash] - 1; tablepos >= t1 && tablepos < t2; tablepos--) + { + backpos = ((uivector*)vector_get(&table, hash))->data[tablepos]; + current_offset = pos - backpos; + + /*test the next characters*/ + foreptr = &in[pos]; + backptr = &in[backpos]; + + if(hash == 0) + { + skip = initialZerosTable.data[tablepos]; + if(skip > initialZeros) skip = initialZeros; + if(skip > insize - pos) skip = insize - pos; + backptr += skip; + foreptr += skip; + } + while(foreptr != lastptr && *backptr == *foreptr) /*maximum supported length by deflate is max length*/ + { + ++backptr; + ++foreptr; + } + current_length = (unsigned)(foreptr - &in[pos]); + if(current_length > length) + { + length = current_length; /*the longest length*/ + offset = current_offset; /*the offset that is related to this longest length*/ + if(current_length == MAX_SUPPORTED_DEFLATE_LENGTH) break; /*you can jump out of this for loop once a length of max length is found (gives significant speed gain)*/ + } + } + + /**encode it as length/distance pair or literal value**/ + if(length < 3) /*only lengths of 3 or higher are supported as length/distance pair*/ + { + if(!uivector_push_back(out, in[pos])) + { + error = 9921; /*memory allocation failed*/ + break; + } + } + else + { + unsigned j, local_hash; + addLengthDistance(out, length, offset); + for(j = 0; j < length - 1; j++) + { + pos++; + local_hash = getHash(in, insize, pos); + if(!uivector_push_back((uivector*)vector_get(&table, local_hash), pos)) + { + error = 9922; /*memory allocation failed*/ + break; + } + if(local_hash == 0 && !uivector_push_back(&initialZerosTable, countInitialZeros(in, insize, pos))) + { + error = 9922; /*memory allocation failed*/ + break; + } + } + } + } /*end of the loop through each character of input*/ + } /*end of "if(!error)"*/ + + /*cleanup*/ + for(i = 0; i < table.size; i++) + { + uivector* v = (uivector*)vector_get(&table, i); + uivector_cleanup(v); + } + vector_cleanup(&table); + uivector_cleanup(&tablepos1); + uivector_cleanup(&tablepos2); + uivector_cleanup(&initialZerosTable); + return error; +} + +/* /////////////////////////////////////////////////////////////////////////// */ + +static unsigned deflateNoCompression(ucvector* out, const unsigned char* data, size_t datasize) +{ + /*non compressed deflate block data: 1 bit BFINAL,2 bits BTYPE,(5 bits): it jumps to start of next byte, 2 bytes LEN, 2 bytes NLEN, LEN bytes literal DATA*/ + + size_t i, j, numdeflateblocks = datasize / 65536 + 1; + unsigned datapos = 0; + for(i = 0; i < numdeflateblocks; i++) + { + unsigned BFINAL, BTYPE, LEN, NLEN; + unsigned char firstbyte; + + BFINAL = (i == numdeflateblocks - 1); + BTYPE = 0; + + firstbyte = (unsigned char)(BFINAL + ((BTYPE & 1) << 1) + ((BTYPE & 2) << 1)); + ucvector_push_back(out, firstbyte); + + LEN = 65535; + if(datasize - datapos < 65535) LEN = (unsigned)datasize - datapos; + NLEN = 65535 - LEN; + + ucvector_push_back(out, (unsigned char)(LEN % 256)); + ucvector_push_back(out, (unsigned char)(LEN / 256)); + ucvector_push_back(out, (unsigned char)(NLEN % 256)); + ucvector_push_back(out, (unsigned char)(NLEN / 256)); + + /*Decompressed data*/ + for(j = 0; j < 65535 && datapos < datasize; j++) + { + ucvector_push_back(out, data[datapos++]); + } + } + + return 0; +} + +/*write the encoded data, using lit/len as well as distance codes*/ +static void writeLZ77data(size_t* bp, ucvector* out, const uivector* lz77_encoded, const HuffmanTree* codes, const HuffmanTree* codesD) +{ + size_t i = 0; + for(i = 0; i < lz77_encoded->size; i++) + { + unsigned val = lz77_encoded->data[i]; + addHuffmanSymbol(bp, out, HuffmanTree_getCode(codes, val), HuffmanTree_getLength(codes, val)); + if(val > 256) /*for a length code, 3 more things have to be added*/ + { + unsigned length_index = val - FIRST_LENGTH_CODE_INDEX; + unsigned n_length_extra_bits = LENGTHEXTRA[length_index]; + unsigned length_extra_bits = lz77_encoded->data[++i]; + + unsigned distance_code = lz77_encoded->data[++i]; + + unsigned distance_index = distance_code; + unsigned n_distance_extra_bits = DISTANCEEXTRA[distance_index]; + unsigned distance_extra_bits = lz77_encoded->data[++i]; + + addBitsToStream(bp, out, length_extra_bits, n_length_extra_bits); + addHuffmanSymbol(bp, out, HuffmanTree_getCode(codesD, distance_code), HuffmanTree_getLength(codesD, distance_code)); + addBitsToStream(bp, out, distance_extra_bits, n_distance_extra_bits); + } + } +} + +static unsigned deflateDynamic(ucvector* out, const unsigned char* data, size_t datasize, const LodeZlib_CompressSettings* settings) +{ + /* + after the BFINAL and BTYPE, the dynamic block consists out of the following: + - 5 bits HLIT, 5 bits HDIST, 4 bits HCLEN + - (HCLEN+4)*3 bits code lengths of code length alphabet + - HLIT + 257 code lenghts of lit/length alphabet (encoded using the code length alphabet, + possible repetition codes 16, 17, 18) + - HDIST + 1 code lengths of distance alphabet (encoded using the code length alphabet, + possible repetition codes 16, 17, 18) + - compressed data + - 256 (end code) + */ + + unsigned error = 0; + + uivector lz77_encoded; + HuffmanTree codes; /*tree for literal values and length codes*/ + HuffmanTree codesD; /*tree for distance codes*/ + HuffmanTree codelengthcodes; + uivector frequencies; + uivector frequenciesD; + uivector amounts; /*the amounts in the "normal" order*/ + uivector lldl; + uivector lldll; /*lit/len & dist code lenghts*/ + uivector clcls; + + unsigned BFINAL = 1; /*make only one block... the first and final one*/ + size_t numcodes, numcodesD, i; + size_t bp = 0; /*the bit pointer*/ + unsigned HLIT, HDIST, HCLEN; + + uivector_init(&lz77_encoded); + HuffmanTree_init(&codes); + HuffmanTree_init(&codesD); + HuffmanTree_init(&codelengthcodes); + uivector_init(&frequencies); + uivector_init(&frequenciesD); + uivector_init(&amounts); + uivector_init(&lldl); + uivector_init(&lldll); + uivector_init(&clcls); + + while(!error) /*the goto-avoiding while construct: break out to go to the cleanup phase, a break at the end makes sure the while is never repeated*/ + { + if(settings->useLZ77) + { + error = encodeLZ77(&lz77_encoded, data, datasize, settings->windowSize); /*LZ77 encoded*/ + if(error) break; + } + else + { + if(!uivector_resize(&lz77_encoded, datasize)) + { + error = 9923; /*memory allocation failed*/ + break; + } + for(i = 0; i < datasize; i++) lz77_encoded.data[i] = data[i]; /*no LZ77, but still will be Huffman compressed*/ + } + + if(!uivector_resizev(&frequencies, 286, 0)) + { + error = 9924; /*memory allocation failed*/ + break; + } + if(!uivector_resizev(&frequenciesD, 30, 0)) + { + error = 9925; /*memory allocation failed*/ + break; + } + for(i = 0; i < lz77_encoded.size; i++) + { + unsigned symbol = lz77_encoded.data[i]; + frequencies.data[symbol]++; + if(symbol > 256) + { + unsigned dist = lz77_encoded.data[i + 2]; + frequenciesD.data[dist]++; + i += 3; + } + } + frequencies.data[256] = 1; /*there will be exactly 1 end code, at the end of the block*/ + + error = HuffmanTree_makeFromFrequencies(&codes, frequencies.data, frequencies.size, 15); + if(error) break; + error = HuffmanTree_makeFromFrequencies(&codesD, frequenciesD.data, frequenciesD.size, 15); + if(error) break; + + addBitToStream(&bp, out, BFINAL); + addBitToStream(&bp, out, 0); /*first bit of BTYPE "dynamic"*/ + addBitToStream(&bp, out, 1); /*second bit of BTYPE "dynamic"*/ + + numcodes = codes.numcodes; if(numcodes > 286) numcodes = 286; + numcodesD = codesD.numcodes; if(numcodesD > 30) numcodesD = 30; + for(i = 0; i < numcodes; i++) uivector_push_back(&lldll, HuffmanTree_getLength(&codes, (unsigned)i)); + for(i = 0; i < numcodesD; i++) uivector_push_back(&lldll, HuffmanTree_getLength(&codesD, (unsigned)i)); + + /*make lldl smaller by using repeat codes 16 (copy length 3-6 times), 17 (3-10 zeroes), 18 (11-138 zeroes)*/ + for(i = 0; i < (unsigned)lldll.size; i++) + { + unsigned j = 0; + while(i + j + 1 < (unsigned)lldll.size && lldll.data[i + j + 1] == lldll.data[i]) j++; + + if(lldll.data[i] == 0 && j >= 2) + { + j++; /*include the first zero*/ + if(j <= 10) + { + uivector_push_back(&lldl, 17); + uivector_push_back(&lldl, j - 3); + } + else + { + if(j > 138) j = 138; + uivector_push_back(&lldl, 18); + uivector_push_back(&lldl, j - 11); + } + i += (j - 1); + } + else if(j >= 3) + { + size_t k; + unsigned num = j / 6, rest = j % 6; + uivector_push_back(&lldl, lldll.data[i]); + for(k = 0; k < num; k++) + { + uivector_push_back(&lldl, 16); + uivector_push_back(&lldl, 6 - 3); + } + if(rest >= 3) + { + uivector_push_back(&lldl, 16); + uivector_push_back(&lldl, rest - 3); + } + else j -= rest; + i += j; + } + else uivector_push_back(&lldl, lldll.data[i]); + } + + /*generate huffmantree for the length codes of lit/len and dist codes*/ + if(!uivector_resizev(&amounts, 19, 0)) /*16 possible lengths (0-15) and 3 repeat codes (16, 17 and 18)*/ + { + error = 9926; /*memory allocation failed*/ + break; + } + for(i = 0; i < lldl.size; i++) + { + amounts.data[lldl.data[i]]++; + if(lldl.data[i] >= 16) i++; /*after a repeat code come the bits that specify the amount, those don't need to be in the amounts calculation*/ + } + + error = HuffmanTree_makeFromFrequencies(&codelengthcodes, amounts.data, amounts.size, 7); + if(error) break; + + if(!uivector_resize(&clcls, 19)) + { + error = 9927; /*memory allocation failed*/ + break; + } + for(i = 0; i < 19; i++) clcls.data[i] = HuffmanTree_getLength(&codelengthcodes, CLCL[i]); /*lenghts of code length tree is in the order as specified by deflate*/ + while(clcls.data[clcls.size - 1] == 0 && clcls.size > 4) + { + if(!uivector_resize(&clcls, clcls.size - 1)) /*remove zeros at the end, but minimum size must be 4*/ + { + error = 9928; /*memory allocation failed*/ + break; + } + } + if(error) break; + + /*write the HLIT, HDIST and HCLEN values*/ + HLIT = (unsigned)(numcodes - 257); + HDIST = (unsigned)(numcodesD - 1); + HCLEN = (unsigned)clcls.size - 4; + addBitsToStream(&bp, out, HLIT, 5); + addBitsToStream(&bp, out, HDIST, 5); + addBitsToStream(&bp, out, HCLEN, 4); + + /*write the code lenghts of the code length alphabet*/ + for(i = 0; i < HCLEN + 4; i++) addBitsToStream(&bp, out, clcls.data[i], 3); + + /*write the lenghts of the lit/len AND the dist alphabet*/ + for(i = 0; i < lldl.size; i++) + { + addHuffmanSymbol(&bp, out, HuffmanTree_getCode(&codelengthcodes, lldl.data[i]), HuffmanTree_getLength(&codelengthcodes, lldl.data[i])); + /*extra bits of repeat codes*/ + if(lldl.data[i] == 16) addBitsToStream(&bp, out, lldl.data[++i], 2); + else if(lldl.data[i] == 17) addBitsToStream(&bp, out, lldl.data[++i], 3); + else if(lldl.data[i] == 18) addBitsToStream(&bp, out, lldl.data[++i], 7); + } + + /*write the compressed data symbols*/ + writeLZ77data(&bp, out, &lz77_encoded, &codes, &codesD); + if(HuffmanTree_getLength(&codes, 256) == 0) + { + error = 64; /*the length of the end code 256 must be larger than 0*/ + break; + } + addHuffmanSymbol(&bp, out, HuffmanTree_getCode(&codes, 256), HuffmanTree_getLength(&codes, 256)); /*end code*/ + + break; /*end of error-while*/ + } + + /*cleanup*/ + uivector_cleanup(&lz77_encoded); + HuffmanTree_cleanup(&codes); + HuffmanTree_cleanup(&codesD); + HuffmanTree_cleanup(&codelengthcodes); + uivector_cleanup(&frequencies); + uivector_cleanup(&frequenciesD); + uivector_cleanup(&amounts); + uivector_cleanup(&lldl); + uivector_cleanup(&lldll); + uivector_cleanup(&clcls); + + return error; +} + +static unsigned deflateFixed(ucvector* out, const unsigned char* data, size_t datasize, const LodeZlib_CompressSettings* settings) +{ + HuffmanTree codes; /*tree for literal values and length codes*/ + HuffmanTree codesD; /*tree for distance codes*/ + + unsigned BFINAL = 1; /*make only one block... the first and final one*/ + unsigned error = 0; + size_t i, bp = 0; /*the bit pointer*/ + + HuffmanTree_init(&codes); + HuffmanTree_init(&codesD); + + generateFixedTree(&codes); + generateDistanceTree(&codesD); + + addBitToStream(&bp, out, BFINAL); + addBitToStream(&bp, out, 1); /*first bit of BTYPE*/ + addBitToStream(&bp, out, 0); /*second bit of BTYPE*/ + + if(settings->useLZ77) /*LZ77 encoded*/ + { + uivector lz77_encoded; + uivector_init(&lz77_encoded); + error = encodeLZ77(&lz77_encoded, data, datasize, settings->windowSize); + if(!error) writeLZ77data(&bp, out, &lz77_encoded, &codes, &codesD); + uivector_cleanup(&lz77_encoded); + } + else /*no LZ77, but still will be Huffman compressed*/ + { + for(i = 0; i < datasize; i++) + { + addHuffmanSymbol(&bp, out, HuffmanTree_getCode(&codes, data[i]), HuffmanTree_getLength(&codes, data[i])); + } + } + if(!error) addHuffmanSymbol(&bp, out, HuffmanTree_getCode(&codes, 256), HuffmanTree_getLength(&codes, 256)); /*"end" code*/ + + /*cleanup*/ + HuffmanTree_cleanup(&codes); + HuffmanTree_cleanup(&codesD); + + return error; +} + +unsigned LodeFlate_deflate(ucvector* out, const unsigned char* data, size_t datasize, const LodeZlib_CompressSettings* settings) +{ + unsigned error = 0; + if(settings->btype == 0) error = deflateNoCompression(out, data, datasize); + else if(settings->btype == 1) error = deflateFixed(out, data, datasize, settings); + else if(settings->btype == 2) error = deflateDynamic(out, data, datasize, settings); + else error = 61; + return error; +} + +#endif /*LODEPNG_COMPILE_DECODER*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Adler32 */ +/* ////////////////////////////////////////////////////////////////////////// */ + +static unsigned update_adler32(unsigned adler, const unsigned char* data, unsigned len) +{ + unsigned s1 = adler & 0xffff; + unsigned s2 = (adler >> 16) & 0xffff; + + while(len > 0) + { + /*at least 5550 sums can be done before the sums overflow, saving us from a lot of module divisions*/ + unsigned amount = len > 5550 ? 5550 : len; + len -= amount; + while(amount > 0) + { + s1 = (s1 + *data++); + s2 = (s2 + s1); + amount--; + } + s1 %= 65521; + s2 %= 65521; + } + + return (s2 << 16) | s1; +} + +/*Return the adler32 of the bytes data[0..len-1]*/ +static unsigned adler32(const unsigned char* data, unsigned len) +{ + return update_adler32(1L, data, len); +} + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Reading and writing single bits and bytes from/to stream for Zlib / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_ENCODER +void LodeZlib_add32bitInt(ucvector* buffer, unsigned value) +{ + ucvector_push_back(buffer, (unsigned char)((value >> 24) & 0xff)); + ucvector_push_back(buffer, (unsigned char)((value >> 16) & 0xff)); + ucvector_push_back(buffer, (unsigned char)((value >> 8) & 0xff)); + ucvector_push_back(buffer, (unsigned char)((value ) & 0xff)); +} +#endif /*LODEPNG_COMPILE_ENCODER*/ + +unsigned LodeZlib_read32bitInt(const unsigned char* buffer) +{ + return (buffer[0] << 24) | (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]; +} + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Zlib / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_DECODER + +unsigned LodeZlib_decompress(unsigned char** out, size_t* outsize, const unsigned char* in, size_t insize, const LodeZlib_DecompressSettings* settings) +{ + unsigned error = 0; + unsigned CM, CINFO, FDICT; + ucvector outv; + + if(insize < 2) return 53; /*error, size of zlib data too small*/ + /*read information from zlib header*/ + if((in[0] * 256 + in[1]) % 31 != 0) return 24; /*error: 256 * in[0] + in[1] must be a multiple of 31, the FCHECK value is supposed to be made that way*/ + + CM = in[0] & 15; + CINFO = (in[0] >> 4) & 15; + /*FCHECK = in[1] & 31; //FCHECK is already tested above*/ + FDICT = (in[1] >> 5) & 1; + /*FLEVEL = (in[1] >> 6) & 3; //not really important, all it does it to give a compiler warning about unused variable, we don't care what encoding setting the encoder used*/ + + if(CM != 8 || CINFO > 7) return 25; /*error: only compression method 8: inflate with sliding window of 32k is supported by the PNG spec*/ + if(FDICT != 0) return 26; /*error: the specification of PNG says about the zlib stream: "The additional flags shall not specify a preset dictionary."*/ + + ucvector_init_buffer(&outv, *out, *outsize); /*ucvector-controlled version of the output buffer, for dynamic array*/ + error = LodeFlate_inflate(&outv, in, insize, 2); + *out = outv.data; + *outsize = outv.size; + if(error) return error; + + if(!settings->ignoreAdler32) + { + unsigned ADLER32 = LodeZlib_read32bitInt(&in[insize - 4]); + unsigned checksum = adler32(outv.data, (unsigned)outv.size); + if(checksum != ADLER32) return 58; /*error, adler checksum not correct, data must be corrupted*/ + } + + return 0; /*no error*/ +} + +#endif /*LODEPNG_COMPILE_DECODER*/ + +#ifdef LODEPNG_COMPILE_ENCODER + +unsigned LodeZlib_compress(unsigned char** out, size_t* outsize, const unsigned char* in, size_t insize, const LodeZlib_CompressSettings* settings) +{ + /*initially, *out must be NULL and outsize 0, if you just give some random *out that's pointing to a non allocated buffer, this'll crash*/ + ucvector deflatedata, outv; + size_t i; + unsigned error; + + unsigned ADLER32; + /*zlib data: 1 byte CMF (CM+CINFO), 1 byte FLG, deflate data, 4 byte ADLER32 checksum of the Decompressed data*/ + unsigned CMF = 120; /*0b01111000: CM 8, CINFO 7. With CINFO 7, any window size up to 32768 can be used.*/ + unsigned FLEVEL = 0; + unsigned FDICT = 0; + unsigned CMFFLG = 256 * CMF + FDICT * 32 + FLEVEL * 64; + unsigned FCHECK = 31 - CMFFLG % 31; + CMFFLG += FCHECK; + + ucvector_init_buffer(&outv, *out, *outsize); /*ucvector-controlled version of the output buffer, for dynamic array*/ + + ucvector_push_back(&outv, (unsigned char)(CMFFLG / 256)); + ucvector_push_back(&outv, (unsigned char)(CMFFLG % 256)); + + ucvector_init(&deflatedata); + error = LodeFlate_deflate(&deflatedata, in, insize, settings); + + if(!error) + { + ADLER32 = adler32(in, (unsigned)insize); + for(i = 0; i < deflatedata.size; i++) ucvector_push_back(&outv, deflatedata.data[i]); + ucvector_cleanup(&deflatedata); + LodeZlib_add32bitInt(&outv, ADLER32); + } + + *out = outv.data; + *outsize = outv.size; + + return error; +} + +#endif /*LODEPNG_COMPILE_ENCODER*/ + +#endif /*LODEPNG_COMPILE_ZLIB*/ + +/* ////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_ENCODER + +void LodeZlib_CompressSettings_init(LodeZlib_CompressSettings* settings) +{ + settings->btype = 2; /*compress with dynamic huffman tree (not in the mathematical sense, just not the predefined one)*/ + settings->useLZ77 = 1; + settings->windowSize = 2048; /*this is a good tradeoff between speed and compression ratio*/ +} + +const LodeZlib_CompressSettings LodeZlib_defaultCompressSettings = {2, 1, 2048}; + +#endif /*LODEPNG_COMPILE_ENCODER*/ + +#ifdef LODEPNG_COMPILE_DECODER + +void LodeZlib_DecompressSettings_init(LodeZlib_DecompressSettings* settings) +{ + settings->ignoreAdler32 = 0; +} + +const LodeZlib_DecompressSettings LodeZlib_defaultDecompressSettings = {0}; + +#endif /*LODEPNG_COMPILE_DECODER*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* ////////////////////////////////////////////////////////////////////////// */ +/* ////////////////////////////////////////////////////////////////////////// */ +/* ////////////////////////////////////////////////////////////////////////// */ +/* ////////////////////////////////////////////////////////////////////////// */ +/* // End of Zlib related code, now comes the PNG related code that uses it// */ +/* ////////////////////////////////////////////////////////////////////////// */ +/* ////////////////////////////////////////////////////////////////////////// */ +/* ////////////////////////////////////////////////////////////////////////// */ +/* ////////////////////////////////////////////////////////////////////////// */ +/* ////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_PNG + +/* +The two functions below (LodePNG_decompress and LodePNG_compress) directly call the +LodeZlib_decompress and LodeZlib_compress functions. The only purpose of the functions +below, is to provide the ability to let LodePNG use a different Zlib encoder by only +changing the two functions below, instead of changing it inside the vareous places +in the other LodePNG functions. + +*out must be NULL and *outsize must be 0 initially, and after the function is done, +*out must point to the decompressed data, *outsize must be the size of it, and must +be the size of the useful data in bytes, not the alloc size. +*/ + +#ifdef LODEPNG_COMPILE_DECODER +static unsigned LodePNG_decompress(unsigned char** out, size_t* outsize, const unsigned char* in, size_t insize, const LodeZlib_DecompressSettings* settings) +{ + /*replace this by custom function call to use an alterntive zlib codec*/ + return LodeZlib_decompress(out, outsize, in, insize, settings); +} +#endif /*LODEPNG_COMPILE_DECODER*/ +#ifdef LODEPNG_COMPILE_ENCODER +static unsigned LodePNG_compress(unsigned char** out, size_t* outsize, const unsigned char* in, size_t insize, const LodeZlib_CompressSettings* settings) +{ + /*replace this by custom function call to use an alterntive zlib codec*/ + return LodeZlib_compress(out, outsize, in, insize, settings); +} +#endif /*LODEPNG_COMPILE_ENCODER*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / CRC32 / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +static unsigned Crc32_crc_table_computed = 0; +static unsigned Crc32_crc_table[256]; + +/*Make the table for a fast CRC.*/ +static void Crc32_make_crc_table(void) +{ + unsigned c, k, n; + for(n = 0; n < 256; n++) + { + c = n; + for(k = 0; k < 8; k++) + { + if(c & 1) c = 0xedb88320L ^ (c >> 1); + else c = c >> 1; + } + Crc32_crc_table[n] = c; + } + Crc32_crc_table_computed = 1; +} + +/*Update a running CRC with the bytes buf[0..len-1]--the CRC should be +initialized to all 1's, and the transmitted value is the 1's complement of the +final running CRC (see the crc() routine below).*/ +static unsigned Crc32_update_crc(const unsigned char* buf, unsigned crc, size_t len) +{ + unsigned c = crc; + size_t n; + + if(!Crc32_crc_table_computed) Crc32_make_crc_table(); + for(n = 0; n < len; n++) + { + c = Crc32_crc_table[(c ^ buf[n]) & 0xff] ^ (c >> 8); + } + return c; +} + +/*Return the CRC of the bytes buf[0..len-1].*/ +static unsigned Crc32_crc(const unsigned char* buf, size_t len) +{ + return Crc32_update_crc(buf, 0xffffffffL, len) ^ 0xffffffffL; +} + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Reading and writing single bits and bytes from/to stream for LodePNG / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +static unsigned char readBitFromReversedStream(size_t* bitpointer, const unsigned char* bitstream) +{ + unsigned char result = (unsigned char)((bitstream[(*bitpointer) >> 3] >> (7 - ((*bitpointer) & 0x7))) & 1); + (*bitpointer)++; + return result; +} + +static unsigned readBitsFromReversedStream(size_t* bitpointer, const unsigned char* bitstream, size_t nbits) +{ + unsigned result = 0; + size_t i; + for(i = nbits - 1; i < nbits; i--) + { + result += (unsigned)readBitFromReversedStream(bitpointer, bitstream) << i; + } + return result; +} + +#ifdef LODEPNG_COMPILE_DECODER +static void setBitOfReversedStream0(size_t* bitpointer, unsigned char* bitstream, unsigned char bit) +{ + /*the current bit in bitstream must be 0 for this to work*/ + if(bit) bitstream[(*bitpointer) >> 3] |= (bit << (7 - ((*bitpointer) & 0x7))); /*earlier bit of huffman code is in a lesser significant bit of an earlier byte*/ + (*bitpointer)++; +} +#endif /*LODEPNG_COMPILE_DECODER*/ + +static void setBitOfReversedStream(size_t* bitpointer, unsigned char* bitstream, unsigned char bit) +{ + /*the current bit in bitstream may be 0 or 1 for this to work*/ + if(bit == 0) bitstream[(*bitpointer) >> 3] &= (unsigned char)(~(1 << (7 - ((*bitpointer) & 0x7)))); + else bitstream[(*bitpointer) >> 3] |= (1 << (7 - ((*bitpointer) & 0x7))); + (*bitpointer)++; +} + +static unsigned LodePNG_read32bitInt(const unsigned char* buffer) +{ + return (buffer[0] << 24) | (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]; +} + +static void LodePNG_set32bitInt(unsigned char* buffer, unsigned value) /*buffer must have at least 4 allocated bytes available*/ +{ + buffer[0] = (unsigned char)((value >> 24) & 0xff); + buffer[1] = (unsigned char)((value >> 16) & 0xff); + buffer[2] = (unsigned char)((value >> 8) & 0xff); + buffer[3] = (unsigned char)((value ) & 0xff); +} + +#ifdef LODEPNG_COMPILE_ENCODER +static void LodePNG_add32bitInt(ucvector* buffer, unsigned value) +{ + ucvector_resize(buffer, buffer->size + 4); /*todo: give error if resize failed*/ + LodePNG_set32bitInt(&buffer->data[buffer->size - 4], value); +} +#endif /*LODEPNG_COMPILE_ENCODER*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / PNG chunks / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +unsigned LodePNG_chunk_length(const unsigned char* chunk) /*get the length of the data of the chunk. Total chunk length has 12 bytes more.*/ +{ + return LodePNG_read32bitInt(&chunk[0]); +} + +void LodePNG_chunk_type(char type[5], const unsigned char* chunk) /*puts the 4-byte type in null terminated string*/ +{ + unsigned i; + for(i = 0; i < 4; i++) type[i] = chunk[4 + i]; + type[4] = 0; /*null termination char*/ +} + +unsigned char LodePNG_chunk_type_equals(const unsigned char* chunk, const char* type) /*check if the type is the given type*/ +{ + if(strlen(type) != 4) return 0; + return (chunk[4] == type[0] && chunk[5] == type[1] && chunk[6] == type[2] && chunk[7] == type[3]); +} + +/*properties of PNG chunks gotten from capitalization of chunk type name, as defined by the standard*/ +unsigned char LodePNG_chunk_critical(const unsigned char* chunk) /*0: ancillary chunk, 1: it's one of the critical chunk types*/ +{ + return((chunk[4] & 32) == 0); +} + +unsigned char LodePNG_chunk_private(const unsigned char* chunk) /*0: public, 1: private*/ +{ + return((chunk[6] & 32) != 0); +} + +unsigned char LodePNG_chunk_safetocopy(const unsigned char* chunk) /*0: the chunk is unsafe to copy, 1: the chunk is safe to copy*/ +{ + return((chunk[7] & 32) != 0); +} + +unsigned char* LodePNG_chunk_data(unsigned char* chunk) /*get pointer to the data of the chunk*/ +{ + return &chunk[8]; +} + +const unsigned char* LodePNG_chunk_data_const(const unsigned char* chunk) /*get pointer to the data of the chunk*/ +{ + return &chunk[8]; +} + +unsigned LodePNG_chunk_check_crc(const unsigned char* chunk) /*returns 0 if the crc is correct, error code if it's incorrect*/ +{ + unsigned length = LodePNG_chunk_length(chunk); + unsigned CRC = LodePNG_read32bitInt(&chunk[length + 8]); + unsigned checksum = Crc32_crc(&chunk[4], length + 4); /*the CRC is taken of the data and the 4 chunk type letters, not the length*/ + if(CRC != checksum) return 1; + else return 0; +} + +void LodePNG_chunk_generate_crc(unsigned char* chunk) /*generates the correct CRC from the data and puts it in the last 4 bytes of the chunk*/ +{ + unsigned length = LodePNG_chunk_length(chunk); + unsigned CRC = Crc32_crc(&chunk[4], length + 4); + LodePNG_set32bitInt(chunk + 8 + length, CRC); +} + +unsigned char* LodePNG_chunk_next(unsigned char* chunk) /*don't use on IEND chunk, as there is no next chunk then*/ +{ + unsigned total_chunk_length = LodePNG_chunk_length(chunk) + 12; + return &chunk[total_chunk_length]; +} + +const unsigned char* LodePNG_chunk_next_const(const unsigned char* chunk) /*don't use on IEND chunk, as there is no next chunk then*/ +{ + unsigned total_chunk_length = LodePNG_chunk_length(chunk) + 12; + return &chunk[total_chunk_length]; +} + +unsigned LodePNG_append_chunk(unsigned char** out, size_t* outlength, const unsigned char* chunk) /*appends chunk that was already created, to the data. Returns error code.*/ +{ + unsigned i; + unsigned total_chunk_length = LodePNG_chunk_length(chunk) + 12; + unsigned char *chunk_start, *new_buffer; + size_t new_length = (*outlength) + total_chunk_length; + if(new_length < total_chunk_length || new_length < (*outlength)) return 77; /*integer overflow happened*/ + + new_buffer = (unsigned char*)realloc(*out, new_length); + if(!new_buffer) return 9929; /*memory allocation failed*/ + (*out) = new_buffer; + (*outlength) = new_length; + chunk_start = &(*out)[new_length - total_chunk_length]; + + for(i = 0; i < total_chunk_length; i++) chunk_start[i] = chunk[i]; + + return 0; +} + +unsigned LodePNG_create_chunk(unsigned char** out, size_t* outlength, unsigned length, const char* type, const unsigned char* data) /*appends new chunk to out. Returns error code; may change memory address of out buffer*/ +{ + unsigned i; + unsigned char *chunk, *new_buffer; + size_t new_length = (*outlength) + length + 12; + if(new_length < length + 12 || new_length < (*outlength)) return 77; /*integer overflow happened*/ + new_buffer = (unsigned char*)realloc(*out, new_length); + if(!new_buffer) return 9930; /*memory allocation failed*/ + (*out) = new_buffer; + (*outlength) = new_length; + chunk = &(*out)[(*outlength) - length - 12]; + + /*1: length*/ + LodePNG_set32bitInt(chunk, (unsigned)length); + + /*2: chunk name (4 letters)*/ + chunk[4] = type[0]; + chunk[5] = type[1]; + chunk[6] = type[2]; + chunk[7] = type[3]; + + /*3: the data*/ + for(i = 0; i < length; i++) chunk[8 + i] = data[i]; + + /*4: CRC (of the chunkname characters and the data)*/ + LodePNG_chunk_generate_crc(chunk); + + return 0; +} + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / Color types and such / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/*return type is a LodePNG error code*/ +static unsigned checkColorValidity(unsigned colorType, unsigned bd) /*bd = bitDepth*/ +{ + switch(colorType) + { + case 0: if(!(bd == 1 || bd == 2 || bd == 4 || bd == 8 || bd == 16)) return 37; break; /*grey*/ + case 2: if(!( bd == 8 || bd == 16)) return 37; break; /*RGB*/ + case 3: if(!(bd == 1 || bd == 2 || bd == 4 || bd == 8 )) return 37; break; /*palette*/ + case 4: if(!( bd == 8 || bd == 16)) return 37; break; /*grey + alpha*/ + case 6: if(!( bd == 8 || bd == 16)) return 37; break; /*RGBA*/ + default: return 31; + } + return 0; /*allowed color type / bits combination*/ +} + +static unsigned getNumColorChannels(unsigned colorType) +{ + switch(colorType) + { + case 0: return 1; /*grey*/ + case 2: return 3; /*RGB*/ + case 3: return 1; /*palette*/ + case 4: return 2; /*grey + alpha*/ + case 6: return 4; /*RGBA*/ + } + return 0; /*unexisting color type*/ +} + +static unsigned getBpp(unsigned colorType, unsigned bitDepth) +{ + return getNumColorChannels(colorType) * bitDepth; /*bits per pixel is amount of channels * bits per channel*/ +} + +/* ////////////////////////////////////////////////////////////////////////// */ + +void LodePNG_InfoColor_init(LodePNG_InfoColor* info) +{ + info->key_defined = 0; + info->key_r = info->key_g = info->key_b = 0; + info->colorType = 6; + info->bitDepth = 8; + info->palette = 0; + info->palettesize = 0; +} + +void LodePNG_InfoColor_cleanup(LodePNG_InfoColor* info) +{ + LodePNG_InfoColor_clearPalette(info); +} + +void LodePNG_InfoColor_clearPalette(LodePNG_InfoColor* info) +{ + if(info->palette) free(info->palette); + info->palettesize = 0; +} + +unsigned LodePNG_InfoColor_addPalette(LodePNG_InfoColor* info, unsigned char r, unsigned char g, unsigned char b, unsigned char a) +{ + unsigned char* data; + /*the same resize technique as C++ std::vectors is used, and here it's made so that for a palette with the max of 256 colors, it'll have the exact alloc size*/ + if(!(info->palettesize & (info->palettesize - 1))) /*if palettesize is 0 or a power of two*/ + { + /*allocated data must be at least 4* palettesize (for 4 color bytes)*/ + size_t alloc_size = info->palettesize == 0 ? 4 : info->palettesize * 4 * 2; + data = (unsigned char*)realloc(info->palette, alloc_size); + if(!data) return 9931; /*memory allocation failed*/ + else info->palette = data; + } + info->palette[4 * info->palettesize + 0] = r; + info->palette[4 * info->palettesize + 1] = g; + info->palette[4 * info->palettesize + 2] = b; + info->palette[4 * info->palettesize + 3] = a; + info->palettesize++; + return 0; +} + +unsigned LodePNG_InfoColor_getBpp(const LodePNG_InfoColor* info) +{ + return getBpp(info->colorType, info->bitDepth); /*calculate bits per pixel out of colorType and bitDepth*/ +} + +unsigned LodePNG_InfoColor_getChannels(const LodePNG_InfoColor* info) +{ + return getNumColorChannels(info->colorType); +} + +unsigned LodePNG_InfoColor_isGreyscaleType(const LodePNG_InfoColor* info) +{ + return info->colorType == 0 || info->colorType == 4; +} + +unsigned LodePNG_InfoColor_isAlphaType(const LodePNG_InfoColor* info) +{ + return (info->colorType & 4) != 0; +} + +unsigned LodePNG_InfoColor_isPaletteType(const LodePNG_InfoColor* info) +{ + return info->colorType == 3; +} + +unsigned LodePNG_InfoColor_hasPaletteAlpha(const LodePNG_InfoColor* info) +{ + size_t i; + for(i = 0; i < info->palettesize; i++) + { + if(info->palette[i * 4 + 3] < 255) return 1; + } + return 0; +} + +unsigned LodePNG_InfoColor_canHaveAlpha(const LodePNG_InfoColor* info) +{ + return info->key_defined + || LodePNG_InfoColor_isAlphaType(info) + || LodePNG_InfoColor_hasPaletteAlpha(info); +} + +unsigned LodePNG_InfoColor_equal(const LodePNG_InfoColor* info1, const LodePNG_InfoColor* info2) +{ + return info1->colorType == info2->colorType + && info1->bitDepth == info2->bitDepth; /*palette and color key not compared*/ +} + +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + +void LodePNG_UnknownChunks_init(LodePNG_UnknownChunks* chunks) +{ + unsigned i; + for(i = 0; i < 3; i++) chunks->data[i] = 0; + for(i = 0; i < 3; i++) chunks->datasize[i] = 0; +} + +void LodePNG_UnknownChunks_cleanup(LodePNG_UnknownChunks* chunks) +{ + unsigned i; + for(i = 0; i < 3; i++) free(chunks->data[i]); +} + +unsigned LodePNG_UnknownChunks_copy(LodePNG_UnknownChunks* dest, const LodePNG_UnknownChunks* src) +{ + unsigned i; + + LodePNG_UnknownChunks_cleanup(dest); + + for(i = 0; i < 3; i++) + { + size_t j; + dest->datasize[i] = src->datasize[i]; + dest->data[i] = (unsigned char*)malloc(src->datasize[i]); + if(!dest->data[i] && dest->datasize[i]) return 9932; /*memory allocation failed*/ + for(j = 0; j < src->datasize[i]; j++) dest->data[i][j] = src->data[i][j]; + } + + return 0; +} + +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + +void LodePNG_Text_init(LodePNG_Text* text) +{ + text->num = 0; + text->keys = NULL; + text->strings = NULL; +} + +void LodePNG_Text_cleanup(LodePNG_Text* text) +{ + LodePNG_Text_clear(text); +} + +unsigned LodePNG_Text_copy(LodePNG_Text* dest, const LodePNG_Text* source) +{ + size_t i = 0; + dest->keys = 0; + dest->strings = 0; + dest->num = 0; + for(i = 0; i < source->num; i++) + { + unsigned error = LodePNG_Text_add(dest, source->keys[i], source->strings[i]); + if(error) return error; + } + return 0; +} + +void LodePNG_Text_clear(LodePNG_Text* text) +{ + size_t i; + for(i = 0; i < text->num; i++) + { + string_cleanup(&text->keys[i]); + string_cleanup(&text->strings[i]); + } + free(text->keys); + free(text->strings); +} + +unsigned LodePNG_Text_add(LodePNG_Text* text, const char* key, const char* str) +{ + char** new_keys = (char**)(realloc(text->keys, sizeof(char*) * (text->num + 1))); + char** new_strings = (char**)(realloc(text->strings, sizeof(char*) * (text->num + 1))); + if(!new_keys || !new_strings) + { + free(new_keys); + free(new_strings); + return 9933; /*memory allocation failed*/ + } + + text->num++; + text->keys = new_keys; + text->strings = new_strings; + + string_init(&text->keys[text->num - 1]); + string_set(&text->keys[text->num - 1], key); + + string_init(&text->strings[text->num - 1]); + string_set(&text->strings[text->num - 1], str); + + return 0; +} + +/******************************************************************************/ + +void LodePNG_IText_init(LodePNG_IText* text) +{ + text->num = 0; + text->keys = NULL; + text->langtags = NULL; + text->transkeys = NULL; + text->strings = NULL; +} + +void LodePNG_IText_cleanup(LodePNG_IText* text) +{ + LodePNG_IText_clear(text); +} + +unsigned LodePNG_IText_copy(LodePNG_IText* dest, const LodePNG_IText* source) +{ + size_t i = 0; + dest->keys = 0; + dest->langtags = 0; + dest->transkeys = 0; + dest->strings = 0; + dest->num = 0; + for(i = 0; i < source->num; i++) + { + unsigned error = LodePNG_IText_add(dest, source->keys[i], source->langtags[i], source->transkeys[i], source->strings[i]); + if(error) return error; + } + return 0; +} + +void LodePNG_IText_clear(LodePNG_IText* text) +{ + size_t i; + for(i = 0; i < text->num; i++) + { + string_cleanup(&text->keys[i]); + string_cleanup(&text->langtags[i]); + string_cleanup(&text->transkeys[i]); + string_cleanup(&text->strings[i]); + } + free(text->keys); + free(text->langtags); + free(text->transkeys); + free(text->strings); +} + +unsigned LodePNG_IText_add(LodePNG_IText* text, const char* key, const char* langtag, const char* transkey, const char* str) +{ + char** new_keys = (char**)(realloc(text->keys, sizeof(char*) * (text->num + 1))); + char** new_langtags = (char**)(realloc(text->langtags, sizeof(char*) * (text->num + 1))); + char** new_transkeys = (char**)(realloc(text->transkeys, sizeof(char*) * (text->num + 1))); + char** new_strings = (char**)(realloc(text->strings, sizeof(char*) * (text->num + 1))); + if(!new_keys || !new_langtags || !new_transkeys || !new_strings) + { + free(new_keys); + free(new_langtags); + free(new_transkeys); + free(new_strings); + return 9934; /*memory allocation failed*/ + } + + text->num++; + text->keys = new_keys; + text->langtags = new_langtags; + text->transkeys = new_transkeys; + text->strings = new_strings; + + string_init(&text->keys[text->num - 1]); + string_set(&text->keys[text->num - 1], key); + + string_init(&text->langtags[text->num - 1]); + string_set(&text->langtags[text->num - 1], langtag); + + string_init(&text->transkeys[text->num - 1]); + string_set(&text->transkeys[text->num - 1], transkey); + + string_init(&text->strings[text->num - 1]); + string_set(&text->strings[text->num - 1], str); + + return 0; +} + +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + +void LodePNG_InfoPng_init(LodePNG_InfoPng* info) +{ + info->width = info->height = 0; + LodePNG_InfoColor_init(&info->color); + info->interlaceMethod = 0; + info->compressionMethod = 0; + info->filterMethod = 0; +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + info->background_defined = 0; + info->background_r = info->background_g = info->background_b = 0; + + LodePNG_Text_init(&info->text); + LodePNG_IText_init(&info->itext); + + info->time_defined = 0; + info->phys_defined = 0; +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + LodePNG_UnknownChunks_init(&info->unknown_chunks); +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ +} + +void LodePNG_InfoPng_cleanup(LodePNG_InfoPng* info) +{ + LodePNG_InfoColor_cleanup(&info->color); +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + LodePNG_Text_cleanup(&info->text); + LodePNG_IText_cleanup(&info->itext); +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + LodePNG_UnknownChunks_cleanup(&info->unknown_chunks); +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ +} + +unsigned LodePNG_InfoPng_copy(LodePNG_InfoPng* dest, const LodePNG_InfoPng* source) +{ + unsigned error = 0; + LodePNG_InfoPng_cleanup(dest); + *dest = *source; + LodePNG_InfoColor_init(&dest->color); + error = LodePNG_InfoColor_copy(&dest->color, &source->color); if(error) return error; + +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + error = LodePNG_Text_copy(&dest->text, &source->text); if(error) return error; + error = LodePNG_IText_copy(&dest->itext, &source->itext); if(error) return error; +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + LodePNG_UnknownChunks_init(&dest->unknown_chunks); + error = LodePNG_UnknownChunks_copy(&dest->unknown_chunks, &source->unknown_chunks); if(error) return error; +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + return error; +} + +void LodePNG_InfoPng_swap(LodePNG_InfoPng* a, LodePNG_InfoPng* b) +{ + LodePNG_InfoPng temp = *a; + *a = *b; + *b = temp; +} + +unsigned LodePNG_InfoColor_copy(LodePNG_InfoColor* dest, const LodePNG_InfoColor* source) +{ + size_t i; + LodePNG_InfoColor_cleanup(dest); + *dest = *source; + dest->palette = (unsigned char*)malloc(source->palettesize * 4); + if(!dest->palette && source->palettesize) return 9935; /*memory allocation failed*/ + for(i = 0; i < source->palettesize * 4; i++) dest->palette[i] = source->palette[i]; + return 0; +} + +void LodePNG_InfoRaw_init(LodePNG_InfoRaw* info) +{ + LodePNG_InfoColor_init(&info->color); +} + +void LodePNG_InfoRaw_cleanup(LodePNG_InfoRaw* info) +{ + LodePNG_InfoColor_cleanup(&info->color); +} + +unsigned LodePNG_InfoRaw_copy(LodePNG_InfoRaw* dest, const LodePNG_InfoRaw* source) +{ + unsigned error = 0; + LodePNG_InfoRaw_cleanup(dest); + *dest = *source; + LodePNG_InfoColor_init(&dest->color); + error = LodePNG_InfoColor_copy(&dest->color, &source->color); + return error; /*this variable could be removed, but it's more clear what is returned this way*/ +} + +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +converts from any color type to 24-bit or 32-bit (later maybe more supported). return value = LodePNG error code +the out buffer must have (w * h * bpp + 7) / 8 bytes, where bpp is the bits per pixel of the output color type (LodePNG_InfoColor_getBpp) +for < 8 bpp images, there may _not_ be padding bits at the end of scanlines. +*/ +unsigned LodePNG_convert(unsigned char* out, const unsigned char* in, LodePNG_InfoColor* infoOut, LodePNG_InfoColor* infoIn, unsigned w, unsigned h) +{ + const size_t numpixels = w * h; /*amount of pixels*/ + const unsigned OUT_BYTES = LodePNG_InfoColor_getBpp(infoOut) / 8; /*bytes per pixel in the output image*/ + const unsigned OUT_ALPHA = LodePNG_InfoColor_isAlphaType(infoOut); /*use 8-bit alpha channel*/ + size_t i, c, bp = 0; /*bp = bitpointer, used by less-than-8-bit color types*/ + + /*cases where in and out already have the same format*/ + if(LodePNG_InfoColor_equal(infoIn, infoOut)) + { + size_t i; + size_t size = (w * h * LodePNG_InfoColor_getBpp(infoIn) + 7) / 8; + for(i = 0; i < size; i++) out[i] = in[i]; + return 0; + } + + if((infoOut->colorType == 2 || infoOut->colorType == 6) && infoOut->bitDepth == 8) + { + if(infoIn->bitDepth == 8) + { + switch(infoIn->colorType) + { + case 0: /*greyscale color*/ + for(i = 0; i < numpixels; i++) + { + if(OUT_ALPHA) out[OUT_BYTES * i + 3] = 255; + out[OUT_BYTES * i + 0] = in[i]; + out[OUT_BYTES * i + 1] = in[i]; + out[OUT_BYTES * i + 2] = in[i]; + if(OUT_ALPHA && infoIn->key_defined && in[i] == infoIn->key_r) out[OUT_BYTES * i + 3] = 0; + } + break; + case 2: /*RGB color*/ + for(i = 0; i < numpixels; i++) + { + if(OUT_ALPHA) out[OUT_BYTES * i + 3] = 255; + for(c = 0; c < 3; c++) out[OUT_BYTES * i + c] = in[3 * i + c]; + if(OUT_ALPHA && infoIn->key_defined == 1 && in[3 * i + 0] == infoIn->key_r + && in[3 * i + 1] == infoIn->key_g && in[3 * i + 2] == infoIn->key_b) + { + out[OUT_BYTES * i + 3] = 0; + } + } + break; + case 3: /*indexed color (palette)*/ + for(i = 0; i < numpixels; i++) + { + if(OUT_ALPHA) out[OUT_BYTES * i + 3] = 255; + if(in[i] >= infoIn->palettesize) return 46; /*invalid palette index*/ + for(c = 0; c < OUT_BYTES; c++) + { + out[OUT_BYTES * i + c] = infoIn->palette[4 * in[i] + c]; /*get rgb colors from the palette*/ + } + } + break; + case 4: /*greyscale with alpha*/ + for(i = 0; i < numpixels; i++) + { + out[OUT_BYTES * i + 0] = in[2 * i + 0]; + out[OUT_BYTES * i + 1] = in[2 * i + 0]; + out[OUT_BYTES * i + 2] = in[2 * i + 0]; + if(OUT_ALPHA) out[OUT_BYTES * i + 3] = in[2 * i + 1]; + } + break; + case 6: /*RGB with alpha*/ + for(i = 0; i < numpixels; i++) + { + for(c = 0; c < OUT_BYTES; c++) out[OUT_BYTES * i + c] = in[4 * i + c]; + } + break; + default: break; + } + } + else if(infoIn->bitDepth == 16) + { + switch(infoIn->colorType) + { + case 0: /*greyscale color*/ + for(i = 0; i < numpixels; i++) + { + if(OUT_ALPHA) out[OUT_BYTES * i + 3] = 255; + out[OUT_BYTES * i + 0] = in[2 * i]; + out[OUT_BYTES * i + 1] = in[2 * i]; + out[OUT_BYTES * i + 2] = in[2 * i]; + if(OUT_ALPHA && infoIn->key_defined && 256U * in[i] + in[i + 1] == infoIn->key_r) + { + out[OUT_BYTES * i + 3] = 0; + } + } + break; + case 2: /*RGB color*/ + for(i = 0; i < numpixels; i++) + { + if(OUT_ALPHA) out[OUT_BYTES * i + 3] = 255; + for(c = 0; c < 3; c++) out[OUT_BYTES * i + c] = in[6 * i + 2 * c]; + if(OUT_ALPHA && infoIn->key_defined && 256U * in[6 * i + 0] + in[6 * i + 1] == infoIn->key_r + && 256U * in[6 * i + 2] + in[6 * i + 3] == infoIn->key_g && 256U * in[6 * i + 4] + in[6 * i + 5] == infoIn->key_b) + { + out[OUT_BYTES * i + 3] = 0; + } + } + break; + case 4: /*greyscale with alpha*/ + for(i = 0; i < numpixels; i++) + { + out[OUT_BYTES * i + 0] = in[4 * i]; + out[OUT_BYTES * i + 1] = in[4 * i]; + out[OUT_BYTES * i + 2] = in[4 * i]; + if(OUT_ALPHA) out[OUT_BYTES * i + 3] = in[4 * i + 2]; + } + break; + case 6: /*RGB with alpha*/ + for(i = 0; i < numpixels; i++) + { + for(c = 0; c < OUT_BYTES; c++) out[OUT_BYTES * i + c] = in[8 * i + 2 * c]; + } + break; + default: break; + } + } + else /*infoIn->bitDepth is less than 8 bit per channel*/ + { + switch(infoIn->colorType) + { + case 0: /*greyscale color*/ + for(i = 0; i < numpixels; i++) + { + unsigned value = readBitsFromReversedStream(&bp, in, infoIn->bitDepth); + if(OUT_ALPHA) out[OUT_BYTES * i + 3] = 255; + if(OUT_ALPHA && infoIn->key_defined && value + && ((1U << infoIn->bitDepth) - 1U) == infoIn->key_r + && ((1U << infoIn->bitDepth) - 1U)) + { + out[OUT_BYTES * i + 3] = 0; + } + value = (value * 255) / ((1 << infoIn->bitDepth) - 1); /*scale value from 0 to 255*/ + out[OUT_BYTES * i + 0] = (unsigned char)(value); + out[OUT_BYTES * i + 1] = (unsigned char)(value); + out[OUT_BYTES * i + 2] = (unsigned char)(value); + } + break; + case 3: /*indexed color (palette)*/ + for(i = 0; i < numpixels; i++) + { + unsigned value = readBitsFromReversedStream(&bp, in, infoIn->bitDepth); + if(OUT_ALPHA) out[OUT_BYTES * i + 3] = 255; + if(value >= infoIn->palettesize) return 47; + for(c = 0; c < OUT_BYTES; c++) + { + out[OUT_BYTES * i + c] = infoIn->palette[4 * value + c]; /*get rgb colors from the palette*/ + } + } + break; + default: break; + } + } + } + else if(LodePNG_InfoColor_isGreyscaleType(infoOut) && infoOut->bitDepth == 8) /*conversion from greyscale to greyscale*/ + { + if(!LodePNG_InfoColor_isGreyscaleType(infoIn)) return 62; + if(infoIn->bitDepth == 8) + { + switch(infoIn->colorType) + { + case 0: /*greyscale color*/ + for(i = 0; i < numpixels; i++) + { + if(OUT_ALPHA) out[OUT_BYTES * i + 1] = 255; + out[OUT_BYTES * i] = in[i]; + if(OUT_ALPHA && infoIn->key_defined && in[i] == infoIn->key_r) out[OUT_BYTES * i + 1] = 0; + } + break; + case 4: /*greyscale with alpha*/ + for(i = 0; i < numpixels; i++) + { + out[OUT_BYTES * i + 0] = in[2 * i + 0]; + if(OUT_ALPHA) out[OUT_BYTES * i + 1] = in[2 * i + 1]; + } + break; + default: return 31; + } + } + else if(infoIn->bitDepth == 16) + { + switch(infoIn->colorType) + { + case 0: /*greyscale color*/ + for(i = 0; i < numpixels; i++) + { + if(OUT_ALPHA) out[OUT_BYTES * i + 1] = 255; + out[OUT_BYTES * i] = in[2 * i]; + if(OUT_ALPHA && infoIn->key_defined && 256U * in[i] + in[i + 1] == infoIn->key_r) + { + out[OUT_BYTES * i + 1] = 0; + } + } + break; + case 4: /*greyscale with alpha*/ + for(i = 0; i < numpixels; i++) + { + out[OUT_BYTES * i] = in[4 * i]; /*most significant byte*/ + if(OUT_ALPHA) out[OUT_BYTES * i + 1] = in[4 * i + 2]; /*most significant byte*/ + } + break; + default: return 31; + } + } + else /*infoIn->bitDepth is less than 8 bit per channel*/ + { + if(infoIn->colorType != 0) return 31; /*colorType 0 is the only greyscale type with < 8 bits per channel*/ + for(i = 0; i < numpixels; i++) + { + unsigned value = readBitsFromReversedStream(&bp, in, infoIn->bitDepth); + if(OUT_ALPHA) out[OUT_BYTES * i + 1] = 255; + if(OUT_ALPHA && infoIn->key_defined && value + && ((1U << infoIn->bitDepth) - 1U) == infoIn->key_r + && ((1U << infoIn->bitDepth) - 1U)) + { + out[OUT_BYTES * i + 1] = 0; + } + value = (value * 255) / ((1 << infoIn->bitDepth) - 1); /*scale value from 0 to 255*/ + out[OUT_BYTES * i] = (unsigned char)(value); + } + } + } + else return 59; /*invalid color mode*/ + + return 0; +} + +/* +Paeth predicter, used by PNG filter type 4 +The parameters are of type short, but should come from unsigned chars, the shorts +are only needed to make the paeth calculation correct. +*/ +static unsigned char paethPredictor(short a, short b, short c) +{ + short pa = abs(b - c); + short pb = abs(a - c); + short pc = abs(a + b - c - c); + + /*short pc = a + b - c; + short pa = abs(pc - a); + short pb = abs(pc - b); + pc = abs(pc - c);*/ + + if(pa <= pb && pa <= pc) return (unsigned char)a; + else if(pb <= pc) return (unsigned char)b; + else return (unsigned char)c; +} + +/*shared values used by multiple Adam7 related functions*/ + +static const unsigned ADAM7_IX[7] = { 0, 4, 0, 2, 0, 1, 0 }; /*x start values*/ +static const unsigned ADAM7_IY[7] = { 0, 0, 4, 0, 2, 0, 1 }; /*y start values*/ +static const unsigned ADAM7_DX[7] = { 8, 8, 4, 4, 2, 2, 1 }; /*x delta values*/ +static const unsigned ADAM7_DY[7] = { 8, 8, 8, 4, 4, 2, 2 }; /*y delta values*/ + +static void Adam7_getpassvalues(unsigned passw[7], unsigned passh[7], size_t filter_passstart[8], size_t padded_passstart[8], size_t passstart[8], unsigned w, unsigned h, unsigned bpp) +{ + /*the passstart values have 8 values: the 8th one actually indicates the byte after the end of the 7th (= last) pass*/ + unsigned i; + + /*calculate width and height in pixels of each pass*/ + for(i = 0; i < 7; i++) + { + passw[i] = (w + ADAM7_DX[i] - ADAM7_IX[i] - 1) / ADAM7_DX[i]; + passh[i] = (h + ADAM7_DY[i] - ADAM7_IY[i] - 1) / ADAM7_DY[i]; + if(passw[i] == 0) passh[i] = 0; + if(passh[i] == 0) passw[i] = 0; + } + + filter_passstart[0] = padded_passstart[0] = passstart[0] = 0; + for(i = 0; i < 7; i++) + { + filter_passstart[i + 1] = filter_passstart[i] + ((passw[i] && passh[i]) ? passh[i] * (1 + (passw[i] * bpp + 7) / 8) : 0); /*if passw[i] is 0, it's 0 bytes, not 1 (no filtertype-byte)*/ + padded_passstart[i + 1] = padded_passstart[i] + passh[i] * ((passw[i] * bpp + 7) / 8); /*bits padded if needed to fill full byte at end of each scanline*/ + passstart[i + 1] = passstart[i] + (passh[i] * passw[i] * bpp + 7) / 8; /*only padded at end of reduced image*/ + } +} + +#ifdef LODEPNG_COMPILE_DECODER + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / PNG Decoder / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/*read the information from the header and store it in the LodePNG_Info. return value is error*/ +void LodePNG_Decoder_inspect(LodePNG_Decoder* decoder, const unsigned char* in, size_t inlength) +{ + if(inlength == 0 || in == 0) + { + decoder->error = 48; /*the given data is empty*/ + return; + } + if(inlength < 29) + { + decoder->error = 27; /*error: the data length is smaller than the length of a PNG header*/ + return; + } + + /*when decoding a new PNG image, make sure all parameters created after previous decoding are reset*/ + LodePNG_InfoPng_cleanup(&decoder->infoPng); + LodePNG_InfoPng_init(&decoder->infoPng); + decoder->error = 0; + + if(in[0] != 137 || in[1] != 80 || in[2] != 78 || in[3] != 71 || in[4] != 13 || in[5] != 10 || in[6] != 26 || in[7] != 10) + { + decoder->error = 28; /*error: the first 8 bytes are not the correct PNG signature*/ + return; + } + if(in[12] != 'I' || in[13] != 'H' || in[14] != 'D' || in[15] != 'R') + { + decoder->error = 29; /*error: it doesn't start with a IHDR chunk!*/ + return; + } + + /*read the values given in the header*/ + decoder->infoPng.width = LodePNG_read32bitInt(&in[16]); + decoder->infoPng.height = LodePNG_read32bitInt(&in[20]); + decoder->infoPng.color.bitDepth = in[24]; + decoder->infoPng.color.colorType = in[25]; + decoder->infoPng.compressionMethod = in[26]; + decoder->infoPng.filterMethod = in[27]; + decoder->infoPng.interlaceMethod = in[28]; + + if(!decoder->settings.ignoreCrc) + { + unsigned CRC = LodePNG_read32bitInt(&in[29]); + unsigned checksum = Crc32_crc(&in[12], 17); + if(CRC != checksum) + { + decoder->error = 57; /*invalid CRC*/ + return; + } + } + + if(decoder->infoPng.compressionMethod != 0) { decoder->error = 32; return; } /*error: only compression method 0 is allowed in the specification*/ + if(decoder->infoPng.filterMethod != 0) { decoder->error = 33; return; } /*error: only filter method 0 is allowed in the specification*/ + if(decoder->infoPng.interlaceMethod > 1) { decoder->error = 34; return; } /*error: only interlace methods 0 and 1 exist in the specification*/ + + decoder->error = checkColorValidity(decoder->infoPng.color.colorType, decoder->infoPng.color.bitDepth); +} + +static unsigned unfilterScanline(unsigned char* recon, const unsigned char* scanline, const unsigned char* precon, size_t bytewidth, unsigned char filterType, size_t length) +{ + /* + For PNG filter method 0 + unfilter a PNG image scanline by scanline. when the pixels are smaller than 1 byte, the filter works byte per byte (bytewidth = 1) + precon is the previous unfiltered scanline, recon the result, scanline the current one + the incoming scanlines do NOT include the filtertype byte, that one is given in the parameter filterType instead + recon and scanline MAY be the same memory address! precon must be disjoint. + */ + + size_t i; + switch(filterType) + { + case 0: + for(i = 0; i < length; i++) recon[i] = scanline[i]; + break; + case 1: + for(i = 0; i < bytewidth; i++) recon[i] = scanline[i]; + for(i = bytewidth; i < length; i++) recon[i] = scanline[i] + recon[i - bytewidth]; + break; + case 2: + if(precon) + { + for(i = 0; i < length; i++) recon[i] = scanline[i] + precon[i]; + } + else + { + for(i = 0; i < length; i++) recon[i] = scanline[i]; + } + break; + case 3: + if(precon) + { + for(i = 0; i < bytewidth; i++) recon[i] = scanline[i] + precon[i] / 2; + for(i = bytewidth; i < length; i++) recon[i] = scanline[i] + ((recon[i - bytewidth] + precon[i]) / 2); + } + else + { + for(i = 0; i < bytewidth; i++) recon[i] = scanline[i]; + for(i = bytewidth; i < length; i++) recon[i] = scanline[i] + recon[i - bytewidth] / 2; + } + break; + case 4: + if(precon) + { + for(i = 0; i < bytewidth; i++) + { + recon[i] = (scanline[i] + precon[i]); /*paethPredictor(0, precon[i], 0) is always precon[i]*/ + } + for(i = bytewidth; i < length; i++) + { + recon[i] = (scanline[i] + paethPredictor(recon[i - bytewidth], precon[i], precon[i - bytewidth])); + } + } + else + { + for(i = 0; i < bytewidth; i++) + { + recon[i] = scanline[i]; + } + for(i = bytewidth; i < length; i++) + { + recon[i] = (scanline[i] + recon[i - bytewidth]); /*paethPredictor(recon[i - bytewidth], 0, 0) is always recon[i - bytewidth]*/ + } + } + break; + default: return 36; /*error: unexisting filter type given*/ + } + return 0; +} + +static unsigned unfilter(unsigned char* out, const unsigned char* in, unsigned w, unsigned h, unsigned bpp) +{ + /* + For PNG filter method 0 + this function unfilters a single image (e.g. without interlacing this is called once, with Adam7 it's called 7 times) + out must have enough bytes allocated already, in must have the scanlines + 1 filtertype byte per scanline + w and h are image dimensions or dimensions of reduced image, bpp is bits per pixel + in and out are allowed to be the same memory address (but are not the same size because in has the extra filter bytes) + */ + + unsigned y; + unsigned char* prevline = 0; + + size_t bytewidth = (bpp + 7) / 8; /*bytewidth is used for filtering, is 1 when bpp < 8, number of bytes per pixel otherwise*/ + size_t linebytes = (w * bpp + 7) / 8; + + for(y = 0; y < h; y++) + { + size_t outindex = linebytes * y; + size_t inindex = (1 + linebytes) * y; /*the extra filterbyte added to each row*/ + unsigned char filterType = in[inindex]; + + unsigned error = unfilterScanline(&out[outindex], &in[inindex + 1], prevline, bytewidth, filterType, linebytes); + if(error) return error; + + prevline = &out[outindex]; + } + + return 0; +} + +static void Adam7_deinterlace(unsigned char* out, const unsigned char* in, unsigned w, unsigned h, unsigned bpp) +{ + /*Note: this function works on image buffers WITHOUT padding bits at end of scanlines with non-multiple-of-8 bit amounts, only between reduced images is padding + out must be big enough AND must be 0 everywhere if bpp < 8 in the current implementation (because that's likely a little bit faster)*/ + unsigned passw[7], passh[7]; + size_t filter_passstart[8], padded_passstart[8], passstart[8]; + unsigned i; + + Adam7_getpassvalues(passw, passh, filter_passstart, padded_passstart, passstart, w, h, bpp); + + if(bpp >= 8) + { + for(i = 0; i < 7; i++) + { + unsigned x, y, b; + size_t bytewidth = bpp / 8; + for(y = 0; y < passh[i]; y++) + for(x = 0; x < passw[i]; x++) + { + size_t pixelinstart = passstart[i] + (y * passw[i] + x) * bytewidth; + size_t pixeloutstart = ((ADAM7_IY[i] + y * ADAM7_DY[i]) * w + ADAM7_IX[i] + x * ADAM7_DX[i]) * bytewidth; + for(b = 0; b < bytewidth; b++) + { + out[pixeloutstart + b] = in[pixelinstart + b]; + } + } + } + } + else /*bpp < 8: Adam7 with pixels < 8 bit is a bit trickier: with bit pointers*/ + { + for(i = 0; i < 7; i++) + { + unsigned x, y, b; + unsigned ilinebits = bpp * passw[i]; + unsigned olinebits = bpp * w; + size_t obp, ibp; /*bit pointers (for out and in buffer)*/ + for(y = 0; y < passh[i]; y++) + for(x = 0; x < passw[i]; x++) + { + ibp = (8 * passstart[i]) + (y * ilinebits + x * bpp); + obp = (ADAM7_IY[i] + y * ADAM7_DY[i]) * olinebits + (ADAM7_IX[i] + x * ADAM7_DX[i]) * bpp; + for(b = 0; b < bpp; b++) + { + unsigned char bit = readBitFromReversedStream(&ibp, in); + setBitOfReversedStream0(&obp, out, bit); /*note that this function assumes the out buffer is completely 0, use setBitOfReversedStream otherwise*/ + } + } + } + } +} + +static void removePaddingBits(unsigned char* out, const unsigned char* in, size_t olinebits, size_t ilinebits, unsigned h) +{ + /* + After filtering there are still padding bits if scanlines have non multiple of 8 bit amounts. They need to be removed (except at last scanline of (Adam7-reduced) image) before working with pure image buffers for the Adam7 code, the color convert code and the output to the user. + in and out are allowed to be the same buffer, in may also be higher but still overlapping; in must have >= ilinebits*h bits, out must have >= olinebits*h bits, olinebits must be <= ilinebits + also used to move bits after earlier such operations happened, e.g. in a sequence of reduced images from Adam7 + only useful if (ilinebits - olinebits) is a value in the range 1..7 + */ + unsigned y; + size_t diff = ilinebits - olinebits; + size_t ibp = 0, obp = 0; /*input and output bit pointers*/ + for(y = 0; y < h; y++) + { + size_t x; + for(x = 0; x < olinebits; x++) + { + unsigned char bit = readBitFromReversedStream(&ibp, in); + setBitOfReversedStream(&obp, out, bit); + } + ibp += diff; + } +} + +/*out must be buffer big enough to contain full image, and in must contain the full decompressed data from the IDAT chunks (with filter index bytes and possible padding bits)*/ +static unsigned postProcessScanlines(unsigned char* out, unsigned char* in, const LodePNG_InfoPng* infoPng) /*return value is error*/ +{ + /* + This function converts the filtered-padded-interlaced data into pure 2D image buffer with the PNG's colortype. Steps: + *) if no Adam7: 1) unfilter 2) remove padding bits (= posible extra bits per scanline if bpp < 8) + *) if adam7: 1) 7x unfilter 2) 7x remove padding bits 3) Adam7_deinterlace + NOTE: the in buffer will be overwritten with intermediate data! + */ + unsigned bpp = LodePNG_InfoColor_getBpp(&infoPng->color); + unsigned w = infoPng->width; + unsigned h = infoPng->height; + unsigned error = 0; + if(bpp == 0) return 31; /*error: invalid colortype*/ + + if(infoPng->interlaceMethod == 0) + { + if(bpp < 8 && w * bpp != ((w * bpp + 7) / 8) * 8) + { + error = unfilter(in, in, w, h, bpp); + if(error) return error; + removePaddingBits(out, in, w * bpp, ((w * bpp + 7) / 8) * 8, h); + } + else error = unfilter(out, in, w, h, bpp); /*we can immediatly filter into the out buffer, no other steps needed*/ + } + else /*interlaceMethod is 1 (Adam7)*/ + { + unsigned passw[7], passh[7]; size_t filter_passstart[8], padded_passstart[8], passstart[8]; + unsigned i; + + Adam7_getpassvalues(passw, passh, filter_passstart, padded_passstart, passstart, w, h, bpp); + + for(i = 0; i < 7; i++) + { + error = unfilter(&in[padded_passstart[i]], &in[filter_passstart[i]], passw[i], passh[i], bpp); + if(error) return error; + if(bpp < 8) /*TODO: possible efficiency improvement: if in this reduced image the bits fit nicely in 1 scanline, move bytes instead of bits or move not at all*/ + { + /*remove padding bits in scanlines; after this there still may be padding bits between the different reduced images: each reduced image still starts nicely at a byte*/ + removePaddingBits(&in[passstart[i]], &in[padded_passstart[i]], passw[i] * bpp, ((passw[i] * bpp + 7) / 8) * 8, passh[i]); + } + } + + Adam7_deinterlace(out, in, w, h, bpp); + } + + return error; +} + +/*read a PNG, the result will be in the same color type as the PNG (hence "generic")*/ +static void decodeGeneric(LodePNG_Decoder* decoder, unsigned char** out, size_t* outsize, const unsigned char* in, size_t insize) +{ + unsigned char IEND = 0; + const unsigned char* chunk; + size_t i; + ucvector idat; /*the data from idat chunks*/ + + /*for unknown chunk order*/ + unsigned unknown = 0; + unsigned critical_pos = 1; /*1 = after IHDR, 2 = after PLTE, 3 = after IDAT*/ + + /*provide some proper output values if error will happen*/ + *out = 0; + *outsize = 0; + + LodePNG_Decoder_inspect(decoder, in, insize); /*reads header and resets other parameters in decoder->infoPng*/ + if(decoder->error) return; + + ucvector_init(&idat); + + chunk = &in[33]; /*first byte of the first chunk after the header*/ + + while(!IEND) /*loop through the chunks, ignoring unknown chunks and stopping at IEND chunk. IDAT data is put at the start of the in buffer*/ + { + unsigned chunkLength; + const unsigned char* data; /*the data in the chunk*/ + + if((size_t)((chunk - in) + 12) > insize || chunk < in) + { + decoder->error = 30; /*error: size of the in buffer too small to contain next chunk*/ + break; + } + chunkLength = LodePNG_chunk_length(chunk); /*length of the data of the chunk, excluding the length bytes, chunk type and CRC bytes*/ + if(chunkLength > 2147483647) + { + decoder->error = 63; /*chunk length larger than the max PNG chunk size*/ + break; + } + if((size_t)((chunk - in) + chunkLength + 12) > insize || (chunk + chunkLength + 12) < in) + { + decoder->error = 35; /*error: size of the in buffer too small to contain next chunk*/ + break; + } + data = LodePNG_chunk_data_const(chunk); + + /*IDAT chunk, containing compressed image data*/ + if(LodePNG_chunk_type_equals(chunk, "IDAT")) + { + size_t oldsize = idat.size; + if(!ucvector_resize(&idat, oldsize + chunkLength)) + { + decoder->error = 9936; /*memory allocation failed*/ + break; + } + for(i = 0; i < chunkLength; i++) idat.data[oldsize + i] = data[i]; + critical_pos = 3; + } + /*IEND chunk*/ + else if(LodePNG_chunk_type_equals(chunk, "IEND")) + { + IEND = 1; + } + /*palette chunk (PLTE)*/ + else if(LodePNG_chunk_type_equals(chunk, "PLTE")) + { + unsigned pos = 0; + if(decoder->infoPng.color.palette) free(decoder->infoPng.color.palette); + decoder->infoPng.color.palettesize = chunkLength / 3; + decoder->infoPng.color.palette = (unsigned char*)malloc(4 * decoder->infoPng.color.palettesize); + if(!decoder->infoPng.color.palette && decoder->infoPng.color.palettesize) + { + decoder->infoPng.color.palettesize = 0; + decoder->error = 9937; /*memory allocation failed*/ + break; + } + if(decoder->infoPng.color.palettesize > 256) + { + decoder->error = 38; /*error: palette too big*/ + break; + } + for(i = 0; i < decoder->infoPng.color.palettesize; i++) + { + decoder->infoPng.color.palette[4 * i + 0] = data[pos++]; /*R*/ + decoder->infoPng.color.palette[4 * i + 1] = data[pos++]; /*G*/ + decoder->infoPng.color.palette[4 * i + 2] = data[pos++]; /*B*/ + decoder->infoPng.color.palette[4 * i + 3] = 255; /*alpha*/ + } + critical_pos = 2; + } + /*palette transparency chunk (tRNS)*/ + else if(LodePNG_chunk_type_equals(chunk, "tRNS")) + { + if(decoder->infoPng.color.colorType == 3) + { + if(chunkLength > decoder->infoPng.color.palettesize) + { + decoder->error = 39; /*error: more alpha values given than there are palette entries*/ + break; + } + for(i = 0; i < chunkLength; i++) decoder->infoPng.color.palette[4 * i + 3] = data[i]; + } + else if(decoder->infoPng.color.colorType == 0) + { + if(chunkLength != 2) + { + decoder->error = 40; /*error: this chunk must be 2 bytes for greyscale image*/ + break; + } + decoder->infoPng.color.key_defined = 1; + decoder->infoPng.color.key_r = decoder->infoPng.color.key_g = decoder->infoPng.color.key_b = 256 * data[0] + data[1]; + } + else if(decoder->infoPng.color.colorType == 2) + { + if(chunkLength != 6) + { + decoder->error = 41; /*error: this chunk must be 6 bytes for RGB image*/ + break; + } + decoder->infoPng.color.key_defined = 1; + decoder->infoPng.color.key_r = 256 * data[0] + data[1]; + decoder->infoPng.color.key_g = 256 * data[2] + data[3]; + decoder->infoPng.color.key_b = 256 * data[4] + data[5]; + } + else + { + decoder->error = 42; /*error: tRNS chunk not allowed for other color models*/ + break; + } + } +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + /*background color chunk (bKGD)*/ + else if(LodePNG_chunk_type_equals(chunk, "bKGD")) + { + if(decoder->infoPng.color.colorType == 3) + { + if(chunkLength != 1) + { + decoder->error = 43; /*error: this chunk must be 1 byte for indexed color image*/ + break; + } + decoder->infoPng.background_defined = 1; + decoder->infoPng.background_r = decoder->infoPng.background_g = decoder->infoPng.background_b = data[0]; + } + else if(decoder->infoPng.color.colorType == 0 || decoder->infoPng.color.colorType == 4) + { + if(chunkLength != 2) + { + decoder->error = 44; /*error: this chunk must be 2 bytes for greyscale image*/ + break; + } + decoder->infoPng.background_defined = 1; + decoder->infoPng.background_r = decoder->infoPng.background_g = decoder->infoPng.background_b = 256 * data[0] + data[1]; + } + else if(decoder->infoPng.color.colorType == 2 || decoder->infoPng.color.colorType == 6) + { + if(chunkLength != 6) + { + decoder->error = 45; /*error: this chunk must be 6 bytes for greyscale image*/ + break; + } + decoder->infoPng.background_defined = 1; + decoder->infoPng.background_r = 256 * data[0] + data[1]; + decoder->infoPng.background_g = 256 * data[2] + data[3]; + decoder->infoPng.background_b = 256 * data[4] + data[5]; + } + } + /*text chunk (tEXt)*/ + else if(LodePNG_chunk_type_equals(chunk, "tEXt")) + { + if(decoder->settings.readTextChunks) + { + char *key = 0, *str = 0; + + while(!decoder->error) /*not really a while loop, only used to break on error*/ + { + unsigned length, string2_begin; + + length = 0; + while(length < chunkLength && data[length] != 0) length++; + if(length + 1 >= chunkLength) + { + decoder->error = 75; /*error, end reached, no null terminator?*/ + break; + } + key = (char*)malloc(length + 1); + if(!key) + { + decoder->error = 9938; /*memory allocation failed*/ + break; + } + key[length] = 0; + for(i = 0; i < length; i++) key[i] = data[i]; + + string2_begin = length + 1; + if(string2_begin > chunkLength) + { + decoder->error = 75; /*error, end reached, no null terminator?*/ + break; + } + length = chunkLength - string2_begin; + str = (char*)malloc(length + 1); + if(!str) + { + decoder->error = 9939; /*memory allocation failed*/ + break; + } + str[length] = 0; + for(i = 0; i < length; i++) str[i] = data[string2_begin + i]; + + decoder->error = LodePNG_Text_add(&decoder->infoPng.text, key, str); + + break; + } + + free(key); + free(str); + } + } + /*compressed text chunk (zTXt)*/ + else if(LodePNG_chunk_type_equals(chunk, "zTXt")) + { + if(decoder->settings.readTextChunks) + { + unsigned length, string2_begin; + char *key = 0; + ucvector decoded; + + ucvector_init(&decoded); + + while(!decoder->error) /*not really a while loop, only used to break on error*/ + { + for(length = 0; length < chunkLength && data[length] != 0; length++) ; + if(length + 2 >= chunkLength) + { + decoder->error = 75; /*no null termination, corrupt?*/ + break; + } + key = (char*)malloc(length + 1); + if(!key) + { + decoder->error = 9940; /*memory allocation failed*/ + break; + } + key[length] = 0; + for(i = 0; i < length; i++) key[i] = data[i]; + + if(data[length + 1] != 0) + { + decoder->error = 72; /*the 0 byte indicating compression must be 0*/ + break; + } + + string2_begin = length + 2; + if(string2_begin > chunkLength) + { + decoder->error = 75; /*no null termination, corrupt?*/ + break; + } + length = chunkLength - string2_begin; + decoder->error = LodePNG_decompress(&decoded.data, &decoded.size, (unsigned char*)(&data[string2_begin]), length, &decoder->settings.zlibsettings); + if(decoder->error) break; + ucvector_push_back(&decoded, 0); + + decoder->error = LodePNG_Text_add(&decoder->infoPng.text, key, (char*)decoded.data); + + break; + } + + free(key); + ucvector_cleanup(&decoded); + if(decoder->error) break; + } + } + /*international text chunk (iTXt)*/ + else if(LodePNG_chunk_type_equals(chunk, "iTXt")) + { + if(decoder->settings.readTextChunks) + { + unsigned length, begin, compressed; + char *key = 0, *langtag = 0, *transkey = 0; + ucvector decoded; + ucvector_init(&decoded); + + while(!decoder->error) /*not really a while loop, only used to break on error*/ + { + /*Quick check if the chunk length isn't too small. Even without check it'd still fail with other error checks below if it's too short. This just gives a different error code.*/ + if(chunkLength < 5) + { + decoder->error = 76; /*iTXt chunk too short*/ + break; + } + + /*read the key*/ + for(length = 0; length < chunkLength && data[length] != 0; length++) ; + if(length + 2 >= chunkLength) + { + decoder->error = 75; /*no null termination char found*/ + break; + } + key = (char*)malloc(length + 1); + if(!key) + { + decoder->error = 9941; /*memory allocation failed*/ + break; + } + key[length] = 0; + for(i = 0; i < length; i++) key[i] = data[i]; + + /*read the compression method*/ + compressed = data[length + 1]; + if(data[length + 2] != 0) + { + decoder->error = 72; /*the 0 byte indicating compression must be 0*/ + break; + } + + /*read the langtag*/ + begin = length + 3; + length = 0; + for(i = begin; i < chunkLength && data[i] != 0; i++) length++; + if(begin + length + 1 >= chunkLength) + { + decoder->error = 75; /*no null termination char found*/ + break; + } + langtag = (char*)malloc(length + 1); + if(!langtag) + { + decoder->error = 9942; /*memory allocation failed*/ + break; + } + langtag[length] = 0; + for(i = 0; i < length; i++) langtag[i] = data[begin + i]; + + /*read the transkey*/ + begin += length + 1; + length = 0; + for(i = begin; i < chunkLength && data[i] != 0; i++) length++; + if(begin + length + 1 >= chunkLength) + { + decoder->error = 75; /*no null termination, corrupt?*/ + break; + } + transkey = (char*)malloc(length + 1); + if(!transkey) + { + decoder->error = 9943; /*memory allocation failed*/ + break; + } + transkey[length] = 0; + for(i = 0; i < length; i++) transkey[i] = data[begin + i]; + + /*read the actual text*/ + begin += length + 1; + if(begin > chunkLength) + { + decoder->error = 75; /*no null termination, corrupt?*/ + break; + } + length = chunkLength - begin; + + if(compressed) + { + decoder->error = LodePNG_decompress(&decoded.data, &decoded.size, (unsigned char*)(&data[begin]), length, &decoder->settings.zlibsettings); + if(decoder->error) break; + ucvector_push_back(&decoded, 0); + } + else + { + if(!ucvector_resize(&decoded, length + 1)) + { + decoder->error = 9944; /*memory allocation failed*/ + break; + } + decoded.data[length] = 0; + for(i = 0; i < length; i++) decoded.data[i] = data[begin + i]; + } + + decoder->error = LodePNG_IText_add(&decoder->infoPng.itext, key, langtag, transkey, (char*)decoded.data); + + break; + } + + free(key); + free(langtag); + free(transkey); + ucvector_cleanup(&decoded); + if(decoder->error) break; + } + } + else if(LodePNG_chunk_type_equals(chunk, "tIME")) + { + if(chunkLength != 7) + { + decoder->error = 73; /*invalid tIME chunk size*/ + break; + } + decoder->infoPng.time_defined = 1; + decoder->infoPng.time.year = 256 * data[0] + data[+ 1]; + decoder->infoPng.time.month = data[2]; + decoder->infoPng.time.day = data[3]; + decoder->infoPng.time.hour = data[4]; + decoder->infoPng.time.minute = data[5]; + decoder->infoPng.time.second = data[6]; + } + else if(LodePNG_chunk_type_equals(chunk, "pHYs")) + { + if(chunkLength != 9) + { + decoder->error = 74; /*invalid pHYs chunk size*/ + break; + } + decoder->infoPng.phys_defined = 1; + decoder->infoPng.phys_x = 16777216 * data[0] + 65536 * data[1] + 256 * data[2] + data[3]; + decoder->infoPng.phys_y = 16777216 * data[4] + 65536 * data[5] + 256 * data[6] + data[7]; + decoder->infoPng.phys_unit = data[8]; + } +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + else /*it's not an implemented chunk type, so ignore it: skip over the data*/ + { + if(LodePNG_chunk_critical(chunk)) + { + decoder->error = 69; /*error: unknown critical chunk (5th bit of first byte of chunk type is 0)*/ + break; + } + unknown = 1; +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + if(decoder->settings.rememberUnknownChunks) + { + LodePNG_UnknownChunks* unknown = &decoder->infoPng.unknown_chunks; + decoder->error = LodePNG_append_chunk(&unknown->data[critical_pos - 1], &unknown->datasize[critical_pos - 1], chunk); + if(decoder->error) break; + } +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + } + + if(!decoder->settings.ignoreCrc && !unknown) /*check CRC if wanted, only on known chunk types*/ + { + if(LodePNG_chunk_check_crc(chunk)) + { + decoder->error = 57; /*invalid CRC*/ + break; + } + } + + if(!IEND) chunk = LodePNG_chunk_next_const(chunk); + } + + if(!decoder->error) + { + ucvector scanlines; + ucvector_init(&scanlines); + if(!ucvector_resize(&scanlines, ((decoder->infoPng.width * (decoder->infoPng.height * LodePNG_InfoColor_getBpp(&decoder->infoPng.color) + 7)) / 8) + decoder->infoPng.height)) decoder->error = 9945; /*maximum final image length is already reserved in the vector's length - this is not really necessary*/ + if(!decoder->error) + { + decoder->error = LodePNG_decompress(&scanlines.data, &scanlines.size, idat.data, idat.size, &decoder->settings.zlibsettings); /*decompress with the Zlib decompressor*/ + } + + if(!decoder->error) + { + ucvector outv; + ucvector_init(&outv); + if(!ucvector_resizev(&outv, (decoder->infoPng.height * decoder->infoPng.width * LodePNG_InfoColor_getBpp(&decoder->infoPng.color) + 7) / 8, 0)) decoder->error = 9946; + if(!decoder->error) decoder->error = postProcessScanlines(outv.data, scanlines.data, &decoder->infoPng); + *out = outv.data; + *outsize = outv.size; + } + ucvector_cleanup(&scanlines); + } + + ucvector_cleanup(&idat); +} + +void LodePNG_Decoder_decode(LodePNG_Decoder* decoder, unsigned char** out, size_t* outsize, const unsigned char* in, size_t insize) +{ + *out = 0; + *outsize = 0; + decodeGeneric(decoder, out, outsize, in, insize); + if(decoder->error) return; + if(!decoder->settings.color_convert || LodePNG_InfoColor_equal(&decoder->infoRaw.color, &decoder->infoPng.color)) + { + /*same color type, no copying or converting of data needed*/ + /*store the infoPng color settings on the infoRaw so that the infoRaw still reflects what colorType + the raw image has to the end user*/ + if(!decoder->settings.color_convert) + { + decoder->error = LodePNG_InfoColor_copy(&decoder->infoRaw.color, &decoder->infoPng.color); + if(decoder->error) return; + } + } + else + { + /*color conversion needed; sort of copy of the data*/ + unsigned char* data = *out; + + /*TODO: check if this works according to the statement in the documentation: "The converter can convert from greyscale input color type, to 8-bit greyscale or greyscale with alpha"*/ + if(!(decoder->infoRaw.color.colorType == 2 || decoder->infoRaw.color.colorType == 6) && !(decoder->infoRaw.color.bitDepth == 8)) + { + decoder->error = 56; /*unsupported color mode conversion*/ + return; + } + + *outsize = (decoder->infoPng.width * decoder->infoPng.height * LodePNG_InfoColor_getBpp(&decoder->infoRaw.color) + 7) / 8; + *out = (unsigned char*)malloc(*outsize); + if(!(*out)) + { + decoder->error = 9947; /*memory allocation failed*/ + *outsize = 0; + } + else decoder->error = LodePNG_convert(*out, data, &decoder->infoRaw.color, &decoder->infoPng.color, decoder->infoPng.width, decoder->infoPng.height); + free(data); + } +} + +unsigned LodePNG_decode(unsigned char** out, unsigned* w, unsigned* h, const unsigned char* in, size_t insize, unsigned colorType, unsigned bitDepth) +{ + unsigned error; + size_t dummy_size; + LodePNG_Decoder decoder; + LodePNG_Decoder_init(&decoder); + decoder.infoRaw.color.colorType = colorType; + decoder.infoRaw.color.bitDepth = bitDepth; + LodePNG_Decoder_decode(&decoder, out, &dummy_size, in, insize); + error = decoder.error; + *w = decoder.infoPng.width; + *h = decoder.infoPng.height; + LodePNG_Decoder_cleanup(&decoder); + return error; +} + +unsigned LodePNG_decode32(unsigned char** out, unsigned* w, unsigned* h, const unsigned char* in, size_t insize) +{ + return LodePNG_decode(out, w, h, in, insize, 6, 8); +} + +#ifdef LODEPNG_COMPILE_DISK +unsigned LodePNG_decode_file(unsigned char** out, unsigned* w, unsigned* h, const char* filename, unsigned colorType, unsigned bitDepth) +{ + unsigned char* buffer; + size_t buffersize; + unsigned error; + error = LodePNG_loadFile(&buffer, &buffersize, filename); + if(!error) error = LodePNG_decode(out, w, h, buffer, buffersize, colorType, bitDepth); + free(buffer); + return error; +} + +unsigned LodePNG_decode32_file(unsigned char** out, unsigned* w, unsigned* h, const char* filename) +{ + return LodePNG_decode_file(out, w, h, filename, 6, 8); +} +#endif /*LODEPNG_COMPILE_DISK*/ + +void LodePNG_DecodeSettings_init(LodePNG_DecodeSettings* settings) +{ + settings->color_convert = 1; +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + settings->readTextChunks = 1; +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + settings->ignoreCrc = 0; +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + settings->rememberUnknownChunks = 0; +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + LodeZlib_DecompressSettings_init(&settings->zlibsettings); +} + +void LodePNG_Decoder_init(LodePNG_Decoder* decoder) +{ + LodePNG_DecodeSettings_init(&decoder->settings); + LodePNG_InfoRaw_init(&decoder->infoRaw); + LodePNG_InfoPng_init(&decoder->infoPng); + decoder->error = 1; +} + +void LodePNG_Decoder_cleanup(LodePNG_Decoder* decoder) +{ + LodePNG_InfoRaw_cleanup(&decoder->infoRaw); + LodePNG_InfoPng_cleanup(&decoder->infoPng); +} + +void LodePNG_Decoder_copy(LodePNG_Decoder* dest, const LodePNG_Decoder* source) +{ + LodePNG_Decoder_cleanup(dest); + *dest = *source; + LodePNG_InfoRaw_init(&dest->infoRaw); + LodePNG_InfoPng_init(&dest->infoPng); + dest->error = LodePNG_InfoRaw_copy(&dest->infoRaw, &source->infoRaw); if(dest->error) return; + dest->error = LodePNG_InfoPng_copy(&dest->infoPng, &source->infoPng); if(dest->error) return; +} + +#endif /*LODEPNG_COMPILE_DECODER*/ + +#ifdef LODEPNG_COMPILE_ENCODER + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / PNG Encoder / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/*chunkName must be string of 4 characters*/ +static unsigned addChunk(ucvector* out, const char* chunkName, const unsigned char* data, size_t length) +{ + unsigned error = LodePNG_create_chunk(&out->data, &out->size, (unsigned)length, chunkName, data); + if(error) return error; + out->allocsize = out->size; /*fix the allocsize again*/ + return 0; +} + +static void writeSignature(ucvector* out) +{ + /*8 bytes PNG signature, aka the magic bytes*/ + ucvector_push_back(out, 137); + ucvector_push_back(out, 80); + ucvector_push_back(out, 78); + ucvector_push_back(out, 71); + ucvector_push_back(out, 13); + ucvector_push_back(out, 10); + ucvector_push_back(out, 26); + ucvector_push_back(out, 10); +} + +static unsigned addChunk_IHDR(ucvector* out, unsigned w, unsigned h, unsigned bitDepth, unsigned colorType, unsigned interlaceMethod) +{ + unsigned error = 0; + ucvector header; + ucvector_init(&header); + + LodePNG_add32bitInt(&header, w); /*width*/ + LodePNG_add32bitInt(&header, h); /*height*/ + ucvector_push_back(&header, (unsigned char)bitDepth); /*bit depth*/ + ucvector_push_back(&header, (unsigned char)colorType); /*color type*/ + ucvector_push_back(&header, 0); /*compression method*/ + ucvector_push_back(&header, 0); /*filter method*/ + ucvector_push_back(&header, interlaceMethod); /*interlace method*/ + + error = addChunk(out, "IHDR", header.data, header.size); + ucvector_cleanup(&header); + + return error; +} + +static unsigned addChunk_PLTE(ucvector* out, const LodePNG_InfoColor* info) +{ + unsigned error = 0; + size_t i; + ucvector PLTE; + ucvector_init(&PLTE); + for(i = 0; i < info->palettesize * 4; i++) + { + if(i % 4 != 3) ucvector_push_back(&PLTE, info->palette[i]); /*add all channels except alpha channel*/ + } + error = addChunk(out, "PLTE", PLTE.data, PLTE.size); + ucvector_cleanup(&PLTE); + + return error; +} + +static unsigned addChunk_tRNS(ucvector* out, const LodePNG_InfoColor* info) +{ + unsigned error = 0; + size_t i; + ucvector tRNS; + ucvector_init(&tRNS); + if(info->colorType == 3) + { + for(i = 0; i < info->palettesize; i++) ucvector_push_back(&tRNS, info->palette[4 * i + 3]); /*add only alpha channel*/ + } + else if(info->colorType == 0) + { + if(info->key_defined) + { + ucvector_push_back(&tRNS, (unsigned char)(info->key_r / 256)); + ucvector_push_back(&tRNS, (unsigned char)(info->key_r % 256)); + } + } + else if(info->colorType == 2) + { + if(info->key_defined) + { + ucvector_push_back(&tRNS, (unsigned char)(info->key_r / 256)); + ucvector_push_back(&tRNS, (unsigned char)(info->key_r % 256)); + ucvector_push_back(&tRNS, (unsigned char)(info->key_g / 256)); + ucvector_push_back(&tRNS, (unsigned char)(info->key_g % 256)); + ucvector_push_back(&tRNS, (unsigned char)(info->key_b / 256)); + ucvector_push_back(&tRNS, (unsigned char)(info->key_b % 256)); + } + } + + error = addChunk(out, "tRNS", tRNS.data, tRNS.size); + ucvector_cleanup(&tRNS); + + return error; +} + +static unsigned addChunk_IDAT(ucvector* out, const unsigned char* data, size_t datasize, LodeZlib_CompressSettings* zlibsettings) +{ + ucvector zlibdata; + unsigned error = 0; + + /*compress with the Zlib compressor*/ + ucvector_init(&zlibdata); + error = LodePNG_compress(&zlibdata.data, &zlibdata.size, data, datasize, zlibsettings); + if(!error) error = addChunk(out, "IDAT", zlibdata.data, zlibdata.size); + ucvector_cleanup(&zlibdata); + + return error; +} + +static unsigned addChunk_IEND(ucvector* out) +{ + unsigned error = 0; + error = addChunk(out, "IEND", 0, 0); + return error; +} + +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + +static unsigned addChunk_tEXt(ucvector* out, const char* keyword, const char* textstring) /*add text chunk*/ +{ + unsigned error = 0; + size_t i; + ucvector text; + ucvector_init(&text); + for(i = 0; keyword[i] != 0; i++) ucvector_push_back(&text, (unsigned char)keyword[i]); + ucvector_push_back(&text, 0); + for(i = 0; textstring[i] != 0; i++) ucvector_push_back(&text, (unsigned char)textstring[i]); + error = addChunk(out, "tEXt", text.data, text.size); + ucvector_cleanup(&text); + + return error; +} + +static unsigned addChunk_zTXt(ucvector* out, const char* keyword, const char* textstring, LodeZlib_CompressSettings* zlibsettings) +{ + unsigned error = 0; + ucvector data, compressed; + size_t i, textsize = strlen(textstring); + + ucvector_init(&data); + ucvector_init(&compressed); + for(i = 0; keyword[i] != 0; i++) ucvector_push_back(&data, (unsigned char)keyword[i]); + ucvector_push_back(&data, 0); /* 0 termination char*/ + ucvector_push_back(&data, 0); /*compression method: 0*/ + + error = LodePNG_compress(&compressed.data, &compressed.size, (unsigned char*)textstring, textsize, zlibsettings); + if(!error) + { + for(i = 0; i < compressed.size; i++) ucvector_push_back(&data, compressed.data[i]); + error = addChunk(out, "zTXt", data.data, data.size); + } + + ucvector_cleanup(&compressed); + ucvector_cleanup(&data); + return error; +} + +static unsigned addChunk_iTXt(ucvector* out, unsigned compressed, const char* keyword, const char* langtag, const char* transkey, const char* textstring, LodeZlib_CompressSettings* zlibsettings) +{ + unsigned error = 0; + ucvector data, compressed_data; + size_t i, textsize = strlen(textstring); + + ucvector_init(&data); + + for(i = 0; keyword[i] != 0; i++) ucvector_push_back(&data, (unsigned char)keyword[i]); + ucvector_push_back(&data, 0); /*null termination char*/ + ucvector_push_back(&data, compressed ? 1 : 0); /*compression flag*/ + ucvector_push_back(&data, 0); /*compression method*/ + for(i = 0; langtag[i] != 0; i++) ucvector_push_back(&data, (unsigned char)langtag[i]); + ucvector_push_back(&data, 0); /*null termination char*/ + for(i = 0; transkey[i] != 0; i++) ucvector_push_back(&data, (unsigned char)transkey[i]); + ucvector_push_back(&data, 0); /*null termination char*/ + + if(compressed) + { + ucvector_init(&compressed_data); + error = LodePNG_compress(&compressed_data.data, &compressed_data.size, (unsigned char*)textstring, textsize, zlibsettings); + if(!error) + { + for(i = 0; i < compressed_data.size; i++) ucvector_push_back(&data, compressed_data.data[i]); + for(i = 0; textstring[i] != 0; i++) ucvector_push_back(&data, (unsigned char)textstring[i]); + } + } + else /*not compressed*/ + { + for(i = 0; textstring[i] != 0; i++) ucvector_push_back(&data, (unsigned char)textstring[i]); + } + + if(!error) error = addChunk(out, "iTXt", data.data, data.size); + ucvector_cleanup(&data); + return error; +} + +static unsigned addChunk_bKGD(ucvector* out, const LodePNG_InfoPng* info) +{ + unsigned error = 0; + ucvector bKGD; + ucvector_init(&bKGD); + if(info->color.colorType == 0 || info->color.colorType == 4) + { + ucvector_push_back(&bKGD, (unsigned char)(info->background_r / 256)); + ucvector_push_back(&bKGD, (unsigned char)(info->background_r % 256)); + } + else if(info->color.colorType == 2 || info->color.colorType == 6) + { + ucvector_push_back(&bKGD, (unsigned char)(info->background_r / 256)); + ucvector_push_back(&bKGD, (unsigned char)(info->background_r % 256)); + ucvector_push_back(&bKGD, (unsigned char)(info->background_g / 256)); + ucvector_push_back(&bKGD, (unsigned char)(info->background_g % 256)); + ucvector_push_back(&bKGD, (unsigned char)(info->background_b / 256)); + ucvector_push_back(&bKGD, (unsigned char)(info->background_b % 256)); + } + else if(info->color.colorType == 3) + { + ucvector_push_back(&bKGD, (unsigned char)(info->background_r % 256)); /*palette index*/ + } + + error = addChunk(out, "bKGD", bKGD.data, bKGD.size); + ucvector_cleanup(&bKGD); + + return error; +} + +static unsigned addChunk_tIME(ucvector* out, const LodePNG_Time* time) +{ + unsigned error = 0; + unsigned char* data = (unsigned char*)malloc(7); + if(!data) return 9948; /*memory allocation failed*/ + data[0] = (unsigned char)(time->year / 256); + data[1] = (unsigned char)(time->year % 256); + data[2] = time->month; + data[3] = time->day; + data[4] = time->hour; + data[5] = time->minute; + data[6] = time->second; + error = addChunk(out, "tIME", data, 7); + free(data); + return error; +} + +static unsigned addChunk_pHYs(ucvector* out, const LodePNG_InfoPng* info) +{ + unsigned error = 0; + ucvector data; + ucvector_init(&data); + + LodePNG_add32bitInt(&data, info->phys_x); + LodePNG_add32bitInt(&data, info->phys_y); + ucvector_push_back(&data, info->phys_unit); + + error = addChunk(out, "pHYs", data.data, data.size); + ucvector_cleanup(&data); + + return error; +} + +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + +static void filterScanline(unsigned char* out, const unsigned char* scanline, const unsigned char* prevline, size_t length, size_t bytewidth, unsigned char filterType) +{ + size_t i; + switch(filterType) + { + case 0: + for(i = 0; i < length; i++) out[i] = scanline[i]; + break; + case 1: + if(prevline) + { + for(i = 0; i < bytewidth; i++) out[i] = scanline[i]; + for(i = bytewidth; i < length ; i++) out[i] = scanline[i] - scanline[i - bytewidth]; + } + else + { + for(i = 0; i < bytewidth; i++) out[i] = scanline[i]; + for(i = bytewidth; i < length; i++) out[i] = scanline[i] - scanline[i - bytewidth]; + } + break; + case 2: + if(prevline) + { + for(i = 0; i < length; i++) out[i] = scanline[i] - prevline[i]; + } + else + { + for(i = 0; i < length; i++) out[i] = scanline[i]; + } + break; + case 3: + if(prevline) + { + for(i = 0; i < bytewidth; i++) out[i] = scanline[i] - prevline[i] / 2; + for(i = bytewidth; i < length; i++) out[i] = scanline[i] - ((scanline[i - bytewidth] + prevline[i]) / 2); + } + else + { + for(i = 0; i < bytewidth; i++) out[i] = scanline[i]; + for(i = bytewidth; i < length; i++) out[i] = scanline[i] - scanline[i - bytewidth] / 2; + } + break; + case 4: + if(prevline) + { + for(i = 0; i < bytewidth; i++) out[i] = (scanline[i] - prevline[i]); /*paethPredictor(0, prevline[i], 0) is always prevline[i]*/ + for(i = bytewidth; i < length; i++) out[i] = (scanline[i] - paethPredictor(scanline[i - bytewidth], prevline[i], prevline[i - bytewidth])); + } + else + { + for(i = 0; i < bytewidth; i++) out[i] = scanline[i]; + for(i = bytewidth; i < length; i++) out[i] = (scanline[i] - scanline[i - bytewidth]); /*paethPredictor(scanline[i - bytewidth], 0, 0) is always scanline[i - bytewidth]*/ + } + break; + default: return; /*unexisting filter type given*/ + } +} + +static unsigned filter(unsigned char* out, const unsigned char* in, unsigned w, unsigned h, const LodePNG_InfoColor* info) +{ + /* + For PNG filter method 0 + out must be a buffer with as size: h + (w * h * bpp + 7) / 8, because there are the scanlines with 1 extra byte per scanline + + There is a nice heuristic described here: http://www.cs.toronto.edu/~cosmin/pngtech/optipng.html. It says: + * If the image type is Palette, or the bit depth is smaller than 8, then do not filter the image (i.e. use fixed filtering, with the filter None). + * (The other case) If the image type is Grayscale or RGB (with or without Alpha), and the bit depth is not smaller than 8, then use adaptive filtering heuristic as follows: independently for each row, apply all five filters and select the filter that produces the smallest sum of absolute values per row. + + Here the above method is used mostly. Note though that it appears to be better to use the adaptive filtering on the plasma 8-bit palette example, but that image isn't the best reference for palette images in general. + */ + + unsigned bpp = LodePNG_InfoColor_getBpp(info); + size_t linebytes = (w * bpp + 7) / 8; /*the width of a scanline in bytes, not including the filter type*/ + size_t bytewidth = (bpp + 7) / 8; /*bytewidth is used for filtering, is 1 when bpp < 8, number of bytes per pixel otherwise*/ + const unsigned char* prevline = 0; + unsigned x, y; + unsigned heuristic; + unsigned error = 0; + + if(bpp == 0) return 31; /*error: invalid color type*/ + + /*choose heuristic as described above*/ + if(info->colorType == 3 || info->bitDepth < 8) heuristic = 0; + else heuristic = 1; + + if(heuristic == 0) /*None filtertype for everything*/ + { + for(y = 0; y < h; y++) + { + size_t outindex = (1 + linebytes) * y; /*the extra filterbyte added to each row*/ + size_t inindex = linebytes * y; + const unsigned TYPE = 0; + out[outindex] = TYPE; /*filter type byte*/ + filterScanline(&out[outindex + 1], &in[inindex], prevline, linebytes, bytewidth, TYPE); + prevline = &in[inindex]; + } + } + else if(heuristic == 1) /*adaptive filtering*/ + { + size_t sum[5]; + ucvector attempt[5]; /*five filtering attempts, one for each filter type*/ + size_t smallest = 0; + unsigned type, bestType = 0; + + for(type = 0; type < 5; type++) ucvector_init(&attempt[type]); + for(type = 0; type < 5; type++) + { + if(!ucvector_resize(&attempt[type], linebytes)) + { + error = 9949; /*memory allocation failed*/ + break; + } + } + + if(!error) + { + for(y = 0; y < h; y++) + { + /*try the 5 filter types*/ + for(type = 0; type < 5; type++) + { + filterScanline(attempt[type].data, &in[y * linebytes], prevline, linebytes, bytewidth, type); + + /*calculate the sum of the result*/ + sum[type] = 0; + for(x = 0; x < attempt[type].size; x+=3) sum[type] += attempt[type].data[x]; /*note that not all pixels are checked to speed this up while still having probably the best choice*/ + + /*check if this is smallest sum (or if type == 0 it's the first case so always store the values)*/ + if(type == 0 || sum[type] < smallest) + { + bestType = type; + smallest = sum[type]; + } + } + + prevline = &in[y * linebytes]; + + /*now fill the out values*/ + out[y * (linebytes + 1)] = bestType; /*the first byte of a scanline will be the filter type*/ + for(x = 0; x < linebytes; x++) out[y * (linebytes + 1) + 1 + x] = attempt[bestType].data[x]; + } + } + + for(type = 0; type < 5; type++) ucvector_cleanup(&attempt[type]); + } + #if 0 /*deflate the scanline with a fixed tree after every filter attempt to see which one deflates best. This is slow, and _does not work as expected_: the heuristic gives smaller result!*/ + else if(heuristic == 2) /*adaptive filtering by using deflate*/ + { + size_t size[5]; + ucvector attempt[5]; /*five filtering attempts, one for each filter type*/ + size_t smallest; + unsigned type = 0, bestType = 0; + unsigned char* dummy; + LodeZlib_CompressSettings deflatesettings = LodeZlib_defaultCompressSettings; + deflatesettings.btype = 1; /*use fixed tree on the attempts so that the tree is not adapted to the filtertype on purpose, to simulate the true case where the tree is the same for the whole image*/ + for(type = 0; type < 5; type++) + { + ucvector_init(&attempt[type]); + ucvector_resize(&attempt[type], linebytes); /*todo: give error if resize failed*/ + } + for(y = 0; y < h; y++) /*try the 5 filter types*/ + { + for(type = 0; type < 5; type++) + { + filterScanline(attempt[type].data, &in[y * linebytes], prevline, linebytes, bytewidth, type); + size[type] = 0; + dummy = 0; + LodePNG_compress(&dummy, &size[type], attempt[type].data, attempt[type].size, &deflatesettings); + free(dummy); + /*check if this is smallest size (or if type == 0 it's the first case so always store the values)*/ + if(type == 0 || size[type] < smallest) + { + bestType = type; + smallest = size[type]; + } + } + prevline = &in[y * linebytes]; + out[y * (linebytes + 1)] = bestType; /*the first byte of a scanline will be the filter type*/ + for(x = 0; x < linebytes; x++) out[y * (linebytes + 1) + 1 + x] = attempt[bestType].data[x]; + } + for(type = 0; type < 5; type++) ucvector_cleanup(&attempt[type]); + } + #endif + + return error; +} + +static void addPaddingBits(unsigned char* out, const unsigned char* in, size_t olinebits, size_t ilinebits, unsigned h) +{ + /*The opposite of the removePaddingBits function + olinebits must be >= ilinebits*/ + unsigned y; + size_t diff = olinebits - ilinebits; + size_t obp = 0, ibp = 0; /*bit pointers*/ + for(y = 0; y < h; y++) + { + size_t x; + for(x = 0; x < ilinebits; x++) + { + unsigned char bit = readBitFromReversedStream(&ibp, in); + setBitOfReversedStream(&obp, out, bit); + } + /*obp += diff; --> no, fill in some value in the padding bits too, to avoid "Use of uninitialised value of size ###" warning from valgrind*/ + for(x = 0; x < diff; x++) setBitOfReversedStream(&obp, out, 0); + } +} + +static void Adam7_interlace(unsigned char* out, const unsigned char* in, unsigned w, unsigned h, unsigned bpp) +{ + /*Note: this function works on image buffers WITHOUT padding bits at end of scanlines with non-multiple-of-8 bit amounts, only between reduced images is padding*/ + unsigned passw[7], passh[7]; + size_t filter_passstart[8], padded_passstart[8], passstart[8]; + unsigned i; + + Adam7_getpassvalues(passw, passh, filter_passstart, padded_passstart, passstart, w, h, bpp); + + if(bpp >= 8) + { + for(i = 0; i < 7; i++) + { + unsigned x, y, b; + size_t bytewidth = bpp / 8; + for(y = 0; y < passh[i]; y++) + for(x = 0; x < passw[i]; x++) + { + size_t pixelinstart = ((ADAM7_IY[i] + y * ADAM7_DY[i]) * w + ADAM7_IX[i] + x * ADAM7_DX[i]) * bytewidth; + size_t pixeloutstart = passstart[i] + (y * passw[i] + x) * bytewidth; + for(b = 0; b < bytewidth; b++) + { + out[pixeloutstart + b] = in[pixelinstart + b]; + } + } + } + } + else /*bpp < 8: Adam7 with pixels < 8 bit is a bit trickier: with bit pointers*/ + { + for(i = 0; i < 7; i++) + { + unsigned x, y, b; + unsigned ilinebits = bpp * passw[i]; + unsigned olinebits = bpp * w; + size_t obp, ibp; /*bit pointers (for out and in buffer)*/ + for(y = 0; y < passh[i]; y++) + for(x = 0; x < passw[i]; x++) + { + ibp = (ADAM7_IY[i] + y * ADAM7_DY[i]) * olinebits + (ADAM7_IX[i] + x * ADAM7_DX[i]) * bpp; + obp = (8 * passstart[i]) + (y * ilinebits + x * bpp); + for(b = 0; b < bpp; b++) + { + unsigned char bit = readBitFromReversedStream(&ibp, in); + setBitOfReversedStream(&obp, out, bit); + } + } + } + } +} + +/*out must be buffer big enough to contain uncompressed IDAT chunk data, and in must contain the full image*/ +static unsigned preProcessScanlines(unsigned char** out, size_t* outsize, const unsigned char* in, const LodePNG_InfoPng* infoPng) /*return value is error*/ +{ + /* + This function converts the pure 2D image with the PNG's colortype, into filtered-padded-interlaced data. Steps: + *) if no Adam7: 1) add padding bits (= posible extra bits per scanline if bpp < 8) 2) filter + *) if adam7: 1) Adam7_interlace 2) 7x add padding bits 3) 7x filter + */ + unsigned bpp = LodePNG_InfoColor_getBpp(&infoPng->color); + unsigned w = infoPng->width; + unsigned h = infoPng->height; + unsigned error = 0; + + if(infoPng->interlaceMethod == 0) + { + *outsize = h + (h * ((w * bpp + 7) / 8)); /*image size plus an extra byte per scanline + possible padding bits*/ + *out = (unsigned char*)malloc(*outsize); + if(!(*out) && (*outsize)) error = 9950; /*memory allocation failed*/ + + if(!error) + { + if(bpp < 8 && w * bpp != ((w * bpp + 7) / 8) * 8) /*non multiple of 8 bits per scanline, padding bits needed per scanline*/ + { + ucvector padded; + ucvector_init(&padded); + if(!ucvector_resize(&padded, h * ((w * bpp + 7) / 8))) error = 9951; + if(!error) + { + addPaddingBits(padded.data, in, ((w * bpp + 7) / 8) * 8, w * bpp, h); + error = filter(*out, padded.data, w, h, &infoPng->color); + } + ucvector_cleanup(&padded); + } + else error = filter(*out, in, w, h, &infoPng->color); /*we can immediatly filter into the out buffer, no other steps needed*/ + } + } + else /*interlaceMethod is 1 (Adam7)*/ + { + unsigned char* adam7 = (unsigned char*)malloc((h * w * bpp + 7) / 8); + if(!adam7 && ((h * w * bpp + 7) / 8)) error = 9952; /*memory allocation failed*/ + + while(!error) /*not a real while loop, used to break out to cleanup to avoid a goto*/ + { + unsigned passw[7], passh[7]; + size_t filter_passstart[8], padded_passstart[8], passstart[8]; + unsigned i; + + Adam7_getpassvalues(passw, passh, filter_passstart, padded_passstart, passstart, w, h, bpp); + + *outsize = filter_passstart[7]; /*image size plus an extra byte per scanline + possible padding bits*/ + *out = (unsigned char*)malloc(*outsize); + if(!(*out) && (*outsize)) + { + error = 9953; /*memory allocation failed*/ + break; + } + + Adam7_interlace(adam7, in, w, h, bpp); + + for(i = 0; i < 7; i++) + { + if(bpp < 8) + { + ucvector padded; + ucvector_init(&padded); + if(!ucvector_resize(&padded, h * ((w * bpp + 7) / 8))) error = 9954; + if(!error) + { + addPaddingBits(&padded.data[padded_passstart[i]], &adam7[passstart[i]], ((passw[i] * bpp + 7) / 8) * 8, passw[i] * bpp, passh[i]); + error = filter(&(*out)[filter_passstart[i]], &padded.data[padded_passstart[i]], passw[i], passh[i], &infoPng->color); + } + + ucvector_cleanup(&padded); + } + else + { + error = filter(&(*out)[filter_passstart[i]], &adam7[padded_passstart[i]], passw[i], passh[i], &infoPng->color); + } + } + + break; + } + + free(adam7); + } + + return error; +} + +/*palette must have 4 * palettesize bytes allocated*/ +static unsigned isPaletteFullyOpaque(const unsigned char* palette, size_t palettesize) /*palette given in format RGBARGBARGBARGBA...*/ +{ + size_t i; + for(i = 0; i < palettesize; i++) + { + if(palette[4 * i + 3] != 255) return 0; + } + return 1; +} + +/*this function checks if the input image given by the user has no transparent pixels*/ +static unsigned isFullyOpaque(const unsigned char* image, unsigned w, unsigned h, const LodePNG_InfoColor* info) +{ + /*TODO: When the user specified a color key for the input image, then this function must also check for pixels that are the same as the color key and treat those as transparent.*/ + + unsigned i, numpixels = w * h; + if(info->colorType == 6) + { + if(info->bitDepth == 8) + { + for(i = 0; i < numpixels; i++) + { + if(image[i * 4 + 3] != 255) return 0; + } + } + else + { + for(i = 0; i < numpixels; i++) + { + if(image[i * 8 + 6] != 255 || image[i * 8 + 7] != 255) return 0; + } + } + return 1; /*no single pixel with alpha channel other than 255 found*/ + } + else if(info->colorType == 4) + { + if(info->bitDepth == 8) + { + for(i = 0; i < numpixels; i++) + { + if(image[i * 2 + 1] != 255) return 0; + } + } + else + { + for(i = 0; i < numpixels; i++) + { + if(image[i * 4 + 2] != 255 || image[i * 4 + 3] != 255) return 0; + } + } + return 1; /*no single pixel with alpha channel other than 255 found*/ + } + else if(info->colorType == 3) + { + /*when there's a palette, we could check every pixel for translucency, but much quicker is to just check the palette*/ + return(isPaletteFullyOpaque(info->palette, info->palettesize)); + } + + return 0; /*color type that isn't supported by this function yet, so assume there is transparency to be safe*/ +} + +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS +static unsigned addUnknownChunks(ucvector* out, unsigned char* data, size_t datasize) +{ + unsigned char* inchunk = data; + while((size_t)(inchunk - data) < datasize) + { + unsigned error = LodePNG_append_chunk(&out->data, &out->size, inchunk); + if(error) return error; /*error: not enough memory*/ + out->allocsize = out->size; /*fix the allocsize again*/ + inchunk = LodePNG_chunk_next(inchunk); + } + return 0; +} +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + +void LodePNG_Encoder_encode(LodePNG_Encoder* encoder, unsigned char** out, size_t* outsize, const unsigned char* image, unsigned w, unsigned h) +{ + LodePNG_InfoPng info; + ucvector outv; + unsigned char* data = 0; /*uncompressed version of the IDAT chunk data*/ + size_t datasize = 0; + + /*provide some proper output values if error will happen*/ + *out = 0; + *outsize = 0; + encoder->error = 0; + + info = encoder->infoPng; /*UNSAFE copy to avoid having to cleanup! but we will only change primitive parameters, and not invoke the cleanup function nor touch the palette's buffer so we use it safely*/ + info.width = w; + info.height = h; + + if(encoder->settings.autoLeaveOutAlphaChannel && isFullyOpaque(image, w, h, &encoder->infoRaw.color)) + { + /*go to a color type without alpha channel*/ + if(info.color.colorType == 6) info.color.colorType = 2; + else if(info.color.colorType == 4) info.color.colorType = 0; + } + + if(encoder->settings.zlibsettings.windowSize > 32768) + { + encoder->error = 60; /*error: windowsize larger than allowed*/ + return; + } + if(encoder->settings.zlibsettings.btype > 2) + { + encoder->error = 61; /*error: unexisting btype*/ + return; + } + if(encoder->infoPng.interlaceMethod > 1) + { + encoder->error = 71; /*error: unexisting interlace mode*/ + return; + } + if((encoder->error = checkColorValidity(info.color.colorType, info.color.bitDepth))) return; /*error: unexisting color type given*/ + if((encoder->error = checkColorValidity(encoder->infoRaw.color.colorType, encoder->infoRaw.color.bitDepth))) return; /*error: unexisting color type given*/ + + if(!LodePNG_InfoColor_equal(&encoder->infoRaw.color, &info.color)) + { + unsigned char* converted; + size_t size = (w * h * LodePNG_InfoColor_getBpp(&info.color) + 7) / 8; + + if((info.color.colorType != 6 && info.color.colorType != 2) || (info.color.bitDepth != 8)) + { + encoder->error = 59; /*for the output image, only these types are supported*/ + return; + } + converted = (unsigned char*)malloc(size); + if(!converted && size) encoder->error = 9955; /*memory allocation failed*/ + if(!encoder->error) encoder->error = LodePNG_convert(converted, image, &info.color, &encoder->infoRaw.color, w, h); + if(!encoder->error) preProcessScanlines(&data, &datasize, converted, &info);/*filter(data.data, converted.data, w, h, LodePNG_InfoColor_getBpp(&info.color));*/ + free(converted); + } + else preProcessScanlines(&data, &datasize, image, &info);/*filter(data.data, image, w, h, LodePNG_InfoColor_getBpp(&info.color));*/ + + ucvector_init(&outv); + while(!encoder->error) /*not really a while loop, this is only used to break out if an error happens to avoid goto's to do the ucvector cleanup*/ + { +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + size_t i; +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + /*write signature and chunks*/ + writeSignature(&outv); + /*IHDR*/ + addChunk_IHDR(&outv, w, h, info.color.bitDepth, info.color.colorType, info.interlaceMethod); +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + /*unknown chunks between IHDR and PLTE*/ + if(info.unknown_chunks.data[0]) + { + encoder->error = addUnknownChunks(&outv, info.unknown_chunks.data[0], info.unknown_chunks.datasize[0]); + if(encoder->error) break; + } +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + /*PLTE*/ + if(info.color.colorType == 3) + { + if(info.color.palettesize == 0 || info.color.palettesize > 256) + { + encoder->error = 68; /*invalid palette size*/ + break; + } + addChunk_PLTE(&outv, &info.color); + } + if(encoder->settings.force_palette && (info.color.colorType == 2 || info.color.colorType == 6)) + { + if(info.color.palettesize == 0 || info.color.palettesize > 256) + { + encoder->error = 68; /*invalid palette size*/ + break; + } + addChunk_PLTE(&outv, &info.color); + } + /*tRNS*/ + if(info.color.colorType == 3 && !isPaletteFullyOpaque(info.color.palette, info.color.palettesize)) + { + addChunk_tRNS(&outv, &info.color); + } + if((info.color.colorType == 0 || info.color.colorType == 2) && info.color.key_defined) + { + addChunk_tRNS(&outv, &info.color); + } +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + /*bKGD (must come between PLTE and the IDAt chunks*/ + if(info.background_defined) addChunk_bKGD(&outv, &info); + /*pHYs (must come before the IDAT chunks)*/ + if(info.phys_defined) addChunk_pHYs(&outv, &info); +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + /*unknown chunks between PLTE and IDAT*/ + if(info.unknown_chunks.data[1]) + { + encoder->error = addUnknownChunks(&outv, info.unknown_chunks.data[1], info.unknown_chunks.datasize[1]); + if(encoder->error) break; + } +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + /*IDAT (multiple IDAT chunks must be consecutive)*/ + encoder->error = addChunk_IDAT(&outv, data, datasize, &encoder->settings.zlibsettings); + if(encoder->error) break; +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + /*tIME*/ + if(info.time_defined) addChunk_tIME(&outv, &info.time); + /*tEXt and/or zTXt*/ + for(i = 0; i < info.text.num; i++) + { + if(strlen(info.text.keys[i]) > 79) + { + encoder->error = 66; /*text chunk too large*/ + break; + } + if(strlen(info.text.keys[i]) < 1) + { + encoder->error = 67; /*text chunk too small*/ + break; + } + if(encoder->settings.text_compression) + addChunk_zTXt(&outv, info.text.keys[i], info.text.strings[i], &encoder->settings.zlibsettings); + else + addChunk_tEXt(&outv, info.text.keys[i], info.text.strings[i]); + } + /*LodePNG version id in text chunk*/ + if(encoder->settings.add_id) + { + unsigned alread_added_id_text = 0; + for(i = 0; i < info.text.num; i++) + { + if(!strcmp(info.text.keys[i], "LodePNG")) + { + alread_added_id_text = 1; + break; + } + } + if(alread_added_id_text == 0) + addChunk_tEXt(&outv, "LodePNG", VERSION_STRING); /*it's shorter as tEXt than as zTXt chunk*/ + } + /*iTXt*/ + for(i = 0; i < info.itext.num; i++) + { + if(strlen(info.itext.keys[i]) > 79) + { + encoder->error = 66; /*text chunk too large*/ + break; + } + if(strlen(info.itext.keys[i]) < 1) + { + encoder->error = 67; /*text chunk too small*/ + break; + } + addChunk_iTXt(&outv, encoder->settings.text_compression, + info.itext.keys[i], info.itext.langtags[i], info.itext.transkeys[i], info.itext.strings[i], + &encoder->settings.zlibsettings); + } +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + /*unknown chunks between IDAT and IEND*/ + if(info.unknown_chunks.data[2]) + { + encoder->error = addUnknownChunks(&outv, info.unknown_chunks.data[2], info.unknown_chunks.datasize[2]); + if(encoder->error) break; + } +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + /*IEND*/ + addChunk_IEND(&outv); + + break; /*this isn't really a while loop; no error happened so break out now!*/ + } + + free(data); + /*instead of cleaning the vector up, give it to the output*/ + *out = outv.data; + *outsize = outv.size; +} + +unsigned LodePNG_encode(unsigned char** out, size_t* outsize, const unsigned char* image, unsigned w, unsigned h, unsigned colorType, unsigned bitDepth) +{ + unsigned error; + LodePNG_Encoder encoder; + LodePNG_Encoder_init(&encoder); + encoder.infoRaw.color.colorType = colorType; + encoder.infoRaw.color.bitDepth = bitDepth; + LodePNG_Encoder_encode(&encoder, out, outsize, image, w, h); + error = encoder.error; + LodePNG_Encoder_cleanup(&encoder); + return error; +} + +unsigned LodePNG_encode32(unsigned char** out, size_t* outsize, const unsigned char* image, unsigned w, unsigned h) +{ + return LodePNG_encode(out, outsize, image, w, h, 6, 8);; +} + +#ifdef LODEPNG_COMPILE_DISK +unsigned LodePNG_encode_file(const char* filename, const unsigned char* image, unsigned w, unsigned h, unsigned colorType, unsigned bitDepth) +{ + unsigned char* buffer; + size_t buffersize; + unsigned error = LodePNG_encode(&buffer, &buffersize, image, w, h, colorType, bitDepth); + LodePNG_saveFile(buffer, buffersize, filename); + free(buffer); + return error; +} + +unsigned LodePNG_encode32_file(const char* filename, const unsigned char* image, unsigned w, unsigned h) +{ + return LodePNG_encode_file(filename, image, w, h, 6, 8);; +} +#endif /*LODEPNG_COMPILE_DISK*/ + +void LodePNG_EncodeSettings_init(LodePNG_EncodeSettings* settings) +{ + LodeZlib_CompressSettings_init(&settings->zlibsettings); + settings->autoLeaveOutAlphaChannel = 1; + settings->force_palette = 0; +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + settings->add_id = 1; + settings->text_compression = 0; +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ +} + +void LodePNG_Encoder_init(LodePNG_Encoder* encoder) +{ + LodePNG_EncodeSettings_init(&encoder->settings); + LodePNG_InfoPng_init(&encoder->infoPng); + LodePNG_InfoRaw_init(&encoder->infoRaw); + encoder->error = 1; +} + +void LodePNG_Encoder_cleanup(LodePNG_Encoder* encoder) +{ + LodePNG_InfoPng_cleanup(&encoder->infoPng); + LodePNG_InfoRaw_cleanup(&encoder->infoRaw); +} + +void LodePNG_Encoder_copy(LodePNG_Encoder* dest, const LodePNG_Encoder* source) +{ + LodePNG_Encoder_cleanup(dest); + *dest = *source; + LodePNG_InfoPng_init(&dest->infoPng); + LodePNG_InfoRaw_init(&dest->infoRaw); + dest->error = LodePNG_InfoPng_copy(&dest->infoPng, &source->infoPng); + if(dest->error) return; + dest->error = LodePNG_InfoRaw_copy(&dest->infoRaw, &source->infoRaw); + if(dest->error) return; +} + +#endif /*LODEPNG_COMPILE_ENCODER*/ + +#endif /*LODEPNG_COMPILE_PNG*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* / File IO / */ +/* ////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_DISK + +unsigned LodePNG_loadFile(unsigned char** out, size_t* outsize, const char* filename) /*designed for loading files from hard disk in a dynamically allocated buffer*/ +{ + FILE* file; + long size; + + /*provide some proper output values if error will happen*/ + *out = 0; + *outsize = 0; + + file = fopen(filename, "rb"); + if(!file) return 78; + + /*get filesize:*/ + fseek(file , 0 , SEEK_END); + size = ftell(file); + rewind(file); + + /*read contents of the file into the vector*/ + *outsize = 0; + *out = (unsigned char*)malloc((size_t)size); + if(size && (*out)) (*outsize) = fread(*out, 1, (size_t)size, file); + + fclose(file); + if(!(*out) && size) return 80; /*the above malloc failed*/ + return 0; +} + +/*write given buffer to the file, overwriting the file, it doesn't append to it.*/ +unsigned LodePNG_saveFile(const unsigned char* buffer, size_t buffersize, const char* filename) +{ + FILE* file; + file = fopen(filename, "wb" ); + if(!file) return 79; + fwrite((char*)buffer , 1 , buffersize, file); + fclose(file); + return 0; +} + +#endif /*LODEPNG_COMPILE_DISK*/ + +#ifdef LODEPNG_COMPILE_ERROR_TEXT + +/* +This returns the description of a numerical error code in English. This is also +the documentation of all the error codes. +*/ +const char* LodePNG_error_text(unsigned code) +{ + switch(code) + { + case 0: return "no error, everything went ok"; + case 1: return "nothing done yet"; /*the Encoder/Decoder has done nothing yet, so error checking makes no sense yet*/ + case 10: return "end of input memory reached without huffman end code"; /*while huffman decoding*/ + case 11: return "error in code tree made it jump outside of huffman tree"; /*while huffman decoding*/ + case 13: return "problem while processing dynamic deflate block"; + case 14: return "problem while processing dynamic deflate block"; + case 15: return "problem while processing dynamic deflate block"; + case 16: return "unexisting code while processing dynamic deflate block"; + case 17: return "end of out buffer memory reached while inflating"; + case 18: return "invalid distance code while inflating"; + case 19: return "end of out buffer memory reached while inflating"; + case 20: return "invalid deflate block BTYPE encountered while decoding"; + case 21: return "NLEN is not ones complement of LEN in a deflate block"; + + /*end of out buffer memory reached while inflating: + This can happen if the inflated deflate data is longer than the amount of bytes required to fill up + all the pixels of the image, given the color depth and image dimensions. Something that doesn't + happen in a normal, well encoded, PNG image.*/ + case 22: return "end of out buffer memory reached while inflating"; + case 23: return "end of in buffer memory reached while inflating"; + case 24: return "invalid FCHECK in zlib header"; + case 25: return "invalid compression method in zlib header"; + case 26: return "FDICT encountered in zlib header while it's not used for PNG"; + case 27: return "PNG file is smaller than a PNG header"; + case 28: return "incorrect PNG signature, it's no PNG or corrupted"; /*Checks the magic file header, the first 8 bytes of the PNG file*/ + case 29: return "first chunk is not the header chunk"; + case 30: return "chunk length too large, chunk broken off at end of file"; + case 31: return "illegal PNG color type or bpp"; + case 32: return "illegal PNG compression method"; + case 33: return "illegal PNG filter method"; + case 34: return "illegal PNG interlace method"; + case 35: return "chunk length of a chunk is too large or the chunk too small"; + case 36: return "illegal PNG filter type encountered"; + case 37: return "illegal bit depth for this color type given"; + case 38: return "the palette is too big"; /*more than 256 colors*/ + case 39: return "more palette alpha values given in tRNS chunk than there are colors in the palette"; + case 40: return "tRNS chunk has wrong size for greyscale image"; + case 41: return "tRNS chunk has wrong size for RGB image"; + case 42: return "tRNS chunk appeared while it was not allowed for this color type"; + case 43: return "bKGD chunk has wrong size for palette image"; + case 44: return "bKGD chunk has wrong size for greyscale image"; + case 45: return "bKGD chunk has wrong size for RGB image"; + case 46: return "a value in indexed image is larger than the palette size (bitdepth = 8)"; /*Is the palette too small?*/ + case 47: return "a value in indexed image is larger than the palette size (bitdepth < 8)"; /*Is the palette too small?*/ + case 48: return "empty input or file doesn't exist"; /*the input data is empty, maybe a PNG file doesn't exist or is in the wrong path*/ + case 49: return "jumped past memory while generating dynamic huffman tree"; + case 50: return "jumped past memory while generating dynamic huffman tree"; + case 51: return "jumped past memory while inflating huffman block"; + case 52: return "jumped past memory while inflating"; + case 53: return "size of zlib data too small"; + + /*jumped past tree while generating huffman tree, this could be when the + tree will have more leaves than symbols after generating it out of the + given lenghts. They call this an oversubscribed dynamic bit lengths tree in zlib.*/ + case 55: return "jumped past tree while generating huffman tree"; + case 56: return "given output image colorType or bitDepth not supported for color conversion"; + case 57: return "invalid CRC encountered (checking CRC can be disabled)"; + case 58: return "invalid ADLER32 encountered (checking ADLER32 can be disabled)"; + case 59: return "conversion to unexisting color mode or color mode conversion not supported"; + case 60: return "invalid window size given in the settings of the encoder (must be 0-32768)"; + case 61: return "invalid BTYPE given in the settings of the encoder (only 0, 1 and 2 are allowed)"; + case 62: return "conversion from RGB to greyscale not supported"; /*LodePNG leaves the choice of RGB to greyscale conversion formula to the user.*/ + case 63: return "length of a chunk too long, max allowed for PNG is 2147483647 bytes per chunk"; /*(2^31-1)*/ + case 64: return "the length of the END symbol 256 in the Huffman tree is 0"; /*this would result in the inability of a deflated block to ever contain an end code. It must be at least 1.*/ + case 66: return "the length of a text chunk keyword given to the encoder is longer than the maximum of 79 bytes"; + case 67: return "the length of a text chunk keyword given to the encoder is smaller than the minimum of 1 byte"; + case 68: return "tried to encode a PLTE chunk with a palette that has less than 1 or more than 256 colors"; + case 69: return "unknown chunk type with 'critical' flag encountered by the decoder"; + case 71: return "unexisting interlace mode given to encoder (must be 0 or 1)"; + case 72: return "while decoding, unexisting compression method encountering in zTXt or iTXt chunk (it must be 0)"; + case 73: return "invalid tIME chunk size"; + case 74: return "invalid pHYs chunk size"; + case 75: return "no null termination char found while decoding text chunk"; /*length could be wrong, or data chopped off*/ + case 76: return "iTXt chunk too short to contain required bytes"; + case 77: return "integer overflow in buffer size"; + case 78: return "failed to open file for reading"; /*file doesn't exist or couldn't be opened for reading*/ + case 79: return "failed to open file for writing"; + case 80: return "tried creating a tree of 0 symbols"; + default: ; /*nothing to do here, checks for other error values are below*/ + } + + if(code >= 9900 && code <= 9999) return "memory allocation failed"; + + return "unknown error code"; +} + +#endif /*LODEPNG_COMPILE_ERROR_TEXT*/ + +#ifdef __cplusplus +/* ////////////////////////////////////////////////////////////////////////// */ +/* / C++ RAII wrapper / */ +/* ////////////////////////////////////////////////////////////////////////// */ +#ifdef LODEPNG_COMPILE_ZLIB +namespace LodeZlib +{ +#ifdef LODEPNG_COMPILE_DECODER + unsigned decompress(std::vector& out, const unsigned char* in, size_t insize, const LodeZlib_DecompressSettings& settings) + { + unsigned char* buffer = 0; + size_t buffersize = 0; + unsigned error = LodeZlib_decompress(&buffer, &buffersize, in, insize, &settings); + if(buffer) + { + out.insert(out.end(), &buffer[0], &buffer[buffersize]); + free(buffer); + } + return error; + } + + unsigned decompress(std::vector& out, const std::vector& in, const LodeZlib_DecompressSettings& settings) + { + return decompress(out, in.empty() ? 0 : &in[0], in.size(), settings); + } +#endif //LODEPNG_COMPILE_DECODER +#ifdef LODEPNG_COMPILE_ENCODER + unsigned compress(std::vector& out, const unsigned char* in, size_t insize, const LodeZlib_CompressSettings& settings) + { + unsigned char* buffer = 0; + size_t buffersize = 0; + unsigned error = LodeZlib_compress(&buffer, &buffersize, in, insize, &settings); + if(buffer) + { + out.insert(out.end(), &buffer[0], &buffer[buffersize]); + free(buffer); + } + return error; + } + + unsigned compress(std::vector& out, const std::vector& in, const LodeZlib_CompressSettings& settings) + { + return compress(out, in.empty() ? 0 : &in[0], in.size(), settings); + } +#endif //LODEPNG_COMPILE_ENCODER +} //namespace LodeZlib +#endif //LODEPNG_COMPILE_ZLIB + +#ifdef LODEPNG_COMPILE_PNG +namespace LodePNG +{ +#ifdef LODEPNG_COMPILE_DECODER + Decoder::Decoder() + { + LodePNG_Decoder_init(this); + } + + Decoder::~Decoder() + { + LodePNG_Decoder_cleanup(this); + } + + void Decoder::operator=(const LodePNG_Decoder& other) + { + LodePNG_Decoder_copy(this, &other); + } + + bool Decoder::hasError() const + { + return error != 0; + } + unsigned Decoder::getError() const + { + return error; + } + + unsigned Decoder::getWidth() const + { + return infoPng.width; + } + + unsigned Decoder::getHeight() const + { + return infoPng.height; + } + + unsigned Decoder::getBpp() + { + return LodePNG_InfoColor_getBpp(&infoPng.color); + } + + unsigned Decoder::getChannels() + { + return LodePNG_InfoColor_getChannels(&infoPng.color); + } + + unsigned Decoder::isGreyscaleType() + { + return LodePNG_InfoColor_isGreyscaleType(&infoPng.color); + } + + unsigned Decoder::isAlphaType() + { + return LodePNG_InfoColor_isAlphaType(&infoPng.color); + } + + void Decoder::decode(std::vector& out, const unsigned char* in, size_t insize) + { + unsigned char* buffer; + size_t buffersize; + LodePNG_Decoder_decode(this, &buffer, &buffersize, in, insize); + if(buffer) + { + out.insert(out.end(), &buffer[0], &buffer[buffersize]); + free(buffer); + } + } + + void Decoder::decode(std::vector& out, const std::vector& in) + { + decode(out, in.empty() ? 0 : &in[0], in.size()); + } + + void Decoder::inspect(const unsigned char* in, size_t insize) + { + LodePNG_Decoder_inspect(this, in, insize); + } + + void Decoder::inspect(const std::vector& in) + { + inspect(in.empty() ? 0 : &in[0], in.size()); + } + + const LodePNG_DecodeSettings& Decoder::getSettings() const + { + return settings; + } + + LodePNG_DecodeSettings& Decoder::getSettings() + { + return settings; + } + + void Decoder::setSettings(const LodePNG_DecodeSettings& settings) + { + this->settings = settings; + } + + const LodePNG_InfoPng& Decoder::getInfoPng() const + { + return infoPng; + } + + LodePNG_InfoPng& Decoder::getInfoPng() + { + return infoPng; + } + + void Decoder::setInfoPng(const LodePNG_InfoPng& info) + { + error = LodePNG_InfoPng_copy(&this->infoPng, &info); + } + + void Decoder::swapInfoPng(LodePNG_InfoPng& info) + { + LodePNG_InfoPng_swap(&this->infoPng, &info); + } + + const LodePNG_InfoRaw& Decoder::getInfoRaw() const + { + return infoRaw; + } + + LodePNG_InfoRaw& Decoder::getInfoRaw() + { + return infoRaw; + } + + void Decoder::setInfoRaw(const LodePNG_InfoRaw& info) + { + error = LodePNG_InfoRaw_copy(&this->infoRaw, &info); + } + +#endif //LODEPNG_COMPILE_DECODER + + /* ////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_ENCODER + + Encoder::Encoder() + { + LodePNG_Encoder_init(this); + } + + Encoder::~Encoder() + { + LodePNG_Encoder_cleanup(this); + } + + void Encoder::operator=(const LodePNG_Encoder& other) + { + LodePNG_Encoder_copy(this, &other); + } + + bool Encoder::hasError() const + { + return error != 0; + } + + unsigned Encoder::getError() const + { + return error; + } + + void Encoder::encode(std::vector& out, const unsigned char* image, unsigned w, unsigned h) + { + unsigned char* buffer; + size_t buffersize; + LodePNG_Encoder_encode(this, &buffer, &buffersize, image, w, h); + if(buffer) + { + out.insert(out.end(), &buffer[0], &buffer[buffersize]); + free(buffer); + } + } + + void Encoder::encode(std::vector& out, const std::vector& image, unsigned w, unsigned h) + { + encode(out, image.empty() ? 0 : &image[0], w, h); + } + + void Encoder::clearPalette() + { + LodePNG_InfoColor_clearPalette(&infoPng.color); + } + + void Encoder::addPalette(unsigned char r, unsigned char g, unsigned char b, unsigned char a) + { + error = LodePNG_InfoColor_addPalette(&infoPng.color, r, g, b, a); + } + +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + void Encoder::clearText() + { + LodePNG_Text_clear(&infoPng.text); + } + + void Encoder::addText(const std::string& key, const std::string& str) + { + error = LodePNG_Text_add(&infoPng.text, key.c_str(), str.c_str()); + } + + void Encoder::clearIText() + { + LodePNG_IText_clear(&infoPng.itext); + } + + void Encoder::addIText(const std::string& key, const std::string& langtag, const std::string& transkey, const std::string& str) + { + error = LodePNG_IText_add(&infoPng.itext, key.c_str(), langtag.c_str(), transkey.c_str(), str.c_str()); + } + +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + + const LodePNG_EncodeSettings& Encoder::getSettings() const + { + return settings; + } + + LodePNG_EncodeSettings& Encoder::getSettings() + { + return settings; + } + + void Encoder::setSettings(const LodePNG_EncodeSettings& settings) + { + this->settings = settings; + } + + const LodePNG_InfoPng& Encoder::getInfoPng() const + { + return infoPng; + } + + LodePNG_InfoPng& Encoder::getInfoPng() + { + return infoPng; + } + + void Encoder::setInfoPng(const LodePNG_InfoPng& info) + { + error = LodePNG_InfoPng_copy(&this->infoPng, &info); + } + + void Encoder::swapInfoPng(LodePNG_InfoPng& info) + { + LodePNG_InfoPng_swap(&this->infoPng, &info); + } + + const LodePNG_InfoRaw& Encoder::getInfoRaw() const + { + return infoRaw; + } + + LodePNG_InfoRaw& Encoder::getInfoRaw() + { + return infoRaw; + } + + void Encoder::setInfoRaw(const LodePNG_InfoRaw& info) + { + error = LodePNG_InfoRaw_copy(&this->infoRaw, &info); + } + +#endif //LODEPNG_COMPILE_ENCODER + + /* ////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_DISK + + void loadFile(std::vector& buffer, const std::string& filename) //designed for loading files from hard disk in an std::vector + { + std::ifstream file(filename.c_str(), std::ios::in|std::ios::binary|std::ios::ate); + + /*get filesize*/ + std::streamsize size = 0; + if(file.seekg(0, std::ios::end).good()) size = file.tellg(); + if(file.seekg(0, std::ios::beg).good()) size -= file.tellg(); + + /*read contents of the file into the vector*/ + buffer.resize(size_t(size)); + if(size > 0) file.read((char*)(&buffer[0]), size); + } + + /*write given buffer to the file, overwriting the file, it doesn't append to it.*/ + void saveFile(const std::vector& buffer, const std::string& filename) + { + std::ofstream file(filename.c_str(), std::ios::out|std::ios::binary); + file.write(buffer.empty() ? 0 : (char*)&buffer[0], std::streamsize(buffer.size())); + } + +#endif /*LODEPNG_COMPILE_DISK*/ + + /* ////////////////////////////////////////////////////////////////////////// */ + +#ifdef LODEPNG_COMPILE_DECODER + + unsigned decode(std::vector& out, unsigned& w, unsigned& h, const unsigned char* in, size_t insize, unsigned colorType, unsigned bitDepth) + { + Decoder decoder; + decoder.getInfoRaw().color.colorType = colorType; + decoder.getInfoRaw().color.bitDepth = bitDepth; + decoder.decode(out, in, insize); + w = decoder.getWidth(); + h = decoder.getHeight(); + return decoder.getError(); + } + + unsigned decode(std::vector& out, unsigned& w, unsigned& h, const std::vector& in, unsigned colorType, unsigned bitDepth) + { + return decode(out, w, h, in.empty() ? 0 : &in[0], (unsigned)in.size(), colorType, bitDepth); + } + +#ifdef LODEPNG_COMPILE_DISK + unsigned decode(std::vector& out, unsigned& w, unsigned& h, const std::string& filename, unsigned colorType, unsigned bitDepth) + { + std::vector buffer; + loadFile(buffer, filename); + return decode(out, w, h, buffer, colorType, bitDepth); + } + +#endif //LODEPNG_COMPILE_DECODER + +#endif /*LODEPNG_COMPILE_DISK*/ + +#ifdef LODEPNG_COMPILE_ENCODER + + unsigned encode(std::vector& out, const unsigned char* in, unsigned w, unsigned h, unsigned colorType, unsigned bitDepth) + { + Encoder encoder; + encoder.getInfoRaw().color.colorType = colorType; + encoder.getInfoRaw().color.bitDepth = bitDepth; + encoder.encode(out, in, w, h); + return encoder.getError(); + } + + unsigned encode(std::vector& out, const std::vector& in, unsigned w, unsigned h, unsigned colorType, unsigned bitDepth) + { + return encode(out, in.empty() ? 0 : &in[0], w, h, colorType, bitDepth); + } + +#ifdef LODEPNG_COMPILE_DISK + unsigned encode(const std::string& filename, const unsigned char* in, unsigned w, unsigned h, unsigned colorType, unsigned bitDepth) + { + std::vector buffer; + Encoder encoder; + encoder.getInfoRaw().color.colorType = colorType; + encoder.getInfoRaw().color.bitDepth = bitDepth; + encoder.encode(buffer, in, w, h); + if(!encoder.hasError()) saveFile(buffer, filename); + return encoder.getError(); + } + + unsigned encode(const std::string& filename, const std::vector& in, unsigned w, unsigned h, unsigned colorType, unsigned bitDepth) + { + return encode(filename, in.empty() ? 0 : &in[0], w, h, colorType, bitDepth); + } +#endif /*LODEPNG_COMPILE_DISK*/ + +#endif //LODEPNG_COMPILE_ENCODER + +} //namespace LodePNG + +#endif //LODEPNG_COMPILE_PNG + +#endif /*__cplusplus C++ RAII wrapper*/ diff --git a/src/lodepng.h b/src/lodepng.h new file mode 100644 index 0000000..59141a7 --- /dev/null +++ b/src/lodepng.h @@ -0,0 +1,1851 @@ +/* +LodePNG version 20110221 + +Copyright (c) 2005-2011 Lode Vandevenne + +This software is provided 'as-is', without any express or implied +warranty. In no event will the authors be held liable for any damages +arising from the use of this software. + +Permission is granted to anyone to use this software for any purpose, +including commercial applications, and to alter it and redistribute it +freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + + 3. This notice may not be removed or altered from any source + distribution. +*/ + +#ifndef LODEPNG_H +#define LODEPNG_H + +#include /*for size_t*/ + +#ifdef __cplusplus +#include +#include +#endif /*__cplusplus*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* Code Sections */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +The following #defines are used to create code sections. They can be disabled +to disable code sections, which can give faster compile time and smaller binary. +Also, some text editors allow expanding/collapsing #ifdef sections. +*/ + +#define LODEPNG_COMPILE_ZLIB /*deflate&zlib encoder and deflate&zlib decoder*/ +#define LODEPNG_COMPILE_PNG /*png encoder and png decoder*/ +#define LODEPNG_COMPILE_DECODER /*deflate&zlib decoder and png decoder*/ +#define LODEPNG_COMPILE_ENCODER /*deflate&zlib encoder and png encoder*/ +#define LODEPNG_COMPILE_DISK /*the optional built in harddisk file loading and saving functions*/ +#define LODEPNG_COMPILE_ANCILLARY_CHUNKS /*any code or struct datamember related to chunks other than IHDR, IDAT, PLTE, tRNS, IEND*/ +#define LODEPNG_COMPILE_UNKNOWN_CHUNKS /*handling of unknown chunks*/ +#define LODEPNG_COMPILE_ERROR_TEXT /*ability to convert error numerical codes to English text string*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* Simple Functions */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +This are the simple functions, they can be used directly to convert raw data +to/from PNG data. Both the C and C++ simple functions are declared here. + +If more flexibility and settings are required, then the more advanced interface +below this "simple" part has to be used. +*/ + +#ifdef LODEPNG_COMPILE_PNG +#ifdef LODEPNG_COMPILE_DECODER + +/* +LodePNG_decode +Converts PNG data in memory to raw pixel data. +out: Output parameter. Pointer to buffer that will contain the raw pixel data. + Its size is w * h * (bytes per pixel), bytes per pixel depends on colorType and bitDepth. + Must be freed after usage with free(*out). +w: Output parameter. Pointer to width of pixel data. +h: Output parameter. Pointer to height of pixel data. +in: Memory buffer with the PNG file. +insize: size of the in buffer. +colorType: the desired color type for the raw output image. See explanation on PNG color types. +bitDepth: the desired bit depth for the raw output image. See explanation on PNG color types. +Return value: LodePNG error code (0 means no error). +*/ +unsigned LodePNG_decode(unsigned char** out, unsigned* w, unsigned* h, const unsigned char* in, size_t insize, unsigned colorType, unsigned bitDepth); /*return value is error*/ + +/* +LodePNG_decode32 +Converts PNG data in memory to 32-bit raw pixel data. +Same as LodePNG_decode, but uses colorType = 6 and bitDepth = 8 by default. +out: Output parameter. Pointer to buffer that will contain the raw pixel data. + Its size is w * h * 4 bytes. + Must be freed after usage with free(*out). +w: Output parameter. Pointer to width of pixel data. +h: Output parameter. Pointer to height of pixel data. +in: Memory buffer with the PNG file. +insize: size of the in buffer. +Return value: LodePNG error code (0 means no error). +*/ +unsigned LodePNG_decode32(unsigned char** out, unsigned* w, unsigned* h, const unsigned char* in, size_t insize); /*return value is error*/ + +#ifdef LODEPNG_COMPILE_DISK + +/* +LodePNG_decode_file +Load PNG from disk, from file with given name. +out: Output parameter. Pointer to buffer that will contain the raw pixel data. + Its size is w * h * (bytes per pixel), bytes per pixel depends on colorType and bitDepth. + Must be freed after usage with free(*out). +w: Output parameter. Pointer to width of pixel data. +h: Output parameter. Pointer to height of pixel data. +filename: Path on disk of the PNG file. +colorType: the desired color type for the raw output image. See explanation on PNG color types. +bitDepth: the desired bit depth for the raw output image. See explanation on PNG color types. +Return value: LodePNG error code (0 means no error). +*/ +unsigned LodePNG_decode_file(unsigned char** out, unsigned* w, unsigned* h, const char* filename, unsigned colorType, unsigned bitDepth); + +/* +LodePNG_decode32_file +Load PNG from disk to 32-bit RGBA pixel buffer, from file with given name. +Same as LodePNG_decode_file, but uses colorType = 6 and bitDepth = 8 by default. +out: Output parameter. Pointer to buffer that will contain the raw pixel data. + Its size is w * h * 4 bytes. + Must be freed after usage with free(*out). +w: Output parameter. Pointer to width of pixel data. +h: Output parameter. Pointer to height of pixel data. +in: Memory buffer with the PNG file. +insize: size of the in buffer. +Return value: LodePNG error code (0 means no error). +*/ +unsigned LodePNG_decode32_file(unsigned char** out, unsigned* w, unsigned* h, const char* filename); + +#endif /*LODEPNG_COMPILE_DISK*/ +#endif /*LODEPNG_COMPILE_DECODER*/ +#ifdef LODEPNG_COMPILE_ENCODER + +/* +LodePNG_encode +Converts raw pixel data into a PNG image in memory. The colorType and bitDepth + of the output PNG image cannot be chosen, they are automatically determined + by the colorType, bitDepth and content of the input pixel data. +out: Output parameter. Pointer to buffer that will contain the raw pixel data. + Must be freed after usage with free(*out). +outsize: Output parameter. Pointer to the size in bytes of the out buffer. +image: The raw pixel data to encode. The size of this buffer should be + w * h * (bytes per pixel), bytes per pixel depends on colorType and bitDepth. +w: width of the raw pixel data in pixels. +h: height of the raw pixel data in pixels. +colorType: the color type of the raw input image. See explanation on PNG color types. +bitDepth: the bit depth of the raw input image. See explanation on PNG color types. +Return value: LodePNG error code (0 means no error). +*/ +unsigned LodePNG_encode(unsigned char** out, size_t* outsize, const unsigned char* image, unsigned w, unsigned h, unsigned colorType, unsigned bitDepth); /*return value is error*/ + +/* +LodePNG_encode32 +Converts 32-bit RGBA raw pixel data into a PNG image in memory. +Same as LodePNG_encode, but uses colorType = 6 and bitDepth = 8 by default. +out: Output parameter. Pointer to buffer that will contain the raw pixel data. + Must be freed after usage with free(*out). +outsize: Output parameter. Pointer to the size in bytes of the out buffer. +image: The raw pixel data to encode. The size of this buffer should be w * h * 4 bytes. +w: width of the raw pixel data in pixels. +h: height of the raw pixel data in pixels. +Return value: LodePNG error code (0 means no error). +*/ +unsigned LodePNG_encode32(unsigned char** out, size_t* outsize, const unsigned char* image, unsigned w, unsigned h); /*return value is error*/ + +#ifdef LODEPNG_COMPILE_DISK + +/* +LodePNG_encode_file +Converts raw pixel data into a PNG file on disk. Same as LodePNG_encode, but +outputs to disk instead of memory buffer. +filename: path to file on disk to write the PNG image to. +image: The raw pixel data to encode. The size of this buffer should be + w * h * (bytes per pixel), bytes per pixel depends on colorType and bitDepth. +w: width of the raw pixel data in pixels. +h: height of the raw pixel data in pixels. +colorType: the color type of the raw input image. See explanation on PNG color types. +bitDepth: the bit depth of the raw input image. See explanation on PNG color types. +Return value: LodePNG error code (0 means no error). +*/ +unsigned LodePNG_encode_file(const char* filename, const unsigned char* image, unsigned w, unsigned h, unsigned colorType, unsigned bitDepth); + +/* +LodePNG_encode_file +Converts 32-bit RGBA raw pixel data into a PNG file on disk. Same as LodePNG_encode_file, +but uses colorType = 6 and bitDepth = 8 by default. +filename: path to file on disk to write the PNG image to. +image: The raw pixel data to encode. The size of this buffer should be w * h * 4 bytes. +w: width of the raw pixel data in pixels. +h: height of the raw pixel data in pixels. +Return value: LodePNG error code (0 means no error). +*/ +unsigned LodePNG_encode32_file(const char* filename, const unsigned char* image, unsigned w, unsigned h); +#endif /*LODEPNG_COMPILE_DISK*/ +#endif /*LODEPNG_COMPILE_ENCODER*/ + + +#ifdef __cplusplus +namespace LodePNG +{ +#ifdef LODEPNG_COMPILE_DECODER + + /* + LodePNG::decode + Converts PNG data in memory to raw pixel data. + out: Output parameter, std::vector containing the raw pixel data. Its size + will be w * h * (bytes per pixel), where bytes per pixel is 4 if the default + colorType=6 and bitDepth=8 is used. The pixels are 32-bit RGBA bit in that case. + w: Output parameter, width of the image in pixels. + h: Output parameter, height of the image in pixels. + in: Memory buffer with the PNG file. + insize: size of the in buffer. + colorType: the desired color type for the raw output image. See explanation on PNG color types. + bitDepth: the desired bit depth for the raw output image. See explanation on PNG color types. + Return value: LodePNG error code (0 means no error). + */ + unsigned decode(std::vector& out, unsigned& w, unsigned& h, const unsigned char* in, size_t insize, unsigned colorType = 6, unsigned bitDepth = 8); + + /* + LodePNG::decode + Exactly the same as the decode function that takes a unsigned char buffer, but instead of giving + a pointer and a size, this takes the input buffer as an std::vector. + */ + unsigned decode(std::vector& out, unsigned& w, unsigned& h, const std::vector& in, unsigned colorType = 6, unsigned bitDepth = 8); +#ifdef LODEPNG_COMPILE_DISK + /* + LodePNG::decode + Converts PNG file from disk to raw pixel data in memory. + out: Output parameter, std::vector containing the raw pixel data. Its size + will be w * h * (bytes per pixel), where bytes per pixel is 4 if the default + colorType=6 and bitDepth=8 is used. The pixels are 32-bit RGBA bit in that case. + w: Output parameter, width of the image in pixels. + h: Output parameter, height of the image in pixels. + filename: Path to PNG file on disk. + colorType: the desired color type for the raw output image. See explanation on PNG color types. + bitDepth: the desired bit depth for the raw output image. See explanation on PNG color types. + Return value: LodePNG error code (0 means no error). + */ + unsigned decode(std::vector& out, unsigned& w, unsigned& h, const std::string& filename, unsigned colorType = 6, unsigned bitDepth = 8); +#endif //LODEPNG_COMPILE_DISK +#endif //LODEPNG_COMPILE_DECODER + +#ifdef LODEPNG_COMPILE_ENCODER + + /* + LodePNG::encode + Converts 32-bit RGBA raw pixel data into a PNG image in memory. + out: Output parameter, std::vector containing the PNG image data. + in: Memory buffer with raw pixel data. The size of this buffer should be + w * h * (bytes per pixel), With the default colorType=6 and bitDepth=8, bytes + per pixel should be 4 and the data is a 32-bit RGBA pixel buffer. + w: Width of the image in pixels. + h: Height of the image in pixels. + colorType: the color type of the raw input image. See explanation on PNG color types. + bitDepth: the bit depth of the raw input image. See explanation on PNG color types. + Return value: LodePNG error code (0 means no error). + */ + unsigned encode(std::vector& out, const unsigned char* in, unsigned w, unsigned h, unsigned colorType = 6, unsigned bitDepth = 8); + + /* + LodePNG::encode + Exactly the same as the encode function that takes a unsigned char buffer, but instead of giving + a pointer and a size, this takes the input buffer as an std::vector. + */ + unsigned encode(std::vector& out, const std::vector& in, unsigned w, unsigned h, unsigned colorType = 6, unsigned bitDepth = 8); +#ifdef LODEPNG_COMPILE_DISK + /* + LodePNG::encode + Converts 32-bit RGBA raw pixel data into a PNG file on disk. + filename: Path to the file to write the PNG image to. + in: Memory buffer with raw pixel data. The size of this buffer should be + w * h * (bytes per pixel), With the default colorType=6 and bitDepth=8, bytes + per pixel should be 4 and the data is a 32-bit RGBA pixel buffer. + w: Width of the image in pixels. + h: Height of the image in pixels. + colorType: the color type of the raw input image. See explanation on PNG color types. + bitDepth: the bit depth of the raw input image. See explanation on PNG color types. + Return value: LodePNG error code (0 means no error). + */ + unsigned encode(const std::string& filename, const unsigned char* in, unsigned w, unsigned h, unsigned colorType = 6, unsigned bitDepth = 8); + + /* + LodePNG::encode + Exactly the same as the encode function that takes a unsigned char buffer, but instead of giving + a pointer and a size, this takes the input buffer as an std::vector. + */ + unsigned encode(const std::string& filename, const std::vector& in, unsigned w, unsigned h, unsigned colorType = 6, unsigned bitDepth = 8); +#endif //LODEPNG_COMPILE_DISK +#endif //LODEPNG_COMPILE_ENCODER +} //namespace LodePNG +#endif /*__cplusplus*/ +#endif /*LODEPNG_COMPILE_PNG*/ + +#ifdef LODEPNG_COMPILE_ERROR_TEXT + +/* +error_text: returns a textual description of the error code, in English. The +numerical value of the code itself is not included in this description. +*/ +const char* LodePNG_error_text(unsigned code); + +#endif /*LODEPNG_COMPILE_ERROR_TEXT*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* Inflate & Deflate Setting Structs */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +These structs contain settings for the decompression and compression of the +PNG files. Typically you won't need these directly. +*/ + +#ifdef LODEPNG_COMPILE_DECODER +typedef struct LodeZlib_DecompressSettings +{ + unsigned ignoreAdler32; /*if 1, continue and don't give an error message if the Adler32 checksum is corrupted*/ +} LodeZlib_DecompressSettings; + +extern const LodeZlib_DecompressSettings LodeZlib_defaultDecompressSettings; +void LodeZlib_DecompressSettings_init(LodeZlib_DecompressSettings* settings); +#endif /*LODEPNG_COMPILE_DECODER*/ + +#ifdef LODEPNG_COMPILE_ENCODER +/* +LodeZlib_CompressSettings +Compression settings. Tweaking these settings tweaks the balance between +speed and compression ratio. +*/ +typedef struct LodeZlib_CompressSettings /*deflate = compress*/ +{ + /*LZ77 related settings*/ + unsigned btype; /*the block type for LZ (0, 1, 2 or 3, see zlib standard)*/ + unsigned useLZ77; /*whether or not to use LZ77. Should be 1 for good compression.*/ + unsigned windowSize; /*the maximum is 32768, higher gives more compression but is slower*/ +} LodeZlib_CompressSettings; + +extern const LodeZlib_CompressSettings LodeZlib_defaultCompressSettings; +void LodeZlib_CompressSettings_init(LodeZlib_CompressSettings* settings); +#endif /*LODEPNG_COMPILE_ENCODER*/ + +#ifdef LODEPNG_COMPILE_PNG + +/* ////////////////////////////////////////////////////////////////////////// */ +/* PNG and Raw Image Information Structs */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +LodePNG_InfoColor +Info about the color type of an image. +The same LodePNG_InfoColor struct is used for both the PNG and raw image type, +even though they are two totally different things. +*/ +typedef struct LodePNG_InfoColor +{ + /*header (IHDR)*/ + unsigned colorType; /*color type, see PNG standard or documentation further in this header file*/ + unsigned bitDepth; /*bits per sample, see PNG standard or documentation further in this header file*/ + + /* + palette (PLTE) + + This is a dynamically allocated unsigned char array with the colors of the palette. The value palettesize + indicates the amount of colors in the palette. The allocated size of the buffer is 4 * palettesize bytes, + because there are 4 values per color: R, G, B and A. Even if less color channels are used, the palette + is always in RGBA format, in the order RGBARGBARGBA..... + + When encoding a PNG, to store your colors in the palette of the LodePNG_InfoRaw, first use + LodePNG_InfoColor_clearPalette, then for each color use LodePNG_InfoColor_addPalette. + In the C++ version the Encoder class also has the above functions available directly in its interface. + + The palette information from the tRNS chunk is also already included in this palette vector. + + If you encode an image with palette, don't forget that you have to set the alpha channels (A) of the palette + too, set them to 255 for an opaque palette. If you leave them at zero, the image will be encoded as + fully invisible. This both for the palette in the infoRaw and the infoPng if the png is to have a palette. + + When decoding, by default you can ignore this information, since LodePNG gives the + raw output as RGBA pixels by default and already fills the palette values in them. + */ + unsigned char* palette; /*palette in RGBARGBA... order*/ + size_t palettesize; /*palette size in number of colors (amount of bytes is 4 * palettesize)*/ + + /* + transparent color key (tRNS) + This color is 8-bit for 8-bit PNGs, 16-bit for 16-bit per channel PNGs. + For greyscale PNGs, r, g and b will all 3 be set to the same. + + When decoding, by default you can ignore this information, since LodePNG sets + pixels with this key to transparent already in the raw RGBA output. + */ + unsigned key_defined; /*is a transparent color key given? 0 = false, 1 = true*/ + unsigned key_r; /*red/greyscale component of color key*/ + unsigned key_g; /*green component of color key*/ + unsigned key_b; /*blue component of color key*/ +} LodePNG_InfoColor; + +/*init, cleanup and copy functions to use with this struct*/ +void LodePNG_InfoColor_init(LodePNG_InfoColor* info); +void LodePNG_InfoColor_cleanup(LodePNG_InfoColor* info); +unsigned LodePNG_InfoColor_copy(LodePNG_InfoColor* dest, const LodePNG_InfoColor* source); /*return value is error code (0 means no error)*/ + +/*Use these functions instead of allocating palette manually*/ +void LodePNG_InfoColor_clearPalette(LodePNG_InfoColor* info); +unsigned LodePNG_InfoColor_addPalette(LodePNG_InfoColor* info, unsigned char r, unsigned char g, unsigned char b, unsigned char a); /*add 1 color to the palette*/ + +/*additional color info*/ +unsigned LodePNG_InfoColor_getBpp(const LodePNG_InfoColor* info); /*get the total amount of bits per pixel, based on colorType and bitDepth in the struct*/ +unsigned LodePNG_InfoColor_getChannels(const LodePNG_InfoColor* info); /*get the amount of color channels used, based on colorType in the struct. If a palette is used, it counts as 1 channel.*/ +unsigned LodePNG_InfoColor_isGreyscaleType(const LodePNG_InfoColor* info); /*is it a greyscale type? (only colorType 0 or 4)*/ +unsigned LodePNG_InfoColor_isAlphaType(const LodePNG_InfoColor* info); /*has it got an alpha channel? (only colorType 2 or 6)*/ +unsigned LodePNG_InfoColor_isPaletteType(const LodePNG_InfoColor* info); /*has it got a palette? (only colorType 3)*/ +unsigned LodePNG_InfoColor_hasPaletteAlpha(const LodePNG_InfoColor* info); /*only returns true if there is a palette and there is a value in the palette with alpha < 255. Loops through the palette to check this.*/ + +/* +LodePNG_InfoColor_canHaveAlpha +Check if the given color info indicates the possibility of having non-opaque pixels in the PNG image. +Returns true if the image can have translucent or invisible pixels (it still be opaque if it doesn't use such pixels). +Returns false if the image can only have opaque pixels. +In detail, it returns true only if it's a color type with alpha, or has a palette with non-opaque values, or if "key_defined" is true. +*/ +unsigned LodePNG_InfoColor_canHaveAlpha(const LodePNG_InfoColor* info); + +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS +/* +LodePNG_Time +The information of a Time chunk in PNG. +To make the encoder add a time chunk, set time_defined to 1 and fill in +the correct values in all the time parameters. LodePNG will not fill the current +time in these values itself, all it does is copy them over into the chunk bytes. +*/ +typedef struct LodePNG_Time +{ + unsigned year; /*2 bytes used (0-65535)*/ + unsigned char month; /*1-12*/ + unsigned char day; /*1-31*/ + unsigned char hour; /*0-23*/ + unsigned char minute; /*0-59*/ + unsigned char second; /*0-60 (to allow for leap seconds)*/ +} LodePNG_Time; + +/* +LodePNG_Text +Info about text chunks in a PNG file. The arrays can contain multiple keys +and strings. The amount of keys and strings is the same. The amount of strings +ends when the pointer to the string is a null pointer. + +They keyword of text chunks gives a short description what the actual text +represents. There are a few standard standard keywords recognised +by many programs: Title, Author, Description, Copyright, Creation Time, +Software, Disclaimer, Warning, Source, Comment. It's allowed to use other keys. + +A keyword is minimum 1 character and maximum 79 characters long. It's +discouraged to use a single line length longer than 79 characters for texts. +*/ +typedef struct LodePNG_Text /*non-international text*/ +{ + /*Don't allocate these text buffers yourself. Use the init/cleanup functions + correctly and use LodePNG_Text_add and LodePNG_Text_clear.*/ + size_t num; /*the amount of texts in these char** buffers (there may be more texts in itext)*/ + char** keys; /*the keyword of a text chunk (e.g. "Comment")*/ + char** strings; /*the actual text*/ +} LodePNG_Text; + +/*init, cleanup and copy functions to use with this struct*/ +void LodePNG_Text_init(LodePNG_Text* text); +void LodePNG_Text_cleanup(LodePNG_Text* text); +unsigned LodePNG_Text_copy(LodePNG_Text* dest, const LodePNG_Text* source); /*return value is error code (0 means no error)*/ + +/*Use these functions instead of allocating the char**s manually*/ +void LodePNG_Text_clear(LodePNG_Text* text); /*use this to clear the texts again after you filled them in*/ +unsigned LodePNG_Text_add(LodePNG_Text* text, const char* key, const char* str); /*push back both texts at once*/ + +/* +LodePNG_IText +Info about international text chunks in a PNG file. The arrays can contain multiple keys +and strings. The amount of keys, lengtags, transkeys and strings is the same. +The amount of strings ends when the pointer to the string is a null pointer. + +A keyword is minimum 1 character and maximum 79 characters long. It's +discouraged to use a single line length longer than 79 characters for texts. +*/ +typedef struct LodePNG_IText /*international text*/ +{ + /*Don't allocate these text buffers yourself. Use the init/cleanup functions + correctly and use LodePNG_IText_add and LodePNG_IText_clear.*/ + size_t num; /*the amount of international texts in this PNG*/ + char** keys; /*the English keyword of the text chunk (e.g. "Comment")*/ + char** langtags; /*the language tag for this text's international language, ISO/IEC 646 string, e.g. ISO 639 language tag*/ + char** transkeys; /*keyword translated to the international language - UTF-8 string*/ + char** strings; /*the actual international text - UTF-8 string*/ +} LodePNG_IText; + +/*init, cleanup and copy functions to use with this struct*/ +void LodePNG_IText_init(LodePNG_IText* text); +void LodePNG_IText_cleanup(LodePNG_IText* text); +unsigned LodePNG_IText_copy(LodePNG_IText* dest, const LodePNG_IText* source); /*return value is error code (0 means no error)*/ + +/*Use these functions instead of allocating the char**s manually*/ +void LodePNG_IText_clear(LodePNG_IText* text); /*use this to clear the itexts again after you filled them in*/ +unsigned LodePNG_IText_add(LodePNG_IText* text, const char* key, const char* langtag, const char* transkey, const char* str); /*push back the 4 texts of 1 chunk at once*/ +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS +/* +LodePNG_UnknownChunks +Unknown chunks read from the PNG, or extra chunks the user wants to have added +in the encoded PNG. +*/ +typedef struct LodePNG_UnknownChunks +{ + /*There are 3 buffers, one for each position in the PNG where unknown chunks can appear + each buffer contains all unknown chunks for that position consecutively + The 3 buffers are the unknown chunks between certain critical chunks: + 0: IHDR-PLTE, 1: PLTE-IDAT, 2: IDAT-IEND + + Do not allocate or traverse this data yourself. Use the chunk traversing functions declared + later, such as LodePNG_chunk_next and LodePNG_append_chunk, to read/write this struct. + */ + unsigned char* data[3]; + size_t datasize[3]; /*size in bytes of the unknown chunks, given for protection*/ + +} LodePNG_UnknownChunks; + +/*init, cleanup and copy functions to use with this struct*/ +void LodePNG_UnknownChunks_init(LodePNG_UnknownChunks* chunks); +void LodePNG_UnknownChunks_cleanup(LodePNG_UnknownChunks* chunks); +unsigned LodePNG_UnknownChunks_copy(LodePNG_UnknownChunks* dest, const LodePNG_UnknownChunks* src); /*return value is error code (0 means no error)*/ +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + +/* +LodePNG_InfoPng +Information about the PNG image, except pixels and sometimes except width and height. +*/ +typedef struct LodePNG_InfoPng +{ + /*header (IHDR), palette (PLTE) and transparency (tRNS)*/ + + /* + Note: width and height are only used as information of a decoded PNG image. When encoding one, you don't have + to specify width and height in an LodePNG_Info struct, but you give them as parameters of the encode function. + The rest of the LodePNG_Info struct IS used by the encoder though! + */ + unsigned width; /*width of the image in pixels (ignored by encoder, but filled in by decoder)*/ + unsigned height; /*height of the image in pixels (ignored by encoder, but filled in by decoder)*/ + unsigned compressionMethod; /*compression method of the original file. Always 0.*/ + unsigned filterMethod; /*filter method of the original file*/ + unsigned interlaceMethod; /*interlace method of the original file*/ + LodePNG_InfoColor color; /*color type and bits, palette and transparency of the PNG file*/ + +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + + /* + suggested background color (bKGD) + This color is 8-bit for 8-bit PNGs, 16-bit for 16-bit PNGs + + For greyscale PNGs, r, g and b will all 3 be set to the same. When encoding + the encoder writes the red one. For palette PNGs: When decoding, the RGB value + will be stored, not a palette index. But when encoding, specify the index of + the palette in background_r, the other two are then ignored. + + The decoder does not use this background color to edit the color of pixels. + */ + unsigned background_defined; /*is a suggested background color given?*/ + unsigned background_r; /*red component of suggested background color*/ + unsigned background_g; /*green component of suggested background color*/ + unsigned background_b; /*blue component of suggested background color*/ + + /*non-international text chunks (tEXt and zTXt)*/ + LodePNG_Text text; + + /*international text chunks (iTXt)*/ + LodePNG_IText itext; + + /*time chunk (tIME)*/ + unsigned char time_defined; /*if 0, no tIME chunk was or will be generated in the PNG image*/ + LodePNG_Time time; + + /*phys chunk (pHYs)*/ + unsigned phys_defined; /*if 0, there is no pHYs chunk and the values below are undefined, if 1 else there is one*/ + unsigned phys_x; /*pixels per unit in x direction*/ + unsigned phys_y; /*pixels per unit in y direction*/ + unsigned char phys_unit; /*may be 0 (unknown unit) or 1 (metre)*/ + +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + /*unknown chunks*/ + LodePNG_UnknownChunks unknown_chunks; +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ + +} LodePNG_InfoPng; + +/*init, cleanup and copy functions to use with this struct*/ +void LodePNG_InfoPng_init(LodePNG_InfoPng* info); +void LodePNG_InfoPng_cleanup(LodePNG_InfoPng* info); +unsigned LodePNG_InfoPng_copy(LodePNG_InfoPng* dest, const LodePNG_InfoPng* source); /*return value is error code (0 means no error)*/ + +/* +LodePNG_InfoRaw +Contains user-chosen information about the raw image data, which is independent of the PNG image +With raw images, I mean the image data in the form of the simple raw buffer to which the +compressed PNG data is decoded, or from which a PNG image can be encoded. +*/ +typedef struct LodePNG_InfoRaw +{ + LodePNG_InfoColor color; /*color info of the raw image, note that the same struct as for PNG data is used.*/ +} LodePNG_InfoRaw; + +/*init, cleanup and copy functions to use with this struct*/ +void LodePNG_InfoRaw_init(LodePNG_InfoRaw* info); +void LodePNG_InfoRaw_cleanup(LodePNG_InfoRaw* info); +unsigned LodePNG_InfoRaw_copy(LodePNG_InfoRaw* dest, const LodePNG_InfoRaw* source); /*return value is error code (0 means no error)*/ + +/* +LodePNG_convert +Converts raw buffer from one color type to another color type, based on +LodePNG_InfoColor structs to describe the input and output color type. +See the reference manual at the end of this header file to see which color conversions are supported. +return value = LodePNG error code (0 if all went ok, an error if the conversion isn't supported) +The out buffer must have size (w * h * bpp + 7) / 8, where bpp is the bits per pixel +of the output color type (LodePNG_InfoColor_getBpp) +*/ +unsigned LodePNG_convert(unsigned char* out, const unsigned char* in, LodePNG_InfoColor* infoOut, LodePNG_InfoColor* infoIn, unsigned w, unsigned h); + +#ifdef LODEPNG_COMPILE_DECODER + +/* ////////////////////////////////////////////////////////////////////////// */ +/* LodePNG Decoder */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +Settings for the decoder. This contains settings for the PNG and the Zlib +decoder, but not the Info settings from the Info structs. +*/ +typedef struct LodePNG_DecodeSettings +{ + LodeZlib_DecompressSettings zlibsettings; /*in here is the setting to ignore Adler32 checksums*/ + + unsigned ignoreCrc; /*ignore CRC checksums*/ + unsigned color_convert; /*whether to convert the PNG to the color type you want. Default: yes*/ + +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + unsigned readTextChunks; /*if false but rememberUnknownChunks is true, they're stored in the unknown chunks*/ +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ + +#ifdef LODEPNG_COMPILE_UNKNOWN_CHUNKS + unsigned rememberUnknownChunks; /*store all bytes from unknown chunks in the InfoPng (off by default, useful for a png editor)*/ +#endif /*LODEPNG_COMPILE_UNKNOWN_CHUNKS*/ +} LodePNG_DecodeSettings; + +void LodePNG_DecodeSettings_init(LodePNG_DecodeSettings* settings); + +/* +The LodePNG_Decoder struct has most input and output parameters the decoder uses, +such as the settings, the info of the PNG and the raw data, and the error. Only +the pixel buffer is not contained in this struct. +*/ +typedef struct LodePNG_Decoder +{ + LodePNG_DecodeSettings settings; /*the decoding settings*/ + LodePNG_InfoRaw infoRaw; /*specifies the format in which you would like to get the raw pixel buffer*/ + LodePNG_InfoPng infoPng; /*info of the PNG image obtained after decoding*/ + unsigned error; +} LodePNG_Decoder; + +/*init, cleanup and copy functions to use with this struct*/ +void LodePNG_Decoder_init(LodePNG_Decoder* decoder); +void LodePNG_Decoder_cleanup(LodePNG_Decoder* decoder); +void LodePNG_Decoder_copy(LodePNG_Decoder* dest, const LodePNG_Decoder* source); + +/* +LodePNG_Decoder_decode +Decode based on a LodePNG_Decoder. +This function allocates the out buffer and stores the size in *outsize. This buffer +needs to be freed after usage. +Other information about the PNG file, such as the size, colorType and extra chunks +are stored in the infoPng field of the LodePNG_Decoder. +*/ +void LodePNG_Decoder_decode(LodePNG_Decoder* decoder, unsigned char** out, size_t* outsize, const unsigned char* in, size_t insize); + +/* +LodePNG_Decoder_inspect +Read the PNG header, but not the actual data. This returns only the information +that is in the header chunk of the PNG, such as width, height and color type. The +information is placed in the infoPng field of the LodePNG_Decoder. +*/ +void LodePNG_Decoder_inspect(LodePNG_Decoder* decoder, const unsigned char* in, size_t insize); /*read the png header*/ + +#endif /*LODEPNG_COMPILE_DECODER*/ + +#ifdef LODEPNG_COMPILE_ENCODER + +/* ////////////////////////////////////////////////////////////////////////// */ +/* LodePNG Encoder */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +LodePNG_EncodeSettings +Extra settings used by the encoder. +*/ +typedef struct LodePNG_EncodeSettings +{ + LodeZlib_CompressSettings zlibsettings; /*settings for the zlib encoder, such as window size, ...*/ + + unsigned autoLeaveOutAlphaChannel; /*automatically use color type without alpha instead of given one, if given image is opaque*/ + unsigned force_palette; /*force creating a PLTE chunk if colortype is 2 or 6 (= a suggested palette). If colortype is 3, PLTE is _always_ created.*/ +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + unsigned add_id; /*add LodePNG version as text chunk*/ + unsigned text_compression; /*encode text chunks as zTXt chunks instead of tEXt chunks, and use compression in iTXt chunks*/ +#endif /*LODEPNG_COMPILE_ANCILLARY_CHUNKS*/ +} LodePNG_EncodeSettings; + +void LodePNG_EncodeSettings_init(LodePNG_EncodeSettings* settings); + +/* +LodePNG_Encoder +This struct has most input and output parameters the encoder uses, +such as the settings, the info of the PNG and the raw data, and the error. Only +the pixel buffer is not contained in this struct. +*/ +typedef struct LodePNG_Encoder +{ + LodePNG_EncodeSettings settings; /*compression settings of the encoder*/ + LodePNG_InfoPng infoPng; /*the info specified by the user is not changed by the encoder. The encoder will try to generate a PNG close to the given info.*/ + LodePNG_InfoRaw infoRaw; /*put the properties of the input raw image in here*/ + unsigned error; /*error value filled in if error happened, or 0 if all went ok*/ +} LodePNG_Encoder; + +/*init, cleanup and copy functions to use with this struct*/ +void LodePNG_Encoder_init(LodePNG_Encoder* encoder); +void LodePNG_Encoder_cleanup(LodePNG_Encoder* encoder); +void LodePNG_Encoder_copy(LodePNG_Encoder* dest, const LodePNG_Encoder* source); + +/*This function allocates the out buffer with standard malloc and stores the size in *outsize.*/ +void LodePNG_Encoder_encode(LodePNG_Encoder* encoder, unsigned char** out, size_t* outsize, const unsigned char* image, unsigned w, unsigned h); + +#endif /*LODEPNG_COMPILE_ENCODER*/ + +/* ////////////////////////////////////////////////////////////////////////// */ +/* Chunk Traversing Utilities */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +LodePNG_chunk functions: +These functions need as input a large enough amount of allocated memory. +These functions can be used on raw PNG data, but they are exposed in the API +because they are needed if you want to traverse the unknown chunks stored +in the LodePNG_UnknownChunks struct, or add new ones to it. +*/ + +unsigned LodePNG_chunk_length(const unsigned char* chunk); /*get the length of the data of the chunk. Total chunk length has 12 bytes more.*/ + +void LodePNG_chunk_type(char type[5], const unsigned char* chunk); /*puts the 4-byte type in null terminated string*/ +unsigned char LodePNG_chunk_type_equals(const unsigned char* chunk, const char* type); /*check if the type is the given type*/ + +/* +These functions get properties of PNG chunks gotten from capitalization of chunk +type name, as defined by the PNG standard. +*/ +unsigned char LodePNG_chunk_critical(const unsigned char* chunk); /*0: ancillary chunk, 1: it's one of the critical chunk types*/ +unsigned char LodePNG_chunk_private(const unsigned char* chunk); /*0: public, 1: private*/ +unsigned char LodePNG_chunk_safetocopy(const unsigned char* chunk); /*0: the chunk is unsafe to copy, 1: the chunk is safe to copy*/ + +unsigned char* LodePNG_chunk_data(unsigned char* chunk); /*get pointer to the data of the chunk*/ +const unsigned char* LodePNG_chunk_data_const(const unsigned char* chunk); /*get pointer to the data of the chunk*/ + +unsigned LodePNG_chunk_check_crc(const unsigned char* chunk); /*returns 0 if the crc is correct, 1 if it's incorrect*/ +void LodePNG_chunk_generate_crc(unsigned char* chunk); /*generates the correct CRC from the data and puts it in the last 4 bytes of the chunk*/ + +/*iterate to next chunks.*/ +unsigned char* LodePNG_chunk_next(unsigned char* chunk); +const unsigned char* LodePNG_chunk_next_const(const unsigned char* chunk); + +/* +LodePNG_append_chunk +Appends chunk to the data in out. The given chunk should already have its chunk header. +The out variable and outlength are updated to reflect the new reallocated buffer. +Returns error code (0 if it went ok) +*/ +unsigned LodePNG_append_chunk(unsigned char** out, size_t* outlength, const unsigned char* chunk); + +/* +LodePNG_create_chunk +Appends new chunk to out. The chunk to append is given by giving its length, type +and data separately. The type is a 4-letter string. +The out variable and outlength are updated to reflect the new reallocated buffer. +Returne error code (0 if it went ok) +*/ +unsigned LodePNG_create_chunk(unsigned char** out, size_t* outlength, unsigned length, const char* type, const unsigned char* data); + +#endif /*LODEPNG_COMPILE_PNG*/ + +#ifdef LODEPNG_COMPILE_ZLIB +/* ////////////////////////////////////////////////////////////////////////// */ +/* Zlib encoder and decoder */ +/* ////////////////////////////////////////////////////////////////////////// */ + +/* +This is "LodeZlib". A C++ wrapper is available further on. + +LodeZlib can be used to zlib compress and decompress a buffer. It cannot be +used to create gzip files however, and it only supports the part of zlib +that is required for PNG, it does not support dictionaries. +*/ + +#ifdef LODEPNG_COMPILE_DECODER +/*This function reallocates the out buffer and appends the data. +Either, *out must be NULL and *outsize must be 0, or, *out must be a valid buffer and *outsize its size in bytes.*/ +unsigned LodeZlib_decompress(unsigned char** out, size_t* outsize, const unsigned char* in, size_t insize, const LodeZlib_DecompressSettings* settings); +#endif /*LODEPNG_COMPILE_DECODER*/ + +#ifdef LODEPNG_COMPILE_ENCODER +/*This function reallocates the out buffer and appends the data. +Either, *out must be NULL and *outsize must be 0, or, *out must be a valid buffer and *outsize its size in bytes.*/ +unsigned LodeZlib_compress(unsigned char** out, size_t* outsize, const unsigned char* in, size_t insize, const LodeZlib_CompressSettings* settings); +#endif /*LODEPNG_COMPILE_ENCODER*/ +#endif /*LODEPNG_COMPILE_ZLIB*/ + +#ifdef LODEPNG_COMPILE_DISK +/* +LodePNG_loadFile +Load a file from disk into buffer. The function allocates the out buffer, and +after usage you are responsible for freeing it. +out: output parameter, contains pointer to loaded buffer. +outsize: output parameter, size of the allocated out buffer +filename: the path to the file to load +return value: error code (0 means ok) +*/ +unsigned LodePNG_loadFile(unsigned char** out, size_t* outsize, const char* filename); + +/* +LodePNG_saveFile +Save a file from buffer to disk. Warning, this function overwrites the file without warning! +buffer: the buffer to write +buffersize: size of the buffer to write +filename: the path to the file to save to +return value: error code (0 means ok) +*/ +unsigned LodePNG_saveFile(const unsigned char* buffer, size_t buffersize, const char* filename); +#endif /*LODEPNG_COMPILE_DISK*/ + +#ifdef __cplusplus + +/* ////////////////////////////////////////////////////////////////////////// */ +/* LodePNG C++ wrapper */ +/* ////////////////////////////////////////////////////////////////////////// */ + +//The LodePNG C++ wrapper uses classes with handy constructors and destructors +//instead of manual init and cleanup functions, and uses std::vectors instead of +//manually allocated memory buffers. + +#ifdef LODEPNG_COMPILE_ZLIB +//The C++ wrapper for LodeZlib +namespace LodeZlib +{ +#ifdef LODEPNG_COMPILE_DECODER + + //Zlib-decompress an unsigned char buffer + unsigned decompress(std::vector& out, const unsigned char* in, size_t insize, const LodeZlib_DecompressSettings& settings = LodeZlib_defaultDecompressSettings); + + //Zlib-decompress an std::vector + unsigned decompress(std::vector& out, const std::vector& in, const LodeZlib_DecompressSettings& settings = LodeZlib_defaultDecompressSettings); + +#endif //LODEPNG_COMPILE_DECODER +#ifdef LODEPNG_COMPILE_ENCODER + + //Zlib-compress an unsigned char buffer + unsigned compress(std::vector& out, const unsigned char* in, size_t insize, const LodeZlib_CompressSettings& settings = LodeZlib_defaultCompressSettings); + + //Zlib-compress an std::vector + unsigned compress(std::vector& out, const std::vector& in, const LodeZlib_CompressSettings& settings = LodeZlib_defaultCompressSettings); + +#endif //LODEPNG_COMPILE_ENCODER +} //namespace LodeZlib +#endif //LODEPNG_COMPILE_ZLIB + +#ifdef LODEPNG_COMPILE_PNG +namespace LodePNG +{ + +#ifdef LODEPNG_COMPILE_DECODER + /* + LodePNG::Decoder + Class to decode a PNG image. Before decoding, settings can be set and + after decoding, extra information about the PNG can be retrieved. + Extends from the C-struct LodePNG_Decoder to add constructors and destructors + to initialize/cleanup it automatically. Beware, no virtual destructor is used. + */ + class Decoder : public LodePNG_Decoder + { + public: + + Decoder(); + ~Decoder(); + void operator=(const LodePNG_Decoder& other); + + //decode PNG buffer to raw out buffer. Width and height can be retrieved with getWidth() and getHeight() and error should be checked with hasError() and getError() + void decode(std::vector& out, const unsigned char* in, size_t insize); + + //decode PNG buffer to raw out buffer. Width and height can be retrieved with getWidth() and getHeight() and error should be checked with hasError() and getError() + void decode(std::vector& out, const std::vector& in); + + //inspect functions: get only the info from the PNG header. The info can then be retrieved with the functions of this class. + void inspect(const unsigned char* in, size_t insize); + + //inspect functions: get only the info from the PNG header. The info can then be retrieved with the functions of this class. + void inspect(const std::vector& in); + + //error checking after decoding + bool hasError() const; + unsigned getError() const; + + //convenient access to some InfoPng parameters after decoding + unsigned getWidth() const; //width of image in pixels + unsigned getHeight() const; //height of image in pixels + unsigned getBpp(); //bits per pixel + unsigned getChannels(); //amount of channels + unsigned isGreyscaleType(); //is it a greyscale type? (colorType 0 or 4) + unsigned isAlphaType(); //has it an alpha channel? (colorType 2 or 6) + + //getters and setters for the decoding settings + const LodePNG_DecodeSettings& getSettings() const; + LodePNG_DecodeSettings& getSettings(); + void setSettings(const LodePNG_DecodeSettings& info); + + //getters and setters for the PNG image info, after decoding this describes information of the PNG image + const LodePNG_InfoPng& getInfoPng() const; + LodePNG_InfoPng& getInfoPng(); + void setInfoPng(const LodePNG_InfoPng& info); + void swapInfoPng(LodePNG_InfoPng& info); //faster than copying with setInfoPng + + //getters and setters for the raw image info, this determines in what format you get the pixel buffer from the decoder + const LodePNG_InfoRaw& getInfoRaw() const; + LodePNG_InfoRaw& getInfoRaw(); + void setInfoRaw(const LodePNG_InfoRaw& info); + }; + +#endif //LODEPNG_COMPILE_DECODER + +#ifdef LODEPNG_COMPILE_ENCODER + /* + LodePNG::Encoder + Class to encode a PNG image. Before encoding, settings can be set. + Extends from the C-struct LodePNG_Enoder to add constructors and destructors + to initialize/cleanup it automatically. Beware, no virtual destructor is used. + */ + class Encoder : public LodePNG_Encoder + { + public: + + Encoder(); + ~Encoder(); + void operator=(const LodePNG_Encoder& other); + + //encoding image to PNG buffer + void encode(std::vector& out, const unsigned char* image, unsigned w, unsigned h); + + //encoding image to PNG buffer + void encode(std::vector& out, const std::vector& image, unsigned w, unsigned h); + + //error checking after decoding + bool hasError() const; + unsigned getError() const; + + //convenient direct access to some parameters of the InfoPng + void clearPalette(); + void addPalette(unsigned char r, unsigned char g, unsigned char b, unsigned char a); //add 1 color to the palette +#ifdef LODEPNG_COMPILE_ANCILLARY_CHUNKS + void clearText(); + void addText(const std::string& key, const std::string& str); //push back both texts at once + void clearIText(); + void addIText(const std::string& key, const std::string& langtag, const std::string& transkey, const std::string& str); +#endif //LODEPNG_COMPILE_ANCILLARY_CHUNKS + + //getters and setters for the encoding settings + const LodePNG_EncodeSettings& getSettings() const; + LodePNG_EncodeSettings& getSettings(); + void setSettings(const LodePNG_EncodeSettings& info); + + //getters and setters for the PNG image info, this describes what color type and other settings the resulting PNG should have + const LodePNG_InfoPng& getInfoPng() const; + LodePNG_InfoPng& getInfoPng(); + void setInfoPng(const LodePNG_InfoPng& info); + void swapInfoPng(LodePNG_InfoPng& info); //faster than copying with setInfoPng + + //getters and setters for the raw image info, this describes how the encoder should interpret the input pixel buffer + const LodePNG_InfoRaw& getInfoRaw() const; + LodePNG_InfoRaw& getInfoRaw(); + void setInfoRaw(const LodePNG_InfoRaw& info); + }; + +#endif //LODEPNG_COMPILE_ENCODER + +#ifdef LODEPNG_COMPILE_DISK + /* + loadFile + Load a file from disk into an std::vector. If the vector is empty, then either + the file doesn't exist or is an empty file. + */ + void loadFile(std::vector& buffer, const std::string& filename); + + /* + saveFile + Save the binary data in an std::vector to a file on disk. The file is overwritten + without warning. + */ + void saveFile(const std::vector& buffer, const std::string& filename); +#endif //LODEPNG_COMPILE_DISK + +} //namespace LodePNG + +#endif //LODEPNG_COMPILE_PNG + +#endif /*end of __cplusplus wrapper*/ + +/* +TODO: +[ ] test if there are no memory leaks or security exploits - done a lot but needs to be checked often +[ ] LZ77 encoder more like the one described in zlib - to make sure it's patentfree +[ ] converting color to 16-bit per channel types +[ ] read all public PNG chunk types (but never let the color profile and gamma ones ever touch RGB values, that is very annoying for textures as well as images in a browser) +[ ] make sure encoder generates no chunks with size > (2^31)-1 +[ ] partial decoding (stream processing) +[ ] let the "isFullyOpaque" function check color keys and transparent palettes too +[ ] better name for the variables "codes", "codesD", "codelengthcodes", "clcl" and "lldl" +[ ] check compatibility with vareous compilers - done but needs to be redone for every newer version +[ ] don't stop decoding on errors like 69, 57, 58 (make warnings that the decoder stores in the error at the very end? and make some errors just let it stop with this one chunk but still do the next ones) +[ ] make option to choose if the raw image with non multiple of 8 bits per scanline should have padding bits or not, if people like storing raw images that way +*/ + +#endif + +/* +LodePNG Documentation +--------------------- + +This documentations contains background information and examples. For the function +and class documentation, see the comments in the declarations above. + +0. table of contents +-------------------- + + 1. about + 1.1. supported features + 1.2. features not supported + 2. C and C++ version + 3. security + 4. decoding + 5. encoding + 6. color conversions + 6.1. PNG color types + 6.2. Default Behaviour of LodePNG + 6.3. Color Conversions + 6.4. More Notes + 7. error values + 8. chunks and PNG editing + 9. compiler support + 10. examples + 10.1. decoder C++ example + 10.2. encoder C++ example + 10.3. decoder C example + 11. changes + 12. contact information + + +1. about +-------- + +PNG is a file format to store raster images losslessly with good compression, +supporting different color types. It can be implemented in a patent-free way. + +LodePNG is a PNG codec according to the Portable Network Graphics (PNG) +Specification (Second Edition) - W3C Recommendation 10 November 2003. + +The specifications used are: + +*) Portable Network Graphics (PNG) Specification (Second Edition): + http://www.w3.org/TR/2003/REC-PNG-20031110 +*) RFC 1950 ZLIB Compressed Data Format version 3.3: + http://www.gzip.org/zlib/rfc-zlib.html +*) RFC 1951 DEFLATE Compressed Data Format Specification ver 1.3: + http://www.gzip.org/zlib/rfc-deflate.html + +The most recent version of LodePNG can currently be found at +http://members.gamedev.net/lode/projects/LodePNG/ + +LodePNG works both in C (ISO C90) and C++, with a C++ wrapper that adds +extra functionality. + +LodePNG exists out of two files: +-lodepng.h: the header file for both C and C++ +-lodepng.c(pp): give it the name lodepng.c or lodepng.cpp (or .cc) depending on your usage + +If you want to start using LodePNG right away without reading this doc, get the +files lodepng_examples.c or lodepng_examples.cpp to see how to use it in code, +or check the (smaller) examples in chapter 13 here. + +LodePNG is simple but only supports the basic requirements. To achieve +simplicity, the following design choices were made: There are no dependencies +on any external library. To decode PNGs, there's a Decoder struct or class that +can convert any PNG file data into an RGBA image buffer with a single function +call. To encode PNGs, there's an Encoder struct or class that can convert image +data into PNG file data with a single function call. To read and write files, +there are simple functions to convert the files to/from buffers in memory. + +This all makes LodePNG suitable for loading textures in games, demoscene +productions, saving a screenshot, images in programs that require them for simple +usage, ... It's less suitable for full fledged image editors, loading PNGs +over network (it requires all the image data to be available before decoding can +begin), life-critical systems, ... +LodePNG has a standards conformant decoder and encoder, and supports the ability +to make a somewhat conformant editor. + +1.1. supported features +----------------------- + +The following features are supported by the decoder: + +*) decoding of PNGs with any color type, bit depth and interlace mode, to a 24- or 32-bit color raw image, or the same color type as the PNG +*) encoding of PNGs, from any raw image to 24- or 32-bit color, or the same color type as the raw image +*) Adam7 interlace and deinterlace for any color type +*) loading the image from harddisk or decoding it from a buffer from other sources than harddisk +*) support for alpha channels, including RGBA color model, translucent palettes and color keying +*) zlib decompression (inflate) +*) zlib compression (deflate) +*) CRC32 and ADLER32 checksums +*) handling of unknown chunks, allowing making a PNG editor that stores custom and unknown chunks. +*) the following chunks are supported (generated/interpreted) by both encoder and decoder: + IHDR: header information + PLTE: color palette + IDAT: pixel data + IEND: the final chunk + tRNS: transparency for palettized images + tEXt: textual information + zTXt: compressed textual information + iTXt: international textual information + bKGD: suggested background color + pHYs: physical dimensions + tIME: modification time + +1.2. features not supported +--------------------------- + +The following features are _not_ supported: + +*) some features needed to make a conformant PNG-Editor might be still missing. +*) partial loading/stream processing. All data must be available and is processed in one call. +*) The following public chunks are not supported but treated as unknown chunks by LodePNG + cHRM, gAMA, iCCP, sRGB, sBIT, hIST, sPLT + + +2. C and C++ version +-------------------- + +The C version uses buffers allocated with alloc that you need to free() +yourself. On top of that, you need to use init and cleanup functions for each +struct whenever using a struct from the C version to avoid exploits and memory leaks. + +The C++ version has constructors and destructors that take care of these things, +and uses std::vectors in the interface for storing data. + +Both the C and the C++ version are contained in this file! The C++ code depends on +the C code, the C code works on its own. + +These files work without modification for both C and C++ compilers because all the +additional C++ code is in "#ifdef __cplusplus" blocks that make C-compilers ignore +it, and the C code is made to compile both with strict ISO C90 and C++. + +To use the C++ version, you need to rename the source file to lodepng.cpp (instead +of lodepng.c), and compile it with a C++ compiler. + +To use the C version, you need to rename the source file to lodepng.c (instead +of lodepng.cpp), and compile it with a C compiler. + + +3. Security +----------- + +As with most software, even if carefully designed, it's always possible that +LodePNG may contain possible exploits. + +If you discover a possible exploit, please let me know, and it will be fixed. + +When using LodePNG, care has to be taken with the C version of LodePNG, as well as the C-style +structs when working with C++. The following conventions are used for all C-style structs: + +-if a struct has a corresponding init function, always call the init function when making a new one, to avoid exploits +-if a struct has a corresponding cleanup function, call it before the struct disappears to avoid memory leaks +-if a struct has a corresponding copy function, use the copy function instead of "=". The destination must also be inited already! + +4. Decoding +----------- + +Decoding converts a PNG compressed image to a raw pixel buffer. + +Most documentation on using the decoder is at its declarations in the header +above. For C, simple decoding can be done with functions such as LodePNG_decode32, +and more advanced decoding can be done with the struct LodePNG_Decoder and its +functions. For C++, simple decoding can be done with the LodePNG::decode functions +and advanced decoding with the LodePNG::Decoder class. + +The Decoder contains 3 components: +*) LodePNG_InfoPng: it stores information about the PNG (the input) in an LodePNG_InfoPng struct, don't modify this one yourself +*) Settings: you can specify a few other settings for the decoder to use +*) LodePNG_InfoRaw: here you can say what type of raw image (the output) you want to get + +Some of the parameters described below may be inside the sub-struct "LodePNG_InfoColor color". +In the C and C++ version, when using Info structs outside of the decoder or encoder, you need to use their +init and cleanup functions, but normally you use the ones in the decoder that are already handled +in the init and cleanup functions of the decoder itself. + +=LodePNG_InfoPng= + +This contains information such as the original color type of the PNG image, text +comments, suggested background color, etc... More details about the LodePNG_InfoPng struct +are at its declaration documentation. + +Because the dimensions of the image are important, there are shortcuts to get them in the +C++ version: use decoder.getWidth() and decoder.getHeight(). +In the C version, use decoder.infoPng.width and decoder.infoPng.height. + +=LodePNG_InfoRaw= + +In the LodePNG_InfoRaw struct of the Decoder, you can specify which color type you want +the resulting raw image to be. If this is different from the colorType of the +PNG, then the decoder will automatically convert the result to your LodePNG_InfoRaw +settings. Not all combinations of color conversions are supported though, see +a different section for information about the color modes and supported conversions. + +Palette of LodePNG_InfoRaw isn't used by the Decoder, when converting from palette color +to palette color, the values of the pixels are left untouched so that the colors +will change if the palette is different. Color key of LodePNG_InfoRaw is not used by the +Decoder. If setting color_convert is false then LodePNG_InfoRaw is completely ignored, +but it will be modified to match the color type of the PNG so will be overwritten. + +By default, 32-bit color is used for the result. + +=Settings= + +The Settings can be used to ignore the errors created by invalid CRC and Adler32 +chunks, and to disable the decoding of tEXt chunks. + +There's also a setting color_convert, true by default. If false, no conversion +is done, the resulting data will be as it was in the PNG (after decompression) +and you'll have to puzzle the colors of the pixels together yourself using the +color type information in the LodePNG_InfoPng. + + +5. Encoding +----------- + +Encoding converts a raw pixel buffer to a PNG compressed image. + +Most documentation on using the encoder is at its declarations in the header +above. For C, simple encoding can be done with functions such as LodePNG_encode32, +and more advanced decoding can be done with the struct LodePNG_Encoder and its +functions. For C++, simple encoding can be done with the LodePNG::encode functions +and advanced decoding with the LodePNG::Encoder class. + +Like the decoder, the encoder can also give errors. However it gives less errors +since the encoder input is trusted, the decoder input (a PNG image that could +be forged by anyone) is not trusted. + +Like the Decoder, the Encoder has 3 components: +*) LodePNG_InfoRaw: here you say what color type of the raw image (the input) has +*) Settings: you can specify a few settings for the encoder to use +*) LodePNG_InfoPng: the same LodePNG_InfoPng struct as created by the Decoder. For the encoder, +with this you specify how you want the PNG (the output) to be. + +Some of the parameters described below may be inside the sub-struct "LodePNG_InfoColor color". +In the C and C++ version, when using Info structs outside of the decoder or encoder, you need to use their +init and cleanup functions, but normally you use the ones in the encoder that are already handled +in the init and cleanup functions of the decoder itself. + +=LodePNG_InfoPng= + +The Decoder class stores information about the PNG image in an LodePNG_InfoPng object. With +the Encoder you can do the opposite: you give it an LodePNG_InfoPng object, and it'll try +to match the LodePNG_InfoPng you give as close as possible in the PNG it encodes. For +example in the LodePNG_InfoPng you can specify the color type you want to use, possible +tEXt chunks you want the PNG to contain, etc... For an explanation of all the +values in LodePNG_InfoPng see a further section. Not all PNG color types are supported +by the Encoder. + +The encoder will not always exactly match the LodePNG_InfoPng struct you give, +it tries as close as possible. Some things are ignored by the encoder. The width +and height of LodePNG_InfoPng are ignored as well, because instead the width and +height of the raw image you give in the input are used. In fact the encoder +currently uses only the following settings from it: +-colorType and bitDepth: the ones it supports +-text chunks, that you can add to the LodePNG_InfoPng with "addText" +-the color key, if applicable for the given color type +-the palette, if you encode to a PNG with colorType 3 +-the background color: it'll add a bKGD chunk to the PNG if one is given +-the interlaceMethod: None (0) or Adam7 (1) + +When encoding to a PNG with colorType 3, the encoder will generate a PLTE chunk. +If the palette contains any colors for which the alpha channel is not 255 (so +there are translucent colors in the palette), it'll add a tRNS chunk. + +=LodePNG_InfoRaw= + +You specify the color type of the raw image that you give to the input here, +including a possible transparent color key and palette you happen to be using in +your raw image data. + +By default, 32-bit color is assumed, meaning your input has to be in RGBA +format with 4 bytes (unsigned chars) per pixel. + +=Settings= + +The following settings are supported (some are in sub-structs): +*) autoLeaveOutAlphaChannel: when this option is enabled, when you specify a PNG +color type with alpha channel (not to be confused with the color type of the raw +image you specify!!), but the encoder detects that all pixels of the given image +are opaque, then it'll automatically use the corresponding type without alpha +channel, resulting in a smaller PNG image. +*) btype: the block type for LZ77. 0 = uncompressed, 1 = fixed huffman tree, 2 = dynamic huffman tree (best compression) +*) useLZ77: whether or not to use LZ77 for compressed block types +*) windowSize: the window size used by the LZ77 encoder (1 - 32768) +*) force_palette: if colorType is 2 or 6, you can make the encoder write a PLTE + chunk if force_palette is true. This can used as suggested palette to convert + to by viewers that don't support more than 256 colors (if those still exist) +*) add_id: add text chunk "Encoder: LodePNG " to the image. +*) text_compression: default 0. If 1, it'll store texts as zTXt instead of tEXt chunks. + zTXt chunks use zlib compression on the text. This gives a smaller result on + large texts but a larger result on small texts (such as a single program name). + It's all tEXt or all zTXt though, there's no separate setting per text yet. + + +6. color conversions +-------------------- + +In LodePNG, the color mode (bits, channels and palette) used in the PNG image, +and the color mode used in the raw data, are separate and independently +configurable. Therefore, LodePNG needs to do conversions from one color mode to +another. Not all possible conversions are supported (e.g. converting to a color +model with palette isn't supported). This section will explain which conversions +are supported and how to configure this. This explains for example when LodePNG +uses the settings in LodePNG_InfoPng, LodePNG_InfoRaw and Settings. + +6.1. PNG color types +-------------------- + +A PNG image can have many color types, ranging from 1-bit color to 64-bit color, +as well as palettized color modes. After the zlib decompression and unfiltering +in the PNG image is done, the raw pixel data will have that color type and thus +a certain amount of bits per pixel. If you want the output raw image after +decoding to have another color type, a conversion is done by LodePNG. + +The PNG specification mentions the following color types: + +0: greyscale, bit depths 1, 2, 4, 8, 16 +2: RGB, bit depths 8 and 16 +3: palette, bit depths 1, 2, 4 and 8 +4: greyscale with alpha, bit depths 8 and 16 +6: RGBA, bit depths 8 and 16 + +Bit depth is the amount of bits per color channel. + +6.2. Default Behaviour of LodePNG +--------------------------------- + +By default, the Decoder will convert the data from the PNG to 32-bit RGBA color, +no matter what color type the PNG has, so that the result can be used directly +as a texture in OpenGL etc... without worries about what color type the original +image has. + +The Encoder assumes by default that the raw input you give it is a 32-bit RGBA +buffer and will store the PNG as either 32 bit or 24 bit depending on whether +or not any translucent pixels were detected in it. + +To get the default behaviour, don't change the values of LodePNG_InfoRaw and LodePNG_InfoPng of +the encoder, and don't change the values of LodePNG_InfoRaw of the decoder. + +6.3. Color Conversions +---------------------- + +As explained in the sections about the Encoder and Decoder, you can specify +color types and bit depths in LodePNG_InfoPng and LodePNG_InfoRaw, to change the default behaviour +explained above. (for the Decoder you can only specify the LodePNG_InfoRaw, because the +LodePNG_InfoPng contains what the PNG file has). + +To avoid some confusion: +-the Decoder converts from PNG to raw image +-the Encoder converts from raw image to PNG +-the color type and bit depth in LodePNG_InfoRaw, are those of the raw image +-the color type and bit depth in LodePNG_InfoPng, are those of the PNG +-if the color type of the LodePNG_InfoRaw and PNG image aren't the same, a conversion +between the color types is done if the color types are supported. If it is not +supported, an error is returned. + +Supported color conversions: +-It's possible to load PNGs from any colortype and to save PNGs of any colorType. +-Both encoder and decoder use the same converter. So both encoder and decoder +suport the same color types at the input and the output. So the decoder supports +any type of PNG image and can convert it to certain types of raw image, while the +encoder supports any type of raw data but only certain color types for the output PNG. +-The converter can convert from _any_ input color type, to 24-bit RGB or 32-bit RGBA +-The converter can convert from greyscale input color type, to 8-bit greyscale or greyscale with alpha +-If both color types are the same, conversion from anything to anything is possible +-Color types that are invalid according to the PNG specification are not allowed +-When converting from a type with alpha channel to one without, the alpha channel information is discarded +-When converting from a type without alpha channel to one with, the result will be opaque except pixels that have the same color as the color key of the input if one was given +-When converting from 16-bit bitDepth to 8-bit bitDepth, the 16-bit precision information is lost, only the most significant byte is kept +-Converting from color to greyscale or to palette is not supported on purpose: there are multiple possible algorithms to do this color reduction, LodePNG does not want to pick one and leaves this choice to the user instead, because it's beyond the scope of PNG encoding. +-Converting from/to a palette type, only keeps the indices, it ignores the colors defined in the palette + +No conversion needed...: +-If the color type of the PNG image and raw image are the same, then no +conversion is done, and all color types are supported. +-In the encoder, you can make it save a PNG with any color by giving the +LodePNG_InfoRaw and LodePNG_InfoPng the same color type. +-In the decoder, you can make it store the pixel data in the same color type +as the PNG has, by setting the color_convert setting to false. Settings in +infoRaw are then ignored. + +The function LodePNG_convert does this, which is available in the interface but +normally isn't needed since the encoder and decoder already call it. + +6.4. More Notes +--------------- + +In the PNG file format, if a less than 8-bit per pixel color type is used and the scanlines +have a bit amount that isn't a multiple of 8, then padding bits are used so that each +scanline starts at a fresh byte. +However: The raw input image you give to the encoder, and the raw output image you get from the decoder +will NOT have these padding bits in that case, e.g. in the case of a 1-bit image with a width +of 7 pixels, the first pixel of the second scanline will the the 8th bit of the first byte, +not the first bit of a new byte. + +7. error values +--------------- + +All functions in LodePNG that return an error code, return 0 if everything went +OK, or one of the code defined by LodePNG if there was an error. + +The meaning of the LodePNG error values can be retrieved with the function +LodePNG_error_text: given the numerical error code, it returns a description +of the error in English as a string. + +Check the implementation of LodePNG_error_text to see the meaning of each error code. + + +8. chunks and PNG editing +------------------------- + +If you want to add extra chunks to a PNG you encode, or use LodePNG for a PNG +editor that should follow the rules about handling of unknown chunks, or if you +program is able to read other types of chunks than the ones handled by LodePNG, +then that's possible with the chunk functions of LodePNG. + +A PNG chunk has the following layout: + +4 bytes length +4 bytes type name +length bytes data +4 bytes CRC + + +8.1. iterating through chunks +----------------------------- + +If you have a buffer containing the PNG image data, then the first chunk (the +IHDR chunk) starts at byte number 8 of that buffer. The first 8 bytes are the +signature of the PNG and are not part of a chunk. But if you start at byte 8 +then you have a chunk, and can check the following things of it. + +NOTE: none of these functions check for memory buffer boundaries. To avoid +exploits, always make sure the buffer contains all the data of the chunks. +When using LodePNG_chunk_next, make sure the returned value is within the +allocated memory. + +unsigned LodePNG_chunk_length(const unsigned char* chunk): + +Get the length of the chunk's data. The total chunk length is this length + 12. + +void LodePNG_chunk_type(char type[5], const unsigned char* chunk): +unsigned char LodePNG_chunk_type_equals(const unsigned char* chunk, const char* type): + +Get the type of the chunk or compare if it's a certain type + +unsigned char LodePNG_chunk_critical(const unsigned char* chunk): +unsigned char LodePNG_chunk_private(const unsigned char* chunk): +unsigned char LodePNG_chunk_safetocopy(const unsigned char* chunk): + +Check if the chunk is critical in the PNG standard (only IHDR, PLTE, IDAT and IEND are). +Check if the chunk is private (public chunks are part of the standard, private ones not). +Check if the chunk is safe to copy. If it's not, then, when modifying data in a critical +chunk, unsafe to copy chunks of the old image may NOT be saved in the new one if your +program doesn't handle that type of unknown chunk. + +unsigned char* LodePNG_chunk_data(unsigned char* chunk): +const unsigned char* LodePNG_chunk_data_const(const unsigned char* chunk): + +Get a pointer to the start of the data of the chunk. + +unsigned LodePNG_chunk_check_crc(const unsigned char* chunk): +void LodePNG_chunk_generate_crc(unsigned char* chunk): + +Check if the crc is correct or generate a correct one. + +unsigned char* LodePNG_chunk_next(unsigned char* chunk): +const unsigned char* LodePNG_chunk_next_const(const unsigned char* chunk): + +Iterate to the next chunk. This works if you have a buffer with consecutive chunks. Note that these +functions do no boundary checking of the allocated data whatsoever, so make sure there is enough +data available in the buffer to be able to go to the next chunk. + +unsigned LodePNG_append_chunk(unsigned char** out, size_t* outlength, const unsigned char* chunk): +unsigned LodePNG_create_chunk(unsigned char** out, size_t* outlength, unsigned length, const char* type, const unsigned char* data): + +These functions are used to create new chunks that are appended to the data in *out that has +length *outlength. The append function appends an existing chunk to the new data. The create +function creates a new chunk with the given parameters and appends it. Type is the 4-letter +name of the chunk. + + +8.2. chunks in infoPng +---------------------- + +The LodePNG_InfoPng struct contains a struct LodePNG_UnknownChunks in it. This +struct has 3 buffers (each with size) to contain 3 types of unknown chunks: +the ones that come before the PLTE chunk, the ones that come between the PLTE +and the IDAT chunks, and the ones that come after the IDAT chunks. +It's necessary to make the distionction between these 3 cases because the PNG +standard forces to keep the ordering of unknown chunks compared to the critical +chunks, but does not force any other ordering rules. + +infoPng.unknown_chunks.data[0] is the chunks before PLTE +infoPng.unknown_chunks.data[1] is the chunks after PLTE, before IDAT +infoPng.unknown_chunks.data[2] is the chunks after IDAT + +The chunks in these 3 buffers can be iterated through and read by using the same +way described in the previous subchapter. + +When using the decoder to decode a PNG, you can make it store all unknown chunks +if you set the option settings.rememberUnknownChunks to 1. By default, this option +is off and is 0. + +The encoder will always encode unknown chunks that are stored in the infoPng. If +you need it to add a particular chunk that isn't known by LodePNG, you can use +LodePNG_append_chunk or LodePNG_create_chunk to the chunk data in +infoPng.unknown_chunks.data[x]. + +Chunks that are known by LodePNG should not be added in that way. E.g. to make +LodePNG add a bKGD chunk, set background_defined to true and add the correct +parameters there and LodePNG will generate the chunk. + + +9. compiler support +------------------- + +No libraries other than the current standard C library are needed to compile +LodePNG. For the C++ version, only the standard C++ library is needed on top. +Add the files lodepng.c(pp) and lodepng.h to your project, include +lodepng.h where needed, and your program can read/write PNG files. + +Use optimization! For both the encoder and decoder, compiling with the best +optimizations makes a large difference. + +Make sure that LodePNG is compiled with the same compiler of the same version +and with the same settings as the rest of the program, or the interfaces with +std::vectors and std::strings in C++ can be incompatible resulting in bad things. + +CHAR_BITS must be 8 or higher, because LodePNG uses unsigned chars for octets. + +*) gcc and g++ + +LodePNG is developed in gcc so this compiler is natively supported. It gives no +warnings with compiler options "-Wall -Wextra -pedantic -ansi", with gcc and g++ +version 4.5.1 on Linux. + +*) Mingw and Bloodshed DevC++ + +The Mingw compiler (a port of gcc) used by Bloodshed DevC++ for Windows is fully +supported by LodePNG. + +*) Visual Studio 2005 and Visual C++ 2005 Express Edition + +Versions 20070604 up to 20080107 have been tested on VS2005 and work. Visual +studio may give warnings about 'fopen' being deprecated. A multiplatform library +can't support the proposed Visual Studio alternative however. + +If you're using LodePNG in VS2005 and don't want to see the deprecated warnings, +put this on top of lodepng.h before the inclusions: #define _CRT_SECURE_NO_DEPRECATE + +*) Visual Studio 6.0 + +The C++ version of LodePNG was not supported by Visual Studio 6.0 because Visual +Studio 6.0 doesn't follow the C++ standard and implements it incorrectly. +The current C version of LodePNG has not been tested in VS6 but may work now. + +*) Comeau C/C++ + +Vesion 20070107 compiles without problems on the Comeau C/C++ Online Test Drive +at http://www.comeaucomputing.com/tryitout in both C90 and C++ mode. + +*) Compilers on Macintosh + +LodePNG has been reported to work both with the gcc and LLVM for Macintosh, both +for C and C++. + +*) Other Compilers + +If you encounter problems on other compilers, I'm happy to help out make LodePNG +support the compiler if it supports the ISO C90 and C++ standard well enough and +the required modification doesn't require using non standard or less good C/C++ +code or headers. + + +10. examples +------------ + +This decoder and encoder example show the most basic usage of LodePNG (using the +classes, not the simple functions, which would be trivial) + +More complex examples can be found in: +-lodepng_examples.c: 9 different examples in C, such as showing the image with SDL, ... +-lodepng_examples.cpp: the same examples in C++ using the C++ wrapper of LodePNG + +These files can be found on the LodePNG website or searched for on the internet. + +10.1. decoder C++ example +------------------------- + +//////////////////////////////////////////////////////////////////////////////// +#include "lodepng.h" +#include + +int main(int argc, char *argv[]) +{ + const char* filename = argc > 1 ? argv[1] : "test.png"; + + //load and decode + std::vector buffer, image; //buffer will contain the PNG file, image will contain the raw pixels + LodePNG::loadFile(buffer, filename); //load the image file with given filename + LodePNG::Decoder decoder; + decoder.decode(image, buffer.size() ? &buffer[0] : 0, (unsigned)buffer.size()); //decode the png + + //if there's an error, display it + if(decoder.hasError()) std::cout << "error " << decoder.getError() << ": " << LodePNG_error_text(decoder.getError()) << std::endl; + + int width = decoder.getWidth(); //get the width in pixels + int height = decoder.getHeight(); //get the height in pixels + //the pixels are now in the vector "image", 4 bytes per pixel, ordered RGBARGBA..., use it as texture, draw it, ... +} + +//alternative version using the "simple" function +int main(int argc, char *argv[]) +{ + const char* filename = argc > 1 ? argv[1] : "test.png"; + + //load and decode + std::vector image; + unsigned width, height; + unsigned error = LodePNG::decode(image, width, height, filename); + + //if there's an error, display it + if(error != 0) std::cout << "error " << error << ": " << LodePNG_error_text(error) << std::endl; + + //the pixels are now in the vector "image", 4 bytes per pixel, ordered RGBARGBA..., use it as texture, draw it, ... +} +//////////////////////////////////////////////////////////////////////////////// + + +10.2. encoder C++ example +------------------------- + +//////////////////////////////////////////////////////////////////////////////// +#include "lodepng.h" +#include + +//saves image to filename given as argument. Warning, this overwrites the file without warning! +int main(int argc, char *argv[]) +{ + //check if user gave a filename + if(argc <= 1) + { + std::cout << "please provide a filename to save to\n"; + return 0; + } + + //generate some image + std::vector image; + image.resize(512 * 512 * 4); + for(unsigned y = 0; y < 512; y++) + for(unsigned x = 0; x < 512; x++) + { + image[4 * 512 * y + 4 * x + 0] = 255 * !(x & y); + image[4 * 512 * y + 4 * x + 1] = x ^ y; + image[4 * 512 * y + 4 * x + 2] = x | y; + image[4 * 512 * y + 4 * x + 3] = 255; + } + + //encode and save, using the Encoder class + std::vector buffer; + LodePNG::Encoder encoder; + encoder.encode(buffer, image, 512, 512); + LodePNG::saveFile(buffer, argv[1]); + + //the same as the 4 lines of code above, but in 1 call without the class: + //LodePNG::encode(argv[1], image, 512, 512); +} +//////////////////////////////////////////////////////////////////////////////// + + +10.3. Decoder C example +----------------------- + +This example loads the PNG from a file into a pixel buffer in 1 function call + +#include "lodepng.h" + +int main(int argc, char *argv[]) +{ + unsigned error; + unsigned char* image; + size_t width, height; + + if(argc <= 1) return 0; + + error = LodePNG_decode32_file(&image, &width, &height, filename); + + if(error != 0) printf("error %u: %s\n", error, LodePNG_error_text(error)); + + //use image here + + free(image); +} + + +11. changes +----------- + +The version number of LodePNG is the date of the change given in the format +yyyymmdd. + +Some changes aren't backwards compatible. Those are indicated with a (!) +symbol. + +*) 21 feb 2011: fixed compiling for C90. Fixed compiling with sections disabled. +*) 11 dec 2010: encoding is made faster, based on suggestion by Peter Eastman + to optimize long sequences of zeros. +*) 13 nov 2010: added LodePNG_InfoColor_hasPaletteAlpha and + LodePNG_InfoColor_canHaveAlpha functions for convenience. +*) 7 nov 2010: added LodePNG_error_text function to get error code description. +*) 30 okt 2010: made decoding slightly faster +*) 26 okt 2010: (!) changed some C function and struct names (more consistent). + Reorganized the documentation and the declaration order in the header. +*) 08 aug 2010: only changed some comments and external samples. +*) 05 jul 2010: fixed bug thanks to warnings in the new gcc version. +*) 14 mar 2010: fixed bug where too much memory was allocated for char buffers. +*) 02 sep 2008: fixed bug where it could create empty tree that linux apps could + read by ignoring the problem but windows apps couldn't. +*) 06 jun 2008: added more error checks for out of memory cases. +*) 26 apr 2008: added a few more checks here and there to ensure more safety. +*) 06 mar 2008: crash with encoding of strings fixed +*) 02 feb 2008: support for international text chunks added (iTXt) +*) 23 jan 2008: small cleanups, and #defines to divide code in sections +*) 20 jan 2008: support for unknown chunks allowing using LodePNG for an editor. +*) 18 jan 2008: support for tIME and pHYs chunks added to encoder and decoder. +*) 17 jan 2008: ability to encode and decode compressed zTXt chunks added + Also vareous fixes, such as in the deflate and the padding bits code. +*) 13 jan 2008: Added ability to encode Adam7-interlaced images. Improved + filtering code of encoder. +*) 07 jan 2008: (!) changed LodePNG to use ISO C90 instead of C++. A + C++ wrapper around this provides an interface almost identical to before. + Having LodePNG be pure ISO C90 makes it more portable. The C and C++ code + are together in these files but it works both for C and C++ compilers. +*) 29 dec 2007: (!) changed most integer types to unsigned int + other tweaks +*) 30 aug 2007: bug fixed which makes this Borland C++ compatible +*) 09 aug 2007: some VS2005 warnings removed again +*) 21 jul 2007: deflate code placed in new namespace separate from zlib code +*) 08 jun 2007: fixed bug with 2- and 4-bit color, and small interlaced images +*) 04 jun 2007: improved support for Visual Studio 2005: crash with accessing + invalid std::vector element [0] fixed, and level 3 and 4 warnings removed +*) 02 jun 2007: made the encoder add a tag with version by default +*) 27 may 2007: zlib and png code separated (but still in the same file), + simple encoder/decoder functions added for more simple usage cases +*) 19 may 2007: minor fixes, some code cleaning, new error added (error 69), + moved some examples from here to lodepng_examples.cpp +*) 12 may 2007: palette decoding bug fixed +*) 24 apr 2007: changed the license from BSD to the zlib license +*) 11 mar 2007: very simple addition: ability to encode bKGD chunks. +*) 04 mar 2007: (!) tEXt chunk related fixes, and support for encoding + palettized PNG images. Plus little interface change with palette and texts. +*) 03 mar 2007: Made it encode dynamic Huffman shorter with repeat codes. + Fixed a bug where the end code of a block had length 0 in the Huffman tree. +*) 26 feb 2007: Huffman compression with dynamic trees (BTYPE 2) now implemented + and supported by the encoder, resulting in smaller PNGs at the output. +*) 27 jan 2007: Made the Adler-32 test faster so that a timewaste is gone. +*) 24 jan 2007: gave encoder an error interface. Added color conversion from any + greyscale type to 8-bit greyscale with or without alpha. +*) 21 jan 2007: (!) Totally changed the interface. It allows more color types + to convert to and is more uniform. See the manual for how it works now. +*) 07 jan 2007: Some cleanup & fixes, and a few changes over the last days: + encode/decode custom tEXt chunks, separate classes for zlib & deflate, and + at last made the decoder give errors for incorrect Adler32 or Crc. +*) 01 jan 2007: Fixed bug with encoding PNGs with less than 8 bits per channel. +*) 29 dec 2006: Added support for encoding images without alpha channel, and + cleaned out code as well as making certain parts faster. +*) 28 dec 2006: Added "Settings" to the encoder. +*) 26 dec 2006: The encoder now does LZ77 encoding and produces much smaller files now. + Removed some code duplication in the decoder. Fixed little bug in an example. +*) 09 dec 2006: (!) Placed output parameters of public functions as first parameter. + Fixed a bug of the decoder with 16-bit per color. +*) 15 okt 2006: Changed documentation structure +*) 09 okt 2006: Encoder class added. It encodes a valid PNG image from the + given image buffer, however for now it's not compressed. +*) 08 sep 2006: (!) Changed to interface with a Decoder class +*) 30 jul 2006: (!) LodePNG_InfoPng , width and height are now retrieved in different + way. Renamed decodePNG to decodePNGGeneric. +*) 29 jul 2006: (!) Changed the interface: image info is now returned as a + struct of type LodePNG::LodePNG_Info, instead of a vector, which was a bit clumsy. +*) 28 jul 2006: Cleaned the code and added new error checks. + Corrected terminology "deflate" into "inflate". +*) 23 jun 2006: Added SDL example in the documentation in the header, this + example allows easy debugging by displaying the PNG and its transparency. +*) 22 jun 2006: (!) Changed way to obtain error value. Added + loadFile function for convenience. Made decodePNG32 faster. +*) 21 jun 2006: (!) Changed type of info vector to unsigned. + Changed position of palette in info vector. Fixed an important bug that + happened on PNGs with an uncompressed block. +*) 16 jun 2006: Internally changed unsigned into unsigned where + needed, and performed some optimizations. +*) 07 jun 2006: (!) Renamed functions to decodePNG and placed them + in LodePNG namespace. Changed the order of the parameters. Rewrote the + documentation in the header. Renamed files to lodepng.cpp and lodepng.h +*) 22 apr 2006: Optimized and improved some code +*) 07 sep 2005: (!) Changed to std::vector interface +*) 12 aug 2005: Initial release + + +12. contact information +----------------------- + +Feel free to contact me with suggestions, problems, comments, ... concerning +LodePNG. If you encounter a PNG image that doesn't work properly with this +decoder, feel free to send it and I'll use it to find and fix the problem. + +My email address is (puzzle the account and domain together with an @ symbol): +Domain: gmail dot com. +Account: lode dot vandevenne. + + +Copyright (c) 2005-2011 Lode Vandevenne +*/ diff --git a/src/m3d_func.S b/src/m3d_func.S new file mode 100644 index 0000000..e5507a6 --- /dev/null +++ b/src/m3d_func.S @@ -0,0 +1,93 @@ + + .align 4 + .globl funcSMULT1616 + .globl funcUMULT1616 + .globl funcSMULT32 + .globl funcUMULT32 + .globl funcUADDMULT1616 + .globl funcSADDMULT1616 + .globl funcSADDMULT32 + .globl funcUADDMULT32 + + + +// Int32 funcSMULT1616(Int32 a,Int32 b,Int32 dummy1,Int32 dummy2) +funcSMULT1616: + mov r2,r0 + mov r3,r1 + smull r0,r1,r3,r2 + mov r0,r0,lsr #16 + orr r0,r0,r1,lsl #16 + mov pc,lr + + +// Int32 funcUMULT1616(UInt32 a,UInt32 b,Int32 dummy1,Int32 dummy2) +funcUMULT1616: + mov r2,r0 + mov r3,r1 + umull r0,r1,r3,r2 + mov r0,r0,lsr #16 + orr r0,r0,r1,lsl #16 + mov pc,lr + +// Int32 funcSMULT32(Int32 a,Int32 b,Int32 dummy1,Int32 dummy2) +funcSMULT32: + mov r2,r0 + mov r3,r1 + smull r1,r0,r2,r3 + mov pc,lr + + +// UInt32 funcUMULT32(UInt32 a,UInt32 b,Int32 dummy1,Int32 dummy2) +funcUMULT32: + mov r2,r0 + mov r3,r1 + umull r1,r0,r3,r2 + mov pc,lr + +// UInt32 funcUADDMULT1616(UInt32 a,UInt32 b,UInt32 c,UInt32 d) +funcUADDMULT1616: + stmfd r13!,{r4,r5} + mov r4,r0 + mov r5,r1 + umull r0,r1,r5,r4 + umlal r0,r1,r2,r3 + mov r0,r0,lsr #16 + orr r0,r0,r1,lsl #16 + ldmfd r13!,{r4,r5} + mov pc,lr + +// Int32 funcSADDMULT1616(Int32 a,Int32 b,Int32 c,Int32 d) +funcSADDMULT1616: + stmfd r13!,{r4,r5} + mov r4,r0 + mov r5,r1 + smull r0,r1,r5,r4 + smlal r0,r1,r2,r3 + mov r0,r0,lsr #16 + orr r0,r0,r1,lsl #16 + ldmfd r13!,{r4,r5} + mov pc,lr + +// Int32 funcSADDMULT32(Int32 a,Int32 b,Int32 c,Int32 d) +funcSADDMULT32: + stmfd r13!,{r4,r5} + mov r4,r0 + mov r5,r1 + smull r1,r0,r5,r4 + smlal r1,r0,r2,r3 + ldmfd r13!,{r4,r5} + mov pc,lr + +// UInt32 funcUADDMULT32(UInt32 a,UInt32 b,UInt32 c,UInt32 d) +funcUADDMULT32: + stmfd r13!,{r4,r5} + mov r4,r0 + mov r5,r1 + umull r1,r0,r5,r4 + umlal r1,r0,r2,r3 + ldmfd r13!,{r4,r5} + mov pc,lr + + +.pool diff --git a/src/main.cpp b/src/main.cpp new file mode 100644 index 0000000..c96d679 --- /dev/null +++ b/src/main.cpp @@ -0,0 +1,1709 @@ +#include +#include +#include +#include +#include +#include +#include +#include "unzip.h" +#include "zip.h" +#include "screenshot.h" +#include "theme.h" + +#ifdef __GIZ__ +#define TIMER_1_SECOND 1000 +#include +#include +#include "giz_sdk.h" +#endif + +#ifdef __GP2X__ +#define TIMER_1_SECOND 1000000 +#include "gp2x_sdk.h" +#include "squidgehack.h" +#endif + +#ifdef __WIZ__ +#define TIMER_1_SECOND 1000000 + #ifdef __CAANOO__ + #include "caanoo_sdk.h" + #else + #include "wiz_sdk.h" + #endif +#include "time.h" +unsigned short *pOutputScreen; +#include "sys/resource.h" +#endif + +#include "menu.h" +#include "snes9x.h" +#include "memmap.h" +#include "apu.h" +#include "gfx.h" +#include "soundux.h" +#include "snapshot.h" + +#include "disk_img.h" +#include "config.h" + +#define EMUVERSION "SquidgeSNES V0.37 01-Jun-06" + +//--------------------------------------------------------------------------- + +#ifdef __GP2X__ +extern "C" char joy_Count(); +extern "C" int InputClose(); +extern "C" int joy_getButton(int joyNumber); +#endif + +extern "C" uint32 Spc700JumpTab_13; +extern "C" uint32 Spc700JumpTab_14; +extern "C" uint32 Spc700JumpTab_15; +extern "C" uint32 Spc700JumpTab_21; + +unsigned char gammatab[10][32]={ + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F, + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F}, + {0x00,0x01,0x02,0x03,0x04,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10, + 0x11,0x12,0x13,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F}, + {0x00,0x01,0x03,0x04,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11, + 0x12,0x13,0x14,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F}, + {0x00,0x02,0x04,0x06,0x07,0x08,0x09,0x0A,0x0C,0x0D,0x0E,0x0F,0x0F,0x10,0x11,0x12, + 0x13,0x14,0x15,0x16,0x16,0x17,0x18,0x19,0x19,0x1A,0x1B,0x1C,0x1C,0x1D,0x1E,0x1F}, + {0x00,0x03,0x05,0x07,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14, + 0x14,0x15,0x16,0x17,0x17,0x18,0x19,0x19,0x1A,0x1B,0x1B,0x1C,0x1D,0x1D,0x1E,0x1F}, + {0x00,0x05,0x07,0x09,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14,0x14,0x15, + 0x16,0x16,0x17,0x18,0x18,0x19,0x1A,0x1A,0x1B,0x1B,0x1C,0x1C,0x1D,0x1D,0x1E,0x1F}, + {0x00,0x07,0x0A,0x0C,0x0D,0x0E,0x10,0x11,0x12,0x12,0x13,0x14,0x15,0x15,0x16,0x17, + 0x17,0x18,0x18,0x19,0x1A,0x1A,0x1B,0x1B,0x1B,0x1C,0x1C,0x1D,0x1D,0x1E,0x1E,0x1F}, + {0x00,0x0B,0x0D,0x0F,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x16,0x17,0x17,0x18,0x18, + 0x19,0x19,0x1A,0x1A,0x1B,0x1B,0x1B,0x1C,0x1C,0x1D,0x1D,0x1D,0x1E,0x1E,0x1E,0x1F}, + {0x00,0x0F,0x11,0x13,0x14,0x15,0x16,0x17,0x17,0x18,0x18,0x19,0x19,0x1A,0x1A,0x1A, + 0x1B,0x1B,0x1B,0x1C,0x1C,0x1C,0x1C,0x1D,0x1D,0x1D,0x1D,0x1E,0x1E,0x1E,0x1E,0x1F}, + {0x00,0x15,0x17,0x18,0x19,0x19,0x1A,0x1A,0x1B,0x1B,0x1B,0x1B,0x1C,0x1C,0x1C,0x1C, + 0x1D,0x1D,0x1D,0x1D,0x1D,0x1D,0x1D,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1E,0x1F} +}; + +int32 gp32_fastmode = 1; +int gp32_8bitmode = 0; +int32 gp32_ShowSub = 0; +int gp32_fastsprite = 1; +int gp32_gammavalue = 0; +int globexit = 0; +int sndvolL, sndvolR; +char fps_display[256]; +int samplecount=0; +int enterMenu = 0; +void *currentFrameBuffer; +int16 oldHeight = 0; +bool8 ROMAPUEnabled = 0; +char lastLoadedFile[2048]; +bool lastLoaded = false; +unsigned short *loadingFB; +int loadingY; +static int loadingPrint(char *txt) { + gp_drawString(20, loadingY, strlen(txt), txt, tTextColorLoading, (unsigned char*)loadingFB); + loadingY += 8; +} + +static int S9xCompareSDD1IndexEntries (const void *p1, const void *p2) +{ + return (*(uint32 *) p1 - *(uint32 *) p2); +} + +void S9xExit () +{ +} +void S9xGenerateSound (void) + { + S9xMessage (0,0,"generate sound"); + return; + } + +extern "C" +{ + void S9xSetPalette () + { + + } + + void S9xExtraUsage () + { + } + + void S9xParseArg (char **argv, int &index, int argc) + { + } + + bool8 S9xOpenSnapshotFile (const char *fname, bool8 read_only, STREAM *file) + { + if (read_only) + { + if (*file = OPEN_STREAM(fname,"rb")) + return(TRUE); + } + else + { + if (*file = OPEN_STREAM(fname,"w+b")) + return(TRUE); + } + + return (FALSE); + } + + void S9xCloseSnapshotFile (STREAM file) + { + CLOSE_STREAM(file); + } + + void S9xMessage (int /* type */, int /* number */, const char *message) + { + printf ("%s\n", message); + } + + void erk (void) + { + S9xMessage (0,0, "Erk!"); + } + + char *osd_GetPackDir(void) + { + S9xMessage (0,0,"get pack dir"); + return "."; + } + + const char *S9xGetSnapshotDirectory(void) + { + S9xMessage (0,0,"get snapshot dir"); + return "."; + } + + void S9xLoadSDD1Data (void) + { + char filename [_MAX_PATH + 1]; + char index [_MAX_PATH + 1]; + char data [_MAX_PATH + 1]; + char patch [_MAX_PATH + 1]; + char text[256]; + //FILE *fs = fopen ("data.log", "w"); + + Settings.SDD1Pack=TRUE; + Memory.FreeSDD1Data (); + + //gp_clearFramebuffer16(framebuffer16[currFB],0x0); + //sprintf(text,"Loading SDD1 pack..."); + //gp_drawString(0,0,strlen(text),text,0xFFFF,(unsigned char*)framebuffer16[currFB]); + //MenuFlip(); + loadingPrint("Loading SDD1 pack..."); + strcpy (filename, romDir); + + if (strncmp (Memory.ROMName, "Star Ocean", 10) == 0) + strcat (filename, "/socnsdd1"); + else + strcat (filename, "/sfa2sdd1"); + + DIR *dir = opendir (filename); + + index [0] = 0; + data [0] = 0; + patch [0] = 0; + + //fprintf(fs,"SDD1 data: %s...\n",filename); + if (dir) + { + struct dirent *d; + + while ((d = readdir (dir))) + { + //fprintf(fs,"File :%s.\n",d->d_name); + if (strcasecmp (d->d_name, "sdd1gfx.idx") == 0) + { + strcpy (index, filename); + strcat (index, "/"); + strcat (index, d->d_name); + //fprintf(fs,"File :%s.\n",index); + } + else + if (strcasecmp (d->d_name, "sdd1gfx.dat") == 0) + { + strcpy (data, filename); + strcat (data, "/"); + strcat (data, d->d_name); + //fprintf(fs,"File :%s.\n",data); + } + if (strcasecmp (d->d_name, "sdd1gfx.pat") == 0) + { + strcpy (patch, filename); + strcat (patch, "/"); + strcat (patch, d->d_name); + } + } + closedir (dir); + + if (strlen (index) && strlen (data)) + { + FILE *fs = fopen (index, "rb"); + int len = 0; + + if (fs) + { + // Index is stored as a sequence of entries, each entry being + // 12 bytes consisting of: + // 4 byte key: (24bit address & 0xfffff * 16) | translated block + // 4 byte ROM offset + // 4 byte length + fseek (fs, 0, SEEK_END); + len = ftell (fs); + rewind (fs); + Memory.SDD1Index = (uint8 *) malloc (len); + fread (Memory.SDD1Index, 1, len, fs); + fclose (fs); + Memory.SDD1Entries = len / 12; + + if (!(fs = fopen (data, "rb"))) + { + free ((char *) Memory.SDD1Index); + Memory.SDD1Index = NULL; + Memory.SDD1Entries = 0; + } + else + { + fseek (fs, 0, SEEK_END); + len = ftell (fs); + rewind (fs); + Memory.SDD1Data = (uint8 *) malloc (len); + fread (Memory.SDD1Data, 1, len, fs); + fclose (fs); + + if (strlen (patch) > 0 && + (fs = fopen (patch, "rb"))) + { + fclose (fs); + } + #ifdef MSB_FIRST + // Swap the byte order of the 32-bit value triplets on + // MSBFirst machines. + uint8 *ptr = Memory.SDD1Index; + for (int i = 0; i < Memory.SDD1Entries; i++, ptr += 12) + { + SWAP_DWORD ((*(uint32 *) (ptr + 0))); + SWAP_DWORD ((*(uint32 *) (ptr + 4))); + SWAP_DWORD ((*(uint32 *) (ptr + 8))); + } + #endif + qsort (Memory.SDD1Index, Memory.SDD1Entries, 12, + S9xCompareSDD1IndexEntries); + } + } + Settings.SDD1Pack = FALSE; + return; + } + } + //fprintf(fs,"Decompressed data pack not found in '%s'\n",filename); + //fclose(fs); + //gp_clearFramebuffer16(framebuffer16[currFB],0x0); + //sprintf(text,"Decompressed data pack not found!"); + //gp_drawString(0,8,strlen(text),text,0xFFFF,(unsigned char*)framebuffer16[currFB]); + //MenuFlip(); + loadingPrint("Decompressed data pack not found!"); + loadingPrint("[Press a button to continue]"); + MenuPause(); + } + + + + bool8_32 S9xInitUpdate () + { + static int needfskip = 0; + + currFB++; + currFB&=3; + + if (snesMenuOptions.renderMode != RENDER_MODE_UNSCALED) + { +#if defined (__WIZ__) + if (PPU.ScreenHeight != SNES_HEIGHT_EXTENDED) + GFX.Screen = (uint8 *) pOutputScreen+ (640*8) + 64; + else + GFX.Screen = (uint8 *) pOutputScreen + 64; +#else + GFX.Screen = (uint8 *) framebuffer16[currFB]; +#endif + } + else if (PPU.ScreenHeight != SNES_HEIGHT_EXTENDED) + GFX.Screen = (uint8 *) framebuffer16[currFB]+ (640*8) + 64; + else + GFX.Screen = (uint8 *) framebuffer16[currFB]+ 64; + + return (TRUE); + } + + bool8_32 S9xDeinitUpdate (int Width, int Height, bool8_32) + { +#if defined (__WIZ__) + if ( snesMenuOptions.renderMode == RENDER_MODE_SCALED) +#else + if ( snesMenuOptions.renderMode == RENDER_MODE_SCALED && oldHeight!=Height) +#endif + { + gp_video_RGB_setscaling(256,Height); + oldHeight=Height; + } +#if defined (__WIZ__) + else if ( snesMenuOptions.renderMode == RENDER_MODE_HORIZONTAL_SCALED) + { + gp_video_RGB_setHZscaling(256,Height); + oldHeight=Height; + } +#endif + + + if ((CPU.SRAMModified) && (snesMenuOptions.autoSram == 2)) Draw16x16Image(framebuffer16[currFB], 320-16, 240-16, disk_img); + + + + if (snesMenuOptions.showFps) + { + unsigned int *pix; + pix=(unsigned int*)framebuffer16[currFB]; + for(int i=8;i;i--) + { + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + *pix++ = 0x0; + pix+=128; + } + gp_setClipping(0, 0, 319, 239); + gp_drawString(0,0,strlen(fps_display),fps_display,0xFFFF,(unsigned char*)framebuffer16[currFB]); + } + + gp_setFramebuffer(currFB,0); + } + + const char *S9xGetFilename (const char *ex) + { + static char filename [PATH_MAX + 1]; + char drive [_MAX_DRIVE + 1]; + char dir [_MAX_DIR + 1]; + char fname [_MAX_FNAME + 1]; + char ext [_MAX_EXT + 1]; + + _splitpath (Memory.ROMFilename, drive, dir, fname, ext); + strcpy (filename, S9xGetSnapshotDirectory ()); + strcat (filename, SLASH_STR); + strcat (filename, fname); + strcat (filename, ex); + + return (filename); + } + +#ifdef __GIZ__ + uint32 S9xReadJoypad (int which1) + { + uint32 val=0x80000000; + + if (which1 != 0) return val; + unsigned long joy = gp_getButton(0); + + if (joy & (1<= joy_Count()) return val; + + joy |= joy_getButton(which1++); + + if (snesMenuOptions.actionButtons) + { + if (joy & (1<100) snesMenuOptions.volume=100; + gp_sound_volume(snesMenuOptions.volume,snesMenuOptions.volume); + } + else if (joy & (1<100) snesMenuOptions.volume=0; + gp_sound_volume(snesMenuOptions.volume,snesMenuOptions.volume); + } + + return val; + } +#endif + +#ifdef __WIZ__ + uint32 S9xReadJoypad (int which1) + { + uint32 val=0x80000000; + if (which1 != 0) return val; + + unsigned long joy = 0; + + joy = gp_getButton(1); + + if (snesMenuOptions.actionButtons) + { + if (joy & (1<100) snesMenuOptions.volume=100; + gp_sound_volume(snesMenuOptions.volume,snesMenuOptions.volume); + } + else if (joy & (1<100) snesMenuOptions.volume=0; + gp_sound_volume(snesMenuOptions.volume,snesMenuOptions.volume); + } + + return val; + } +#endif + + bool8 S9xReadMousePosition (int /* which1 */, int &/* x */, int & /* y */, + uint32 & /* buttons */) + { + S9xMessage (0,0,"read mouse"); + return (FALSE); + } + + bool8 S9xReadSuperScopePosition (int & /* x */, int & /* y */, + uint32 & /* buttons */) + { + S9xMessage (0,0,"read scope"); + return (FALSE); + } + + const char *S9xGetFilenameInc (const char *e) + { + S9xMessage (0,0,"get filename inc"); + return e; + } + + void S9xSyncSpeed(void) + { + //S9xMessage (0,0,"sync speed"); + } + + const char *S9xBasename (const char *f) + { + const char *p; + + S9xMessage (0,0,"s9x base name"); + + if ((p = strrchr (f, '/')) != NULL || (p = strrchr (f, '\\')) != NULL) + return (p + 1); + + return (f); + } + +}; + + +void S9xAutoSaveSRAM (void) +{ + //since I can't sync the data, there is no point in even writing the data + //out at this point. Instead I'm now saving the data as the users enter the menu. + //Memory.SaveSRAM (S9xGetFilename (".srm")); + //sync(); can't sync when emulator is running as it causes delays +} + +void S9xLoadSRAM (void) +{ + char path[MAX_PATH]; + + sprintf(path,"%s%s%s",snesSramDir,DIR_SEP,S9xGetFilename (".srm")); + Memory.LoadSRAM (path); +} + +void S9xSaveSRAM (void) +{ + char path[MAX_PATH]; + + if (CPU.SRAMModified) + { + sprintf(path,"%s%s%s",snesSramDir,DIR_SEP,S9xGetFilename (".srm")); + Memory.SaveSRAM (path); + CPU.SRAMModified = FALSE; + if (snesMenuOptions.autoSram == 2) { + Draw16x16Square(framebuffer16[0], 320-16, 240-16, 0, 0, 0); + Draw16x16Square(framebuffer16[1], 320-16, 240-16, 0, 0, 0); + Draw16x16Square(framebuffer16[2], 320-16, 240-16, 0, 0, 0); + Draw16x16Square(framebuffer16[3], 320-16, 240-16, 0, 0, 0); + } + sync(); + } +} + +bool JustifierOffscreen(void) +{ + return false; +} + +void JustifierButtons(uint32& justifiers) +{ +} + +int os9x_findhacks(int game_crc32){ + int i=0,j; + int _crc32; + char c; + char str[256]; + unsigned int size_snesadvance; + unsigned char *snesadvance; + FILE *f; + + sprintf(str,"%s/snesadvance.dat",currentWorkingDir); + f=fopen(str,"rb"); + if (!f) return 0; + fseek(f,0,SEEK_END); + size_snesadvance=ftell(f); + fseek(f,0,SEEK_SET); + snesadvance=(unsigned char*)malloc(size_snesadvance); + fread(snesadvance,1,size_snesadvance,f); + fclose(f); + + for (;;) { + //get crc32 + j=i; + while ((i='0')&&(c<='9')) _crc32=(_crc32<<4)|(c-'0'); + else if ((c>='A')&&(c<='F')) _crc32=(_crc32<<4)|(c-'A'+10); + else if ((c>='a')&&(c<='f')) _crc32=(_crc32<<4)|(c-'a'+10); + j++; + } + if (game_crc32==_crc32) { + char text[32]; + //gp_clearFramebuffer16(framebuffer16[currFB],0x0); + //sprintf(text,"Loading speed hacks..."); + //gp_drawString(0,0,strlen(text),text,0xFFFF,(unsigned char*)framebuffer16[currFB]); + //MenuFlip(); + loadingPrint("Loading speed hacks..."); + sleep(2); + //int p=0; + for (;;) { + int adr,val; + + i++; + j=i; + while ((i>8)&0xFF; + ROM[adr+1]=val&0xFF; + } else ROM[adr]=val; + } + + if (snesadvance[i]==0x0D) {free(snesadvance);return 1; } + } + + } + while ((i 0; x--) + if (lastLoadedFile[x] == '/') { + x++; + break; + }; + fLoad = lastLoadedFile; + cFile = &lastLoadedFile[x]; + strcpy(currentRomFilename, cFile); + } + + //gp_clearFramebuffer16(framebuffer16[currFB],0x0); + loadingFB = framebuffer16[currFB]; + loadingY = 45; + gp_setClipping(0, 0, 319, 239); + gClearScreen(loadingFB, tBackgroundColor); + if (tBmpLoading != NULL) gDrawBitmap16(loadingFB, 0, 0, tBmpLoading, 0, 0, tBmpLoading->w, tBmpLoading->h); + gp_setClipping(20, 40, 320 - 20, 240 - 40); + MenuFlip(); + //sprintf(text,"Loading Rom..."); + //gp_drawString(0,0,strlen(text),text,tTextColorLoading,(unsigned char*)framebuffer16[currFB]); + loadingPrint("Loading Rom..."); + //x = strlen(cFile); + //if (x > 40) x = 40; + //gp_drawString(0,8,x,cFile,0xFFFF,(unsigned char*)framebuffer16[currFB]); + loadingPrint(cFile); + S9xReset(); + + if (!Memory.LoadROM (fLoad)) + { + //sprintf(text,"Loading ROM...Failed"); + //gp_drawString(0,0,strlen(text),text,0xFFFF,(unsigned char*)framebuffer16[currFB]); + //gp_drawString(0,8,x,cFile,0xFFFF,(unsigned char*)framebuffer16[currFB]); + loadingPrint("Loading ROM...Failed"); + loadingPrint("[Press a button to continue]"); + //sprintf(text, "Press a button to continue."); + //gp_drawString(0,16,strlen(text),text,0xFFFF,(unsigned char*)framebuffer16[currFB]); + //MenuFlip(); + MenuPause(); + return 0; + } + + if (!lastLoaded) setConfigValue(CONFIG_LASTLOADED, filename); + else lastLoaded = false; + + //sprintf(text,"Loading Rom...OK!"); + //gp_drawString(0,0,strlen(text),text,0xFFFF,(unsigned char*)framebuffer16[currFB]); + //sprintf(text,"Loading Sram"); + //gp_drawString(0,8,strlen(text),text,0xFFFF,(unsigned char*)framebuffer16[currFB]); + //MenuFlip(); + loadingPrint("Loading ROM...OK!"); + loadingPrint("Loading SRAM..."); + + //Memory.LoadSRAM (S9xGetFilename (".srm")); + S9xLoadSRAM(); + + //auto load default config for this rom if one exists + loadingPrint("Loading ROM options..."); + if (LoadMenuOptions(snesOptionsDir, currentRomFilename, MENU_OPTIONS_EXT, (char*)&snesMenuOptions, sizeof(snesMenuOptions),0)) + { + loadingPrint("Not found. Loading global options..."); + //failed to load options for game, so load the default global ones instead + if (LoadMenuOptions(snesOptionsDir, MENU_OPTIONS_FILENAME, MENU_OPTIONS_EXT, (char*)&snesMenuOptions, sizeof(snesMenuOptions),0)) + { + //failed to load global options, so use default values + SnesDefaultMenuOptions(); + } + } + if (Settings.SpeedHacks) os9x_findhacks(Memory.CalculatedChecksum); + + //gp_clearFramebuffer16(framebuffer16[currFB],0x0); + gp_setClipping(0, 0, 319, 239); + return(1); +} + +#ifdef __GIZ__ +static int SegAim() +{ + + int aim=FrameworkAudio_GetCurrentBank(); + return aim; +} +#endif + +#if defined(__GP2X__) || defined(__WIZ__) +static int SegAim() +{ + int aim=CurrentSoundBank; + aim--; if (aim<0) aim+=8; + + return aim; +} +#endif + + +void _makepath (char *path, const char *, const char *dir, + const char *fname, const char *ext) +{ + if (dir && *dir) + { + strcpy (path, dir); + strcat (path, "/"); + } + else + *path = 0; + strcat (path, fname); + if (ext && *ext) + { + strcat (path, "."); + strcat (path, ext); + } +} + +void _splitpath (const char *path, char *drive, char *dir, char *fname, + char *ext) +{ + *drive = 0; + + char *slash = strrchr (path, '/'); + if (!slash) + slash = strrchr (path, '\\'); + + char *dot = strrchr (path, '.'); + + if (dot && slash && dot < slash) + dot = NULL; + + if (!slash) + { + strcpy (dir, ""); + strcpy (fname, path); + if (dot) + { + *(fname + (dot - path)) = 0; + strcpy (ext, dot + 1); + } + else + strcpy (ext, ""); + } + else + { + strcpy (dir, path); + *(dir + (slash - path)) = 0; + strcpy (fname, slash + 1); + if (dot) + { + *(fname + (dot - slash) - 1) = 0; + strcpy (ext, dot + 1); + } + else + strcpy (ext, ""); + } +} + +// save state file I/O +int (*statef_open)(const char *fname, const char *mode); +int (*statef_read)(void *p, int l); +int (*statef_write)(void *p, int l); +void (*statef_close)(); +static FILE *state_file = 0; +static char state_filename[MAX_PATH]; +static char *state_mem = NULL; +static int state_mem_pos = 0; +static int state_mem_size=0; +static int state_mode = 0; +static int open_mode = 0; + +int check_zip(char *filename) +{ + uint8 buf[2]; + FILE *fd = NULL; + fd = (FILE*)fopen(filename, "rb"); + if(!fd) return (0); + fread(buf, 1, 2, fd); + fclose(fd); + if(memcmp(buf, "PK", 2) == 0) return (1); + return (0); +} + +static char *load_archive(char *filename, int *file_size) +{ + int size = 0; + char *buf = NULL; + char text[128]; + + unzFile fd = NULL; + unz_file_info info; + int ret = 0; + + /* Attempt to open the archive */ + fd = unzOpen(filename); + if(!fd) + { + printf("Failed to open archive\r\n"); + return NULL; + } + + /* Go to first file in archive */ + ret = unzGoToFirstFile(fd); + if(ret != UNZ_OK) + { + printf("Failed to find first file in zip\r\n"); + unzClose(fd); + return NULL; + } + + ret = unzGetCurrentFileInfo(fd, &info, NULL, 0, NULL, 0, NULL, 0); + if(ret != UNZ_OK) + { + printf("Failed to zip info\r\n"); + unzClose(fd); + return NULL; + } + + /* Open the file for reading */ + ret = unzOpenCurrentFile(fd); + if(ret != UNZ_OK) + { + printf("Failed to read file\r\n"); + unzClose(fd); + return NULL; + } + + /* Allocate file data buffer */ + size = info.uncompressed_size; + buf=(char*)malloc(size); + if(!buf) + { + printf("Failed to malloc zip buffer\r\n"); + unzClose(fd); + return NULL; + } + + /* Read (decompress) the file */ + ret = unzReadCurrentFile(fd, buf, info.uncompressed_size); + if(ret != info.uncompressed_size) + { + free(buf); + printf("File failed to uncompress fully\r\n"); + unzCloseCurrentFile(fd); + unzClose(fd); + return NULL; + } + + /* Close the current file */ + ret = unzCloseCurrentFile(fd); + if(ret != UNZ_OK) + { + free(buf); + printf("Failed to close file in zip\r\n"); + unzClose(fd); + return NULL; + } + + /* Close the archive */ + ret = unzClose(fd); + if(ret != UNZ_OK) + { + free(buf); + printf("Failed to close zip\r\n"); + return NULL; + } + + /* Update file size and return pointer to file data */ + *file_size = size; + return buf; +} + +static int save_archive(char *filename, char *buffer, int size) +{ + uint8 *buf = NULL; + char text[128]=""; + zipFile fd = NULL; + int ret = 0; + fd=zipOpen(filename,0); + if(!fd) + { + printf("Failed to create zip\r\n"); + return (0); + } + + ret=zipOpenNewFileInZip(fd,"SNAPSHOT", + NULL, + NULL,0, + NULL,0, + NULL, + Z_DEFLATED, + Z_BEST_COMPRESSION); + + if(ret != ZIP_OK) + { + zipClose(fd,NULL); + printf("Failed to create file in zip\r\n"); + return (0); + } + + ret=zipWriteInFileInZip(fd,buffer,size); + if(ret != ZIP_OK) + { + zipCloseFileInZip(fd); + zipClose(fd,NULL); + printf("Failed to write file in zip\r\n"); + return (0); + } + + ret=zipCloseFileInZip(fd); + if(ret != ZIP_OK) + { + zipClose(fd,NULL); + printf("Failed to close file in zip\r\n"); + return (0); + } + + ret=zipClose(fd,NULL); + if(ret != ZIP_OK) + { + printf("Failed to close zip\r\n"); + return (0); + } + + return(1); +} + +int state_unc_open(const char *fname, const char *mode) +{ + //mode = "wb" or "rb" + //If mode is write then create a new buffer to hold written data + //when file is closed buffer will be compressed to zip file and then freed + if(mode[0]=='r') + { + //Read mode requested + if(check_zip((char*)fname)) + { + //File is a zip, so uncompress + state_mode = 1; //zip mode + open_mode = 0; + state_mem=load_archive((char*)fname,&state_mem_size); + if(!state_mem) return 0; + state_mem_pos=0; + strcpy(state_filename,fname); + return 1; + } + else + { + state_mode = 0; //normal file mode + state_file = fopen(fname, mode); + return (int) state_file; + } + } + else + { + //Write mode requested. Zip only option + open_mode = 1; + state_mode = 1; //normal file mode + state_mem=(char*)malloc(200); + state_mem_size=200; + state_mem_pos = 0; + strcpy(state_filename,fname); + return 1; + } +} + +int state_unc_read(void *p, int l) +{ + if(state_mode==0) + { + return fread(p, 1, l, state_file); + } + else + { + + if((state_mem_pos+l)>state_mem_size) + { + //Read requested that exceeded memory limits + return 0; + } + else + { + memcpy(p,state_mem+state_mem_pos,l); + state_mem_pos+=l; + } + return l; + } +} + +int state_unc_write(void *p, int l) +{ + if(state_mode==0) + { + return fwrite(p, 1, l, state_file); + } + else + { + if((state_mem_pos+l)>state_mem_size) + { + printf("realloc\r\n"); + //Write will exceed current buffer, re-alloc buffer and continue + state_mem=(char*)realloc(state_mem,state_mem_pos+l); + state_mem_size=state_mem_pos+l; + } + //Now do write + memcpy(state_mem+state_mem_pos,p,l); + state_mem_pos+=l; + return l; + } +} + +void state_unc_close() +{ + if(state_mode==0) + { + fclose(state_file); + } + else + { + if (open_mode == 1) + save_archive(state_filename,state_mem,state_mem_size); + free(state_mem); + state_mem=NULL; + state_mem_size=0; + state_mem_pos=0; + state_filename[0]=0; + } +} + +char **g_argv; +int main(int argc, char *argv[]) +{ + unsigned int i,j = 0; + unsigned int romrunning = 0; + int aim=0, done=0, skip=0, Frames=0, fps=0, tick=0,efps=0; + uint8 *soundbuffer=NULL; + int Timer=0; + int action=0; + int romloaded=0; + char text[256]; + DIR *d; + + g_argv = argv; + + // saves + statef_open = state_unc_open; + statef_read = state_unc_read; + statef_write = state_unc_write; + statef_close = state_unc_close; + + + + getcwd(currentWorkingDir, MAX_PATH); + CheckDirSep(currentWorkingDir); + + sprintf(snesOptionsDir,"%s%s%s",currentWorkingDir,DIR_SEP,SNES_OPTIONS_DIR); + sprintf(snesSramDir,"%s%s%s",currentWorkingDir,DIR_SEP,SNES_SRAM_DIR); + sprintf(snesSaveStateDir,"%s%s%s",currentWorkingDir,DIR_SEP,SNES_SAVESTATE_DIR); + +#ifdef __WIZ__ + setpriority (PRIO_PROCESS, 0, -20); +#endif + + + InputInit(); // clear input context + + //ensure dirs exist + //should really check if these worked but hey whatever + mkdir(snesOptionsDir,0777); + mkdir(snesSramDir,0777); + mkdir(snesSaveStateDir,0777); + + printf("Loading global menu options\r\n"); fflush(stdout); + if (LoadMenuOptions(snesOptionsDir,MENU_OPTIONS_FILENAME,MENU_OPTIONS_EXT,(char*)&snesMenuOptions, sizeof(snesMenuOptions),0)) + { + // Failed to load menu options so default options + printf("Failed to load global options, so using defaults\r\n"); fflush(stdout); + SnesDefaultMenuOptions(); + } + + printf("Loading default rom directory\r\n"); fflush(stdout); + if (LoadMenuOptions(snesOptionsDir,DEFAULT_ROM_DIR_FILENAME,DEFAULT_ROM_DIR_EXT,(char*)snesRomDir, MAX_PATH,0)) + { + // Failed to load options to default rom directory to current working directory + printf("Failed to default rom dir, so using current dir\r\n"); fflush(stdout); + strcpy(snesRomDir,currentWorkingDir); + } + + //Check that rom directory actually exists + d = opendir(snesRomDir); + if(d) + { + closedir(d); + } + else + { + //Failed to open Rom directory, so reset to current directory + strcpy(snesRomDir,currentWorkingDir); + } + + // Init graphics (must be done before MMUHACK) + gp_initGraphics(16,0,1); + + + +#ifdef __GP2X__ + if (1) + { + printf("Craigs RAM settings are enabled. Now applying settings..."); fflush(stdout); + // craigix: --trc 6 --tras 4 --twr 1 --tmrd 1 --trfc 1 --trp 2 --trcd 2 + set_RAM_Timings(6, 4, 1, 1, 1, 2, 2); + printf("Done\r\n"); fflush(stdout); + } + else + { + printf("Using normal Ram settings.\r\n"); fflush(stdout); + } + + set_gamma(snesMenuOptions.gamma+100); +#endif + + UpdateMenuGraphicsGamma(); + + // Initialise Snes stuff + ZeroMemory (&Settings, sizeof (Settings)); + + Settings.JoystickEnabled = FALSE; + Settings.SoundPlaybackRate = 22050; + Settings.Stereo = FALSE; + Settings.SoundBufferSize = 0; + Settings.CyclesPercentage = 100; + Settings.DisableSoundEcho = FALSE; + Settings.APUEnabled = FALSE; + Settings.H_Max = SNES_CYCLES_PER_SCANLINE; + Settings.SkipFrames = AUTO_FRAMERATE; + Settings.Shutdown = Settings.ShutdownMaster = TRUE; + Settings.FrameTimePAL = 20000; + Settings.FrameTimeNTSC = 16667; + Settings.FrameTime = Settings.FrameTimeNTSC; + Settings.DisableSampleCaching = FALSE; + Settings.DisableMasterVolume = FALSE; + Settings.Mouse = FALSE; + Settings.SuperScope = FALSE; + Settings.MultiPlayer5 = FALSE; + // Settings.ControllerOption = SNES_MULTIPLAYER5; + Settings.ControllerOption = 0; + + Settings.ForceTransparency = FALSE; + Settings.Transparency = FALSE; + Settings.SixteenBit = TRUE; + + Settings.SupportHiRes = FALSE; + Settings.NetPlay = FALSE; + Settings.ServerName [0] = 0; + Settings.AutoSaveDelay = 30; + Settings.ApplyCheats = FALSE; + Settings.TurboMode = FALSE; + Settings.TurboSkipFrames = 15; + Settings.ThreadSound = FALSE; + Settings.SoundSync = FALSE; + Settings.asmspc700 = TRUE; + Settings.SpeedHacks = TRUE; + + //Settings.NoPatch = true; + + //initScreenShots(); + + GFX.Screen = (uint8 *) framebuffer16[currFB]; +#if defined(__WIZ__) || defined(__GP2X__) + GFX.SubScreen = (uint8 *)malloc(GFX_PITCH * 240 * 2); + GFX.ZBuffer = (uint8 *)malloc(0x13000*2); + GFX.SubZBuffer = GFX.ZBuffer + ZDELTA; + //GFX.ZBuffer = (uint8 *)malloc(320 * 240); + //GFX.SubZBuffer = (uint8 *)malloc(320 * 240); + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; +#else + GFX.SubScreen = (uint8 *)malloc(GFX_PITCH * 480 * 2); + GFX.ZBuffer = (uint8 *)malloc(GFX_PITCH * 480 * 2); + GFX.SubZBuffer = (uint8 *)malloc(GFX_PITCH * 480 * 2); + GFX.Delta = (GFX.SubScreen - GFX.Screen) >> 1; +#endif + +#if defined(__WIZ__) + pOutputScreen = NULL; + pOutputScreen = (uint16 *)malloc(320*240*2); +#endif + + if (Settings.ForceNoTransparency) + Settings.Transparency = FALSE; + + if (Settings.Transparency) + Settings.SixteenBit = TRUE; + + Settings.HBlankStart = (256 * Settings.H_Max) / SNES_HCOUNTER_MAX; + + if (!Memory.Init () || !S9xInitAPU()) + erk(); + + S9xInitSound (); + + //S9xSetRenderPixelFormat (RGB565); + S9xSetSoundMute (TRUE); + + if (!S9xGraphicsInit ()) + erk(); + + // Look for last loaded game + if (snesMenuOptions.loadOnInit == 1) { + getConfigValue(CONFIG_LASTLOADED, lastLoadedFile, sizeof(lastLoadedFile)-1) ; + action = EVENT_LOAD_SNES_ROM; + lastLoaded = true; + } + + while (1) + { + S9xSetSoundMute (TRUE); + + if (!lastLoaded) { + getScreenShot(framebuffer16[prevFB]); + initTheme(); + action=MainMenu(action); + destroyScreenShot(); + } + + //gp_clearFramebuffer16(framebuffer16[currFB],0x0); + if (action==EVENT_EXIT_APP) break; + + if (action==EVENT_LOAD_SNES_ROM) + { + // user wants to load a rom + Settings.SpeedHacks = snesMenuOptions.SpeedHacks; + gp_setCpuspeed(MENU_FAST_CPU_SPEED); + romloaded=SnesRomLoad(); + gp_setCpuspeed(MENU_CPU_SPEED); + if(romloaded) + { + action=EVENT_RUN_SNES_ROM; // rom loaded okay so continue with emulation + } + else + action=0; // rom failed to load so return to menu + } + + if (action==EVENT_RESET_SNES_ROM) + { + // user wants to reset current game + Settings.asmspc700 = snesMenuOptions.asmspc700; + Settings.SpeedHacks = snesMenuOptions.SpeedHacks; + S9xReset(); + action=EVENT_RUN_SNES_ROM; + } + + if (action==EVENT_RUN_SNES_ROM) + { +#ifdef __WIZ__ + // scaling ? + if (snesMenuOptions.renderMode == RENDER_MODE_UNSCALED) { + if (pOutputScreen) { + free(pOutputScreen); + pOutputScreen = NULL; + } + } else { + if (!pOutputScreen) { + pOutputScreen = (uint16 *)malloc(320*240*2); + if (!pOutputScreen) snesMenuOptions.renderMode == RENDER_MODE_UNSCALED; + } + } +#endif + // any change in configuration? + gp_setCpuspeed(cpuSpeedLookup[snesMenuOptions.cpuSpeed]); + gp_clearFramebuffer16(framebuffer16[0], tBackgroundColor); + gp_clearFramebuffer16(framebuffer16[1], tBackgroundColor); + gp_clearFramebuffer16(framebuffer16[2], tBackgroundColor); + gp_clearFramebuffer16(framebuffer16[3], tBackgroundColor); + if (tBmpInGame) { + gDrawBitmap16(framebuffer16[0], 0, 0, tBmpInGame, 0, 0, tBmpInGame->w, tBmpInGame->h); + gDrawBitmap16(framebuffer16[1], 0, 0, tBmpInGame, 0, 0, tBmpInGame->w, tBmpInGame->h); + gDrawBitmap16(framebuffer16[2], 0, 0, tBmpInGame, 0, 0, tBmpInGame->w, tBmpInGame->h); + gDrawBitmap16(framebuffer16[3], 0, 0, tBmpInGame, 0, 0, tBmpInGame->w, tBmpInGame->h); + } + destroyTheme(); + + // Set APU speed + switch (IAPU.OneCycle) { + case 13: + IAPU.asmJumpTab = &Spc700JumpTab_13; + break; + case 14: + IAPU.asmJumpTab = &Spc700JumpTab_14; + break; + //default: + case 15: + IAPU.asmJumpTab = &Spc700JumpTab_15; + break; + default: + case 21: + IAPU.asmJumpTab = &Spc700JumpTab_21; + break; + } + +#ifdef ASMCPU + CPU.DSPGet = (void *)GetDSP; + CPU.DSPSet = (void *)SetDSP; +#endif + + Settings.os9x_hack = snesMenuOptions.graphHacks; + if (snesMenuOptions.transparency) + { + Settings.Transparency = TRUE; + Settings.SixteenBit = TRUE; + } + else + { + Settings.Transparency = FALSE; + Settings.SixteenBit = TRUE; + } + + //SelectUpdateScreen(); + switch (snesMenuOptions.region) + { + case 0: + Settings.ForceNTSC = Settings.ForcePAL = FALSE; + if (Memory.HiROM) + // Country code + Settings.PAL = ROM [0xffd9] >= 2; + else + Settings.PAL = ROM [0x7fd9] >= 2; + break; + case 1: + Settings.ForceNTSC = TRUE; + Settings.PAL = Settings.ForcePAL= FALSE; + break; + case 2: + Settings.ForceNTSC = FALSE; + Settings.PAL = Settings.ForcePAL= TRUE; + break; + } + Settings.FrameTime = Settings.PAL?Settings.FrameTimePAL:Settings.FrameTimeNTSC; + Memory.ROMFramesPerSecond = Settings.PAL?50:60; + + oldHeight = 0; + + if (!S9xGraphicsInit ()) + erk(); + + if (snesMenuOptions.soundOn) + { + unsigned int frame_limit = (Settings.PAL?50:60); + gp32_fastmode = 1; + gp32_8bitmode = 0; + gp32_ShowSub = 0; + gp32_fastsprite = 1; + gp32_gammavalue = snesMenuOptions.gamma; + Settings.asmspc700 = snesMenuOptions.asmspc700; + if (snesMenuOptions.soundHack) + CPU.APU_APUExecuting = Settings.APUEnabled = 3; + else + { + CPU.APU_APUExecuting = Settings.APUEnabled = 1; + } + Settings.SoundPlaybackRate=(unsigned int)soundRates[snesMenuOptions.soundRate]; + Settings.SixteenBitSound=true; + Settings.Stereo=snesMenuOptions.stereo; + samplecount=Settings.SoundPlaybackRate/frame_limit; + if (Settings.Stereo) + samplecount = samplecount * 2; + gp_initSound(Settings.SoundPlaybackRate,16,Settings.Stereo,frame_limit,0x0002000F); + so.stereo = Settings.Stereo; + so.playback_rate = Settings.SoundPlaybackRate; + S9xSetPlaybackRate(so.playback_rate); + S9xSetSoundMute (FALSE); +#if defined(__GP2X__) || defined(__WIZ__) + SoundThreadFlag = SOUND_THREAD_SOUND_ON; +#endif + gp_sound_volume(snesMenuOptions.volume,snesMenuOptions.volume); + + while (1) + { + for (i=10;i;i--) + { + Timer=gp_timer_read(); + if(Timer-tick>TIMER_1_SECOND) + { + fps=Frames; + Frames=0; + tick=Timer; + sprintf(fps_display,"Fps: %2d",fps); + } + else if (Timer=8) done=0; + if(snesMenuOptions.frameSkip==0) + { +#if defined(__GIZ__) + int aim1; + int aim2; + int aim3; + aim1=aim-1; + if(aim1<0) aim1+=7; + aim2=aim-2; + if(aim2<0) aim2+=7; + aim3=aim-3; + if(aim3<0) aim3+=7; + //If we start to get to slow the audio buffer will start + //to catch us up. So we need to skip frames in order to + //catch up the real time rendering + if( + (done==aim) || // we up right up to speed to render frame + (done==aim1) || // we are 1 bank behind so still okay + (done==aim2) || // we are 2 banks behind so just about ok + (done==aim3) // we are 3 banks behind so getting dodgy + ) + { + IPPU.RenderThisFrame=TRUE; // Render last frame + Frames++; + } + +#endif +#if defined(__GP2X__) || defined(__WIZ__) + if ((done==aim)) + { + IPPU.RenderThisFrame=TRUE; // Render last frame + Frames++; + } +#endif + else IPPU.RenderThisFrame=FALSE; + } + else + { + if (skip) + { + IPPU.RenderThisFrame=FALSE; + skip--; + } + else + { + IPPU.RenderThisFrame=TRUE; + Frames++; + skip=snesMenuOptions.frameSkip-1; + } + } + S9xMainLoop (); + S9xMixSamples((short*)soundbuffer, samplecount); + } + if (done==aim) break; // Up to date now + } +#if defined (__GP2X__) || defined(__WIZ__) + done=aim; // Make sure up to date +#endif + // need some way to exit menu + if (enterMenu) + break; + } + enterMenu=0; + gp_stopSound(); + } + else + { + int quit=0,ticks=0,now=0,done=0,i=0; + int tick=0,fps=0; + unsigned int frame_limit = (Settings.PAL?50:60); + unsigned int frametime=TIMER_1_SECOND/frame_limit; + CPU.APU_APUExecuting = Settings.APUEnabled = 0; + S9xSetSoundMute (TRUE); + Timer=0; + Frames=0; + while (1) + { + Timer=gp_timer_read()/frametime; + if(Timer-tick>frame_limit) + { + fps=Frames; + Frames=0; + tick=Timer; + sprintf(fps_display,"Fps: %2d",fps); + } + else if (Timer10) ticks=10; + for (i=0; i=1) + { + IPPU.RenderThisFrame=TRUE; // Render last frame + Frames++; + S9xMainLoop (); + } + } + else + { + if(ticks>(snesMenuOptions.frameSkip-1)) ticks=snesMenuOptions.frameSkip-1; + for (i=0; i=1) + { + IPPU.RenderThisFrame=TRUE; // Render last frame + Frames++; + S9xMainLoop (); + } + } + + done=now; + + // need some way to exit menu + if (enterMenu) + break; + } + enterMenu=0; + } + + if (snesMenuOptions.autoSram) + { + S9xSaveSRAM(); + } + } + } + set_gamma(100); + + //deinitScreenShots(); + destroyTheme(); + + free(GFX.SubScreen); + free(GFX.ZBuffer); +#ifndef __WIZ__ + free(GFX.SubZBuffer); +#endif + +#if defined(__WIZ__) + if (pOutputScreen) free(pOutputScreen); +#endif +#if defined(__GP2X__) + InputClose(); +#endif + gp_Reset(); + return 0; +} diff --git a/src/memcmp.S b/src/memcmp.S new file mode 100644 index 0000000..0692766 --- /dev/null +++ b/src/memcmp.S @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2002 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Adapted for uClibc from NetBSD memcmp.S, version 1.2 2003/04/05 + * by Erik Andersen + */ + + + .text + .global memcmp; + .type memcmp,%function + .align 4; + +memcmp: + /* if ((len - 1) < 0) return 0 */ + subs r2, r2, #1 + movmi r0, #0 + //movmi pc, lr + bxmi lr + + /* ip == last src address to compare */ + add ip, r0, r2 +1: + ldrb r2, [r0], #1 + ldrb r3, [r1], #1 + cmp ip, r0 + cmpcs r2, r3 + beq 1b + sub r0, r2, r3 + //mov pc, lr + bx lr + +.weak bcmp; + bcmp = memcmp + diff --git a/src/memcpy.S b/src/memcpy.S new file mode 100644 index 0000000..fbd0b63 --- /dev/null +++ b/src/memcpy.S @@ -0,0 +1,496 @@ +/* $NetBSD: memcpy.S,v 1.3 1997/11/22 03:27:12 mark Exp $ */ + +/*- +* Copyright (c) 1997 The NetBSD Foundation, Inc. +* All rights reserved. +* +* This code is derived from software contributed to The NetBSD Foundation +* by Neil A. Carson and Mark Brinicombe +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. All advertising materials mentioning features or use of this software +* must display the following acknowledgement: +* This product includes software developed by the NetBSD +* Foundation, Inc. and its contributors. +* 4. Neither the name of The NetBSD Foundation nor the names of its +* contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS +* ``AS IS\'\' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS +* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +*/ + +/* This was modified by Jay Monkman to +* save and restore r12. This is necessary for RTEMS. +*/ +/* #include */ + +/* +.globl memcpy +memcpy: +stmfd sp!, {r0, r12, lr} +bl _memcpy +ldmfd sp!, {r0, r12, pc} +*/ +/* +.globl memove +memmove: +stmfd sp!, {r0, r12, lr} +bl _memcpy +ldmfd sp!, {r0, r12, pc} +*/ + + +/* +* This is one fun bit of code ... +* Some easy listening music is suggested while trying to understand this +* code e.g. Iron Maiden +* +* For anyone attempting to understand it : +* +* The core code is implemented here with simple stubs for memcpy() +* memmove() and bcopy(). +* +* All local labels are prefixed with Lmemcpy_ +* Following the prefix a label starting f is used in the forward copy code +* while a label using b is used in the backwards copy code +* The source and destination addresses determine whether a forward or +* backward copy is performed. +* Separate bits of code are used to deal with the following situations +* for both the forward and backwards copy. +* unaligned source address +* unaligned destination address +* Separate copy routines are used to produce an optimised result for each +* of these cases. +* The copy code will use LDM/STM instructions to copy up to 32 bytes at +* a time where possible. +* +* Note: r12 (aka ip) can be trashed during the function along with +* r0-r3 although r0-r2 have defined uses i.e. src, dest, len through out. +* Additional registers are preserved prior to use i.e. r4, r5 & lr +* +* Apologies for the state of the comments;-) +*/ + + +.globl memove +.globl memcpy +memmove: +memcpy: + +_memcpy: +/* Determine copy direction */ +cmp r1, r0 +bcc Lmemcpy_backwards + +moveq r0, #0 /* Quick abort for len=0 */ +//moveq pc, lr +bxeq lr + +stmdb sp!, {r0, lr} /* memcpy() returns dest addr */ +subs r2, r2, #4 +blt Lmemcpy_fl4 /* less than 4 bytes */ +ands r12, r0, #3 +bne Lmemcpy_fdestul /* oh unaligned destination addr */ +ands r12, r1, #3 +bne Lmemcpy_fsrcul /* oh unaligned source addr */ + +Lmemcpy_ft8: +/* We have aligned source and destination */ +subs r2, r2, #8 +blt Lmemcpy_fl12 /* less than 12 bytes (4 from above) */ +subs r2, r2, #0x14 +blt Lmemcpy_fl32 /* less than 32 bytes (12 from above) */ +stmdb sp!, {r4} /* borrow r4 */ + +/* blat 32 bytes at a time */ +/* XXX for really big copies perhaps we should use more registers */ +Lmemcpy_floop32: +ldmia r1!, {r3, r4, r12, lr} +stmia r0!, {r3, r4, r12, lr} +ldmia r1!, {r3, r4, r12, lr} +stmia r0!, {r3, r4, r12, lr} +subs r2, r2, #0x20 +bge Lmemcpy_floop32 + +cmn r2, #0x10 +ldmgeia r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */ +stmgeia r0!, {r3, r4, r12, lr} +subge r2, r2, #0x10 +ldmia sp!, {r4} /* return r4 */ + +Lmemcpy_fl32: +adds r2, r2, #0x14 + +/* blat 12 bytes at a time */ +Lmemcpy_floop12: +ldmgeia r1!, {r3, r12, lr} +stmgeia r0!, {r3, r12, lr} +subges r2, r2, #0x0c +bge Lmemcpy_floop12 + +Lmemcpy_fl12: +adds r2, r2, #8 +blt Lmemcpy_fl4 + +subs r2, r2, #4 +ldrlt r3, [r1], #4 +strlt r3, [r0], #4 +ldmgeia r1!, {r3, r12} +stmgeia r0!, {r3, r12} +subge r2, r2, #4 + +Lmemcpy_fl4: +/* less than 4 bytes to go */ +adds r2, r2, #4 +ldmeqia sp!, {r0, pc} /* done */ + +/* copy the crud byte at a time */ +cmp r2, #2 +ldrb r3, [r1], #1 +strb r3, [r0], #1 +ldrgeb r3, [r1], #1 +strgeb r3, [r0], #1 +ldrgtb r3, [r1], #1 +strgtb r3, [r0], #1 +ldmia sp!, {r0, pc} + +/* erg - unaligned destination */ +Lmemcpy_fdestul: +rsb r12, r12, #4 +cmp r12, #2 + +/* align destination with byte copies */ +ldrb r3, [r1], #1 +strb r3, [r0], #1 +ldrgeb r3, [r1], #1 +strgeb r3, [r0], #1 +ldrgtb r3, [r1], #1 +strgtb r3, [r0], #1 +subs r2, r2, r12 +blt Lmemcpy_fl4 /* less the 4 bytes */ + +ands r12, r1, #3 +beq Lmemcpy_ft8 /* we have an aligned source */ + +/* erg - unaligned source */ +/* This is where it gets nasty ... */ +Lmemcpy_fsrcul: +bic r1, r1, #3 +ldr lr, [r1], #4 +cmp r12, #2 +bgt Lmemcpy_fsrcul3 +beq Lmemcpy_fsrcul2 +cmp r2, #0x0c +blt Lmemcpy_fsrcul1loop4 +sub r2, r2, #0x0c +stmdb sp!, {r4, r5} + +Lmemcpy_fsrcul1loop16: +mov r3, lr, lsr #8 +ldmia r1!, {r4, r5, r12, lr} +orr r3, r3, r4, lsl #24 +mov r4, r4, lsr #8 +orr r4, r4, r5, lsl #24 +mov r5, r5, lsr #8 +orr r5, r5, r12, lsl #24 +mov r12, r12, lsr #8 +orr r12, r12, lr, lsl #24 +stmia r0!, {r3-r5, r12} +subs r2, r2, #0x10 +bge Lmemcpy_fsrcul1loop16 +ldmia sp!, {r4, r5} +adds r2, r2, #0x0c +blt Lmemcpy_fsrcul1l4 + +Lmemcpy_fsrcul1loop4: +mov r12, lr, lsr #8 +ldr lr, [r1], #4 +orr r12, r12, lr, lsl #24 +str r12, [r0], #4 +subs r2, r2, #4 +bge Lmemcpy_fsrcul1loop4 + +Lmemcpy_fsrcul1l4: +sub r1, r1, #3 +b Lmemcpy_fl4 + +Lmemcpy_fsrcul2: +cmp r2, #0x0c +blt Lmemcpy_fsrcul2loop4 +sub r2, r2, #0x0c +stmdb sp!, {r4, r5} + +Lmemcpy_fsrcul2loop16: +mov r3, lr, lsr #16 +ldmia r1!, {r4, r5, r12, lr} +orr r3, r3, r4, lsl #16 +mov r4, r4, lsr #16 +orr r4, r4, r5, lsl #16 +mov r5, r5, lsr #16 +orr r5, r5, r12, lsl #16 +mov r12, r12, lsr #16 +orr r12, r12, lr, lsl #16 +stmia r0!, {r3-r5, r12} +subs r2, r2, #0x10 +bge Lmemcpy_fsrcul2loop16 +ldmia sp!, {r4, r5} +adds r2, r2, #0x0c +blt Lmemcpy_fsrcul2l4 + +Lmemcpy_fsrcul2loop4: +mov r12, lr, lsr #16 +ldr lr, [r1], #4 +orr r12, r12, lr, lsl #16 +str r12, [r0], #4 +subs r2, r2, #4 +bge Lmemcpy_fsrcul2loop4 + +Lmemcpy_fsrcul2l4: +sub r1, r1, #2 +b Lmemcpy_fl4 + +Lmemcpy_fsrcul3: +cmp r2, #0x0c +blt Lmemcpy_fsrcul3loop4 +sub r2, r2, #0x0c +stmdb sp!, {r4, r5} + +Lmemcpy_fsrcul3loop16: +mov r3, lr, lsr #24 +ldmia r1!, {r4, r5, r12, lr} +orr r3, r3, r4, lsl #8 +mov r4, r4, lsr #24 +orr r4, r4, r5, lsl #8 +mov r5, r5, lsr #24 +orr r5, r5, r12, lsl #8 +mov r12, r12, lsr #24 +orr r12, r12, lr, lsl #8 +stmia r0!, {r3-r5, r12} +subs r2, r2, #0x10 +bge Lmemcpy_fsrcul3loop16 +ldmia sp!, {r4, r5} +adds r2, r2, #0x0c +blt Lmemcpy_fsrcul3l4 + +Lmemcpy_fsrcul3loop4: +mov r12, lr, lsr #24 +ldr lr, [r1], #4 +orr r12, r12, lr, lsl #8 +str r12, [r0], #4 +subs r2, r2, #4 +bge Lmemcpy_fsrcul3loop4 + +Lmemcpy_fsrcul3l4: +sub r1, r1, #1 +b Lmemcpy_fl4 + +Lmemcpy_backwards: +add r1, r1, r2 +add r0, r0, r2 +subs r2, r2, #4 +blt Lmemcpy_bl4 /* less than 4 bytes */ +ands r12, r0, #3 +bne Lmemcpy_bdestul /* oh unaligned destination addr */ +ands r12, r1, #3 +bne Lmemcpy_bsrcul /* oh unaligned source addr */ + +Lmemcpy_bt8: +/* We have aligned source and destination */ +subs r2, r2, #8 +blt Lmemcpy_bl12 /* less than 12 bytes (4 from above) */ +stmdb sp!, {r4, lr} +subs r2, r2, #0x14 /* less than 32 bytes (12 from above) */ +blt Lmemcpy_bl32 + +/* blat 32 bytes at a time */ +/* XXX for really big copies perhaps we should use more registers */ +Lmemcpy_bloop32: +ldmdb r1!, {r3, r4, r12, lr} +stmdb r0!, {r3, r4, r12, lr} +ldmdb r1!, {r3, r4, r12, lr} +stmdb r0!, {r3, r4, r12, lr} +subs r2, r2, #0x20 +bge Lmemcpy_bloop32 + +Lmemcpy_bl32: +cmn r2, #0x10 +ldmgedb r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */ +stmgedb r0!, {r3, r4, r12, lr} +subge r2, r2, #0x10 +adds r2, r2, #0x14 +ldmgedb r1!, {r3, r12, lr} /* blat a remaining 12 bytes */ +stmgedb r0!, {r3, r12, lr} +subge r2, r2, #0x0c +ldmia sp!, {r4, lr} + +Lmemcpy_bl12: +adds r2, r2, #8 +blt Lmemcpy_bl4 +subs r2, r2, #4 +ldrlt r3, [r1, #-4]! +strlt r3, [r0, #-4]! +ldmgedb r1!, {r3, r12} +stmgedb r0!, {r3, r12} +subge r2, r2, #4 + +Lmemcpy_bl4: +/* less than 4 bytes to go */ +adds r2, r2, #4 +//moveq pc, lr /* done */ +bxeq lr + +/* copy the crud byte at a time */ +cmp r2, #2 +ldrb r3, [r1, #-1]! +ldrgeb r2, [r1, #-1]! +ldrgtb r1, [r1, #-1]! +strb r3, [r0, #-1]! +strgeb r2, [r0, #-1]! +strgtb r1, [r0, #-1]! +//mov pc, lr +bx lr + +/* erg - unaligned destination */ +Lmemcpy_bdestul: +cmp r12, #2 + +/* align destination with byte copies */ +ldrb r3, [r1, #-1]! +strb r3, [r0, #-1]! +ldrgeb r3, [r1, #-1]! +strgeb r3, [r0, #-1]! +ldrgtb r3, [r1, #-1]! +strgtb r3, [r0, #-1]! +subs r2, r2, r12 +blt Lmemcpy_bl4 /* less than 4 bytes to go */ +ands r12, r1, #3 +beq Lmemcpy_bt8 /* we have an aligned source */ + +/* erg - unaligned source */ +/* This is where it gets nasty ... */ +Lmemcpy_bsrcul: +bic r1, r1, #3 +ldr r3, [r1, #0] +cmp r12, #2 +blt Lmemcpy_bsrcul1 +beq Lmemcpy_bsrcul2 +cmp r2, #0x0c +blt Lmemcpy_bsrcul3loop4 +sub r2, r2, #0x0c +stmdb sp!, {r4, r5, lr} + +Lmemcpy_bsrcul3loop16: +mov lr, r3, lsl #8 +ldmdb r1!, {r3-r5, r12} +orr lr, lr, r12, lsr #24 +mov r12, r12, lsl #8 +orr r12, r12, r5, lsr #24 +mov r5, r5, lsl #8 +orr r5, r5, r4, lsr #24 +mov r4, r4, lsl #8 +orr r4, r4, r3, lsr #24 +stmdb r0!, {r4, r5, r12, lr} +subs r2, r2, #0x10 +bge Lmemcpy_bsrcul3loop16 +ldmia sp!, {r4, r5, lr} +adds r2, r2, #0x0c +blt Lmemcpy_bsrcul3l4 + +Lmemcpy_bsrcul3loop4: +mov r12, r3, lsl #8 +ldr r3, [r1, #-4]! +orr r12, r12, r3, lsr #24 +str r12, [r0, #-4]! +subs r2, r2, #4 +bge Lmemcpy_bsrcul3loop4 + +Lmemcpy_bsrcul3l4: +add r1, r1, #3 +b Lmemcpy_bl4 + +Lmemcpy_bsrcul2: +cmp r2, #0x0c +blt Lmemcpy_bsrcul2loop4 +sub r2, r2, #0x0c +stmdb sp!, {r4, r5, lr} + +Lmemcpy_bsrcul2loop16: +mov lr, r3, lsl #16 +ldmdb r1!, {r3-r5, r12} +orr lr, lr, r12, lsr #16 +mov r12, r12, lsl #16 +orr r12, r12, r5, lsr #16 +mov r5, r5, lsl #16 +orr r5, r5, r4, lsr #16 +mov r4, r4, lsl #16 +orr r4, r4, r3, lsr #16 +stmdb r0!, {r4, r5, r12, lr} +subs r2, r2, #0x10 +bge Lmemcpy_bsrcul2loop16 +ldmia sp!, {r4, r5, lr} +adds r2, r2, #0x0c +blt Lmemcpy_bsrcul2l4 + +Lmemcpy_bsrcul2loop4: +mov r12, r3, lsl #16 +ldr r3, [r1, #-4]! +orr r12, r12, r3, lsr #16 +str r12, [r0, #-4]! +subs r2, r2, #4 +bge Lmemcpy_bsrcul2loop4 + +Lmemcpy_bsrcul2l4: +add r1, r1, #2 +b Lmemcpy_bl4 + +Lmemcpy_bsrcul1: +cmp r2, #0x0c +blt Lmemcpy_bsrcul1loop4 +sub r2, r2, #0x0c +stmdb sp!, {r4, r5, lr} + +Lmemcpy_bsrcul1loop32: +mov lr, r3, lsl #24 +ldmdb r1!, {r3-r5, r12} +orr lr, lr, r12, lsr #8 +mov r12, r12, lsl #24 +orr r12, r12, r5, lsr #8 +mov r5, r5, lsl #24 +orr r5, r5, r4, lsr #8 +mov r4, r4, lsl #24 +orr r4, r4, r3, lsr #8 +stmdb r0!, {r4, r5, r12, lr} +subs r2, r2, #0x10 +bge Lmemcpy_bsrcul1loop32 +ldmia sp!, {r4, r5, lr} +adds r2, r2, #0x0c +blt Lmemcpy_bsrcul1l4 + +Lmemcpy_bsrcul1loop4: +mov r12, r3, lsl #24 +ldr r3, [r1, #-4]! +orr r12, r12, r3, lsr #8 +str r12, [r0, #-4]! +subs r2, r2, #4 +bge Lmemcpy_bsrcul1loop4 + +Lmemcpy_bsrcul1l4: +add r1, r1, #1 +b Lmemcpy_bl4 diff --git a/src/memmap.cpp b/src/memmap.cpp new file mode 100644 index 0000000..dffbbd9 --- /dev/null +++ b/src/memmap.cpp @@ -0,0 +1,2782 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include +#include + +#ifdef __linux +//#include +#endif + +#include "snes9x.h" +#include "memmap.h" +#include "cpuexec.h" +#include "ppu.h" +#include "display.h" +#include "cheats.h" +#include "apu.h" +#include "sa1.h" +#include "srtc.h" +#include "sdd1.h" + +#ifndef ZSNES_FX +#include "fxemu.h" +extern struct FxInit_s SuperFX; +#else +START_EXTERN_C +extern uint8 *SFXPlotTable; +END_EXTERN_C +#endif + +static uint8 bytes0x2000 [0x2000]; + +extern bool8 ROMAPUEnabled; + +extern char *rom_filename; +extern bool8 LoadZip(const char* , int32 *, int32 *); + +bool8_32 CMemory::AllASCII (uint8 *b, int size) +{ + for (int i = 0; i < size; i++) + { + if (b[i] < 32 || b[i] > 126) + return (FALSE); + } + return (TRUE); +} + +int CMemory::ScoreHiROM (bool8_32 skip_header) +{ + int score = 0; + int o = skip_header ? 0xff00 + 0x200 : 0xff00; + + if ((Memory.ROM [o + 0xdc] + (Memory.ROM [o + 0xdd] << 8) + + Memory.ROM [o + 0xde] + (Memory.ROM [o + 0xdf] << 8)) == 0xffff) + score += 2; + + if (Memory.ROM [o + 0xda] == 0x33) + score += 2; + if ((Memory.ROM [o + 0xd5] & 0xf) < 4) + score += 2; + if (!(Memory.ROM [o + 0xfd] & 0x80)) + score -= 4; + if (CalculatedSize > 1024 * 1024 * 3) + score += 4; + if ((1 << (Memory.ROM [o + 0xd7] - 7)) > 48) + score -= 1; + if (!AllASCII (&Memory.ROM [o + 0xb0], 6)) + score -= 1; + if (!AllASCII (&Memory.ROM [o + 0xc0], ROM_NAME_LEN - 1)) + score -= 1; + + return (score); +} + +int CMemory::ScoreLoROM (bool8_32 skip_header) +{ + int score = 0; + int o = skip_header ? 0x7f00 + 0x200 : 0x7f00; + + if ((Memory.ROM [o + 0xdc] + (Memory.ROM [o + 0xdd] << 8) + + Memory.ROM [o + 0xde] + (Memory.ROM [o + 0xdf] << 8)) == 0xffff) + score += 2; + + if (Memory.ROM [o + 0xda] == 0x33) + score += 2; + if ((Memory.ROM [o + 0xd5] & 0xf) < 4) + score += 2; + if (CalculatedSize <= 1024 * 1024 * 16) + score += 2; + if (!(Memory.ROM [o + 0xfd] & 0x80)) + score -= 4; + if ((1 << (Memory.ROM [o + 0xd7] - 7)) > 48) + score -= 1; + if (!AllASCII (&Memory.ROM [o + 0xb0], 6)) + score -= 1; + if (!AllASCII (&Memory.ROM [o + 0xc0], ROM_NAME_LEN - 1)) + score -= 1; + + return (score); +} + +char *CMemory::Safe (const char *s) +{ + static char *safe = NULL; + static int safe_len = 0; + + int len = strlen (s); + if (!safe || len + 1 > safe_len) + { + if (safe) + free ((char *) safe); + safe = (char *) malloc (safe_len = len + 1); + } + + for (int i = 0; i < len; i++) + { + if (s [i] >= 32 && s [i] < 127) + safe [i] = s[i]; + else + safe [i] = '?'; + } + safe [len] = 0; + return (safe); +} + +/**********************************************************************************************/ +/* Init() */ +/* This function allocates all the memory needed by the emulator */ +/**********************************************************************************************/ +bool8_32 CMemory::Init () +{ + RAM = (uint8 *) malloc (0x20000); + SRAM = (uint8 *) malloc (0x20000); + VRAM = (uint8 *) malloc (0x10000); + ROM = (uint8 *) malloc (MAX_ROM_SIZE + 0x200 + 0x8000); + FillRAM = NULL; + + IPPU.TileCache [TILE_2BIT] = (uint8 *) malloc (MAX_2BIT_TILES * 128); + IPPU.TileCache [TILE_4BIT] = (uint8 *) malloc (MAX_4BIT_TILES * 128); + IPPU.TileCache [TILE_8BIT] = (uint8 *) malloc (MAX_8BIT_TILES * 128); + + IPPU.TileCached [TILE_2BIT] = (uint8 *) malloc (MAX_2BIT_TILES); + IPPU.TileCached [TILE_4BIT] = (uint8 *) malloc (MAX_4BIT_TILES); + IPPU.TileCached [TILE_8BIT] = (uint8 *) malloc (MAX_8BIT_TILES); + + if (!RAM || !SRAM || !VRAM || !ROM || + !IPPU.TileCache [TILE_2BIT] || !IPPU.TileCache [TILE_4BIT] || + !IPPU.TileCache [TILE_8BIT] || !IPPU.TileCached [TILE_2BIT] || + !IPPU.TileCached [TILE_4BIT] || !IPPU.TileCached [TILE_8BIT]) + { + Deinit (); + return (FALSE); + } + + // FillRAM uses first 32K of ROM image area, otherwise space just + // wasted. Might be read by the SuperFX code. + + FillRAM = ROM; + + // Add 0x8000 to ROM image pointer to stop SuperFX code accessing + // unallocated memory (can cause crash on some ports). + ROM += 0x8000; + + C4RAM = ROM + 0x400000 + 8192 * 8; + ::ROM = ROM; + ::SRAM = SRAM; + ::RegRAM = FillRAM; + +#ifdef ZSNES_FX + SFXPlotTable = ROM + 0x400000; +#else + SuperFX.pvRegisters = &Memory.FillRAM [0x3000]; + SuperFX.nRamBanks = 1; + SuperFX.pvRam = ::SRAM; + SuperFX.nRomBanks = (2 * 1024 * 1024) / (32 * 1024); + SuperFX.pvRom = (uint8 *) ROM; +#endif + + ZeroMemory (IPPU.TileCached [TILE_2BIT], MAX_2BIT_TILES); + ZeroMemory (IPPU.TileCached [TILE_4BIT], MAX_4BIT_TILES); + ZeroMemory (IPPU.TileCached [TILE_8BIT], MAX_8BIT_TILES); + + SDD1Data = NULL; + SDD1Index = NULL; + + return (TRUE); +} + +void CMemory::Deinit () +{ + if (RAM) + { + free ((char *) RAM); + RAM = NULL; + } + if (SRAM) + { + free ((char *) SRAM); + SRAM = NULL; + } + if (VRAM) + { + free ((char *) VRAM); + VRAM = NULL; + } + if (ROM) + { + ROM -= 0x8000; + free ((char *) ROM); + ROM = NULL; + } + + if (IPPU.TileCache [TILE_2BIT]) + { + free ((char *) IPPU.TileCache [TILE_2BIT]); + IPPU.TileCache [TILE_2BIT] = NULL; + } + if (IPPU.TileCache [TILE_4BIT]) + { + free ((char *) IPPU.TileCache [TILE_4BIT]); + IPPU.TileCache [TILE_4BIT] = NULL; + } + if (IPPU.TileCache [TILE_8BIT]) + { + free ((char *) IPPU.TileCache [TILE_8BIT]); + IPPU.TileCache [TILE_8BIT] = NULL; + } + + if (IPPU.TileCached [TILE_2BIT]) + { + free ((char *) IPPU.TileCached [TILE_2BIT]); + IPPU.TileCached [TILE_2BIT] = NULL; + } + if (IPPU.TileCached [TILE_4BIT]) + { + free ((char *) IPPU.TileCached [TILE_4BIT]); + IPPU.TileCached [TILE_4BIT] = NULL; + } + if (IPPU.TileCached [TILE_8BIT]) + { + free ((char *) IPPU.TileCached [TILE_8BIT]); + IPPU.TileCached [TILE_8BIT] = NULL; + } + + FreeSDD1Data (); +} + +void CMemory::FreeSDD1Data () +{ + if (SDD1Index) + { + free ((char *) SDD1Index); + SDD1Index = NULL; + } + if (SDD1Data) + { + free ((char *) SDD1Data); + SDD1Data = NULL; + } +} + +/**********************************************************************************************/ +/* checkext() */ +/**********************************************************************************************/ +int checkzip( char * fn ) +{ + int cnt = strlen(fn); + if( ( (fn[cnt-1] == 'p') || (fn[cnt-1] == 'P') ) && + ( (fn[cnt-2] == 'i') || (fn[cnt-2] == 'I') ) && + ( (fn[cnt-3] == 'z') || (fn[cnt-3] == 'Z') ) ){ + return true; + + } + return false; +} + +/**********************************************************************************************/ +/* LoadROM() */ +/* This function loads a Snes-Backup image */ +/**********************************************************************************************/ +#ifdef _SNESPPC +#pragma warning(disable : 4101) +#pragma warning(disable : 4700) +#endif +bool8_32 CMemory::LoadROM (const char *filename) +{ + unsigned long FileSize = 0; + int retry_count = 0; + STREAM ROMFile; + bool8_32 Interleaved = FALSE; + bool8_32 Tales = FALSE; + char dir [_MAX_DIR + 1]; + char drive [_MAX_DRIVE + 1]; + char name [_MAX_FNAME + 1]; + char ext [_MAX_EXT + 1]; + char fname [_MAX_PATH + 1]; + int i; + + memset (&SNESGameFixes, 0, sizeof(SNESGameFixes)); + SNESGameFixes.SRAMInitialValue = 0x60; + + memset (bytes0x2000, 0, 0x2000); + CPU.TriedInterleavedMode2 = FALSE; + + CalculatedSize = 0; +again: +#ifndef _SNESPPC + _splitpath (filename, drive, dir, name, ext); + _makepath (fname, drive, dir, name, ext); +#else + strcpy(fname, filename); +// strupr(fname); +#endif + +#ifdef __WIN32__ + memmove (&ext [0], &ext[1], 4); +#endif + + int32 TotalFileSize = 0; + +#ifdef UNZIP_SUPPORT + + if( checkzip( fname ) ) + { + if (!LoadZip (fname, &TotalFileSize, &HeaderCount)) + return (FALSE); + + strcpy (ROMFilename, fname); + } + else +#endif + { + if ((ROMFile = OPEN_STREAM (fname, "rb")) == NULL) + return (FALSE); + + strcpy (ROMFilename, fname); + + HeaderCount = 0; + uint8 *ptr = ROM; + bool8_32 more = FALSE; + + do + { + FileSize = READ_STREAM (ptr, MAX_ROM_SIZE + 0x200 - (ptr - ROM), ROMFile); + CLOSE_STREAM (ROMFile); + int calc_size = (FileSize / 0x2000) * 0x2000; + + if ((FileSize - calc_size == 512 && !Settings.ForceNoHeader) || + Settings.ForceHeader) + { + memmove (ptr, ptr + 512, calc_size); + HeaderCount++; + FileSize -= 512; + } + ptr += FileSize; + TotalFileSize += FileSize; + + int len; + if (ptr - ROM < MAX_ROM_SIZE + 0x200 && + (isdigit (ext [0]) && ext [1] == 0 && ext [0] < '9')) + { + more = TRUE; + ext [0]++; +#ifdef __WIN32__ + memmove (&ext [1], &ext [0], 4); + ext [0] = '.'; +#endif +#ifndef _SNESPPC + _makepath (fname, drive, dir, name, ext); +#endif + } + else + if (ptr - ROM < MAX_ROM_SIZE + 0x200 && + (((len = strlen (name)) == 7 || len == 8) && + strncasecmp (name, "sf", 2) == 0 && + isdigit (name [2]) && isdigit (name [3]) && isdigit (name [4]) && + isdigit (name [5]) && isalpha (name [len - 1]))) + { + more = TRUE; + name [len - 1]++; +#ifdef __WIN32__ + memmove (&ext [1], &ext [0], 4); + ext [0] = '.'; +#endif +#ifndef _SNESPPC + _makepath (fname, drive, dir, name, ext); +#endif + } + else + more = FALSE; + } while (more && (ROMFile = OPEN_STREAM (fname, "rb")) != NULL); + } + + if (HeaderCount == 0) + S9xMessage (S9X_INFO, S9X_HEADERS_INFO, "No ROM file header found."); + else + { + if (HeaderCount == 1) + S9xMessage (S9X_INFO, S9X_HEADERS_INFO, + "Found ROM file header (and ignored it)."); + else + S9xMessage (S9X_INFO, S9X_HEADERS_INFO, + "Found multiple ROM file headers (and ignored them)."); + } + + CheckForIPSPatch (filename, HeaderCount != 0, TotalFileSize); + int orig_hi_score, orig_lo_score; + int hi_score, lo_score; + + orig_hi_score = hi_score = ScoreHiROM (FALSE); + orig_lo_score = lo_score = ScoreLoROM (FALSE); + + if (HeaderCount == 0 && !Settings.ForceNoHeader && + ((hi_score > lo_score && ScoreHiROM (TRUE) > hi_score) || + (hi_score <= lo_score && ScoreLoROM (TRUE) > lo_score))) + { + memmove (Memory.ROM, Memory.ROM + 512, TotalFileSize - 512); + TotalFileSize -= 512; + S9xMessage (S9X_INFO, S9X_HEADER_WARNING, + "Try specifying the -nhd command line option if the game doesn't work\n"); + } + + CalculatedSize = (TotalFileSize / 0x2000) * 0x2000; + ZeroMemory (ROM + CalculatedSize, MAX_ROM_SIZE - CalculatedSize); + + // Check for cherryroms.com DAIKAIJYUMONOGATARI2 + + if (CalculatedSize == 0x500000 && + strncmp ((const char *)&ROM [0x40ffc0], "DAIKAIJYUMONOGATARI2", 20) == 0 && + strncmp ((const char *)&ROM [0x40ffb0], "18AE6J", 6) == 0 && + memcmp (&ROM[0x40ffb0], &ROM [0xffb0], 0x30)) + { + memmove (&ROM[0x100000], ROM, 0x500000); + memmove (ROM, &ROM[0x500000], 0x100000); + } + + Interleaved = Settings.ForceInterleaved || Settings.ForceInterleaved2; + if (Settings.ForceLoROM || (!Settings.ForceHiROM && lo_score >= hi_score)) + { + LoROM = TRUE; + HiROM = FALSE; + + // Ignore map type byte if not 0x2x or 0x3x + if ((ROM [0x7fd5] & 0xf0) == 0x20 || (ROM [0x7fd5] & 0xf0) == 0x30) + { + switch (ROM [0x7fd5] & 0xf) + { + case 1: + if (strncmp ((char *) &ROM [0x7fc0], "TREASURE HUNTER G", 17) != 0) + Interleaved = TRUE; + break; + case 2: +#if 0 + if (!Settings.ForceLoROM && + strncmp ((char *) &ROM [0x7fc0], "SUPER FORMATION SOCCE", 21) != 0 && + strncmp ((char *) &ROM [0x7fc0], "Star Ocean", 10) != 0) + { + LoROM = FALSE; + HiROM = TRUE; + } +#endif + break; + case 5: + Interleaved = TRUE; + Tales = TRUE; + break; + } + } + } + else + { + if ((ROM [0xffd5] & 0xf0) == 0x20 || (ROM [0xffd5] & 0xf0) == 0x30) + { + switch (ROM [0xffd5] & 0xf) + { + case 0: + case 3: + Interleaved = TRUE; + break; + } + } + LoROM = FALSE; + HiROM = TRUE; + } + + // More + if (!Settings.ForceHiROM && !Settings.ForceLoROM && + !Settings.ForceInterleaved && !Settings.ForceInterleaved2 && + !Settings.ForceNotInterleaved && !Settings.ForcePAL && + !Settings.ForceSuperFX && !Settings.ForceDSP1 && + !Settings.ForceSA1 && !Settings.ForceC4 && + !Settings.ForceSDD1) + { + if (strncmp ((char *) &ROM [0x7fc0], "YUYU NO QUIZ DE GO!GO!", 22) == 0) + { + LoROM = TRUE; + HiROM = FALSE; + Interleaved = FALSE; + } + else + if (strncmp ((char *) &ROM [0x7fc0], "SP MOMOTAROU DENTETSU2", 22) == 0) + { + LoROM = TRUE; + HiROM = FALSE; + Interleaved = FALSE; + } + else + if (CalculatedSize == 0x100000 && + strncmp ((char *) &ROM [0xffc0], "WWF SUPER WRESTLEMANIA", 22) == 0) + { + int cvcount; + + memmove (&ROM[0x100000] , ROM, 0x100000); + for (cvcount = 0; cvcount < 16; cvcount++) + { + memmove (&ROM[0x8000 * cvcount], &ROM[0x10000 * cvcount + 0x100000 + 0x8000], 0x8000); + memmove (&ROM[0x8000 * cvcount + 0x80000], &ROM[0x10000 * cvcount + 0x100000], 0x8000); + } + LoROM = TRUE; + HiROM = FALSE; + ZeroMemory (ROM + CalculatedSize, MAX_ROM_SIZE - CalculatedSize); + } + } + + if (!Settings.ForceNotInterleaved && Interleaved) + { + CPU.TriedInterleavedMode2 = TRUE; + S9xMessage (S9X_INFO, S9X_ROM_INTERLEAVED_INFO, + "ROM image is in interleaved format - converting..."); + + int nblocks = CalculatedSize >> 16; +#if 0 + int step = 64; + + while (nblocks <= step) + step >>= 1; + + nblocks = step; +#endif + uint8 blocks [256]; + + if (Tales) + { + nblocks = 0x60; + for (i = 0; i < 0x40; i += 2) + { + blocks [i + 0] = (i >> 1) + 0x20; + blocks [i + 1] = (i >> 1) + 0x00; + } + for (i = 0; i < 0x80; i += 2) + { + blocks [i + 0x40] = (i >> 1) + 0x80; + blocks [i + 0x41] = (i >> 1) + 0x40; + } + LoROM = FALSE; + HiROM = TRUE; + } + else + if (Settings.ForceInterleaved2) + { + for (i = 0; i < nblocks * 2; i++) + { + blocks [i] = (i & ~0x1e) | ((i & 2) << 2) | ((i & 4) << 2) | + ((i & 8) >> 2) | ((i & 16) >> 2); + } + } + else + { + bool8_32 t = LoROM; + + LoROM = HiROM; + HiROM = t; + + for (i = 0; i < nblocks; i++) + { + blocks [i * 2] = i + nblocks; + blocks [i * 2 + 1] = i; + } + } + + uint8 *tmp = (uint8 *) malloc (0x8000); + if (tmp) + { + for (i = 0; i < nblocks * 2; i++) + { + for (int j = i; j < nblocks * 2; j++) + { + if (blocks [j] == i) + { + memmove (tmp, &ROM [blocks [j] * 0x8000], 0x8000); + memmove (&ROM [blocks [j] * 0x8000], + &ROM [blocks [i] * 0x8000], 0x8000); + memmove (&ROM [blocks [i] * 0x8000], tmp, 0x8000); + uint8 b = blocks [j]; + blocks [j] = blocks [i]; + blocks [i] = b; + break; + } + } + } + free ((char *) tmp); + } + + hi_score = ScoreHiROM (FALSE); + lo_score = ScoreLoROM (FALSE); + + if ((HiROM && + (lo_score >= hi_score || hi_score < 0)) || + (LoROM && + (hi_score > lo_score || lo_score < 0))) + { + if (retry_count == 0) + { + S9xMessage (S9X_INFO, S9X_ROM_CONFUSING_FORMAT_INFO, + "ROM lied about its type! Trying again."); + Settings.ForceNotInterleaved = TRUE; + Settings.ForceInterleaved = FALSE; + retry_count++; + goto again; + } + } + } + FreeSDD1Data (); + InitROM (Tales); + + S9xLoadCheatFile (S9xGetFilename(".cht")); + S9xInitCheatData (); + S9xApplyCheats (); + + S9xReset (); + + return (TRUE); +} + +void S9xDeinterleaveMode2 () +{ + S9xMessage (S9X_INFO, S9X_ROM_INTERLEAVED_INFO, + "ROM image is in interleaved format - converting..."); + + int nblocks = Memory.CalculatedSize >> 15; + int step = 64; + + while (nblocks <= step) + step >>= 1; + + nblocks = step; + uint8 blocks [256]; + int i; + + for (i = 0; i < nblocks * 2; i++) + { + blocks [i] = (i & ~0x1e) | ((i & 2) << 2) | ((i & 4) << 2) | + ((i & 8) >> 2) | ((i & 16) >> 2); + } + + uint8 *tmp = (uint8 *) malloc (0x8000); + + if (tmp) + { + for (i = 0; i < nblocks * 2; i++) + { + for (int j = i; j < nblocks * 2; j++) + { + if (blocks [j] == i) + { + memmove (tmp, &Memory.ROM [blocks [j] * 0x8000], 0x8000); + memmove (&Memory.ROM [blocks [j] * 0x8000], + &Memory.ROM [blocks [i] * 0x8000], 0x8000); + memmove (&Memory.ROM [blocks [i] * 0x8000], tmp, 0x8000); + uint8 b = blocks [j]; + blocks [j] = blocks [i]; + blocks [i] = b; + break; + } + } + } + free ((char *) tmp); + } + Memory.InitROM (FALSE); + S9xReset (); +} + +void CMemory::InitROM (bool8_32 Interleaved) +{ +#ifndef ZSNES_FX + SuperFX.nRomBanks = CalculatedSize >> 15; +#endif + Settings.MultiPlayer5Master = Settings.MultiPlayer5; + Settings.MouseMaster = Settings.Mouse; + Settings.SuperScopeMaster = Settings.SuperScope; + Settings.DSP1Master = Settings.ForceDSP1; + Settings.SuperFX = FALSE; + Settings.SA1 = FALSE; + Settings.C4 = FALSE; + Settings.SDD1 = FALSE; + Settings.SRTC = FALSE; + + ZeroMemory (BlockIsRAM, MEMMAP_NUM_BLOCKS); + ZeroMemory (BlockIsROM, MEMMAP_NUM_BLOCKS); + + ::SRAM = SRAM; + memset (ROMId, 0, 5); + memset (CompanyId, 0, 3); + + if (Memory.HiROM) + { + Memory.SRAMSize = ROM [0xffd8]; + strncpy (ROMName, (char *) &ROM[0xffc0], ROM_NAME_LEN - 1); + ROMSpeed = ROM [0xffd5]; + ROMType = ROM [0xffd6]; + ROMSize = ROM [0xffd7]; + ROMChecksum = ROM [0xffde] + (ROM [0xffdf] << 8); + ROMComplementChecksum = ROM [0xffdc] + (ROM [0xffdd] << 8); + + memmove (ROMId, &ROM [0xffb2], 4); + memmove (CompanyId, &ROM [0xffb0], 2); + + // Try to auto-detect the DSP1 chip + if (!Settings.ForceNoDSP1 && + (ROMType & 0xf) >= 3 && (ROMType & 0xf0) == 0) + Settings.DSP1Master = TRUE; + + Settings.SDD1 = Settings.ForceSDD1; + if ((ROMType & 0xf0) == 0x40) + Settings.SDD1 = !Settings.ForceNoSDD1; + + if (Settings.BS) + BSHiROMMap (); + else + if ((ROMSpeed & ~0x10) == 0x25) + TalesROMMap (Interleaved); + else + if ((ROMSpeed & ~0x10) == 0x22 && + strncmp (ROMName, "Super Street Fighter", 20) != 0) + { + AlphaROMMap (); + } + else + HiROMMap (); + } + else + { + Memory.HiROM = FALSE; + Memory.SRAMSize = ROM [0x7fd8]; + ROMSpeed = ROM [0x7fd5]; + ROMType = ROM [0x7fd6]; + ROMSize = ROM [0x7fd7]; + ROMChecksum = ROM [0x7fde] + (ROM [0x7fdf] << 8); + ROMComplementChecksum = ROM [0x7fdc] + (ROM [0x7fdd] << 8); + memmove (ROMId, &ROM [0x7fb2], 4); + memmove (CompanyId, &ROM [0x7fb0], 2); + + strncpy (ROMName, (char *) &ROM[0x7fc0], ROM_NAME_LEN - 1); + Settings.SuperFX = Settings.ForceSuperFX; + + if ((ROMType & 0xf0) == 0x10) + Settings.SuperFX = !Settings.ForceNoSuperFX; + + // Try to auto-detect the DSP1 chip + if (!Settings.ForceNoDSP1 && + (ROMType & 0xf) >= 3 && (ROMType & 0xf0) == 0) + Settings.DSP1Master = TRUE; + + Settings.SDD1 = Settings.ForceSDD1; + if ((ROMType & 0xf0) == 0x40) + Settings.SDD1 = !Settings.ForceNoSDD1; + + if (Settings.SDD1) + S9xLoadSDD1Data (); + + Settings.C4 = Settings.ForceC4; + if ((ROMType & 0xf0) == 0xf0 && + (strncmp (ROMName, "MEGAMAN X", 9) == 0 || + strncmp (ROMName, "ROCKMAN X", 9) == 0)) + { + Settings.C4 = !Settings.ForceNoC4; + } + + if (Settings.SuperFX) + { + //::SRAM = ROM + 1024 * 1024 * 4; + SuperFXROMMap (); + Settings.MultiPlayer5Master = FALSE; + //Settings.MouseMaster = FALSE; + //Settings.SuperScopeMaster = FALSE; + Settings.DSP1Master = FALSE; + Settings.SA1 = FALSE; + Settings.C4 = FALSE; + Settings.SDD1 = FALSE; + } + else + if (Settings.ForceSA1 || + (!Settings.ForceNoSA1 && (ROMSpeed & ~0x10) == 0x23 && + (ROMType & 0xf) > 3 && (ROMType & 0xf0) == 0x30)) + { + Settings.SA1 = TRUE; + Settings.MultiPlayer5Master = FALSE; + //Settings.MouseMaster = FALSE; + //Settings.SuperScopeMaster = FALSE; + Settings.DSP1Master = FALSE; + Settings.C4 = FALSE; + Settings.SDD1 = FALSE; + SA1ROMMap (); + } + else + if ((ROMSpeed & ~0x10) == 0x25) + TalesROMMap (Interleaved); + else + if (strncmp ((char *) &Memory.ROM [0x7fc0], "SOUND NOVEL-TCOOL", 17) == 0 || + strncmp ((char *) &Memory.ROM [0x7fc0], "DERBY STALLION 96", 17) == 0) + { + LoROM24MBSMap (); + Settings.DSP1Master = FALSE; + } + else + if (strncmp ((char *) &Memory.ROM [0x7fc0], "THOROUGHBRED BREEDER3", 21) == 0 || + strncmp ((char *) &Memory.ROM [0x7fc0], "RPG-TCOOL 2", 11) == 0) + { + SRAM512KLoROMMap (); + Settings.DSP1Master = FALSE; + } + else + if (strncmp ((char *) &Memory.ROM [0x7fc0], "DEZAEMON ", 10) == 0) + { + Settings.DSP1Master = FALSE; + SRAM1024KLoROMMap (); + } + else + if (strncmp ((char *) &Memory.ROM [0x7fc0], "ADD-ON BASE CASSETE", 19) == 0) + { + Settings.MultiPlayer5Master = FALSE; + Settings.MouseMaster = FALSE; + Settings.SuperScopeMaster = FALSE; + Settings.DSP1Master = FALSE; + SufamiTurboLoROMMap(); + Memory.SRAMSize = 3; + } + else + if ((ROMSpeed & ~0x10) == 0x22 && + strncmp (ROMName, "Super Street Fighter", 20) != 0) + { + AlphaROMMap (); + } + else + LoROMMap (); + } + + int power2 = 0; + int size = CalculatedSize; + + while (size >>= 1) + power2++; + + size = 1 << power2; + uint32 remainder = CalculatedSize - size; + + uint32 sum1 = 0; + uint32 sum2 = 0; + + int i; + + for (i = 0; i < size; i++) + sum1 += ROM [i]; + + for (i = 0; i < (int) remainder; i++) + sum2 += ROM [size + i]; + + if (remainder) + { + //for Tengai makyou + if (CalculatedSize == 0x500000 && Memory.HiROM && + strncmp ((const char *)&ROM[0xffb0], "18AZ", 4) == 0 && + !memcmp(&ROM[0xffd5], "\x3a\xf9\x0d\x03\x00\x33\x00", 7)) + sum1 += sum2; + else + sum1 += sum2 * (size / remainder); + } + + sum1 &= 0xffff; + + CalculatedChecksum = caCRC32(&ROM[0], CalculatedSize); + if (Settings.ForceNTSC) + Settings.PAL = FALSE; + else + if (Settings.ForcePAL) + Settings.PAL = TRUE; + else + if (Memory.HiROM) + // Country code + Settings.PAL = ROM [0xffd9] >= 2; + else + Settings.PAL = ROM [0x7fd9] >= 2; + + if (Settings.PAL) + { + Settings.FrameTime = Settings.FrameTimePAL; + Memory.ROMFramesPerSecond = 50; + } + else + { + Settings.FrameTime = Settings.FrameTimeNTSC; + Memory.ROMFramesPerSecond = 60; + } + + ROMName[ROM_NAME_LEN - 1] = 0; + if (strlen (ROMName)) + { + char *p = ROMName + strlen (ROMName) - 1; + + while (p > ROMName && *(p - 1) == ' ') + p--; + *p = 0; + } + + if (Settings.SuperFX) + { + CPU.Memory_SRAMMask = 0xffff; + Memory.SRAMSize = 16; + } + else + { + CPU.Memory_SRAMMask = Memory.SRAMSize ? + ((1 << (Memory.SRAMSize + 3)) * 128) - 1 : 0; + } + + IAPU.OneCycle = ONE_APU_CYCLE; + Settings.Shutdown = Settings.ShutdownMaster; + + SetDSP = &DSP1SetByte; + GetDSP = &DSP1GetByte; + + ApplyROMFixes (); + sprintf (ROMName, "%s", Safe (ROMName)); + sprintf (ROMId, "%s", Safe (ROMId)); + sprintf (CompanyId, "%s", Safe (CompanyId)); + + sprintf (String, "\"%s\" [%s] %s, %s, Type: %s, Mode: %s, TV: %s, S-RAM: %s, ROMId: %s Company: %2.2s", + ROMName, + (ROMChecksum + ROMComplementChecksum != 0xffff || + ROMChecksum != sum1) ? "bad checksum" : "checksum ok", + MapType (), + Size (), + KartContents (), + MapMode (), + TVStandard (), + StaticRAMSize (), + ROMId, + CompanyId); + + S9xMessage (S9X_INFO, S9X_ROM_INFO, String); +} + +bool8_32 CMemory::LoadSRAM (const char *filename) +{ + int size = Memory.SRAMSize ? + (1 << (Memory.SRAMSize + 3)) * 128 : 0; + + memset (SRAM, SNESGameFixes.SRAMInitialValue, 0x20000); + + if (size > 0x20000) + size = 0x20000; + + if (size) + { + FILE *file; + if ((file = fopen(filename, "rb"))) + { + int len = fread ((char*) ::SRAM, 1, 0x20000, file); + fclose (file); + if (len - size == 512) + { + // S-RAM file has a header - remove it + memmove (::SRAM, ::SRAM + 512, size); + } + if (len == size + SRTC_SRAM_PAD) + { + S9xSRTCPostLoadState (); + S9xResetSRTC (); + rtc.index = -1; + rtc.mode = MODE_READ; + } + else + S9xHardResetSRTC (); + + return (TRUE); + } + S9xHardResetSRTC (); + return (FALSE); + } + + return (TRUE); +} + +bool8_32 CMemory::SaveSRAM (const char *filename) +{ + int size = Memory.SRAMSize ? + (1 << (Memory.SRAMSize + 3)) * 128 : 0; + if (Settings.SRTC) + { + size += SRTC_SRAM_PAD; + S9xSRTCPreSaveState (); + } + + + if (size > 0x20000) + size = 0x20000; + + if (size && *Memory.ROMFilename) + { + FILE *file; + if ((file = fopen (filename, "wb"))) + { + fwrite ((char *) ::SRAM, size, 1, file); + fclose (file); + sync(); +#if defined(__linux) + chown (filename, getuid (), getgid ()); +#endif + return (TRUE); + } + } + return (FALSE); +} + +void CMemory::FixROMSpeed () +{ + int c; + + for (c = 0x800; c < 0x1000; c++) + { + if (BlockIsROM [c]) + MemorySpeed [c] = (uint8) CPU.FastROMSpeed; + } +} + +void CMemory::WriteProtectROM () +{ + memmove ((void *) WriteMap, (void *) Map, sizeof (Map)); + for (int c = 0; c < 0x1000; c++) + { + if (BlockIsROM [c]) + WriteMap [c] = (uint8 *) MAP_NONE; + } +} + +void CMemory::MapRAM () +{ + int c; + + // Banks 7e->7f, RAM + for (c = 0; c < 16; c++) + { + Map [c + 0x7e0] = RAM; + Map [c + 0x7f0] = RAM + 0x10000; + BlockIsRAM [c + 0x7e0] = TRUE; + BlockIsRAM [c + 0x7f0] = TRUE; + BlockIsROM [c + 0x7e0] = FALSE; + BlockIsROM [c + 0x7f0] = FALSE; + } + + // Banks 70->77, S-RAM + for (c = 0; c < 0x80; c++) + { + Map [c + 0x700] = (uint8 *) MAP_LOROM_SRAM; + BlockIsRAM [c + 0x700] = TRUE; + BlockIsROM [c + 0x700] = FALSE; + } +} + +void CMemory::MapExtraRAM () +{ + int c; + + // Banks 7e->7f, RAM + for (c = 0; c < 16; c++) + { + Map [c + 0x7e0] = RAM; + Map [c + 0x7f0] = RAM + 0x10000; + BlockIsRAM [c + 0x7e0] = TRUE; + BlockIsRAM [c + 0x7f0] = TRUE; + BlockIsROM [c + 0x7e0] = FALSE; + BlockIsROM [c + 0x7f0] = FALSE; + } + + // Banks 70->73, S-RAM + for (c = 0; c < 16; c++) + { + Map [c + 0x700] = ::SRAM; + Map [c + 0x710] = ::SRAM + 0x8000; + Map [c + 0x720] = ::SRAM + 0x10000; + Map [c + 0x730] = ::SRAM + 0x18000; + + BlockIsRAM [c + 0x700] = TRUE; + BlockIsROM [c + 0x700] = FALSE; + BlockIsRAM [c + 0x710] = TRUE; + BlockIsROM [c + 0x710] = FALSE; + BlockIsRAM [c + 0x720] = TRUE; + BlockIsROM [c + 0x720] = FALSE; + BlockIsRAM [c + 0x730] = TRUE; + BlockIsROM [c + 0x730] = FALSE; + } +} + +void CMemory::LoROMMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; + if (Settings.DSP1Master) + { + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_DSP; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_DSP; + } + else + if (Settings.C4) + { + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_C4; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_C4; + } + else + { + Map [c + 6] = Map [c + 0x806] = (uint8 *) bytes0x2000 - 0x6000; + Map [c + 7] = Map [c + 0x807] = (uint8 *) bytes0x2000 - 0x6000; + } + + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = &ROM [(c << 11) % CalculatedSize] - 0x8000; + BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + if (Settings.DSP1Master) + { + // Banks 30->3f and b0->bf + for (c = 0x300; c < 0x400; c += 16) + { + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = (uint8 *) MAP_DSP; + BlockIsROM [i] = BlockIsROM [i + 0x800] = FALSE; + } + } + } + + // Banks 40->7f and c0->ff + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 8; i++) + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 11) % CalculatedSize]; + + for (i = c + 8; i < c + 16; i++) + Map [i + 0x400] = Map [i + 0xc00] = &ROM [((c << 11) + 0x200000) % CalculatedSize - 0x8000]; + + for (i = c; i < c + 16; i++) + { + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; + } + } + + if (Settings.DSP1Master) + { + for (c = 0; c < 0x100; c++) + { + Map [c + 0xe00] = (uint8 *) MAP_DSP; + MemorySpeed [c + 0xe00] = SLOW_ONE_CYCLE; + BlockIsROM [c + 0xe00] = FALSE; + } + } + MapRAM (); + WriteProtectROM (); +} + +void CMemory::HiROMMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; + if (Settings.DSP1Master) + { + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_DSP; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_DSP; + } + else + { + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; + } + + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = &ROM [(c << 12) % CalculatedSize]; + BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + // Banks 30->3f and b0->bf, address ranges 6000->7fff is S-RAM. + for (c = 0; c < 16; c++) + { + Map [0x306 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; + Map [0x307 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; + Map [0xb06 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; + Map [0xb07 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; + BlockIsRAM [0x306 + (c << 4)] = TRUE; + BlockIsRAM [0x307 + (c << 4)] = TRUE; + BlockIsRAM [0xb06 + (c << 4)] = TRUE; + BlockIsRAM [0xb07 + (c << 4)] = TRUE; + } + + // Banks 40->7f and c0->ff + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 16; i++) + { + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 12) % CalculatedSize]; + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; + } + } + + MapRAM (); + WriteProtectROM (); +} + +void CMemory::TalesROMMap (bool8_32 Interleaved) +{ + int c; + int i; + + uint32 OFFSET0 = 0x400000; + uint32 OFFSET1 = 0x400000; + uint32 OFFSET2 = 0x000000; + + if (Interleaved) + { + OFFSET0 = 0x000000; + OFFSET1 = 0x000000; + OFFSET2 = 0x200000; + } + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; + for (i = c + 8; i < c + 16; i++) + { + Map [i] = &ROM [((c << 12) + OFFSET0) % CalculatedSize]; + Map [i + 0x800] = &ROM [((c << 12) + OFFSET0) % CalculatedSize]; + BlockIsROM [i] = TRUE; + BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + // Banks 30->3f and b0->bf, address ranges 6000->7ffff is S-RAM. + for (c = 0; c < 16; c++) + { + Map [0x306 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; + Map [0x307 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; + Map [0xb06 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; + Map [0xb07 + (c << 4)] = (uint8 *) MAP_HIROM_SRAM; + BlockIsRAM [0x306 + (c << 4)] = TRUE; + BlockIsRAM [0x307 + (c << 4)] = TRUE; + BlockIsRAM [0xb06 + (c << 4)] = TRUE; + BlockIsRAM [0xb07 + (c << 4)] = TRUE; + } + + // Banks 40->7f and c0->ff + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 8; i++) + { + Map [i + 0x400] = &ROM [((c << 12) + OFFSET1) % CalculatedSize]; + Map [i + 0x408] = &ROM [((c << 12) + OFFSET1) % CalculatedSize]; + Map [i + 0xc00] = &ROM [((c << 12) + OFFSET2) % CalculatedSize]; + Map [i + 0xc08] = &ROM [((c << 12) + OFFSET2) % CalculatedSize]; + BlockIsROM [i + 0x400] = TRUE; + BlockIsROM [i + 0x408] = TRUE; + BlockIsROM [i + 0xc00] = TRUE; + BlockIsROM [i + 0xc08] = TRUE; + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + MemorySpeed [i + 0x408] = MemorySpeed [i + 0xc08] = SLOW_ONE_CYCLE; + } + } + MapRAM (); + WriteProtectROM (); +} + +void CMemory::AlphaROMMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_DSP; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_DSP; + + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; + BlockIsROM [i] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + // Banks 40->7f and c0->ff + + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 16; i++) + { + Map [i + 0x400] = &ROM [(c << 12) % CalculatedSize]; + Map [i + 0xc00] = &ROM [(c << 12) % CalculatedSize]; + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; + } + } + + MapRAM (); + WriteProtectROM (); +} + +void CMemory::SuperFXROMMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_DSP; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_DSP; + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; + BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 8; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + // Banks 40->7f and c0->ff + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 16; i++) + { + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 12) % CalculatedSize]; + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; + } + } + + // Banks 7e->7f, RAM + for (c = 0; c < 16; c++) + { + Map [c + 0x7e0] = RAM; + Map [c + 0x7f0] = RAM + 0x10000; + BlockIsRAM [c + 0x7e0] = TRUE; + BlockIsRAM [c + 0x7f0] = TRUE; + BlockIsROM [c + 0x7e0] = FALSE; + BlockIsROM [c + 0x7f0] = FALSE; + } + + // Banks 70->71, S-RAM + for (c = 0; c < 32; c++) + { + Map [c + 0x700] = ::SRAM + (((c >> 4) & 1) << 16); + BlockIsRAM [c + 0x700] = TRUE; + BlockIsROM [c + 0x700] = FALSE; + } + + // Banks 00->3f and 80->bf address ranges 6000->7fff is RAM. + for (c = 0; c < 0x40; c++) + { + Map [0x006 + (c << 4)] = (uint8 *) ::SRAM - 0x6000; + Map [0x007 + (c << 4)] = (uint8 *) ::SRAM - 0x6000; + Map [0x806 + (c << 4)] = (uint8 *) ::SRAM - 0x6000; + Map [0x807 + (c << 4)] = (uint8 *) ::SRAM - 0x6000; + BlockIsRAM [0x006 + (c << 4)] = TRUE; + BlockIsRAM [0x007 + (c << 4)] = TRUE; + BlockIsRAM [0x806 + (c << 4)] = TRUE; + BlockIsRAM [0x807 + (c << 4)] = TRUE; + } + // Replicate the first 2Mb of the ROM at ROM + 2MB such that each 32K + // block is repeated twice in each 64K block. + for (c = 0; c < 64; c++) + { + memmove (&ROM [0x200000 + c * 0x10000], &ROM [c * 0x8000], 0x8000); + memmove (&ROM [0x208000 + c * 0x10000], &ROM [c * 0x8000], 0x8000); + } + + WriteProtectROM (); +} + +void CMemory::SA1ROMMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) &Memory.FillRAM [0x3000] - 0x3000; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_BWRAM; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_BWRAM; + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; + BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + // Banks 40->7f + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 16; i++) + Map [i + 0x400] = (uint8 *) &SRAM [(c << 12) & 0x1ffff]; + + for (i = c; i < c + 16; i++) + { + MemorySpeed [i + 0x400] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0x400] = FALSE; + } + } + + // c0->ff + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 16; i++) + { + Map [i + 0xc00] = &ROM [(c << 12) % CalculatedSize]; + MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0xc00] = TRUE; + } + } + + for (c = 0; c < 16; c++) + { + Map [c + 0x7e0] = RAM; + Map [c + 0x7f0] = RAM + 0x10000; + BlockIsRAM [c + 0x7e0] = TRUE; + BlockIsRAM [c + 0x7f0] = TRUE; + BlockIsROM [c + 0x7e0] = FALSE; + BlockIsROM [c + 0x7f0] = FALSE; + } + WriteProtectROM (); + +#ifdef USE_SA1 + // Now copy the map and correct it for the SA1 CPU. + memmove ((void *) SA1_WriteMap, (void *) WriteMap, sizeof (WriteMap)); + memmove ((void *) SA1_Map, (void *) Map, sizeof (Map)); + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + SA1_Map [c + 0] = SA1_Map [c + 0x800] = &Memory.FillRAM [0x3000]; + SA1_Map [c + 1] = SA1_Map [c + 0x801] = (uint8 *) MAP_NONE; + SA1_WriteMap [c + 0] = SA1_WriteMap [c + 0x800] = &Memory.FillRAM [0x3000]; + SA1_WriteMap [c + 1] = SA1_WriteMap [c + 0x801] = (uint8 *) MAP_NONE; + } + + // Banks 60->6f + for (c = 0; c < 0x100; c++) + SA1_Map [c + 0x600] = SA1_WriteMap [c + 0x600] = (uint8 *) MAP_BWRAM_BITMAP; +#endif // USE_SA1 + + BWRAM = SRAM; +} + +void CMemory::LoROM24MBSMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; + + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; + BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x200; c += 16) + { + Map [c + 0x800] = RAM; + Map [c + 0x801] = RAM; + BlockIsRAM [c + 0x800] = TRUE; + BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 0x805] = (uint8 *) MAP_CPU; + Map [c + 0x806] = (uint8 *) MAP_NONE; + Map [c + 0x807] = (uint8 *) MAP_NONE; + + for (i = c + 8; i < c + 16; i++) + { + Map [i + 0x800] = &ROM [c << 11] - 0x8000 + 0x200000; + BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + // Banks 40->7f and c0->ff + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 8; i++) + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 11) + 0x200000]; + + for (i = c + 8; i < c + 16; i++) + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 11) + 0x200000 - 0x8000]; + + for (i = c; i < c + 16; i++) + { + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; + } + } + + MapExtraRAM (); + WriteProtectROM (); +} + +void CMemory::SufamiTurboLoROMMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; + if (Settings.DSP1Master) + { + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_DSP; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_DSP; + } + else + { + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; + } + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; + BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + if (Settings.DSP1Master) + { + // Banks 30->3f and b0->bf + for (c = 0x300; c < 0x400; c += 16) + { + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = (uint8 *) MAP_DSP; + BlockIsROM [i] = BlockIsROM [i + 0x800] = FALSE; + } + } + } + + // Banks 40->7f and c0->ff + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 8; i++) + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 11) + 0x200000]; + + for (i = c + 8; i < c + 16; i++) + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 11) + 0x200000 - 0x8000]; + + for (i = c; i < c + 16; i++) + { + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; + } + } + + if (Settings.DSP1Master) + { + for (c = 0; c < 0x100; c++) + { + Map [c + 0xe00] = (uint8 *) MAP_DSP; + MemorySpeed [c + 0xe00] = SLOW_ONE_CYCLE; + BlockIsROM [c + 0xe00] = FALSE; + } + } + + // Banks 7e->7f, RAM + for (c = 0; c < 16; c++) + { + Map [c + 0x7e0] = RAM; + Map [c + 0x7f0] = RAM + 0x10000; + BlockIsRAM [c + 0x7e0] = TRUE; + BlockIsRAM [c + 0x7f0] = TRUE; + BlockIsROM [c + 0x7e0] = FALSE; + BlockIsROM [c + 0x7f0] = FALSE; + } + + // Banks 60->67, S-RAM + for (c = 0; c < 0x80; c++) + { + Map [c + 0x600] = (uint8 *) MAP_LOROM_SRAM; + BlockIsRAM [c + 0x600] = TRUE; + BlockIsROM [c + 0x600] = FALSE; + } + + WriteProtectROM (); +} + +void CMemory::SRAM512KLoROMMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = (uint8 *) MAP_CPU; + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; + + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = &ROM [c << 11] - 0x8000; + BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + // Banks 40->7f and c0->ff + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 8; i++) + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 11) + 0x200000]; + + for (i = c + 8; i < c + 16; i++) + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 11) + 0x200000 - 0x8000]; + + for (i = c; i < c + 16; i++) + { + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; + + + } + } + + MapExtraRAM (); + WriteProtectROM (); +} + +void CMemory::SRAM1024KLoROMMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = Map [c + 0x400] = Map [c + 0xc00] = RAM; + Map [c + 1] = Map [c + 0x801] = Map [c + 0x401] = Map [c + 0xc01] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = BlockIsRAM [c + 0x400] = BlockIsRAM [c + 0xc00] = TRUE; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = BlockIsRAM [c + 0x401] = BlockIsRAM [c + 0xc01] = TRUE; + + Map [c + 2] = Map [c + 0x802] = Map [c + 0x402] = Map [c + 0xc02] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = Map [c + 0x403] = Map [c + 0xc03] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = Map [c + 0x404] = Map [c + 0xc04] = (uint8 *) MAP_CPU; + Map [c + 5] = Map [c + 0x805] = Map [c + 0x405] = Map [c + 0xc05] = (uint8 *) MAP_CPU; + Map [c + 6] = Map [c + 0x806] = Map [c + 0x406] = Map [c + 0xc06] = (uint8 *) MAP_NONE; + Map [c + 7] = Map [c + 0x807] = Map [c + 0x407] = Map [c + 0xc07] = (uint8 *) MAP_NONE; + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = Map [i + 0x400] = Map [i + 0xc00] = &ROM [c << 11] - 0x8000; + BlockIsROM [i] = BlockIsROM [i + 0x800] = BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = MemorySpeed [i + 0x800] = + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + MapExtraRAM (); + WriteProtectROM (); +} + +void CMemory::BSHiROMMap () +{ + int c; + int i; + + // Banks 00->3f and 80->bf + for (c = 0; c < 0x400; c += 16) + { + Map [c + 0] = Map [c + 0x800] = RAM; + BlockIsRAM [c + 0] = BlockIsRAM [c + 0x800] = TRUE; + Map [c + 1] = Map [c + 0x801] = RAM; + BlockIsRAM [c + 1] = BlockIsRAM [c + 0x801] = TRUE; + + Map [c + 2] = Map [c + 0x802] = (uint8 *) MAP_PPU; + Map [c + 3] = Map [c + 0x803] = (uint8 *) MAP_PPU; + Map [c + 4] = Map [c + 0x804] = (uint8 *) MAP_CPU; + // XXX: How large is SRAM?? + Map [c + 5] = Map [c + 0x805] = (uint8 *) SRAM; + BlockIsRAM [c + 5] = BlockIsRAM [c + 0x805] = TRUE; + Map [c + 6] = Map [c + 0x806] = (uint8 *) MAP_NONE; + Map [c + 7] = Map [c + 0x807] = (uint8 *) MAP_NONE; + + for (i = c + 8; i < c + 16; i++) + { + Map [i] = Map [i + 0x800] = &ROM [(c << 12) % CalculatedSize]; + BlockIsROM [i] = BlockIsROM [i + 0x800] = TRUE; + } + + for (i = c; i < c + 16; i++) + { + int ppu = i & 15; + + MemorySpeed [i] = + MemorySpeed [i + 0x800] = ppu >= 2 && ppu <= 3 ? ONE_CYCLE : SLOW_ONE_CYCLE; + } + } + + // Banks 60->7d offset 0000->7fff & 60->7f offset 8000->ffff PSRAM + // XXX: How large is PSRAM? + for (c = 0x600; c < 0x7e0; c += 16) + { + for (i = c; i < c + 8; i++) + { + Map [i] = &ROM [0x400000 + (c << 11)]; + BlockIsRAM [i] = TRUE; + } + for (i = c + 8; i < c + 16; i++) + { + Map [i] = &ROM [0x400000 + (c << 11) - 0x8000]; + BlockIsRAM [i] = TRUE; + } + } + + // Banks 40->7f and c0->ff + for (c = 0; c < 0x400; c += 16) + { + for (i = c; i < c + 16; i++) + { + Map [i + 0x400] = Map [i + 0xc00] = &ROM [(c << 12) % CalculatedSize]; + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = SLOW_ONE_CYCLE; + BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = TRUE; + } + } + + MapRAM (); + WriteProtectROM (); +} + +const char *CMemory::TVStandard () +{ + return (Settings.PAL ? "PAL" : "NTSC"); +} + +const char *CMemory::Speed () +{ + return (ROMSpeed & 0x10 ? "120ns" : "200ns"); +} + +const char *CMemory::MapType () +{ + return (HiROM ? "HiROM" : "LoROM"); +} + +const char *CMemory::StaticRAMSize () +{ + static char tmp [20]; + + if (Memory.SRAMSize > 16) + return ("Corrupt"); + sprintf (tmp, "%dKb", (CPU.Memory_SRAMMask + 1) / 1024); + return (tmp); +} + +const char *CMemory::Size () +{ + static char tmp [20]; + + if (ROMSize < 7 || ROMSize - 7 > 23) + return ("Corrupt"); + sprintf (tmp, "%dMbits", 1 << (ROMSize - 7)); + return (tmp); +} + +const char *CMemory::KartContents () +{ + static char tmp [30]; + static const char *CoPro [16] = { + "DSP1", "SuperFX", "OBC1", "SA-1", "S-DD1", "S-RTC", "CoPro#6", + "CoPro#7", "CoPro#8", "CoPro#9", "CoPro#10", "CoPro#11", "CoPro#12", + "CoPro#13", "CoPro#14", "CoPro-Custom" + }; + static const char *Contents [3] = { + "ROM", "ROM+RAM", "ROM+RAM+BAT" + }; + if (ROMType == 0) + return ("ROM only"); + + sprintf (tmp, "%s", Contents [(ROMType & 0xf) % 3]); + + if ((ROMType & 0xf) >= 3) + sprintf (tmp, "%s+%s", tmp, CoPro [(ROMType & 0xf0) >> 4]); + + return (tmp); +} + +const char *CMemory::MapMode () +{ + static char tmp [4]; + sprintf (tmp, "%02x", ROMSpeed & ~0x10); + return (tmp); +} + +const char *CMemory::ROMID () +{ + return (ROMId); +} + +void CMemory::ApplyROMFixes () +{ + ROMAPUEnabled = 0; + DSP1.version = 0; + //Settings.HBlankStart = (256 * Settings.H_Max) / SNES_HCOUNTER_MAX; + if (strncmp(ROMName, "DUNGEON MASTER", 14) == 0) + { + DSP1.version = 1; + SetDSP=&DSP2SetByte; + GetDSP=&DSP2GetByte; + } + + //OAM hacks because we don't fully understand the + //behavior of the SNES. + + //possibly an RTO issue? + //part of Fred's club is drawn over his face. + if(strncmp(ROMName, "THE FLINTSTONES TTOSM", 21)==0) + { + SNESGameFixes.Flintstones=true; + } + + if(strncmp(ROMName, "SUPER MARIO KART", 16)==0 + || strncmp(ROMName, "F-ZERO", 6)==0) + { + SNESGameFixes.Mode7Hack=true; + } + + //Totally wacky display... + //seems to need a disproven behavior, so + //we're definitely overlooking some other bug? + if(strncmp(ROMName, "UNIRACERS", 9)==0) + SNESGameFixes.Uniracers=true; + + // Enable S-RTC (Real Time Clock) emulation for Dai Kaijyu Monogatari 2 + Settings.SRTC = ((ROMType & 0xf0) >> 4) == 5; + + Settings.StrikeGunnerOffsetHack = strcmp (ROMName, "STRIKE GUNNER") == 0 ? 7 : 0; + + CPU.NMITriggerPoint = 4; + if (strcmp (ROMName, "CACOMA KNIGHT") == 0) + CPU.NMITriggerPoint = 25; + + // These games complain if the multi-player adaptor is 'connected' + if (strcmp (ROMName, "TETRIS&Dr.MARIO") == 0 || + strcmp (ROMName, "JIGSAW PARTY") == 0 || + strcmp (ROMName, "SUPER PICROSS") == 0 || + strcmp (ROMName, "KIRBY NO KIRA KIZZU") == 0 || + strcmp (ROMName, "BLOCK") == 0 || + strncmp (ROMName, "SUPER BOMBLISS", 14) == 0 || + strcmp (ROMId, "ABOJ") == 0) + { + Settings.MultiPlayer5Master = FALSE; + Settings.MouseMaster = FALSE; + Settings.SuperScopeMaster = FALSE; + } + + // Games which spool sound samples between the SNES and sound CPU using + // H-DMA as the sample is playing. + if (strcmp (ROMName, "EARTHWORM JIM 2") == 0 || + strcmp (ROMName, "PRIMAL RAGE") == 0 || + strcmp (ROMName, "CLAY FIGHTER") == 0 || + strcmp (ROMName, "ClayFighter 2") == 0 || + strncasecmp (ROMName, "MADDEN", 6) == 0 || + strncmp (ROMName, "NHL", 3) == 0 || + strcmp (ROMName, "WEAPONLORD") == 0) + { + Settings.Shutdown = FALSE; + } + + + // Stunt Racer FX + if (strcmp (ROMId, "CQ ") == 0 || + // Illusion of Gaia + strncmp (ROMId, "JG", 2) == 0 || + strcmp (ROMName, "GAIA GENSOUKI 1 JPN") == 0) + { + IAPU.OneCycle = 13; + ROMAPUEnabled |= 2; + CPU.APU_APUExecuting |= 2; + } + + // RENDERING RANGER R2 + if (strcmp (ROMId, "AVCJ") == 0 || + // Star Ocean + strncmp (ROMId, "ARF", 3) == 0 || + // Tales of Phantasia + strncmp (ROMId, "ATV", 3) == 0 || + // Act Raiser 1 & 2 + strncasecmp (ROMName, "ACTRAISER", 9) == 0 || + strncasecmp (ROMName, "ActRaiser", 9) == 0 || // I kown both sentences are supposed to be equivalent each other but they aren't on my compiler + // Soulblazer + strcmp (ROMName, "SOULBLAZER - 1 USA") == 0 || + strcmp (ROMName, "SOULBLADER - 1") == 0 || + strncmp (ROMName, "SOULBLAZER 1",12) == 0 || + // Terranigma + strncmp (ROMId, "AQT", 3) == 0 || + // Robotrek + strncmp (ROMId, "E9 ", 3) == 0 || + strcmp (ROMName, "SLAP STICK 1 JPN") == 0 || + // ZENNIHON PURORESU2 + strncmp (ROMId, "APR", 3) == 0 || + // Bomberman 4 + strncmp (ROMId, "A4B", 3) == 0 || + // UFO KAMEN YAKISOBAN + strncmp (ROMId, "Y7 ", 3) == 0 || + strncmp (ROMId, "Y9 ", 3) == 0 || + // Panic Bomber World + strncmp (ROMId, "APB", 3) == 0 || + ((strncmp (ROMName, "Parlor", 6) == 0 || + strcmp (ROMName, "HEIWA PARLOR!MINI8") == 0 || + strncmp (ROMName, "SANKYO Fever! ̨°ÊÞ°!", 21) == 0) && + strcmp (CompanyId, "A0") == 0) || + strcmp (ROMName, "DARK KINGDOM") == 0 || + strcmp (ROMName, "ZAN3 SFC") == 0 || + strcmp (ROMName, "HIOUDEN") == 0 || + strcmp (ROMName, "ÃݼɳÀ") == 0 || + strcmp (ROMName, "FORTUNE QUEST") == 0 || + strcmp (ROMName, "FISHING TO BASSING") == 0 || + strncmp (ROMName, "TOKYODOME '95BATTLE 7", 21) == 0 || + strcmp (ROMName, "OHMONO BLACKBASS") == 0) + { + IAPU.OneCycle = 15; + // notaz: strangely enough, these games work properly with my hack enabled + if (strcmp (ROMId, "AVCJ") != 0) + ROMAPUEnabled |= 2; + CPU.APU_APUExecuting |= 2; + } + + if (strcmp (ROMName, "BATMAN--REVENGE JOKER") == 0) + { + Memory.HiROM = FALSE; + Memory.LoROM = TRUE; + LoROMMap (); + } + Settings.StarfoxHack = strcmp (ROMName, "STAR FOX") == 0 || + strcmp (ROMName, "STAR WING") == 0; + Settings.WinterGold = strcmp (ROMName, "FX SKIING NINTENDO 96") == 0 || + strcmp (ROMName, "DIRT RACER") == 0 || + strcmp (ROMName, "Stunt Race FX") == 0 || + Settings.StarfoxHack; + Settings.ChuckRock = strcmp (ROMName, "CHUCK ROCK") == 0; + Settings.Dezaemon = strcmp (ROMName, "DEZAEMON") == 0; + + if (strcmp (ROMName, "RADICAL DREAMERS") == 0 || + strcmp (ROMName, "TREASURE CONFLIX") == 0) + { + int c; + + for (c = 0; c < 0x80; c++) + { + Map [c + 0x700] = ROM + 0x200000 + 0x1000 * (c & 0xf0); + BlockIsRAM [c + 0x700] = TRUE; + BlockIsROM [c + 0x700] = FALSE; + } + for (c = 0; c < 0x400; c += 16) + { + Map [c + 5] = Map [c + 0x805] = ROM + 0x300000; + BlockIsRAM [c + 5] = BlockIsRAM [c + 0x805] = TRUE; + } + WriteProtectROM (); + } + + Settings.H_Max = (SNES_CYCLES_PER_SCANLINE * + Settings.CyclesPercentage) / 100; + + // A Couple of HDMA related hacks - Lantus + if ((strcmp(ROMName, "SFX SUPERBUTOUDEN2")==0) || + (strcmp(ROMName, "ALIEN vs. PREDATOR")==0) || + (strcmp(ROMName, "STONE PROTECTORS")==0) || + (strcmp(ROMName, "SUPER BATTLETANK 2")==0)) + Settings.H_Max = (SNES_CYCLES_PER_SCANLINE * 130) / 100; + + if (strcmp (ROMId, "ASRJ") == 0 && Settings.CyclesPercentage == 100) + // Street Racer + Settings.H_Max = (SNES_CYCLES_PER_SCANLINE * 95) / 100; + + // Power Rangers Fight + if (strncmp (ROMId, "A3R", 3) == 0 || + // Clock Tower + strncmp (ROMId, "AJE", 3) == 0) + Settings.H_Max = (SNES_CYCLES_PER_SCANLINE * 103) / 100; + + if (strcmp (ROMId, "AWVP") == 0 || strcmp (ROMId, "AWVE") == 0 || + strcmp (ROMId, "AWVJ") == 0) + { + // Wrestlemania Arcade +#if 0 + if (Settings.CyclesPercentage == 100) + Settings.H_Max = (SNES_CYCLES_PER_SCANLINE * 140) / 100; // Fixes sound +#endif + Settings.WrestlemaniaArcade = TRUE; + } + // Theme Park - disable offset-per-tile mode. + if (strcmp (ROMId, "ATQP") == 0) + Settings.WrestlemaniaArcade = TRUE; + + if (strncmp (ROMId, "A3M", 3) == 0 && Settings.CyclesPercentage == 100) + // Mortal Kombat 3. Fixes cut off speech sample + Settings.H_Max = (SNES_CYCLES_PER_SCANLINE * 110) / 100; + + if (strcmp (ROMName, "\x0bd\x0da\x0b2\x0d4\x0b0\x0bd\x0de") == 0 && + Settings.CyclesPercentage == 100) + Settings.H_Max = (SNES_CYCLES_PER_SCANLINE * 101) / 100; + + if (strcmp (ROMName, "WILD TRAX") == 0 || + strcmp (ROMName, "YOSSY'S ISLAND") == 0 || + strcmp (ROMName, "YOSHI'S ISLAND") == 0) + CPU.TriedInterleavedMode2 = TRUE; + + // Start Trek: Deep Sleep 9 + if (strncmp (ROMId, "A9D", 3) == 0 && Settings.CyclesPercentage == 100) + Settings.H_Max = (SNES_CYCLES_PER_SCANLINE * 110) / 100; + + Settings.APURAMInitialValue = 0xff; + + if (strcmp (ROMName, "·­³Ô¸¥Ò¶ÞÐÃݾ²") == 0 || + strcmp (ROMName, "KENTOUOU WORLDCHAMPIO") == 0 || + strcmp (ROMName, "TKO SUPERCHAMPIONSHIP") == 0 || + strcmp (ROMName, "TKO SUPER CHAMPIONSHI") == 0 || + strcmp (ROMName, "IHATOVO STORY") == 0 || + strcmp (ROMName, "WANDERERS FROM YS") == 0 || + strcmp (ROMName, "SUPER GENTYOUHISHI") == 0 || + // Panic Bomber World + strncmp (ROMId, "APB", 3) == 0) + { + Settings.APURAMInitialValue = 0; + } + + Settings.DaffyDuck = strcmp (ROMName, "DAFFY DUCK: MARV MISS") == 0; + Settings.HBlankStart = (256 * Settings.H_Max) / SNES_HCOUNTER_MAX; + +#ifdef USE_SA1 + SA1.WaitAddress = NULL; + SA1.WaitByteAddress1 = NULL; + SA1.WaitByteAddress2 = NULL; + + /* Bass Fishing */ + if (strcmp (ROMId, "ZBPJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x0093f1 >> MEMMAP_SHIFT] + 0x93f1; + SA1.WaitByteAddress1 = FillRAM + 0x304a; + } + /* DAISENRYAKU EXPERTWW2 */ + if (strcmp (ROMId, "AEVJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x0ed18d >> MEMMAP_SHIFT] + 0xd18d; + SA1.WaitByteAddress1 = FillRAM + 0x3000; + } + /* debjk2 */ + if (strcmp (ROMId, "A2DJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x008b62 >> MEMMAP_SHIFT] + 0x8b62; + } + /* Dragon Ballz HD */ + if (strcmp (ROMId, "AZIJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x008083 >> MEMMAP_SHIFT] + 0x8083; + SA1.WaitByteAddress1 = FillRAM + 0x3020; + } + /* SFC SDGUNDAMGNEXT */ + if (strcmp (ROMId, "ZX3J") == 0) + { + SA1.WaitAddress = SA1_Map [0x0087f2 >> MEMMAP_SHIFT] + 0x87f2; + SA1.WaitByteAddress1 = FillRAM + 0x30c4; + } + /* ShougiNoHanamichi */ + if (strcmp (ROMId, "AARJ") == 0) + { + SA1.WaitAddress = SA1_Map [0xc1f85a >> MEMMAP_SHIFT] + 0xf85a; + SA1.WaitByteAddress1 = SRAM + 0x0c64; + SA1.WaitByteAddress2 = SRAM + 0x0c66; + } + /* KATO HIFUMI9DAN SYOGI */ + if (strcmp (ROMId, "A23J") == 0) + { + SA1.WaitAddress = SA1_Map [0xc25037 >> MEMMAP_SHIFT] + 0x5037; + SA1.WaitByteAddress1 = SRAM + 0x0c06; + SA1.WaitByteAddress2 = SRAM + 0x0c08; + } + /* idaten */ + if (strcmp (ROMId, "AIIJ") == 0) + { + SA1.WaitAddress = SA1_Map [0xc100be >> MEMMAP_SHIFT] + 0x00be; + SA1.WaitByteAddress1 = SRAM + 0x1002; + SA1.WaitByteAddress2 = SRAM + 0x1004; + } + /* igotais */ + if (strcmp (ROMId, "AITJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x0080b7 >> MEMMAP_SHIFT] + 0x80b7; + } + /* J96 DREAM STADIUM */ + if (strcmp (ROMId, "AJ6J") == 0) + { + SA1.WaitAddress = SA1_Map [0xc0f74a >> MEMMAP_SHIFT] + 0xf74a; + } + /* JumpinDerby */ + if (strcmp (ROMId, "AJUJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x00d926 >> MEMMAP_SHIFT] + 0xd926; + } + /* JKAKINOKI SHOUGI */ + if (strcmp (ROMId, "AKAJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x00f070 >> MEMMAP_SHIFT] + 0xf070; + } + /* HOSHI NO KIRBY 3 & KIRBY'S DREAM LAND 3 JAP & US */ + if (strcmp (ROMId, "AFJJ") == 0 || strcmp (ROMId, "AFJE") == 0) + { + SA1.WaitAddress = SA1_Map [0x0082d4 >> MEMMAP_SHIFT] + 0x82d4; + SA1.WaitByteAddress1 = SRAM + 0x72a4; + } + /* KIRBY SUPER DELUXE JAP */ + if (strcmp (ROMId, "AKFJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x008c93 >> MEMMAP_SHIFT] + 0x8c93; + SA1.WaitByteAddress1 = FillRAM + 0x300a; + SA1.WaitByteAddress2 = FillRAM + 0x300e; + } + /* KIRBY SUPER DELUXE US */ + if (strcmp (ROMId, "AKFE") == 0) + { + SA1.WaitAddress = SA1_Map [0x008cb8 >> MEMMAP_SHIFT] + 0x8cb8; + SA1.WaitByteAddress1 = FillRAM + 0x300a; + SA1.WaitByteAddress2 = FillRAM + 0x300e; + } + /* SUPER MARIO RPG JAP & US */ + if (strcmp (ROMId, "ARWJ") == 0 || strcmp (ROMId, "ARWE") == 0) + { + SA1.WaitAddress = SA1_Map [0xc0816f >> MEMMAP_SHIFT] + 0x816f; + SA1.WaitByteAddress1 = FillRAM + 0x3000; + } + /* marvelous.zip */ + if (strcmp (ROMId, "AVRJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x0085f2 >> MEMMAP_SHIFT] + 0x85f2; + SA1.WaitByteAddress1 = FillRAM + 0x3024; + } + /* AUGUSTA3 MASTERS NEW */ + if (strcmp (ROMId, "AO3J") == 0) + { + SA1.WaitAddress = SA1_Map [0x00dddb >> MEMMAP_SHIFT] + 0xdddb; + SA1.WaitByteAddress1 = FillRAM + 0x37b4; + } + /* OSHABERI PARODIUS */ + if (strcmp (ROMId, "AJOJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x8084e5 >> MEMMAP_SHIFT] + 0x84e5; + } + /* PANIC BOMBER WORLD */ + if (strcmp (ROMId, "APBJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x00857a >> MEMMAP_SHIFT] + 0x857a; + } + /* PEBBLE BEACH NEW */ + if (strcmp (ROMId, "AONJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x00df33 >> MEMMAP_SHIFT] + 0xdf33; + SA1.WaitByteAddress1 = FillRAM + 0x37b4; + } + /* PGA EUROPEAN TOUR */ + if (strcmp (ROMId, "AEPE") == 0) + { + SA1.WaitAddress = SA1_Map [0x003700 >> MEMMAP_SHIFT] + 0x3700; + SA1.WaitByteAddress1 = FillRAM + 0x3102; + } + /* PGA TOUR 96 */ + if (strcmp (ROMId, "A3GE") == 0) + { + SA1.WaitAddress = SA1_Map [0x003700 >> MEMMAP_SHIFT] + 0x3700; + SA1.WaitByteAddress1 = FillRAM + 0x3102; + } + /* POWER RANGERS 4 */ + if (strcmp (ROMId, "A4RE") == 0) + { + SA1.WaitAddress = SA1_Map [0x009899 >> MEMMAP_SHIFT] + 0x9899; + SA1.WaitByteAddress1 = FillRAM + 0x3000; + } + /* PACHISURO PALUSUPE */ + if (strcmp (ROMId, "AGFJ") == 0) + { + // Never seems to turn on the SA-1! + } + /* SD F1 GRAND PRIX */ + if (strcmp (ROMId, "AGFJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x0181bc >> MEMMAP_SHIFT] + 0x81bc; + } + /* SHOUGI MARJONG */ + if (strcmp (ROMId, "ASYJ") == 0) + { + SA1.WaitAddress = SA1_Map [0x00f2cc >> MEMMAP_SHIFT] + 0xf2cc; + SA1.WaitByteAddress1 = SRAM + 0x7ffe; + SA1.WaitByteAddress2 = SRAM + 0x7ffc; + } + /* shogisai2 */ + if (strcmp (ROMId, "AX2J") == 0) + { + SA1.WaitAddress = SA1_Map [0x00d675 >> MEMMAP_SHIFT] + 0xd675; + } + + /* SHINING SCORPION */ + if (strcmp (ROMId, "A4WJ") == 0) + { + SA1.WaitAddress = SA1_Map [0xc048be >> MEMMAP_SHIFT] + 0x48be; + } + /* SHIN SHOUGI CLUB */ + if (strcmp (ROMId, "AHJJ") == 0) + { + SA1.WaitAddress = SA1_Map [0xc1002a >> MEMMAP_SHIFT] + 0x002a; + SA1.WaitByteAddress1 = SRAM + 0x0806; + SA1.WaitByteAddress2 = SRAM + 0x0808; + } +#endif // USE_SA1 + + // Additional game fixes by sanmaiwashi ... + if (strcmp (ROMName, "SFX ŲĶÞÝÀÞÑÓɶÞÀØ 1") == 0) + { + bytes0x2000 [0xb18] = 0x4c; + bytes0x2000 [0xb19] = 0x4b; + bytes0x2000 [0xb1a] = 0xea; + } + + if (strcmp (ROMName, "GOGO ACKMAN3") == 0 || + strcmp (ROMName, "HOME ALONE") == 0) + { + // Banks 00->3f and 80->bf + for (int c = 0; c < 0x400; c += 16) + { + Map [c + 6] = Map [c + 0x806] = SRAM; + Map [c + 7] = Map [c + 0x807] = SRAM; + BlockIsROM [c + 6] = BlockIsROM [c + 0x806] = FALSE; + BlockIsROM [c + 7] = BlockIsROM [c + 0x807] = FALSE; + BlockIsRAM [c + 6] = BlockIsRAM [c + 0x806] = TRUE; + BlockIsRAM [c + 7] = BlockIsRAM [c + 0x807] = TRUE; + } + WriteProtectROM (); + } + + if (strncmp (ROMName, "SWORD WORLD SFC", 15) == 0 || + strcmp (ROMName, "SFC ¶ÒÝײÀÞ°") == 0) + { + IAPU.OneCycle = 15; + SNESGameFixes.NeedInit0x2137 = TRUE; + ROMAPUEnabled |= 2; + CPU.APU_APUExecuting |= 2; + } + + if (strncmp (ROMName, "SHIEN THE BLADE CHASE", 21) == 0) + SNESGameFixes.Old_Read0x4200 = TRUE; + + if (strcmp (ROMName, "ºÞ¼Þ× ¶²¼Þ­³ÀÞ²¹¯¾Ý") == 0) + SNESGameFixes.NeedInit0x2137 = TRUE; + + if (strcmp (ROMName, "UMIHARAKAWASE") == 0) + SNESGameFixes.umiharakawaseFix = TRUE; + + if (strcmp (ROMName, "ALIENS vs. PREDATOR") == 0) + SNESGameFixes.alienVSpredetorFix = TRUE; + + if (strcmp (ROMName, "demon's blazon") == 0 || + strcmp (ROMName, "demon's crest") == 0 || + strcmp (ROMName, "ROCKMAN X") == 0 || + strcmp (ROMName, "MEGAMAN X") == 0) + { + + // CAPCOM's protect + // Banks 0x808000, 0x408000 are mirroring. + for (int c = 0; c < 8; c++) + Map [0x408 + c] = ROM - 0x8000; + } + + if (strcmp (ROMName, "½°Ȩ̂߰нÀ") == 0 || + strcmp (ROMName, "½°Ȩ̂߰нÀ 2") == 0 || + strcmp (ROMName, "ZENKI TENCHIMEIDOU") == 0 || + strcmp (ROMName, "GANBA LEAGUE") == 0) + { + SNESGameFixes.APU_OutPorts_ReturnValueFix = TRUE; + } + + // HITOMI3 + if (strcmp (ROMName, "HITOMI3") == 0) + { + Memory.SRAMSize = 1; + CPU.Memory_SRAMMask = Memory.SRAMSize ? + ((1 << (Memory.SRAMSize + 3)) * 128) - 1 : 0; + } + + if (strcmp (ROMName, "goemon 4") == 0) + SNESGameFixes.SRAMInitialValue = 0x00; + + if (strcmp (ROMName, "PACHISLO ¹Ý·­³") == 0) + SNESGameFixes._0x213E_ReturnValue = 1; + + if (strcmp (ROMName, "»Þ Ï°¼Þ¬Ý ijʲÃÞÝ") == 0) + SNESGameFixes.TouhaidenControllerFix = TRUE; + + if (strcmp (ROMName, "DRAGON KNIGHT 4") == 0) + { + // Banks 70->7e, S-RAM + for (int c = 0; c < 0xe0; c++) + { + Map [c + 0x700] = (uint8 *) MAP_LOROM_SRAM; + BlockIsRAM [c + 0x700] = TRUE; + BlockIsROM [c + 0x700] = FALSE; + } + WriteProtectROM (); + } + + if (strncmp (ROMName, "LETs PACHINKO(", 14) == 0) + { + IAPU.OneCycle = 15; + ROMAPUEnabled |= 2; + CPU.APU_APUExecuting |= 2; + if (!Settings.ForceNTSC && !Settings.ForcePAL) + { + Settings.PAL = FALSE; + Settings.FrameTime = Settings.FrameTimeNTSC; + Memory.ROMFramesPerSecond = 60; + } + } + + if (strcmp (ROMName, "FURAI NO SIREN") == 0) + SNESGameFixes.SoundEnvelopeHeightReading2 = TRUE; +#if 0 + if(strcmp (ROMName, "XBAND JAPANESE MODEM") == 0) + { + for (c = 0x200; c < 0x400; c += 16) + { + for (int i = c; i < c + 16; i++) + { + Map [i + 0x400] = Map [i + 0xc00] = &ROM[c * 0x1000]; + MemorySpeed [i + 0x400] = MemorySpeed [i + 0xc00] = 8; + BlockIsRAM [i + 0x400] = BlockIsRAM [i + 0xc00] = TRUE; + BlockIsROM [i + 0x400] = BlockIsROM [i + 0xc00] = FALSE; + } + } + WriteProtectROM (); + } +#endif + +#define RomPatch(adr,ov,nv) \ +if (ROM [adr] == ov) \ + ROM [adr] = nv + + // Love Quest + if (strcmp (ROMName, "LOVE QUEST") == 0) + { + RomPatch (0x1385ec, 0xd0, 0xea); + RomPatch (0x1385ed, 0xb2, 0xea); + } + + // Nangoku Syonen Papuwa Kun + if (strcmp (ROMName, "NANGOKUSYONEN PAPUWA") == 0) + RomPatch (0x1f0d1, 0xa0, 0x6b); + + // Tetsuwan Atom + if (strcmp (ROMName, "Tetsuwan Atom") == 0) + { + RomPatch (0xe24c5, 0x90, 0xea); + RomPatch (0xe24c6, 0xf3, 0xea); + } + + // Oda Nobunaga + if (strcmp (ROMName, "SFC ODA NOBUNAGA") == 0) + { + RomPatch (0x7497, 0x80, 0xea); + RomPatch (0x7498, 0xd5, 0xea); + } + + // Super Batter Up + if (strcmp (ROMName, "Super Batter Up") == 0) + { + RomPatch (0x27ae0, 0xd0, 0xea); + RomPatch (0x27ae1, 0xfa, 0xea); + } + + // Super Professional Baseball 2 + if (strcmp (ROMName, "SUPER PRO. BASE BALL2") == 0) + { + RomPatch (0x1e4, 0x50, 0xea); + RomPatch (0x1e5, 0xfb, 0xea); + } + +} + +// Read variable size MSB int from a file +static long ReadInt (FILE *f, unsigned nbytes) +{ + long v = 0; + while (nbytes--) + { + int c = fgetc(f); + if (c == EOF) + return -1; + v = (v << 8) | (c & 0xFF); + } + return (v); +} + +#define IPS_EOF 0x00454F46l + +void CMemory::CheckForIPSPatch (const char *rom_filename, bool8_32 header, + int32 &rom_size) +{ + char dir [_MAX_DIR + 1]; + char drive [_MAX_DRIVE + 1]; + char name [_MAX_FNAME + 1]; + char ext [_MAX_EXT + 1]; + char fname [_MAX_PATH + 1]; + FILE *patch_file = NULL; + long offset = header ? 512 : 0; + + if (!(patch_file = fopen(S9xGetFilename (".ips"), "rb"))) return; + + if (fread (fname, 1, 5, patch_file) != 5 || strncmp (fname, "PATCH", 5) != 0) + { + fclose (patch_file); + return; + } + + int32 ofs; + + for (;;) + { + long len; + long rlen; + int rchar; + + ofs = ReadInt (patch_file, 3); + if (ofs == -1) + goto err_eof; + + if (ofs == IPS_EOF) + break; + + ofs -= offset; + + len = ReadInt (patch_file, 2); + if (len == -1) + goto err_eof; + + /* Apply patch block */ + if (len) + { + if (ofs + len > MAX_ROM_SIZE) + goto err_eof; + + while (len--) + { + rchar = fgetc (patch_file); + if (rchar == EOF) + goto err_eof; + ROM [ofs++] = (uint8) rchar; + } + if (ofs > rom_size) + rom_size = ofs; + } + else + { + rlen = ReadInt (patch_file, 2); + if (rlen == -1) + goto err_eof; + + + rchar = fgetc (patch_file); + if (rchar == EOF) + goto err_eof; + + if (ofs + rlen > MAX_ROM_SIZE) + goto err_eof; + + while (rlen--) + ROM [ofs++] = (uint8) rchar; + + if (ofs > rom_size) + rom_size = ofs; + } + } + + // Check if ROM image needs to be truncated + ofs = ReadInt (patch_file, 3); + if (ofs != -1 && ofs - offset < rom_size) + { + // Need to truncate ROM image + rom_size = ofs - offset; + } + fclose (patch_file); + return; + +err_eof: + if (patch_file) + fclose (patch_file); +} + +const uint32 crc32Table[256] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +//CRC32 for char arrays +uint32 CMemory::caCRC32(uint8 *array, uint32 size, register uint32 crc32) { + for (register uint32 i = 0; i < size; i++) { + crc32 = ((crc32 >> 8) & 0x00FFFFFF) ^ crc32Table[(crc32 ^ array[i]) & 0xFF]; + } + return ~crc32; +} +#include "getset.h" diff --git a/src/memmap.h b/src/memmap.h new file mode 100644 index 0000000..ca234ea --- /dev/null +++ b/src/memmap.h @@ -0,0 +1,200 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _memmap_h_ +#define _memmap_h_ + +#include "snes9x.h" + +#ifdef FAST_LSB_WORD_ACCESS +#define READ_WORD(s) (*(uint16 *) (s)) +#define READ_DWORD(s) (*(uint32 *) (s)) +#define WRITE_WORD(s, d) (*(uint16 *) (s) = (d) +#define WRITE_DWORD(s, d) (*(uint32 *) (s) = (d) +#else +#define READ_WORD(s) ( *(uint8 *) (s) |\ + (*((uint8 *) (s) + 1) << 8)) +#define READ_DWORD(s) ( *(uint8 *) (s) |\ + (*((uint8 *) (s) + 1) << 8) |\ + (*((uint8 *) (s) + 2) << 16) |\ + (*((uint8 *) (s) + 3) << 24)) +#define WRITE_WORD(s, d) *(uint8 *) (s) = (d), \ + *((uint8 *) (s) + 1) = (d) >> 8 +#define WRITE_DWORD(s, d) *(uint8 *) (s) = (uint8) (d), \ + *((uint8 *) (s) + 1) = (uint8) ((d) >> 8),\ + *((uint8 *) (s) + 2) = (uint8) ((d) >> 16),\ + *((uint8 *) (s) + 3) = (uint8) ((d) >> 24) +#define WRITE_3WORD(s, d) *(uint8 *) (s) = (uint8) (d), \ + *((uint8 *) (s) + 1) = (uint8) ((d) >> 8),\ + *((uint8 *) (s) + 2) = (uint8) ((d) >> 16) +#define READ_3WORD(s) ( *(uint8 *) (s) |\ + (*((uint8 *) (s) + 1) << 8) |\ + (*((uint8 *) (s) + 2) << 16)) + +#endif + +#define MEMMAP_BLOCK_SIZE (0x1000) +#define MEMMAP_NUM_BLOCKS (0x1000000 / MEMMAP_BLOCK_SIZE) +#define MEMMAP_BLOCKS_PER_BANK (0x10000 / MEMMAP_BLOCK_SIZE) +#define MEMMAP_SHIFT 12 +#define MEMMAP_MASK (MEMMAP_BLOCK_SIZE - 1) +#define MEMMAP_MAX_SDD1_LOGGED_ENTRIES (0x10000 / 8) + +class CMemory { +public: + bool8_32 LoadROM (const char *); + void InitROM (bool8_32); + bool8_32 LoadSRAM (const char *); + bool8_32 SaveSRAM (const char *); + bool8_32 Init (); + void Deinit (); + void FreeSDD1Data (); + + void WriteProtectROM (); + void FixROMSpeed (); + void MapRAM (); + void MapExtraRAM (); + char *Safe (const char *); + + void LoROMMap (); + void LoROM24MBSMap (); + void SRAM512KLoROMMap (); + void SRAM1024KLoROMMap (); + void SufamiTurboLoROMMap (); + void HiROMMap (); + void SuperFXROMMap (); + void TalesROMMap (bool8_32); + void AlphaROMMap (); + void SA1ROMMap (); + void BSHiROMMap (); + bool8_32 AllASCII (uint8 *b, int size); + int ScoreHiROM (bool8_32 skip_header); + int ScoreLoROM (bool8_32 skip_header); + void ApplyROMFixes (); + void CheckForIPSPatch (const char *rom_filename, bool8_32 header, + int32 &rom_size); + + const char *TVStandard (); + const char *Speed (); + const char *StaticRAMSize (); + const char *MapType (); + const char *MapMode (); + const char *KartContents (); + const char *Size (); + const char *Headers (); + const char *ROMID (); + const char *CompanyID (); + uint32 caCRC32(uint8 *array, uint32 size, register uint32 crc32= 0xFFFFFFFF); + + enum { + MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM, + MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP, + MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST + }; + enum { MAX_ROM_SIZE = 0x600000 }; + + uint8 *RAM; + uint8 *ROM; + uint8 *VRAM; + uint8 *SRAM; + uint8 *BWRAM; + uint8 *FillRAM; + uint8 *C4RAM; + bool8_32 HiROM; + bool8_32 LoROM; + uint16 SRAMMask; + uint8 SRAMSize; + uint8 *Map [MEMMAP_NUM_BLOCKS]; + uint8 *WriteMap [MEMMAP_NUM_BLOCKS]; + uint32 MemorySpeed [MEMMAP_NUM_BLOCKS]; + uint8 BlockIsRAM [MEMMAP_NUM_BLOCKS]; + uint8 BlockIsROM [MEMMAP_NUM_BLOCKS]; + char ROMName [ROM_NAME_LEN]; + char ROMId [5]; + char CompanyId [3]; + uint8 ROMSpeed; + uint8 ROMType; + uint8 ROMSize; + int32 ROMFramesPerSecond; + int32 HeaderCount; + uint32 CalculatedSize; + uint32 CalculatedChecksum; + uint32 ROMChecksum; + uint32 ROMComplementChecksum; + uint8 *SDD1Index; + uint8 *SDD1Data; + uint32 SDD1Entries; + uint32 SDD1LoggedDataCountPrev; + uint32 SDD1LoggedDataCount; + uint8 SDD1LoggedData [MEMMAP_MAX_SDD1_LOGGED_ENTRIES]; +#ifndef _SNESPPC + char ROMFilename [_MAX_PATH]; +#else + char ROMFilename [1024]; +#endif +}; + +START_EXTERN_C +extern CMemory Memory; +extern uint8 *SRAM; +extern uint8 *ROM; +extern uint8 *RegRAM; +void S9xDeinterleaveMode2 (); +void S9xSaveSRAM (void); +END_EXTERN_C + +void S9xAutoSaveSRAM (); + +#ifdef NO_INLINE_SET_GET +uint8 S9xGetByte (uint32 Address, struct SCPUState *); +uint16 S9xGetWord (uint32 Address, struct SCPUState *); +void S9xSetByte (uint8 Byte, uint32 Address, struct SCPUState * ); +void S9xSetWord (uint16 Byte, uint32 Address, struct SCPUState *); +void S9xSetPCBase (uint32 Address, struct SCPUState *); +uint8 *S9xGetMemPointer (uint32 Address); +uint8 *GetBasePointer (uint32 Address); +#else +#ifndef INLINE +#define INLINE inline +#endif +#include "getset.h" +#endif // NO_INLINE_SET_GET + +#endif // _memmap_h_ diff --git a/src/memset.S b/src/memset.S new file mode 100644 index 0000000..e8b1e59 --- /dev/null +++ b/src/memset.S @@ -0,0 +1,72 @@ +/* Copyright (C) 1998 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Philip Blundell + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +/*#include */ + + .text + .global memset; + .type memset,%function + .align 4; +memset: + mov a4, a1 + cmp a3, $8 @ at least 8 bytes to do? + blt 2f + orr a2, a2, a2, lsl $8 + orr a2, a2, a2, lsl $16 +1: + tst a4, $3 @ aligned yet? + strneb a2, [a4], $1 + subne a3, a3, $1 + bne 1b + mov ip, a2 +1: + cmp a3, $8 @ 8 bytes still to do? + blt 2f + stmia a4!, {a2, ip} + sub a3, a3, $8 + cmp a3, $8 @ 8 bytes still to do? + blt 2f + stmia a4!, {a2, ip} + sub a3, a3, $8 + cmp a3, $8 @ 8 bytes still to do? + blt 2f + stmia a4!, {a2, ip} + sub a3, a3, $8 + cmp a3, $8 @ 8 bytes still to do? + stmgeia a4!, {a2, ip} + subge a3, a3, $8 + bge 1b +2: + movs a3, a3 @ anything left? + moveq pc, lr @ nope + rsb a3, a3, $7 + add pc, pc, a3, lsl $2 + mov r0, r0 + strb a2, [a4], $1 + strb a2, [a4], $1 + strb a2, [a4], $1 + strb a2, [a4], $1 + strb a2, [a4], $1 + strb a2, [a4], $1 + strb a2, [a4], $1 + //mov pc, lr + bx lr + +.size memset,.-memset; + diff --git a/src/menu.c b/src/menu.c new file mode 100644 index 0000000..1908323 --- /dev/null +++ b/src/menu.c @@ -0,0 +1,2385 @@ +#include "menu.h" +#include "theme.h" +#include "config.h" +#include "screenshot.h" +#include "graphics.h" +#include "png.h" + +#define MENU_AREA_Y_START 50 +#define MENU_AREA_Y_END 227 + +#define PPU_IGNORE_FIXEDCOLCHANGES (1<<0) +#define PPU_IGNORE_WINDOW (1<<1) +#define PPU_IGNORE_ADDSUB (1<<2) +#define PPU_IGNORE_PALWRITE (1<<3) +#define GFX_IGNORE_OBJ (1<<4) +#define GFX_IGNORE_BG0 (1<<5) +#define GFX_IGNORE_BG1 (1<<6) +#define GFX_IGNORE_BG2 (1<<7) +#define GFX_IGNORE_BG3 (1<<8) + +char romDir[MAX_PATH+1]; +char snesRomDir[MAX_PATH+1]; + +#define ROM_SELECTOR_DEFAULT_FOCUS 3 + +DIRDATA dir; + +#if defined (__GP2X__) +unsigned short cpuSpeedLookup[46]={ + 10,20, 30, 40, 50, + 60,70, 80, 90,100, + 110,120,130,144,150, + 160,170,180,190,200, + 210,220,230,240,250, + 255,260,265,270,275, + 280,285,290,295,300, + 305,310,315,320,325, + 330,335,340,345,350, + 355}; +#endif + +#if defined (__WIZ__) +unsigned short cpuSpeedLookup[46]={ + 200,250, 300, 350, 400, + 450,500, 520, 540,560, + 580,590,600,610,620, + 630,640,650,660,670, + 680,690,700,710,720, + 730,740,750,760,770, + 780,790,800,810,820, + 830,840,850,860,870, + 875,880,885,890,895, + 900}; +#endif + +extern volatile int timer; +static int menutileXscroll=0; +static int menutileYscroll=0; +static int headerDone[4]; // variable that records if header graphics have been rendered or not +int quickSavePresent=0; +struct ROM_LIST_RECORD +{ + char filename[MAX_PATH+1]; + char type; +}; + +static struct ROM_LIST_RECORD romList[MAX_ROMS]; +struct SNES_MENU_OPTIONS snesMenuOptions; + +static int romCount; +char currentRomFilename[MAX_PATH+1]=""; +int currFB=0; +int prevFB=0; +int currentEmuMode=EMU_MODE_SNES; + +char currentWorkingDir[MAX_PATH+1]; +char snesOptionsDir[MAX_PATH+1]; +char snesSramDir[MAX_PATH+1]; +char snesSaveStateDir[MAX_PATH+1]; +#if defined(__WIZ__) +float soundRates[3]={22050.0,32000.0,44100.0}; +#else +float soundRates[5]={8000.0,11025.0,16000.0,22050.0,44100.0}; +#endif +char menutext[256][50]; + +struct SAVE_STATE saveState[10]; // holds the filenames for the savestate and "inuse" flags +char saveStateName[MAX_PATH+MAX_PATH+2]; // holds the last filename to be scanned for save states + +// a few vars for persistent file selector +int lastSelected = -1; +int defaultDir; + +unsigned char gammaConv[32*29]={ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 0, 2, 3, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 24, 25, 26, 27, 28, 29, 29, 30, 31, + 0, 3, 5, 7, 8, 9, 10, 11, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 22, 22, 23, 24, 25, 25, 26, 27, 28, 28, 29, 30, 30, 31, + 0, 4, 6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 20, 21, 22, 23, 23, 24, 25, 25, 26, 27, 27, 28, 29, 29, 30, 30, 31, + 0, 6, 8, 10, 11, 12, 14, 15, 16, 17, 18, 18, 19, 20, 21, 22, 22, 23, 24, 24, 25, 26, 26, 27, 27, 28, 28, 29, 29, 30, 30, 31, + 0, 7, 9, 11, 12, 14, 15, 16, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24, 25, 26, 26, 27, 27, 28, 28, 29, 29, 30, 30, 31, 31, + 0, 8, 10, 12, 14, 15, 16, 17, 18, 19, 20, 20, 21, 22, 23, 23, 24, 24, 25, 25, 26, 27, 27, 28, 28, 28, 29, 29, 30, 30, 31, 31, + 0, 9, 11, 13, 15, 16, 17, 18, 19, 20, 21, 21, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29, 29, 30, 30, 31, 31, + 0, 10, 12, 14, 16, 17, 18, 19, 20, 21, 21, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 28, 29, 29, 30, 30, 30, 31, 31, + 0, 11, 13, 15, 17, 18, 19, 20, 20, 21, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 29, 29, 29, 30, 30, 30, 31, 31, + 0, 12, 14, 16, 17, 18, 19, 20, 21, 22, 22, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 30, 30, 30, 31, 31, + 0, 12, 15, 17, 18, 19, 20, 21, 22, 22, 23, 24, 24, 25, 25, 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, 29, 30, 30, 30, 30, 31, 31, + 0, 13, 16, 17, 19, 20, 21, 21, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 30, 30, 30, 30, 31, 31, + 0, 14, 16, 18, 19, 20, 21, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 29, 30, 30, 30, 31, 31, 31, + 0, 14, 17, 18, 20, 21, 22, 22, 23, 24, 24, 25, 25, 26, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 30, 30, 30, 30, 31, 31, 31, + 0, 15, 17, 19, 20, 21, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 29, 30, 30, 30, 30, 31, 31, 31, + 0, 16, 18, 19, 21, 22, 22, 23, 24, 24, 25, 25, 26, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 29, 30, 30, 30, 30, 31, 31, 31, + 0, 16, 18, 20, 21, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 29, 30, 30, 30, 30, 30, 31, 31, 31, + 0, 17, 19, 20, 21, 22, 23, 24, 24, 25, 25, 26, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 29, 30, 30, 30, 30, 30, 31, 31, 31, + 0, 17, 19, 21, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 28, 29, 29, 29, 29, 30, 30, 30, 30, 30, 31, 31, 31, + 0, 17, 20, 21, 22, 23, 24, 24, 25, 25, 26, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 31, 31, 31, + 0, 18, 20, 21, 22, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 28, 29, 29, 29, 29, 30, 30, 30, 30, 30, 30, 31, 31, 31, + 0, 18, 20, 22, 23, 23, 24, 25, 25, 26, 26, 26, 27, 27, 27, 28, 28, 28, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 31, 31, 31, 31, + 0, 19, 21, 22, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 28, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 31, 31, 31, 31, + 0, 19, 21, 22, 23, 24, 25, 25, 26, 26, 26, 27, 27, 27, 28, 28, 28, 28, 29, 29, 29, 29, 30, 30, 30, 30, 30, 30, 31, 31, 31, 31, + 0, 19, 21, 22, 23, 24, 25, 25, 26, 26, 27, 27, 27, 27, 28, 28, 28, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 30, 31, 31, 31, 31, + 0, 20, 22, 23, 24, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 28, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 30, 31, 31, 31, 31, + 0, 20, 22, 23, 24, 24, 25, 26, 26, 26, 27, 27, 27, 28, 28, 28, 28, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 30, 31, 31, 31, 31, + 0, 20, 22, 23, 24, 25, 25, 26, 26, 27, 27, 27, 28, 28, 28, 28, 29, 29, 29, 29, 29, 30, 30, 30, 30, 30, 30, 30, 31, 31, 31, 31}; + + +void InitMenu(void) { + +} + +void UpdateMenuGraphicsGamma(void) +{ + unsigned int currPix=0; + unsigned short pixel=0; + unsigned char R,G,B; + for(currPix=0;currPix<15360;currPix++) + { + // md 0000 bbb0 ggg0 rrr0 + // gp rrrr rggg ggbb bbbi + pixel=menuHeaderOrig[currPix]; + R=(pixel>>11)&0x1F; // 0000 0RRR - 3 bits Red + G=(pixel>>6)&0x1F; + B=(pixel>>1)&0x1F; + + // Do gamma correction + R=gammaConv[R+(0<<5)]; + G=gammaConv[G+(0<<5)]; + B=gammaConv[B+(0<<5)]; + + pixel=MENU_RGB(R,G,B); + menuHeader[currPix]=pixel; + } + for(currPix=0;currPix<5120;currPix++) + { + // md 0000 bbb0 ggg0 rrr0 + // gp rrrr rggg ggbb bbbi + pixel=highLightBarOrig[currPix]; + R=(pixel>>11)&0x1F; // 0000 0RRR - 3 bits Red + G=(pixel>>6)&0x1F; + B=(pixel>>1)&0x1F; + + // Do gamma correction + R=gammaConv[R+(0<<5)]; + G=gammaConv[G+(0<<5)]; + B=gammaConv[B+(0<<5)]; + + pixel=MENU_RGB(R,G,B); + highLightBar[currPix]=pixel; + + } + + for(currPix=0;currPix<(MENU_TILE_WIDTH*MENU_TILE_HEIGHT);currPix++) + { + // md 0000 bbb0 ggg0 rrr0 + // gp rrrr rggg ggbb bbbi + pixel=menuTileOrig[currPix]; + R=(pixel>>11)&0x1F; // 0000 0RRR - 3 bits Red + G=(pixel>>6)&0x1F; + B=(pixel>>1)&0x1F; + + // Do gamma correction + R=gammaConv[R+(0<<5)]; + G=gammaConv[G+(0<<5)]; + B=gammaConv[B+(0<<5)]; + + pixel=MENU_RGB(R,G,B); + menuTile[currPix]=pixel; + + } +} + +void SnesDefaultMenuOptions(void) +{ + // no options file loaded, so set to defaults + snesMenuOptions.menuVer=SNES_OPTIONS_VER; + snesMenuOptions.frameSkip=0; + snesMenuOptions.soundOn = 1; + snesMenuOptions.volume=100; + memset(snesMenuOptions.padConfig,0xFF,sizeof(snesMenuOptions.padConfig)); + snesMenuOptions.showFps=1; + snesMenuOptions.gamma=0; + snesMenuOptions.asmspc700=1; + snesMenuOptions.SpeedHacks=1; +#if defined(__WIZ__) + snesMenuOptions.soundRate=0; + snesMenuOptions.cpuSpeed=8; +#else + snesMenuOptions.soundRate=2; + snesMenuOptions.cpuSpeed=19; +#endif + snesMenuOptions.loadOnInit = 0; + snesMenuOptions.delayedRasterFX = 1; +} + +static void ShowMessage(char *text, int showMessage) { + if (showMessage) { + gp_setClipping(0, 0, 310, 239); + PrintBar(prevFB,240-16); + gp_drawString(40,228,strlen(text),text,tTextColorFocus,framebuffer16[prevFB]); + } +} + +int LoadMenuOptions(char *path, char *filename, char *ext, char *optionsmem, int maxsize, int showMessage) +{ + char fullFilename[MAX_PATH+MAX_PATH+1]; + char _filename[MAX_PATH+1]; + char _ext[MAX_PATH+1]; + FILE *stream; + int size=0; + char text[50]; + + ShowMessage("Loading...", showMessage); + + SplitFilename(filename, _filename, _ext); + sprintf(fullFilename,"%s%s%s.%s",path,DIR_SEP,_filename,ext); + stream=fopen(fullFilename,"rb"); + if(stream) + { + // File exists do try to load it + fseek(stream,0,SEEK_END); + size=ftell(stream); + if (size>maxsize) size=maxsize; + fseek(stream,0,SEEK_SET); + fread(optionsmem, 1, size, stream); + fclose(stream); + return(0); + } + else + { + return(1); + } +} + +int SaveMenuOptions(char *path, char *filename, char *ext, char *optionsmem, int maxsize, int showMessage) +{ + char fullFilename[MAX_PATH+MAX_PATH+1]; + char _filename[MAX_PATH+1]; + char _ext[MAX_PATH+1]; + FILE *stream; + char text[50]; + + ShowMessage("Saving...", showMessage); + + SplitFilename(filename, _filename, _ext); + sprintf(fullFilename,"%s%s%s.%s",path,DIR_SEP,_filename,ext); + stream=fopen(fullFilename,"wb"); + if(stream) + { + fwrite(optionsmem, 1, maxsize, stream); + fclose(stream); + sync(); + return(0); + } + else + { + return(1); + } +} + +int DeleteMenuOptions(char *path, char *filename, char *ext, int showMessage) +{ + char fullFilename[MAX_PATH+MAX_PATH+1]; + char _filename[MAX_PATH+1]; + char _ext[MAX_PATH+1]; + char text[50]; + + ShowMessage("Deleting...", showMessage); + + SplitFilename(filename, _filename, _ext); + sprintf(fullFilename,"%s%s%s.%s",path,DIR_SEP,_filename,ext); + remove(fullFilename); + sync(); + return(0); +} + +#ifdef __GIZ__ +void sync(void) +{ +} +#endif + +static void WaitForButtonsUp(void) +{ + int i=0,j=0,z=0; + + for(i=0;i<100;i++) + { + while(1) + { + InputUpdate(0); + z=0; + for (j=0;j<32;j++) + { + if (Inp.held[j]) z=1; + } + if (z==0) break; + } + } +} + +void MenuPause() +{ + int i=0,j=0,z=0; + // wait for keys to be released + for(i=0;i<100;i++) // deal with keybounce by checking a few times + { + while(1) + { + InputUpdate(0); + z=0; + for (j=0;j<32;j++) + { + if (Inp.held[j]) z=1; + } + if (z==0) break; + } + } + + for(i=0;i<100;i++) // deal with keybounce by checking a few times + { + while(1) + { + InputUpdate(0); + z=0; + for (j=0;j<32;j++) + { + if (Inp.held[j]) z=1; + } + if (z==1) break; + } + } +} +#if defined (__GP2X__) || defined(__WIZ__) +void MenuFlip() +{ + prevFB=currFB; + gp_setFramebuffer(currFB,1); + currFB++; + currFB&=3; +} +#endif +#if defined (__GIZ__) +void MenuFlip() +{ + prevFB=currFB=0; + gp_setFramebuffer(currFB,0); +} +#endif +void SplitFilename(char *wholeFilename, char *filename, char *ext) +{ + int len=strlen(wholeFilename); + int i=0,y=-1; + + ext[0]=0; + filename[0]=0; + //Check given string is not null + if (len<=0) + { + return; + } + y=-1; + for(i=len-2;i>0;i--) + { + if (wholeFilename[i]=='.') + { + y=i; + break; + } + } + + if (y>=0) + { + memcpy(filename,wholeFilename,y); + filename[y]=0; // change "." to zero to end string + memcpy(ext,wholeFilename+y+1,len-(y+1)); + //ext[len-(y+1)+1]=0; + ext[len-(y+1)]=0; + } + else + { + strcpy(filename,wholeFilename); + } +} + +//Ensures all directory seperators are valid for system +void CheckDirSep(char *path) +{ + int i=0; + char dirSepBad[2]={DIR_SEP_BAD}; + char dirSep[2]={DIR_SEP}; + for(i=0;i39)len=39; + gp_drawString(8,50,len,message1,tTextColorItem,framebuffer16[currFB]); + len=strlen(message2); + if(len>39)len=39; + gp_drawString(8,60,len,message2,tTextColorItem,framebuffer16[currFB]); + len=strlen(message3); + if(len>39)len=39; + gp_drawString(8,70,len,message3,tTextColorItem,framebuffer16[currFB]); + switch(mode) + { + case 0: // yes no input + if(select==0) + { + PrintBar(currFB, 120-4); + gp_drawString(8,120,3,"YES",tTextColorFocus,framebuffer16[currFB]); + gp_drawString(8,140,2,"NO",tTextColorItem,framebuffer16[currFB]); + } + else + { + PrintBar(currFB, 140-4); + gp_drawString(8,120,3,"YES",tTextColorItem,framebuffer16[currFB]); + gp_drawString(8,140,2,"NO",tTextColorFocus,framebuffer16[currFB]); + + } + break; + } + MenuFlip(); + } + return(subaction); +} + +static +int deleterom(int romindex) +{ + char text[MAX_PATH+1]; + char fullfilename[MAX_PATH+MAX_PATH+1]; + int x; + FILE *stream=NULL; + + PrintTile(currFB); + PrintTitle(currFB); + MenuFlip(); + + sprintf(text,"Deleting Rom.."); + gp_drawString(8,50,strlen(text),text,tTextColorItem,framebuffer16[prevFB]); + + sprintf(text,"%s",romList[romindex].filename); + x=strlen(text); + if(x>40) x=40; + gp_drawString(0,60,x,text,tTextColorItem,framebuffer16[prevFB]); + + sprintf(fullfilename,"%s%s%s",romDir,DIR_SEP,romList[romindex].filename); + remove(fullfilename); + sync(); + + sprintf(text,"Updating Rom List.."); + gp_drawString(8,70,strlen(text),text,tTextColorItem,framebuffer16[prevFB]); + for(x=romindex;xw, tBmpBackground->h - MENU_AREA_Y_START + 1); + } else { + + x2=menutileXscroll; + y2=(menutileYscroll*MENU_TILE_WIDTH); + graphics1 = menuTile+y2; + for (y=0; y<(240-48); y++) + { + for (x=0; x<320; x++) + { + *framebuffer1++ = graphics1[x2]; + x2++; + x2&=(MENU_TILE_WIDTH-1); + } + y2+=MENU_TILE_WIDTH; + y2&=((MENU_TILE_HEIGHT*MENU_TILE_WIDTH)-1); + graphics1=menuTile+y2; + } + + tileCounter++; + if (tileCounter > 5) + { + tileCounter=0; + menutileXscroll++; + if(menutileXscroll>=MENU_TILE_WIDTH) menutileXscroll=0; + + menutileYscroll++; + if(menutileYscroll>=MENU_TILE_HEIGHT) menutileYscroll=0; + } + } + return; +} + +void PrintTitle(int flip) +{ + unsigned int x,y; + char text[] = DRSNES_VERSION; + //If header already drawn for this layer exit + if (headerDone[flip]) return; + + if (isThemeActive() != 0) { + gDrawBitmap16((unsigned short *)framebuffer16[flip], 0, 0, tBmpBackground, 0, 0, tBmpBackground->w, MENU_AREA_Y_START); + } else { + unsigned short *framebuffer = (unsigned short*)framebuffer16[flip]; + unsigned short *graphics = (unsigned short*)menuHeader; + + for (y=0; y<48; y++) + { + for (x=0; x<320; x++) + { + *framebuffer++ = *graphics++; + } + } + } + + //sprintf(text,"%s",DRSNES_VERSION); + gp_drawString(175,15,strlen(text),text,tTextColorVersion,framebuffer16[flip]); + headerDone[currFB] = 1; +} + +void PrintBar(int flip, unsigned int givenY) +{ + if (isThemeActive()) { + gBlendBitmap16((unsigned short *)framebuffer16[flip], 0, givenY, tBmpBar, 0, 0, tBmpBar->w, tBmpBar->h); + } else { + unsigned int *framebuffer1 = NULL; + unsigned int *graphics1 = (unsigned int *)highLightBar; + unsigned int x,y; + + framebuffer1 = (unsigned int*)framebuffer16[flip]+(givenY*160); + for (y=0; y<16; y++) + { + for (x=0; x<160; x++) + { + *framebuffer1++ = *graphics1++; + } + } + } +} + +static int StringCompare(char *string1, char *string2) +{ + int i=0; + char c1=0,c2=0; + while(1) + { + c1=string1[i]; + c2=string2[i]; + // check for string end + + if ((c1 == 0) && (c2 == 0)) return 0; + if (c1 == 0) return 1; + if (c2 == 0) return -1; + + if ((c1 >= 0x61)&&(c1<=0x7A)) c1-=0x20; + if ((c2 >= 0x61)&&(c2<=0x7A)) c2-=0x20; + if (c1>c2) + return 1; + else if (c1d_name[0] != '.') + { +#if defined(__GP2X__) || defined(__WIZ__) + if (de->d_type == 4) // Directory +#endif +#ifdef __GIZ__ + sprintf(dirCheck,"%s%s%s",romDir,DIR_SEP,de->d_name); + CharToWChar(wc, dirCheck); + hTest=FindFirstFileW(wc, &fileInfo); + if (fileInfo.dwFileAttributes&FILE_ATTRIBUTE_DIRECTORY) +#endif + { + + for (i=ROM_SELECTOR_DEFAULT_FOCUS+1;i<=(romCount+1);i++) + { + if (romList[i].filename[0] == 0) // string is empty so shove new value in + { + strcpy(romList[i].filename,de->d_name); + romList[i].type=FILE_TYPE_DIRECTORY;//de->d_type; + break; + } + else + { + if ((StringCompare(romList[i].filename,de->d_name) > 0) || + (romList[i].type != FILE_TYPE_DIRECTORY)) + { + // new entry is lower than current string so move all entries up one and insert + // new value in + for (j=romCount;j>=i;j--) + { + strcpy(romList[j+1].filename,romList[j].filename); + romList[j+1].type=romList[j].type; + } + strcpy(romList[i].filename,de->d_name); + romList[i].type=FILE_TYPE_DIRECTORY;//de->d_type; + break; + } + } + } + dirCount++; + romCount++; + } + else // File + { + // only interested in Zip and SMC files + SplitFilename(de->d_name,_filename,_ext); + if ((StringCompare(_ext,"zip") == 0) || + (StringCompare(_ext,"smc") == 0) || + (StringCompare(_ext,"sfc") == 0)) + { + for (i=ROM_SELECTOR_DEFAULT_FOCUS+1+dirCount;i<=(romCount+1);i++) + { + if (romList[i].filename[0] == 0) // string is empty so shove new value in + { + strcpy(romList[i].filename,de->d_name); + romList[i].type=FILE_TYPE_FILE;//de->d_type; + break; + } + else + { + if (StringCompare(romList[i].filename,de->d_name) > 0) + { + // new entry is lower than current string so move all entries up one and insert + // new value in + for (j=romCount;j>=i;j--) + { + strcpy(romList[j+1].filename,romList[j].filename); + romList[j+1].type=romList[j].type; + } + strcpy(romList[i].filename,de->d_name); + romList[i].type=FILE_TYPE_FILE;//de->d_type; + break; + } + } + } + romCount++; + } + } + + + if (romCount > MAX_ROMS) + { + PrintTile(currFB); + PrintTitle(currFB); + sprintf(text,"Max rom limit exceeded! %d max",MAX_ROMS); + gp_drawString(8,120,strlen(text),text,tTextColorItem,framebuffer16[currFB]); + sprintf(text,"Please reduce number of roms"); + gp_drawString(8,130,strlen(text),text,tTextColorItem,framebuffer16[currFB]); + MenuFlip(); + MenuPause(); + break; + } + } + } + closedir(d); + + getConfigValue(CONFIG_LASTLOADED, ll, sizeof(ll)); + if (strstr(ll, romDir)) { // where loaded in current dir + llf = strrchr(ll, '/'); + if (!llf) { + ll[0] = '\0'; + llf = ll; + } else llf++; + + for(i = 4; i < romCount; i++) { + if ((romList[i].type == FILE_TYPE_FILE) && + (strncmp(romList[i].filename, llf, strlen(romList[i].filename)) == 0)) { + lastSelected = i; + } + } + } + } + else + { + PrintTile(currFB); + PrintTitle(currFB); + sprintf(text,"Failed to open directory!"); + gp_drawString(8,120,strlen(text),text,tTextColorItem,framebuffer16[currFB]); + MenuFlip(); + MenuPause(); + } + + + + return romCount; +} + +int FileSelect(int mode) +{ + char text[256]; + int romname_length; + int action=0; + int smooth=0; + unsigned short color=0; + int i=0; + int focus=ROM_SELECTOR_DEFAULT_FOCUS; + int menuExit=0; + int scanstart=0,scanend=0; + char dirSep[2]={DIR_SEP}; + char dirSepBad[2]={DIR_SEP_BAD}; + + //int x = lastSelected; + int txt_dir; + int txt_offset; + int frame; + +#define TIME_TO_SCREENSHOT (20 * 1) +#define RESET_SCREENSHOT_COUNTER \ + timeToScreenshot = TIME_TO_SCREENSHOT;\ + if (bmpScreenshot) {\ + gDestroyBitmap(bmpScreenshot); \ + bmpScreenshot = NULL; \ + }\ + noScreenshot = 0; + + int timeToScreenshot; + int noScreenshot; + int xScreenshot; + gBITMAP *bmpScreenshot = NULL; + + FileScan(); +#define RESET_NAME_SCROLL \ + txt_dir = 1; \ + txt_offset = -1; + + RESET_NAME_SCROLL + RESET_SCREENSHOT_COUNTER + + if (lastSelected >= 0) focus = lastSelected; + if (focus>romCount-1) focus = ROM_SELECTOR_DEFAULT_FOCUS; + smooth=focus<<8; + + while (menuExit==0) + { + InputUpdate(0); + + // Change which rom is focused on: + if (Inp.repeat[INP_BUTTON_UP]) + { + focus--; // Up + RESET_NAME_SCROLL + RESET_SCREENSHOT_COUNTER + } + if (Inp.repeat[INP_BUTTON_DOWN]) + { + focus++; // Down + RESET_NAME_SCROLL + RESET_SCREENSHOT_COUNTER + } + + if (Inp.held[INP_BUTTON_MENU_CANCEL]==1 ) {action=0; menuExit=1;} + + if (Inp.repeat[INP_BUTTON_LEFT] || Inp.repeat[INP_BUTTON_RIGHT] ) + { + if (Inp.repeat[INP_BUTTON_LEFT]) + { + focus-=12; + smooth=(focus<<8)-1; + } + else if (Inp.repeat[INP_BUTTON_RIGHT]) + { + focus+=12; + smooth=(focus<<8)-1; + } + + if (focus>romCount-1) + { + focus=romCount-1; + smooth=(focus<<8)-1; + } + else if (focus<0) + { + focus=0; + smooth=(focus<<8)-1; + } + RESET_NAME_SCROLL + RESET_SCREENSHOT_COUNTER + } + + if (focus>romCount-1) + { + focus=0; + smooth=(focus<<8)-1; + RESET_NAME_SCROLL + RESET_SCREENSHOT_COUNTER + } + else if (focus<0) + { + focus=romCount-1; + smooth=(focus<<8)-1; + RESET_NAME_SCROLL + RESET_SCREENSHOT_COUNTER + } + //if (defaultDir) lastSelected = focus; + if (Inp.held[INP_BUTTON_MENU_SELECT]==1) + { + switch(focus) + { + case 0: //Save default directory + SaveMenuOptions(snesOptionsDir, DEFAULT_ROM_DIR_FILENAME, DEFAULT_ROM_DIR_EXT, romDir, strlen(romDir),1); + strcpy(snesRomDir,romDir); + break; + + case 1: //Return to menu + action=0; + menuExit=1; + break; + + case 2: //Goto Parent Directory + // up a directory + //Remove a directory from RomPath and rescan + //Code below will never let you go further up than \SD Card\ on the Gizmondo + //This is by design. + for(i=strlen(romDir)-1;i>0;i--) // don't want to change first char in screen + { + if((romDir[i] == dirSep[0]) || (romDir[i] == dirSepBad[0])) + { + romDir[i] = 0; + break; + } + } + FileScan(); + RESET_NAME_SCROLL + RESET_SCREENSHOT_COUNTER + focus=ROM_SELECTOR_DEFAULT_FOCUS; // default menu to non menu item + // just to stop directory scan being started + smooth=focus<<8; + memset(&headerDone,0,sizeof(headerDone)); //clear header + break; + + case ROM_SELECTOR_DEFAULT_FOCUS: //blank space - do nothing + break; + + default: + // normal file or dir selected + if (romList[focus].type == FILE_TYPE_DIRECTORY) + { + //Just check we are not in root dir as this will always have + //a trailing directory seperater which screws with things + sprintf(romDir,"%s%s%s",romDir,DIR_SEP,romList[focus].filename); + FileScan(); + RESET_NAME_SCROLL + RESET_SCREENSHOT_COUNTER + focus=ROM_SELECTOR_DEFAULT_FOCUS; // default menu to non menu item + // just to stop directory scan being started + smooth=focus<<8; + } + else + { + // user has selected a rom, so load it + sprintf(currentRomFilename,romList[focus].filename); + quickSavePresent=0; // reset any quick saves + action=1; + menuExit=1; + } + break; + } + } + + if (Inp.held[INP_BUTTON_MENU_DELETE]==1) + { + if(focus>ROM_SELECTOR_DEFAULT_FOCUS) + { + //delete current rom + if (romList[focus].type != FILE_TYPE_DIRECTORY) + { + sprintf(text,"%s",romList[focus].filename); + + if(MenuMessageBox("Are you sure you want to delete",text,"",0)==0) + { + deleterom(focus); + RESET_NAME_SCROLL + RESET_SCREENSHOT_COUNTER + } + } + } + } + #define MAX_WIDTH (39 * 8) + + if (timeToScreenshot) timeToScreenshot--; + else if ((!bmpScreenshot) && (focus > ROM_SELECTOR_DEFAULT_FOCUS) && (!noScreenshot)) { + char png_fn[1024]; + char *ext; + gBITMAP *b; + // Compose focused filename + screenshots dir + snprintf(png_fn, sizeof(png_fn), "%s/%s", getScreenShotsDir(), romList[focus].filename); + // set file ext to .png + ext = strrchr(png_fn, '.'); + if (!ext) ext = &png_fn[strlen(png_fn)]; + strcpy(ext, ".png"); + // load screenshot + b = load_png(png_fn, NULL); + if (!b) noScreenshot = 1; + else { + unsigned int sh, sw; + sh = MENU_AREA_Y_END - MENU_AREA_Y_START - 2 + 1; + sw = (sh * b->w)/ b->h; + bmpScreenshot = gStretchBitmap(b, sw, sh); + gDestroyBitmap(b); + if (!bmpScreenshot) noScreenshot = 1; + else xScreenshot = SCREEN_WIDTH - 2; + } + } + + // Draw screen: + PrintTile(currFB); + PrintTitle(currFB); + sprintf(text,"%s:%s",mode?"Select Rom":"Delete Rom",romDir); + gp_setClipping(0, 0, 319, 239); + gp_drawString(6,35,strlen(text)>=40?39:strlen(text),text,tTextColorTitle,framebuffer16[currFB]); + //gp_setClipping(8, MENU_AREA_Y_START, 8 + MAX_WIDTH, MENU_AREA_Y_END); + + // Draw focused file's screenshot + if (bmpScreenshot) { + //unsigned int sh, sw; + //sh = MENU_AREA_Y_END - MENU_AREA_Y_START - 2 + 1; + //sw = (sh * bmpScreenshot->w)/ bmpScreenshot->h; + //gDrawScaledBitmap16(framebuffer16[currFB], xScreenshot, MENU_AREA_Y_START + 1, bmpScreenshot, sw, sh); + //if (xScreenshot > (SCREEN_WIDTH - sw - 4)) xScreenshot -= 2; + gDrawBitmap16(framebuffer16[currFB], xScreenshot, MENU_AREA_Y_START + 1, bmpScreenshot, 0, 0, bmpScreenshot->w, bmpScreenshot->h); + if (xScreenshot > (SCREEN_WIDTH - bmpScreenshot->w - 4)) xScreenshot -= 8; + } + + smooth=smooth*7+(focus<<8); smooth>>=3; + + scanstart=focus-15; + if (scanstart<0) scanstart=0; + scanend = focus+15; + if (scanend>romCount) scanend=romCount; + + for (i=scanstart;i>4); + x=8; + y+=112; + if (y<= (MENU_AREA_Y_START - 8) || y>=232) continue; + + gp_setClipping(8, MENU_AREA_Y_START, 8 + MAX_WIDTH, MENU_AREA_Y_END); + romname_length=strlen(romList[i].filename); + if (i==focus) + { + color=tTextColorFocus; + PrintBar(currFB,y-4); + if ((romname_length * 8) > MAX_WIDTH) { // let's scroll romname if length is bigger than screen width + if (frame == 0) txt_offset += txt_dir; // one of each 4 frames + if (txt_offset == 1) {txt_offset = 0; txt_dir = -1;} + if ((romname_length * 8 + txt_offset) < MAX_WIDTH) txt_dir = 1; + offset = txt_offset; + } + } + else + { + color=tTextColorItem; + if (bmpScreenshot) gp_setClipping(8, MENU_AREA_Y_START, xScreenshot - 1, MENU_AREA_Y_END); + } + + // Draw Directory icon if current entry is a directory + if(romList[i].type == FILE_TYPE_DIRECTORY) + { + gp_drawString(x-8,y,1,"+",color,framebuffer16[currFB]); + } + + gp_drawString(x + offset, y, romname_length,romList[i].filename,color,framebuffer16[currFB]); + } + gp_setClipping(0, 0, 319, 239); + frame = (frame + 1) & 3; + MenuFlip(); + } + + gDestroyBitmap(bmpScreenshot); + return action; +} + +static void ScanSaveStates(char *romname) +{ + FILE *stream; + int i=0; + char savename[MAX_PATH+1]; + char filename[MAX_PATH+1]; + char ext[MAX_PATH+1]; + + if(!strcmp(romname,saveStateName)) return; // is current save state rom so exit + + SplitFilename(romname,filename,ext); + + sprintf(savename,"%s.%s",filename,SAVESTATE_EXT); + + for(i=0;i<10;i++) + { + /* + need to build a save state filename + all saves are held in current working directory (snesSaveStateDir) + save filename has following format + shortname(minus file ext) + SV + saveno ( 0 to 9 ) + */ + sprintf(saveState[i].filename,"%s%d",savename,i); + sprintf(saveState[i].fullFilename,"%s%s%s",snesSaveStateDir,DIR_SEP,saveState[i].filename); + stream=(FILE*)fopen(saveState[i].fullFilename,"rb"); + if(stream) + { + // we have a savestate + saveState[i].inUse = 1; + fclose(stream); + } + else + { + // no save state + saveState[i].inUse = 0; + } + } + strcpy(saveStateName,romname); // save the last scanned romname +} + +void LoadStateFile(char *filename) +{ + S9xUnfreezeGame(filename); +} + +static void SaveStateFile(char *filename) +{ + S9xFreezeGame(filename); + sync(); +} + +static int SaveStateSelect(int mode) +{ + char text[128]; + int action=11; + int saveno=0; + + if(currentRomFilename[0]==0) + { + // no rom loaded + // display error message and exit + return(0); + } + + memset(&headerDone,0,sizeof(headerDone)); + ScanSaveStates(currentRomFilename); + + while (action!=0&&action!=100) + { + InputUpdate(0); + if(Inp.held[INP_BUTTON_UP]==1) {saveno--; action=1;} + if(Inp.held[INP_BUTTON_DOWN]==1) {saveno++; action=1;} + if(saveno<-1) saveno=9; + if(saveno>9) saveno=-1; + + if(Inp.held[INP_BUTTON_MENU_CANCEL]==1) action=0; // exit + else if((Inp.held[INP_BUTTON_MENU_SELECT]==1)&&(saveno==-1)) action=0; // exit + else if((Inp.held[INP_BUTTON_MENU_SELECT]==1)&&(mode==0)&&((action==2)||(action==5))) action=6; // pre-save mode + else if((Inp.held[INP_BUTTON_MENU_SELECT]==1)&&(mode==1)&&(action==5)) action=8; // pre-load mode + else if((Inp.held[INP_BUTTON_MENU_SELECT]==1)&&(mode==2)&&(action==5)) + { + if(MenuMessageBox("Are you sure you want to delete","this save?","",0)==0) action=13; //delete slot with no preview + } + //else if((Inp.held[INP_BUTTON_R]==1)&&(action==12)) action=3; // preview slot mode + else if((Inp.held[INP_BUTTON_MENU_SELECT]==1)&&(mode==1)&&(action==12)) action=8; //load slot with no preview + else if((Inp.held[INP_BUTTON_MENU_SELECT]==1)&&(mode==0)&&(action==12)) action=6; //save slot with no preview + else if((Inp.held[INP_BUTTON_MENU_SELECT]==1)&&(mode==2)&&(action==12)) + { + if(MenuMessageBox("Are you sure you want to delete","this save?","",0)==0) action=13; //delete slot with no preview + } + + PrintTile(currFB); + PrintTitle(currFB); + if(mode==SAVESTATE_MODE_SAVE) gp_drawString(6,35,10,"Save State",tTextColorTitle,framebuffer16[currFB]); + if(mode==SAVESTATE_MODE_LOAD) gp_drawString(6,35,10,"Load State",tTextColorTitle,framebuffer16[currFB]); + if(mode==SAVESTATE_MODE_DELETE) gp_drawString(6,35,12,"Delete State",tTextColorTitle,framebuffer16[currFB]); + sprintf(text,"Press UP and DOWN to change save slot"); + gp_drawString(12,230,strlen(text),text,(unsigned short)MENU_RGB(31,15,5),framebuffer16[currFB]); + + if(saveno==-1) + { + if(action!=10&&action!=0) + { + action=10; + } + } + else + { + PrintBar(currFB,60-4); + sprintf(text,"SLOT %d",saveno); + gp_drawString(136,60,strlen(text),text,tTextColorItem,framebuffer16[currFB]); + } + + switch(action) + { + case 1: + //gp_drawString(112,145,14,"Checking....",tTextColorItem,framebuffer16[currFB]); + break; + case 2: + gp_drawString(144,145,4,"FREE",tTextColorItem,framebuffer16[currFB]); + break; + case 3: + gp_drawString(104,145,14,"Previewing....",tTextColorItem,framebuffer16[currFB]); + break; + case 4: + gp_drawString(88,145,18,"Previewing....fail",tTextColorItem,framebuffer16[currFB]); + break; + case 5: + gp_drawString(112,145,17, "Not gonna happen!",tTextColorItem,framebuffer16[currFB]); + if(mode==1) gp_drawString((320-(strlen(MENU_TEXT_LOAD_SAVESTATE)<<3))>>1,210,strlen(MENU_TEXT_LOAD_SAVESTATE), MENU_TEXT_LOAD_SAVESTATE,tTextColorItem,framebuffer16[currFB]); + else if(mode==0) gp_drawString((320-(strlen(MENU_TEXT_OVERWRITE_SAVESTATE)<<3))>>1,210,strlen(MENU_TEXT_OVERWRITE_SAVESTATE), MENU_TEXT_OVERWRITE_SAVESTATE,tTextColorItem,framebuffer16[currFB]); + else if(mode==2) gp_drawString((320-(strlen(MENU_TEXT_DELETE_SAVESTATE)<<3))>>1,210,strlen(MENU_TEXT_DELETE_SAVESTATE), MENU_TEXT_DELETE_SAVESTATE,tTextColorItem,framebuffer16[currFB]); + break; + case 6: + gp_drawString(124,145,9,"Saving...",tTextColorItem,framebuffer16[currFB]); + break; + case 7: + gp_drawString(124,145,14,"Saving...Fail!",tTextColorItem,framebuffer16[currFB]); + break; + case 8: + gp_drawString(116,145,11,"loading....",tTextColorItem,framebuffer16[currFB]); + break; + case 9: + gp_drawString(116,145,15,"loading....Fail",tTextColorItem,framebuffer16[currFB]); + break; + case 10: + + PrintBar(currFB,145-4); + gp_drawString(104,145,14,"Return To Menu",tTextColorItem,framebuffer16[currFB]); + break; + case 12: + gp_drawString(124,145,9,"Slot used",tTextColorItem,framebuffer16[currFB]); + //gp_drawString((320-(strlen(MENU_TEXT_PREVIEW_SAVESTATE)<<3))>>1,165,strlen(MENU_TEXT_PREVIEW_SAVESTATE),MENU_TEXT_PREVIEW_SAVESTATE,tTextColorItem,framebuffer16[currFB]); + if(mode==1) gp_drawString((320-(strlen(MENU_TEXT_LOAD_SAVESTATE)<<3))>>1,175,strlen(MENU_TEXT_LOAD_SAVESTATE), MENU_TEXT_LOAD_SAVESTATE,tTextColorItem,framebuffer16[currFB]); + else if(mode==0) gp_drawString((320-(strlen(MENU_TEXT_OVERWRITE_SAVESTATE)<<3))>>1,175,strlen(MENU_TEXT_OVERWRITE_SAVESTATE), MENU_TEXT_OVERWRITE_SAVESTATE,tTextColorItem,framebuffer16[currFB]); + else if(mode==2) gp_drawString((320-(strlen(MENU_TEXT_DELETE_SAVESTATE)<<3))>>1,175,strlen(MENU_TEXT_DELETE_SAVESTATE), MENU_TEXT_DELETE_SAVESTATE,tTextColorItem,framebuffer16[currFB]); + break; + case 13: + gp_drawString(116,145,11,"Deleting....",tTextColorItem,framebuffer16[currFB]); + break; + } + + MenuFlip(); + + switch(action) + { + case 1: + if(saveState[saveno].inUse) + { + action=12; + } + else + { + action=2; + } + break; + case 3: + gp_setCpuspeed(MENU_FAST_CPU_SPEED); + LoadStateFile(saveState[saveno].fullFilename); + gp_setCpuspeed(MENU_CPU_SPEED); + action=5; + break; + case 6: + gp_setCpuspeed(MENU_FAST_CPU_SPEED); + SaveStateFile(saveState[saveno].fullFilename); + gp_setCpuspeed(MENU_CPU_SPEED); + saveState[saveno].inUse=1; + action=1; + break; + case 7: + action=1; + break; + case 8: + LoadStateFile(saveState[saveno].fullFilename); + action=100; // loaded ok so exit + break; + case 9: + action=1; + break; + case 11: + action=1; + break; + case 13: + remove(saveState[saveno].fullFilename); + sync(); + saveState[saveno].inUse = 0; + action=1; + break; + } + } + memset(&headerDone,0,sizeof(headerDone)); + return(action); +} + +static +void RenderMenu(char *menuName, int menuCount, int menuSmooth, int menufocus) +{ + int i=0; + char text[50]; + unsigned short color=0; + PrintTile(currFB); + PrintTitle(currFB); + + gp_setClipping(0, 0, 319, 239); + gp_drawString(6,35,strlen(menuName),menuName,tTextColorTitle,framebuffer16[currFB]); + gp_setClipping(8, MENU_AREA_Y_START, SCREEN_WIDTH - 8, MENU_AREA_Y_END); + + // RRRRRGGGGGBBBBBI gp32 color format + for (i=0;i>4); + x=8; + y+=112; + + if (y<= (MENU_AREA_Y_START - 8) || y>=232) continue; + + if (i==menufocus) + { + color=tTextColorFocus; + PrintBar(currFB,y-4); + } + else + { + color=tTextColorItem; + } + + sprintf(text,"%s",menutext[i]); + gp_drawString(x,y,strlen(text),text,color,framebuffer16[currFB]); + } + gp_setClipping(0, 0, 319, 239); +} + +static +int LoadRomMenu(void) +{ + int menuExit=0,menuCount=LOAD_ROM_MENU_COUNT,menufocus=0,menuSmooth=0; + int action=0; + int subaction=0; + + memset(&headerDone,0,sizeof(headerDone)); + strcpy(romDir,snesRomDir); + subaction=FileSelect(0); + memset(&headerDone,0,sizeof(headerDone)); + if(subaction) + { + action=EVENT_LOAD_SNES_ROM; + menuExit=1; + } + + return action; +} + +static +int SaveStateMenu(void) +{ + int menuExit=0,menuCount=SAVESTATE_MENU_COUNT,menufocus=0,menuSmooth=0; + int action=0; + int subaction=0; + + memset(&headerDone,0,sizeof(headerDone)); + + //Update + sprintf(menutext[SAVESTATE_MENU_LOAD],"Load State"); + sprintf(menutext[SAVESTATE_MENU_SAVE],"Save State"); + sprintf(menutext[SAVESTATE_MENU_DELETE],"Delete State"); + sprintf(menutext[SAVESTATE_MENU_RETURN],"Back"); + + while (!menuExit) + { + InputUpdate(0); + + // Change which rom is focused on: + if (Inp.repeat[INP_BUTTON_UP]) menufocus--; // Up + if (Inp.repeat[INP_BUTTON_DOWN]) menufocus++; // Down + + if (Inp.held[INP_BUTTON_MENU_CANCEL]==1 ) menuExit=1; + + if (menufocus>menuCount-1) + { + menufocus=0; + menuSmooth=(menufocus<<8)-1; + } + else if (menufocus<0) + { + menufocus=menuCount-1; + menuSmooth=(menufocus<<8)-1; + } + + if (Inp.held[INP_BUTTON_MENU_SELECT]==1) + { + switch(menufocus) + { + case SAVESTATE_MENU_LOAD: + subaction=SaveStateSelect(SAVESTATE_MODE_LOAD); + if(subaction==100) + { + menuExit=1; + action=100; + } + break; + case SAVESTATE_MENU_SAVE: + SaveStateSelect(SAVESTATE_MODE_SAVE); + break; + case SAVESTATE_MENU_DELETE: + SaveStateSelect(SAVESTATE_MODE_DELETE); + break; + case SAVESTATE_MENU_RETURN: + menuExit=1; + break; + } + } + // Draw screen: + menuSmooth=menuSmooth*7+(menufocus<<8); menuSmooth>>=3; + RenderMenu("Save States", menuCount,menuSmooth,menufocus); + MenuFlip(); + + } + + return action; +} + +static +int SramMenu(void) +{ + int menuExit=0,menuCount=SRAM_MENU_COUNT,menufocus=0,menuSmooth=0; + int action=0; + int subaction=0; + char *srammem=NULL; + + + memset(&headerDone,0,sizeof(headerDone)); + + //Update + sprintf(menutext[SRAM_MENU_LOAD],"Load SRAM"); + sprintf(menutext[SRAM_MENU_SAVE],"Save SRAM"); + sprintf(menutext[SRAM_MENU_DELETE],"Delete SRAM"); + sprintf(menutext[SRAM_MENU_RETURN],"Back"); + + while (!menuExit) + { + InputUpdate(0); + + // Change which rom is focused on: + if (Inp.repeat[INP_BUTTON_UP]) menufocus--; // Up + if (Inp.repeat[INP_BUTTON_DOWN]) menufocus++; // Down + + if (Inp.held[INP_BUTTON_MENU_CANCEL]==1 ) menuExit=1; + + if (menufocus>menuCount-1) + { + menufocus=0; + menuSmooth=(menufocus<<8)-1; + } + else if (menufocus<0) + { + menufocus=menuCount-1; + menuSmooth=(menufocus<<8)-1; + } + + if (Inp.held[INP_BUTTON_MENU_SELECT]==1) + { + switch(menufocus) + { + case SRAM_MENU_LOAD: + //LoadSram(snesSramDir,currentRomFilename,SRAM_FILE_EXT,(char*)&sram); + break; + case SRAM_MENU_SAVE: + //SaveSram(snesSramDir,currentRomFilename,SRAM_FILE_EXT,(char*)&sram); + break; + case SRAM_MENU_DELETE: + //DeleteSram(snesSramDir,currentRomFilename,SRAM_FILE_EXT); + break; + case SRAM_MENU_RETURN: + menuExit=1; + break; + } + } + // Draw screen: + menuSmooth=menuSmooth*7+(menufocus<<8); menuSmooth>>=3; + RenderMenu("SRAM", menuCount,menuSmooth,menufocus); + MenuFlip(); + + } + + return action; +} + +static +void SNESOptionsUpdateText(int menu_index) +{ + switch(menu_index) + { + case SNES_MENU_SOUND: + switch(snesMenuOptions.soundOn) + { + case 0: + sprintf(menutext[SNES_MENU_SOUND],"Sound: OFF"); + break; + case 1: + sprintf(menutext[SNES_MENU_SOUND],"Sound: ON"); + break; + } + break; + + case SNES_MENU_SOUND_RATE: + if (snesMenuOptions.stereo) + sprintf(menutext[SNES_MENU_SOUND_RATE],"Sound Rate: %d stereo",(unsigned int)soundRates[snesMenuOptions.soundRate]); + else + sprintf(menutext[SNES_MENU_SOUND_RATE],"Sound Rate: %d mono",(unsigned int)soundRates[snesMenuOptions.soundRate]); + break; +#if defined(__GP2X__) || defined(__WIZ__) + case SNES_MENU_CPUSPEED: + sprintf(menutext[SNES_MENU_CPUSPEED],"Cpu Speed: %d",(unsigned int)cpuSpeedLookup[snesMenuOptions.cpuSpeed]); + break; +#endif + case SNES_MENU_SOUND_VOL: + sprintf(menutext[SNES_MENU_SOUND_VOL],"Volume: %d",snesMenuOptions.volume); + break; + + case SNES_MENU_FRAMESKIP: + switch(snesMenuOptions.frameSkip) + { + case 0: + sprintf(menutext[SNES_MENU_FRAMESKIP],"Frameskip: AUTO"); + break; + default: + sprintf(menutext[SNES_MENU_FRAMESKIP],"Frameskip: %d",snesMenuOptions.frameSkip-1); + break; + } + break; + + case SNES_MENU_REGION: + switch(snesMenuOptions.region) + { + case 0: + sprintf(menutext[SNES_MENU_REGION],"Region: AUTO"); + break; + case 1: + sprintf(menutext[SNES_MENU_REGION],"Region: NTSC"); + break; + case 2: + sprintf(menutext[SNES_MENU_REGION],"Region: PAL"); + break; + } + break; + + case SNES_MENU_FPS: + switch(snesMenuOptions.showFps) + { + case 0: + sprintf(menutext[SNES_MENU_FPS],"Show FPS: OFF"); + break; + case 1: + sprintf(menutext[SNES_MENU_FPS],"Show FPS: ON"); + break; + } + break; +#if defined(__GP2X__) + case SNES_MENU_GAMMA: + sprintf(menutext[SNES_MENU_GAMMA],"Brightness: %d",snesMenuOptions.gamma+100); + break; +#endif + case SNES_MENU_TRANSPARENCY: + switch(snesMenuOptions.transparency) + { + case 0: + sprintf(menutext[SNES_MENU_TRANSPARENCY],"Transparencies: OFF"); + break; + case 1: + sprintf(menutext[SNES_MENU_TRANSPARENCY],"Transparencies: ON"); + break; + } + break; + + case SNES_MENU_LOAD_GLOBAL: + sprintf(menutext[SNES_MENU_LOAD_GLOBAL],"Load Global Settings"); + break; + + case SNES_MENU_SAVE_GLOBAL: + sprintf(menutext[SNES_MENU_SAVE_GLOBAL],"Save Global Settings"); + break; + + case SNES_MENU_DELETE_GLOBAL: + sprintf(menutext[SNES_MENU_DELETE_GLOBAL],"Delete Global Settings"); + break; + + case SNES_MENU_LOAD_CURRENT: + sprintf(menutext[SNES_MENU_LOAD_CURRENT],"Load Settings For Current Game"); + break; + + case SNES_MENU_SAVE_CURRENT: + sprintf(menutext[SNES_MENU_SAVE_CURRENT],"Save Settings For Current Game"); + break; + + case SNES_MENU_DELETE_CURRENT: + sprintf(menutext[SNES_MENU_DELETE_CURRENT],"Delete Settings For Current Game"); + break; + + case SNES_MENU_SET_ROMDIR: + sprintf(menutext[SNES_MENU_SET_ROMDIR],"Save Current Rom Directory"); + break; + + case SNES_MENU_CLEAR_ROMDIR: + sprintf(menutext[SNES_MENU_CLEAR_ROMDIR],"Reset Default Rom Directory"); + break; + + case SNES_MENU_RETURN: + sprintf(menutext[SNES_MENU_RETURN],"Back"); + break; +#if defined(__GP2X__) || defined(__WIZ__) + case SNES_MENU_RENDER_MODE: + switch(snesMenuOptions.renderMode) + { + case RENDER_MODE_UNSCALED: + sprintf(menutext[SNES_MENU_RENDER_MODE],"Render Mode: Unscaled"); + break; + case RENDER_MODE_SCALED: + sprintf(menutext[SNES_MENU_RENDER_MODE],"Render Mode: Scaled"); + break; + case RENDER_MODE_HORIZONTAL_SCALED: + sprintf(menutext[SNES_MENU_RENDER_MODE],"Render Mode: Horizontal Scaled"); + break; + default: + sprintf(menutext[SNES_MENU_RENDER_MODE],"Render Mode: Unscaled"); + break; + } + break; + case SNES_MENU_ACTION_BUTTONS: + switch(snesMenuOptions.actionButtons) + { + case 0: + sprintf(menutext[SNES_MENU_ACTION_BUTTONS],"Action Buttons: Normal"); + break; + case 1: + sprintf(menutext[SNES_MENU_ACTION_BUTTONS],"Action Buttons: Swapped"); + break; + } + break; +#endif + case SNES_MENU_AUTO_SAVE_SRAM: + switch(snesMenuOptions.autoSram) + { + case 0: + sprintf(menutext[SNES_MENU_AUTO_SAVE_SRAM],"Saving SRAM: Manual"); + break; + case 1: + sprintf(menutext[SNES_MENU_AUTO_SAVE_SRAM],"Saving SRAM: Automatic"); + break; + case 2: + sprintf(menutext[SNES_MENU_AUTO_SAVE_SRAM],"Saving SRAM: Manual + indicator"); + break; + } + break; + case SNES_MENU_EMULATION_TYPE: + switch(snesMenuOptions.asmspc700) + { + case 0: + sprintf(menutext[SNES_MENU_EMULATION_TYPE],"Emulation (Reset Required): Compatible"); + break; + case 1: + sprintf(menutext[SNES_MENU_EMULATION_TYPE],"Emulation (Reset Required): Fast"); + break; + } + break; + case SNES_MENU_LOAD_ROM_ON_INIT: + switch(snesMenuOptions.loadOnInit) + { + case 0: + sprintf(menutext[SNES_MENU_LOAD_ROM_ON_INIT],"Load last played ROM at startup: OFF"); + break; + case 1: + sprintf(menutext[SNES_MENU_LOAD_ROM_ON_INIT],"Load last played ROM at startup: ON"); + break; + } + break; + case SNES_MENU_ADVANCED_HACKS: + sprintf(menutext[SNES_MENU_ADVANCED_HACKS],"Advanced hacks"); + break; + } +} + +static +void SNESHacksUpdateText(int menu_index) +{ + switch(menu_index) + { + case HACKS_MENU_SNESADVANCE_DAT: + if (snesMenuOptions.SpeedHacks) + sprintf(menutext[HACKS_MENU_SNESADVANCE_DAT],"Apply snesadvance.dat on ROM load: ON"); + else + sprintf(menutext[HACKS_MENU_SNESADVANCE_DAT],"Apply snesadvance.dat on ROM load: OFF"); + break; + case HACKS_MENU_AUDIO: + if(snesMenuOptions.soundHack) + sprintf(menutext[HACKS_MENU_AUDIO],"Audio Performance hack: ON"); + else + sprintf(menutext[HACKS_MENU_AUDIO],"Audio Performance hack: OFF"); + break; +#ifdef __OLD_RASTER_FX__ + case HACKS_MENU_DELAYED_RASTER_FX: + sprintf(menutext[HACKS_MENU_DELAYED_RASTER_FX], "Delayed Raster FX: %s", snesMenuOptions.delayedRasterFX ? "ON" : "OFF"); + break; +#endif + case HACKS_MENU_PALETTE: + if(snesMenuOptions.graphHacks & PPU_IGNORE_PALWRITE) + sprintf(menutext[HACKS_MENU_PALETTE],"Ignore Palette writes: ON"); + else + sprintf(menutext[HACKS_MENU_PALETTE],"Ignore Palette writes: OFF"); + break; + case HACKS_MENU_FIXEDCOL: + if(snesMenuOptions.graphHacks & PPU_IGNORE_FIXEDCOLCHANGES) + sprintf(menutext[HACKS_MENU_FIXEDCOL],"Ignore Fixed Colour: ON"); + else + sprintf(menutext[HACKS_MENU_FIXEDCOL],"Ignore Fixed Colour: OFF"); + break; + case HACKS_MENU_WINDOW: + if(snesMenuOptions.graphHacks & PPU_IGNORE_WINDOW) + sprintf(menutext[HACKS_MENU_WINDOW],"Ignore Windows clipping: ON"); + else + sprintf(menutext[HACKS_MENU_WINDOW],"Ignore Windows clipping: OFF"); + break; + case HACKS_MENU_ADDSUB: + if(snesMenuOptions.graphHacks & PPU_IGNORE_ADDSUB) + sprintf(menutext[HACKS_MENU_ADDSUB],"Ignore Add/Sub modes: ON"); + else + sprintf(menutext[HACKS_MENU_ADDSUB],"Ignore Add/Sub modes: OFF"); + break; + case HACKS_MENU_OBJ: + if(snesMenuOptions.graphHacks & GFX_IGNORE_OBJ) + sprintf(menutext[HACKS_MENU_OBJ],"Ignore objects layer: ON"); + else + sprintf(menutext[HACKS_MENU_OBJ],"Ignore objects layer: OFF"); + break; + case HACKS_MENU_BG0: + if(snesMenuOptions.graphHacks & GFX_IGNORE_BG0) + sprintf(menutext[HACKS_MENU_BG0],"Ignore background layer 0: ON"); + else + sprintf(menutext[HACKS_MENU_BG0],"Ignore background layer 0: OFF"); + break; + case HACKS_MENU_BG1: + if(snesMenuOptions.graphHacks & GFX_IGNORE_BG1) + sprintf(menutext[HACKS_MENU_BG1],"Ignore background layer 1: ON"); + else + sprintf(menutext[HACKS_MENU_BG1],"Ignore background layer 1: OFF"); + break; + case HACKS_MENU_BG2: + if(snesMenuOptions.graphHacks & GFX_IGNORE_BG2) + sprintf(menutext[HACKS_MENU_BG2],"Ignore background layer 2: ON"); + else + sprintf(menutext[HACKS_MENU_BG2],"Ignore background layer 2: OFF"); + break; + case HACKS_MENU_BG3: + if(snesMenuOptions.graphHacks & GFX_IGNORE_BG3) + sprintf(menutext[HACKS_MENU_BG3],"Ignore background layer 3: ON"); + else + sprintf(menutext[HACKS_MENU_BG3],"Ignore background layer 3: OFF"); + break; + case HACKS_MENU_RETURN: + sprintf(menutext[HACKS_MENU_RETURN],"Back"); + break; + + + } +} + +static +void SNESHacksUpdateText_All() +{ + SNESHacksUpdateText(HACKS_MENU_AUDIO); + SNESHacksUpdateText(HACKS_MENU_SNESADVANCE_DAT); +#ifdef __OLD_RASTER_FX__ + SNESHacksUpdateText(HACKS_MENU_DELAYED_RASTER_FX); +#endif + SNESHacksUpdateText(HACKS_MENU_PALETTE); + SNESHacksUpdateText(HACKS_MENU_FIXEDCOL); + SNESHacksUpdateText(HACKS_MENU_WINDOW); + SNESHacksUpdateText(HACKS_MENU_ADDSUB); + SNESHacksUpdateText(HACKS_MENU_OBJ); + SNESHacksUpdateText(HACKS_MENU_BG0); + SNESHacksUpdateText(HACKS_MENU_BG1); + SNESHacksUpdateText(HACKS_MENU_BG2); + SNESHacksUpdateText(HACKS_MENU_BG3); + SNESHacksUpdateText(HACKS_MENU_RETURN); +} + +static +int SNESHacksMenu(void) +{ + int menuExit=0,menuCount=HACKS_MENU_COUNT,menufocus=0,menuSmooth=0; + int action=0; + int subaction=0; + + memset(&headerDone,0,sizeof(headerDone)); + + //Update all items + SNESHacksUpdateText_All(); + + while (!menuExit) + { + InputUpdate(0); + + // Change which rom is focused on: + if (Inp.repeat[INP_BUTTON_UP]) menufocus--; // Up + if (Inp.repeat[INP_BUTTON_DOWN]) menufocus++; // Down + + if (Inp.held[INP_BUTTON_MENU_CANCEL]==1 ) menuExit=1; + + if (menufocus>menuCount-1) + { + menufocus=0; + menuSmooth=(menufocus<<8)-1; + } + else if (menufocus<0) + { + menufocus=menuCount-1; + menuSmooth=(menufocus<<8)-1; + + } + + if (Inp.held[INP_BUTTON_LEFT]==1|| + Inp.held[INP_BUTTON_RIGHT]==1|| + Inp.repeat[INP_BUTTON_LEFT]|| + Inp.repeat[INP_BUTTON_RIGHT]) + { + switch(menufocus) + { + case HACKS_MENU_SNESADVANCE_DAT: + snesMenuOptions.SpeedHacks^=1; + SNESHacksUpdateText(HACKS_MENU_SNESADVANCE_DAT); + break; + case HACKS_MENU_AUDIO: + snesMenuOptions.soundHack^=1; + SNESHacksUpdateText(HACKS_MENU_AUDIO); + break; +#ifdef __OLD_RASTER_FX__ + case HACKS_MENU_DELAYED_RASTER_FX: + snesMenuOptions.delayedRasterFX ^= 1; + SNESHacksUpdateText(HACKS_MENU_DELAYED_RASTER_FX); + break; +#endif + case HACKS_MENU_PALETTE: + if (snesMenuOptions.graphHacks & PPU_IGNORE_PALWRITE) + snesMenuOptions.graphHacks &= ~PPU_IGNORE_PALWRITE; + else + snesMenuOptions.graphHacks |= PPU_IGNORE_PALWRITE; + SNESHacksUpdateText(HACKS_MENU_PALETTE); + break; + case HACKS_MENU_FIXEDCOL: + if (snesMenuOptions.graphHacks & PPU_IGNORE_FIXEDCOLCHANGES) + snesMenuOptions.graphHacks &= ~PPU_IGNORE_FIXEDCOLCHANGES; + else + snesMenuOptions.graphHacks |= PPU_IGNORE_FIXEDCOLCHANGES; + SNESHacksUpdateText(HACKS_MENU_FIXEDCOL); + break; + case HACKS_MENU_WINDOW: + if (snesMenuOptions.graphHacks & PPU_IGNORE_WINDOW) + snesMenuOptions.graphHacks &= ~PPU_IGNORE_WINDOW; + else + snesMenuOptions.graphHacks |= PPU_IGNORE_WINDOW; + SNESHacksUpdateText(HACKS_MENU_WINDOW); + break; + case HACKS_MENU_ADDSUB: + if (snesMenuOptions.graphHacks & PPU_IGNORE_ADDSUB) + snesMenuOptions.graphHacks &= ~PPU_IGNORE_ADDSUB; + else + snesMenuOptions.graphHacks |= PPU_IGNORE_ADDSUB; + SNESHacksUpdateText(HACKS_MENU_ADDSUB); + + break; + case HACKS_MENU_OBJ: + if (snesMenuOptions.graphHacks & GFX_IGNORE_OBJ) + snesMenuOptions.graphHacks &= ~GFX_IGNORE_OBJ; + else + snesMenuOptions.graphHacks |= GFX_IGNORE_OBJ; + SNESHacksUpdateText(HACKS_MENU_OBJ); + break; + case HACKS_MENU_BG0: + if (snesMenuOptions.graphHacks & GFX_IGNORE_BG0) + snesMenuOptions.graphHacks &= ~GFX_IGNORE_BG0; + else + snesMenuOptions.graphHacks |= GFX_IGNORE_BG0; + SNESHacksUpdateText(HACKS_MENU_BG0); + break; + case HACKS_MENU_BG1: + if (snesMenuOptions.graphHacks & GFX_IGNORE_BG1) + snesMenuOptions.graphHacks &= ~GFX_IGNORE_BG1; + else + snesMenuOptions.graphHacks |= GFX_IGNORE_BG1; + SNESHacksUpdateText(HACKS_MENU_BG1); + break; + case HACKS_MENU_BG2: + if (snesMenuOptions.graphHacks & GFX_IGNORE_BG2) + snesMenuOptions.graphHacks &= ~GFX_IGNORE_BG2; + else + snesMenuOptions.graphHacks |= GFX_IGNORE_BG2; + SNESHacksUpdateText(HACKS_MENU_BG2); + break; + case HACKS_MENU_BG3: + if (snesMenuOptions.graphHacks & GFX_IGNORE_BG3) + snesMenuOptions.graphHacks &= ~GFX_IGNORE_BG3; + else + snesMenuOptions.graphHacks |= GFX_IGNORE_BG3; + SNESHacksUpdateText(HACKS_MENU_BG3); + break; + } + } + if (Inp.held[INP_BUTTON_MENU_SELECT]==1) + { + switch(menufocus) + { + case HACKS_MENU_RETURN: + menuExit=1; + break; + } + } + // Draw screen: + menuSmooth=menuSmooth*7+(menufocus<<8); menuSmooth>>=3; + RenderMenu("SNES Advanced Hacks", menuCount,menuSmooth,menufocus); + MenuFlip(); + + } + + return action; +} + +static +void SNESOptionsUpdateText_All() +{ + SNESOptionsUpdateText(SNES_MENU_SOUND); + SNESOptionsUpdateText(SNES_MENU_SOUND_RATE); + SNESOptionsUpdateText(SNES_MENU_SOUND_VOL); + SNESOptionsUpdateText(SNES_MENU_FRAMESKIP); + SNESOptionsUpdateText(SNES_MENU_REGION); + SNESOptionsUpdateText(SNES_MENU_FPS); + SNESOptionsUpdateText(SNES_MENU_TRANSPARENCY); + SNESOptionsUpdateText(SNES_MENU_LOAD_GLOBAL); + SNESOptionsUpdateText(SNES_MENU_SAVE_GLOBAL); + SNESOptionsUpdateText(SNES_MENU_DELETE_GLOBAL); + SNESOptionsUpdateText(SNES_MENU_LOAD_CURRENT); + SNESOptionsUpdateText(SNES_MENU_SAVE_CURRENT); + SNESOptionsUpdateText(SNES_MENU_DELETE_CURRENT); + SNESOptionsUpdateText(SNES_MENU_SET_ROMDIR); + SNESOptionsUpdateText(SNES_MENU_CLEAR_ROMDIR); + SNESOptionsUpdateText(SNES_MENU_RETURN); +#if defined(__GP2X__) || defined(__WIZ__) + SNESOptionsUpdateText(SNES_MENU_RENDER_MODE); + SNESOptionsUpdateText(SNES_MENU_CPUSPEED); + SNESOptionsUpdateText(SNES_MENU_ACTION_BUTTONS); +#endif +#if defined(__GP2X__) + SNESOptionsUpdateText(SNES_MENU_GAMMA); +#endif + SNESOptionsUpdateText(SNES_MENU_EMULATION_TYPE); + SNESOptionsUpdateText(SNES_MENU_AUTO_SAVE_SRAM); + SNESOptionsUpdateText(SNES_MENU_LOAD_ROM_ON_INIT); + SNESOptionsUpdateText(SNES_MENU_ADVANCED_HACKS); +} + +static +int SNESOptionsMenu(void) +{ + int menuExit=0,menuCount=SNES_MENU_COUNT,menufocus=0,menuSmooth=0; + int action=0; + int subaction=0; + + memset(&headerDone,0,sizeof(headerDone)); + + //Update all items + SNESOptionsUpdateText_All(); + + while (!menuExit) + { + InputUpdate(0); + + // Change which rom is focused on: + if (Inp.repeat[INP_BUTTON_UP]) menufocus--; // Up + if (Inp.repeat[INP_BUTTON_DOWN]) menufocus++; // Down + + if (Inp.held[INP_BUTTON_MENU_CANCEL]==1 ) menuExit=1; + + if (menufocus>menuCount-1) + { + menufocus=0; + menuSmooth=(menufocus<<8)-1; + } + else if (menufocus<0) + { + menufocus=menuCount-1; + menuSmooth=(menufocus<<8)-1; + } + + if (Inp.held[INP_BUTTON_LEFT]==1|| + Inp.held[INP_BUTTON_RIGHT]==1|| + Inp.repeat[INP_BUTTON_LEFT]|| + Inp.repeat[INP_BUTTON_RIGHT]) + { + switch(menufocus) + { + case SNES_MENU_SOUND: + snesMenuOptions.soundOn^=1; + SNESOptionsUpdateText(SNES_MENU_SOUND); + break; + case SNES_MENU_SOUND_RATE: + if (Inp.held[INP_BUTTON_RIGHT]==1||Inp.repeat[INP_BUTTON_RIGHT]) + { + if (!snesMenuOptions.stereo) + snesMenuOptions.stereo = 1; + else + { + snesMenuOptions.soundRate++; + snesMenuOptions.stereo = 0; + } +#if defined(__WIZ__) + if(snesMenuOptions.soundRate>2) snesMenuOptions.soundRate=0; +#else + if(snesMenuOptions.soundRate>4) snesMenuOptions.soundRate=0; +#endif + } + else + { + if (snesMenuOptions.stereo) + snesMenuOptions.stereo = 0; + else + { + snesMenuOptions.soundRate--; + snesMenuOptions.stereo = 1; + } +#if defined(__WIZ__) + if(snesMenuOptions.soundRate>2) snesMenuOptions.soundRate=2; +#else + if(snesMenuOptions.soundRate>4) snesMenuOptions.soundRate=4; +#endif + } + SNESOptionsUpdateText(SNES_MENU_SOUND_RATE); + break; + case SNES_MENU_SOUND_VOL: + if (Inp.held[INP_BUTTON_RIGHT]==1||Inp.repeat[INP_BUTTON_RIGHT]) + { + snesMenuOptions.volume+=1; + if(snesMenuOptions.volume>100) snesMenuOptions.volume=0; + } + else + { + snesMenuOptions.volume-=1; + if(snesMenuOptions.volume>100) snesMenuOptions.volume=100; + } + SNESOptionsUpdateText(SNES_MENU_SOUND_VOL); + break; +#if defined(__GP2X__) || defined(__WIZ__) + case SNES_MENU_CPUSPEED: + if (Inp.held[INP_BUTTON_RIGHT]==1||Inp.repeat[INP_BUTTON_RIGHT]) + { + snesMenuOptions.cpuSpeed++; + if(snesMenuOptions.cpuSpeed>45) snesMenuOptions.cpuSpeed=0; + } + else + { + snesMenuOptions.cpuSpeed--; + if(snesMenuOptions.cpuSpeed>45) snesMenuOptions.cpuSpeed=45; + } + SNESOptionsUpdateText(SNES_MENU_CPUSPEED); + break; +#endif + case SNES_MENU_FRAMESKIP: + if (Inp.held[INP_BUTTON_RIGHT]==1||Inp.repeat[INP_BUTTON_RIGHT]) + { + snesMenuOptions.frameSkip++; + if(snesMenuOptions.frameSkip>6) snesMenuOptions.frameSkip=0; + } + else + { + snesMenuOptions.frameSkip--; + if(snesMenuOptions.frameSkip>6) snesMenuOptions.frameSkip=6; + } + SNESOptionsUpdateText(SNES_MENU_FRAMESKIP); + break; + case SNES_MENU_REGION: + if (Inp.held[INP_BUTTON_RIGHT]==1||Inp.repeat[INP_BUTTON_RIGHT]) + { + snesMenuOptions.region++; + if(snesMenuOptions.region>2) snesMenuOptions.region=0; + } + else + { + snesMenuOptions.region--; + if(snesMenuOptions.region>2) snesMenuOptions.region=2; + } + SNESOptionsUpdateText(SNES_MENU_REGION); + break; + case SNES_MENU_FPS: + snesMenuOptions.showFps^=1; + SNESOptionsUpdateText(SNES_MENU_FPS); + break; +#if defined(__GP2X__) + case SNES_MENU_GAMMA: + if (Inp.held[INP_BUTTON_RIGHT]==1||Inp.repeat[INP_BUTTON_RIGHT]) + { + snesMenuOptions.gamma++; + if(snesMenuOptions.gamma>100) snesMenuOptions.gamma=100; + } + else + { + snesMenuOptions.gamma--; + if(snesMenuOptions.gamma<-100) snesMenuOptions.gamma=-100; + } + set_gamma(snesMenuOptions.gamma+100); + SNESOptionsUpdateText(SNES_MENU_GAMMA); + break; +#endif +#if defined(__GP2X__) || defined(__WIZ__) + case SNES_MENU_ACTION_BUTTONS: + snesMenuOptions.actionButtons^=1; + SNESOptionsUpdateText(SNES_MENU_ACTION_BUTTONS); + break; +#endif + case SNES_MENU_TRANSPARENCY: + snesMenuOptions.transparency^=1; + SNESOptionsUpdateText(SNES_MENU_TRANSPARENCY); + break; +#if defined(__GP2X__) || defined(__WIZ__) + case SNES_MENU_RENDER_MODE: + if (Inp.held[INP_BUTTON_RIGHT]==1||Inp.repeat[INP_BUTTON_RIGHT]) + { + snesMenuOptions.renderMode++; + if (snesMenuOptions.renderMode > RENDER_MODE_HORIZONTAL_SCALED) + snesMenuOptions.renderMode = RENDER_MODE_UNSCALED; + } + else + { + snesMenuOptions.renderMode--; + if (snesMenuOptions.renderMode > RENDER_MODE_HORIZONTAL_SCALED) + snesMenuOptions.renderMode = RENDER_MODE_HORIZONTAL_SCALED; + } + SNESOptionsUpdateText(SNES_MENU_RENDER_MODE); + break; +#endif + case SNES_MENU_AUTO_SAVE_SRAM: + //snesMenuOptions.autoSram^=1; + if ((++snesMenuOptions.autoSram) > 2) snesMenuOptions.autoSram = 0; + SNESOptionsUpdateText(SNES_MENU_AUTO_SAVE_SRAM); + break; + case SNES_MENU_EMULATION_TYPE: + snesMenuOptions.asmspc700^=1; + SNESOptionsUpdateText(SNES_MENU_EMULATION_TYPE); + break; + case SNES_MENU_LOAD_ROM_ON_INIT: + snesMenuOptions.loadOnInit ^= 1; + SNESOptionsUpdateText(SNES_MENU_LOAD_ROM_ON_INIT); + break; + + } + } + if (Inp.held[INP_BUTTON_MENU_SELECT]==1) + { + switch(menufocus) + { + case SNES_MENU_ADVANCED_HACKS: + memset(&headerDone,0,sizeof(headerDone)); + subaction = SNESHacksMenu(); + memset(&headerDone,0,sizeof(headerDone)); + SNESOptionsUpdateText_All(); + break; + case SNES_MENU_LOAD_GLOBAL: + LoadMenuOptions(snesOptionsDir, MENU_OPTIONS_FILENAME, MENU_OPTIONS_EXT, (char*)&snesMenuOptions, sizeof(snesMenuOptions),1); + SNESOptionsUpdateText_All(); + break; + case SNES_MENU_SAVE_GLOBAL: + SaveMenuOptions(snesOptionsDir, MENU_OPTIONS_FILENAME, MENU_OPTIONS_EXT, (char*)&snesMenuOptions, sizeof(snesMenuOptions),1); + break; + case SNES_MENU_DELETE_GLOBAL: + DeleteMenuOptions(snesOptionsDir,MENU_OPTIONS_FILENAME,MENU_OPTIONS_EXT,1); + break; + case SNES_MENU_LOAD_CURRENT: + if(currentRomFilename[0]!=0) + { + LoadMenuOptions(snesOptionsDir, currentRomFilename, MENU_OPTIONS_EXT, (char*)&snesMenuOptions, sizeof(snesMenuOptions),1); + SNESOptionsUpdateText_All(); + } + break; + case SNES_MENU_SAVE_CURRENT: + if(currentRomFilename[0]!=0) + { + SaveMenuOptions(snesOptionsDir, currentRomFilename, MENU_OPTIONS_EXT, (char*)&snesMenuOptions, sizeof(snesMenuOptions),1); + } + break; + case SNES_MENU_DELETE_CURRENT: + if(currentRomFilename[0]!=0) + { + DeleteMenuOptions(snesOptionsDir, currentRomFilename, MENU_OPTIONS_EXT,1); + } + break; + case SNES_MENU_SET_ROMDIR: + SaveMenuOptions(snesOptionsDir, DEFAULT_ROM_DIR_FILENAME, DEFAULT_ROM_DIR_EXT, romDir, strlen(romDir),1); + strcpy(snesRomDir,romDir); + break; + case SNES_MENU_CLEAR_ROMDIR: + DeleteMenuOptions(snesOptionsDir, DEFAULT_ROM_DIR_FILENAME, DEFAULT_ROM_DIR_EXT,1); + strcpy(snesRomDir,currentWorkingDir); + break; + case SNES_MENU_RETURN: + menuExit=1; + break; + } + } + // Draw screen: + menuSmooth=menuSmooth*7+(menufocus<<8); menuSmooth>>=3; + RenderMenu("SNES Options", menuCount,menuSmooth,menufocus); + MenuFlip(); + + } + + return action; +} + +static int screenshotSaved; +static void MainMenuUpdateText(void) +{ + sprintf(menutext[MAIN_MENU_ROM_SELECT],"Select Rom"); + sprintf(menutext[MAIN_MENU_MANAGE_SAVE_STATE],"Manage Save States"); + sprintf(menutext[MAIN_MENU_SAVE_SRAM],"Save SRAM"); + if (!screenshotSaved) sprintf(menutext[MAIN_MENU_SAVE_SCREENSHOT],"Save Screenshot"); + else sprintf(menutext[MAIN_MENU_SAVE_SCREENSHOT],"[Screenshot already saved]"); + sprintf(menutext[MAIN_MENU_SNES_OPTIONS],"SNES Options"); + sprintf(menutext[MAIN_MENU_RESET_GAME],"Reset Game"); + sprintf(menutext[MAIN_MENU_EXIT_APP],"Exit Application"); + sprintf(menutext[MAIN_MENU_RETURN],"Return To Game"); +} + + +int MainMenu(int prevaction) +{ + int menuExit=0,menuCount=MAIN_MENU_COUNT,menufocus=0,menuSmooth=0; + int action=prevaction; + int subaction=0; + screenshotSaved = 0; + + gp_setCpuspeed(MENU_CPU_SPEED); + + gp_initGraphics(16,currFB,1); + gp_clearFramebuffer16((unsigned short*)framebuffer16[currFB],0x0); + MenuFlip(); +#if !defined(__WIZ__) + gp_video_RGB_setscaling(320,240); +#endif + + memset(&headerDone,0,sizeof(headerDone)); + MainMenuUpdateText(); + + while (!menuExit) + { + InputUpdate(0); + + // Change which rom is focused on: + if (Inp.repeat[INP_BUTTON_UP]) menufocus--; // Up + if (Inp.repeat[INP_BUTTON_DOWN]) menufocus++; // Down + + if (Inp.held[INP_BUTTON_MENU_CANCEL]==1 ) + { + if(currentRomFilename[0]!=0) + { + menuExit=1; + } + } + + if (menufocus>menuCount-1) + { + menufocus=0; + menuSmooth=(menufocus<<8)-1; + } + else if (menufocus<0) + { + menufocus=menuCount-1; + menuSmooth=(menufocus<<8)-1; + } + + if (Inp.held[INP_BUTTON_MENU_SELECT]==1) + { + switch(menufocus) + { + case MAIN_MENU_ROM_SELECT: + memset(&headerDone,0,sizeof(headerDone)); + subaction=LoadRomMenu(); + memset(&headerDone,0,sizeof(headerDone)); + if(subaction) + { + action=subaction; + menuExit=1; + } + MainMenuUpdateText(); + break; + + case MAIN_MENU_MANAGE_SAVE_STATE: + if(currentRomFilename[0]!=0) + { + memset(&headerDone,0,sizeof(headerDone)); + subaction=SaveStateMenu(); + if (subaction==100) + { + menuExit=1; + } + memset(&headerDone,0,sizeof(headerDone)); + } + MainMenuUpdateText(); + break; + case MAIN_MENU_SAVE_SRAM: + if(currentRomFilename[0]!=0) + { + S9xSaveSRAM(); + } + break; + case MAIN_MENU_SNES_OPTIONS: + + memset(&headerDone,0,sizeof(headerDone)); + subaction=SNESOptionsMenu(); + memset(&headerDone,0,sizeof(headerDone)); + MainMenuUpdateText(); + break; + case MAIN_MENU_SAVE_SCREENSHOT: + if (!screenshotSaved) { + ShowMessage("Saving screenshot...", 1); + if (saveScreenShot() == 0) { + screenshotSaved = 1; + MainMenuUpdateText(); + } + } + break; + case MAIN_MENU_RESET_GAME : + if(currentRomFilename[0]!=0) + { + switch(currentEmuMode) + { + case EMU_MODE_SNES: + action=EVENT_RESET_SNES_ROM; + menuExit=1; + break; + } + } + break; + case MAIN_MENU_RETURN: + if(currentRomFilename[0]!=0) + { + menuExit=1; + } + break; + case MAIN_MENU_EXIT_APP: + action=EVENT_EXIT_APP; + menuExit=1; + break; + } + } + // Draw screen: + menuSmooth=menuSmooth*7+(menufocus<<8); menuSmooth>>=3; + RenderMenu("Main Menu", menuCount,menuSmooth,menufocus); + MenuFlip(); + + + } + + WaitForButtonsUp(); + + return action; +} + + + diff --git a/src/menu.h b/src/menu.h new file mode 100644 index 0000000..c0d102d --- /dev/null +++ b/src/menu.h @@ -0,0 +1,380 @@ +#ifndef _MENU_H_ +#define _MENU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include +#include + +#ifdef __GIZ__ +#define DIR_SEP "\\" +#define DIR_SEP_BAD "/" +#define SYSTEM_DIR "\\SD Card\\DrPocketSnes" +#else + #ifdef __GP2X__ + #include "gp2x_sdk.h" + #endif + #ifdef __WIZ__ + #ifdef __CAANOO__ + #include "caanoo_sdk.h" + #else + #include "wiz_sdk.h" + #endif + #endif + + #define DIR_SEP "/" + #define DIR_SEP_BAD "\\" + #define SYSTEM_DIR "/mnt/sd/DrPocketSnes" +#endif + +#define SNES_OPTIONS_DIR "options" +#define SNES_SRAM_DIR "sram" +#define SNES_SAVESTATE_DIR "savestate" + +#define ROM_LIST_FILENAME "romlist.bin" +#define SRAM_FILE_EXT "srm" +#define SAVESTATE_EXT "sv" +#define MENU_OPTIONS_FILENAME "menu" +#define MENU_OPTIONS_EXT "opt" +#define DEFAULT_ROM_DIR_FILENAME "romdir" +#define DEFAULT_ROM_DIR_EXT "opt" + + +//define emulation modes +#define EMU_MODE_NONE 0 +#define EMU_MODE_SNES 1 + +#define SAVESTATE_MODE_SAVE 0 +#define SAVESTATE_MODE_LOAD 1 +#define SAVESTATE_MODE_DELETE 2 + +#define SNES_OPTIONS_VER 1 +#define PSVER "7.2.0" +#ifdef ASMCPU + #define DRSNES_VERSION "v " PSVER " fast" +#else + #define DRSNES_VERSION "v " PSVER " compatible" +#endif + +#define ROM_SIZE 0x500000 //ssf2(40mbits) +#define MENU_RGB(r,g,b) ((r) << 11 | (g) << 6 | (b) << 0 ) +#define COLOR_TITLE MENU_RGB(31, 0, 0) +#define COLOR_FOCUS MENU_RGB(0, 0, 0) +#define COLOR_ITEM MENU_RGB(31, 31, 31) +#define COLOR_VERSION MENU_RGB(0, 0, 31) +#define MAX_ROMS 3000 +#define MAX_CPU 39 +#ifndef MAX_PATH +#define MAX_PATH 255 +#endif + +#if defined(__WIZ__) + #ifdef __CAANOO__ + #define MENU_CPU_SPEED 300 + #else + #define MENU_CPU_SPEED 120 + #endif + #define MENU_FAST_CPU_SPEED 300 +#else + #define MENU_CPU_SPEED 66 + #define MENU_FAST_CPU_SPEED 200 +#endif +enum FILE_TYPE_ENUM +{ + FILE_TYPE_FILE = 0, + FILE_TYPE_DIRECTORY +}; + +enum MAIN_MENU_ENUM +{ + MAIN_MENU_RETURN = 0, + MAIN_MENU_ROM_SELECT, + MAIN_MENU_MANAGE_SAVE_STATE, + MAIN_MENU_SAVE_SRAM, + MAIN_MENU_SAVE_SCREENSHOT, + MAIN_MENU_SNES_OPTIONS, + MAIN_MENU_RESET_GAME, + MAIN_MENU_EXIT_APP, + MAIN_MENU_COUNT +}; + +enum LOAD_ROM_ENUM +{ + LOAD_ROM_MENU_SNES = 0, + LOAD_ROM_MENU_RETURN, + LOAD_ROM_MENU_COUNT +}; + +enum SNES_MENU_ENUM +{ + SNES_MENU_SOUND = 0, + SNES_MENU_SOUND_RATE, + SNES_MENU_SOUND_VOL, + SNES_MENU_FRAMESKIP, + SNES_MENU_REGION, + SNES_MENU_FPS, + SNES_MENU_TRANSPARENCY, +#if defined(__GP2X__) + SNES_MENU_CPUSPEED, + SNES_MENU_RENDER_MODE, + SNES_MENU_GAMMA, + SNES_MENU_ACTION_BUTTONS, +#endif +#if defined(__WIZ__) + SNES_MENU_CPUSPEED, + SNES_MENU_RENDER_MODE, + SNES_MENU_ACTION_BUTTONS, +#endif + SNES_MENU_EMULATION_TYPE, + SNES_MENU_LOAD_ROM_ON_INIT, + SNES_MENU_ADVANCED_HACKS, + SNES_MENU_AUTO_SAVE_SRAM, + SNES_MENU_LOAD_GLOBAL, + SNES_MENU_SAVE_GLOBAL, + SNES_MENU_DELETE_GLOBAL, + SNES_MENU_LOAD_CURRENT, + SNES_MENU_SAVE_CURRENT, + SNES_MENU_DELETE_CURRENT, + SNES_MENU_SET_ROMDIR, + SNES_MENU_CLEAR_ROMDIR, + SNES_MENU_RETURN, + SNES_MENU_COUNT +}; + +enum SAVESTATE_MENU_ENUM +{ + SAVESTATE_MENU_LOAD = 0, + SAVESTATE_MENU_SAVE, + SAVESTATE_MENU_DELETE, + SAVESTATE_MENU_RETURN, + SAVESTATE_MENU_COUNT +}; + +enum HACKS_MENU_ENUM +{ + HACKS_MENU_AUDIO = 0, + HACKS_MENU_SNESADVANCE_DAT, +#ifdef __OLD_RASTER_FX__ + HACKS_MENU_DELAYED_RASTER_FX, +#endif + HACKS_MENU_PALETTE, + HACKS_MENU_FIXEDCOL, + HACKS_MENU_WINDOW, + HACKS_MENU_ADDSUB, + HACKS_MENU_OBJ, + HACKS_MENU_BG0, + HACKS_MENU_BG1, + HACKS_MENU_BG2, + HACKS_MENU_BG3, + HACKS_MENU_RETURN, + HACKS_MENU_COUNT +}; + +enum SRAM_MENU_ENUM +{ + SRAM_MENU_LOAD = 0, + SRAM_MENU_SAVE, + SRAM_MENU_DELETE, + SRAM_MENU_RETURN, + SRAM_MENU_COUNT, +}; + +enum EVENT_TYPES +{ + EVENT_NONE = 0, + EVENT_EXIT_APP, + EVENT_LOAD_SNES_ROM, + EVENT_RUN_SNES_ROM, + EVENT_RESET_SNES_ROM +}; + +enum RENDER_MODE_ENUM +{ + RENDER_MODE_UNSCALED = 0, + RENDER_MODE_SCALED, + RENDER_MODE_HORIZONTAL_SCALED +}; + +#define MENU_TILE_WIDTH 64 +#define MENU_TILE_HEIGHT 64 + +#define GP32_GCC + +#ifdef __GIZ__ +#define INP_BUTTON_MENU_SELECT INP_BUTTON_PLAY +#define INP_BUTTON_MENU_CANCEL INP_BUTTON_STOP +#define INP_BUTTON_MENU_ENTER INP_BUTTON_BRIGHT +#define INP_BUTTON_MENU_DELETE INP_BUTTON_REWIND +#define INP_BUTTON_MENU_QUICKSAVE1 INP_BUTTON_R +#define INP_BUTTON_MENU_QUICKSAVE2 INP_BUTTON_BRIGHT +#define INP_BUTTON_MENU_QUICKLOAD1 INP_BUTTON_L +#define INP_BUTTON_MENU_QUICKLOAD2 INP_BUTTON_BRIGHT + +//Menu Text +#define MENU_TEXT_LOAD_SAVESTATE "Press Play to load" +#define MENU_TEXT_OVERWRITE_SAVESTATE "Press Play to overwrite" +#define MENU_TEXT_DELETE_SAVESTATE "Press Play to delete" +#define MENU_TEXT_PREVIEW_SAVESTATE "Press R to preview" +#endif + +#if defined(__GP2X__) || defined(__WIZ__) +#define INP_BUTTON_MENU_SELECT INP_BUTTON_B +#define INP_BUTTON_MENU_CANCEL INP_BUTTON_X +#define INP_BUTTON_MENU_ENTER INP_BUTTON_SELECT +#define INP_BUTTON_MENU_DELETE INP_BUTTON_SELECT +#define INP_BUTTON_MENU_QUICKSAVE1 INP_BUTTON_R +#define INP_BUTTON_MENU_QUICKSAVE2 INP_BUTTON_SELECT +#define INP_BUTTON_MENU_QUICKLOAD1 INP_BUTTON_L +#define INP_BUTTON_MENU_QUICKLOAD2 INP_BUTTON_SELECT + + +//Menu Text +#define MENU_TEXT_LOAD_SAVESTATE "Press B to load" +#define MENU_TEXT_OVERWRITE_SAVESTATE "Press B to overwrite" +#define MENU_TEXT_DELETE_SAVESTATE "Press B to delete" +#define MENU_TEXT_PREVIEW_SAVESTATE "Press Y to preview" +#endif + +typedef struct { + char name[MAX_ROMS][MAX_PATH]; // 128 entrys,16 Bytes long + int size[MAX_ROMS]; +} DIRDATA; + +//Graphics - moved to objects because they get updated with current gamma setting +extern unsigned short menuHeader[]; +extern unsigned short menuHeaderOrig[]; +extern unsigned short highLightBar[]; +extern unsigned short highLightBarOrig[]; +extern unsigned short menuTile[]; +extern unsigned short menuTileOrig[]; + +extern unsigned char padConfig[]; +extern float soundRates[]; +extern char currentWorkingDir[]; +extern char snesOptionsDir[]; +extern char snesSramDir[]; +extern char snesSaveStateDir[]; +extern unsigned char gammaConv[]; +extern char lastSaveName[]; +extern short *soundBuffer; +extern unsigned char *RomData; +extern int currentEmuMode; +extern int lastStage; +extern int currFB; +extern int prevFB; +extern int saveStateSize; +extern int romLoaded; +extern int frames,taken; // Frames and 60hz ticks +extern char showFps; +extern char soundRate; +extern char soundOn; + +void UpdateMenuGraphicsGamma(void); +int RoundDouble(double val); +void ClearScreen(unsigned int *buffer,unsigned int data); +void LoadSram(char *path,char *romname,char *ext,char *srammem); +void SaveSram(char *path,char *romname,char *ext,char *srammem); +void DeleteSram(char *path,char *romname,char *ext); +int SaveMenuOptions(char *path, char *filename, char *ext, char *optionsmem, int maxsize, int showMessage); +int LoadMenuOptions(char *path, char *filename, char *ext, char *optionsmem, int maxsize, int showMessage); +int DeleteMenuOptions(char *path, char *filename, char *ext, int showMessage); +void SnesDefaultMenuOptions(void); +#ifdef __GIZ__ +void sync(void); +#endif +// menu.cpp +void MenuPause(void); +void MenuFlip(void); +void SplitFilename(char *wholeFilename, char *filename, char *ext); +void CheckDirSep(char *path); +int FileSelect(int mode); +int MainMenu(int prevAction); +void PrintTitle(int flip); +void PrintTile(int flip); +void PrintBar(int flip, unsigned int givenY); + +int FileScan(); +extern void loadStateFile(char *filename); +extern int quickSavePresent; +extern unsigned short cpuSpeedLookup[]; +extern float gammaLookup[]; + +extern char currentRomFilename[]; +extern char romDir[]; +extern char snesRomDir[]; + +struct SNES_MENU_OPTIONS +{ + unsigned char menuVer; + unsigned char frameSkip; + unsigned char soundOn; + unsigned char cpuSpeed; + unsigned char padConfig[32]; + unsigned char tripleBuffer; + unsigned char forceRegion; + unsigned char showFps; + signed char gamma; + unsigned char lcdver; + unsigned char stereo; + unsigned char soundRate; + unsigned char autoSram; + unsigned char renderMode; + unsigned char volume; + unsigned char actionButtons; + unsigned char transparency; + unsigned char ramSettings; + unsigned char mmuHack; + unsigned char region; + unsigned char soundHack; + unsigned short graphHacks; + unsigned char asmspc700; + unsigned char SpeedHacks; + unsigned char loadOnInit; + unsigned char delayedRasterFX; + unsigned char spare1A; + unsigned char spare1B; + unsigned char spare1C; + unsigned char spare1D; + unsigned char spare1E; +}; + +extern struct SNES_MENU_OPTIONS snesMenuOptions; + +struct SAVE_STATE +{ + char filename[MAX_PATH+1]; + char fullFilename[MAX_PATH+1]; + unsigned int inUse; +}; + + +extern struct SAVE_STATE saveState[]; // holds the filenames for the savestate and "inuse" flags +extern char saveStateName[]; + +// Input.cpp +struct INPUT +{ + unsigned int held[32]; + unsigned int repeat[32]; +}; +extern struct INPUT Inp; + +int InputInit(); +int InputUpdate(int EnableDiagnals); + +#ifdef __cplusplus +} +#endif + +#endif /* _MENU_H_ */ + + + + + diff --git a/src/menu_header.bmp b/src/menu_header.bmp new file mode 100644 index 0000000..6066978 Binary files /dev/null and b/src/menu_header.bmp differ diff --git a/src/menu_header.psp b/src/menu_header.psp new file mode 100644 index 0000000..48fccc6 Binary files /dev/null and b/src/menu_header.psp differ diff --git a/src/messages.h b/src/messages.h new file mode 100644 index 0000000..96ef8d1 --- /dev/null +++ b/src/messages.h @@ -0,0 +1,82 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _messages_h_ +#define _messages_h_ + +/* Types of message sent to S9xMessage routine */ +enum { + S9X_TRACE, + S9X_DEBUG, + S9X_WARNING, + S9X_INFO, + S9X_ERROR, + S9X_FATAL_ERROR +}; + +/* Individual message numbers */ +enum { + S9X_ROM_INFO, + S9X_HEADERS_INFO, + S9X_ROM_CONFUSING_FORMAT_INFO, + S9X_ROM_INTERLEAVED_INFO, + S9X_SOUND_DEVICE_OPEN_FAILED, + S9X_APU_STOPPED, + S9X_USAGE, + S9X_GAME_GENIE_CODE_ERROR, + S9X_ACTION_REPLY_CODE_ERROR, + S9X_GOLD_FINGER_CODE_ERROR, + S9X_DEBUG_OUTPUT, + S9X_DMA_TRACE, + S9X_HDMA_TRACE, + S9X_WRONG_FORMAT, + S9X_WRONG_VERSION, + S9X_ROM_NOT_FOUND, + S9X_FREEZE_FILE_NOT_FOUND, + S9X_PPU_TRACE, + S9X_TRACE_DSP1, + S9X_FREEZE_ROM_NAME, + S9X_HEADER_WARNING, + S9X_NETPLAY_NOT_SERVER, + S9X_FREEZE_FILE_INFO, + S9X_TURBO_MODE +}; + +#endif diff --git a/src/minGlue.h b/src/minGlue.h new file mode 100644 index 0000000..5a4c66a --- /dev/null +++ b/src/minGlue.h @@ -0,0 +1,32 @@ +/* Glue functions for the minIni library, based on the C/C++ stdio library + * + * Or better said: this file contains macros that maps the function interface + * used by minIni to the standard C/C++ file I/O functions. + * + * Copyright (c) CompuPhase, 2008-2011 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not + * use this file except in compliance with the License. You may obtain a copy + * of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * Version: $Id: minGlue.h 31 2011-01-28 10:46:16Z thiadmer.riemersma $ + */ + +/* map required file I/O to the standard C library */ +#include +#define ini_openread(filename,file) ((*(file) = fopen((filename),"rt")) != NULL) +#define ini_openwrite(filename,file) ((*(file) = fopen((filename),"wt")) != NULL) +#define ini_close(file) fclose(*(file)) +#define ini_read(buffer,size,file) fgets((buffer),(size),*(file)) +#define ini_write(buffer,file) fputs((buffer),*(file)) +#define ini_rename(source,dest) rename((source),(dest)) +#define ini_remove(filename) remove(filename) +#define ini_rewind(file) rewind(*(file)) diff --git a/src/minIni.c b/src/minIni.c new file mode 100644 index 0000000..6f94518 --- /dev/null +++ b/src/minIni.c @@ -0,0 +1,733 @@ +/* minIni - Multi-Platform INI file parser, suitable for embedded systems + * + * These routines are in part based on the article "Multiplatform .INI Files" + * by Joseph J. Graf in the March 1994 issue of Dr. Dobb's Journal. + * + * Copyright (c) CompuPhase, 2008-2011 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not + * use this file except in compliance with the License. You may obtain a copy + * of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * Version: $Id: minIni.c 31 2011-01-28 10:46:16Z thiadmer.riemersma $ + */ + +#if (defined _UNICODE || defined __UNICODE__ || defined UNICODE) && !defined MININI_ANSI +# if !defined UNICODE /* for Windows */ +# define UNICODE +# endif +# if !defined _UNICODE /* for C library */ +# define _UNICODE +# endif +#endif + +#define MININI_IMPLEMENTATION +#include "minIni.h" +#if defined NDEBUG + #define assert(e) +#else + #include +#endif + +#if !defined __T + #include + #include + #include + /* definition of TCHAR already in minIni.h */ + #define __T(s) s + #define _tcscat strcat + #define _tcschr strchr + #define _tcscmp strcmp + #define _tcscpy strcpy + #define _tcsicmp stricmp + #define _tcslen strlen + #define _tcsncpy strncpy + #define _tcsnicmp strnicmp + #define _tcsrchr strrchr + #define _tcstol strtol + #define _tcstod strtod + #define _totupper toupper + #define _stprintf sprintf + #define _tfgets fgets + #define _tfputs fputs + #define _tfopen fopen + #define _tremove remove + #define _trename rename +#endif + +#if defined __linux || defined __linux__ + #define __LINUX__ +#endif +#if defined FREEBSD && !defined __FreeBSD__ + #define __FreeBSD__ +#endif +#if !defined strnicmp + #if defined __LINUX__ || defined __FreeBSD__ || defined __OpenBSD__ || defined __APPLE__ + #define strnicmp strncasecmp + #endif +#endif + +#if !defined INI_LINETERM + #define INI_LINETERM __T("\n") +#endif +#if !defined INI_FILETYPE + #define INI_FILETYPE FILE* +#endif + +#if !defined sizearray + #define sizearray(a) (sizeof(a) / sizeof((a)[0])) +#endif + +enum quote_option { + QUOTE_NONE, + QUOTE_ENQUOTE, + QUOTE_DEQUOTE, +}; + +static TCHAR *skipleading(const TCHAR *str) +{ + assert(str != NULL); + while (*str != '\0' && *str <= ' ') + str++; + return (TCHAR *)str; +} + +static TCHAR *skiptrailing(const TCHAR *str, const TCHAR *base) +{ + assert(str != NULL); + assert(base != NULL); + while (str > base && *(str-1) <= ' ') + str--; + return (TCHAR *)str; +} + +static TCHAR *striptrailing(TCHAR *str) +{ + TCHAR *ptr = skiptrailing(_tcschr(str, '\0'), str); + assert(ptr != NULL); + *ptr='\0'; + return str; +} + +static TCHAR *save_strncpy(TCHAR *dest, const TCHAR *source, size_t maxlen, enum quote_option option) +{ + size_t d, s; + + assert(maxlen>0); + if (option == QUOTE_ENQUOTE && maxlen < 3) + option = QUOTE_NONE; /* cannot store two quotes and a terminating zero in less than 3 characters */ + + switch (option) { + case QUOTE_NONE: + _tcsncpy(dest,source,maxlen); + dest[maxlen-1]='\0'; + break; + case QUOTE_ENQUOTE: + d = 0; + dest[d++] = '"'; + for (s = 0; source[s] != '\0' && d < maxlen - 2; s++, d++) { + if (source[s] == '"') { + if (d >= maxlen - 3) + break; /* no space to store the escape character plus the one that follows it */ + dest[d++] = '\\'; + } /* if */ + dest[d] = source[s]; + } /* for */ + dest[d++] = '"'; + dest[d] = '\0'; + break; + case QUOTE_DEQUOTE: + for (d = s = 0; source[s] != '\0' && d < maxlen - 1; s++, d++) { + if ((source[s] == '"' || source[s] == '\\') && source[s + 1] == '"') + s++; + dest[d] = source[s]; + } /* for */ + dest[d] = '\0'; + break; + default: + assert(0); + } /* switch */ + + return dest; +} + +static int getkeystring(INI_FILETYPE *fp, const TCHAR *Section, const TCHAR *Key, + int idxSection, int idxKey, TCHAR *Buffer, int BufferSize) +{ + TCHAR *sp, *ep; + int len, idx, isstring; + enum quote_option quotes; + TCHAR LocalBuffer[INI_BUFFERSIZE]; + + assert(fp != NULL); + /* Move through file 1 line at a time until a section is matched or EOF. If + * parameter Section is NULL, only look at keys above the first section. If + * idxSection is postive, copy the relevant section name. + */ + len = (Section != NULL) ? _tcslen(Section) : 0; + if (len > 0 || idxSection >= 0) { + idx = -1; + do { + if (!ini_read(LocalBuffer, INI_BUFFERSIZE, fp)) + return 0; + sp = skipleading(LocalBuffer); + ep = _tcschr(sp, ']'); + } while (*sp != '[' || ep == NULL || (((int)(ep-sp-1) != len || _tcsnicmp(sp+1,Section,len) != 0) && ++idx != idxSection)); + if (idxSection >= 0) { + if (idx == idxSection) { + assert(ep != NULL); + assert(*ep == ']'); + *ep = '\0'; + save_strncpy(Buffer, sp + 1, BufferSize, QUOTE_NONE); + return 1; + } /* if */ + return 0; /* no more section found */ + } /* if */ + } /* if */ + + /* Now that the section has been found, find the entry. + * Stop searching upon leaving the section's area. + */ + assert(Key != NULL || idxKey >= 0); + len = (Key != NULL) ? (int)_tcslen(Key) : 0; + idx = -1; + do { + if (!ini_read(LocalBuffer,INI_BUFFERSIZE,fp) || *(sp = skipleading(LocalBuffer)) == '[') + return 0; + sp = skipleading(LocalBuffer); + ep = _tcschr(sp, '='); /* Parse out the equal sign */ + if (ep == NULL) + ep = _tcschr(sp, ':'); + } while (*sp == ';' || *sp == '#' || ep == NULL || (((int)(skiptrailing(ep,sp)-sp) != len || _tcsnicmp(sp,Key,len) != 0) && ++idx != idxKey)); + if (idxKey >= 0) { + if (idx == idxKey) { + assert(ep != NULL); + assert(*ep == '=' || *ep == ':'); + *ep = '\0'; + striptrailing(sp); + save_strncpy(Buffer, sp, BufferSize, QUOTE_NONE); + return 1; + } /* if */ + return 0; /* no more key found (in this section) */ + } /* if */ + + /* Copy up to BufferSize chars to buffer */ + assert(ep != NULL); + assert(*ep == '=' || *ep == ':'); + sp = skipleading(ep + 1); + /* Remove a trailing comment */ + isstring = 0; + for (ep = sp; *ep != '\0' && ((*ep != ';' && *ep != '#') || isstring); ep++) { + if (*ep == '"') { + if (*(ep + 1) == '"') + ep++; /* skip "" (both quotes) */ + else + isstring = !isstring; /* single quote, toggle isstring */ + } else if (*ep == '\\' && *(ep + 1) == '"') { + ep++; /* skip \" (both quotes */ + } /* if */ + } /* for */ + assert(ep != NULL && (*ep == '\0' || *ep == ';' || *ep == '#')); + *ep = '\0'; /* terminate at a comment */ + striptrailing(sp); + /* Remove double quotes surrounding a value */ + quotes = QUOTE_NONE; + if (*sp == '"' && (ep = _tcschr(sp, '\0')) != NULL && *(ep - 1) == '"') { + sp++; + *--ep = '\0'; + quotes = QUOTE_DEQUOTE; /* this is a string, so remove escaped characters */ + } /* if */ + save_strncpy(Buffer, sp, BufferSize, quotes); + return 1; +} + +/** ini_gets() + * \param Section the name of the section to search for + * \param Key the name of the entry to find the value of + * \param DefValue default string in the event of a failed read + * \param Buffer a pointer to the buffer to copy into + * \param BufferSize the maximum number of characters to copy + * \param Filename the name and full path of the .ini file to read from + * + * \return the number of characters copied into the supplied buffer + */ +int ini_gets(const TCHAR *Section, const TCHAR *Key, const TCHAR *DefValue, + TCHAR *Buffer, int BufferSize, const TCHAR *Filename) +{ + INI_FILETYPE fp; + int ok = 0; + + if (Buffer == NULL || BufferSize <= 0 || Key == NULL) + return 0; + if (ini_openread(Filename, &fp)) { + ok = getkeystring(&fp, Section, Key, -1, -1, Buffer, BufferSize); + ini_close(&fp); + } /* if */ + if (!ok) + save_strncpy(Buffer, DefValue, BufferSize, QUOTE_NONE); + return _tcslen(Buffer); +} + +/** ini_getl() + * \param Section the name of the section to search for + * \param Key the name of the entry to find the value of + * \param DefValue the default value in the event of a failed read + * \param Filename the name of the .ini file to read from + * + * \return the value located at Key + */ +long ini_getl(const TCHAR *Section, const TCHAR *Key, long DefValue, const TCHAR *Filename) +{ + TCHAR buff[64]; + int len = ini_gets(Section, Key, __T(""), buff, sizearray(buff), Filename); + return (len == 0) ? DefValue : _tcstol(buff,NULL,10); +} + +#if !defined INI_NOFLOAT +/** ini_getf() + * \param Section the name of the section to search for + * \param Key the name of the entry to find the value of + * \param DefValue the default value in the event of a failed read + * \param Filename the name of the .ini file to read from + * + * \return the value located at Key + */ +float ini_getf(const TCHAR *Section, const TCHAR *Key, float DefValue, const TCHAR *Filename) +{ + TCHAR buff[64]; + int len = ini_gets(Section, Key, __T(""), buff, sizearray(buff), Filename); + return (len == 0) ? DefValue : (float)_tcstod(buff,NULL); +} +#endif + +/** ini_getbool() + * \param Section the name of the section to search for + * \param Key the name of the entry to find the value of + * \param DefValue default value in the event of a failed read; it should + * zero (0) or one (1). + * \param Buffer a pointer to the buffer to copy into + * \param BufferSize the maximum number of characters to copy + * \param Filename the name and full path of the .ini file to read from + * + A true boolean is found if one of the following is matched: + + - A string starting with 'y' + - A string starting with 'Y' + - A string starting with 't' + - A string starting with 'T' + - A string starting with '1' + + A false boolean is found if one of the following is matched: + + - A string starting with 'n' + - A string starting with 'N' + - A string starting with 'f' + - A string starting with 'F' + - A string starting with '0' + * + * \return the true/false flag as interpreted at Key + */ +int ini_getbool(const TCHAR *Section, const TCHAR *Key, int DefValue, const TCHAR *Filename) +{ + TCHAR buff[2]; + int ret; + + ini_gets(Section, Key, __T(""), buff, sizearray(buff), Filename); + buff[0] = toupper(buff[0]); + if (buff[0]=='Y' || buff[0]=='1' || buff[0]=='T') + ret = 1; + else if (buff[0]=='N' || buff[0]=='0' || buff[0]=='F') + ret = 0; + else + ret = DefValue; + + return(ret); +} + +/** ini_getsection() + * \param idx the zero-based sequence number of the section to return + * \param Buffer a pointer to the buffer to copy into + * \param BufferSize the maximum number of characters to copy + * \param Filename the name and full path of the .ini file to read from + * + * \return the number of characters copied into the supplied buffer + */ +int ini_getsection(int idx, TCHAR *Buffer, int BufferSize, const TCHAR *Filename) +{ + INI_FILETYPE fp; + int ok = 0; + + if (Buffer == NULL || BufferSize <= 0 || idx < 0) + return 0; + if (ini_openread(Filename, &fp)) { + ok = getkeystring(&fp, NULL, NULL, idx, -1, Buffer, BufferSize); + ini_close(&fp); + } /* if */ + if (!ok) + *Buffer = '\0'; + return _tcslen(Buffer); +} + +/** ini_getkey() + * \param Section the name of the section to browse through, or NULL to + * browse through the keys outside any section + * \param idx the zero-based sequence number of the key to return + * \param Buffer a pointer to the buffer to copy into + * \param BufferSize the maximum number of characters to copy + * \param Filename the name and full path of the .ini file to read from + * + * \return the number of characters copied into the supplied buffer + */ +int ini_getkey(const TCHAR *Section, int idx, TCHAR *Buffer, int BufferSize, const TCHAR *Filename) +{ + INI_FILETYPE fp; + int ok = 0; + + if (Buffer == NULL || BufferSize <= 0 || idx < 0) + return 0; + if (ini_openread(Filename, &fp)) { + ok = getkeystring(&fp, Section, NULL, -1, idx, Buffer, BufferSize); + ini_close(&fp); + } /* if */ + if (!ok) + *Buffer = '\0'; + return _tcslen(Buffer); +} + + +#if ! defined INI_READONLY +static void ini_tempname(TCHAR *dest, const TCHAR *source, int maxlength) +{ + TCHAR *p; + + save_strncpy(dest, source, maxlength, QUOTE_NONE); + p = _tcsrchr(dest, '\0'); + assert(p != NULL); + *(p - 1) = '~'; +} + +static enum quote_option check_enquote(const TCHAR *Value) +{ + const TCHAR *p; + + /* run through the value, if it has trailing spaces, or '"', ';' or '#' + * characters, enquote it + */ + assert(Value != NULL); + for (p = Value; *p != '\0' && *p != '"' && *p != ';' && *p != '#'; p++) + /* nothing */; + return (*p != '\0' || (p > Value && *(p - 1) == ' ')) ? QUOTE_ENQUOTE : QUOTE_NONE; +} + +static void writesection(TCHAR *LocalBuffer, const TCHAR *Section, INI_FILETYPE *fp) +{ + TCHAR *p; + + if (Section != NULL && _tcslen(Section) > 0) { + LocalBuffer[0] = '['; + save_strncpy(LocalBuffer + 1, Section, INI_BUFFERSIZE - 4, QUOTE_NONE); /* -1 for '[', -1 for ']', -2 for '\r\n' */ + p = _tcsrchr(LocalBuffer, '\0'); + assert(p != NULL); + *p++ = ']'; + _tcscpy(p, INI_LINETERM); /* copy line terminator (typically "\n") */ + ini_write(LocalBuffer, fp); + } /* if */ +} + +static void writekey(TCHAR *LocalBuffer, const TCHAR *Key, const TCHAR *Value, INI_FILETYPE *fp) +{ + TCHAR *p; + enum quote_option option = check_enquote(Value); + save_strncpy(LocalBuffer, Key, INI_BUFFERSIZE - 3, QUOTE_NONE); /* -1 for '=', -2 for '\r\n' */ + p = _tcsrchr(LocalBuffer, '\0'); + assert(p != NULL); + *p++ = '='; + save_strncpy(p, Value, INI_BUFFERSIZE - (p - LocalBuffer) - 2, option); /* -2 for '\r\n' */ + p = _tcsrchr(LocalBuffer, '\0'); + assert(p != NULL); + _tcscpy(p, INI_LINETERM); /* copy line terminator (typically "\n") */ + ini_write(LocalBuffer, fp); +} + +static void write_quoted(const TCHAR *Value, INI_FILETYPE *fp) +{ + TCHAR s[3]; + int idx; + if (check_enquote(Value) == QUOTE_NONE) { + ini_write(Value, fp); + } else { + ini_write("\"", fp); + for (idx = 0; Value[idx] != '\0'; idx++) { + if (Value[idx] == '"') { + s[0] = '\\'; + s[1] = Value[idx]; + s[2] = '\0'; + } else { + s[0] = Value[idx]; + s[1] = '\0'; + } /* if */ + ini_write(s, fp); + } /* for */ + ini_write("\"", fp); + } /* if */ +} + +/** ini_puts() + * \param Section the name of the section to write the string in + * \param Key the name of the entry to write, or NULL to erase all keys in the section + * \param Value a pointer to the buffer the string, or NULL to erase the key + * \param Filename the name and full path of the .ini file to write to + * + * \return 1 if successful, otherwise 0 + */ +int ini_puts(const TCHAR *Section, const TCHAR *Key, const TCHAR *Value, const TCHAR *Filename) +{ + INI_FILETYPE rfp; + INI_FILETYPE wfp; + TCHAR *sp, *ep; + TCHAR LocalBuffer[INI_BUFFERSIZE]; + int len, match, count; + + assert(Filename!=NULL); + if (!ini_openread(Filename, &rfp)) { + /* If the .ini file doesn't exist, make a new file */ + if (Key!=NULL && Value!=NULL) { + if (!ini_openwrite(Filename, &wfp)) + return 0; + writesection(LocalBuffer, Section, &wfp); + writekey(LocalBuffer, Key, Value, &wfp); + ini_close(&wfp); + } /* if */ + return 1; + } /* if */ + + /* If parameters Key and Value are valid (so this is not an "erase" request) + * and the setting already exists and it already has the correct value, do + * nothing. This early bail-out avoids rewriting the INI file for no reason. + */ + if (Key!=NULL && Value!=NULL) { + match = getkeystring(&rfp, Section, Key, -1, -1, LocalBuffer, sizearray(LocalBuffer)); + if (match && _tcscmp(LocalBuffer,Value)==0) { + ini_close(&rfp); + return 1; + } /* if */ + /* key not found, or different value -> proceed (but rewind the input file first) */ + ini_rewind(&rfp); + } /* if */ + + /* Get a temporary file name to copy to. Use the existing name, but with + * the last character set to a '~'. + */ + ini_tempname(LocalBuffer, Filename, INI_BUFFERSIZE); + if (!ini_openwrite(LocalBuffer, &wfp)) { + ini_close(&rfp); + return 0; + } /* if */ + + /* Move through the file one line at a time until a section is + * matched or until EOF. Copy to temp file as it is read. + */ + count = 0; + len = (Section != NULL) ? _tcslen(Section) : 0; + if (len > 0) { + do { + if (!ini_read(LocalBuffer, INI_BUFFERSIZE, &rfp)) { + /* Failed to find section, so add one to the end */ + if (Key!=NULL && Value!=NULL) { + ini_write(INI_LINETERM, &wfp); /* force a new line (there may not have been one) behind the last line of the INI file */ + writesection(LocalBuffer, Section, &wfp); + writekey(LocalBuffer, Key, Value, &wfp); + } /* if */ + /* Clean up and rename */ + ini_close(&rfp); + ini_close(&wfp); + ini_remove(Filename); + ini_tempname(LocalBuffer, Filename, INI_BUFFERSIZE); + ini_rename(LocalBuffer, Filename); + return 1; + } /* if */ + /* Copy the line from source to dest, but not if this is the section that + * we are looking for and this section must be removed + */ + sp = skipleading(LocalBuffer); + ep = _tcschr(sp, ']'); + match = (*sp == '[' && ep != NULL && (int)(ep-sp-1) == len && _tcsnicmp(sp + 1,Section,len) == 0); + if (!match || Key!=NULL) { + /* Remove blank lines, but insert a blank line (possibly one that was + * removed on the previous iteration) before a new section. This creates + * "neat" INI files. + */ + if (_tcslen(sp) > 0) { + if (*sp == '[' && count > 0) + ini_write(INI_LINETERM, &wfp); + ini_write(sp, &wfp); + count++; + } /* if */ + } /* if */ + } while (!match); + } /* if */ + + /* Now that the section has been found, find the entry. Stop searching + * upon leaving the section's area. Copy the file as it is read + * and create an entry if one is not found. + */ + len = (Key!=NULL) ? _tcslen(Key) : 0; + for( ;; ) { + if (!ini_read(LocalBuffer, INI_BUFFERSIZE, &rfp)) { + /* EOF without an entry so make one */ + if (Key!=NULL && Value!=NULL) { + ini_write(INI_LINETERM, &wfp); /* force a new line (there may not have been one) behind the last line of the INI file */ + writekey(LocalBuffer, Key, Value, &wfp); + } /* if */ + /* Clean up and rename */ + ini_close(&rfp); + ini_close(&wfp); + ini_remove(Filename); + ini_tempname(LocalBuffer, Filename, INI_BUFFERSIZE); + ini_rename(LocalBuffer, Filename); + return 1; + } /* if */ + sp = skipleading(LocalBuffer); + ep = _tcschr(sp, '='); /* Parse out the equal sign */ + if (ep == NULL) + ep = _tcschr(sp, ':'); + match = (ep != NULL && (int)(skiptrailing(ep,sp)-sp) == len && _tcsnicmp(sp,Key,len) == 0); + if ((Key!=NULL && match) || *sp == '[') + break; /* found the key, or found a new section */ + /* in the section that we re-write, do not copy empty lines */ + if (Key!=NULL && _tcslen(sp) > 0) + ini_write(sp, &wfp); + } /* for */ + if (*sp == '[') { + /* found start of new section, the key was not in the specified + * section, so we add it just before the new section + */ + if (Key!=NULL && Value!=NULL) { + /* We cannot use "writekey()" here, because we need to preserve the + * contents of LocalBuffer. + */ + ini_write(Key, &wfp); + ini_write("=", &wfp); + write_quoted(Value, &wfp); + ini_write(INI_LINETERM INI_LINETERM, &wfp); /* put a blank line between the current and the next section */ + } /* if */ + /* write the new section header that we read previously */ + ini_write(sp, &wfp); + } else { + /* We found the key; ignore the line just read (with the key and + * the current value) and write the key with the new value. + */ + if (Key!=NULL && Value!=NULL) + writekey(LocalBuffer, Key, Value, &wfp); + } /* if */ + /* Copy the rest of the INI file (removing empty lines, except before a section) */ + while (ini_read(LocalBuffer, INI_BUFFERSIZE, &rfp)) { + sp = skipleading(LocalBuffer); + if (_tcslen(sp) > 0) { + if (*sp == '[') + ini_write(INI_LINETERM, &wfp); + ini_write(sp, &wfp); + } /* if */ + } /* while */ + /* Clean up and rename */ + ini_close(&rfp); + ini_close(&wfp); + ini_remove(Filename); + ini_tempname(LocalBuffer, Filename, INI_BUFFERSIZE); + ini_rename(LocalBuffer, Filename); + return 1; +} + +/* Ansi C "itoa" based on Kernighan & Ritchie's "Ansi C" book. */ +#define ABS(v) ((v) < 0 ? -(v) : (v)) + +static void strreverse(TCHAR *str) +{ + TCHAR t; + int i, j; + + for (i = 0, j = _tcslen(str) - 1; i < j; i++, j--) { + t = str[i]; + str[i] = str[j]; + str[j] = t; + } /* for */ +} + +static void long2str(long value, TCHAR *str) +{ + int i = 0; + long sign = value; + int n; + + /* generate digits in reverse order */ + do { + n = (int)(value % 10); /* get next lowest digit */ + str[i++] = (TCHAR)(ABS(n) + '0'); /* handle case of negative digit */ + } while (value /= 10); /* delete the lowest digit */ + if (sign < 0) + str[i++] = '-'; + str[i] = '\0'; + + strreverse(str); +} + +/** ini_putl() + * \param Section the name of the section to write the value in + * \param Key the name of the entry to write + * \param Value the value to write + * \param Filename the name and full path of the .ini file to write to + * + * \return 1 if successful, otherwise 0 + */ +int ini_putl(const TCHAR *Section, const TCHAR *Key, long Value, const TCHAR *Filename) +{ + TCHAR buff[32]; + long2str(Value, buff); + return ini_puts(Section, Key, buff, Filename); +} + +#if !defined INI_NOFLOAT +/** ini_putf() + * \param Section the name of the section to write the value in + * \param Key the name of the entry to write + * \param Value the value to write + * \param Filename the name and full path of the .ini file to write to + * + * \return 1 if successful, otherwise 0 + */ +int ini_putf(const TCHAR *Section, const TCHAR *Key, float Value, const TCHAR *Filename) +{ + TCHAR buff[64]; + _stprintf(buff, __T("%f"), Value); + return ini_puts(Section, Key, buff, Filename); +} +#endif /* INI_FLOAT */ +#endif /* !INI_READONLY */ + + +#if defined PORTABLE_STRNICMP +int strnicmp(const TCHAR *s1, const TCHAR *s2, size_t n) +{ + register unsigned TCHAR c1, c2; + + while (n-- != 0 && (*s1 || *s2)) { + c1 = *(const unsigned TCHAR *)s1++; + if ('a' <= c1 && c1 <= 'z') + c1 += ('A' - 'a'); + c2 = *(const unsigned TCHAR *)s2++; + if ('a' <= c2 && c2 <= 'z') + c2 += ('A' - 'a'); + if (c1 != c2) + return c1 - c2; + } /* while */ + return 0; +} +#endif /* PORTABLE_STRNICMP */ diff --git a/src/minIni.h b/src/minIni.h new file mode 100644 index 0000000..f1e419d --- /dev/null +++ b/src/minIni.h @@ -0,0 +1,145 @@ +/* minIni - Multi-Platform INI file parser, suitable for embedded systems + * + * Copyright (c) CompuPhase, 2008-2011 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may not + * use this file except in compliance with the License. You may obtain a copy + * of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * Version: $Id: minIni.h 31 2011-01-28 10:46:16Z thiadmer.riemersma $ + */ +#ifndef MININI_H +#define MININI_H + +#include "minGlue.h" + +#if (defined _UNICODE || defined __UNICODE__ || defined UNICODE) && !defined INI_ANSIONLY + #include +#elif !defined __T + typedef char TCHAR; +#endif + +#if !defined INI_BUFFERSIZE + #define INI_BUFFERSIZE 512 +#endif + +#if defined __cplusplus + extern "C" { +#endif + +int ini_getbool(const TCHAR *Section, const TCHAR *Key, int DefValue, const TCHAR *Filename); +long ini_getl(const TCHAR *Section, const TCHAR *Key, long DefValue, const TCHAR *Filename); +int ini_gets(const TCHAR *Section, const TCHAR *Key, const TCHAR *DefValue, TCHAR *Buffer, int BufferSize, const TCHAR *Filename); +int ini_getsection(int idx, TCHAR *Buffer, int BufferSize, const TCHAR *Filename); +int ini_getkey(const TCHAR *Section, int idx, TCHAR *Buffer, int BufferSize, const TCHAR *Filename); + +#if !defined INI_NOFLOAT +float ini_getf(const TCHAR *Section, const TCHAR *Key, float DefValue, const TCHAR *Filename); +#endif + +#if !defined INI_READONLY +int ini_putl(const TCHAR *Section, const TCHAR *Key, long Value, const TCHAR *Filename); +int ini_puts(const TCHAR *Section, const TCHAR *Key, const TCHAR *Value, const TCHAR *Filename); +#if !defined INI_NOFLOAT +int ini_putf(const TCHAR *Section, const TCHAR *Key, float Value, const TCHAR *Filename); +#endif /* INI_NOFLOAT */ +#endif /* INI_READONLY */ + +#if defined __cplusplus + } +#endif + + +#if defined __cplusplus + +#if defined __WXWINDOWS__ + #include "wxMinIni.h" +#else + #include + + /* The C++ class in minIni.h was contributed by Steven Van Ingelgem. */ + class minIni + { + public: + minIni(const std::string& filename) : iniFilename(filename) + { } + + bool getbool(const std::string& Section, const std::string& Key, bool DefValue=false) const + { return static_cast(ini_getbool(Section.c_str(), Key.c_str(), int(DefValue), iniFilename.c_str())); } + + long getl(const std::string& Section, const std::string& Key, long DefValue=0) const + { return ini_getl(Section.c_str(), Key.c_str(), DefValue, iniFilename.c_str()); } + + int geti(const std::string& Section, const std::string& Key, int DefValue=0) const + { return static_cast(this->getl(Section, Key, long(DefValue))); } + + std::string gets(const std::string& Section, const std::string& Key, const std::string& DefValue="") const + { + char buffer[INI_BUFFERSIZE]; + ini_gets(Section.c_str(), Key.c_str(), DefValue.c_str(), buffer, INI_BUFFERSIZE, iniFilename.c_str()); + return buffer; + } + + std::string getsection(int idx) const + { + char buffer[INI_BUFFERSIZE]; + ini_getsection(idx, buffer, INI_BUFFERSIZE, iniFilename.c_str()); + return buffer; + } + + std::string getkey(const std::string& Section, int idx) const + { + char buffer[INI_BUFFERSIZE]; + ini_getkey(Section.c_str(), idx, buffer, INI_BUFFERSIZE, iniFilename.c_str()); + return buffer; + } + +#if !defined INI_NOFLOAT + float getf(const std::string& Section, const std::string& Key, float DefValue=0) const + { return ini_getf(Section.c_str(), Key.c_str(), DefValue, iniFilename.c_str()); } +#endif + +#if ! defined INI_READONLY + bool put(const std::string& Section, const std::string& Key, long Value) const + { return (bool)ini_putl(Section.c_str(), Key.c_str(), Value, iniFilename.c_str()); } + + bool put(const std::string& Section, const std::string& Key, int Value) const + { return (bool)ini_putl(Section.c_str(), Key.c_str(), (long)Value, iniFilename.c_str()); } + + bool put(const std::string& Section, const std::string& Key, bool Value) const + { return (bool)ini_putl(Section.c_str(), Key.c_str(), (long)Value, iniFilename.c_str()); } + + bool put(const std::string& Section, const std::string& Key, const std::string& Value) const + { return (bool)ini_puts(Section.c_str(), Key.c_str(), Value.c_str(), iniFilename.c_str()); } + + bool put(const std::string& Section, const std::string& Key, const char* Value) const + { return (bool)ini_puts(Section.c_str(), Key.c_str(), Value, iniFilename.c_str()); } + +#if !defined INI_NOFLOAT + bool put(const std::string& Section, const std::string& Key, float Value) const + { return (bool)ini_putf(Section.c_str(), Key.c_str(), Value, iniFilename.c_str()); } +#endif + + bool del(const std::string& Section, const std::string& Key) const + { return (bool)ini_puts(Section.c_str(), Key.c_str(), 0, iniFilename.c_str()); } + + bool del(const std::string& Section) const + { return (bool)ini_puts(Section.c_str(), 0, 0, iniFilename.c_str()); } +#endif + + private: + std::string iniFilename; + }; + +#endif /* __WXWINDOWS__ */ +#endif /* __cplusplus */ + +#endif /* MININI_H */ diff --git a/src/misc.s b/src/misc.s new file mode 100644 index 0000000..596daf5 --- /dev/null +++ b/src/misc.s @@ -0,0 +1,179 @@ +@ vim:filetype=armasm + +@ Generic memory routines. +@ (c) Copyright 2007, Grazvydas "notaz" Ignotas + + +.global memcpy16 @ unsigned short *dest, unsigned short *src, int count + +memcpy16: + eor r3, r0, r1 + tst r3, #2 + bne mcp16_cant_align + + tst r0, #2 + ldrneh r3, [r1], #2 + subne r2, r2, #1 + strneh r3, [r0], #2 + + subs r2, r2, #4 + bmi mcp16_fin + +mcp16_loop: + ldmia r1!, {r3,r12} + subs r2, r2, #4 + stmia r0!, {r3,r12} + bpl mcp16_loop + +mcp16_fin: + tst r2, #2 + ldrne r3, [r1], #4 + strne r3, [r0], #4 + ands r2, r2, #1 + bxeq lr + +mcp16_cant_align: + ldrh r3, [r1], #2 + subs r2, r2, #1 + strh r3, [r0], #2 + bne mcp16_cant_align + + bx lr + + + +@ 0x12345678 -> 0x34127856 +@ r4=temp, lr=0x00ff00ff +.macro bswap reg + and r4, \reg, lr + and \reg, lr, \reg, lsr #8 + orr \reg, \reg, r4, lsl #8 +.endm + + +@ dest must be halfword aligned, src can be unaligned +.global memcpy16bswap @ unsigned short *dest, void *src, int count + +memcpy16bswap: + tst r1, #1 + bne mcp16bs_cant_align2 + + eor r3, r0, r1 + tst r3, #2 + bne mcp16bs_cant_align + + tst r0, #2 + beq mcp16bs_aligned + ldrh r3, [r1], #2 + sub r2, r2, #1 + orr r3, r3, r3, lsl #16 + mov r3, r3, lsr #8 + strh r3, [r0], #2 + +mcp16bs_aligned: + stmfd sp!, {r4,lr} + mov lr, #0xff + orr lr, lr, lr, lsl #16 + + subs r2, r2, #4 + bmi mcp16bs_fin4 + +mcp16bs_loop: + ldmia r1!, {r3,r12} + subs r2, r2, #4 + bswap r3 + bswap r12 + stmia r0!, {r3,r12} + bpl mcp16bs_loop + +mcp16bs_fin4: + tst r2, #2 + beq mcp16bs_fin2 + ldr r3, [r1], #4 + bswap r3 + str r3, [r0], #4 + +mcp16bs_fin2: + ldmfd sp!, {r4,lr} + ands r2, r2, #1 + bxeq lr + +mcp16bs_cant_align: + ldrh r3, [r1], #2 + subs r2, r2, #1 + orr r3, r3, r3, lsl #16 + mov r3, r3, lsr #8 + strh r3, [r0], #2 + bne mcp16bs_cant_align + bx lr + + @ worst case +mcp16bs_cant_align2: + ldrb r3, [r1], #1 + ldrb r12,[r1], #1 + subs r2, r2, #1 + mov r3, r3, lsl #8 + orr r3, r3, r12 + strh r3, [r0], #2 + bne mcp16bs_cant_align2 + bx lr + + + +.global memcpy32 @ int *dest, int *src, int count + +memcpy32: + stmfd sp!, {r4,lr} + + subs r2, r2, #4 + bmi mcp32_fin + +mcp32_loop: + ldmia r1!, {r3,r4,r12,lr} + subs r2, r2, #4 + stmia r0!, {r3,r4,r12,lr} + bpl mcp32_loop + +mcp32_fin: + tst r2, #3 + ldmeqfd sp!, {r4,pc} + tst r2, #1 + ldrne r3, [r1], #4 + strne r3, [r0], #4 + +mcp32_no_unal1: + tst r2, #2 + ldmneia r1!, {r3,r12} + ldmfd sp!, {r4,lr} + stmneia r0!, {r3,r12} + bx lr + + + +.global memset32 @ int *dest, int c, int count + +memset32: + stmfd sp!, {lr} + + mov r3, r1 + subs r2, r2, #4 + bmi mst32_fin + + mov r12,r1 + mov lr, r1 + +mst32_loop: + subs r2, r2, #4 + stmia r0!, {r1,r3,r12,lr} + bpl mst32_loop + +mst32_fin: + tst r2, #1 + strne r1, [r0], #4 + + tst r2, #2 + stmneia r0!, {r1,r3} + + ldmfd sp!, {pc} + + diff --git a/src/missing.h b/src/missing.h new file mode 100644 index 0000000..804f8b5 --- /dev/null +++ b/src/missing.h @@ -0,0 +1,114 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _MISSING_H_ +#define _MISSING_H_ + +struct HDMA +{ + uint8 used; + uint8 bbus_address; + uint8 abus_bank; + uint16 abus_address; + uint8 indirect_address; + uint8 force_table_address_write; + uint8 force_table_address_read; + uint8 line_count_write; + uint8 line_count_read; +}; + +struct Missing +{ + uint8 emulate6502; + uint8 decimal_mode; + uint8 mv_8bit_index; + uint8 mv_8bit_acc; + uint8 interlace; + uint8 lines_239; + uint8 pseudo_512; + struct HDMA hdma [8]; + uint8 modes [8]; + uint8 mode7_fx; + uint8 mode7_flip; + uint8 mode7_bgmode; + uint8 direct; + uint8 matrix_multiply; + uint8 oam_read; + uint8 vram_read; + uint8 cgram_read; + uint8 wram_read; + uint8 dma_read; + uint8 vram_inc; + uint8 vram_full_graphic_inc; + uint8 virq; + uint8 hirq; + uint16 virq_pos; + uint16 hirq_pos; + uint8 h_v_latch; + uint8 h_counter_read; + uint8 v_counter_read; + uint8 fast_rom; + uint8 window1 [6]; + uint8 window2 [6]; + uint8 sprite_priority_rotation; + uint8 subscreen; + uint8 subscreen_add; + uint8 subscreen_sub; + uint8 fixed_colour_add; + uint8 fixed_colour_sub; + uint8 mosaic; + uint8 sprite_double_height; + uint8 dma_channels; + uint8 dma_this_frame; + uint8 oam_address_read; + uint8 bg_offset_read; + uint8 matrix_read; + uint8 hdma_channels; + uint8 hdma_this_frame; + uint16 unknownppu_read; + uint16 unknownppu_write; + uint16 unknowncpu_read; + uint16 unknowncpu_write; + uint16 unknowndsp_read; + uint16 unknowndsp_write; +}; + +EXTERN_C struct Missing missing; +#endif diff --git a/src/mmuhack.c b/src/mmuhack.c new file mode 100644 index 0000000..00bc8e1 --- /dev/null +++ b/src/mmuhack.c @@ -0,0 +1,344 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern int errno; + +int memfd; + +void *trymmap (void *start, size_t length, int prot, int flags, int fd, off_t offset) +{ + char *p; + int aa; + + //printf ("mmap(%X, %X, %X, %X, %X, %X) ... ", (unsigned int)start, length, prot, flags, fd, (unsigned int)offset); + p = mmap (start, length, prot, flags, fd, offset); + if (p == (char *)0xFFFFFFFF) + { + aa = errno; + printf ("failed mmap(%X, %X, %X, %X, %X, %X) errno = %d\n", (unsigned int)start, length, prot, flags, fd, (unsigned int)offset, aa); + } + else + { + //printf ("OK! (%X)\n", (unsigned int)p); + } + + return p; +} + +unsigned char initphys (void) +{ + memfd = open("/dev/mem", O_RDWR); + if (memfd == -1) + { + printf ("Open failed\n"); + return 0; + } + + printf ("/dev/mem opened successfully - fd = %d\n", memfd); + + return 1; +} + +void closephys (void) +{ + close (memfd); +} + +int myuname(char *buffer) +{ + asm volatile ("swi #0x90007a"); +} + +void DecodeCoarse (unsigned int indx, unsigned int sa) +{ + unsigned int cpt[256]; + unsigned int dom = (sa >> 5) & 15; + unsigned int temp; + unsigned int i = 0; + unsigned int wb = 0; + + sa &= 0xfffffc00; + indx *= 1048576; + + //printf (" > %08X\n", sa); + //printf ("%d\n", + lseek (memfd, sa, SEEK_SET); + memset (cpt, 0, 256*4); + temp = read (memfd, cpt, 256*4); + //printf ("%d\n", temp); + if (temp != 256*4) + { + printf (" # Bad read\n"); + return; + } + + //printf ("%08X %08X %08X %08X\n", cpt[0], cpt[4], cpt[8], cpt[12]); + + for (i = 0; i < 256; i ++) + { + if (cpt[i]) + { + switch (cpt[i] & 3) + { + case 0: + //printf (" -- [%08X] Invalid --\n", cpt[i]); + break; + case 1: + printf (" VA: %08X PA: %08X - %08X A: %d %d %d %d D: %d C: %d B: %d\n", indx, + cpt[i] & 0xFFFF0000, (cpt[i] & 0xFFFF0000) | 0xFFFF, + (cpt[i] >> 10) & 3, (cpt[i] >> 8) & 3, (cpt[i] >> 6) & 3, + (cpt[i] >> 4) & 3, dom, (cpt[i] >> 3) & 1, (cpt[i] >> 2) & 1); + break; + case 2: + printf (" VA: %08X PA: %08X - %08X A: %d %d %d %d D: %d C: %d B: %d\n", indx, + cpt[i] & 0xfffff000, (cpt[i] & 0xfffff000) | 0xFFF, + (cpt[i] >> 10) & 3, (cpt[i] >> 8) & 3, (cpt[i] >> 6) & 3, + (cpt[i] >> 4) & 3, dom, (cpt[i] >> 3) & 1, (cpt[i] >> 2) & 1); + // This is where we look for any virtual addresses that map to physical address 0x03000000 and + // alter the cachable and bufferable bits... + /*if (((cpt[i] & 0xffff0000) == 0x03000000) && ((cpt[i] & 12)==0)) + { + //printf("c and b bits not set, overwriting\n"); + cpt[i] |= 0xFFC; + wb = 1; + }*/ + if (((cpt[i] & 0xff000000) == 0x02000000) ) + { + //printf("SOUND c and b bits not set, overwriting\n"); + if((cpt[i] & 12)==0) { + cpt[i] |= 0xFFC; + wb++; + } + } + //if ((a>=0x31 && a<=0x36) && ((cpt[i] & 12)==0)) + if (((cpt[i] & 0xff000000) == 0x03000000) ) + { + //printf("SDL c and b bits not set, overwriting\n"); + if((cpt[i] & 12)==0) { + cpt[i] |= 0xFFC; + wb++; + } + } + break; + case 3: + //printf (" -- [%08X/%d] Unsupported --\n", cpt[i],cpt[i] & 3); + break; + default: + //printf (" -- [%08X/%d] Unknown --\n", cpt[i], cpt[i] & 3); + break; + } + } + indx += 4096; + } + //printf ("%08X %08X %08X %08X\n", cpt[0], cpt[4], cpt[8], cpt[12]); + if (wb) + { + //printf("Hacking cpt\n"); + lseek (memfd, sa, SEEK_SET); + temp = write (memfd, cpt, 256*4); + printf("%d bytes written, %s\n", temp, temp == 1024 ? "yay!" : "oh fooble :(!"); + } +} + +void dumppgtable (unsigned int ttb) +{ + unsigned int pgtable[4096]; + char *desctypes[] = {"Invalid", "Coarse", "Section", "Fine"}; + + memset (pgtable, 0, 4096*4); + lseek (memfd, ttb, SEEK_SET); + read (memfd, pgtable, 4096*4); + + int i; + for (i = 0; i < 4096; i ++) + { + int temp; + + if (pgtable[i]) + { + printf ("Indx: %d VA: %08X Type: %d [%s] \n", i, i * 1048576, pgtable[i] & 3, desctypes[pgtable[i]&3]); + switch (pgtable[i]&3) + { + case 0: + //printf (" -- Invalid --\n"); + break; + case 1: + DecodeCoarse(i, pgtable[i]); + break; + case 2: + temp = pgtable[i] & 0xFFF00000; + //printf (" PA: %08X - %08X A: %d D: %d C: %d B: %d\n", temp, temp | 0xFFFFF, + // (pgtable[i] >> 10) & 3, (pgtable[i] >> 5) & 15, (pgtable[i] >> 3) & 1, + // (pgtable[i] >> 2) & 1); + + break; + case 3: + printf (" -- Unsupported! --\n"); + break; + } + } + } +} + +void benchmark (void *memptr) +{ + int starttime = time (NULL); + int a,b,c,d; + volatile unsigned int *pp = (unsigned int *) memptr; + + while (starttime == time (NULL)); + + printf ("\n\nmemory benchmark of volatile VA: %08X\n\nread test\n", memptr); + for (d = 0; d < 3; d ++) + { + starttime = time (NULL); + b = 0; + c = 0; + while (starttime == time (NULL)) + { + for (a = 0; a < 20000; a ++) + { + b += pp[a]; + } + c ++; + } + printf ("Count is %d. %dMB/sec\n", c, (c * 20000)/1024/1024); + } + + printf ("write test\n"); + for (d = 0; d < 3; d ++) + { + starttime = time (NULL); + b = 0; + c = 0; + while (starttime == time (NULL)) + { + for (a = 0; a < 20000; a ++) + { + pp[a] = 0x37014206; + } + c ++; + } + printf ("Count is %d. %dMB/sec\n", c, (c * 20000)/1024/1024); + } + + printf ("combined test (read, write back)\n"); + for (d = 0; d < 3; d ++) + { + starttime = time (NULL); + b = 0; + c = 0; + while (starttime == time (NULL)) + { + for (a = 0; a < 20000; a ++) + { + pp[a] += 0x55017601; + } + c ++; + } + printf ("Count is %d. %dMB/sec\n", c, (c * 20000)/1024/1024); + } + + printf ("test complete\n"); +} + +void hackpgtable (void) +{ + unsigned int oldc1, oldc2, oldc3, oldc4; + unsigned int newc1 = 0xee120f10, newc2 = 0xe12fff1e; + unsigned int ttb, ttx; + char name[256]; + + // We need to execute a "MRC p15, 0, r0, c2, c0, 0", to get the pointer to the translation table base, but we can't + // do this in user mode, so we have to patch the kernel to get it to run it for us in supervisor mode. We do this + // at the moment by overwriting the sys_newuname function and then calling it. + + lseek (memfd, 0x6ec00, SEEK_SET); // fixme: We should ask the kernel for this address rather than assuming it... + read (memfd, &oldc1, 4); + read (memfd, &oldc2, 4); + read (memfd, &oldc3, 4); + read (memfd, &oldc4, 4); + + printf ("0:%08X %08X\n", oldc1, oldc2); + + lseek (memfd, 0x6ec00, SEEK_SET); + write (memfd, &newc1, 4); + write (memfd, &newc2, 4); + + ttb = myuname(name); + + lseek (memfd, 0x6ec00, SEEK_SET); + write (memfd, &oldc1, 4); + write (memfd, &oldc2, 4); + + printf ("1:%08X\n", ttb); + + //printf ("Restored contents\n"); + + // We now have the translation table base ! Walk the table looking for our allocation and hack it :) + dumppgtable(ttb); + + // Now drain the write buffer and flush the tlb caches. Something else we can't do in user mode... + unsigned int tlbc1 = 0xe3a00000; // mov r0, #0 + unsigned int tlbc2 = 0xee070f9a; // mcr 15, 0, r0, cr7, cr10, 4 + unsigned int tlbc3 = 0xee080f17; // mcr 15, 0, r0, cr8, cr7, 0 + unsigned int tlbc4 = 0xe1a0f00e; // mov pc, lr + + lseek (memfd, 0x6ec00, SEEK_SET); + write (memfd, &tlbc1, 4); + write (memfd, &tlbc2, 4); + write (memfd, &tlbc3, 4); + write (memfd, &tlbc4, 4); + + ttx = myuname(name); + + //printf ("Return from uname: %08X\n", ttx); + + lseek (memfd, 0x6ec00, SEEK_SET); + write (memfd, &oldc1, 4); + write (memfd, &oldc2, 4); + write (memfd, &oldc3, 4); + write (memfd, &oldc4, 4); + + //printf ("Restored contents\n"); + + //printf ("Pagetable after modification!\n"); + //printf ("-------------------------------\n"); + //dumppgtable(ttb); +} + +/*int +main( int argc, char* argv[] ) +{ + if (!initphys()) + return 0; + + volatile unsigned int *myBuf = trymmap((void *)0, 65536, PROT_READ | PROT_WRITE, MAP_SHARED, memfd, 0x03000000); + volatile unsigned int *secbuf = (unsigned int *)malloc (204800); + + //memset ((void *)myBuf, 0x55, 65536); + //memset ((void *)secbuf, 0x55, 65536); + + printf("mmaped 0x03000000 buffer @ VA: %08X malloc'd buffer @ VA: %08X\n", myBuf, secbuf); + + hackpgtable(); + + //benchmark ((void*)myBuf); + //benchmark ((void*)secbuf); + +///////////////////////////////////////////////////////////////////////////////////////////////////////////// + printf ("\n\nCleaning up...\n"); + printf ("Closing files...\n"); + close (memfd); + printf ("Exiting...\n"); + + return 0; +} */ \ No newline at end of file diff --git a/src/mode7.caanoo.log b/src/mode7.caanoo.log new file mode 100644 index 0000000..f9566b9 --- /dev/null +++ b/src/mode7.caanoo.log @@ -0,0 +1,5482 @@ +AA:-6094645, CC:-6151989, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-6061878, CC:-6119222, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-6029111, CC:-6086455, daa: 32767, dcc: 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32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4423541, CC:-4302709, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4390774, CC:-4269942, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4358007, CC:-4237175, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4325240, CC:-4204408, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4292473, CC:-4171641, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4259706, CC:-4138874, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4226939, CC:-4106107, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4194172, CC:-4073340, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4161405, CC:-4040573, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4128638, CC:-4007806, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4095871, CC:-3975039, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4063104, CC:-3942272, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-4030337, CC:-3909505, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-3997570, CC:-3876738, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-3964803, CC:-3843971, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-3932036, CC:-3811204, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-3899269, CC:-3778437, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 +AA:-3866502, CC:-3745670, daa: 32767, dcc: 32767, MA: 32767, MB: 32767, MC: 32767, MD: 32767 diff --git a/src/mode7.cpp b/src/mode7.cpp new file mode 100644 index 0000000..88b4d89 --- /dev/null +++ b/src/mode7.cpp @@ -0,0 +1,489 @@ +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; +extern uint8 Mode7Depths [2]; + +#define M7 19 + +/* +void DrawBGMode7Background16 (uint8 *Screen, int bg, int depth) +{ + RENDER_BACKGROUND_MODE7ADDSUB (depth, GFX.ScreenColors [b & 0xff]); +} +*/ + +#ifdef __DEBUG__ + + #define DMSG(rop) printf("Rendering Mode7 w/prio, ROp: " rop ", R:%d, r2130: %d, bg: %d\n", PPU.Mode7Repeat, GFX.r2130 & 1, bg) +#else + #define DMSG(rop) +#endif + +void DrawBGMode7Background16R0 (uint8 *Screen, int bg, int depth); +void DrawBGMode7Background16R1R2 (uint8 *Screen, int bg, int depth); +void DrawBGMode7Background16R3 (uint8 *Screen, int bg, int depth); + +void DrawBGMode7Background16 (uint8 *Screen, int bg, int depth) +{ + DMSG("opaque"); + CHECK_SOUND(); + + if (GFX.r2130 & 1) { + if (IPPU.DirectColourMapsNeedRebuild) S9xBuildDirectColourMaps (); + GFX.ScreenColors = DirectColourMaps [0]; + } else GFX.ScreenColors = IPPU.ScreenColors; + + switch (PPU.Mode7Repeat) { + case 0: + DrawBGMode7Background16R0(Screen, bg, depth); + return; + case 3: + DrawBGMode7Background16R3(Screen, bg, depth); + return; + default: + DrawBGMode7Background16R1R2(Screen, bg, depth); + return; + } +} + +#define M7C 0x1fff + +void DrawBGMode7Background16R3 (uint8 *Screen, int bg, int depth) +{ + + uint8 *VRAM1 = Memory.VRAM + 1; + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int dir; + int yy; + int xx; + int yy3; + int xx3; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint8 *Depth; + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + yy3 = ((yy + CentreY) & 7) << 4; + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + dir = -1; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + dir = 1; + } + + + xx3 = (startx + HOffset); + + asm volatile ( + "1: \n" + " ldrb r0, [%[d]] \n" + " mov r3, %[AA], asr #18 \n" + " cmp %[depth], r0 \n" + " bls 4f \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " mov r3, %[CC], asr #11 \n" + " mov r1, %[AA], asr #11 \n" + " add r3, r1, r3, lsl #7 \n" + " mov r3, r3, lsl #1 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, %[CC], #(7 << 8) \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " and r0, %[AA], #(7 << 8) \n" + " add r3, r3, r1, asr #4 \n" + " add r3, r3, r0, asr #7 \n" + " \n" + " ldr r1, %[daa] \n" + " ldrb r0, [r3, #1] \n" + " add %[AA], %[AA], r1 \n" + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " add %[xx3], %[xx3], %[dir] \n" + " strneb %[depth], [%[d]] \n" + " ldr r0, %[dcc] \n" + " strneh r1, [%[p]] \n" + " \n" + " add %[CC], %[CC], r0 \n" + " add %[d], %[d], #1 \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + " b 3f \n" + "2: \n" + //" and r1, %[yy3], #7 \n" + " and r0, %[xx3], #7 \n" + //" mov r3, r1, lsl #4 \n" + " add r3, %[yy3], r0, lsl #1 \n" + " \n" + " add r3, %[VRAM], r3 \n" + " ldrb r0, [r3, #1] \n" + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " strneb %[depth], [%[d]] \n" + " strneh r1, [%[p]] \n" + "4: \n" + " ldr r0, %[daa] \n" + " ldr r1, %[dcc] \n" + " add %[xx3], %[xx3], %[dir] \n" + " add %[AA], %[AA], r0 \n" + " add %[CC], %[CC], r1 \n" + " add %[p], %[p], #2 \n" + " add %[d], %[d], #1 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + "3: \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "m" (aa), + [dcc] "m" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d), + [depth] "r" (depth), + [dir] "r" (dir), + [yy3] "r" (yy3), + [xx3] "r" (xx3) + : "r0", "r1", "r3", "cc" + ); + } + } + +} + +void DrawBGMode7Background16R1R2 (uint8 *Screen, int bg, int depth) +{ + + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint32 AndByY; + uint32 AndByX = 0xffffffff; + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) AndByX = 0x7ff; + AndByY = AndByX << 4; + AndByX = AndByX << 1; + uint8 *Depth; + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + "1: \n" + " ldrb r0, [%[d]] \n" + " mov r3, %[AA], asr #18 \n" + " cmp %[depth], r0 \n" + " bls 2f \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " ldr r1, %[AndByY] \n" + " ldr r0, %[AndByX] \n" + " and r1, r1, %[CC], asr #4 \n" + " and r0, r0, %[AA], asr #7 \n" + " \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " and r1, r1, #0x70 \n" + " \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " add %[AA], %[AA], %[daa] \n" + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " strneb %[depth], [%[d]] \n" + " add %[CC], %[CC], %[dcc] \n" + " strneh r1, [%[p]] \n" + " add %[p], %[p], #2 \n" + " add %[d], %[d], #1 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + " b 3f \n" + "2: \n" + " add %[AA], %[AA], %[daa] \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " add %[d], %[d], #1 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + "3: \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d), + [depth] "r" (depth), + [AndByX] "m" (AndByX), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + } + } +} + + +void DrawBGMode7Background16R0 (uint8 *Screen, int bg, int depth) +{ + uint8 *VRAM1 = Memory.VRAM + 1; + int aa, cc; + int startx; + uint32 Left; + uint32 Right; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint16 *p; + uint8 *d; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + struct SLineMatrixData *l; + uint8 *Depth; + + + Left = 0; + Right = 256; + + + if (!ClipCount) ClipCount = 1; + + + l = &LineMatrixData [GFX.StartY]; + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + /*yy += (VOffset - CentreY) % 1023; + xx = (HOffset - CentreX) % 1023; +*/ + + yy += ((VOffset - CentreY) << (32-10+1)) >> (32-10+1) ; + xx = ((HOffset - CentreX) << (32-10+1)) >> (32-10+1); + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + " b 1f \n" + //"7: \n" // AndByX + //" .word (0x3ff << 1) \n" + "8: \n" // AndByY + " .word (0x3ff << 4) \n" + " \n" + "1: \n" + " ldr r3, 8b \n" + " ldrb r0, [%[d]] \n" + " and r1, r3, %[CC], asr #4 \n" + " cmp %[depth], r0 \n" + " bls 2f \n" + //" ldr r0, 7b \n" + " mov r0, r3, asr #3 \n" + " and r3, r1, #0x7f \n" + " and r0, r0, %[AA], asr #7 \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, r1, #0x70 \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " strneb %[depth], [%[d]] \n" + " strneh r1, [%[p]] \n" + " \n" + "2: \n" + " add %[AA], %[AA], %[daa] \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " add %[d], %[d], #1 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d), + [depth] "r" (depth) + : "r0", "r1", "r3", "cc" + ); + + } + } + +} + diff --git a/src/mode7.h b/src/mode7.h new file mode 100644 index 0000000..faa53a9 --- /dev/null +++ b/src/mode7.h @@ -0,0 +1,17 @@ +void DrawBGMode7Background16New (uint8 *Screen); +void DrawBGMode7Background16 (uint8 *Screen, int bg, int depth); +void DrawBGMode7Background16Add (uint8 *Screen, int bg, int depth); +void DrawBGMode7Background16Add1_2 (uint8 *Screen, int bg, int depth); +void DrawBGMode7Background16Sub (uint8 *Screen, int bg, int depth); +void DrawBGMode7Background16Sub1_2 (uint8 *Screen, int bg, int depth); + +void DrawBGMode7Background16Prio (uint8 *Screen, int bg); +void DrawBGMode7Background16PrioAdd (uint8 *Screen, int bg); +void DrawBGMode7Background16PrioAdd1_2 (uint8 *Screen, int bg); +void DrawBGMode7Background16PrioSub (uint8 *Screen, int bg); +void DrawBGMode7Background16PrioSub1_2 (uint8 *Screen, int bg); + + + + + diff --git a/src/mode7.wiz.log b/src/mode7.wiz.log new file mode 100644 index 0000000..48be543 --- /dev/null +++ b/src/mode7.wiz.log @@ -0,0 +1,5280 @@ +AA:-79872, CC:-58070, daa: 1648, dcc: 0 +AA:-78720, CC:-53452, daa: 1639, dcc: 0 +AA:-77696, CC:-48768, daa: 1631, dcc: 0 +AA:-76544, CC:-44211, daa: 1622, dcc: 0 +AA:-75520, CC:-39684, daa: 1614, dcc: 0 +AA:-74368, CC:-35187, daa: 1605, dcc: 0 +AA:-73344, CC:-30720, daa: 1597, dcc: 0 +AA:-72320, CC:-26374, daa: 1589, dcc: 0 +AA:-71296, CC:-21966, daa: 1581, dcc: 0 +AA:-70272, CC:-17677, daa: 1573, dcc: 0 +AA:-69248, CC:-13416, daa: 1565, dcc: 0 +AA:-68352, CC:-9183, daa: 1558, dcc: 0 +AA:-67328, CC:-4978, daa: 1550, dcc: 0 +AA:-66304, CC:-801, daa: 1542, dcc: 0 +AA:-65408, CC:3348, daa: 1535, dcc: 0 +AA:-64384, CC:7386, daa: 1527, dcc: 0 +AA:-63488, CC:11480, daa: 1520, dcc: 0 +AA:-62464, CC:15465, daa: 1512, dcc: 0 +AA:-61568, CC:19424, daa: 1505, dcc: 0 +AA:-60672, CC:23357, daa: 1498, dcc: 0 +AA:-59776, CC:27264, daa: 1491, dcc: 0 +AA:-58880, CC:31145, daa: 1484, dcc: 0 +AA:-57984, CC:35000, daa: 1477, dcc: 0 +AA:-57088, CC:38754, daa: 1470, dcc: 0 +AA:-56192, CC:42558, daa: 1463, dcc: 0 +AA:-55296, CC:46263, daa: 1456, dcc: 0 +AA:-54528, CC:50016, daa: 1450, dcc: 0 +AA:-53632, CC:53672, daa: 1443, dcc: 0 +AA:-52736, CC:57304, daa: 1436, dcc: 0 +AA:-51968, CC:60912, daa: 1430, dcc: 0 +AA:-51072, CC:64496, daa: 1423, dcc: 0 +AA:-50304, CC:67989, daa: 1417, dcc: 0 +AA:-49536, CC:71526, daa: 1411, dcc: 0 +AA:-48640, CC:75039, daa: 1404, dcc: 0 +AA:-47872, CC:78464, daa: 1398, dcc: 0 +AA:-47104, CC:81867, daa: 1392, dcc: 0 +AA:-46336, CC:85310, daa: 1386, dcc: 0 +AA:-45568, CC:88668, daa: 1380, dcc: 0 +AA:-44800, CC:92004, daa: 1374, dcc: 0 +AA:-44032, CC:95318, daa: 1368, dcc: 0 +AA:-43264, CC:98610, daa: 1362, dcc: 0 +AA:-42496, CC:101880, daa: 1356, dcc: 0 +AA:-41728, CC:105072, daa: 1350, dcc: 0 +AA:-41088, CC:108299, daa: 1345, dcc: 0 +AA:-40320, CC:111450, daa: 1339, dcc: 0 +AA:-39552, CC:114634, daa: 1333, dcc: 0 +AA:-38912, CC:117744, daa: 1328, dcc: 0 +AA:-38144, CC:120834, daa: 1322, dcc: 0 +AA:-37504, CC:123954, daa: 1317, dcc: 0 +AA:-36736, CC:127003, daa: 1311, dcc: 0 +AA:-36096, CC:130032, daa: 1306, dcc: 0 +AA:-35328, CC:133041, daa: 1300, dcc: 0 +AA:-34688, CC:136030, daa: 1295, dcc: 0 +AA:-34048, CC:138954, daa: 1290, dcc: 0 +AA:-33408, CC:141904, daa: 1285, dcc: 0 +AA:-32768, CC:144834, daa: 1280, dcc: 0 +AA:-32000, CC:147702, daa: 1274, dcc: 0 +AA:-31360, CC:150593, daa: 1269, dcc: 0 +AA:-30720, CC:153424, daa: 1264, dcc: 0 +AA:-30080, CC:156276, daa: 1259, dcc: 0 +AA:-29440, CC:159070, daa: 1254, dcc: 0 +AA:-28928, CC:161846, daa: 1250, dcc: 0 +AA:-28288, CC:164604, daa: 1245, dcc: 0 +AA:-27648, CC:167344, daa: 1240, dcc: 0 +AA:-27008, CC:170066, daa: 1235, dcc: 0 +AA:-26368, CC:172770, daa: 1230, dcc: 0 +AA:-25856, CC:175456, daa: 1226, dcc: 0 +AA:-25216, CC:178124, daa: 1221, dcc: 0 +AA:-24576, CC:180774, daa: 1216, dcc: 0 +AA:-24064, CC:183377, daa: 1212, dcc: 0 +AA:-23424, CC:185992, daa: 1207, dcc: 0 +AA:-22912, CC:188562, daa: 1203, dcc: 0 +AA:-22272, CC:191142, daa: 1198, dcc: 0 +AA:-21760, CC:193679, daa: 1194, dcc: 0 +AA:-21120, CC:196224, daa: 1189, dcc: 0 +AA:-20608, CC:198728, daa: 1185, dcc: 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+AA:-15232, CC:222888, daa: 1143, dcc: 0 +AA:-14720, CC:225204, daa: 1139, dcc: 0 +AA:-14208, CC:227517, daa: 1135, dcc: 0 +AA:-13824, CC:229814, daa: 1132, dcc: 0 +AA:-13312, CC:232086, daa: 1128, dcc: 0 +AA:-12800, CC:234344, daa: 1124, dcc: 0 +AA:-12288, CC:236595, daa: 1120, dcc: 0 +AA:-11776, CC:238824, daa: 1116, dcc: 0 +AA:-11264, CC:241044, daa: 1112, dcc: 0 +AA:-10880, CC:243244, daa: 1109, dcc: 0 +AA:-10368, CC:245430, daa: 1105, dcc: 0 +AA:-9856, CC:247602, daa: 1101, dcc: 0 +AA:-9472, CC:249760, daa: 1098, dcc: 0 +AA:-8960, CC:251904, daa: 1094, dcc: 0 +AA:-8448, CC:254034, daa: 1090, dcc: 0 +AA:-8064, CC:256150, daa: 1087, dcc: 0 +AA:-8064, CC:258273, daa: 1087, dcc: 0 +AA:-7168, CC:260340, daa: 1080, dcc: 0 +AA:-6656, CC:262414, daa: 1076, dcc: 0 +AA:-6272, CC:264474, daa: 1073, dcc: 0 +AA:-6272, CC:266569, daa: 1073, dcc: 0 +AA:-6272, CC:268664, daa: 1073, dcc: 0 +AA:-6272, CC:270759, daa: 1073, dcc: 0 +AA:-6272, CC:272854, daa: 1073, dcc: 0 +AA:-6272, CC:274949, daa: 1073, dcc: 0 +AA:-6272, CC:277044, daa: 1073, dcc: 0 +AA:-6272, CC:279139, daa: 1073, dcc: 0 +AA:-6272, CC:281234, daa: 1073, dcc: 0 +AA:-6272, CC:283329, daa: 1073, dcc: 0 +AA:-6272, CC:285424, daa: 1073, dcc: 0 +AA:-6272, CC:287519, daa: 1073, dcc: 0 +AA:-6272, CC:289614, daa: 1073, dcc: 0 +AA:-6272, CC:291709, daa: 1073, dcc: 0 +AA:-6272, CC:293804, daa: 1073, dcc: 0 +AA:-6272, CC:295899, daa: 1073, dcc: 0 diff --git a/src/mode7_t.h b/src/mode7_t.h new file mode 100644 index 0000000..0d066b5 --- /dev/null +++ b/src/mode7_t.h @@ -0,0 +1,526 @@ +#include "port.h" +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; +extern uint8 Mode7Depths [2]; + +#define M7 19 +#define M7C 0x1fff + +#define MACRO_CONCAT(a,b) a##b +#define DEC_FMODE7(n) MACRO_CONCAT(void DrawBGMode7Background16, n)(uint8 *Screen, int bg, int depth) + +static void DrawBGMode7Background16R3 (uint8 *Screen, int bg, int depth) +{ + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + //uint8 *d; + //uint16 *p; + //int dir; + int yy; + int yy3; + int xx3; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + //uint8 b; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + + //int x, AA, CC, xx3; + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + yy3 = ((yy + CentreY) & 7) << 4; + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + uint16 *p = (uint16 *) Screen + Left; + uint8 *d = Depth + Left - 1; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + + int x = (Right - Left); + int AA = (l->MatrixA * (startx + xx) + BB); + int CC = (l->MatrixC * (startx + xx) + DD); + xx3 = (startx + HOffset); + +#define M7R3(dir) \ + asm volatile (\ + "1: \n"\ + " ldrb r0, [%[d], #1]! \n"\ + " mov r3, %[AA], asr #18 \n"\ + " mov r1, %[AA], asr #11 \n"\ + " cmp %[depth], r0 \n"\ + " bls 4f \n"\ + " orrs r3, r3, %[CC], asr #18 \n"\ + " bne 2f \n"\ + " \n"\ + " mov r3, %[CC], asr #11 \n"\ + " add r3, r1, r3, lsl #7 \n"\ + " mov r3, r3, lsl #1 \n"\ + " ldrb r3, [%[VRAM], r3] \n"\ + " \n"\ + " and r0, %[AA], #(7 << 8) \n"\ + " and r1, %[CC], #(7 << 8) \n"\ + " add r3, %[VRAM], r3, lsl #7 \n"\ + " add r3, r3, r1, asr #4 \n"\ + " add r3, r3, r0, asr #7 \n"\ + " \n"\ + " ldrb r0, [r3, #1] \n"\ + " mov r1, #0x13000 \n"\ + " ldrb r3, [%[d], r1] \n"\ + " movs r0, r0, lsl #2 \n"\ + " beq 4f \n"\ + " strb %[depth], [%[d]] \n"\ + " ldr r1, [%[colors], r0] \n"\ + \ + " cmp r3, #1 \n"\ + " blo 11f \n"\ + " ldrneh r3, [%[p], %[delta]] \n"\ + " ldreq r3, %[fixedcolour] \n"\ + \ + ROP\ + "11: \n"\ + " strh r1, [%[p]] \n"\ + \ + " ldr r0, %[dcc] \n"\ + " add %[xx3], %[xx3], #(" #dir ") \n"\ + " add %[AA], %[AA], %[daa] \n"\ + " add %[CC], %[CC], r0 \n"\ + " add %[p], %[p], #2 \n"\ + " subs %[x], %[x], #1 \n"\ + " bne 1b \n"\ + " b 3f \n"\ + "2: \n"\ + " ldr r3, %[yy3] \n"\ + " and r0, %[xx3], #7 \n"\ + " add r3, r3, r0, lsl #1 \n"\ + " \n"\ + " add r3, %[VRAM], r3 \n"\ + " ldrb r0, [r3, #1] \n"\ + " mov r1, #0x13000 \n"\ + " ldrb r3, [%[d], r1] \n"\ + " movs r0, r0, lsl #2 \n"\ + " beq 4f \n"\ + " strb %[depth], [%[d]] \n"\ + \ + " ldr r1, [%[colors], r0] \n"\ + \ + " cmp r3, #1 \n"\ + " blo 12f \n"\ + " ldrneh r3, [%[p], %[delta]] \n"\ + " ldreq r3, %[fixedcolour] \n"\ + \ + ROP\ + "12: \n"\ + " strh r1, [%[p]] \n"\ + "4: \n"\ + " ldr r1, %[dcc] \n"\ + " add %[xx3], %[xx3], #(" #dir ") \n"\ + " add %[AA], %[AA], %[daa] \n"\ + " add %[CC], %[CC], r1 \n"\ + " add %[p], %[p], #2 \n"\ + " subs %[x], %[x], #1 \n"\ + " bne 1b \n"\ + "3: \n"\ + : [p] "+r" (p),\ + [x] "+r" (x),\ + [AA] "+r" (AA),\ + [CC] "+r" (CC),\ + [xx3] "+r" (xx3),\ + [d] "+r" (d)\ + : [daa] "r" (aa),\ + [dcc] "m" (cc),\ + [VRAM] "r" (Memory.VRAM),\ + [colors] "r" (GFX.ScreenColors),\ + [depth] "r" (depth),\ + [yy3] "m" (yy3), \ + [delta] "r" (GFX.Delta << 1),\ + [fixedcolour] "m" (fixedColour)\ + : "r0", "r1", "r3", "cc"\ + ); + + if (!PPU.Mode7HFlip) { + M7R3(1) + } else { + M7R3(-1) + } + } + } + +} + +static void DrawBGMode7Background16R1R2 (uint8 *Screen, int bg, int depth) +{ + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint32 AndByY; + uint32 AndByX = 0xffffffff; + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) AndByX = 0x7ff; + AndByY = AndByX << 4; + AndByX = AndByX << 1; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + + int x, AA, CC; + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left - 1; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + + x = (Right - Left); + AA = (l->MatrixA * (startx + xx) + BB); + CC = (l->MatrixC * (startx + xx) + DD); + + asm volatile ( + "1: \n" + " ldrb r0, [%[d], #1]! \n" + " mov r3, %[AA], asr #18 \n" + " cmp %[depth], r0 \n" + " bls 2f \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " ldr r1, %[AndByY] \n" + " ldr r0, %[AndByX] \n" + " and r1, r1, %[CC], asr #4 \n" + " and r0, r0, %[AA], asr #7 \n" + " \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " and r1, r1, #0x70 \n" + " \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " mov r1, #0x13000 \n" // R1 = ZDELTA + " ldrb r3, [%[d], r1] \n" +// " ldrb r3, [%[d], %[zdelta]] \n" + " movs r0, r0, lsl #2 \n" + " beq 2f \n" + " strb %[depth], [%[d]] \n" + + " ldr r1, [%[colors], r0] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + "2: \n" + //" ldr r0, %[dcc] \n" + " add %[AA], %[AA], %[daa] \n" + //" add %[CC], %[CC], r0 \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + : [p] "+r" (p), + [d] "+r" (d), + [x] "+r" (x), + [AA] "+r" (AA), + [CC] "+r" (CC) + : [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (depth), + //[zdelta] "r" (GFX.DepthDelta), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "m" (fixedColour), + [AndByX] "m" (AndByX), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + } + } +} + + +static void DrawBGMode7Background16R0 (uint8 *Screen, int bg, int depth) +{ + int aa, cc; + int startx; + uint32 Left; + uint32 Right; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint16 *p; + uint8 *d; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + struct SLineMatrixData *l; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + + int x, AA, CC; + unsigned int AndByY = (0x3ff << 4); + + Left = 0; + Right = 256; + + if (!ClipCount) ClipCount = 1; + + + l = &LineMatrixData [GFX.StartY]; + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += (VOffset - CentreY) % 1023; + xx = (HOffset - CentreX) % 1023; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + + p = (uint16 *) Screen + Left; + d = Depth + Left -1; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + x = (Right - Left); + AA = (l->MatrixA * (startx + xx) + BB); + CC = (l->MatrixC * (startx + xx) + DD); + + asm volatile ( + " ldrb r0, [%[d], #1]! \n" + "1: \n" + " ldr r3, %[AndByY] \n" + " cmp %[depth], r0 \n" + " bls 2f \n" + + " and r1, r3, %[CC], asr #4 \n" + " and r0, r3, %[AA], asr #4 \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #7 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, r1, #0x70 \n" + " and r0, r0, #(14 << 3) \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " add r3, r3, r1 \n" + " add r3, r3, r0, asr #3 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " mov r1, #0x13000 \n" // r1 = ZDELTA + " ldrb r3, [%[d], r1] \n" + " movs r0, r0, lsl #2 \n" + " beq 2f \n" + " strb %[depth], [%[d]] \n" + + " ldr r1, [%[colors], r0] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + + "2: \n" + " add %[AA], %[AA], %[daa] \n" + " add %[p], %[p], #2 \n" + " add %[CC], %[CC], %[dcc] \n" + " subs %[x], %[x], #1 \n" + " ldrneb r0, [%[d], #1]! \n" + " bne 1b \n" + : [p] "+r" (p), + [d] "+r" (d), + [x] "+r" (x), + [AA] "+r" (AA), + [CC] "+r" (CC) + : [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + //[zdelta] "r" (GFX.DepthDelta), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "m" (fixedColour), + [depth] "r" (depth), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + + } + } + +} + +DEC_FMODE7(ROPNAME) +{ +#ifdef __DEBUG__ + #define DMESG(n) printf("Rendering Mode7, ROp: " #n ", R:%d, r2130: %d, bg: %d\n", PPU.Mode7Repeat, GFX.r2130 & 1, bg) + DMESG(ROPNAME) +#endif + CHECK_SOUND(); + + if (GFX.r2130 & 1) { + if (IPPU.DirectColourMapsNeedRebuild) S9xBuildDirectColourMaps (); + GFX.ScreenColors = DirectColourMaps [0]; + } else GFX.ScreenColors = IPPU.ScreenColors; + + switch (PPU.Mode7Repeat) { + case 0: + DrawBGMode7Background16R0(Screen, bg, depth); + return; + case 3: + DrawBGMode7Background16R3(Screen, bg, depth); + return; + default: + DrawBGMode7Background16R1R2(Screen, bg, depth); + return; + } +} diff --git a/src/mode7_t.h.gch b/src/mode7_t.h.gch new file mode 100644 index 0000000..f55f12a Binary files /dev/null and b/src/mode7_t.h.gch differ diff --git a/src/mode7_t.h.new b/src/mode7_t.h.new new file mode 100644 index 0000000..f37e332 --- /dev/null +++ b/src/mode7_t.h.new @@ -0,0 +1,526 @@ +#include "port.h" +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; +extern uint8 Mode7Depths [2]; + +#define M7 19 +#define M7C 0x1fff + +#define MACRO_CONCAT(a,b) a##b +#define DEC_FMODE7(n) MACRO_CONCAT(void DrawBGMode7Background16, n)(uint8 *Screen, int bg, int depth) + +static void DrawBGMode7Background16R3 (uint8 *Screen, int bg, int depth) +{ + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + //uint8 *d; + //uint16 *p; + //int dir; + int yy; + int yy3; + int xx3; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + //uint8 b; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + + //int x, AA, CC, xx3; + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + yy3 = ((yy + CentreY) & 7) << 4; + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + uint16 *p = (uint16 *) Screen + Left; + uint8 *d = Depth + Left - 1; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + + int x = (Right - Left); + int AA = (l->MatrixA * (startx + xx) + BB); + int CC = (l->MatrixC * (startx + xx) + DD); + xx3 = (startx + HOffset); + +#define M7R3(dir) \ + asm volatile (\ + "1: \n"\ + " ldrb r0, [%[d], #1]! \n"\ + " mov r3, %[AA], asr #18 \n"\ + " mov r1, %[AA], asr #11 \n"\ + " cmp %[depth], r0 \n"\ + " bls 4f \n"\ + " orrs r3, r3, %[CC], asr #18 \n"\ + " bne 2f \n"\ + " \n"\ + " mov r3, %[CC], asr #11 \n"\ + " add r3, r1, r3, lsl #7 \n"\ + " mov r3, r3, lsl #1 \n"\ + " ldrb r3, [%[VRAM], r3] \n"\ + " \n"\ + " and r0, %[AA], #(7 << 8) \n"\ + " and r1, %[CC], #(7 << 8) \n"\ + " add r3, %[VRAM], r3, lsl #7 \n"\ + " add r3, r3, r1, asr #4 \n"\ + " add r3, r3, r0, asr #7 \n"\ + " \n"\ + " ldrb r0, [r3, #1] \n"\ + " mov r1, #0x13000 \n"\ + " ldrb r3, [%[d], r1] \n"\ + " movs r0, r0, lsl #2 \n"\ + " beq 4f \n"\ + " strb %[depth], [%[d]] \n"\ + " ldr r1, [%[colors], r0] \n"\ + \ + " cmp r3, #1 \n"\ + " blo 11f \n"\ + " ldrneh r3, [%[p], %[delta]] \n"\ + " ldreq r3, %[fixedcolour] \n"\ + \ + ROP\ + "11: \n"\ + " strh r1, [%[p]] \n"\ + \ + " ldr r0, %[dcc] \n"\ + " add %[xx3], %[xx3], #(" #dir ") \n"\ + " add %[AA], %[AA], %[daa] \n"\ + " add %[CC], %[CC], r0 \n"\ + " add %[p], %[p], #2 \n"\ + " subs %[x], %[x], #1 \n"\ + " bne 1b \n"\ + " b 3f \n"\ + "2: \n"\ + " ldr r3, %[yy3] \n"\ + " and r0, %[xx3], #7 \n"\ + " add r3, r3, r0, lsl #1 \n"\ + " \n"\ + " add r3, %[VRAM], r3 \n"\ + " ldrb r0, [r3, #1] \n"\ + " mov r1, #0x13000 \n"\ + " ldrb r3, [%[d], r1] \n"\ + " movs r0, r0, lsl #2 \n"\ + " beq 4f \n"\ + " strb %[depth], [%[d]] \n"\ + \ + " ldr r1, [%[colors], r0] \n"\ + \ + " cmp r3, #1 \n"\ + " blo 12f \n"\ + " ldrneh r3, [%[p], %[delta]] \n"\ + " ldreq r3, %[fixedcolour] \n"\ + \ + ROP\ + "12: \n"\ + " strh r1, [%[p]] \n"\ + "4: \n"\ + " ldr r1, %[dcc] \n"\ + " add %[xx3], %[xx3], #(" #dir ") \n"\ + " add %[AA], %[AA], %[daa] \n"\ + " add %[CC], %[CC], r1 \n"\ + " add %[p], %[p], #2 \n"\ + " subs %[x], %[x], #1 \n"\ + " bne 1b \n"\ + "3: \n"\ + : [p] "+r" (p),\ + [x] "+r" (x),\ + [AA] "+r" (AA),\ + [CC] "+r" (CC),\ + [xx3] "+r" (xx3),\ + [d] "+r" (d)\ + : [daa] "r" (aa),\ + [dcc] "m" (cc),\ + [VRAM] "r" (Memory.VRAM),\ + [colors] "r" (GFX.ScreenColors),\ + [depth] "r" (depth),\ + [yy3] "m" (yy3), \ + [delta] "r" (GFX.Delta << 1),\ + [fixedcolour] "m" (fixedColour)\ + : "r0", "r1", "r3", "cc"\ + ); + + if (!PPU.Mode7HFlip) { + M7R3(1) + } else { + M7R3(-1) + } + } + } + +} + +static void DrawBGMode7Background16R1R2 (uint8 *Screen, int bg, int depth) +{ + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint32 AndByY; + uint32 AndByX = 0xffffffff; + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) AndByX = 0x7ff; + AndByY = AndByX << 4; + AndByX = AndByX << 1; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + + int x, AA, CC; + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left - 1; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + + x = (Right - Left); + AA = (l->MatrixA * (startx + xx) + BB); + CC = (l->MatrixC * (startx + xx) + DD); + + asm volatile ( + "1: \n" + " ldrb r0, [%[d], #1]! \n" + " mov r3, %[AA], asr #18 \n" + " cmp %[depth], r0 \n" + " bls 2f \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " ldr r1, %[AndByY] \n" + " ldr r0, %[AndByX] \n" + " and r1, r1, %[CC], asr #4 \n" + " and r0, r0, %[AA], asr #7 \n" + " \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " and r1, r1, #0x70 \n" + " \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " mov r1, #0x13000 \n" // R1 = ZDELTA + " ldrb r3, [%[d], r1] \n" +// " ldrb r3, [%[d], %[zdelta]] \n" + " movs r0, r0, lsl #2 \n" + " beq 2f \n" + " strb %[depth], [%[d]] \n" + + " ldr r1, [%[colors], r0] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + "2: \n" + //" ldr r0, %[dcc] \n" + " add %[AA], %[AA], %[daa] \n" + //" add %[CC], %[CC], r0 \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + : [p] "+r" (p), + [d] "+r" (d), + [x] "+r" (x), + [AA] "+r" (AA), + [CC] "+r" (CC) + : [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (depth), + //[zdelta] "r" (GFX.DepthDelta << 1), + [delta] "r" (GFX.Delta), + [fixedcolour] "m" (fixedColour), + [AndByX] "m" (AndByX), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + } + } +} + + +static void DrawBGMode7Background16R0 (uint8 *Screen, int bg, int depth) +{ + int aa, cc; + int startx; + uint32 Left; + uint32 Right; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint16 *p; + uint8 *d; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + struct SLineMatrixData *l; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + + int x, AA, CC; + unsigned int AndByY = (0x3ff << 4); + + Left = 0; + Right = 256; + + if (!ClipCount) ClipCount = 1; + + + l = &LineMatrixData [GFX.StartY]; + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += (VOffset - CentreY) % 1023; + xx = (HOffset - CentreX) % 1023; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + + p = (uint16 *) Screen + Left; + d = Depth + Left -1; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + x = (Right - Left); + AA = (l->MatrixA * (startx + xx) + BB); + CC = (l->MatrixC * (startx + xx) + DD); + + asm volatile ( + " ldrb r0, [%[d], #1]! \n" + "1: \n" + " ldr r3, %[AndByY] \n" + " cmp %[depth], r0 \n" + " bls 2f \n" + + " and r1, r3, %[CC], asr #4 \n" + " and r0, r3, %[AA], asr #4 \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #7 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, r1, #0x70 \n" + " and r0, r0, #(14 << 3) \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " add r3, r3, r1 \n" + " add r3, r3, r0, asr #3 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " mov r1, #0x13000 \n" // r1 = ZDELTA + " ldrb r3, [%[d], r1] \n" + " movs r0, r0, lsl #2 \n" + " beq 2f \n" + " strb %[depth], [%[d]] \n" + + " ldr r1, [%[colors], r0] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + + "2: \n" + " add %[AA], %[AA], %[daa] \n" + " add %[p], %[p], #2 \n" + " add %[CC], %[CC], %[dcc] \n" + " subs %[x], %[x], #1 \n" + " ldrneb r0, [%[d], #1]! \n" + " bne 1b \n" + : [p] "+r" (p), + [d] "+r" (d), + [x] "+r" (x), + [AA] "+r" (AA), + [CC] "+r" (CC) + : [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + //[zdelta] "r" (GFX.DepthDelta), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "m" (fixedColour), + [depth] "r" (depth), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + + } + } + +} + +DEC_FMODE7(ROPNAME) +{ +#ifdef __DEBUG__ + #define DMESG(n) printf("Rendering Mode7, ROp: " #n ", R:%d, r2130: %d, bg: %d\n", PPU.Mode7Repeat, GFX.r2130 & 1, bg) + DMESG(ROPNAME) +#endif + CHECK_SOUND(); + + if (GFX.r2130 & 1) { + if (IPPU.DirectColourMapsNeedRebuild) S9xBuildDirectColourMaps (); + GFX.ScreenColors = DirectColourMaps [0]; + } else GFX.ScreenColors = IPPU.ScreenColors; + + switch (PPU.Mode7Repeat) { + case 0: + DrawBGMode7Background16R0(Screen, bg, depth); + return; + case 3: + DrawBGMode7Background16R3(Screen, bg, depth); + return; + default: + DrawBGMode7Background16R1R2(Screen, bg, depth); + return; + } +} diff --git a/src/mode7add.cpp b/src/mode7add.cpp new file mode 100644 index 0000000..0670b89 --- /dev/null +++ b/src/mode7add.cpp @@ -0,0 +1,5 @@ +#include "rops.h" +#define ROPNAME Add +#define ROP ROP_ADD(r1, r3) + +#include "mode7_t.h" diff --git a/src/mode7add1_2.cpp b/src/mode7add1_2.cpp new file mode 100644 index 0000000..c01ef6f --- /dev/null +++ b/src/mode7add1_2.cpp @@ -0,0 +1,6 @@ +#include "rops.h" +#define ROPNAME Add1_2 +#define ROP ROP_ADD1_2(r1, r3) + +#include "mode7_t.h" + diff --git a/src/mode7add1_2prio.cpp b/src/mode7add1_2prio.cpp new file mode 100644 index 0000000..0826461 --- /dev/null +++ b/src/mode7add1_2prio.cpp @@ -0,0 +1,8 @@ +#include "rops.h" +#define ROPNAME Add1_2 +#define ROP ROP_ADD1_2(r1, r3) + +#include "mode7prio_t.h" + + + diff --git a/src/mode7addprio.cpp b/src/mode7addprio.cpp new file mode 100644 index 0000000..38cbdfd --- /dev/null +++ b/src/mode7addprio.cpp @@ -0,0 +1,5 @@ +#include "rops.h" +#define ROPNAME Add +#define ROP ROP_ADD(r1, r3) + +#include "mode7prio_t.h" diff --git a/src/mode7new.cpp b/src/mode7new.cpp new file mode 100644 index 0000000..33ff453 --- /dev/null +++ b/src/mode7new.cpp @@ -0,0 +1,439 @@ +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; +extern uint8 Mode7Depths [2]; + +#define M7 19 + +#ifdef __DEBUG__ + + #define DMSG(rop) printf("Rendering Mode7, ROp: " rop ", R:%d, r2130: %d\n", PPU.Mode7Repeat, GFX.r2130 & 1) +#else + #define DMSG(rop) +#endif + +void DrawBGMode7Background16NewR0 (uint8 *Screen); +void DrawBGMode7Background16NewR1R2 (uint8 *Screen); +void DrawBGMode7Background16NewR3 (uint8 *Screen); + +void DrawBGMode7Background16New (uint8 *Screen) +{ + DMSG("totally opaque"); + CHECK_SOUND(); + + if (GFX.r2130 & 1) { + if (IPPU.DirectColourMapsNeedRebuild) S9xBuildDirectColourMaps (); + GFX.ScreenColors = DirectColourMaps [0]; + } else GFX.ScreenColors = IPPU.ScreenColors; + + switch (PPU.Mode7Repeat) { + case 0: + DrawBGMode7Background16NewR0(Screen); + return; + case 3: + DrawBGMode7Background16NewR3(Screen); + return; + default: + DrawBGMode7Background16NewR1R2(Screen); + return; + } +} + +#define M7C 0x1fff + +void DrawBGMode7Background16NewR3 (uint8 *Screen) +{ + uint8 *VRAM1 = Memory.VRAM + 1; + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int HOffset; + int VOffset; + int CentreX; + int CentreY; + uint16 *p; + int dir; + int yy; + int xx; + int yy3; + int xx3; + int BB; + int DD; + int Line; + uint32 clip; + + //FILE *f = fopen("mode7.log", "a"); + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + yy3 = ((yy + CentreY) & 7) << 4; + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + dir = -1; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + dir = 1; + } + + int AA = (l->MatrixA * (startx + xx) + BB); + int CC = (l->MatrixC * (startx + xx) + DD); + + int width = Right - Left; + xx3 = (startx + HOffset); + + //fprintf(f, "AA:%d, CC:%d, daa: %d, dcc: %d, MA: %d, MB: %d, MC: %d, MD: %d\n", AA, CC, aa, cc, l->MatrixA, l->MatrixB, l->MatrixC, l->MatrixD); + + + asm volatile ( + "1: \n" + " mov r3, %[AA], asr #18 \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " mov r3, %[CC], asr #11 \n" + " mov r1, %[AA], asr #11 \n" + " add r3, r1, r3, lsl #7 \n" + " mov r3, r3, lsl #1 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, %[CC], #(7 << 8) \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " and r0, %[AA], #(7 << 8) \n" + " add r3, r3, r1, asr #4 \n" + " add r3, r3, r0, asr #7 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " add %[AA], %[AA], %[daa] \n" + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " add %[xx3], %[xx3], %[dir] \n" + " strneh r1, [%[p]] \n" + " \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + " b 3f \n" + "2: \n" + " and r0, %[xx3], #7 \n" + " add r3, %[yy3], r0, lsl #1 \n" + " \n" + " add r3, %[VRAM], r3 \n" + " ldrb r0, [r3, #1] \n" + " add %[AA], %[AA], %[daa] \n" + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " add %[xx3], %[xx3], %[dir] \n" + " strneh r1, [%[p]] \n" + " \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + "3: \n" + : [xx3] "+r" (xx3), + [x] "+r" (width), + [p] "+r" (p), + [AA] "+r" (AA), + [CC] "+r" (CC) + : [yy3] "r" (yy3), + [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [dir] "r" (dir) + : "r0", "r1", "r3", "cc" + ); + } + } + + //fclose(f); + +} + +void DrawBGMode7Background16NewR1R2 (uint8 *Screen) +{ + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint16 *p; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint32 AndByY; + uint32 AndByX = 0xffffffff; + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) AndByX = 0x7ff; + AndByY = AndByX << 4; + AndByX = AndByX << 1; + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + "1: \n" + " mov r3, %[AA], asr #18 \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " and r1, %[AndByY], %[CC], asr #4 \n" + " and r0, %[AndByX], %[AA], asr #7 \n" + " \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " and r1, r1, #0x70 \n" + " \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " add %[AA], %[AA], %[daa] \n" + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " add %[CC], %[CC], %[dcc] \n" + " strneh r1, [%[p]] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + " b 3f \n" + "2: \n" + " add %[AA], %[AA], %[daa] \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + "3: \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [AndByX] "r" (AndByX), + [AndByY] "r" (AndByY) + : "r0", "r1", "r3", "cc" + ); + } + } +} + + +void DrawBGMode7Background16NewR0 (uint8 *Screen) +{ + uint8 *VRAM1 = Memory.VRAM + 1; + int aa, cc; + int startx; + uint32 Left; + uint32 Right; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint16 *p; +uint8 *z; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + struct SLineMatrixData *l; + + + + Left = 0; + Right = 256; + + + if (!ClipCount) ClipCount = 1; + + + l = &LineMatrixData [GFX.StartY]; + Screen += GFX.StartY * GFX_PITCH; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + /*yy += (VOffset - CentreY) % 1023; + xx = (HOffset - CentreX) % 1023; +*/ + + yy += ((VOffset - CentreY) << (32-10+1)) >> (32-10+1) ; + xx = ((HOffset - CentreX) << (32-10+1)) >> (32-10+1); + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + + p = (uint16 *) Screen + Left; + + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + " \n" + "1: \n" + " and r1, %[AndByY], %[CC], asr #4 \n" + " and r3, r1, #0x7f \n" + " and r0, %[AndByX], %[AA], asr #7 \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, r1, #0x70 \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " add %[AA], %[AA], %[daa] \n" + " movs r0, r0, lsl #2 \n" + " add %[CC], %[CC], %[dcc] \n" + " ldrne r1, [%[colors], r0] \n" + " add %[p], %[p], #2 \n" + " strneh r1, [%[p]] \n" + " \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [AndByX] "r" (0x3ff << 1), + [AndByY] "r" (0x3ff << 4) + : "r0", "r1", "r3", "cc" + ); + + } + } + +} + diff --git a/src/mode7prio.cpp b/src/mode7prio.cpp new file mode 100644 index 0000000..e4878fd --- /dev/null +++ b/src/mode7prio.cpp @@ -0,0 +1,503 @@ +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; +extern uint8 Mode7Depths [2]; + +#define M7 19 + +/* +void DrawBGMode7Background16Prio (uint8 *Screen, int bg) +{ + RENDER_BACKGROUND_MODE7PRIO (GFX.ScreenColors [b & 0x7f]); +} +*/ + + +#ifdef __DEBUG__ + + #define DMSG(rop) printf("Rendering Mode7 w/prio, ROp: " rop ", R:%d, r2130: %d, bg: %d\n", PPU.Mode7Repeat, GFX.r2130 & 1, bg) +#else + #define DMSG(rop) +#endif + +void DrawBGMode7Background16PrioR0 (uint8 *Screen, int bg); +void DrawBGMode7Background16PrioR1R2 (uint8 *Screen, int bg); +void DrawBGMode7Background16PrioR3 (uint8 *Screen, int bg); + +void DrawBGMode7Background16Prio (uint8 *Screen, int bg) +{ + DMSG("opaque"); + CHECK_SOUND(); + + if (GFX.r2130 & 1) { + if (IPPU.DirectColourMapsNeedRebuild) S9xBuildDirectColourMaps (); + GFX.ScreenColors = DirectColourMaps [0]; + } else GFX.ScreenColors = IPPU.ScreenColors; + + switch (PPU.Mode7Repeat) { + case 0: + DrawBGMode7Background16PrioR0(Screen, bg); + return; + case 3: + DrawBGMode7Background16PrioR3(Screen, bg); + return; + default: + DrawBGMode7Background16PrioR1R2(Screen, bg); + return; + } +} + +#define M7C 0x1fff + +void DrawBGMode7Background16PrioR3 (uint8 *Screen, int bg) +{ + + uint8 *VRAM1 = Memory.VRAM + 1; + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int dir; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint8 *Depth; + uint32 depth = Mode7Depths[0] | (Mode7Depths[1] << 8); + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + dir = -1; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + dir = 1; + } + asm volatile ( + "1: \n" + " mov r3, %[AA], lsr #18 \n" + " orrs r3, r3, %[CC], lsr #18 \n" + " bne 2f \n" + " \n" + " mov r3, %[CC], lsr #11 \n" + " mov r1, %[AA], lsr #11 \n" + " add r3, r1, r3, lsl #7 \n" + " mov r3, r3, lsl #1 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " mov r1, %[CC], lsr #8 \n" + " mov r0, %[AA], lsr #8 \n" + " \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r1, r1, #7 \n" + " and r0, r0, #7 \n" + " add r3, r3, r1, lsl #4 \n" + " add r3, r3, r0, lsl #1 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d]] \n" + " tst r0, #0x80 \n" + " andeq r1, %[depth], #0xff \n" + " mov r1, %[depth], lsr #8 \n" + " cmp r1, r3 \n" + " bls 4f \n" + + " ldr r1, %[daa] \n" + " movs r0, r0, lsl #2 \n" + " add %[AA], %[AA], r1 \n" + " ldrne r1, [%[colors], r0] \n" + " add %[xx3], %[xx3], %[dir] \n" + " strneb %[depth], [%[d]] \n" + " ldr r0, %[dcc] \n" + " strneh r1, [%[p]] \n" + " \n" + " add %[CC], %[CC], r0 \n" + " add %[d], %[d], #1 \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + " b 3f \n" + "2: \n" + " and r1, %[yy3], #7 \n" + " and r0, %[xx3], #7 \n" + " mov r3, r1, lsl #4 \n" + " add r3, r3, r0, lsl #1 \n" + " \n" + " add r3, %[VRAM], r3 \n" + + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d]] \n" + " tst r0, #0x80 \n" + " andeq r1, %[depth], #0xff \n" + " mov r1, %[depth], lsr #8 \n" + " cmp r1, r3 \n" + " bls 4f \n" + + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " strneb %[depth], [%[d]] \n" + " strneh r1, [%[p]] \n" + "4: \n" + " ldr r0, %[daa] \n" + " ldr r1, %[dcc] \n" + " add %[xx3], %[xx3], %[dir] \n" + " add %[AA], %[AA], r0 \n" + " add %[CC], %[CC], r1 \n" + " add %[p], %[p], #2 \n" + " add %[d], %[d], #1 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + "3: \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "m" (aa), + [dcc] "m" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d), + [depth] "r" (depth), + [dir] "r" (dir), + [yy3] "r" (yy + CentreY), + [xx3] "r" (startx + HOffset) + : "r0", "r1", "r3", "cc" + ); + } + } + +} + +void DrawBGMode7Background16PrioR1R2 (uint8 *Screen, int bg) +{ + + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint32 AndByY; + uint32 AndByX = 0xffffffff; + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) AndByX = 0x7ff; + AndByY = AndByX << 4; + AndByX = AndByX << 1; + uint8 *Depth; + uint32 depth = Mode7Depths[0] | (Mode7Depths[1] << 8); + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + "1: \n" + " mov r3, %[AA], lsr #18 \n" + " orrs r3, r3, %[CC], lsr #18 \n" + " bne 2f \n" + " \n" + " ldr r1, %[AndByY] \n" + " ldr r0, %[AndByX] \n" + " and r1, r1, %[CC], lsr #4 \n" + " and r0, r0, %[AA], lsr #7 \n" + " \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, lsr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " and r1, r1, #0x70 \n" + " \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d]] \n" + " tst r0, #0x80 \n" + " andeq r1, %[depth], #0xff \n" + " mov r1, %[depth], lsr #8 \n" + " cmp r1, r3 \n" + " bls 2f \n" + + " add %[AA], %[AA], %[daa] \n" + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " strneb %[depth], [%[d]] \n" + " add %[CC], %[CC], %[dcc] \n" + " strneh r1, [%[p]] \n" + " add %[p], %[p], #2 \n" + " add %[d], %[d], #1 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + " b 3f \n" + "2: \n" + " add %[AA], %[AA], %[daa] \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " add %[d], %[d], #1 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + "3: \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d), + [depth] "r" (depth), + [AndByX] "m" (AndByX), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + } + } +} + + +void DrawBGMode7Background16PrioR0 (uint8 *Screen, int bg) +{ + uint8 *VRAM1 = Memory.VRAM + 1; + int aa, cc; + int startx; + uint32 Left; + uint32 Right; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint16 *p; + uint8 *d; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + struct SLineMatrixData *l; + uint8 *Depth; + uint32 depth = Mode7Depths[0] | (Mode7Depths[1] << 8); + + Left = 0; + Right = 256; + + + if (!ClipCount) ClipCount = 1; + + + l = &LineMatrixData [GFX.StartY]; + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += (VOffset - CentreY) % 1023; + xx = (HOffset - CentreX) % 1023; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + " b 1f \n" + "7: \n" // AndByX + " .word (0x3ff << 1) \n" + "8: \n" // AndByY + " .word (0x3ff << 4) \n" + " \n" + "1: \n" + " ldr r3, 8b \n" + " ldr r0, 7b \n" + " and r1, r3, %[CC], lsr #4 \n" + " and r3, r1, #0x7f \n" + " and r0, r0, %[AA], lsr #7 \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, lsr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, r1, #0x70 \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d]] \n" + " tst r0, #0x80 \n" + " andeq r1, %[depth], #0xff \n" + " mov r1, %[depth], lsr #8 \n" + " cmp r1, r3 \n" + " bls 2f \n" + + " movs r0, r0, lsl #2 \n" + " ldrne r1, [%[colors], r0] \n" + " strneb %[depth], [%[d]] \n" + " strneh r1, [%[p]] \n" + " \n" + "2: \n" + " add %[AA], %[AA], %[daa] \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " add %[d], %[d], #1 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d), + [depth] "r" (depth) + : "r0", "r1", "r3", "cc" + ); + + } + } + +} + diff --git a/src/mode7prio_t.h b/src/mode7prio_t.h new file mode 100644 index 0000000..24d0062 --- /dev/null +++ b/src/mode7prio_t.h @@ -0,0 +1,535 @@ +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; +extern uint8 Mode7Depths [2]; + +#define M7 19 +#define M7C 0x1fff + +#define MACRO_CONCAT(a,b) a##b +#define DEC_FMODE7(n) MACRO_CONCAT(void DrawBGMode7Background16Prio, n)(uint8 *Screen, int bg) + +static void DrawBGMode7Background16R3 (uint8 *Screen, int bg) +{ + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int dir; + int yy; + int yy3; + int xx3; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + uint32 depth = Mode7Depths[0] | (Mode7Depths[1] << 8); + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + yy3 = ((yy + CentreY) & 7) << 4; + + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + dir = -1; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + dir = 1; + } + + xx3 = (startx + HOffset); + + asm volatile ( + "1: \n" + " mov r3, %[AA], asr #18 \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " mov r3, %[CC], asr #11 \n" + " mov r1, %[AA], asr #11 \n" + " add r3, r1, r3, lsl #7 \n" + " mov r3, r3, lsl #1 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, %[CC], #(7 << 8) \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " and r0, %[AA], #(7 << 8) \n" + " add r3, r3, r1, asr #4 \n" + " add r3, r3, r0, asr #7 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d], #1]! \n" + " movs r1, r0, lsl #24 \n" + " beq 4f \n" + " andpl r1, %[depth], #0xff \n" + " movmi r1, %[depth], asr #8 \n" + " cmp r1, r3 \n" + " bls 4f \n" + + " strb r1, [%[d]] \n" + + " mov r1, #0x13000 \n" // R1 = ZDELTA + " ldrb r3, [%[d], r1] \n" + " ldr r1, [%[colors], r0, lsl #2] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " addne r0, %[delta], %[delta] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + + " ldr r3, %[dir] \n" + " ldr r1, %[daa] \n" + //" ldr r0, %[dcc] \n" + " add %[xx3], %[xx3], r3 \n" + " add %[AA], %[AA], r1 \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + " b 3f \n" + "2: \n" + " ldr r3, %[yy3] \n" + " and r0, %[xx3], #7 \n" + //" and r1, r3, #7 \n" + //" mov r3, r1, lsl #4 \n" + " add r3, r3, r0, lsl #1 \n" + " \n" + " add r3, %[VRAM], r3 \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d], #1]! \n" + " movs r1, r0, lsl #24 \n" + " beq 4f \n" + " andpl r1, %[depth], #0xff \n" + " movmi r1, %[depth], asr #8 \n" + " cmp r1, r3 \n" + " bls 4f \n" + + " strb r1, [%[d]] \n" + + " mov r1, #0x13000 \n" // R1 = ZDELTA + " ldrb r3, [%[d], r1] \n" + " ldr r1, [%[colors], r0, lsl #2] \n" + + " cmp r3, #1 \n" + " blo 12f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "12: \n" + " strh r1, [%[p]] \n" + "4: \n" + " ldr r3, %[dir] \n" + " ldr r0, %[daa] \n" + //" ldr r1, %[dcc] \n" + " add %[xx3], %[xx3], r3 \n" + " add %[AA], %[AA], r0 \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + "3: \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "m" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d-1), + [depth] "r" (depth), + [dir] "m" (dir), + [yy3] "m" (yy3), + //[zdelta] "r" (GFX.DepthDelta), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "m" (fixedColour), + [xx3] "r" (xx3) + : "r0", "r1", "r3", "cc" + ); + } + } + +} + +static void DrawBGMode7Background16R1R2 (uint8 *Screen, int bg) +{ + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint32 AndByY; + uint32 AndByX = 0xffffffff; + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) AndByX = 0x7ff; + AndByY = AndByX << 4; + AndByX = AndByX << 1; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + uint32 depth = Mode7Depths[0] | (Mode7Depths[1] << 8); + + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + "1: \n" + " mov r3, %[AA], asr #18 \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " ldr r1, %[AndByY] \n" + " ldr r0, %[AndByX] \n" + " and r1, r1, %[CC], asr #4 \n" + " and r0, r0, %[AA], asr #7 \n" + " \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " and r1, r1, #0x70 \n" + " \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d], #1]! \n" + " movs r1, r0, lsl #24 \n" + " beq 2f \n" + " andpl r1, %[depth], #0xff \n" + " movmi r1, %[depth], asr #8 \n" + " cmp r1, r3 \n" + " bls 2f \n" + + " strb r1, [%[d]] \n" + + " mov r1, #0x13000 \n" // R1 = ZDELTA + " ldrb r3, [%[d], r1] \n" + " ldr r1, [%[colors], r0, lsl #2] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + "2: \n" + //" ldr r0, %[dcc] \n" + " add %[AA], %[AA], %[daa] \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d-1), + [depth] "r" (depth), + //[zdelta] "r" (GFX.DepthDelta), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "m" (fixedColour), + [AndByX] "m" (AndByX), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + } + } +} + + + +static void DrawBGMode7Background16R0 (uint8 *Screen, int bg) +{ + int aa, cc; + int startx; + uint32 Left; + uint32 Right; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint16 *p; + uint8 *d; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + struct SLineMatrixData *l; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + uint32 depth = Mode7Depths[0] | (Mode7Depths[1] << 8); + unsigned int AndByY = (0x3ff << 4); + + Left = 0; + Right = 256; + + + if (!ClipCount) ClipCount = 1; + + + l = &LineMatrixData [GFX.StartY]; + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += (VOffset - CentreY) % 1023; + xx = (HOffset - CentreX) % 1023; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + " ldr r3, %[AndByY] \n" + "1: \n" + " and r1, r3, %[CC], asr #4 \n" + " and r0, r3, %[AA], asr #4 \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #7 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, r1, #0x70 \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #(14 << 3) \n" + " add r3, r3, r1 \n" + " add r3, r3, r0, asr #3 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d], #1]! \n" + " movs r1, r0, lsl #24 \n" + " beq 2f \n" + " andpl r1, %[depth], #0xff \n" + " movmi r1, %[depth], asr #8 \n" + " cmp r1, r3 \n" + " bls 2f \n" + + " strb r1, [%[d]] \n" + + " mov r1, #0x13000 \n" // R1 = ZDELTA + " ldrb r3, [%[d], r1] \n" + " ldr r1, [%[colors], r0, lsl #2] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + + "2: \n" + //" ldr r0, %[dcc] \n" + " add %[AA], %[AA], %[daa] \n" + " add %[CC], %[CC], %[dcc] \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " ldrne r3, %[AndByY] \n" + " bne 1b \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "r" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d-1), + //[zdelta] "r" (GFX.DepthDelta), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "m" (fixedColour), + [depth] "r" (depth), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + + } + } + +} + +DEC_FMODE7(ROPNAME) +{ +#ifdef __DEBUG__ + #define TOSTRING(n) #n + printf("Rendering Mode7 w/prio, ROp: " TOSTRING(ROPNAME) ", R:%d, r2130: %d, bg: %d\n", PPU.Mode7Repeat, GFX.r2130 & 1, bg) +#endif + CHECK_SOUND(); + + if (GFX.r2130 & 1) { + if (IPPU.DirectColourMapsNeedRebuild) S9xBuildDirectColourMaps (); + GFX.ScreenColors = DirectColourMaps [0]; + } else GFX.ScreenColors = IPPU.ScreenColors; + + switch (PPU.Mode7Repeat) { + case 0: + DrawBGMode7Background16R0(Screen, bg); + return; + case 3: + DrawBGMode7Background16R3(Screen, bg); + return; + default: + DrawBGMode7Background16R1R2(Screen, bg); + return; + } +} + diff --git a/src/mode7prio_t.h.last b/src/mode7prio_t.h.last new file mode 100644 index 0000000..444c1fd --- /dev/null +++ b/src/mode7prio_t.h.last @@ -0,0 +1,540 @@ +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "gfx.h" +#include "apu.h" + +extern struct SLineData LineData[240]; +extern struct SLineMatrixData LineMatrixData [240]; +extern uint8 Mode7Depths [2]; + +#define M7 19 +#define M7C 0x1fff + +#define MACRO_CONCAT(a,b) a##b +#define DEC_FMODE7(n) MACRO_CONCAT(void DrawBGMode7Background16Prio, n)(uint8 *Screen, int bg) + +static void DrawBGMode7Background16R3 (uint8 *Screen, int bg) +{ + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int dir; + int yy; + int yy3; + int xx3; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + uint32 depth = Mode7Depths[0] | (Mode7Depths[1] << 8); + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + yy3 = ((yy + CentreY) & 7) << 4; + + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + dir = -1; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + dir = 1; + } + + xx3 = (startx + HOffset); + + asm volatile ( + "1: \n" + " mov r3, %[AA], asr #18 \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " mov r3, %[CC], asr #11 \n" + " mov r1, %[AA], asr #11 \n" + " add r3, r1, r3, lsl #7 \n" + " mov r3, r3, lsl #1 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, %[CC], #(7 << 8) \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " and r0, %[AA], #(7 << 8) \n" + " add r3, r3, r1, asr #4 \n" + " add r3, r3, r0, asr #7 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d], #1]! \n" + " movs r1, r0, lsl #24 \n" + " beq 4f \n" + " andpl r1, %[depth], #0xff \n" + " movmi r1, %[depth], asr #8 \n" + " cmp r1, r3 \n" + " bls 4f \n" + + " strb r1, [%[d]] \n" + + " ldrb r3, [%[d], %[zdelta]] \n" + " ldr r1, [%[colors], r0, lsl #2] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " addne r0, %[delta], %[delta] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + + " ldr r3, %[dir] \n" + " ldr r1, %[daa] \n" + " ldr r0, %[dcc] \n" + " add %[xx3], %[xx3], r3 \n" + " add %[AA], %[AA], r1 \n" + " add %[CC], %[CC], r0 \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + " b 3f \n" + "2: \n" + " ldr r3, %[yy3] \n" + " and r0, %[xx3], #7 \n" + //" and r1, r3, #7 \n" + //" mov r3, r1, lsl #4 \n" + " add r3, r3, r0, lsl #1 \n" + " \n" + " add r3, %[VRAM], r3 \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d], #1]! \n" + " movs r1, r0, lsl #24 \n" + " beq 4f \n" + " andpl r1, %[depth], #0xff \n" + " movmi r1, %[depth], asr #8 \n" + " cmp r1, r3 \n" + " bls 4f \n" + + " strb r1, [%[d]] \n" + + " ldrb r3, [%[d], %[zdelta]] \n" + " ldr r1, [%[colors], r0, lsl #2] \n" + + " cmp r3, #1 \n" + " blo 12f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "12: \n" + " strh r1, [%[p]] \n" + "4: \n" + " ldr r3, %[dir] \n" + " ldr r0, %[daa] \n" + " ldr r1, %[dcc] \n" + " add %[xx3], %[xx3], r3 \n" + " add %[AA], %[AA], r0 \n" + " add %[CC], %[CC], r1 \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + "3: \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "m" (aa), + [dcc] "m" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d-1), + [depth] "r" (depth), + [dir] "m" (dir), + [yy3] "m" (yy3), + [zdelta] "r" (GFX.DepthDelta), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "m" (fixedColour), + [xx3] "r" (xx3) + : "r0", "r1", "r3", "cc" + ); + } + } + +} + +static void DrawBGMode7Background16R1R2 (uint8 *Screen, int bg) +{ + int aa, cc; + int startx; + uint32 Left = 0; + uint32 Right = 256; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint8 *d; + uint16 *p; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + uint8 b; + uint32 AndByY; + uint32 AndByX = 0xffffffff; + if (Settings.Dezaemon && PPU.Mode7Repeat == 2) AndByX = 0x7ff; + AndByY = AndByX << 4; + AndByX = AndByX << 1; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + uint32 depth = Mode7Depths[0] | (Mode7Depths[1] << 8); + + + if (!ClipCount) ClipCount = 1; + + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + struct SLineMatrixData *l = &LineMatrixData [GFX.StartY]; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += VOffset - CentreY; + xx = HOffset - CentreX; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + "1: \n" + " mov r3, %[AA], asr #18 \n" + " orrs r3, r3, %[CC], asr #18 \n" + " bne 2f \n" + " \n" + " ldr r1, %[AndByY] \n" + " ldr r0, %[AndByX] \n" + " and r1, r1, %[CC], asr #4 \n" + " and r0, r0, %[AA], asr #7 \n" + " \n" + " and r3, r1, #0x7f \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " and r1, r1, #0x70 \n" + " \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d], #1]! \n" + " movs r1, r0, lsl #24 \n" + " beq 2f \n" + " andpl r1, %[depth], #0xff \n" + " movmi r1, %[depth], asr #8 \n" + " cmp r1, r3 \n" + " bls 2f \n" + + " strb r1, [%[d]] \n" + + " ldrb r3, [%[d], %[zdelta]] \n" + " ldr r1, [%[colors], r0, lsl #2] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + "2: \n" + " ldr r0, %[dcc] \n" + " add %[AA], %[AA], %[daa] \n" + " add %[CC], %[CC], r0 \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " bne 1b \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "m" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d-1), + [depth] "r" (depth), + [zdelta] "r" (GFX.DepthDelta), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "m" (fixedColour), + [AndByX] "m" (AndByX), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + } + } +} + + + +static void DrawBGMode7Background16R0 (uint8 *Screen, int bg) +{ + int aa, cc; + int startx; + uint32 Left; + uint32 Right; + uint32 ClipCount = GFX.pCurrentClip->Count [0]; + + int32 HOffset; + int32 VOffset; + int32 CentreX; + int32 CentreY; + uint16 *p; + uint8 *d; + int yy; + int xx; + int BB; + int DD; + uint32 Line; + uint32 clip; + struct SLineMatrixData *l; + uint8 *Depth; + unsigned int fixedColour = GFX.FixedColour; + uint32 depth = Mode7Depths[0] | (Mode7Depths[1] << 8); + unsigned int AndByY = (0x3ff << 4); + + Left = 0; + Right = 256; + + + if (!ClipCount) ClipCount = 1; + + + l = &LineMatrixData [GFX.StartY]; + Screen += GFX.StartY * GFX_PITCH; + Depth = GFX.DB + GFX.StartY * GFX_PPL; + + for (Line = GFX.StartY; Line <= GFX.EndY; Line++, Screen += GFX_PITCH, Depth += GFX_PPL, l++) { + HOffset = ((int32) LineData[Line].BG[0].HOffset << M7) >> M7; + VOffset = ((int32) LineData[Line].BG[0].VOffset << M7) >> M7; + + CentreX = ((int32) l->CentreX << M7) >> M7; + CentreY = ((int32) l->CentreY << M7) >> M7; + + if (PPU.Mode7VFlip) yy = 255 - (int) Line; + else yy = Line; + + yy += (VOffset - CentreY) % 1023; + xx = (HOffset - CentreX) % 1023; + + BB = l->MatrixB * yy + (CentreX << 8); + DD = l->MatrixD * yy + (CentreY << 8); + + for (clip = 0; clip < ClipCount; clip++) + { + if (GFX.pCurrentClip->Count [0]){ + Left = GFX.pCurrentClip->Left [clip][0]; + Right = GFX.pCurrentClip->Right [clip][0]; + if (Right <= Left) continue; + } + + p = (uint16 *) Screen + Left; + d = Depth + Left; + + if (PPU.Mode7HFlip) { + startx = Right - 1; + aa = -l->MatrixA; + cc = -l->MatrixC; + } else { + startx = Left; + aa = l->MatrixA; + cc = l->MatrixC; + } + asm volatile ( + //" b 1f \n" + //"7: \n" // AndByX + //" .word (0x3ff << 1) \n" + //"8: \n" // AndByY + //" .word (0x3ff << 4) \n" + //" \n" + " ldr r3, %[AndByY] \n" + "1: \n" + //" ldr r3, 8b \n" + //" ldr r0, 7b \n" + " mov r0, r3, lsr #3 \n" + " and r1, r3, %[CC], asr #4 \n" + " and r3, r1, #0x7f \n" + " and r0, r0, %[AA], asr #7 \n" + " sub r3, r1, r3 \n" + " add r3, r3, r0, asr #4 \n" + " add r3, r3, r3 \n" + " ldrb r3, [%[VRAM], r3] \n" + " \n" + " and r1, r1, #0x70 \n" + " add r3, %[VRAM], r3, lsl #7 \n" + " \n" + " and r0, r0, #14 \n" + " add r3, r3, r1 \n" + " add r3, r3, r0 \n" + " \n" + " ldrb r0, [r3, #1] \n" + " ldrb r3, [%[d], #1]! \n" + " movs r1, r0, lsl #24 \n" + " beq 2f \n" + " andpl r1, %[depth], #0xff \n" + " movmi r1, %[depth], asr #8 \n" + " cmp r1, r3 \n" + " bls 2f \n" + + " strb r1, [%[d]] \n" + + " ldrb r3, [%[d], %[zdelta]] \n" + " ldr r1, [%[colors], r0, lsl #2] \n" + + " cmp r3, #1 \n" + " blo 11f \n" + " ldrneh r3, [%[p], %[delta]] \n" + " ldreq r3, %[fixedcolour] \n" + + ROP + "11: \n" + " strh r1, [%[p]] \n" + + "2: \n" + " ldr r0, %[dcc] \n" + " add %[AA], %[AA], %[daa] \n" + " add %[CC], %[CC], r0 \n" + " add %[p], %[p], #2 \n" + " subs %[x], %[x], #1 \n" + " ldrne r3, %[AndByY] \n" + " bne 1b \n" + : + : [x] "r" (Right - Left), + [AA] "r" (l->MatrixA * (startx + xx) + BB), + [CC] "r" (l->MatrixC * (startx + xx) + DD), + [daa] "r" (aa), + [dcc] "m" (cc), + [VRAM] "r" (Memory.VRAM), + [colors] "r" (GFX.ScreenColors), + [p] "r" (p), + [d] "r" (d-1), + [zdelta] "r" (GFX.DepthDelta), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "m" (fixedColour), + [depth] "r" (depth), + [AndByY] "m" (AndByY) + : "r0", "r1", "r3", "cc" + ); + + } + } + +} + +DEC_FMODE7(ROPNAME) +{ +#ifdef __DEBUG__ + #define TOSTRING(n) #n + printf("Rendering Mode7 w/prio, ROp: " TOSTRING(ROPNAME) ", R:%d, r2130: %d, bg: %d\n", PPU.Mode7Repeat, GFX.r2130 & 1, bg) +#endif + CHECK_SOUND(); + + if (GFX.r2130 & 1) { + if (IPPU.DirectColourMapsNeedRebuild) S9xBuildDirectColourMaps (); + GFX.ScreenColors = DirectColourMaps [0]; + } else GFX.ScreenColors = IPPU.ScreenColors; + + switch (PPU.Mode7Repeat) { + case 0: + DrawBGMode7Background16R0(Screen, bg); + return; + case 3: + DrawBGMode7Background16R3(Screen, bg); + return; + default: + DrawBGMode7Background16R1R2(Screen, bg); + return; + } +} + diff --git a/src/mode7sub.cpp b/src/mode7sub.cpp new file mode 100644 index 0000000..2ba1209 --- /dev/null +++ b/src/mode7sub.cpp @@ -0,0 +1,6 @@ +#include "rops.h" +#define ROPNAME Sub +#define ROP ROP_SUB(r1, r3) + +#include "mode7_t.h" + diff --git a/src/mode7sub1_2.cpp b/src/mode7sub1_2.cpp new file mode 100644 index 0000000..0b87cbf --- /dev/null +++ b/src/mode7sub1_2.cpp @@ -0,0 +1,6 @@ +#include "rops.h" +#define ROPNAME Sub1_2 +#define ROP ROP_SUB1_2(r1, r3) + +#include "mode7_t.h" + diff --git a/src/mode7sub1_2prio.cpp b/src/mode7sub1_2prio.cpp new file mode 100644 index 0000000..6da6869 --- /dev/null +++ b/src/mode7sub1_2prio.cpp @@ -0,0 +1,5 @@ +#include "rops.h" +#define ROPNAME Sub1_2 +#define ROP ROP_SUB1_2(r1, r3) + +#include "mode7prio_t.h" diff --git a/src/mode7subprio.cpp b/src/mode7subprio.cpp new file mode 100644 index 0000000..61a3870 --- /dev/null +++ b/src/mode7subprio.cpp @@ -0,0 +1,6 @@ +#include "rops.h" +#define ROPNAME Sub +#define ROP ROP_SUB(r1, r3) + +#include "mode7prio_t.h" + diff --git a/src/movie.cpp b/src/movie.cpp new file mode 100644 index 0000000..518cd82 --- /dev/null +++ b/src/movie.cpp @@ -0,0 +1,786 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + Input recording/playback code + (c) Copyright 2004 blip + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#include "port.h" +#include +#ifdef HAVE_STRINGS_H +#include +#endif +#include +#include + +#if defined(__unix) || defined(__linux) || defined(__sun) || defined(__DJGPP) +#include +#include +#include +#endif +#include + +#ifdef WIN32 +#include +#ifndef W_OK +#define W_OK 2 +#endif +#endif + +#include "movie.h" +#include "snes9x.h" +#include "cpuexec.h" +#include "snapshot.h" + +#define SMV_MAGIC 0x1a564d53 // SMV0x1a +#define SMV_VERSION 1 +#define SMV_HEADER_SIZE 32 +#define CONTROLLER_DATA_SIZE 2 +#define BUFFER_GROWTH_SIZE 4096 + +enum MovieState +{ + MOVIE_STATE_NONE=0, + MOVIE_STATE_PLAY, + MOVIE_STATE_RECORD +}; + +static struct SMovie +{ + enum MovieState State; + char Filename [_MAX_PATH]; + FILE* File; + uint32 SaveStateOffset; + uint32 ControllerDataOffset; + uint32 MovieId; + uint32 CurrentFrame; + uint32 MaxFrame; + uint32 RerecordCount; + uint8 ControllersMask; + uint8 Opts; + bool8 ReadOnly; + uint32 BytesPerFrame; + uint8* InputBuffer; + uint32 InputBufferSize; + uint8* InputBufferPtr; + bool8 FrameDisplay; + char FrameDisplayString[256]; +} Movie; + +/* + For illustration: +struct MovieFileHeader +{ + uint32 magic; // SMV0x1a + uint32 version; + uint32 uid; // used to match savestates to a particular movie + uint32 rerecord_count; + uint32 length_frames; + uint8 flags[4]; + uint32 offset_to_savestate; // smvs have an embedded savestate + uint32 offset_to_controller_data; + // after the header comes extra metadata + // sizeof(metadata) = offset_to_savestate - sizeof(MovieFileHeader) +}; +*/ + +static int bytes_per_frame() +{ + int i; + int num_controllers; + + num_controllers=0; + for(i=0; i<5; ++i) + { + if(Movie.ControllersMask & (1<>8)&0xff); + ptr[2]=(uint8)((v>>16)&0xff); + ptr[3]=(uint8)((v>>24)&0xff); + ptr += 4; +} + +static void Write16(uint16 v, uint8*& ptr) +{ + ptr[0]=(uint8)(v&0xff); + ptr[1]=(uint8)((v>>8)&0xff); + ptr += 2; +} + +static int read_movie_header(FILE* fd, SMovie* movie) +{ + uint8 header[SMV_HEADER_SIZE]; + if(fread(header, 1, SMV_HEADER_SIZE, fd) != SMV_HEADER_SIZE) + return WRONG_FORMAT; + + const uint8* ptr=header; + uint32 magic=Read32(ptr); + if(magic!=SMV_MAGIC) + return WRONG_FORMAT; + + uint32 version=Read32(ptr); + if(version!=SMV_VERSION) + return WRONG_VERSION; + + movie->MovieId=Read32(ptr); + movie->RerecordCount=Read32(ptr); + movie->MaxFrame=Read32(ptr); + + movie->ControllersMask=*ptr++; + movie->Opts=*ptr++; + ptr += 2; + + movie->SaveStateOffset=Read32(ptr); + movie->ControllerDataOffset=Read32(ptr); + + return SUCCESS; +} + +static void write_movie_header(FILE* fd, const SMovie* movie) +{ + uint8 header[SMV_HEADER_SIZE]; + uint8* ptr=header; + + Write32(SMV_MAGIC, ptr); + Write32(SMV_VERSION, ptr); + Write32(movie->MovieId, ptr); + Write32(movie->RerecordCount, ptr); + Write32(movie->MaxFrame, ptr); + + *ptr++=movie->ControllersMask; + *ptr++=movie->Opts; + *ptr++=0; + *ptr++=0; + + Write32(movie->SaveStateOffset, ptr); + Write32(movie->ControllerDataOffset, ptr); + + fwrite(header, 1, SMV_HEADER_SIZE, fd); +} + +static void flush_movie() +{ + fseek(Movie.File, 0, SEEK_SET); + write_movie_header(Movie.File, &Movie); + fseek(Movie.File, Movie.ControllerDataOffset, SEEK_SET); + fwrite(Movie.InputBuffer, 1, Movie.BytesPerFrame*(Movie.MaxFrame+1), Movie.File); +} + +static void change_state(MovieState new_state) +{ + if(new_state==Movie.State) + return; + + if(Movie.State==MOVIE_STATE_RECORD) + { + flush_movie(); + } + + Movie.State=new_state; + + if(new_state==MOVIE_STATE_NONE) + { + fclose(Movie.File); + Movie.File=NULL; + // FIXME: truncate movie to MaxFrame length + /* truncate() could be used, if it's certain + * that the savestate block is never after + * the controller data block. It is not guaranteed + * by the format. + */ + } +} + +static void reserve_buffer_space(uint32 space_needed) +{ + if(space_needed > Movie.InputBufferSize) + { + uint32 ptr_offset = Movie.InputBufferPtr - Movie.InputBuffer; + uint32 alloc_chunks = space_needed / BUFFER_GROWTH_SIZE; + Movie.InputBufferSize = BUFFER_GROWTH_SIZE * (alloc_chunks+1); + Movie.InputBuffer = (uint8*)realloc(Movie.InputBuffer, Movie.InputBufferSize); + Movie.InputBufferPtr = Movie.InputBuffer + ptr_offset; + } +} + +static void read_frame_controller_data() +{ + int i; + for(i=0; i<5; ++i) + { + if(Movie.ControllersMask & (1<MOVIE_MAX_METADATA) + { + metadata_length=MOVIE_MAX_METADATA; + } + + Movie.MovieId=(uint32)time(NULL); + Movie.RerecordCount=0; + Movie.MaxFrame=0; + Movie.SaveStateOffset=SMV_HEADER_SIZE+(sizeof(uint16)*metadata_length); + Movie.ControllerDataOffset=0; + Movie.ControllersMask=controllers_mask; + Movie.Opts=opts; + if(Settings.PAL) + { + Movie.Opts |= MOVIE_OPT_PAL; + } + else + { + Movie.Opts &= ~MOVIE_OPT_PAL; + } + + write_movie_header(fd, &Movie); + + // convert wchar_t metadata string/array to a uint16 array + if(metadata_length>0) + { + uint8 meta_buf[MOVIE_MAX_METADATA * sizeof(uint16)]; + int i; + + for(i=0; i>8)&0xff); + } + + fwrite(meta_buf, sizeof(uint16), metadata_length, fd); + } + + // write snapshot + fn=dup(fileno(fd)); + fclose(fd); + + // lseek(fn, Movie.SaveStateOffset, SEEK_SET); + if(!(stream=REOPEN_STREAM(fn, "ab"))) + return FILE_NOT_FOUND; + + if(opts & MOVIE_OPT_FROM_RESET) + { + S9xReset(); + // save only SRAM for a from-reset snapshot + WRITE_STREAM(SRAM, 0x20000, stream); + } + else + { + S9xFreezeToStream(stream); + } + CLOSE_STREAM(stream); + + if(!(fd=fopen(filename, "rb+"))) + return FILE_NOT_FOUND; + + fseek(fd, 0, SEEK_END); + Movie.ControllerDataOffset=(uint32)ftell(fd); + + // write "baseline" controller data + Movie.File=fd; + Movie.BytesPerFrame=bytes_per_frame(); + Movie.InputBufferPtr=Movie.InputBuffer; + write_frame_controller_data(); + + strncpy(Movie.Filename, filename, _MAX_PATH); + Movie.Filename[_MAX_PATH-1]='\0'; + Movie.CurrentFrame=0; + Movie.ReadOnly=false; + change_state(MOVIE_STATE_RECORD); + + S9xMessage(S9X_INFO, S9X_MOVIE_INFO, MOVIE_INFO_RECORD); + return SUCCESS; +#endif +} + +void S9xMovieUpdate () +{ + switch(Movie.State) + { + case MOVIE_STATE_PLAY: + if(Movie.CurrentFrame>=Movie.MaxFrame) + { + change_state(MOVIE_STATE_NONE); + S9xMessage(S9X_INFO, S9X_MOVIE_INFO, MOVIE_INFO_END); + return; + } + else + { + if(Movie.FrameDisplay) + { + sprintf(Movie.FrameDisplayString, "Playing frame: %d", Movie.CurrentFrame); + S9xMessage (S9X_INFO, S9X_MOVIE_INFO, Movie.FrameDisplayString); + } + read_frame_controller_data(); + ++Movie.CurrentFrame; + } + break; + + case MOVIE_STATE_RECORD: + { + if(Movie.FrameDisplay) + { + sprintf(Movie.FrameDisplayString, "Recording frame: %d", Movie.CurrentFrame); + S9xMessage (S9X_INFO, S9X_MOVIE_INFO, Movie.FrameDisplayString); + } + write_frame_controller_data(); + ++Movie.CurrentFrame; + Movie.MaxFrame=Movie.CurrentFrame; + fwrite((Movie.InputBufferPtr - Movie.BytesPerFrame), 1, Movie.BytesPerFrame, Movie.File); + } + break; + + default: + break; + } +} + +void S9xMovieStop (bool8 suppress_message) +{ + if(Movie.State!=MOVIE_STATE_NONE) + { + change_state(MOVIE_STATE_NONE); + + if(!suppress_message) + S9xMessage(S9X_INFO, S9X_MOVIE_INFO, MOVIE_INFO_STOP); + } +} + +int S9xMovieGetInfo (const char* filename, struct MovieInfo* info) +{ + FILE* fd; + int result; + SMovie local_movie; + int metadata_length; + + return FILE_NOT_FOUND; +#if 0 + + memset(info, 0, sizeof(*info)); + if(!(fd=fopen(filename, "rb"))) + return FILE_NOT_FOUND; + + if((result=(read_movie_header(fd, &local_movie)))!=SUCCESS) + return result; + + info->TimeCreated=(time_t)local_movie.MovieId; + info->LengthFrames=local_movie.MaxFrame; + info->RerecordCount=local_movie.RerecordCount; + info->Opts=local_movie.Opts; + info->ControllersMask=local_movie.ControllersMask; + + if(local_movie.SaveStateOffset > SMV_HEADER_SIZE) + { + uint8 meta_buf[MOVIE_MAX_METADATA * sizeof(uint16)]; + int i; + + metadata_length=((int)local_movie.SaveStateOffset-SMV_HEADER_SIZE)/sizeof(uint16); + metadata_length=(metadata_length>=MOVIE_MAX_METADATA) ? MOVIE_MAX_METADATA-1 : metadata_length; + metadata_length=(int)fread(meta_buf, sizeof(uint16), metadata_length, fd); + + for(i=0; iMetadata[i]=(wchar_t)c; + } + info->Metadata[i]='\0'; + } + else + { + info->Metadata[0]='\0'; + } + + fclose(fd); + + if(access(filename, W_OK)) + info->ReadOnly=true; + + return SUCCESS; +#endif +} + +bool8 S9xMovieActive () +{ + return (Movie.State!=MOVIE_STATE_NONE); +} + +bool8 S9xMovieReadOnly () +{ + if(!S9xMovieActive()) + return false; + + return Movie.ReadOnly; +} + +uint32 S9xMovieGetId () +{ + if(!S9xMovieActive()) + return 0; + + return Movie.MovieId; +} + +uint32 S9xMovieGetLength () +{ + if(!S9xMovieActive()) + return 0; + + return Movie.MaxFrame; +} + +uint32 S9xMovieGetFrameCounter () +{ + if(!S9xMovieActive()) + return 0; + + return Movie.CurrentFrame; +} + +void S9xMovieToggleFrameDisplay () +{ + Movie.FrameDisplay = !Movie.FrameDisplay; + if(!Movie.FrameDisplay) + { + GFX.InfoStringTimeout = 1; + } +} + +void S9xMovieFreeze (uint8** buf, uint32* size) +{ + // sanity check + if(!S9xMovieActive()) + { + return; + } + + *buf = NULL; + *size = 0; + + // compute size needed for the buffer + uint32 size_needed = 4*3; // room for MovieId, CurrentFrame, and MaxFrame + size_needed += (uint32)(Movie.BytesPerFrame * (Movie.MaxFrame+1)); + *buf=new uint8[size_needed]; + *size=size_needed; + + uint8* ptr = *buf; + if(!ptr) + { + return; + } + + Write32(Movie.MovieId, ptr); + Write32(Movie.CurrentFrame, ptr); + Write32(Movie.MaxFrame, ptr); + + memcpy(ptr, Movie.InputBuffer, Movie.BytesPerFrame * (Movie.MaxFrame+1)); +} + +bool8 S9xMovieUnfreeze (const uint8* buf, uint32 size) +{ + // sanity check + if(!S9xMovieActive()) + { + return false; + } + + const uint8* ptr = buf; + if(size < 4*3) + { + return false; + } + + uint32 movie_id = Read32(ptr); + uint32 current_frame = Read32(ptr); + uint32 max_frame = Read32(ptr); + uint32 space_needed = (Movie.BytesPerFrame * (max_frame+1)); + + if(movie_id != Movie.MovieId || + current_frame > max_frame || + space_needed > size) + { + return false; + } + + if(!Movie.ReadOnly) + { + // here, we are going to take the input data from the savestate + // and make it the input data for the current movie, then continue + // writing new input data at the currentframe pointer + change_state(MOVIE_STATE_RECORD); + S9xMessage(S9X_INFO, S9X_MOVIE_INFO, MOVIE_INFO_RERECORD); + + Movie.CurrentFrame = current_frame; + Movie.MaxFrame = max_frame; + ++Movie.RerecordCount; + + reserve_buffer_space(space_needed); + memcpy(Movie.InputBuffer, ptr, space_needed); + flush_movie(); + fseek(Movie.File, Movie.ControllerDataOffset+(Movie.BytesPerFrame * (Movie.CurrentFrame+1)), SEEK_SET); + } + else + { + // here, we are going to keep the input data from the movie file + // and simply rewind to the currentframe pointer + // this will cause a desync if the savestate is not in sync + // with the on-disk recording data, but it's easily solved + // by loading another savestate or playing the movie from the beginning + + // and older savestate might have a currentframe pointer past + // the end of the input data, so check for that here + if(current_frame > Movie.MaxFrame) + { + return false; + } + + change_state(MOVIE_STATE_PLAY); + S9xMessage(S9X_INFO, S9X_MOVIE_INFO, MOVIE_INFO_REWIND); + + Movie.CurrentFrame = current_frame; + } + + Movie.InputBufferPtr = Movie.InputBuffer + (Movie.BytesPerFrame * Movie.CurrentFrame); + read_frame_controller_data(); + + return true; +} diff --git a/src/movie.h b/src/movie.h new file mode 100644 index 0000000..3c5684e --- /dev/null +++ b/src/movie.h @@ -0,0 +1,146 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + Input recording/playback code + (c) Copyright 2004 blip + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#ifndef _MOVIE_H_ +#define _MOVIE_H_ + +#include +#include +#include "snes9x.h" + +#ifndef SUCCESS +# define SUCCESS 1 +# define WRONG_FORMAT (-1) +# define WRONG_VERSION (-2) +# define FILE_NOT_FOUND (-3) +#endif + +#define MOVIE_OPT_FROM_SNAPSHOT 0 +#define MOVIE_OPT_FROM_RESET (1<<0) +#define MOVIE_OPT_PAL (1<<1) +#define MOVIE_MAX_METADATA 512 + +START_EXTERN_C +struct MovieInfo +{ + time_t TimeCreated; + uint32 LengthFrames; + uint32 RerecordCount; + wchar_t Metadata[MOVIE_MAX_METADATA]; // really should be wchar_t + uint8 Opts; + uint8 ControllersMask; + bool8 ReadOnly; +}; + +// methods used by the user-interface code +int S9xMovieOpen (const char* filename, bool8 read_only); +int S9xMovieCreate (const char* filename, uint8 controllers_mask, uint8 opts, const wchar_t* metadata, int metadata_length); +int S9xMovieGetInfo (const char* filename, struct MovieInfo* info); +void S9xMovieStop (bool8 suppress_message); +void S9xMovieToggleFrameDisplay (); + +// methods used by the emulation +void S9xMovieInit (); +void S9xMovieUpdate (); +//bool8 S9xMovieRewind (uint32 at_frame); +void S9xMovieFreeze (uint8** buf, uint32* size); +bool8 S9xMovieUnfreeze (const uint8* buf, uint32 size); + +// accessor functions +bool8 S9xMovieActive (); +// the following accessors return 0/false if !S9xMovieActive() +bool8 S9xMovieReadOnly (); +uint32 S9xMovieGetId (); +uint32 S9xMovieGetLength (); +uint32 S9xMovieGetFrameCounter (); + +END_EXTERN_C + +#endif diff --git a/src/netplay.h b/src/netplay.h new file mode 100644 index 0000000..287da9c --- /dev/null +++ b/src/netplay.h @@ -0,0 +1,282 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ + +#ifndef _NETPLAY_H_ +#define _NETPLAY_H_ + +/* + * Client to server joypad update + * + * magic 1 + * sequence_no 1 + * opcode 1 + * joypad data 4 + * + * Server to client joypad update + * magic 1 + * sequence_no 1 + * opcode 1 + num joypads (top 3 bits) + * joypad data 4 * n + */ + +//#define NP_DEBUG 1 + +#define NP_VERSION 10 +#define NP_JOYPAD_HIST_SIZE 120 +#define NP_DEFAULT_PORT 6096 + +#define NP_MAX_CLIENTS 5 + +#define NP_SERV_MAGIC 'S' +#define NP_CLNT_MAGIC 'C' + +#define NP_CLNT_HELLO 0 +#define NP_CLNT_JOYPAD 1 +#define NP_CLNT_RESET 2 +#define NP_CLNT_PAUSE 3 +#define NP_CLNT_LOAD_ROM 4 +#define NP_CLNT_ROM_IMAGE 5 +#define NP_CLNT_FREEZE_FILE 6 +#define NP_CLNT_SRAM_DATA 7 +#define NP_CLNT_READY 8 +#define NP_CLNT_LOADED_ROM 9 +#define NP_CLNT_RECEIVED_ROM_IMAGE 10 +#define NP_CLNT_WAITING_FOR_ROM_IMAGE 11 + +#define NP_SERV_HELLO 0 +#define NP_SERV_JOYPAD 1 +#define NP_SERV_RESET 2 +#define NP_SERV_PAUSE 3 +#define NP_SERV_LOAD_ROM 4 +#define NP_SERV_ROM_IMAGE 5 +#define NP_SERV_FREEZE_FILE 6 +#define NP_SERV_SRAM_DATA 7 +#define NP_SERV_READY 8 + +struct SNPClient +{ + volatile uint8 SendSequenceNum; + volatile uint8 ReceiveSequenceNum; + volatile bool8 Connected; + volatile bool8 SaidHello; + volatile bool8 Paused; + volatile bool8 Ready; + int Socket; + char *ROMName; + char *HostName; + char *Who; +}; + +enum { + NP_SERVER_SEND_ROM_IMAGE, + NP_SERVER_SYNC_ALL, + NP_SERVER_SYNC_CLIENT, + NP_SERVER_SEND_FREEZE_FILE_ALL, + NP_SERVER_SEND_ROM_LOAD_REQUEST_ALL, + NP_SERVER_RESET_ALL, + NP_SERVER_SEND_SRAM_ALL, + NP_SERVER_SEND_SRAM +}; + +#define NP_MAX_TASKS 20 + +struct NPServerTask +{ + uint32 Task; + void *Data; +}; + +struct SNPServer +{ + struct SNPClient Clients [NP_MAX_CLIENTS]; + int NumClients; + volatile struct NPServerTask TaskQueue [NP_MAX_TASKS]; + volatile uint32 TaskHead; + volatile uint32 TaskTail; + int Socket; + uint32 FrameTime; + uint32 FrameCount; + char ROMName [30]; + uint32 Joypads [5]; + bool8 ClientPaused; + uint32 Paused; + bool8 SendROMImageOnConnect; + bool8 SyncByReset; +}; + +#define NP_MAX_ACTION_LEN 200 + +struct SNetPlay +{ + volatile uint8 MySequenceNum; + volatile uint8 ServerSequenceNum; + volatile bool8 Connected; + volatile bool8 Abort; + volatile uint8 Player; + volatile bool8 ClientsReady [NP_MAX_CLIENTS]; + volatile bool8 ClientsPaused [NP_MAX_CLIENTS]; + volatile bool8 Paused; + volatile bool8 PendingWait4Sync; + volatile uint8 PercentageComplete; + volatile bool8 Waiting4EmulationThread; + volatile bool8 Answer; + volatile int Socket; + char *ServerHostName; + char *ROMName; + int Port; + volatile uint32 JoypadWriteInd; + volatile uint32 JoypadReadInd; + uint32 Joypads [NP_JOYPAD_HIST_SIZE][NP_MAX_CLIENTS]; + uint32 Frame [NP_JOYPAD_HIST_SIZE]; + uint32 FrameCount; + uint32 MaxFrameSkip; + uint32 MaxBehindFrameCount; + char ActionMsg [NP_MAX_ACTION_LEN]; + char ErrorMsg [NP_MAX_ACTION_LEN]; + char WarningMsg [NP_MAX_ACTION_LEN]; +}; + +extern "C" struct SNetPlay NetPlay; + +// +// NETPLAY_CLIENT_HELLO message format: +// header +// frame_time (4) +// ROMName (variable) + +#define WRITE_LONG(p, v) { \ +*((p) + 0) = (uint8) ((v) >> 24); \ +*((p) + 1) = (uint8) ((v) >> 16); \ +*((p) + 2) = (uint8) ((v) >> 8); \ +*((p) + 3) = (uint8) ((v) >> 0); \ +} + +#define READ_LONG(p) \ +((((uint8) *((p) + 0)) << 24) | \ + (((uint8) *((p) + 1)) << 16) | \ + (((uint8) *((p) + 2)) << 8) | \ + (((uint8) *((p) + 3)) << 0)) + +bool8 S9xNPConnectToServer (const char *server_name, int port, + const char *rom_name); +bool8 S9xNPWaitForHeartBeat (); +uint32 S9xNPGetJoypad (int which1); +bool8 S9xNPSendJoypadUpdate (uint32 joypad); +void S9xNPDisconnect (); +bool8 S9xNPInitialise (); +bool8 S9xNPSendData (int fd, const uint8 *data, int len); +bool8 S9xNPGetData (int fd, uint8 *data, int len); + +void S9xNPSyncClients (); +void S9xNPStepJoypadHistory (); + +void S9xNPResetJoypadReadPos (); +bool8 S9xNPSendReady (uint8 op = NP_CLNT_READY); +bool8 S9xNPSendPause (bool8 pause); +void S9xNPReset (); +void S9xNPSetAction (const char *action, bool8 force = FALSE); +void S9xNPSetError (const char *error); +void S9xNPSetWarning (const char *warning); +void S9xNPDiscardHeartbeats (); +void S9xNPServerQueueSendingFreezeFile (const char *filename); +void S9xNPServerQueueSyncAll (); +void S9xNPServerQueueSendingROMImage (); +void S9xNPServerQueueSendingLoadROMRequest (const char *filename); + +void S9xNPServerAddTask (uint32 task, void *data); + +bool8 S9xNPStartServer (int port); +void S9xNPStopServer (); +#ifdef __WIN32kk__ +#define S9xGetMilliTime timeGetTime +#else +uint32 S9xGetMilliTime (); +#endif +#endif + diff --git a/src/newres.h b/src/newres.h new file mode 100644 index 0000000..ecda174 --- /dev/null +++ b/src/newres.h @@ -0,0 +1,41 @@ +#ifndef __NEWRES_H__ +#define __NEWRES_H__ + +#if !defined(UNDER_CE) +#define UNDER_CE _WIN32_WCE +#endif + +#if defined(_WIN32_WCE) + #if !defined(WCEOLE_ENABLE_DIALOGEX) + #define DIALOGEX DIALOG DISCARDABLE + #endif + #include + #define SHMENUBAR RCDATA + #if defined(WIN32_PLATFORM_PSPC) && (_WIN32_WCE >= 300) + #include + #define AFXCE_IDR_SCRATCH_SHMENU 28700 + #else + #define I_IMAGENONE (-2) + #define NOMENU 0xFFFF + #define IDS_SHNEW 1 + + #define IDM_SHAREDNEW 10 + #define IDM_SHAREDNEWDEFAULT 11 + #endif // _WIN32_WCE_PSPC + #define AFXCE_IDD_SAVEMODIFIEDDLG 28701 +#endif // _WIN32_WCE + +#ifdef RC_INVOKED +#ifndef _INC_WINDOWS +#define _INC_WINDOWS + #include "winuser.h" // extract from windows header + //#include "winver.h" +#endif +#endif + +#ifdef IDC_STATIC +#undef IDC_STATIC +#endif +#define IDC_STATIC (-1) + +#endif //__NEWRES_H__ diff --git a/src/notas b/src/notas new file mode 100644 index 0000000..c7a908b --- /dev/null +++ b/src/notas @@ -0,0 +1 @@ +echale un vistazo a S9xDoHBlankProcessing, está todavía en C++ diff --git a/src/os9x_65c816.s b/src/os9x_65c816.s new file mode 100644 index 0000000..1715510 --- /dev/null +++ b/src/os9x_65c816.s @@ -0,0 +1,4951 @@ + .DATA +/**************************************************************** +****************************************************************/ + .align 4 + .include "os9x_65c816_common.s" + + + @ notaz + .equiv ASM_SPC700, 1 ;@ 1 = use notaz's ASM_SPC700 core + + +.macro asmAPU_EXECUTE + LDR R0,[reg_cpu_var,#APUExecuting_ofs] + CMP R0,#1 @ spc700 enabled, hack mode off + BNE 43210f + LDR R0,[reg_cpu_var,#APU_Cycles] + SUBS R0,reg_cycles,R0 + BMI 43210f +.if ASM_SPC700 + PREPARE_C_CALL_LIGHTR12 + BL spc700_execute + RESTORE_C_CALL_LIGHTR12 + SUB R0,reg_cycles,R0 @ sub cycles left + STR R0,[reg_cpu_var,#APU_Cycles] +.else + @ SAVE_REGS + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] + PREPARE_C_CALL_LIGHTR12 + BL asm_APU_EXECUTE + RESTORE_C_CALL_LIGHTR12 + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] +.endif + @ LOAD_REGS + @ S9xFixCycles +43210: +.endm + +.macro asmAPU_EXECUTE2 +.if ASM_SPC700 + LDR R0,[reg_cpu_var,#APUExecuting_ofs] + CMP R0,#1 @ spc700 enabled, hack mode off + BNE 43211f + SUBS R0,reg_cycles,R0 @ reg_cycles == NextEvent + BLE 43211f + PREPARE_C_CALL_LIGHTR12 + BL spc700_execute + RESTORE_C_CALL_LIGHTR12 + SUB R0,reg_cycles,R0 @ sub cycles left + STR R0,[reg_cpu_var,#APU_Cycles] +43211: +.else + @ SAVE_REGS + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] + PREPARE_C_CALL_LIGHTR12 + BL asm_APU_EXECUTE2 + RESTORE_C_CALL_LIGHTR12 + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] + @ LOAD_REGS +.endif +.endm + + .include "os9x_65c816_opcodes.s" + + +/* + + +CLI_OPE_REC_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @treasuryDate, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @accountingDate, 103) + +CLI_OPE_Nos_Ope_Layer0 + n.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + n.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +CLI_OPE_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +Ecrans: +------ + + +[GNV] : utilisation de la lard (laccdate) pour afficher les openings. + +nécessité d'avoir des valeurs dans l'opening pour date tréso=date compta=laccdate + +[Accounting rec] : si laccdate pas bonne (pas = BD-1) -> message warning et pas de donnée +sinon : + +données nécessaires : opening date tréso=date compta=laccdate=BD-1 + +données nécessaires : opening date tréso=date compta=laccdate-1 + +données nécessaires : opening date tréso=laccdate-1 et date compta=laccdate + */ + + + +/**************************************************************** + GLOBAL +****************************************************************/ + .globl test_opcode + .globl asmMainLoop + + +@ void asmMainLoop(asm_cpu_var_t *asmcpuPtr); +asmMainLoop: + doMainLoop +.pool + +@ void test_opcode(struct asm_cpu_var *asm_var); +test_opcode: + doTestOpcode +.pool + +/***************************************************************** + ASM CODE +*****************************************************************/ + + +jumptable1: .long Op00mod1 + .long Op01M1mod1 + .long Op02mod1 + .long Op03M1mod1 + .long Op04M1mod1 + .long Op05M1mod1 + .long Op06M1mod1 + .long Op07M1mod1 + .long Op08mod1 + .long Op09M1mod1 + .long Op0AM1mod1 + .long Op0Bmod1 + .long Op0CM1mod1 + .long Op0DM1mod1 + .long Op0EM1mod1 + .long Op0FM1mod1 + .long Op10mod1 + .long Op11M1mod1 + .long Op12M1mod1 + .long Op13M1mod1 + .long Op14M1mod1 + .long Op15M1mod1 + .long Op16M1mod1 + .long Op17M1mod1 + .long Op18mod1 + .long Op19M1mod1 + .long Op1AM1mod1 + .long Op1Bmod1 + .long Op1CM1mod1 + .long Op1DM1mod1 + .long Op1EM1mod1 + .long Op1FM1mod1 + .long Op20mod1 + .long Op21M1mod1 + .long Op22mod1 + .long Op23M1mod1 + .long Op24M1mod1 + .long Op25M1mod1 + .long Op26M1mod1 + .long Op27M1mod1 + .long Op28mod1 + .long Op29M1mod1 + .long Op2AM1mod1 + .long Op2Bmod1 + .long Op2CM1mod1 + .long Op2DM1mod1 + .long Op2EM1mod1 + .long Op2FM1mod1 + .long Op30mod1 + .long Op31M1mod1 + .long Op32M1mod1 + .long Op33M1mod1 + .long Op34M1mod1 + .long Op35M1mod1 + .long Op36M1mod1 + .long Op37M1mod1 + .long Op38mod1 + .long Op39M1mod1 + .long Op3AM1mod1 + .long Op3Bmod1 + .long Op3CM1mod1 + .long Op3DM1mod1 + .long Op3EM1mod1 + .long Op3FM1mod1 + .long Op40mod1 + .long Op41M1mod1 + .long Op42mod1 + .long Op43M1mod1 + .long Op44X1mod1 + .long Op45M1mod1 + .long Op46M1mod1 + .long Op47M1mod1 + .long Op48M1mod1 + .long Op49M1mod1 + .long Op4AM1mod1 + .long Op4Bmod1 + .long Op4Cmod1 + .long Op4DM1mod1 + .long Op4EM1mod1 + .long Op4FM1mod1 + .long Op50mod1 + .long Op51M1mod1 + .long Op52M1mod1 + .long Op53M1mod1 + .long Op54X1mod1 + .long Op55M1mod1 + .long Op56M1mod1 + .long Op57M1mod1 + .long Op58mod1 + .long Op59M1mod1 + .long Op5AX1mod1 + .long Op5Bmod1 + .long Op5Cmod1 + .long Op5DM1mod1 + .long Op5EM1mod1 + .long Op5FM1mod1 + .long Op60mod1 + .long Op61M1mod1 + .long Op62mod1 + .long Op63M1mod1 + .long Op64M1mod1 + .long Op65M1mod1 + .long Op66M1mod1 + .long Op67M1mod1 + .long Op68M1mod1 + .long Op69M1mod1 + .long Op6AM1mod1 + .long Op6Bmod1 + .long Op6Cmod1 + .long Op6DM1mod1 + .long Op6EM1mod1 + .long Op6FM1mod1 + .long Op70mod1 + .long Op71M1mod1 + .long Op72M1mod1 + .long Op73M1mod1 + .long Op74M1mod1 + .long Op75M1mod1 + .long Op76M1mod1 + .long Op77M1mod1 + .long Op78mod1 + .long Op79M1mod1 + .long Op7AX1mod1 + .long Op7Bmod1 + .long Op7Cmod1 + .long Op7DM1mod1 + .long Op7EM1mod1 + .long Op7FM1mod1 + .long Op80mod1 + .long Op81M1mod1 + .long Op82mod1 + .long Op83M1mod1 + .long Op84X1mod1 + .long Op85M1mod1 + .long Op86X1mod1 + .long Op87M1mod1 + .long Op88X1mod1 + .long Op89M1mod1 + .long Op8AM1mod1 + .long Op8Bmod1 + .long Op8CX1mod1 + .long Op8DM1mod1 + .long Op8EX1mod1 + .long Op8FM1mod1 + .long Op90mod1 + .long Op91M1mod1 + .long Op92M1mod1 + .long Op93M1mod1 + .long Op94X1mod1 + .long Op95M1mod1 + .long Op96X1mod1 + .long Op97M1mod1 + .long Op98M1mod1 + .long Op99M1mod1 + .long Op9Amod1 + .long Op9BX1mod1 + + .long Op9CM1mod1 + .long Op9DM1mod1 + .long Op9EM1mod1 + .long Op9FM1mod1 + .long OpA0X1mod1 + .long OpA1M1mod1 + .long OpA2X1mod1 + .long OpA3M1mod1 + .long OpA4X1mod1 + .long OpA5M1mod1 + .long OpA6X1mod1 + .long OpA7M1mod1 + .long OpA8X1mod1 + .long OpA9M1mod1 + .long OpAAX1mod1 + .long OpABmod1 + .long OpACX1mod1 + .long OpADM1mod1 + .long OpAEX1mod1 + .long OpAFM1mod1 + .long OpB0mod1 + .long OpB1M1mod1 + .long OpB2M1mod1 + .long OpB3M1mod1 + .long OpB4X1mod1 + .long OpB5M1mod1 + .long OpB6X1mod1 + .long OpB7M1mod1 + .long OpB8mod1 + .long OpB9M1mod1 + .long OpBAX1mod1 + .long OpBBX1mod1 + .long OpBCX1mod1 + .long OpBDM1mod1 + .long OpBEX1mod1 + .long OpBFM1mod1 + .long OpC0X1mod1 + .long OpC1M1mod1 + .long OpC2mod1 + .long OpC3M1mod1 + .long OpC4X1mod1 + .long OpC5M1mod1 + .long OpC6M1mod1 + .long OpC7M1mod1 + .long OpC8X1mod1 + .long OpC9M1mod1 + .long OpCAX1mod1 + .long OpCBmod1 + .long OpCCX1mod1 + .long OpCDM1mod1 + .long OpCEM1mod1 + .long OpCFM1mod1 + .long OpD0mod1 + .long OpD1M1mod1 + .long OpD2M1mod1 + .long OpD3M1mod1 + .long OpD4mod1 + .long OpD5M1mod1 + .long OpD6M1mod1 + .long OpD7M1mod1 + .long OpD8mod1 + .long OpD9M1mod1 + .long OpDAX1mod1 + .long OpDBmod1 + .long OpDCmod1 + .long OpDDM1mod1 + .long OpDEM1mod1 + .long OpDFM1mod1 + .long OpE0X1mod1 + .long OpE1M1mod1 + .long OpE2mod1 + .long OpE3M1mod1 + .long OpE4X1mod1 + .long OpE5M1mod1 + .long OpE6M1mod1 + .long OpE7M1mod1 + .long OpE8X1mod1 + .long OpE9M1mod1 + .long OpEAmod1 + .long OpEBmod1 + .long OpECX1mod1 + .long OpEDM1mod1 + .long OpEEM1mod1 + .long OpEFM1mod1 + .long OpF0mod1 + .long OpF1M1mod1 + .long OpF2M1mod1 + .long OpF3M1mod1 + .long OpF4mod1 + .long OpF5M1mod1 + .long OpF6M1mod1 + .long OpF7M1mod1 + .long OpF8mod1 + .long OpF9M1mod1 + .long OpFAX1mod1 + .long OpFBmod1 + .long OpFCmod1 + .long OpFDM1mod1 + .long OpFEM1mod1 + .long OpFFM1mod1 + +Op00mod1: +lbl00mod1: Op00 + NEXTOPCODE +Op01M1mod1: +lbl01mod1a: DirectIndexedIndirect1 +lbl01mod1b: ORA8 + NEXTOPCODE +Op02mod1: +lbl02mod1: Op02 + NEXTOPCODE +Op03M1mod1: +lbl03mod1a: StackasmRelative +lbl03mod1b: ORA8 + NEXTOPCODE +Op04M1mod1: +lbl04mod1a: Direct +lbl04mod1b: TSB8 + NEXTOPCODE +Op05M1mod1: +lbl05mod1a: Direct +lbl05mod1b: ORA8 + NEXTOPCODE +Op06M1mod1: +lbl06mod1a: Direct +lbl06mod1b: ASL8 + NEXTOPCODE +Op07M1mod1: +lbl07mod1a: DirectIndirectLong +lbl07mod1b: ORA8 + NEXTOPCODE +Op08mod1: +lbl08mod1: Op08 + NEXTOPCODE +Op09M1mod1: +lbl09mod1: Op09M1 + NEXTOPCODE +Op0AM1mod1: +lbl0Amod1a: A_ASL8 + NEXTOPCODE +Op0Bmod1: +lbl0Bmod1: Op0B + NEXTOPCODE +Op0CM1mod1: +lbl0Cmod1a: Absolute +lbl0Cmod1b: TSB8 + NEXTOPCODE +Op0DM1mod1: +lbl0Dmod1a: Absolute +lbl0Dmod1b: ORA8 + NEXTOPCODE +Op0EM1mod1: +lbl0Emod1a: Absolute +lbl0Emod1b: ASL8 + NEXTOPCODE +Op0FM1mod1: +lbl0Fmod1a: AbsoluteLong +lbl0Fmod1b: ORA8 + NEXTOPCODE +Op10mod1: +lbl10mod1: Op10 + NEXTOPCODE +Op11M1mod1: +lbl11mod1a: DirectIndirectIndexed1 +lbl11mod1b: ORA8 + NEXTOPCODE +Op12M1mod1: +lbl12mod1a: DirectIndirect +lbl12mod1b: ORA8 + NEXTOPCODE +Op13M1mod1: + +lbl13mod1a: StackasmRelativeIndirectIndexed1 +lbl13mod1b: ORA8 + NEXTOPCODE +Op14M1mod1: +lbl14mod1a: Direct +lbl14mod1b: TRB8 + NEXTOPCODE +Op15M1mod1: +lbl15mod1a: DirectIndexedX1 +lbl15mod1b: ORA8 + NEXTOPCODE +Op16M1mod1: +lbl16mod1a: DirectIndexedX1 +lbl16mod1b: ASL8 + NEXTOPCODE +Op17M1mod1: +lbl17mod1a: DirectIndirectIndexedLong1 +lbl17mod1b: ORA8 + NEXTOPCODE +Op18mod1: +lbl18mod1: Op18 + NEXTOPCODE +Op19M1mod1: +lbl19mod1a: AbsoluteIndexedY1 +lbl19mod1b: ORA8 + NEXTOPCODE +Op1AM1mod1: +lbl1Amod1a: A_INC8 + NEXTOPCODE +Op1Bmod1: +lbl1Bmod1: Op1BM1 + NEXTOPCODE +Op1CM1mod1: +lbl1Cmod1a: Absolute +lbl1Cmod1b: TRB8 + NEXTOPCODE +Op1DM1mod1: +lbl1Dmod1a: AbsoluteIndexedX1 +lbl1Dmod1b: ORA8 + NEXTOPCODE +Op1EM1mod1: +lbl1Emod1a: AbsoluteIndexedX1 +lbl1Emod1b: ASL8 + NEXTOPCODE +Op1FM1mod1: +lbl1Fmod1a: AbsoluteLongIndexedX1 +lbl1Fmod1b: ORA8 + NEXTOPCODE +Op20mod1: +lbl20mod1: Op20 + NEXTOPCODE +Op21M1mod1: +lbl21mod1a: DirectIndexedIndirect1 +lbl21mod1b: AND8 + NEXTOPCODE +Op22mod1: +lbl22mod1: Op22 + NEXTOPCODE +Op23M1mod1: +lbl23mod1a: StackasmRelative +lbl23mod1b: AND8 + NEXTOPCODE +Op24M1mod1: +lbl24mod1a: Direct +lbl24mod1b: BIT8 + NEXTOPCODE +Op25M1mod1: +lbl25mod1a: Direct +lbl25mod1b: AND8 + NEXTOPCODE +Op26M1mod1: +lbl26mod1a: Direct +lbl26mod1b: ROL8 + NEXTOPCODE +Op27M1mod1: +lbl27mod1a: DirectIndirectLong +lbl27mod1b: AND8 + NEXTOPCODE +Op28mod1: +lbl28mod1: Op28X1M1 + NEXTOPCODE +.pool +Op29M1mod1: +lbl29mod1: Op29M1 + NEXTOPCODE +Op2AM1mod1: +lbl2Amod1a: A_ROL8 + NEXTOPCODE +Op2Bmod1: +lbl2Bmod1: Op2B + NEXTOPCODE +Op2CM1mod1: +lbl2Cmod1a: Absolute +lbl2Cmod1b: BIT8 + NEXTOPCODE +Op2DM1mod1: +lbl2Dmod1a: Absolute +lbl2Dmod1b: AND8 + NEXTOPCODE +Op2EM1mod1: +lbl2Emod1a: Absolute +lbl2Emod1b: ROL8 + NEXTOPCODE +Op2FM1mod1: +lbl2Fmod1a: AbsoluteLong +lbl2Fmod1b: AND8 + NEXTOPCODE +Op30mod1: +lbl30mod1: Op30 + NEXTOPCODE +Op31M1mod1: +lbl31mod1a: DirectIndirectIndexed1 +lbl31mod1b: AND8 + NEXTOPCODE +Op32M1mod1: +lbl32mod1a: DirectIndirect +lbl32mod1b: AND8 + NEXTOPCODE +Op33M1mod1: +lbl33mod1a: StackasmRelativeIndirectIndexed1 +lbl33mod1b: AND8 + NEXTOPCODE +Op34M1mod1: +lbl34mod1a: DirectIndexedX1 +lbl34mod1b: BIT8 + NEXTOPCODE +Op35M1mod1: +lbl35mod1a: DirectIndexedX1 +lbl35mod1b: AND8 + NEXTOPCODE +Op36M1mod1: +lbl36mod1a: DirectIndexedX1 +lbl36mod1b: ROL8 + NEXTOPCODE +Op37M1mod1: +lbl37mod1a: DirectIndirectIndexedLong1 +lbl37mod1b: AND8 + NEXTOPCODE +Op38mod1: +lbl38mod1: Op38 + NEXTOPCODE +Op39M1mod1: +lbl39mod1a: AbsoluteIndexedY1 +lbl39mod1b: AND8 + NEXTOPCODE +Op3AM1mod1: +lbl3Amod1a: A_DEC8 + NEXTOPCODE +Op3Bmod1: +lbl3Bmod1: Op3BM1 + NEXTOPCODE +Op3CM1mod1: +lbl3Cmod1a: AbsoluteIndexedX1 +lbl3Cmod1b: BIT8 + NEXTOPCODE +Op3DM1mod1: +lbl3Dmod1a: AbsoluteIndexedX1 +lbl3Dmod1b: AND8 + NEXTOPCODE +Op3EM1mod1: +lbl3Emod1a: AbsoluteIndexedX1 +lbl3Emod1b: ROL8 + NEXTOPCODE +Op3FM1mod1: +lbl3Fmod1a: AbsoluteLongIndexedX1 +lbl3Fmod1b: AND8 + NEXTOPCODE +Op40mod1: +lbl40mod1: Op40X1M1 + NEXTOPCODE +.pool +Op41M1mod1: +lbl41mod1a: DirectIndexedIndirect1 +lbl41mod1b: EOR8 + NEXTOPCODE +Op42mod1: +lbl42mod1: Op42 + NEXTOPCODE +Op43M1mod1: +lbl43mod1a: StackasmRelative +lbl43mod1b: EOR8 + NEXTOPCODE +Op44X1mod1: +lbl44mod1: Op44X1M1 + NEXTOPCODE +Op45M1mod1: +lbl45mod1a: Direct +lbl45mod1b: EOR8 + NEXTOPCODE +Op46M1mod1: +lbl46mod1a: Direct +lbl46mod1b: LSR8 + NEXTOPCODE +Op47M1mod1: +lbl47mod1a: DirectIndirectLong +lbl47mod1b: EOR8 + NEXTOPCODE +Op48M1mod1: +lbl48mod1: Op48M1 + NEXTOPCODE +Op49M1mod1: +lbl49mod1: Op49M1 + NEXTOPCODE +Op4AM1mod1: +lbl4Amod1a: A_LSR8 + NEXTOPCODE +Op4Bmod1: +lbl4Bmod1: Op4B + NEXTOPCODE +Op4Cmod1: +lbl4Cmod1: Op4C + NEXTOPCODE +Op4DM1mod1: +lbl4Dmod1a: Absolute +lbl4Dmod1b: EOR8 + NEXTOPCODE +Op4EM1mod1: +lbl4Emod1a: Absolute +lbl4Emod1b: LSR8 + NEXTOPCODE +Op4FM1mod1: +lbl4Fmod1a: AbsoluteLong +lbl4Fmod1b: EOR8 + NEXTOPCODE +Op50mod1: +lbl50mod1: Op50 + NEXTOPCODE +Op51M1mod1: +lbl51mod1a: DirectIndirectIndexed1 +lbl51mod1b: EOR8 + NEXTOPCODE +Op52M1mod1: +lbl52mod1a: DirectIndirect +lbl52mod1b: EOR8 + NEXTOPCODE +Op53M1mod1: +lbl53mod1a: StackasmRelativeIndirectIndexed1 +lbl53mod1b: EOR8 + NEXTOPCODE +Op54X1mod1: +lbl54mod1: Op54X1M1 + NEXTOPCODE +Op55M1mod1: +lbl55mod1a: DirectIndexedX1 +lbl55mod1b: EOR8 + NEXTOPCODE +Op56M1mod1: +lbl56mod1a: DirectIndexedX1 +lbl56mod1b: LSR8 + NEXTOPCODE +Op57M1mod1: +lbl57mod1a: DirectIndirectIndexedLong1 +lbl57mod1b: EOR8 + NEXTOPCODE +Op58mod1: +lbl58mod1: Op58 + NEXTOPCODE +Op59M1mod1: +lbl59mod1a: AbsoluteIndexedY1 +lbl59mod1b: EOR8 + NEXTOPCODE +Op5AX1mod1: +lbl5Amod1: Op5AX1 + NEXTOPCODE +Op5Bmod1: +lbl5Bmod1: Op5BM1 + NEXTOPCODE +Op5Cmod1: +lbl5Cmod1: Op5C + NEXTOPCODE +Op5DM1mod1: +lbl5Dmod1a: AbsoluteIndexedX1 +lbl5Dmod1b: EOR8 + NEXTOPCODE +Op5EM1mod1: +lbl5Emod1a: AbsoluteIndexedX1 +lbl5Emod1b: LSR8 + NEXTOPCODE +Op5FM1mod1: +lbl5Fmod1a: AbsoluteLongIndexedX1 +lbl5Fmod1b: EOR8 + NEXTOPCODE +Op60mod1: +lbl60mod1: Op60 + NEXTOPCODE +Op61M1mod1: +lbl61mod1a: DirectIndexedIndirect1 +lbl61mod1b: ADC8 + NEXTOPCODE +Op62mod1: +lbl62mod1: Op62 + NEXTOPCODE +Op63M1mod1: +lbl63mod1a: StackasmRelative +lbl63mod1b: ADC8 + NEXTOPCODE +Op64M1mod1: +lbl64mod1a: Direct +lbl64mod1b: STZ8 + NEXTOPCODE +Op65M1mod1: +lbl65mod1a: Direct +lbl65mod1b: ADC8 + NEXTOPCODE +Op66M1mod1: +lbl66mod1a: Direct +lbl66mod1b: ROR8 + NEXTOPCODE +Op67M1mod1: +lbl67mod1a: DirectIndirectLong +lbl67mod1b: ADC8 + + NEXTOPCODE + +Op68M1mod1: +lbl68mod1: Op68M1 + NEXTOPCODE +Op69M1mod1: +lbl69mod1a: Immediate8 +lbl69mod1b: ADC8 + NEXTOPCODE +Op6AM1mod1: +lbl6Amod1a: A_ROR8 + NEXTOPCODE +Op6Bmod1: +lbl6Bmod1: Op6B + NEXTOPCODE +Op6Cmod1: +lbl6Cmod1: Op6C + NEXTOPCODE +Op6DM1mod1: +lbl6Dmod1a: Absolute +lbl6Dmod1b: ADC8 + NEXTOPCODE +Op6EM1mod1: + + +lbl6Emod1a: Absolute +lbl6Emod1b: ROR8 + NEXTOPCODE +Op6FM1mod1: +lbl6Fmod1a: AbsoluteLong +lbl6Fmod1b: ADC8 + NEXTOPCODE +Op70mod1: +lbl70mod1: Op70 + NEXTOPCODE +Op71M1mod1: +lbl71mod1a: DirectIndirectIndexed1 +lbl71mod1b: ADC8 + NEXTOPCODE +Op72M1mod1: +lbl72mod1a: DirectIndirect +lbl72mod1b: ADC8 + NEXTOPCODE +Op73M1mod1: +lbl73mod1a: StackasmRelativeIndirectIndexed1 +lbl73mod1b: ADC8 + NEXTOPCODE + +Op74M1mod1: +lbl74mod1a: DirectIndexedX1 +lbl74mod1b: STZ8 + NEXTOPCODE +Op75M1mod1: +lbl75mod1a: DirectIndexedX1 +lbl75mod1b: ADC8 + NEXTOPCODE +Op76M1mod1: +lbl76mod1a: DirectIndexedX1 +lbl76mod1b: ROR8 + NEXTOPCODE +Op77M1mod1: +lbl77mod1a: DirectIndirectIndexedLong1 +lbl77mod1b: ADC8 + NEXTOPCODE +Op78mod1: +lbl78mod1: Op78 + NEXTOPCODE +Op79M1mod1: +lbl79mod1a: AbsoluteIndexedY1 +lbl79mod1b: ADC8 + NEXTOPCODE +Op7AX1mod1: +lbl7Amod1: Op7AX1 + NEXTOPCODE +Op7Bmod1: +lbl7Bmod1: Op7BM1 + NEXTOPCODE +Op7Cmod1: +lbl7Cmod1: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE +Op7DM1mod1: +lbl7Dmod1a: AbsoluteIndexedX1 +lbl7Dmod1b: ADC8 + NEXTOPCODE +Op7EM1mod1: +lbl7Emod1a: AbsoluteIndexedX1 +lbl7Emod1b: ROR8 + NEXTOPCODE +Op7FM1mod1: +lbl7Fmod1a: AbsoluteLongIndexedX1 +lbl7Fmod1b: ADC8 + NEXTOPCODE + + +Op80mod1: +lbl80mod1: Op80 + NEXTOPCODE +Op81M1mod1: +lbl81mod1a: DirectIndexedIndirect1 +lbl81mod1b: Op81M1 + NEXTOPCODE +Op82mod1: +lbl82mod1: Op82 + NEXTOPCODE +Op83M1mod1: +lbl83mod1a: StackasmRelative +lbl83mod1b: STA8 + NEXTOPCODE +Op84X1mod1: +lbl84mod1a: Direct +lbl84mod1b: STY8 + NEXTOPCODE +Op85M1mod1: +lbl85mod1a: Direct +lbl85mod1b: STA8 + NEXTOPCODE +Op86X1mod1: +lbl86mod1a: Direct +lbl86mod1b: STX8 + NEXTOPCODE +Op87M1mod1: +lbl87mod1a: DirectIndirectLong +lbl87mod1b: STA8 + NEXTOPCODE +Op88X1mod1: +lbl88mod1: Op88X1 + NEXTOPCODE +Op89M1mod1: +lbl89mod1: Op89M1 + NEXTOPCODE +Op8AM1mod1: +lbl8Amod1: Op8AM1X1 + NEXTOPCODE +Op8Bmod1: +lbl8Bmod1: Op8B + NEXTOPCODE +Op8CX1mod1: +lbl8Cmod1a: Absolute +lbl8Cmod1b: STY8 + NEXTOPCODE +Op8DM1mod1: +lbl8Dmod1a: Absolute +lbl8Dmod1b: STA8 + NEXTOPCODE +Op8EX1mod1: +lbl8Emod1a: Absolute +lbl8Emod1b: STX8 + NEXTOPCODE +Op8FM1mod1: +lbl8Fmod1a: AbsoluteLong +lbl8Fmod1b: STA8 + NEXTOPCODE +Op90mod1: +lbl90mod1: Op90 + NEXTOPCODE +Op91M1mod1: +lbl91mod1a: DirectIndirectIndexed1 +lbl91mod1b: STA8 + NEXTOPCODE +Op92M1mod1: +lbl92mod1a: DirectIndirect +lbl92mod1b: STA8 + NEXTOPCODE +Op93M1mod1: +lbl93mod1a: StackasmRelativeIndirectIndexed1 +lbl93mod1b: STA8 + NEXTOPCODE +Op94X1mod1: +lbl94mod1a: DirectIndexedX1 +lbl94mod1b: STY8 + NEXTOPCODE +Op95M1mod1: +lbl95mod1a: DirectIndexedX1 +lbl95mod1b: STA8 + NEXTOPCODE +Op96X1mod1: +lbl96mod1a: DirectIndexedY1 +lbl96mod1b: STX8 + NEXTOPCODE +Op97M1mod1: +lbl97mod1a: DirectIndirectIndexedLong1 +lbl97mod1b: STA8 + NEXTOPCODE +Op98M1mod1: +lbl98mod1: Op98M1X1 + NEXTOPCODE +Op99M1mod1: +lbl99mod1a: AbsoluteIndexedY1 +lbl99mod1b: STA8 + NEXTOPCODE +Op9Amod1: +lbl9Amod1: Op9AX1 + NEXTOPCODE +Op9BX1mod1: +lbl9Bmod1: Op9BX1 + NEXTOPCODE +Op9CM1mod1: +lbl9Cmod1a: Absolute +lbl9Cmod1b: STZ8 + NEXTOPCODE +Op9DM1mod1: +lbl9Dmod1a: AbsoluteIndexedX1 +lbl9Dmod1b: STA8 + NEXTOPCODE +Op9EM1mod1: +lbl9Emod1: AbsoluteIndexedX1 + STZ8 + NEXTOPCODE +Op9FM1mod1: +lbl9Fmod1a: AbsoluteLongIndexedX1 +lbl9Fmod1b: STA8 + NEXTOPCODE +OpA0X1mod1: +lblA0mod1: OpA0X1 + NEXTOPCODE +OpA1M1mod1: +lblA1mod1a: DirectIndexedIndirect1 +lblA1mod1b: LDA8 + NEXTOPCODE +OpA2X1mod1: +lblA2mod1: OpA2X1 + NEXTOPCODE +OpA3M1mod1: +lblA3mod1a: StackasmRelative +lblA3mod1b: LDA8 + NEXTOPCODE +OpA4X1mod1: +lblA4mod1a: Direct +lblA4mod1b: LDY8 + NEXTOPCODE +OpA5M1mod1: +lblA5mod1a: Direct +lblA5mod1b: LDA8 + NEXTOPCODE +OpA6X1mod1: +lblA6mod1a: Direct +lblA6mod1b: LDX8 + NEXTOPCODE +OpA7M1mod1: +lblA7mod1a: DirectIndirectLong +lblA7mod1b: LDA8 + NEXTOPCODE +OpA8X1mod1: +lblA8mod1: OpA8X1M1 + NEXTOPCODE +OpA9M1mod1: +lblA9mod1: OpA9M1 + NEXTOPCODE +OpAAX1mod1: +lblAAmod1: OpAAX1M1 + NEXTOPCODE +OpABmod1: +lblABmod1: OpAB + NEXTOPCODE +OpACX1mod1: +lblACmod1a: Absolute +lblACmod1b: LDY8 + NEXTOPCODE +OpADM1mod1: +lblADmod1a: Absolute +lblADmod1b: LDA8 + NEXTOPCODE +OpAEX1mod1: +lblAEmod1a: Absolute +lblAEmod1b: LDX8 + NEXTOPCODE +OpAFM1mod1: +lblAFmod1a: AbsoluteLong +lblAFmod1b: LDA8 + NEXTOPCODE +OpB0mod1: +lblB0mod1: OpB0 + NEXTOPCODE +OpB1M1mod1: +lblB1mod1a: DirectIndirectIndexed1 +lblB1mod1b: LDA8 + NEXTOPCODE +OpB2M1mod1: +lblB2mod1a: DirectIndirect +lblB2mod1b: LDA8 + NEXTOPCODE +OpB3M1mod1: +lblB3mod1a: StackasmRelativeIndirectIndexed1 +lblB3mod1b: LDA8 + NEXTOPCODE +OpB4X1mod1: +lblB4mod1a: DirectIndexedX1 +lblB4mod1b: LDY8 + NEXTOPCODE +OpB5M1mod1: +lblB5mod1a: DirectIndexedX1 +lblB5mod1b: LDA8 + NEXTOPCODE +OpB6X1mod1: +lblB6mod1a: DirectIndexedY1 +lblB6mod1b: LDX8 + NEXTOPCODE +OpB7M1mod1: +lblB7mod1a: DirectIndirectIndexedLong1 +lblB7mod1b: LDA8 + NEXTOPCODE +OpB8mod1: +lblB8mod1: OpB8 + NEXTOPCODE +OpB9M1mod1: +lblB9mod1a: AbsoluteIndexedY1 +lblB9mod1b: LDA8 + NEXTOPCODE +OpBAX1mod1: +lblBAmod1: OpBAX1 + NEXTOPCODE +OpBBX1mod1: +lblBBmod1: OpBBX1 + NEXTOPCODE +OpBCX1mod1: +lblBCmod1a: AbsoluteIndexedX1 +lblBCmod1b: LDY8 + NEXTOPCODE +OpBDM1mod1: +lblBDmod1a: AbsoluteIndexedX1 +lblBDmod1b: LDA8 + NEXTOPCODE +OpBEX1mod1: +lblBEmod1a: AbsoluteIndexedY1 +lblBEmod1b: LDX8 + NEXTOPCODE +OpBFM1mod1: +lblBFmod1a: AbsoluteLongIndexedX1 +lblBFmod1b: LDA8 + NEXTOPCODE +OpC0X1mod1: +lblC0mod1: OpC0X1 + NEXTOPCODE +OpC1M1mod1: +lblC1mod1a: DirectIndexedIndirect1 +lblC1mod1b: CMP8 + NEXTOPCODE +OpC2mod1: +lblC2mod1: OpC2 + NEXTOPCODE +.pool +OpC3M1mod1: +lblC3mod1a: StackasmRelative +lblC3mod1b: CMP8 + NEXTOPCODE +OpC4X1mod1: +lblC4mod1a: Direct +lblC4mod1b: CMY8 + NEXTOPCODE +OpC5M1mod1: +lblC5mod1a: Direct +lblC5mod1b: CMP8 + NEXTOPCODE +OpC6M1mod1: +lblC6mod1a: Direct +lblC6mod1b: DEC8 + NEXTOPCODE +OpC7M1mod1: +lblC7mod1a: DirectIndirectLong +lblC7mod1b: CMP8 + NEXTOPCODE +OpC8X1mod1: +lblC8mod1: OpC8X1 + NEXTOPCODE +OpC9M1mod1: +lblC9mod1: OpC9M1 + NEXTOPCODE +OpCAX1mod1: +lblCAmod1: OpCAX1 + NEXTOPCODE +OpCBmod1: +lblCBmod1: OpCB + NEXTOPCODE +OpCCX1mod1: +lblCCmod1a: Absolute +lblCCmod1b: CMY8 + NEXTOPCODE +OpCDM1mod1: +lblCDmod1a: Absolute +lblCDmod1b: CMP8 + NEXTOPCODE +OpCEM1mod1: +lblCEmod1a: Absolute +lblCEmod1b: DEC8 + NEXTOPCODE +OpCFM1mod1: +lblCFmod1a: AbsoluteLong +lblCFmod1b: CMP8 + NEXTOPCODE +OpD0mod1: +lblD0mod1: OpD0 + NEXTOPCODE +OpD1M1mod1: +lblD1mod1a: DirectIndirectIndexed1 +lblD1mod1b: CMP8 + NEXTOPCODE +OpD2M1mod1: +lblD2mod1a: DirectIndirect +lblD2mod1b: CMP8 + NEXTOPCODE +OpD3M1mod1: +lblD3mod1a: StackasmRelativeIndirectIndexed1 +lblD3mod1b: CMP8 + + NEXTOPCODE +OpD4mod1: +lblD4mod1: OpD4 + NEXTOPCODE +OpD5M1mod1: +lblD5mod1a: DirectIndexedX1 +lblD5mod1b: CMP8 + NEXTOPCODE +OpD6M1mod1: +lblD6mod1a: DirectIndexedX1 +lblD6mod1b: DEC8 + NEXTOPCODE +OpD7M1mod1: +lblD7mod1a: DirectIndirectIndexedLong1 +lblD7mod1b: CMP8 + NEXTOPCODE +OpD8mod1: +lblD8mod1: OpD8 + NEXTOPCODE +OpD9M1mod1: +lblD9mod1a: AbsoluteIndexedY1 +lblD9mod1b: CMP8 + NEXTOPCODE +OpDAX1mod1: +lblDAmod1: OpDAX1 + NEXTOPCODE +OpDBmod1: +lblDBmod1: OpDB + NEXTOPCODE +OpDCmod1: +lblDCmod1: OpDC + NEXTOPCODE +OpDDM1mod1: +lblDDmod1a: AbsoluteIndexedX1 +lblDDmod1b: CMP8 + NEXTOPCODE +OpDEM1mod1: +lblDEmod1a: AbsoluteIndexedX1 +lblDEmod1b: DEC8 + NEXTOPCODE +OpDFM1mod1: +lblDFmod1a: AbsoluteLongIndexedX1 +lblDFmod1b: CMP8 + NEXTOPCODE +OpE0X1mod1: +lblE0mod1: OpE0X1 + NEXTOPCODE +OpE1M1mod1: +lblE1mod1a: DirectIndexedIndirect1 +lblE1mod1b: SBC8 + NEXTOPCODE +OpE2mod1: +lblE2mod1: OpE2 + NEXTOPCODE +.pool +OpE3M1mod1: +lblE3mod1a: StackasmRelative +lblE3mod1b: SBC8 + NEXTOPCODE +OpE4X1mod1: +lblE4mod1a: Direct +lblE4mod1b: CMX8 + NEXTOPCODE +OpE5M1mod1: +lblE5mod1a: Direct +lblE5mod1b: SBC8 + NEXTOPCODE +OpE6M1mod1: +lblE6mod1a: Direct +lblE6mod1b: INC8 + NEXTOPCODE +OpE7M1mod1: +lblE7mod1a: DirectIndirectLong +lblE7mod1b: SBC8 + NEXTOPCODE +OpE8X1mod1: +lblE8mod1: OpE8X1 + NEXTOPCODE +OpE9M1mod1: +lblE9mod1a: Immediate8 +lblE9mod1b: SBC8 + NEXTOPCODE +OpEAmod1: +lblEAmod1: OpEA + NEXTOPCODE +OpEBmod1: +lblEBmod1: OpEBM1 + NEXTOPCODE +OpECX1mod1: +lblECmod1a: Absolute +lblECmod1b: CMX8 + NEXTOPCODE +OpEDM1mod1: +lblEDmod1a: Absolute +lblEDmod1b: SBC8 + NEXTOPCODE +OpEEM1mod1: +lblEEmod1a: Absolute +lblEEmod1b: INC8 + NEXTOPCODE +OpEFM1mod1: +lblEFmod1a: AbsoluteLong +lblEFmod1b: SBC8 + NEXTOPCODE +OpF0mod1: +lblF0mod1: OpF0 + NEXTOPCODE +OpF1M1mod1: +lblF1mod1a: DirectIndirectIndexed1 +lblF1mod1b: SBC8 + NEXTOPCODE +OpF2M1mod1: +lblF2mod1a: DirectIndirect +lblF2mod1b: SBC8 + NEXTOPCODE +OpF3M1mod1: +lblF3mod1a: StackasmRelativeIndirectIndexed1 +lblF3mod1b: SBC8 + NEXTOPCODE +OpF4mod1: +lblF4mod1: OpF4 + NEXTOPCODE +OpF5M1mod1: +lblF5mod1a: DirectIndexedX1 +lblF5mod1b: SBC8 + NEXTOPCODE +OpF6M1mod1: +lblF6mod1a: DirectIndexedX1 +lblF6mod1b: INC8 + NEXTOPCODE +OpF7M1mod1: +lblF7mod1a: DirectIndirectIndexedLong1 +lblF7mod1b: SBC8 + NEXTOPCODE +OpF8mod1: +lblF8mod1: OpF8 + NEXTOPCODE +OpF9M1mod1: +lblF9mod1a: AbsoluteIndexedY1 +lblF9mod1b: SBC8 + NEXTOPCODE +OpFAX1mod1: +lblFAmod1: OpFAX1 + NEXTOPCODE +OpFBmod1: +lblFBmod1: OpFB + NEXTOPCODE +OpFCmod1: +lblFCmod1: OpFCX1 + NEXTOPCODE +OpFDM1mod1: +lblFDmod1a: AbsoluteIndexedX1 +lblFDmod1b: SBC8 + NEXTOPCODE +OpFEM1mod1: +lblFEmod1a: AbsoluteIndexedX1 +lblFEmod1b: INC8 + NEXTOPCODE +OpFFM1mod1: +lblFFmod1a: AbsoluteLongIndexedX1 +lblFFmod1b: SBC8 + NEXTOPCODE +.pool + + +jumptable2: .long Op00mod2 + .long Op01M1mod2 + .long Op02mod2 + .long Op03M1mod2 + .long Op04M1mod2 + .long Op05M1mod2 + .long Op06M1mod2 + .long Op07M1mod2 + .long Op08mod2 + .long Op09M1mod2 + .long Op0AM1mod2 + .long Op0Bmod2 + .long Op0CM1mod2 + .long Op0DM1mod2 + .long Op0EM1mod2 + .long Op0FM1mod2 + .long Op10mod2 + .long Op11M1mod2 + .long Op12M1mod2 + .long Op13M1mod2 + .long Op14M1mod2 + .long Op15M1mod2 + .long Op16M1mod2 + .long Op17M1mod2 + .long Op18mod2 + .long Op19M1mod2 + .long Op1AM1mod2 + .long Op1Bmod2 + .long Op1CM1mod2 + .long Op1DM1mod2 + .long Op1EM1mod2 + .long Op1FM1mod2 + .long Op20mod2 + .long Op21M1mod2 + .long Op22mod2 + .long Op23M1mod2 + .long Op24M1mod2 + .long Op25M1mod2 + .long Op26M1mod2 + .long Op27M1mod2 + .long Op28mod2 + .long Op29M1mod2 + .long Op2AM1mod2 + .long Op2Bmod2 + .long Op2CM1mod2 + .long Op2DM1mod2 + .long Op2EM1mod2 + .long Op2FM1mod2 + .long Op30mod2 + .long Op31M1mod2 + .long Op32M1mod2 + .long Op33M1mod2 + .long Op34M1mod2 + .long Op35M1mod2 + .long Op36M1mod2 + .long Op37M1mod2 + .long Op38mod2 + .long Op39M1mod2 + .long Op3AM1mod2 + .long Op3Bmod2 + .long Op3CM1mod2 + .long Op3DM1mod2 + .long Op3EM1mod2 + .long Op3FM1mod2 + .long Op40mod2 + .long Op41M1mod2 + .long Op42mod2 + .long Op43M1mod2 + .long Op44X0mod2 + .long Op45M1mod2 + .long Op46M1mod2 + .long Op47M1mod2 + .long Op48M1mod2 + .long Op49M1mod2 + .long Op4AM1mod2 + .long Op4Bmod2 + .long Op4Cmod2 + .long Op4DM1mod2 + .long Op4EM1mod2 + .long Op4FM1mod2 + .long Op50mod2 + .long Op51M1mod2 + .long Op52M1mod2 + .long Op53M1mod2 + .long Op54X0mod2 + .long Op55M1mod2 + .long Op56M1mod2 + .long Op57M1mod2 + .long Op58mod2 + .long Op59M1mod2 + .long Op5AX0mod2 + .long Op5Bmod2 + .long Op5Cmod2 + .long Op5DM1mod2 + .long Op5EM1mod2 + .long Op5FM1mod2 + .long Op60mod2 + .long Op61M1mod2 + .long Op62mod2 + .long Op63M1mod2 + .long Op64M1mod2 + .long Op65M1mod2 + .long Op66M1mod2 + .long Op67M1mod2 + .long Op68M1mod2 + .long Op69M1mod2 + .long Op6AM1mod2 + .long Op6Bmod2 + .long Op6Cmod2 + .long Op6DM1mod2 + .long Op6EM1mod2 + .long Op6FM1mod2 + .long Op70mod2 + .long Op71M1mod2 + .long Op72M1mod2 + .long Op73M1mod2 + .long Op74M1mod2 + .long Op75M1mod2 + .long Op76M1mod2 + .long Op77M1mod2 + .long Op78mod2 + .long Op79M1mod2 + .long Op7AX0mod2 + .long Op7Bmod2 + .long Op7Cmod2 + .long Op7DM1mod2 + .long Op7EM1mod2 + .long Op7FM1mod2 + .long Op80mod2 + .long Op81M1mod2 + .long Op82mod2 + .long Op83M1mod2 + .long Op84X0mod2 + .long Op85M1mod2 + .long Op86X0mod2 + .long Op87M1mod2 + .long Op88X0mod2 + .long Op89M1mod2 + .long Op8AM1mod2 + .long Op8Bmod2 + .long Op8CX0mod2 + .long Op8DM1mod2 + .long Op8EX0mod2 + .long Op8FM1mod2 + .long Op90mod2 + .long Op91M1mod2 + .long Op92M1mod2 + .long Op93M1mod2 + .long Op94X0mod2 + .long Op95M1mod2 + .long Op96X0mod2 + .long Op97M1mod2 + .long Op98M1mod2 + .long Op99M1mod2 + .long Op9Amod2 + .long Op9BX0mod2 + .long Op9CM1mod2 + .long Op9DM1mod2 + .long Op9EM1mod2 + .long Op9FM1mod2 + .long OpA0X0mod2 + .long OpA1M1mod2 + .long OpA2X0mod2 + .long OpA3M1mod2 + .long OpA4X0mod2 + .long OpA5M1mod2 + .long OpA6X0mod2 + .long OpA7M1mod2 + .long OpA8X0mod2 + .long OpA9M1mod2 + .long OpAAX0mod2 + .long OpABmod2 + .long OpACX0mod2 + .long OpADM1mod2 + .long OpAEX0mod2 + .long OpAFM1mod2 + .long OpB0mod2 + .long OpB1M1mod2 + .long OpB2M1mod2 + .long OpB3M1mod2 + .long OpB4X0mod2 + .long OpB5M1mod2 + .long OpB6X0mod2 + .long OpB7M1mod2 + .long OpB8mod2 + .long OpB9M1mod2 + .long OpBAX0mod2 + .long OpBBX0mod2 + .long OpBCX0mod2 + .long OpBDM1mod2 + .long OpBEX0mod2 + .long OpBFM1mod2 + .long OpC0X0mod2 + .long OpC1M1mod2 + .long OpC2mod2 + .long OpC3M1mod2 + .long OpC4X0mod2 + .long OpC5M1mod2 + .long OpC6M1mod2 + .long OpC7M1mod2 + .long OpC8X0mod2 + .long OpC9M1mod2 + .long OpCAX0mod2 + .long OpCBmod2 + .long OpCCX0mod2 + .long OpCDM1mod2 + .long OpCEM1mod2 + .long OpCFM1mod2 + .long OpD0mod2 + .long OpD1M1mod2 + .long OpD2M1mod2 + .long OpD3M1mod2 + .long OpD4mod2 + .long OpD5M1mod2 + .long OpD6M1mod2 + .long OpD7M1mod2 + .long OpD8mod2 + .long OpD9M1mod2 + .long OpDAX0mod2 + .long OpDBmod2 + .long OpDCmod2 + .long OpDDM1mod2 + .long OpDEM1mod2 + .long OpDFM1mod2 + .long OpE0X0mod2 + .long OpE1M1mod2 + .long OpE2mod2 + .long OpE3M1mod2 + .long OpE4X0mod2 + .long OpE5M1mod2 + .long OpE6M1mod2 + .long OpE7M1mod2 + .long OpE8X0mod2 + .long OpE9M1mod2 + .long OpEAmod2 + .long OpEBmod2 + .long OpECX0mod2 + .long OpEDM1mod2 + .long OpEEM1mod2 + .long OpEFM1mod2 + .long OpF0mod2 + .long OpF1M1mod2 + .long OpF2M1mod2 + .long OpF3M1mod2 + .long OpF4mod2 + .long OpF5M1mod2 + .long OpF6M1mod2 + .long OpF7M1mod2 + .long OpF8mod2 + .long OpF9M1mod2 + .long OpFAX0mod2 + .long OpFBmod2 + .long OpFCmod2 + .long OpFDM1mod2 + .long OpFEM1mod2 + .long OpFFM1mod2 +Op00mod2: +lbl00mod2: Op00 + NEXTOPCODE +Op01M1mod2: +lbl01mod2a: DirectIndexedIndirect0 +lbl01mod2b: ORA8 + NEXTOPCODE +Op02mod2: +lbl02mod2: Op02 + NEXTOPCODE +Op03M1mod2: +lbl03mod2a: StackasmRelative +lbl03mod2b: ORA8 + NEXTOPCODE +Op04M1mod2: +lbl04mod2a: Direct +lbl04mod2b: TSB8 + NEXTOPCODE +Op05M1mod2: +lbl05mod2a: Direct +lbl05mod2b: ORA8 + NEXTOPCODE +Op06M1mod2: +lbl06mod2a: Direct +lbl06mod2b: ASL8 + NEXTOPCODE +Op07M1mod2: +lbl07mod2a: DirectIndirectLong +lbl07mod2b: ORA8 + NEXTOPCODE +Op08mod2: + +lbl08mod2: Op08 + NEXTOPCODE +Op09M1mod2: +lbl09mod2: Op09M1 + NEXTOPCODE +Op0AM1mod2: +lbl0Amod2a: A_ASL8 + NEXTOPCODE +Op0Bmod2: +lbl0Bmod2: Op0B + NEXTOPCODE +Op0CM1mod2: +lbl0Cmod2a: Absolute +lbl0Cmod2b: TSB8 + NEXTOPCODE +Op0DM1mod2: +lbl0Dmod2a: Absolute +lbl0Dmod2b: ORA8 + NEXTOPCODE +Op0EM1mod2: +lbl0Emod2a: Absolute +lbl0Emod2b: ASL8 + NEXTOPCODE +Op0FM1mod2: +lbl0Fmod2a: AbsoluteLong +lbl0Fmod2b: ORA8 + NEXTOPCODE +Op10mod2: +lbl10mod2: Op10 + NEXTOPCODE +Op11M1mod2: +lbl11mod2a: DirectIndirectIndexed0 +lbl11mod2b: ORA8 + NEXTOPCODE +Op12M1mod2: +lbl12mod2a: DirectIndirect +lbl12mod2b: ORA8 + NEXTOPCODE +Op13M1mod2: +lbl13mod2a: StackasmRelativeIndirectIndexed0 +lbl13mod2b: ORA8 + NEXTOPCODE +Op14M1mod2: +lbl14mod2a: Direct +lbl14mod2b: TRB8 + NEXTOPCODE +Op15M1mod2: +lbl15mod2a: DirectIndexedX0 +lbl15mod2b: ORA8 + NEXTOPCODE +Op16M1mod2: +lbl16mod2a: DirectIndexedX0 +lbl16mod2b: ASL8 + NEXTOPCODE +Op17M1mod2: +lbl17mod2a: DirectIndirectIndexedLong0 +lbl17mod2b: ORA8 + NEXTOPCODE +Op18mod2: +lbl18mod2: Op18 + NEXTOPCODE +Op19M1mod2: +lbl19mod2a: AbsoluteIndexedY0 +lbl19mod2b: ORA8 + NEXTOPCODE +Op1AM1mod2: +lbl1Amod2a: A_INC8 + NEXTOPCODE +Op1Bmod2: +lbl1Bmod2: Op1BM1 + NEXTOPCODE +Op1CM1mod2: +lbl1Cmod2a: Absolute +lbl1Cmod2b: TRB8 + NEXTOPCODE +Op1DM1mod2: +lbl1Dmod2a: AbsoluteIndexedX0 +lbl1Dmod2b: ORA8 + NEXTOPCODE +Op1EM1mod2: +lbl1Emod2a: AbsoluteIndexedX0 +lbl1Emod2b: ASL8 + NEXTOPCODE +Op1FM1mod2: +lbl1Fmod2a: AbsoluteLongIndexedX0 +lbl1Fmod2b: ORA8 + NEXTOPCODE +Op20mod2: +lbl20mod2: Op20 + NEXTOPCODE +Op21M1mod2: +lbl21mod2a: DirectIndexedIndirect0 +lbl21mod2b: AND8 + NEXTOPCODE +Op22mod2: +lbl22mod2: Op22 + NEXTOPCODE +Op23M1mod2: +lbl23mod2a: StackasmRelative +lbl23mod2b: AND8 + NEXTOPCODE +Op24M1mod2: +lbl24mod2a: Direct +lbl24mod2b: BIT8 + NEXTOPCODE +Op25M1mod2: +lbl25mod2a: Direct +lbl25mod2b: AND8 + NEXTOPCODE +Op26M1mod2: +lbl26mod2a: Direct +lbl26mod2b: ROL8 + NEXTOPCODE +Op27M1mod2: +lbl27mod2a: DirectIndirectLong +lbl27mod2b: AND8 + NEXTOPCODE +Op28mod2: +lbl28mod2: Op28X0M1 + NEXTOPCODE +.pool +Op29M1mod2: +lbl29mod2: Op29M1 + NEXTOPCODE +Op2AM1mod2: +lbl2Amod2a: A_ROL8 + NEXTOPCODE +Op2Bmod2: +lbl2Bmod2: Op2B + NEXTOPCODE +Op2CM1mod2: +lbl2Cmod2a: Absolute +lbl2Cmod2b: BIT8 + NEXTOPCODE +Op2DM1mod2: +lbl2Dmod2a: Absolute +lbl2Dmod2b: AND8 + NEXTOPCODE +Op2EM1mod2: +lbl2Emod2a: Absolute +lbl2Emod2b: ROL8 + NEXTOPCODE +Op2FM1mod2: +lbl2Fmod2a: AbsoluteLong +lbl2Fmod2b: AND8 + NEXTOPCODE +Op30mod2: +lbl30mod2: Op30 + NEXTOPCODE +Op31M1mod2: +lbl31mod2a: DirectIndirectIndexed0 +lbl31mod2b: AND8 + NEXTOPCODE +Op32M1mod2: +lbl32mod2a: DirectIndirect +lbl32mod2b: AND8 + NEXTOPCODE +Op33M1mod2: +lbl33mod2a: StackasmRelativeIndirectIndexed0 +lbl33mod2b: AND8 + NEXTOPCODE +Op34M1mod2: +lbl34mod2a: DirectIndexedX0 +lbl34mod2b: BIT8 + NEXTOPCODE +Op35M1mod2: +lbl35mod2a: DirectIndexedX0 +lbl35mod2b: AND8 + NEXTOPCODE +Op36M1mod2: +lbl36mod2a: DirectIndexedX0 +lbl36mod2b: ROL8 + NEXTOPCODE +Op37M1mod2: +lbl37mod2a: DirectIndirectIndexedLong0 +lbl37mod2b: AND8 + NEXTOPCODE +Op38mod2: +lbl38mod2: Op38 + NEXTOPCODE +Op39M1mod2: +lbl39mod2a: AbsoluteIndexedY0 +lbl39mod2b: AND8 + NEXTOPCODE +Op3AM1mod2: +lbl3Amod2a: A_DEC8 + NEXTOPCODE +Op3Bmod2: +lbl3Bmod2: Op3BM1 + NEXTOPCODE +Op3CM1mod2: +lbl3Cmod2a: AbsoluteIndexedX0 +lbl3Cmod2b: BIT8 + NEXTOPCODE +Op3DM1mod2: +lbl3Dmod2a: AbsoluteIndexedX0 +lbl3Dmod2b: AND8 + NEXTOPCODE +Op3EM1mod2: +lbl3Emod2a: AbsoluteIndexedX0 +lbl3Emod2b: ROL8 + NEXTOPCODE +Op3FM1mod2: +lbl3Fmod2a: AbsoluteLongIndexedX0 +lbl3Fmod2b: AND8 + NEXTOPCODE +Op40mod2: +lbl40mod2: Op40X0M1 + NEXTOPCODE +.pool +Op41M1mod2: +lbl41mod2a: DirectIndexedIndirect0 +lbl41mod2b: EOR8 + NEXTOPCODE +Op42mod2: +lbl42mod2: Op42 + NEXTOPCODE +Op43M1mod2: +lbl43mod2a: StackasmRelative +lbl43mod2b: EOR8 + NEXTOPCODE +Op44X0mod2: +lbl44mod2: Op44X0M1 + NEXTOPCODE +Op45M1mod2: +lbl45mod2a: Direct +lbl45mod2b: EOR8 + NEXTOPCODE +Op46M1mod2: +lbl46mod2a: Direct +lbl46mod2b: LSR8 + NEXTOPCODE +Op47M1mod2: +lbl47mod2a: DirectIndirectLong +lbl47mod2b: EOR8 + NEXTOPCODE +Op48M1mod2: +lbl48mod2: Op48M1 + NEXTOPCODE +Op49M1mod2: +lbl49mod2: Op49M1 + NEXTOPCODE +Op4AM1mod2: +lbl4Amod2a: A_LSR8 + NEXTOPCODE +Op4Bmod2: +lbl4Bmod2: Op4B + NEXTOPCODE +Op4Cmod2: +lbl4Cmod2: Op4C + NEXTOPCODE +Op4DM1mod2: +lbl4Dmod2a: Absolute +lbl4Dmod2b: EOR8 + NEXTOPCODE +Op4EM1mod2: +lbl4Emod2a: Absolute +lbl4Emod2b: LSR8 + NEXTOPCODE +Op4FM1mod2: +lbl4Fmod2a: AbsoluteLong +lbl4Fmod2b: EOR8 + NEXTOPCODE +Op50mod2: +lbl50mod2: Op50 + NEXTOPCODE +Op51M1mod2: +lbl51mod2a: DirectIndirectIndexed0 +lbl51mod2b: EOR8 + NEXTOPCODE +Op52M1mod2: +lbl52mod2a: DirectIndirect +lbl52mod2b: EOR8 + NEXTOPCODE +Op53M1mod2: +lbl53mod2a: StackasmRelativeIndirectIndexed0 +lbl53mod2b: EOR8 + NEXTOPCODE +Op54X0mod2: +lbl54mod2: Op54X0M1 + NEXTOPCODE +Op55M1mod2: +lbl55mod2a: DirectIndexedX0 +lbl55mod2b: EOR8 + NEXTOPCODE +Op56M1mod2: +lbl56mod2a: DirectIndexedX0 +lbl56mod2b: LSR8 + NEXTOPCODE +Op57M1mod2: +lbl57mod2a: DirectIndirectIndexedLong0 +lbl57mod2b: EOR8 + NEXTOPCODE +Op58mod2: +lbl58mod2: Op58 + NEXTOPCODE +Op59M1mod2: +lbl59mod2a: AbsoluteIndexedY0 +lbl59mod2b: EOR8 + NEXTOPCODE +Op5AX0mod2: +lbl5Amod2: Op5AX0 + NEXTOPCODE +Op5Bmod2: +lbl5Bmod2: Op5BM1 + NEXTOPCODE +Op5Cmod2: +lbl5Cmod2: Op5C + NEXTOPCODE +Op5DM1mod2: +lbl5Dmod2a: AbsoluteIndexedX0 +lbl5Dmod2b: EOR8 + NEXTOPCODE +Op5EM1mod2: +lbl5Emod2a: AbsoluteIndexedX0 +lbl5Emod2b: LSR8 + NEXTOPCODE +Op5FM1mod2: +lbl5Fmod2a: AbsoluteLongIndexedX0 +lbl5Fmod2b: EOR8 + NEXTOPCODE +Op60mod2: +lbl60mod2: Op60 + NEXTOPCODE +Op61M1mod2: +lbl61mod2a: DirectIndexedIndirect0 +lbl61mod2b: ADC8 + NEXTOPCODE +Op62mod2: +lbl62mod2: Op62 + NEXTOPCODE +Op63M1mod2: +lbl63mod2a: StackasmRelative +lbl63mod2b: ADC8 + NEXTOPCODE +Op64M1mod2: +lbl64mod2a: Direct +lbl64mod2b: STZ8 + NEXTOPCODE +Op65M1mod2: +lbl65mod2a: Direct +lbl65mod2b: ADC8 + NEXTOPCODE +Op66M1mod2: +lbl66mod2a: Direct +lbl66mod2b: ROR8 + NEXTOPCODE +Op67M1mod2: +lbl67mod2a: DirectIndirectLong +lbl67mod2b: ADC8 + NEXTOPCODE +Op68M1mod2: +lbl68mod2: Op68M1 + NEXTOPCODE +Op69M1mod2: +lbl69mod2a: Immediate8 +lbl69mod2b: ADC8 + NEXTOPCODE +Op6AM1mod2: +lbl6Amod2a: A_ROR8 + NEXTOPCODE +Op6Bmod2: +lbl6Bmod2: Op6B + NEXTOPCODE +Op6Cmod2: +lbl6Cmod2: Op6C + NEXTOPCODE +Op6DM1mod2: +lbl6Dmod2a: Absolute +lbl6Dmod2b: ADC8 + NEXTOPCODE +Op6EM1mod2: +lbl6Emod2a: Absolute +lbl6Emod2b: ROR8 + NEXTOPCODE +Op6FM1mod2: +lbl6Fmod2a: AbsoluteLong +lbl6Fmod2b: ADC8 + NEXTOPCODE +Op70mod2: +lbl70mod2: Op70 + NEXTOPCODE +Op71M1mod2: +lbl71mod2a: DirectIndirectIndexed0 +lbl71mod2b: ADC8 + NEXTOPCODE +Op72M1mod2: +lbl72mod2a: DirectIndirect +lbl72mod2b: ADC8 + NEXTOPCODE +Op73M1mod2: +lbl73mod2a: StackasmRelativeIndirectIndexed0 +lbl73mod2b: ADC8 + NEXTOPCODE +Op74M1mod2: +lbl74mod2a: DirectIndexedX0 +lbl74mod2b: STZ8 + NEXTOPCODE +Op75M1mod2: +lbl75mod2a: DirectIndexedX0 +lbl75mod2b: ADC8 + NEXTOPCODE +Op76M1mod2: +lbl76mod2a: DirectIndexedX0 +lbl76mod2b: ROR8 + NEXTOPCODE +Op77M1mod2: +lbl77mod2a: DirectIndirectIndexedLong0 +lbl77mod2b: ADC8 + NEXTOPCODE +Op78mod2: +lbl78mod2: Op78 + NEXTOPCODE +Op79M1mod2: +lbl79mod2a: AbsoluteIndexedY0 +lbl79mod2b: ADC8 + NEXTOPCODE +Op7AX0mod2: +lbl7Amod2: Op7AX0 + NEXTOPCODE +Op7Bmod2: +lbl7Bmod2: Op7BM1 + NEXTOPCODE +Op7Cmod2: +lbl7Cmod2: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE +Op7DM1mod2: +lbl7Dmod2a: AbsoluteIndexedX0 +lbl7Dmod2b: ADC8 + NEXTOPCODE +Op7EM1mod2: +lbl7Emod2a: AbsoluteIndexedX0 +lbl7Emod2b: ROR8 + NEXTOPCODE +Op7FM1mod2: +lbl7Fmod2a: AbsoluteLongIndexedX0 +lbl7Fmod2b: ADC8 + NEXTOPCODE + + +Op80mod2: +lbl80mod2: Op80 + NEXTOPCODE +Op81M1mod2: +lbl81mod2a: DirectIndexedIndirect0 +lbl81mod2b: Op81M1 + NEXTOPCODE +Op82mod2: +lbl82mod2: Op82 + NEXTOPCODE +Op83M1mod2: +lbl83mod2a: StackasmRelative +lbl83mod2b: STA8 + NEXTOPCODE +Op84X0mod2: +lbl84mod2a: Direct +lbl84mod2b: STY16 + NEXTOPCODE +Op85M1mod2: +lbl85mod2a: Direct +lbl85mod2b: STA8 + NEXTOPCODE +Op86X0mod2: +lbl86mod2a: Direct +lbl86mod2b: STX16 + NEXTOPCODE +Op87M1mod2: +lbl87mod2a: DirectIndirectLong +lbl87mod2b: STA8 + NEXTOPCODE +Op88X0mod2: +lbl88mod2: Op88X0 + NEXTOPCODE +Op89M1mod2: +lbl89mod2: Op89M1 + NEXTOPCODE +Op8AM1mod2: +lbl8Amod2: Op8AM1X0 + NEXTOPCODE +Op8Bmod2: +lbl8Bmod2: Op8B + NEXTOPCODE +Op8CX0mod2: +lbl8Cmod2a: Absolute +lbl8Cmod2b: STY16 + NEXTOPCODE +Op8DM1mod2: +lbl8Dmod2a: Absolute +lbl8Dmod2b: STA8 + NEXTOPCODE +Op8EX0mod2: +lbl8Emod2a: Absolute +lbl8Emod2b: STX16 + NEXTOPCODE +Op8FM1mod2: +lbl8Fmod2a: AbsoluteLong +lbl8Fmod2b: STA8 + NEXTOPCODE +Op90mod2: +lbl90mod2: Op90 + NEXTOPCODE +Op91M1mod2: +lbl91mod2a: DirectIndirectIndexed0 +lbl91mod2b: STA8 + NEXTOPCODE +Op92M1mod2: +lbl92mod2a: DirectIndirect +lbl92mod2b: STA8 + NEXTOPCODE +Op93M1mod2: +lbl93mod2a: StackasmRelativeIndirectIndexed0 +lbl93mod2b: STA8 + NEXTOPCODE +Op94X0mod2: +lbl94mod2a: DirectIndexedX0 +lbl94mod2b: STY16 + NEXTOPCODE +Op95M1mod2: + +lbl95mod2a: DirectIndexedX0 +lbl95mod2b: STA8 + NEXTOPCODE +Op96X0mod2: +lbl96mod2a: DirectIndexedY0 +lbl96mod2b: STX16 + NEXTOPCODE +Op97M1mod2: +lbl97mod2a: DirectIndirectIndexedLong0 +lbl97mod2b: STA8 + NEXTOPCODE +Op98M1mod2: +lbl98mod2: Op98M1X0 + NEXTOPCODE +Op99M1mod2: +lbl99mod2a: AbsoluteIndexedY0 +lbl99mod2b: STA8 + NEXTOPCODE +Op9Amod2: +lbl9Amod2: Op9AX0 + NEXTOPCODE +Op9BX0mod2: +lbl9Bmod2: Op9BX0 + NEXTOPCODE +Op9CM1mod2: +lbl9Cmod2a: Absolute +lbl9Cmod2b: STZ8 + NEXTOPCODE +Op9DM1mod2: +lbl9Dmod2a: AbsoluteIndexedX0 +lbl9Dmod2b: STA8 + NEXTOPCODE +Op9EM1mod2: +lbl9Emod2: AbsoluteIndexedX0 + STZ8 + NEXTOPCODE +Op9FM1mod2: +lbl9Fmod2a: AbsoluteLongIndexedX0 +lbl9Fmod2b: STA8 + NEXTOPCODE +OpA0X0mod2: +lblA0mod2: OpA0X0 + NEXTOPCODE +OpA1M1mod2: +lblA1mod2a: DirectIndexedIndirect0 +lblA1mod2b: LDA8 + NEXTOPCODE +OpA2X0mod2: +lblA2mod2: OpA2X0 + NEXTOPCODE +OpA3M1mod2: +lblA3mod2a: StackasmRelative +lblA3mod2b: LDA8 + NEXTOPCODE +OpA4X0mod2: +lblA4mod2a: Direct +lblA4mod2b: LDY16 + NEXTOPCODE +OpA5M1mod2: +lblA5mod2a: Direct +lblA5mod2b: LDA8 + NEXTOPCODE +OpA6X0mod2: +lblA6mod2a: Direct +lblA6mod2b: LDX16 + NEXTOPCODE +OpA7M1mod2: +lblA7mod2a: DirectIndirectLong +lblA7mod2b: LDA8 + NEXTOPCODE +OpA8X0mod2: +lblA8mod2: OpA8X0M1 + NEXTOPCODE +OpA9M1mod2: +lblA9mod2: OpA9M1 + NEXTOPCODE +OpAAX0mod2: +lblAAmod2: OpAAX0M1 + NEXTOPCODE +OpABmod2: +lblABmod2: OpAB + NEXTOPCODE +OpACX0mod2: +lblACmod2a: Absolute +lblACmod2b: LDY16 + NEXTOPCODE +OpADM1mod2: +lblADmod2a: Absolute +lblADmod2b: LDA8 + NEXTOPCODE +OpAEX0mod2: +lblAEmod2a: Absolute +lblAEmod2b: LDX16 + NEXTOPCODE +OpAFM1mod2: +lblAFmod2a: AbsoluteLong +lblAFmod2b: LDA8 + NEXTOPCODE +OpB0mod2: +lblB0mod2: OpB0 + NEXTOPCODE +OpB1M1mod2: +lblB1mod2a: DirectIndirectIndexed0 +lblB1mod2b: LDA8 + NEXTOPCODE +OpB2M1mod2: +lblB2mod2a: DirectIndirect +lblB2mod2b: LDA8 + NEXTOPCODE +OpB3M1mod2: +lblB3mod2a: StackasmRelativeIndirectIndexed0 +lblB3mod2b: LDA8 + NEXTOPCODE +OpB4X0mod2: +lblB4mod2a: DirectIndexedX0 +lblB4mod2b: LDY16 + NEXTOPCODE +OpB5M1mod2: +lblB5mod2a: DirectIndexedX0 +lblB5mod2b: LDA8 + NEXTOPCODE +OpB6X0mod2: +lblB6mod2a: DirectIndexedY0 +lblB6mod2b: LDX16 + NEXTOPCODE +OpB7M1mod2: +lblB7mod2a: DirectIndirectIndexedLong0 +lblB7mod2b: LDA8 + NEXTOPCODE +OpB8mod2: +lblB8mod2: OpB8 + NEXTOPCODE +OpB9M1mod2: +lblB9mod2a: AbsoluteIndexedY0 +lblB9mod2b: LDA8 + NEXTOPCODE +OpBAX0mod2: +lblBAmod2: OpBAX0 + NEXTOPCODE +OpBBX0mod2: +lblBBmod2: OpBBX0 + NEXTOPCODE +OpBCX0mod2: +lblBCmod2a: AbsoluteIndexedX0 +lblBCmod2b: LDY16 + NEXTOPCODE +OpBDM1mod2: +lblBDmod2a: AbsoluteIndexedX0 +lblBDmod2b: LDA8 + NEXTOPCODE +OpBEX0mod2: +lblBEmod2a: AbsoluteIndexedY0 +lblBEmod2b: LDX16 + NEXTOPCODE +OpBFM1mod2: +lblBFmod2a: AbsoluteLongIndexedX0 +lblBFmod2b: LDA8 + NEXTOPCODE +OpC0X0mod2: +lblC0mod2: OpC0X0 + NEXTOPCODE +OpC1M1mod2: +lblC1mod2a: DirectIndexedIndirect0 +lblC1mod2b: CMP8 + NEXTOPCODE +OpC2mod2: +lblC2mod2: OpC2 + NEXTOPCODE +.pool +OpC3M1mod2: +lblC3mod2a: StackasmRelative +lblC3mod2b: CMP8 + NEXTOPCODE +OpC4X0mod2: +lblC4mod2a: Direct +lblC4mod2b: CMY16 + NEXTOPCODE +OpC5M1mod2: +lblC5mod2a: Direct +lblC5mod2b: CMP8 + NEXTOPCODE +OpC6M1mod2: +lblC6mod2a: Direct +lblC6mod2b: DEC8 + NEXTOPCODE +OpC7M1mod2: +lblC7mod2a: DirectIndirectLong +lblC7mod2b: CMP8 + NEXTOPCODE +OpC8X0mod2: +lblC8mod2: OpC8X0 + NEXTOPCODE +OpC9M1mod2: +lblC9mod2: OpC9M1 + NEXTOPCODE +OpCAX0mod2: +lblCAmod2: OpCAX0 + NEXTOPCODE +OpCBmod2: +lblCBmod2: OpCB + NEXTOPCODE +OpCCX0mod2: +lblCCmod2a: Absolute +lblCCmod2b: CMY16 + NEXTOPCODE +OpCDM1mod2: +lblCDmod2a: Absolute +lblCDmod2b: CMP8 + NEXTOPCODE +OpCEM1mod2: +lblCEmod2a: Absolute +lblCEmod2b: DEC8 + NEXTOPCODE +OpCFM1mod2: +lblCFmod2a: AbsoluteLong +lblCFmod2b: CMP8 + NEXTOPCODE +OpD0mod2: +lblD0mod2: OpD0 + NEXTOPCODE +OpD1M1mod2: +lblD1mod2a: DirectIndirectIndexed0 +lblD1mod2b: CMP8 + NEXTOPCODE +OpD2M1mod2: +lblD2mod2a: DirectIndirect +lblD2mod2b: CMP8 + NEXTOPCODE +OpD3M1mod2: +lblD3mod2a: StackasmRelativeIndirectIndexed0 +lblD3mod2b: CMP8 + NEXTOPCODE +OpD4mod2: +lblD4mod2: OpD4 + NEXTOPCODE +OpD5M1mod2: +lblD5mod2a: DirectIndexedX0 +lblD5mod2b: CMP8 + NEXTOPCODE +OpD6M1mod2: +lblD6mod2a: DirectIndexedX0 +lblD6mod2b: DEC8 + NEXTOPCODE +OpD7M1mod2: +lblD7mod2a: DirectIndirectIndexedLong0 +lblD7mod2b: CMP8 + NEXTOPCODE +OpD8mod2: +lblD8mod2: OpD8 + NEXTOPCODE +OpD9M1mod2: +lblD9mod2a: AbsoluteIndexedY0 +lblD9mod2b: CMP8 + NEXTOPCODE +OpDAX0mod2: +lblDAmod2: OpDAX0 + NEXTOPCODE +OpDBmod2: +lblDBmod2: OpDB + NEXTOPCODE +OpDCmod2: +lblDCmod2: OpDC + NEXTOPCODE +OpDDM1mod2: +lblDDmod2a: AbsoluteIndexedX0 +lblDDmod2b: CMP8 + NEXTOPCODE +OpDEM1mod2: +lblDEmod2a: AbsoluteIndexedX0 +lblDEmod2b: DEC8 + NEXTOPCODE +OpDFM1mod2: +lblDFmod2a: AbsoluteLongIndexedX0 +lblDFmod2b: CMP8 + NEXTOPCODE +OpE0X0mod2: +lblE0mod2: OpE0X0 + NEXTOPCODE +OpE1M1mod2: +lblE1mod2a: DirectIndexedIndirect0 +lblE1mod2b: SBC8 + NEXTOPCODE +OpE2mod2: +lblE2mod2: OpE2 + NEXTOPCODE +.pool +OpE3M1mod2: +lblE3mod2a: StackasmRelative +lblE3mod2b: SBC8 + NEXTOPCODE +OpE4X0mod2: +lblE4mod2a: Direct +lblE4mod2b: CMX16 + NEXTOPCODE +OpE5M1mod2: +lblE5mod2a: Direct +lblE5mod2b: SBC8 + NEXTOPCODE +OpE6M1mod2: +lblE6mod2a: Direct +lblE6mod2b: INC8 + NEXTOPCODE +OpE7M1mod2: +lblE7mod2a: DirectIndirectLong +lblE7mod2b: SBC8 + NEXTOPCODE +OpE8X0mod2: +lblE8mod2: OpE8X0 + NEXTOPCODE +OpE9M1mod2: +lblE9mod2a: Immediate8 +lblE9mod2b: SBC8 + NEXTOPCODE +OpEAmod2: +lblEAmod2: OpEA + NEXTOPCODE +OpEBmod2: +lblEBmod2: OpEBM1 + NEXTOPCODE +OpECX0mod2: +lblECmod2a: Absolute +lblECmod2b: CMX16 + NEXTOPCODE +OpEDM1mod2: +lblEDmod2a: Absolute +lblEDmod2b: SBC8 + NEXTOPCODE +OpEEM1mod2: +lblEEmod2a: Absolute +lblEEmod2b: INC8 + NEXTOPCODE +OpEFM1mod2: +lblEFmod2a: AbsoluteLong +lblEFmod2b: SBC8 + NEXTOPCODE +OpF0mod2: +lblF0mod2: OpF0 + NEXTOPCODE +OpF1M1mod2: +lblF1mod2a: DirectIndirectIndexed0 +lblF1mod2b: SBC8 + NEXTOPCODE +OpF2M1mod2: +lblF2mod2a: DirectIndirect +lblF2mod2b: SBC8 + NEXTOPCODE +OpF3M1mod2: +lblF3mod2a: StackasmRelativeIndirectIndexed0 +lblF3mod2b: SBC8 + NEXTOPCODE +OpF4mod2: +lblF4mod2: OpF4 + NEXTOPCODE +OpF5M1mod2: +lblF5mod2a: DirectIndexedX0 +lblF5mod2b: SBC8 + NEXTOPCODE +OpF6M1mod2: +lblF6mod2a: DirectIndexedX0 +lblF6mod2b: INC8 + NEXTOPCODE +OpF7M1mod2: +lblF7mod2a: DirectIndirectIndexedLong0 +lblF7mod2b: SBC8 + NEXTOPCODE +OpF8mod2: +lblF8mod2: OpF8 + NEXTOPCODE +OpF9M1mod2: +lblF9mod2a: AbsoluteIndexedY0 +lblF9mod2b: SBC8 + NEXTOPCODE +OpFAX0mod2: +lblFAmod2: OpFAX0 + NEXTOPCODE +OpFBmod2: +lblFBmod2: OpFB + NEXTOPCODE +OpFCmod2: +lblFCmod2: OpFCX0 + NEXTOPCODE +OpFDM1mod2: +lblFDmod2a: AbsoluteIndexedX0 +lblFDmod2b: SBC8 + NEXTOPCODE +OpFEM1mod2: +lblFEmod2a: AbsoluteIndexedX0 +lblFEmod2b: INC8 + NEXTOPCODE +OpFFM1mod2: +lblFFmod2a: AbsoluteLongIndexedX0 +lblFFmod2b: SBC8 + NEXTOPCODE + +.pool + + +jumptable3: .long Op00mod3 + .long Op01M0mod3 + .long Op02mod3 + .long Op03M0mod3 + .long Op04M0mod3 + .long Op05M0mod3 + .long Op06M0mod3 + .long Op07M0mod3 + .long Op08mod3 + .long Op09M0mod3 + .long Op0AM0mod3 + .long Op0Bmod3 + .long Op0CM0mod3 + .long Op0DM0mod3 + .long Op0EM0mod3 + .long Op0FM0mod3 + .long Op10mod3 + .long Op11M0mod3 + .long Op12M0mod3 + .long Op13M0mod3 + .long Op14M0mod3 + .long Op15M0mod3 + .long Op16M0mod3 + .long Op17M0mod3 + .long Op18mod3 + .long Op19M0mod3 + .long Op1AM0mod3 + .long Op1Bmod3 + .long Op1CM0mod3 + .long Op1DM0mod3 + .long Op1EM0mod3 + .long Op1FM0mod3 + .long Op20mod3 + .long Op21M0mod3 + .long Op22mod3 + .long Op23M0mod3 + .long Op24M0mod3 + .long Op25M0mod3 + .long Op26M0mod3 + .long Op27M0mod3 + .long Op28mod3 + .long Op29M0mod3 + .long Op2AM0mod3 + .long Op2Bmod3 + .long Op2CM0mod3 + .long Op2DM0mod3 + .long Op2EM0mod3 + .long Op2FM0mod3 + .long Op30mod3 + .long Op31M0mod3 + .long Op32M0mod3 + .long Op33M0mod3 + .long Op34M0mod3 + .long Op35M0mod3 + .long Op36M0mod3 + .long Op37M0mod3 + .long Op38mod3 + .long Op39M0mod3 + .long Op3AM0mod3 + .long Op3Bmod3 + .long Op3CM0mod3 + .long Op3DM0mod3 + .long Op3EM0mod3 + .long Op3FM0mod3 + .long Op40mod3 + .long Op41M0mod3 + .long Op42mod3 + .long Op43M0mod3 + .long Op44X0mod3 + .long Op45M0mod3 + .long Op46M0mod3 + .long Op47M0mod3 + .long Op48M0mod3 + .long Op49M0mod3 + .long Op4AM0mod3 + .long Op4Bmod3 + .long Op4Cmod3 + .long Op4DM0mod3 + .long Op4EM0mod3 + .long Op4FM0mod3 + .long Op50mod3 + .long Op51M0mod3 + .long Op52M0mod3 + .long Op53M0mod3 + .long Op54X0mod3 + .long Op55M0mod3 + .long Op56M0mod3 + .long Op57M0mod3 + .long Op58mod3 + .long Op59M0mod3 + .long Op5AX0mod3 + .long Op5Bmod3 + .long Op5Cmod3 + .long Op5DM0mod3 + .long Op5EM0mod3 + .long Op5FM0mod3 + .long Op60mod3 + .long Op61M0mod3 + .long Op62mod3 + .long Op63M0mod3 + .long Op64M0mod3 + .long Op65M0mod3 + .long Op66M0mod3 + .long Op67M0mod3 + .long Op68M0mod3 + .long Op69M0mod3 + .long Op6AM0mod3 + .long Op6Bmod3 + .long Op6Cmod3 + .long Op6DM0mod3 + .long Op6EM0mod3 + .long Op6FM0mod3 + .long Op70mod3 + .long Op71M0mod3 + .long Op72M0mod3 + .long Op73M0mod3 + .long Op74M0mod3 + .long Op75M0mod3 + .long Op76M0mod3 + .long Op77M0mod3 + .long Op78mod3 + .long Op79M0mod3 + .long Op7AX0mod3 + .long Op7Bmod3 + .long Op7Cmod3 + .long Op7DM0mod3 + .long Op7EM0mod3 + .long Op7FM0mod3 + .long Op80mod3 + .long Op81M0mod3 + .long Op82mod3 + .long Op83M0mod3 + .long Op84X0mod3 + .long Op85M0mod3 + .long Op86X0mod3 + .long Op87M0mod3 + .long Op88X0mod3 + .long Op89M0mod3 + .long Op8AM0mod3 + .long Op8Bmod3 + .long Op8CX0mod3 + .long Op8DM0mod3 + .long Op8EX0mod3 + .long Op8FM0mod3 + .long Op90mod3 + .long Op91M0mod3 + .long Op92M0mod3 + .long Op93M0mod3 + .long Op94X0mod3 + .long Op95M0mod3 + .long Op96X0mod3 + .long Op97M0mod3 + .long Op98M0mod3 + .long Op99M0mod3 + .long Op9Amod3 + .long Op9BX0mod3 + .long Op9CM0mod3 + .long Op9DM0mod3 + .long Op9EM0mod3 + .long Op9FM0mod3 + .long OpA0X0mod3 + .long OpA1M0mod3 + .long OpA2X0mod3 + .long OpA3M0mod3 + .long OpA4X0mod3 + .long OpA5M0mod3 + .long OpA6X0mod3 + .long OpA7M0mod3 + .long OpA8X0mod3 + .long OpA9M0mod3 + .long OpAAX0mod3 + .long OpABmod3 + .long OpACX0mod3 + .long OpADM0mod3 + .long OpAEX0mod3 + .long OpAFM0mod3 + .long OpB0mod3 + .long OpB1M0mod3 + .long OpB2M0mod3 + .long OpB3M0mod3 + .long OpB4X0mod3 + .long OpB5M0mod3 + .long OpB6X0mod3 + .long OpB7M0mod3 + .long OpB8mod3 + .long OpB9M0mod3 + .long OpBAX0mod3 + .long OpBBX0mod3 + .long OpBCX0mod3 + .long OpBDM0mod3 + .long OpBEX0mod3 + .long OpBFM0mod3 + .long OpC0X0mod3 + .long OpC1M0mod3 + .long OpC2mod3 + .long OpC3M0mod3 + .long OpC4X0mod3 + .long OpC5M0mod3 + .long OpC6M0mod3 + .long OpC7M0mod3 + .long OpC8X0mod3 + .long OpC9M0mod3 + .long OpCAX0mod3 + .long OpCBmod3 + .long OpCCX0mod3 + .long OpCDM0mod3 + .long OpCEM0mod3 + .long OpCFM0mod3 + .long OpD0mod3 + .long OpD1M0mod3 + .long OpD2M0mod3 + .long OpD3M0mod3 + .long OpD4mod3 + .long OpD5M0mod3 + .long OpD6M0mod3 + .long OpD7M0mod3 + .long OpD8mod3 + .long OpD9M0mod3 + .long OpDAX0mod3 + .long OpDBmod3 + .long OpDCmod3 + .long OpDDM0mod3 + .long OpDEM0mod3 + .long OpDFM0mod3 + .long OpE0X0mod3 + .long OpE1M0mod3 + .long OpE2mod3 + .long OpE3M0mod3 + .long OpE4X0mod3 + .long OpE5M0mod3 + .long OpE6M0mod3 + .long OpE7M0mod3 + .long OpE8X0mod3 + .long OpE9M0mod3 + .long OpEAmod3 + .long OpEBmod3 + .long OpECX0mod3 + .long OpEDM0mod3 + .long OpEEM0mod3 + .long OpEFM0mod3 + .long OpF0mod3 + .long OpF1M0mod3 + .long OpF2M0mod3 + .long OpF3M0mod3 + .long OpF4mod3 + .long OpF5M0mod3 + .long OpF6M0mod3 + .long OpF7M0mod3 + .long OpF8mod3 + .long OpF9M0mod3 + .long OpFAX0mod3 + .long OpFBmod3 + .long OpFCmod3 + .long OpFDM0mod3 + .long OpFEM0mod3 + .long OpFFM0mod3 +Op00mod3: +lbl00mod3: Op00 + NEXTOPCODE +Op01M0mod3: +lbl01mod3a: DirectIndexedIndirect0 +lbl01mod3b: ORA16 + NEXTOPCODE +Op02mod3: +lbl02mod3: Op02 + NEXTOPCODE +Op03M0mod3: +lbl03mod3a: StackasmRelative +lbl03mod3b: ORA16 + NEXTOPCODE +Op04M0mod3: +lbl04mod3a: Direct +lbl04mod3b: TSB16 + NEXTOPCODE +Op05M0mod3: +lbl05mod3a: Direct +lbl05mod3b: ORA16 + NEXTOPCODE +Op06M0mod3: +lbl06mod3a: Direct +lbl06mod3b: ASL16 + NEXTOPCODE +Op07M0mod3: +lbl07mod3a: DirectIndirectLong +lbl07mod3b: ORA16 + NEXTOPCODE +Op08mod3: +lbl08mod3: Op08 + NEXTOPCODE +Op09M0mod3: +lbl09mod3: Op09M0 + NEXTOPCODE +Op0AM0mod3: +lbl0Amod3a: A_ASL16 + NEXTOPCODE +Op0Bmod3: +lbl0Bmod3: Op0B + NEXTOPCODE +Op0CM0mod3: +lbl0Cmod3a: Absolute +lbl0Cmod3b: TSB16 + NEXTOPCODE +Op0DM0mod3: +lbl0Dmod3a: Absolute +lbl0Dmod3b: ORA16 + NEXTOPCODE +Op0EM0mod3: +lbl0Emod3a: Absolute +lbl0Emod3b: ASL16 + NEXTOPCODE +Op0FM0mod3: +lbl0Fmod3a: AbsoluteLong +lbl0Fmod3b: ORA16 + NEXTOPCODE +Op10mod3: +lbl10mod3: Op10 + NEXTOPCODE +Op11M0mod3: +lbl11mod3a: DirectIndirectIndexed0 +lbl11mod3b: ORA16 + NEXTOPCODE +Op12M0mod3: +lbl12mod3a: DirectIndirect +lbl12mod3b: ORA16 + NEXTOPCODE +Op13M0mod3: +lbl13mod3a: StackasmRelativeIndirectIndexed0 +lbl13mod3b: ORA16 + NEXTOPCODE +Op14M0mod3: +lbl14mod3a: Direct +lbl14mod3b: TRB16 + NEXTOPCODE +Op15M0mod3: +lbl15mod3a: DirectIndexedX0 +lbl15mod3b: ORA16 + NEXTOPCODE +Op16M0mod3: +lbl16mod3a: DirectIndexedX0 +lbl16mod3b: ASL16 + NEXTOPCODE +Op17M0mod3: +lbl17mod3a: DirectIndirectIndexedLong0 +lbl17mod3b: ORA16 + NEXTOPCODE +Op18mod3: +lbl18mod3: Op18 + NEXTOPCODE +Op19M0mod3: +lbl19mod3a: AbsoluteIndexedY0 +lbl19mod3b: ORA16 + NEXTOPCODE +Op1AM0mod3: +lbl1Amod3a: A_INC16 + NEXTOPCODE +Op1Bmod3: +lbl1Bmod3: Op1BM0 + NEXTOPCODE +Op1CM0mod3: +lbl1Cmod3a: Absolute +lbl1Cmod3b: TRB16 + NEXTOPCODE +Op1DM0mod3: +lbl1Dmod3a: AbsoluteIndexedX0 +lbl1Dmod3b: ORA16 + NEXTOPCODE +Op1EM0mod3: +lbl1Emod3a: AbsoluteIndexedX0 +lbl1Emod3b: ASL16 + NEXTOPCODE +Op1FM0mod3: +lbl1Fmod3a: AbsoluteLongIndexedX0 +lbl1Fmod3b: ORA16 + NEXTOPCODE +Op20mod3: +lbl20mod3: Op20 + NEXTOPCODE +Op21M0mod3: +lbl21mod3a: DirectIndexedIndirect0 +lbl21mod3b: AND16 + NEXTOPCODE +Op22mod3: +lbl22mod3: Op22 + NEXTOPCODE +Op23M0mod3: +lbl23mod3a: StackasmRelative +lbl23mod3b: AND16 + NEXTOPCODE +Op24M0mod3: +lbl24mod3a: Direct +lbl24mod3b: BIT16 + NEXTOPCODE +Op25M0mod3: +lbl25mod3a: Direct +lbl25mod3b: AND16 + NEXTOPCODE +Op26M0mod3: +lbl26mod3a: Direct +lbl26mod3b: ROL16 + NEXTOPCODE +Op27M0mod3: +lbl27mod3a: DirectIndirectLong + +lbl27mod3b: AND16 + NEXTOPCODE +Op28mod3: +lbl28mod3: Op28X0M0 + NEXTOPCODE +.pool +Op29M0mod3: +lbl29mod3: Op29M0 + NEXTOPCODE +Op2AM0mod3: +lbl2Amod3a: A_ROL16 + NEXTOPCODE +Op2Bmod3: +lbl2Bmod3: Op2B + NEXTOPCODE +Op2CM0mod3: +lbl2Cmod3a: Absolute +lbl2Cmod3b: BIT16 + NEXTOPCODE +Op2DM0mod3: +lbl2Dmod3a: Absolute +lbl2Dmod3b: AND16 + NEXTOPCODE +Op2EM0mod3: +lbl2Emod3a: Absolute +lbl2Emod3b: ROL16 + NEXTOPCODE +Op2FM0mod3: +lbl2Fmod3a: AbsoluteLong +lbl2Fmod3b: AND16 + NEXTOPCODE +Op30mod3: +lbl30mod3: Op30 + NEXTOPCODE +Op31M0mod3: +lbl31mod3a: DirectIndirectIndexed0 +lbl31mod3b: AND16 + NEXTOPCODE +Op32M0mod3: +lbl32mod3a: DirectIndirect +lbl32mod3b: AND16 + NEXTOPCODE +Op33M0mod3: +lbl33mod3a: StackasmRelativeIndirectIndexed0 +lbl33mod3b: AND16 + NEXTOPCODE +Op34M0mod3: +lbl34mod3a: DirectIndexedX0 +lbl34mod3b: BIT16 + NEXTOPCODE +Op35M0mod3: +lbl35mod3a: DirectIndexedX0 +lbl35mod3b: AND16 + NEXTOPCODE +Op36M0mod3: +lbl36mod3a: DirectIndexedX0 +lbl36mod3b: ROL16 + NEXTOPCODE +Op37M0mod3: +lbl37mod3a: DirectIndirectIndexedLong0 +lbl37mod3b: AND16 + NEXTOPCODE +Op38mod3: +lbl38mod3: Op38 + NEXTOPCODE +Op39M0mod3: +lbl39mod3a: AbsoluteIndexedY0 +lbl39mod3b: AND16 + NEXTOPCODE +Op3AM0mod3: +lbl3Amod3a: A_DEC16 + NEXTOPCODE +Op3Bmod3: +lbl3Bmod3: Op3BM0 + NEXTOPCODE +Op3CM0mod3: +lbl3Cmod3a: AbsoluteIndexedX0 +lbl3Cmod3b: BIT16 + NEXTOPCODE +Op3DM0mod3: +lbl3Dmod3a: AbsoluteIndexedX0 +lbl3Dmod3b: AND16 + NEXTOPCODE +Op3EM0mod3: +lbl3Emod3a: AbsoluteIndexedX0 +lbl3Emod3b: ROL16 + NEXTOPCODE +Op3FM0mod3: +lbl3Fmod3a: AbsoluteLongIndexedX0 +lbl3Fmod3b: AND16 + NEXTOPCODE +Op40mod3: +lbl40mod3: Op40X0M0 + NEXTOPCODE +.pool +Op41M0mod3: +lbl41mod3a: DirectIndexedIndirect0 +lbl41mod3b: EOR16 + NEXTOPCODE +Op42mod3: +lbl42mod3: Op42 + NEXTOPCODE +Op43M0mod3: +lbl43mod3a: StackasmRelative +lbl43mod3b: EOR16 + NEXTOPCODE +Op44X0mod3: +lbl44mod3: Op44X0M0 + NEXTOPCODE +Op45M0mod3: +lbl45mod3a: Direct +lbl45mod3b: EOR16 + NEXTOPCODE +Op46M0mod3: +lbl46mod3a: Direct +lbl46mod3b: LSR16 + NEXTOPCODE +Op47M0mod3: +lbl47mod3a: DirectIndirectLong +lbl47mod3b: EOR16 + NEXTOPCODE +Op48M0mod3: +lbl48mod3: Op48M0 + NEXTOPCODE +Op49M0mod3: +lbl49mod3: Op49M0 + NEXTOPCODE +Op4AM0mod3: +lbl4Amod3a: A_LSR16 + NEXTOPCODE +Op4Bmod3: +lbl4Bmod3: Op4B + NEXTOPCODE +Op4Cmod3: +lbl4Cmod3: Op4C + NEXTOPCODE +Op4DM0mod3: +lbl4Dmod3a: Absolute +lbl4Dmod3b: EOR16 + NEXTOPCODE +Op4EM0mod3: +lbl4Emod3a: Absolute +lbl4Emod3b: LSR16 + NEXTOPCODE +Op4FM0mod3: +lbl4Fmod3a: AbsoluteLong +lbl4Fmod3b: EOR16 + NEXTOPCODE +Op50mod3: +lbl50mod3: Op50 + NEXTOPCODE +Op51M0mod3: +lbl51mod3a: DirectIndirectIndexed0 +lbl51mod3b: EOR16 + NEXTOPCODE +Op52M0mod3: +lbl52mod3a: DirectIndirect +lbl52mod3b: EOR16 + NEXTOPCODE +Op53M0mod3: +lbl53mod3a: StackasmRelativeIndirectIndexed0 +lbl53mod3b: EOR16 + NEXTOPCODE +Op54X0mod3: +lbl54mod3: Op54X0M0 + NEXTOPCODE +Op55M0mod3: +lbl55mod3a: DirectIndexedX0 +lbl55mod3b: EOR16 + NEXTOPCODE +Op56M0mod3: +lbl56mod3a: DirectIndexedX0 +lbl56mod3b: LSR16 + NEXTOPCODE +Op57M0mod3: +lbl57mod3a: DirectIndirectIndexedLong0 +lbl57mod3b: EOR16 + NEXTOPCODE +Op58mod3: +lbl58mod3: Op58 + NEXTOPCODE +Op59M0mod3: +lbl59mod3a: AbsoluteIndexedY0 +lbl59mod3b: EOR16 + NEXTOPCODE +Op5AX0mod3: +lbl5Amod3: Op5AX0 + NEXTOPCODE +Op5Bmod3: +lbl5Bmod3: Op5BM0 + NEXTOPCODE +Op5Cmod3: +lbl5Cmod3: Op5C + NEXTOPCODE +Op5DM0mod3: +lbl5Dmod3a: AbsoluteIndexedX0 +lbl5Dmod3b: EOR16 + NEXTOPCODE +Op5EM0mod3: +lbl5Emod3a: AbsoluteIndexedX0 +lbl5Emod3b: LSR16 + NEXTOPCODE +Op5FM0mod3: +lbl5Fmod3a: AbsoluteLongIndexedX0 +lbl5Fmod3b: EOR16 + NEXTOPCODE +Op60mod3: +lbl60mod3: Op60 + NEXTOPCODE +Op61M0mod3: +lbl61mod3a: DirectIndexedIndirect0 +lbl61mod3b: ADC16 + NEXTOPCODE +Op62mod3: +lbl62mod3: Op62 + NEXTOPCODE +Op63M0mod3: +lbl63mod3a: StackasmRelative +lbl63mod3b: ADC16 + NEXTOPCODE +.pool +Op64M0mod3: +lbl64mod3a: Direct +lbl64mod3b: STZ16 + NEXTOPCODE +Op65M0mod3: +lbl65mod3a: Direct +lbl65mod3b: ADC16 + NEXTOPCODE +.pool +Op66M0mod3: +lbl66mod3a: Direct +lbl66mod3b: ROR16 + NEXTOPCODE +Op67M0mod3: +lbl67mod3a: DirectIndirectLong +lbl67mod3b: ADC16 + NEXTOPCODE +.pool +Op68M0mod3: +lbl68mod3: Op68M0 + NEXTOPCODE +Op69M0mod3: +lbl69mod3a: Immediate16 +lbl69mod3b: ADC16 + NEXTOPCODE +.pool +Op6AM0mod3: +lbl6Amod3a: A_ROR16 + NEXTOPCODE +Op6Bmod3: +lbl6Bmod3: Op6B + NEXTOPCODE +Op6Cmod3: +lbl6Cmod3: Op6C + NEXTOPCODE +Op6DM0mod3: +lbl6Dmod3a: Absolute +lbl6Dmod3b: ADC16 + NEXTOPCODE +Op6EM0mod3: +lbl6Emod3a: Absolute +lbl6Emod3b: ROR16 + NEXTOPCODE +Op6FM0mod3: +lbl6Fmod3a: AbsoluteLong +lbl6Fmod3b: ADC16 + NEXTOPCODE +Op70mod3: +lbl70mod3: Op70 + NEXTOPCODE +Op71M0mod3: +lbl71mod3a: DirectIndirectIndexed0 +lbl71mod3b: ADC16 + NEXTOPCODE +Op72M0mod3: +lbl72mod3a: DirectIndirect +lbl72mod3b: ADC16 + NEXTOPCODE +Op73M0mod3: +lbl73mod3a: StackasmRelativeIndirectIndexed0 +lbl73mod3b: ADC16 + NEXTOPCODE +.pool +Op74M0mod3: +lbl74mod3a: DirectIndexedX0 +lbl74mod3b: STZ16 + NEXTOPCODE +Op75M0mod3: +lbl75mod3a: DirectIndexedX0 +lbl75mod3b: ADC16 + NEXTOPCODE +.pool +Op76M0mod3: +lbl76mod3a: DirectIndexedX0 +lbl76mod3b: ROR16 + NEXTOPCODE +Op77M0mod3: +lbl77mod3a: DirectIndirectIndexedLong0 +lbl77mod3b: ADC16 + NEXTOPCODE +Op78mod3: +lbl78mod3: Op78 + NEXTOPCODE +Op79M0mod3: +lbl79mod3a: AbsoluteIndexedY0 +lbl79mod3b: ADC16 + NEXTOPCODE +Op7AX0mod3: +lbl7Amod3: Op7AX0 + NEXTOPCODE +Op7Bmod3: +lbl7Bmod3: Op7BM0 + NEXTOPCODE +Op7Cmod3: +lbl7Cmod3: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE +Op7DM0mod3: +lbl7Dmod3a: AbsoluteIndexedX0 +lbl7Dmod3b: ADC16 + NEXTOPCODE +Op7EM0mod3: +lbl7Emod3a: AbsoluteIndexedX0 +lbl7Emod3b: ROR16 + NEXTOPCODE +Op7FM0mod3: +lbl7Fmod3a: AbsoluteLongIndexedX0 +lbl7Fmod3b: ADC16 + NEXTOPCODE +.pool +Op80mod3: +lbl80mod3: Op80 + NEXTOPCODE +Op81M0mod3: +lbl81mod3a: DirectIndexedIndirect0 +lbl81mod3b: Op81M0 + NEXTOPCODE +Op82mod3: +lbl82mod3: Op82 + NEXTOPCODE +Op83M0mod3: +lbl83mod3a: StackasmRelative +lbl83mod3b: STA16 + NEXTOPCODE +Op84X0mod3: +lbl84mod3a: Direct +lbl84mod3b: STY16 + NEXTOPCODE +Op85M0mod3: +lbl85mod3a: Direct +lbl85mod3b: STA16 + NEXTOPCODE +Op86X0mod3: +lbl86mod3a: Direct +lbl86mod3b: STX16 + NEXTOPCODE +Op87M0mod3: +lbl87mod3a: DirectIndirectLong +lbl87mod3b: STA16 + NEXTOPCODE +Op88X0mod3: +lbl88mod3: Op88X0 + NEXTOPCODE +Op89M0mod3: +lbl89mod3: Op89M0 + NEXTOPCODE +Op8AM0mod3: +lbl8Amod3: Op8AM0X0 + NEXTOPCODE +Op8Bmod3: +lbl8Bmod3: Op8B + NEXTOPCODE +Op8CX0mod3: +lbl8Cmod3a: Absolute +lbl8Cmod3b: STY16 + NEXTOPCODE +Op8DM0mod3: +lbl8Dmod3a: Absolute +lbl8Dmod3b: STA16 + NEXTOPCODE +Op8EX0mod3: +lbl8Emod3a: Absolute +lbl8Emod3b: STX16 + NEXTOPCODE +Op8FM0mod3: +lbl8Fmod3a: AbsoluteLong +lbl8Fmod3b: STA16 + NEXTOPCODE +Op90mod3: +lbl90mod3: Op90 + NEXTOPCODE +Op91M0mod3: +lbl91mod3a: DirectIndirectIndexed0 +lbl91mod3b: STA16 + NEXTOPCODE +Op92M0mod3: +lbl92mod3a: DirectIndirect +lbl92mod3b: STA16 + NEXTOPCODE +Op93M0mod3: +lbl93mod3a: StackasmRelativeIndirectIndexed0 +lbl93mod3b: STA16 + NEXTOPCODE +Op94X0mod3: +lbl94mod3a: DirectIndexedX0 +lbl94mod3b: STY16 + NEXTOPCODE +Op95M0mod3: +lbl95mod3a: DirectIndexedX0 +lbl95mod3b: STA16 + NEXTOPCODE +Op96X0mod3: +lbl96mod3a: DirectIndexedY0 +lbl96mod3b: STX16 + NEXTOPCODE +Op97M0mod3: +lbl97mod3a: DirectIndirectIndexedLong0 +lbl97mod3b: STA16 + NEXTOPCODE +Op98M0mod3: +lbl98mod3: Op98M0X0 + NEXTOPCODE +Op99M0mod3: +lbl99mod3a: AbsoluteIndexedY0 +lbl99mod3b: STA16 + NEXTOPCODE +Op9Amod3: +lbl9Amod3: Op9AX0 + NEXTOPCODE +Op9BX0mod3: +lbl9Bmod3: Op9BX0 + NEXTOPCODE +Op9CM0mod3: +lbl9Cmod3a: Absolute +lbl9Cmod3b: STZ16 + NEXTOPCODE +Op9DM0mod3: +lbl9Dmod3a: AbsoluteIndexedX0 +lbl9Dmod3b: STA16 + NEXTOPCODE +Op9EM0mod3: +lbl9Emod3: AbsoluteIndexedX0 + STZ16 + NEXTOPCODE +Op9FM0mod3: +lbl9Fmod3a: AbsoluteLongIndexedX0 +lbl9Fmod3b: STA16 + NEXTOPCODE +OpA0X0mod3: +lblA0mod3: OpA0X0 + NEXTOPCODE +OpA1M0mod3: +lblA1mod3a: DirectIndexedIndirect0 +lblA1mod3b: LDA16 + NEXTOPCODE +OpA2X0mod3: +lblA2mod3: OpA2X0 + NEXTOPCODE +OpA3M0mod3: +lblA3mod3a: StackasmRelative +lblA3mod3b: LDA16 + NEXTOPCODE +OpA4X0mod3: +lblA4mod3a: Direct +lblA4mod3b: LDY16 + NEXTOPCODE +OpA5M0mod3: +lblA5mod3a: Direct +lblA5mod3b: LDA16 + NEXTOPCODE +OpA6X0mod3: +lblA6mod3a: Direct +lblA6mod3b: LDX16 + NEXTOPCODE +OpA7M0mod3: +lblA7mod3a: DirectIndirectLong +lblA7mod3b: LDA16 + NEXTOPCODE +OpA8X0mod3: +lblA8mod3: OpA8X0M0 + NEXTOPCODE +OpA9M0mod3: +lblA9mod3: OpA9M0 + NEXTOPCODE +OpAAX0mod3: +lblAAmod3: OpAAX0M0 + NEXTOPCODE +OpABmod3: +lblABmod3: OpAB + NEXTOPCODE +OpACX0mod3: +lblACmod3a: Absolute +lblACmod3b: LDY16 + NEXTOPCODE +OpADM0mod3: +lblADmod3a: Absolute +lblADmod3b: LDA16 + NEXTOPCODE +OpAEX0mod3: +lblAEmod3a: Absolute +lblAEmod3b: LDX16 + NEXTOPCODE +OpAFM0mod3: +lblAFmod3a: AbsoluteLong +lblAFmod3b: LDA16 + NEXTOPCODE +OpB0mod3: +lblB0mod3: OpB0 + NEXTOPCODE +OpB1M0mod3: +lblB1mod3a: DirectIndirectIndexed0 +lblB1mod3b: LDA16 + NEXTOPCODE +OpB2M0mod3: +lblB2mod3a: DirectIndirect +lblB2mod3b: LDA16 + NEXTOPCODE +OpB3M0mod3: +lblB3mod3a: StackasmRelativeIndirectIndexed0 +lblB3mod3b: LDA16 + NEXTOPCODE +OpB4X0mod3: +lblB4mod3a: DirectIndexedX0 +lblB4mod3b: LDY16 + NEXTOPCODE +OpB5M0mod3: +lblB5mod3a: DirectIndexedX0 +lblB5mod3b: LDA16 + NEXTOPCODE +OpB6X0mod3: +lblB6mod3a: DirectIndexedY0 +lblB6mod3b: LDX16 + NEXTOPCODE +OpB7M0mod3: +lblB7mod3a: DirectIndirectIndexedLong0 +lblB7mod3b: LDA16 + NEXTOPCODE +OpB8mod3: +lblB8mod3: OpB8 + NEXTOPCODE +OpB9M0mod3: +lblB9mod3a: AbsoluteIndexedY0 +lblB9mod3b: LDA16 + NEXTOPCODE +OpBAX0mod3: +lblBAmod3: OpBAX0 + NEXTOPCODE +OpBBX0mod3: +lblBBmod3: OpBBX0 + NEXTOPCODE +OpBCX0mod3: +lblBCmod3a: AbsoluteIndexedX0 +lblBCmod3b: LDY16 + NEXTOPCODE +OpBDM0mod3: +lblBDmod3a: AbsoluteIndexedX0 +lblBDmod3b: LDA16 + NEXTOPCODE +OpBEX0mod3: +lblBEmod3a: AbsoluteIndexedY0 +lblBEmod3b: LDX16 + NEXTOPCODE +OpBFM0mod3: +lblBFmod3a: AbsoluteLongIndexedX0 +lblBFmod3b: LDA16 + NEXTOPCODE +OpC0X0mod3: +lblC0mod3: OpC0X0 + NEXTOPCODE +OpC1M0mod3: +lblC1mod3a: DirectIndexedIndirect0 +lblC1mod3b: CMP16 + NEXTOPCODE +OpC2mod3: +lblC2mod3: OpC2 + NEXTOPCODE +.pool +OpC3M0mod3: +lblC3mod3a: StackasmRelative +lblC3mod3b: CMP16 + NEXTOPCODE +OpC4X0mod3: +lblC4mod3a: Direct +lblC4mod3b: CMY16 + NEXTOPCODE +OpC5M0mod3: +lblC5mod3a: Direct +lblC5mod3b: CMP16 + NEXTOPCODE +OpC6M0mod3: +lblC6mod3a: Direct +lblC6mod3b: DEC16 + NEXTOPCODE +OpC7M0mod3: +lblC7mod3a: DirectIndirectLong +lblC7mod3b: CMP16 + NEXTOPCODE +OpC8X0mod3: +lblC8mod3: OpC8X0 + NEXTOPCODE +OpC9M0mod3: +lblC9mod3: OpC9M0 + NEXTOPCODE +OpCAX0mod3: +lblCAmod3: OpCAX0 + NEXTOPCODE +OpCBmod3: +lblCBmod3: OpCB + NEXTOPCODE +OpCCX0mod3: +lblCCmod3a: Absolute +lblCCmod3b: CMY16 + NEXTOPCODE +OpCDM0mod3: +lblCDmod3a: Absolute +lblCDmod3b: CMP16 + NEXTOPCODE +OpCEM0mod3: +lblCEmod3a: Absolute +lblCEmod3b: DEC16 + NEXTOPCODE +OpCFM0mod3: +lblCFmod3a: AbsoluteLong +lblCFmod3b: CMP16 + NEXTOPCODE +OpD0mod3: +lblD0mod3: OpD0 + NEXTOPCODE +OpD1M0mod3: +lblD1mod3a: DirectIndirectIndexed0 +lblD1mod3b: CMP16 + NEXTOPCODE +OpD2M0mod3: +lblD2mod3a: DirectIndirect +lblD2mod3b: CMP16 + NEXTOPCODE +OpD3M0mod3: +lblD3mod3a: StackasmRelativeIndirectIndexed0 +lblD3mod3b: CMP16 + NEXTOPCODE +OpD4mod3: +lblD4mod3: OpD4 + NEXTOPCODE +OpD5M0mod3: +lblD5mod3a: DirectIndexedX0 +lblD5mod3b: CMP16 + NEXTOPCODE +OpD6M0mod3: +lblD6mod3a: DirectIndexedX0 +lblD6mod3b: DEC16 + NEXTOPCODE +OpD7M0mod3: +lblD7mod3a: DirectIndirectIndexedLong0 +lblD7mod3b: CMP16 + NEXTOPCODE +OpD8mod3: +lblD8mod3: OpD8 + NEXTOPCODE +OpD9M0mod3: +lblD9mod3a: AbsoluteIndexedY0 +lblD9mod3b: CMP16 + NEXTOPCODE +OpDAX0mod3: +lblDAmod3: OpDAX0 + NEXTOPCODE +OpDBmod3: +lblDBmod3: OpDB + NEXTOPCODE +OpDCmod3: +lblDCmod3: OpDC + NEXTOPCODE +OpDDM0mod3: +lblDDmod3a: AbsoluteIndexedX0 +lblDDmod3b: CMP16 + NEXTOPCODE +OpDEM0mod3: +lblDEmod3a: AbsoluteIndexedX0 +lblDEmod3b: DEC16 + NEXTOPCODE +OpDFM0mod3: +lblDFmod3a: AbsoluteLongIndexedX0 +lblDFmod3b: CMP16 + NEXTOPCODE +OpE0X0mod3: +lblE0mod3: OpE0X0 + NEXTOPCODE +OpE1M0mod3: +lblE1mod3a: DirectIndexedIndirect0 +lblE1mod3b: SBC16 + NEXTOPCODE +OpE2mod3: +lblE2mod3: OpE2 + NEXTOPCODE +.pool +OpE3M0mod3: +lblE3mod3a: StackasmRelative +lblE3mod3b: SBC16 + NEXTOPCODE +OpE4X0mod3: +lblE4mod3a: Direct +lblE4mod3b: CMX16 + NEXTOPCODE +OpE5M0mod3: +lblE5mod3a: Direct +lblE5mod3b: SBC16 + NEXTOPCODE +OpE6M0mod3: +lblE6mod3a: Direct +lblE6mod3b: INC16 + NEXTOPCODE +OpE7M0mod3: +lblE7mod3a: DirectIndirectLong +lblE7mod3b: SBC16 + NEXTOPCODE +OpE8X0mod3: +lblE8mod3: OpE8X0 + NEXTOPCODE +OpE9M0mod3: +lblE9mod3a: Immediate16 +lblE9mod3b: SBC16 + NEXTOPCODE +OpEAmod3: +lblEAmod3: OpEA + NEXTOPCODE +OpEBmod3: +lblEBmod3: OpEBM0 + NEXTOPCODE +OpECX0mod3: +lblECmod3a: Absolute +lblECmod3b: CMX16 + NEXTOPCODE +OpEDM0mod3: +lblEDmod3a: Absolute +lblEDmod3b: SBC16 + NEXTOPCODE +OpEEM0mod3: +lblEEmod3a: Absolute +lblEEmod3b: INC16 + NEXTOPCODE +OpEFM0mod3: +lblEFmod3a: AbsoluteLong +lblEFmod3b: SBC16 + NEXTOPCODE +OpF0mod3: +lblF0mod3: OpF0 + NEXTOPCODE +OpF1M0mod3: +lblF1mod3a: DirectIndirectIndexed0 +lblF1mod3b: SBC16 + NEXTOPCODE +OpF2M0mod3: +lblF2mod3a: DirectIndirect +lblF2mod3b: SBC16 + NEXTOPCODE +OpF3M0mod3: +lblF3mod3a: StackasmRelativeIndirectIndexed0 +lblF3mod3b: SBC16 + NEXTOPCODE +OpF4mod3: +lblF4mod3: OpF4 + NEXTOPCODE +OpF5M0mod3: +lblF5mod3a: DirectIndexedX0 +lblF5mod3b: SBC16 + NEXTOPCODE +OpF6M0mod3: +lblF6mod3a: DirectIndexedX0 +lblF6mod3b: INC16 + NEXTOPCODE +OpF7M0mod3: +lblF7mod3a: DirectIndirectIndexedLong0 +lblF7mod3b: SBC16 + NEXTOPCODE +OpF8mod3: +lblF8mod3: OpF8 + NEXTOPCODE +OpF9M0mod3: +lblF9mod3a: AbsoluteIndexedY0 +lblF9mod3b: SBC16 + NEXTOPCODE +OpFAX0mod3: +lblFAmod3: OpFAX0 + NEXTOPCODE +OpFBmod3: +lblFBmod3: OpFB + NEXTOPCODE +OpFCmod3: +lblFCmod3: OpFCX0 + NEXTOPCODE +OpFDM0mod3: +lblFDmod3a: AbsoluteIndexedX0 +lblFDmod3b: SBC16 + NEXTOPCODE +OpFEM0mod3: +lblFEmod3a: AbsoluteIndexedX0 +lblFEmod3b: INC16 + NEXTOPCODE +OpFFM0mod3: +lblFFmod3a: AbsoluteLongIndexedX0 +lblFFmod3b: SBC16 + NEXTOPCODE +.pool + +jumptable4: .long Op00mod4 + .long Op01M0mod4 + .long Op02mod4 + .long Op03M0mod4 + .long Op04M0mod4 + .long Op05M0mod4 + .long Op06M0mod4 + .long Op07M0mod4 + .long Op08mod4 + .long Op09M0mod4 + .long Op0AM0mod4 + .long Op0Bmod4 + .long Op0CM0mod4 + .long Op0DM0mod4 + .long Op0EM0mod4 + .long Op0FM0mod4 + .long Op10mod4 + .long Op11M0mod4 + .long Op12M0mod4 + .long Op13M0mod4 + .long Op14M0mod4 + .long Op15M0mod4 + .long Op16M0mod4 + .long Op17M0mod4 + .long Op18mod4 + .long Op19M0mod4 + .long Op1AM0mod4 + .long Op1Bmod4 + .long Op1CM0mod4 + .long Op1DM0mod4 + .long Op1EM0mod4 + .long Op1FM0mod4 + .long Op20mod4 + .long Op21M0mod4 + .long Op22mod4 + .long Op23M0mod4 + .long Op24M0mod4 + .long Op25M0mod4 + .long Op26M0mod4 + .long Op27M0mod4 + .long Op28mod4 + .long Op29M0mod4 + .long Op2AM0mod4 + .long Op2Bmod4 + .long Op2CM0mod4 + .long Op2DM0mod4 + .long Op2EM0mod4 + .long Op2FM0mod4 + .long Op30mod4 + .long Op31M0mod4 + .long Op32M0mod4 + .long Op33M0mod4 + .long Op34M0mod4 + .long Op35M0mod4 + .long Op36M0mod4 + .long Op37M0mod4 + .long Op38mod4 + .long Op39M0mod4 + .long Op3AM0mod4 + .long Op3Bmod4 + .long Op3CM0mod4 + .long Op3DM0mod4 + .long Op3EM0mod4 + .long Op3FM0mod4 + .long Op40mod4 + .long Op41M0mod4 + .long Op42mod4 + .long Op43M0mod4 + .long Op44X1mod4 + .long Op45M0mod4 + .long Op46M0mod4 + .long Op47M0mod4 + .long Op48M0mod4 + .long Op49M0mod4 + .long Op4AM0mod4 + .long Op4Bmod4 + .long Op4Cmod4 + .long Op4DM0mod4 + .long Op4EM0mod4 + .long Op4FM0mod4 + .long Op50mod4 + .long Op51M0mod4 + .long Op52M0mod4 + .long Op53M0mod4 + .long Op54X1mod4 + .long Op55M0mod4 + .long Op56M0mod4 + .long Op57M0mod4 + .long Op58mod4 + .long Op59M0mod4 + .long Op5AX1mod4 + .long Op5Bmod4 + .long Op5Cmod4 + .long Op5DM0mod4 + .long Op5EM0mod4 + .long Op5FM0mod4 + .long Op60mod4 + .long Op61M0mod4 + .long Op62mod4 + .long Op63M0mod4 + .long Op64M0mod4 + .long Op65M0mod4 + .long Op66M0mod4 + .long Op67M0mod4 + .long Op68M0mod4 + .long Op69M0mod4 + .long Op6AM0mod4 + .long Op6Bmod4 + .long Op6Cmod4 + .long Op6DM0mod4 + .long Op6EM0mod4 + .long Op6FM0mod4 + .long Op70mod4 + .long Op71M0mod4 + .long Op72M0mod4 + .long Op73M0mod4 + .long Op74M0mod4 + .long Op75M0mod4 + .long Op76M0mod4 + .long Op77M0mod4 + .long Op78mod4 + .long Op79M0mod4 + .long Op7AX1mod4 + .long Op7Bmod4 + .long Op7Cmod4 + .long Op7DM0mod4 + .long Op7EM0mod4 + .long Op7FM0mod4 + .long Op80mod4 + .long Op81M0mod4 + .long Op82mod4 + .long Op83M0mod4 + .long Op84X1mod4 + .long Op85M0mod4 + .long Op86X1mod4 + .long Op87M0mod4 + .long Op88X1mod4 + .long Op89M0mod4 + .long Op8AM0mod4 + .long Op8Bmod4 + .long Op8CX1mod4 + .long Op8DM0mod4 + .long Op8EX1mod4 + .long Op8FM0mod4 + .long Op90mod4 + .long Op91M0mod4 + .long Op92M0mod4 + .long Op93M0mod4 + .long Op94X1mod4 + .long Op95M0mod4 + .long Op96X1mod4 + .long Op97M0mod4 + .long Op98M0mod4 + .long Op99M0mod4 + .long Op9Amod4 + .long Op9BX1mod4 + .long Op9CM0mod4 + .long Op9DM0mod4 + + .long Op9EM0mod4 + .long Op9FM0mod4 + .long OpA0X1mod4 + .long OpA1M0mod4 + .long OpA2X1mod4 + .long OpA3M0mod4 + .long OpA4X1mod4 + .long OpA5M0mod4 + .long OpA6X1mod4 + .long OpA7M0mod4 + .long OpA8X1mod4 + .long OpA9M0mod4 + .long OpAAX1mod4 + .long OpABmod4 + .long OpACX1mod4 + .long OpADM0mod4 + .long OpAEX1mod4 + .long OpAFM0mod4 + .long OpB0mod4 + .long OpB1M0mod4 + .long OpB2M0mod4 + .long OpB3M0mod4 + .long OpB4X1mod4 + .long OpB5M0mod4 + .long OpB6X1mod4 + .long OpB7M0mod4 + .long OpB8mod4 + .long OpB9M0mod4 + .long OpBAX1mod4 + .long OpBBX1mod4 + .long OpBCX1mod4 + .long OpBDM0mod4 + .long OpBEX1mod4 + .long OpBFM0mod4 + .long OpC0X1mod4 + .long OpC1M0mod4 + .long OpC2mod4 + .long OpC3M0mod4 + .long OpC4X1mod4 + .long OpC5M0mod4 + .long OpC6M0mod4 + .long OpC7M0mod4 + .long OpC8X1mod4 + .long OpC9M0mod4 + .long OpCAX1mod4 + .long OpCBmod4 + .long OpCCX1mod4 + .long OpCDM0mod4 + .long OpCEM0mod4 + .long OpCFM0mod4 + .long OpD0mod4 + .long OpD1M0mod4 + .long OpD2M0mod4 + .long OpD3M0mod4 + .long OpD4mod4 + .long OpD5M0mod4 + .long OpD6M0mod4 + .long OpD7M0mod4 + .long OpD8mod4 + .long OpD9M0mod4 + .long OpDAX1mod4 + .long OpDBmod4 + .long OpDCmod4 + .long OpDDM0mod4 + .long OpDEM0mod4 + .long OpDFM0mod4 + .long OpE0X1mod4 + .long OpE1M0mod4 + .long OpE2mod4 + .long OpE3M0mod4 + .long OpE4X1mod4 + .long OpE5M0mod4 + .long OpE6M0mod4 + .long OpE7M0mod4 + .long OpE8X1mod4 + .long OpE9M0mod4 + .long OpEAmod4 + .long OpEBmod4 + .long OpECX1mod4 + .long OpEDM0mod4 + .long OpEEM0mod4 + .long OpEFM0mod4 + .long OpF0mod4 + .long OpF1M0mod4 + .long OpF2M0mod4 + .long OpF3M0mod4 + .long OpF4mod4 + .long OpF5M0mod4 + .long OpF6M0mod4 + .long OpF7M0mod4 + .long OpF8mod4 + .long OpF9M0mod4 + .long OpFAX1mod4 + .long OpFBmod4 + .long OpFCmod4 + .long OpFDM0mod4 + .long OpFEM0mod4 + .long OpFFM0mod4 +Op00mod4: +lbl00mod4: Op00 + NEXTOPCODE +Op01M0mod4: +lbl01mod4a: DirectIndexedIndirect1 +lbl01mod4b: ORA16 + NEXTOPCODE +Op02mod4: +lbl02mod4: Op02 + NEXTOPCODE +Op03M0mod4: +lbl03mod4a: StackasmRelative +lbl03mod4b: ORA16 + NEXTOPCODE +Op04M0mod4: +lbl04mod4a: Direct +lbl04mod4b: TSB16 + NEXTOPCODE +Op05M0mod4: +lbl05mod4a: Direct +lbl05mod4b: ORA16 + NEXTOPCODE +Op06M0mod4: +lbl06mod4a: Direct +lbl06mod4b: ASL16 + NEXTOPCODE +Op07M0mod4: +lbl07mod4a: DirectIndirectLong +lbl07mod4b: ORA16 + NEXTOPCODE +Op08mod4: +lbl08mod4: Op08 + NEXTOPCODE +Op09M0mod4: +lbl09mod4: Op09M0 + NEXTOPCODE +Op0AM0mod4: +lbl0Amod4a: A_ASL16 + NEXTOPCODE +Op0Bmod4: +lbl0Bmod4: Op0B + NEXTOPCODE +Op0CM0mod4: +lbl0Cmod4a: Absolute +lbl0Cmod4b: TSB16 + NEXTOPCODE +Op0DM0mod4: +lbl0Dmod4a: Absolute +lbl0Dmod4b: ORA16 + NEXTOPCODE +Op0EM0mod4: +lbl0Emod4a: Absolute +lbl0Emod4b: ASL16 + NEXTOPCODE +Op0FM0mod4: +lbl0Fmod4a: AbsoluteLong +lbl0Fmod4b: ORA16 + NEXTOPCODE +Op10mod4: +lbl10mod4: Op10 + NEXTOPCODE +Op11M0mod4: +lbl11mod4a: DirectIndirectIndexed1 +lbl11mod4b: ORA16 + NEXTOPCODE +Op12M0mod4: +lbl12mod4a: DirectIndirect +lbl12mod4b: ORA16 + NEXTOPCODE +Op13M0mod4: +lbl13mod4a: StackasmRelativeIndirectIndexed1 +lbl13mod4b: ORA16 + NEXTOPCODE +Op14M0mod4: +lbl14mod4a: Direct +lbl14mod4b: TRB16 + NEXTOPCODE +Op15M0mod4: +lbl15mod4a: DirectIndexedX1 +lbl15mod4b: ORA16 + NEXTOPCODE +Op16M0mod4: +lbl16mod4a: DirectIndexedX1 +lbl16mod4b: ASL16 + NEXTOPCODE +Op17M0mod4: +lbl17mod4a: DirectIndirectIndexedLong1 +lbl17mod4b: ORA16 + NEXTOPCODE +Op18mod4: +lbl18mod4: Op18 + NEXTOPCODE +Op19M0mod4: +lbl19mod4a: AbsoluteIndexedY1 +lbl19mod4b: ORA16 + NEXTOPCODE +Op1AM0mod4: +lbl1Amod4a: A_INC16 + NEXTOPCODE +Op1Bmod4: +lbl1Bmod4: Op1BM0 + NEXTOPCODE +Op1CM0mod4: +lbl1Cmod4a: Absolute +lbl1Cmod4b: TRB16 + NEXTOPCODE +Op1DM0mod4: +lbl1Dmod4a: AbsoluteIndexedX1 +lbl1Dmod4b: ORA16 + NEXTOPCODE +Op1EM0mod4: +lbl1Emod4a: AbsoluteIndexedX1 +lbl1Emod4b: ASL16 + NEXTOPCODE +Op1FM0mod4: +lbl1Fmod4a: AbsoluteLongIndexedX1 +lbl1Fmod4b: ORA16 + NEXTOPCODE +Op20mod4: +lbl20mod4: Op20 + NEXTOPCODE +Op21M0mod4: +lbl21mod4a: DirectIndexedIndirect1 +lbl21mod4b: AND16 + NEXTOPCODE +Op22mod4: +lbl22mod4: Op22 + NEXTOPCODE +Op23M0mod4: +lbl23mod4a: StackasmRelative +lbl23mod4b: AND16 + NEXTOPCODE +Op24M0mod4: +lbl24mod4a: Direct +lbl24mod4b: BIT16 + NEXTOPCODE +Op25M0mod4: +lbl25mod4a: Direct +lbl25mod4b: AND16 + NEXTOPCODE +Op26M0mod4: +lbl26mod4a: Direct +lbl26mod4b: ROL16 + NEXTOPCODE +Op27M0mod4: +lbl27mod4a: DirectIndirectLong +lbl27mod4b: AND16 + NEXTOPCODE +Op28mod4: +lbl28mod4: Op28X1M0 + NEXTOPCODE +.pool +Op29M0mod4: +lbl29mod4: Op29M0 + NEXTOPCODE +Op2AM0mod4: +lbl2Amod4a: A_ROL16 + NEXTOPCODE +Op2Bmod4: +lbl2Bmod4: Op2B + NEXTOPCODE +Op2CM0mod4: +lbl2Cmod4a: Absolute +lbl2Cmod4b: BIT16 + NEXTOPCODE +Op2DM0mod4: +lbl2Dmod4a: Absolute +lbl2Dmod4b: AND16 + NEXTOPCODE +Op2EM0mod4: +lbl2Emod4a: Absolute +lbl2Emod4b: ROL16 + NEXTOPCODE +Op2FM0mod4: +lbl2Fmod4a: AbsoluteLong +lbl2Fmod4b: AND16 + NEXTOPCODE +Op30mod4: +lbl30mod4: Op30 + NEXTOPCODE +Op31M0mod4: +lbl31mod4a: DirectIndirectIndexed1 +lbl31mod4b: AND16 + NEXTOPCODE +Op32M0mod4: +lbl32mod4a: DirectIndirect +lbl32mod4b: AND16 + NEXTOPCODE +Op33M0mod4: +lbl33mod4a: StackasmRelativeIndirectIndexed1 +lbl33mod4b: AND16 + NEXTOPCODE +Op34M0mod4: +lbl34mod4a: DirectIndexedX1 +lbl34mod4b: BIT16 + NEXTOPCODE +Op35M0mod4: +lbl35mod4a: DirectIndexedX1 +lbl35mod4b: AND16 + NEXTOPCODE +Op36M0mod4: +lbl36mod4a: DirectIndexedX1 +lbl36mod4b: ROL16 + NEXTOPCODE +Op37M0mod4: +lbl37mod4a: DirectIndirectIndexedLong1 +lbl37mod4b: AND16 + NEXTOPCODE +Op38mod4: +lbl38mod4: Op38 + NEXTOPCODE +Op39M0mod4: +lbl39mod4a: AbsoluteIndexedY1 +lbl39mod4b: AND16 + NEXTOPCODE +Op3AM0mod4: +lbl3Amod4a: A_DEC16 + NEXTOPCODE +Op3Bmod4: +lbl3Bmod4: Op3BM0 + NEXTOPCODE +Op3CM0mod4: +lbl3Cmod4a: AbsoluteIndexedX1 +lbl3Cmod4b: BIT16 + NEXTOPCODE +Op3DM0mod4: +lbl3Dmod4a: AbsoluteIndexedX1 +lbl3Dmod4b: AND16 + NEXTOPCODE +Op3EM0mod4: +lbl3Emod4a: AbsoluteIndexedX1 +lbl3Emod4b: ROL16 + NEXTOPCODE +Op3FM0mod4: +lbl3Fmod4a: AbsoluteLongIndexedX1 +lbl3Fmod4b: AND16 + NEXTOPCODE +Op40mod4: +lbl40mod4: Op40X1M0 + NEXTOPCODE +.pool +Op41M0mod4: +lbl41mod4a: DirectIndexedIndirect1 +lbl41mod4b: EOR16 + NEXTOPCODE +Op42mod4: +lbl42mod4: Op42 + NEXTOPCODE +Op43M0mod4: +lbl43mod4a: StackasmRelative +lbl43mod4b: EOR16 + NEXTOPCODE +Op44X1mod4: +lbl44mod4: Op44X1M0 + NEXTOPCODE +Op45M0mod4: +lbl45mod4a: Direct +lbl45mod4b: EOR16 + NEXTOPCODE +Op46M0mod4: +lbl46mod4a: Direct +lbl46mod4b: LSR16 + NEXTOPCODE +Op47M0mod4: +lbl47mod4a: DirectIndirectLong +lbl47mod4b: EOR16 + NEXTOPCODE +Op48M0mod4: +lbl48mod4: Op48M0 + NEXTOPCODE +Op49M0mod4: +lbl49mod4: Op49M0 + NEXTOPCODE +Op4AM0mod4: +lbl4Amod4a: A_LSR16 + NEXTOPCODE +Op4Bmod4: +lbl4Bmod4: Op4B + NEXTOPCODE +Op4Cmod4: +lbl4Cmod4: Op4C + NEXTOPCODE +Op4DM0mod4: +lbl4Dmod4a: Absolute +lbl4Dmod4b: EOR16 + NEXTOPCODE +Op4EM0mod4: +lbl4Emod4a: Absolute +lbl4Emod4b: LSR16 + NEXTOPCODE +Op4FM0mod4: +lbl4Fmod4a: AbsoluteLong +lbl4Fmod4b: EOR16 + NEXTOPCODE +Op50mod4: +lbl50mod4: Op50 + NEXTOPCODE +Op51M0mod4: +lbl51mod4a: DirectIndirectIndexed1 +lbl51mod4b: EOR16 + NEXTOPCODE +Op52M0mod4: +lbl52mod4a: DirectIndirect +lbl52mod4b: EOR16 + NEXTOPCODE +Op53M0mod4: +lbl53mod4a: StackasmRelativeIndirectIndexed1 +lbl53mod4b: EOR16 + NEXTOPCODE + +Op54X1mod4: +lbl54mod4: Op54X1M0 + NEXTOPCODE +Op55M0mod4: +lbl55mod4a: DirectIndexedX1 +lbl55mod4b: EOR16 + NEXTOPCODE +Op56M0mod4: +lbl56mod4a: DirectIndexedX1 +lbl56mod4b: LSR16 + NEXTOPCODE +Op57M0mod4: +lbl57mod4a: DirectIndirectIndexedLong1 +lbl57mod4b: EOR16 + NEXTOPCODE +Op58mod4: +lbl58mod4: Op58 + NEXTOPCODE +Op59M0mod4: +lbl59mod4a: AbsoluteIndexedY1 +lbl59mod4b: EOR16 + NEXTOPCODE +Op5AX1mod4: +lbl5Amod4: Op5AX1 + NEXTOPCODE +Op5Bmod4: +lbl5Bmod4: Op5BM0 + NEXTOPCODE +Op5Cmod4: +lbl5Cmod4: Op5C + NEXTOPCODE +Op5DM0mod4: +lbl5Dmod4a: AbsoluteIndexedX1 +lbl5Dmod4b: EOR16 + NEXTOPCODE +Op5EM0mod4: +lbl5Emod4a: AbsoluteIndexedX1 +lbl5Emod4b: LSR16 + NEXTOPCODE +Op5FM0mod4: +lbl5Fmod4a: AbsoluteLongIndexedX1 +lbl5Fmod4b: EOR16 + NEXTOPCODE +Op60mod4: +lbl60mod4: Op60 + NEXTOPCODE +Op61M0mod4: +lbl61mod4a: DirectIndexedIndirect1 +lbl61mod4b: ADC16 + NEXTOPCODE +Op62mod4: +lbl62mod4: Op62 + NEXTOPCODE +Op63M0mod4: +lbl63mod4a: StackasmRelative +lbl63mod4b: ADC16 + NEXTOPCODE +.pool +Op64M0mod4: +lbl64mod4a: Direct +lbl64mod4b: STZ16 + NEXTOPCODE +Op65M0mod4: +lbl65mod4a: Direct +lbl65mod4b: ADC16 + NEXTOPCODE +.pool +Op66M0mod4: +lbl66mod4a: Direct +lbl66mod4b: ROR16 + NEXTOPCODE +Op67M0mod4: +lbl67mod4a: DirectIndirectLong +lbl67mod4b: ADC16 + NEXTOPCODE +.pool +Op68M0mod4: +lbl68mod4: Op68M0 + NEXTOPCODE +Op69M0mod4: +lbl69mod4a: Immediate16 +lbl69mod4b: ADC16 + NEXTOPCODE +.pool +Op6AM0mod4: +lbl6Amod4a: A_ROR16 + NEXTOPCODE +Op6Bmod4: +lbl6Bmod4: Op6B + NEXTOPCODE +Op6Cmod4: +lbl6Cmod4: Op6C + NEXTOPCODE +Op6DM0mod4: +lbl6Dmod4a: Absolute +lbl6Dmod4b: ADC16 + NEXTOPCODE +Op6EM0mod4: +lbl6Emod4a: Absolute +lbl6Emod4b: ROR16 + NEXTOPCODE +Op6FM0mod4: +lbl6Fmod4a: AbsoluteLong +lbl6Fmod4b: ADC16 + NEXTOPCODE +Op70mod4: +lbl70mod4: Op70 + NEXTOPCODE +Op71M0mod4: +lbl71mod4a: DirectIndirectIndexed1 +lbl71mod4b: ADC16 + NEXTOPCODE +Op72M0mod4: +lbl72mod4a: DirectIndirect +lbl72mod4b: ADC16 + NEXTOPCODE +Op73M0mod4: +lbl73mod4a: StackasmRelativeIndirectIndexed1 +lbl73mod4b: ADC16 + NEXTOPCODE +.pool +Op74M0mod4: +lbl74mod4a: DirectIndexedX1 +lbl74mod4b: STZ16 + NEXTOPCODE +Op75M0mod4: +lbl75mod4a: DirectIndexedX1 +lbl75mod4b: ADC16 + NEXTOPCODE +.pool +Op76M0mod4: +lbl76mod4a: DirectIndexedX1 +lbl76mod4b: ROR16 + NEXTOPCODE +Op77M0mod4: +lbl77mod4a: DirectIndirectIndexedLong1 +lbl77mod4b: ADC16 + NEXTOPCODE +Op78mod4: +lbl78mod4: Op78 + NEXTOPCODE +Op79M0mod4: +lbl79mod4a: AbsoluteIndexedY1 +lbl79mod4b: ADC16 + NEXTOPCODE +Op7AX1mod4: +lbl7Amod4: Op7AX1 + NEXTOPCODE +Op7Bmod4: +lbl7Bmod4: Op7BM0 + NEXTOPCODE +Op7Cmod4: +lbl7Cmod4: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE +Op7DM0mod4: +lbl7Dmod4a: AbsoluteIndexedX1 +lbl7Dmod4b: ADC16 + NEXTOPCODE +Op7EM0mod4: +lbl7Emod4a: AbsoluteIndexedX1 +lbl7Emod4b: ROR16 + NEXTOPCODE +Op7FM0mod4: +lbl7Fmod4a: AbsoluteLongIndexedX1 +lbl7Fmod4b: ADC16 + NEXTOPCODE +.pool +Op80mod4: +lbl80mod4: Op80 + NEXTOPCODE +Op81M0mod4: +lbl81mod4a: DirectIndexedIndirect1 +lbl81mod4b: Op81M0 + NEXTOPCODE +Op82mod4: +lbl82mod4: Op82 + NEXTOPCODE +Op83M0mod4: +lbl83mod4a: StackasmRelative +lbl83mod4b: STA16 + NEXTOPCODE +Op84X1mod4: +lbl84mod4a: Direct +lbl84mod4b: STY8 + NEXTOPCODE +Op85M0mod4: +lbl85mod4a: Direct +lbl85mod4b: STA16 + NEXTOPCODE +Op86X1mod4: +lbl86mod4a: Direct +lbl86mod4b: STX8 + NEXTOPCODE +Op87M0mod4: +lbl87mod4a: DirectIndirectLong +lbl87mod4b: STA16 + NEXTOPCODE +Op88X1mod4: +lbl88mod4: Op88X1 + NEXTOPCODE +Op89M0mod4: +lbl89mod4: Op89M0 + NEXTOPCODE +Op8AM0mod4: +lbl8Amod4: Op8AM0X1 + NEXTOPCODE +Op8Bmod4: +lbl8Bmod4: Op8B + NEXTOPCODE +Op8CX1mod4: +lbl8Cmod4a: Absolute +lbl8Cmod4b: STY8 + NEXTOPCODE +Op8DM0mod4: +lbl8Dmod4a: Absolute +lbl8Dmod4b: STA16 + NEXTOPCODE +Op8EX1mod4: +lbl8Emod4a: Absolute +lbl8Emod4b: STX8 + NEXTOPCODE +Op8FM0mod4: +lbl8Fmod4a: AbsoluteLong +lbl8Fmod4b: STA16 + NEXTOPCODE +Op90mod4: +lbl90mod4: Op90 + NEXTOPCODE +Op91M0mod4: +lbl91mod4a: DirectIndirectIndexed1 +lbl91mod4b: STA16 + NEXTOPCODE +Op92M0mod4: +lbl92mod4a: DirectIndirect +lbl92mod4b: STA16 + NEXTOPCODE +Op93M0mod4: +lbl93mod4a: StackasmRelativeIndirectIndexed1 +lbl93mod4b: STA16 + NEXTOPCODE +Op94X1mod4: +lbl94mod4a: DirectIndexedX1 +lbl94mod4b: STY8 + NEXTOPCODE +Op95M0mod4: +lbl95mod4a: DirectIndexedX1 +lbl95mod4b: STA16 + NEXTOPCODE +Op96X1mod4: +lbl96mod4a: DirectIndexedY1 +lbl96mod4b: STX8 + NEXTOPCODE +Op97M0mod4: +lbl97mod4a: DirectIndirectIndexedLong1 +lbl97mod4b: STA16 + NEXTOPCODE +Op98M0mod4: +lbl98mod4: Op98M0X1 + NEXTOPCODE +Op99M0mod4: +lbl99mod4a: AbsoluteIndexedY1 +lbl99mod4b: STA16 + NEXTOPCODE +Op9Amod4: +lbl9Amod4: Op9AX1 + NEXTOPCODE +Op9BX1mod4: +lbl9Bmod4: Op9BX1 + NEXTOPCODE +Op9CM0mod4: +lbl9Cmod4a: Absolute +lbl9Cmod4b: STZ16 + NEXTOPCODE +Op9DM0mod4: +lbl9Dmod4a: AbsoluteIndexedX1 +lbl9Dmod4b: STA16 + NEXTOPCODE +Op9EM0mod4: +lbl9Emod4: AbsoluteIndexedX1 + STZ16 + NEXTOPCODE +Op9FM0mod4: +lbl9Fmod4a: AbsoluteLongIndexedX1 +lbl9Fmod4b: STA16 + NEXTOPCODE +OpA0X1mod4: +lblA0mod4: OpA0X1 + NEXTOPCODE +OpA1M0mod4: +lblA1mod4a: DirectIndexedIndirect1 +lblA1mod4b: LDA16 + NEXTOPCODE +OpA2X1mod4: +lblA2mod4: OpA2X1 + NEXTOPCODE +OpA3M0mod4: +lblA3mod4a: StackasmRelative +lblA3mod4b: LDA16 + NEXTOPCODE +OpA4X1mod4: +lblA4mod4a: Direct +lblA4mod4b: LDY8 + NEXTOPCODE +OpA5M0mod4: +lblA5mod4a: Direct +lblA5mod4b: LDA16 + NEXTOPCODE +OpA6X1mod4: +lblA6mod4a: Direct +lblA6mod4b: LDX8 + NEXTOPCODE +OpA7M0mod4: +lblA7mod4a: DirectIndirectLong +lblA7mod4b: LDA16 + NEXTOPCODE +OpA8X1mod4: +lblA8mod4: OpA8X1M0 + NEXTOPCODE +OpA9M0mod4: +lblA9mod4: OpA9M0 + NEXTOPCODE +OpAAX1mod4: +lblAAmod4: OpAAX1M0 + NEXTOPCODE +OpABmod4: +lblABmod4: OpAB + NEXTOPCODE +OpACX1mod4: +lblACmod4a: Absolute +lblACmod4b: LDY8 + NEXTOPCODE +OpADM0mod4: +lblADmod4a: Absolute +lblADmod4b: LDA16 + NEXTOPCODE +OpAEX1mod4: +lblAEmod4a: Absolute +lblAEmod4b: LDX8 + NEXTOPCODE +OpAFM0mod4: +lblAFmod4a: AbsoluteLong +lblAFmod4b: LDA16 + NEXTOPCODE +OpB0mod4: +lblB0mod4: OpB0 + NEXTOPCODE +OpB1M0mod4: +lblB1mod4a: DirectIndirectIndexed1 +lblB1mod4b: LDA16 + NEXTOPCODE +OpB2M0mod4: +lblB2mod4a: DirectIndirect +lblB2mod4b: LDA16 + NEXTOPCODE +OpB3M0mod4: +lblB3mod4a: StackasmRelativeIndirectIndexed1 +lblB3mod4b: LDA16 + NEXTOPCODE +OpB4X1mod4: +lblB4mod4a: DirectIndexedX1 +lblB4mod4b: LDY8 + NEXTOPCODE +OpB5M0mod4: +lblB5mod4a: DirectIndexedX1 +lblB5mod4b: LDA16 + NEXTOPCODE +OpB6X1mod4: +lblB6mod4a: DirectIndexedY1 +lblB6mod4b: LDX8 + NEXTOPCODE +OpB7M0mod4: +lblB7mod4a: DirectIndirectIndexedLong1 +lblB7mod4b: LDA16 + NEXTOPCODE +OpB8mod4: +lblB8mod4: OpB8 + NEXTOPCODE +OpB9M0mod4: +lblB9mod4a: AbsoluteIndexedY1 +lblB9mod4b: LDA16 + NEXTOPCODE +OpBAX1mod4: +lblBAmod4: OpBAX1 + NEXTOPCODE +OpBBX1mod4: +lblBBmod4: OpBBX1 + NEXTOPCODE +OpBCX1mod4: +lblBCmod4a: AbsoluteIndexedX1 +lblBCmod4b: LDY8 + NEXTOPCODE +OpBDM0mod4: +lblBDmod4a: AbsoluteIndexedX1 +lblBDmod4b: LDA16 + NEXTOPCODE +OpBEX1mod4: +lblBEmod4a: AbsoluteIndexedY1 +lblBEmod4b: LDX8 + NEXTOPCODE +OpBFM0mod4: +lblBFmod4a: AbsoluteLongIndexedX1 +lblBFmod4b: LDA16 + NEXTOPCODE +OpC0X1mod4: +lblC0mod4: OpC0X1 + NEXTOPCODE +OpC1M0mod4: +lblC1mod4a: DirectIndexedIndirect1 +lblC1mod4b: CMP16 + NEXTOPCODE +OpC2mod4: +lblC2mod4: OpC2 + NEXTOPCODE +.pool +OpC3M0mod4: +lblC3mod4a: StackasmRelative +lblC3mod4b: CMP16 + NEXTOPCODE +OpC4X1mod4: +lblC4mod4a: Direct +lblC4mod4b: CMY8 + NEXTOPCODE +OpC5M0mod4: +lblC5mod4a: Direct +lblC5mod4b: CMP16 + NEXTOPCODE +OpC6M0mod4: +lblC6mod4a: Direct +lblC6mod4b: DEC16 + NEXTOPCODE +OpC7M0mod4: +lblC7mod4a: DirectIndirectLong +lblC7mod4b: CMP16 + NEXTOPCODE +OpC8X1mod4: +lblC8mod4: OpC8X1 + NEXTOPCODE +OpC9M0mod4: +lblC9mod4: OpC9M0 + NEXTOPCODE +OpCAX1mod4: +lblCAmod4: OpCAX1 + NEXTOPCODE +OpCBmod4: +lblCBmod4: OpCB + NEXTOPCODE +OpCCX1mod4: +lblCCmod4a: Absolute +lblCCmod4b: CMY8 + NEXTOPCODE +OpCDM0mod4: +lblCDmod4a: Absolute +lblCDmod4b: CMP16 + NEXTOPCODE +OpCEM0mod4: +lblCEmod4a: Absolute +lblCEmod4b: DEC16 + NEXTOPCODE +OpCFM0mod4: +lblCFmod4a: AbsoluteLong +lblCFmod4b: CMP16 + NEXTOPCODE +OpD0mod4: +lblD0mod4: OpD0 + NEXTOPCODE +OpD1M0mod4: +lblD1mod4a: DirectIndirectIndexed1 +lblD1mod4b: CMP16 + + NEXTOPCODE +OpD2M0mod4: +lblD2mod4a: DirectIndirect +lblD2mod4b: CMP16 + NEXTOPCODE +OpD3M0mod4: +lblD3mod4a: StackasmRelativeIndirectIndexed1 +lblD3mod4b: CMP16 + NEXTOPCODE +OpD4mod4: +lblD4mod4: OpD4 + NEXTOPCODE +OpD5M0mod4: +lblD5mod4a: DirectIndexedX1 +lblD5mod4b: CMP16 + NEXTOPCODE +OpD6M0mod4: +lblD6mod4a: DirectIndexedX1 +lblD6mod4b: DEC16 + NEXTOPCODE +OpD7M0mod4: +lblD7mod4a: DirectIndirectIndexedLong1 +lblD7mod4b: CMP16 + NEXTOPCODE +OpD8mod4: +lblD8mod4: OpD8 + NEXTOPCODE +OpD9M0mod4: +lblD9mod4a: AbsoluteIndexedY1 +lblD9mod4b: CMP16 + NEXTOPCODE +OpDAX1mod4: +lblDAmod4: OpDAX1 + NEXTOPCODE +OpDBmod4: +lblDBmod4: OpDB + NEXTOPCODE +OpDCmod4: +lblDCmod4: OpDC + NEXTOPCODE +OpDDM0mod4: +lblDDmod4a: AbsoluteIndexedX1 +lblDDmod4b: CMP16 + NEXTOPCODE +OpDEM0mod4: +lblDEmod4a: AbsoluteIndexedX1 +lblDEmod4b: DEC16 + NEXTOPCODE +OpDFM0mod4: +lblDFmod4a: AbsoluteLongIndexedX1 +lblDFmod4b: CMP16 + NEXTOPCODE +OpE0X1mod4: +lblE0mod4: OpE0X1 + NEXTOPCODE +OpE1M0mod4: +lblE1mod4a: DirectIndexedIndirect1 +lblE1mod4b: SBC16 + NEXTOPCODE +OpE2mod4: +lblE2mod4: OpE2 + NEXTOPCODE +.pool +OpE3M0mod4: +lblE3mod4a: StackasmRelative +lblE3mod4b: SBC16 + NEXTOPCODE +OpE4X1mod4: +lblE4mod4a: Direct +lblE4mod4b: CMX8 + NEXTOPCODE +OpE5M0mod4: +lblE5mod4a: Direct +lblE5mod4b: SBC16 + NEXTOPCODE +OpE6M0mod4: +lblE6mod4a: Direct +lblE6mod4b: INC16 + NEXTOPCODE +OpE7M0mod4: +lblE7mod4a: DirectIndirectLong +lblE7mod4b: SBC16 + NEXTOPCODE +OpE8X1mod4: +lblE8mod4: OpE8X1 + NEXTOPCODE +OpE9M0mod4: +lblE9mod4a: Immediate16 +lblE9mod4b: SBC16 + NEXTOPCODE +OpEAmod4: +lblEAmod4: OpEA + NEXTOPCODE +OpEBmod4: +lblEBmod4: OpEBM0 + NEXTOPCODE +OpECX1mod4: +lblECmod4a: Absolute +lblECmod4b: CMX8 + NEXTOPCODE +OpEDM0mod4: +lblEDmod4a: Absolute +lblEDmod4b: SBC16 + NEXTOPCODE +OpEEM0mod4: +lblEEmod4a: Absolute +lblEEmod4b: INC16 + NEXTOPCODE +OpEFM0mod4: +lblEFmod4a: AbsoluteLong +lblEFmod4b: SBC16 + NEXTOPCODE +OpF0mod4: +lblF0mod4: OpF0 + NEXTOPCODE +OpF1M0mod4: +lblF1mod4a: DirectIndirectIndexed1 +lblF1mod4b: SBC16 + NEXTOPCODE +OpF2M0mod4: +lblF2mod4a: DirectIndirect +lblF2mod4b: SBC16 + NEXTOPCODE +OpF3M0mod4: +lblF3mod4a: StackasmRelativeIndirectIndexed1 +lblF3mod4b: SBC16 + NEXTOPCODE +OpF4mod4: +lblF4mod4: OpF4 + NEXTOPCODE +OpF5M0mod4: +lblF5mod4a: DirectIndexedX1 +lblF5mod4b: SBC16 + NEXTOPCODE +OpF6M0mod4: +lblF6mod4a: DirectIndexedX1 +lblF6mod4b: INC16 + NEXTOPCODE +OpF7M0mod4: +lblF7mod4a: DirectIndirectIndexedLong1 +lblF7mod4b: SBC16 + NEXTOPCODE +OpF8mod4: +lblF8mod4: OpF8 + NEXTOPCODE +OpF9M0mod4: +lblF9mod4a: AbsoluteIndexedY1 +lblF9mod4b: SBC16 + NEXTOPCODE +OpFAX1mod4: +lblFAmod4: OpFAX1 + NEXTOPCODE +OpFBmod4: +lblFBmod4: OpFB + NEXTOPCODE +OpFCmod4: +lblFCmod4: OpFCX1 + NEXTOPCODE +OpFDM0mod4: +lblFDmod4a: AbsoluteIndexedX1 +lblFDmod4b: SBC16 + NEXTOPCODE +OpFEM0mod4: +lblFEmod4a: AbsoluteIndexedX1 +lblFEmod4b: INC16 + NEXTOPCODE +OpFFM0mod4: +lblFFmod4a: AbsoluteLongIndexedX1 +lblFFmod4b: SBC16 + NEXTOPCODE + + + .pool + diff --git a/src/os9x_65c816_common.s b/src/os9x_65c816_common.s new file mode 100644 index 0000000..e4230fa --- /dev/null +++ b/src/os9x_65c816_common.s @@ -0,0 +1,949 @@ +/**************************************************************** + DEFINES +****************************************************************/ + +.equ MAP_LAST, 12 + +rstatus .req R4 @ format : 0xff800000 +reg_d_bank .req R4 @ format : 0x000000ll +reg_a .req R5 @ format : 0xhhll0000 or 0xll000000 +reg_d .req R6 @ format : 0xhhll0000 +reg_p_bank .req R6 @ format : 0x000000ll +reg_x .req R7 @ format : 0xhhll0000 or 0xll000000 +reg_s .req R8 @ format : 0x0000hhll +reg_y .req R9 @ format : 0xhhll0000 or 0xll000000 + +rpc .req R10 @ 32bits address +reg_cycles .req R11 @ 32bits counter +regpcbase .req R12 @ 32bits address + +rscratch .req R0 @ format : 0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD +regopcode .req R0 @ format : 0x000000ll +rscratch2 .req R1 @ format : 0xhhll for calculation and value +rscratch3 .req R2 @ +rscratch4 .req R3 @ ?????? + +@ used for SBC opcode +rscratch9 .req R10 @ ?????? + +reg_cpu_var .req R14 + + + +@ not used +@ R13 @ Pointer 32 bit on a struct. + +@ R15 = pc (sic!) + + +/* +.equ Carry 1 +.equ Zero 2 +.equ IRQ 4 +.equ Decimal 8 +.equ IndexFlag 16 +.equ MemoryFlag 32 +.equ Overflow 64 +.equ Negative 128 +.equ Emulation 256*/ + +.equ STATUS_SHIFTER, 24 +.equ MASK_APU_EXECUTING,(1<<(STATUS_SHIFTER-4)) +.equ MASK_SHUTDOWN, (1<<(STATUS_SHIFTER-3)) +.equ MASK_BRANCHSKIP, (1<<(STATUS_SHIFTER-2)) +.equ MASK_EMUL, (1<<(STATUS_SHIFTER-1)) +.equ MASK_SHIFTER_CARRY, (STATUS_SHIFTER+1) +.equ MASK_CARRY, (1<<(STATUS_SHIFTER)) @ 0 +.equ MASK_ZERO, (2<<(STATUS_SHIFTER)) @ 1 +.equ MASK_IRQ, (4<<(STATUS_SHIFTER)) @ 2 +.equ MASK_DECIMAL, (8<<(STATUS_SHIFTER)) @ 3 +.equ MASK_INDEX, (16<<(STATUS_SHIFTER)) @ 4 @ 1 +.equ MASK_MEM, (32<<(STATUS_SHIFTER)) @ 5 @ 2 +.equ MASK_OVERFLOW, (64<<(STATUS_SHIFTER)) @ 6 @ 4 +.equ MASK_NEG, (128<<(STATUS_SHIFTER))@ 7 @ 8 + +.equ ONE_CYCLE, 6 +.equ SLOW_ONE_CYCLE, 8 +.equ NOSA1, 1 + +.equ NMI_FLAG, (1 << 7) +.equ IRQ_PENDING_FLAG, (1 << 11) +.equ SCAN_KEYS_FLAG, (1 << 4) + + +.equ MEMMAP_BLOCK_SIZE, (0x1000) +.equ MEMMAP_SHIFT, 12 +.equ MEMMAP_MASK, (0xFFF) + +.equ MEMSPEED_MASK, (0xF0000) +.equ MEMSPEED_SHIFT, 16 + +/**************************************************************** + MACROS +****************************************************************/ + +@ #include "os9x_65c816_mac_gen.h" +/*****************************************************************/ +/* Offset in SCPUState structure */ +/*****************************************************************/ +.equ Flags_ofs, 0 +.equ BranchSkip_ofs, 4 +.equ NMIActive_ofs, 5 +.equ IRQActive_ofs, 6 +.equ WaitingForInterrupt_ofs, 7 + +.equ RPB_ofs, 8 +.equ RDB_ofs, 9 +.equ RP_ofs, 10 +.equ RA_ofs, 12 +.equ RAH_ofs, 13 +.equ RD_ofs, 14 +.equ RX_ofs, 16 +.equ RS_ofs, 18 +.equ RY_ofs, 20 +@.equ RPC_ofs, 22 + +.equ PC_ofs, 24 +.equ Cycles_ofs, 28 +.equ PCBase_ofs, 32 + +.equ PCAtOpcodeStart_ofs, 36 +.equ WaitAddress_ofs, 40 +.equ WaitCounter_ofs, 44 +.equ NextEvent_ofs, 48 +.equ V_Counter_ofs, 52 +.equ MemSpeed_ofs, 56 +.equ MemSpeedx2_ofs, 60 +.equ FastROMSpeed_ofs, 64 +.equ AutoSaveTimer_ofs, 68 +.equ NMITriggerPoint_ofs, 72 +.equ NMICycleCount_ofs, 76 +.equ IRQCycleCount_ofs, 80 + +.equ InDMA_ofs, 84 +.equ WhichEvent, 85 +.equ SRAMModified_ofs, 86 +.equ BRKTriggered_ofs, 87 +.equ asm_OPTABLE_ofs, 88 +.equ TriedInterleavedMode2_ofs, 92 + +.equ Map_ofs, 96 +.equ WriteMap_ofs, 100 +.equ MemorySpeed_ofs, 104 +.equ BlockIsRAM_ofs, 108 +.equ SRAM, 112 +.equ BWRAM, 116 +.equ SRAMMask, 120 + +.equ APUExecuting_ofs, 124 + +.equ PALMOS_R9_ofs, 132 +.equ PALMOS_R10_ofs, 136 + +@ notaz +.equ APU_Cycles, 140 + +.equ DSPGet_ofs, 144 +.equ DSPSet_ofs, 148 +.equ rstatus_ofs, 152 + +/*****************************************************************/ +/* Offset in CMemory structure */ +/*****************************************************************/ +.equ _sram, 12 +.equ _bwram, 16 +.equ _fillram, 20 +.equ _c4ram, 24 + +/*****************************************************************/ + +/* prepare */ +.macro PREPARE_C_CALL + STMFD R13!,{R12,R14} +.endm +.macro PREPARE_C_CALL_R0 + STMFD R13!,{R0,R12,R14} +.endm +.macro PREPARE_C_CALL_R0R1 + STMFD R13!,{R0,R1,R12,R14} +.endm +.macro PREPARE_C_CALL_LIGHT + STMFD R13!,{R14} +.endm +.macro PREPARE_C_CALL_LIGHTR12 + STMFD R13!,{R12,R14} +.endm +/* restore */ +.macro RESTORE_C_CALL + LDMFD R13!,{R12,R14} +.endm +.macro RESTORE_C_CALL_R0 + LDMFD R13!,{R0,R12,R14} +.endm +.macro RESTORE_C_CALL_R1 + LDMFD R13!,{R1,R12,R14} +.endm +.macro RESTORE_C_CALL_LIGHT + LDMFD R13!,{R14} +.endm +.macro RESTORE_C_CALL_LIGHTR12 + LDMFD R13!,{R12,R14} +.endm + + +@ -------------- + +.macro LOAD_REGS + @ notaz + add r0,reg_cpu_var,#8 + ldmia r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase} + @ rstatus (P) & reg_d_bank + mov reg_d_bank,r1,lsl #16 + mov reg_d_bank,reg_d_bank,lsr #24 + mov r0,r1,lsr #16 + orrs rstatus, rstatus, r0,lsl #STATUS_SHIFTER @ 24 + @ if Carry set, then EMULATION bit was set + orrcs rstatus,rstatus,#MASK_EMUL + @ reg_d & reg_p_bank + mov reg_d,reg_a,lsr #16 + mov reg_d,reg_d,lsl #8 + orr reg_d,reg_d,r1,lsl #24 + mov reg_d,reg_d,ror #24 @ 0xdddd00pb + @ reg_x, reg_s + mov reg_s,reg_x,lsr #16 + @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits) + tst rstatus,#MASK_INDEX + movne reg_x,reg_x,lsl #24 + movne reg_y,reg_y,lsl #24 + moveq reg_x,reg_x,lsl #16 + moveq reg_y,reg_y,lsl #16 + tst rstatus,#MASK_MEM + movne reg_a,reg_a,lsl #24 + moveq reg_a,reg_a,lsl #16 + + @-- load MemSpeed into rstatus + ldr r0, [reg_cpu_var, #MemSpeed_ofs] + bic rstatus, rstatus, #MEMSPEED_MASK + orr rstatus, rstatus, r0, lsl #MEMSPEED_SHIFT + + @-- load BranchSpkip into rstatus + ldrb r0, [reg_cpu_var, #BranchSkip_ofs] + movs r0, r0 + biceq rstatus, rstatus, #MASK_BRANCHSKIP + orrne rstatus, rstatus, #MASK_BRANCHSKIP + + @-- load Shutdown + ldr r0, [reg_cpu_var, #WaitAddress_ofs] + movs r0, r0 + biceq rstatus, rstatus, #MASK_SHUTDOWN + orrne rstatus, rstatus, #MASK_SHUTDOWN + + +/* + @ reg_d & reg_p_bank share the same register + LDRB reg_p_bank,[reg_cpu_var,#RPB_ofs] + LDRH rscratch,[reg_cpu_var,#RD_ofs] + ORR reg_d,reg_d,rscratch, LSL #16 + @ rstatus & reg_d_bank share the same register + LDRB reg_d_bank,[reg_cpu_var,#RDB_ofs] + LDRH rscratch,[reg_cpu_var,#RP_ofs] + ORRS rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER @ 24 + @ if Carry set, then EMULATION bit was set + ORRCS rstatus,rstatus,#MASK_EMUL + @ + LDRH reg_a,[reg_cpu_var,#RA_ofs] + LDRH reg_x,[reg_cpu_var,#RX_ofs] + LDRH reg_y,[reg_cpu_var,#RY_ofs] + LDRH reg_s,[reg_cpu_var,#RS_ofs] + @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits) + TST rstatus,#MASK_INDEX + MOVNE reg_x,reg_x,LSL #24 + MOVNE reg_y,reg_y,LSL #24 + MOVEQ reg_x,reg_x,LSL #16 + MOVEQ reg_y,reg_y,LSL #16 + TST rstatus,#MASK_MEM + MOVNE reg_a,reg_a,LSL #24 + MOVEQ reg_a,reg_a,LSL #16 + + LDR regpcbase,[reg_cpu_var,#PCBase_ofs] + LDR rpc,[reg_cpu_var,#PC_ofs] + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] +*/ +.endm + + +.macro SAVE_REGS + @-- Save Shutdown flag + tst rstatus, #MASK_BRANCHSKIP + moveq r0, #0 + movne r0, #1 + str r0, [reg_cpu_var, #WaitAddress_ofs] + + @-- Save BranchSkip flag + tst rstatus, #MASK_BRANCHSKIP + moveq r0, #0 + movne r0, #1 + strb r0, [reg_cpu_var, #BranchSkip_ofs] + + @-- Save MemSpeed2x for compatibility with other cores + ldr r0, [reg_cpu_var, #MemSpeed_ofs] + mov r0, r0, lsl #1 + str r0, [reg_cpu_var, #MemSpeedx2_ofs] + + @ notaz + @ reg_p_bank, reg_d_bank and rstatus + mov r1, rstatus, lsr #16 + orr r1, r1, reg_p_bank, lsl #24 + movs r1, r1, lsr #8 + orrcs r1, r1, #0x100 @ EMULATION bit + orr r1, r1, reg_d_bank, lsl #24 + mov r1, r1, ror #16 + @ reg_a, reg_d + tst rstatus,#MASK_MEM + ldrneh r0, [reg_cpu_var,#RA_ofs] + bicne r0, r0,#0xFF + orrne reg_a, r0, reg_a,lsr #24 + moveq reg_a, reg_a, lsr #16 + mov reg_d, reg_d, lsr #16 + orr reg_a, reg_a, reg_d, lsl #16 + @ Shift X&Y according to the current mode (INDEX, MEMORY bits) + tst rstatus,#MASK_INDEX + movne reg_x,reg_x,LSR #24 + movne reg_y,reg_y,LSR #24 + moveq reg_x,reg_x,LSR #16 + moveq reg_y,reg_y,LSR #16 + @ reg_x, reg_s + orr reg_x, reg_x, reg_s, lsl #16 + @ store + add r0,reg_cpu_var,#8 + stmia r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase} + +/* + @ reg_d & reg_p_bank is same register + STRB reg_p_bank,[reg_cpu_var,#RPB_ofs] + MOV rscratch,reg_d, LSR #16 + STRH rscratch,[reg_cpu_var,#RD_ofs] + @ rstatus & reg_d_bank is same register + STRB reg_d_bank,[reg_cpu_var,#RDB_ofs] + MOVS rscratch, rstatus, LSR #STATUS_SHIFTER + ORRCS rscratch,rscratch,#0x100 @ EMULATION bit + STRH rscratch,[reg_cpu_var,#RP_ofs] + @ + @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits) + TST rstatus,#MASK_INDEX + MOVNE rscratch,reg_x,LSR #24 + MOVNE rscratch2,reg_y,LSR #24 + MOVEQ rscratch,reg_x,LSR #16 + MOVEQ rscratch2,reg_y,LSR #16 + STRH rscratch,[reg_cpu_var,#RX_ofs] + STRH rscratch2,[reg_cpu_var,#RY_ofs] + TST rstatus,#MASK_MEM + LDRNEH rscratch,[reg_cpu_var,#RA_ofs] + BICNE rscratch,rscratch,#0xFF + ORRNE rscratch,rscratch,reg_a,LSR #24 + MOVEQ rscratch,reg_a,LSR #16 + STRH rscratch,[reg_cpu_var,#RA_ofs] + + STRH reg_s,[reg_cpu_var,#RS_ofs] + STR regpcbase,[reg_cpu_var,#PCBase_ofs] + STR rpc,[reg_cpu_var,#PC_ofs] + + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] +*/ +.endm + +/*****************************************************************/ +.macro ADD1CYCLE + add reg_cycles,reg_cycles, #ONE_CYCLE +.endm +.macro ADD1CYCLENE + addne reg_cycles,reg_cycles, #ONE_CYCLE +.endm +.macro ADD1CYCLEEQ + addeq reg_cycles,reg_cycles, #ONE_CYCLE +.endm + +.macro ADD2CYCLE + add reg_cycles,reg_cycles, #(ONE_CYCLE*2) +.endm +.macro ADD2CYCLENE + addne reg_cycles,reg_cycles, #(ONE_CYCLE*2) +.endm +.macro ADD2CYCLE2MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + add reg_cycles,reg_cycles, #(ONE_CYCLE*2) + @add reg_cycles, reg_cycles, rscratch, LSL #1 + add reg_cycles, reg_cycles, rscratch, LSR #(MEMSPEED_SHIFT - 1) +.endm +.macro ADD2CYCLE1MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + add reg_cycles,reg_cycles, #(ONE_CYCLE*2) + @add reg_cycles, reg_cycles, rscratch + add reg_cycles, reg_cycles, rscratch, LSR #MEMSPEED_SHIFT +.endm + +.macro ADD3CYCLE + add reg_cycles,reg_cycles, #(ONE_CYCLE*3) +.endm + +.macro ADD1CYCLE1MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + add reg_cycles,reg_cycles, #ONE_CYCLE + @add reg_cycles, reg_cycles, rscratch + add reg_cycles, reg_cycles, rscratch, LSR #MEMSPEED_SHIFT +.endm + +.macro ADD1CYCLE2MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + add reg_cycles,reg_cycles, #ONE_CYCLE + @add reg_cycles, reg_cycles, rscratch, LSL #1 + add reg_cycles, reg_cycles, rscratch, LSR #(MEMSPEED_SHIFT - 1) +.endm + +.macro ADD1MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + @add reg_cycles, reg_cycles, rscratch + add reg_cycles, reg_cycles, rscratch, LSR #MEMSPEED_SHIFT +.endm + +.macro ADD2MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + @add reg_cycles, reg_cycles, rscratch, LSL #1 + add reg_cycles, reg_cycles, rscratch, LSR #(MEMSPEED_SHIFT - 1) +.endm + +.macro ADD3MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + @add reg_cycles, reg_cycles, rscratch + add reg_cycles, reg_cycles, rscratch, LSR #MEMSPEED_SHIFT + @add reg_cycles, reg_cycles, rscratch, LSL #1 + add reg_cycles, reg_cycles, rscratch, LSR #(MEMSPEED_SHIFT - 1) +.endm + +/**************/ +/*****************************************************************/ +.macro ADD1CYCLENEX x + addne reg_cycles,reg_cycles, #(ONE_CYCLE+(NOSA1*\x)) +.endm +.macro ADD1CYCLEEQX x + addeq reg_cycles,reg_cycles, #(ONE_CYCLE+(NOSA1*\x)) +.endm +.macro ADD2CYCLENEX x + addne reg_cycles,reg_cycles, #(ONE_CYCLE*2+(NOSA1*\x)) +.endm + +.macro ADD1CYCLEX x + add reg_cycles,reg_cycles, #(ONE_CYCLE+(NOSA1*\x)) +.endm +.macro ADD2CYCLEX x + add reg_cycles,reg_cycles, #(ONE_CYCLE*2+(NOSA1*\x)) +.endm +.macro ADD2CYCLE2MEMX x + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + add reg_cycles,reg_cycles, #(ONE_CYCLE*2+(NOSA1*\x)) + @add reg_cycles, reg_cycles, rscratch, LSL #1 + add reg_cycles, reg_cycles, rscratch, LSR #(MEMSPEED_SHIFT - 1) +.endm +.macro ADD2CYCLE1MEMX x + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + add reg_cycles,reg_cycles, #(ONE_CYCLE*2+(NOSA1*\x)) + @add reg_cycles, reg_cycles, rscratch + add reg_cycles, reg_cycles, rscratch, LSR #MEMSPEED_SHIFT +.endm + +.macro ADD3CYCLEX x + add reg_cycles,reg_cycles, #(ONE_CYCLE*3+(NOSA1*\x)) +.endm + +.macro ADD1CYCLE1MEMX x + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + add reg_cycles,reg_cycles, #(ONE_CYCLE+(NOSA1*\x)) + @add reg_cycles, reg_cycles, rscratch + add reg_cycles, reg_cycles, rscratch, LSR #MEMSPEED_SHIFT +.endm + +.macro ADD1CYCLE2MEMX x + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + and rscratch, rstatus, #MEMSPEED_MASK + add reg_cycles,reg_cycles, #(ONE_CYCLE+(NOSA1*\x)) + @add reg_cycles, reg_cycles, rscratch, LSL #1 + add reg_cycles, reg_cycles, rscratch, LSR #(MEMSPEED_SHIFT - 1) +.endm + +/**************/ + +.macro ClearDecimal + BIC rstatus,rstatus,#MASK_DECIMAL +.endm +.macro SetDecimal + ORR rstatus,rstatus,#MASK_DECIMAL +.endm +.macro SetIRQ + ORR rstatus,rstatus,#MASK_IRQ +.endm +.macro ClearIRQ + BIC rstatus,rstatus,#MASK_IRQ +.endm + +.macro CPUShutdown +@ if (Settings.Shutdown && CPU.PC == CPU.WaitAddress) + tst rstatus, #MASK_SHUTDOWN + beq 5431f + LDR rscratch,[reg_cpu_var,#WaitAddress_ofs] + CMP rpc,rscratch + BNE 5431f +@ if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG))) + LDR rscratch,[reg_cpu_var,#Flags_ofs] + LDR rscratch2,[reg_cpu_var,#WaitCounter_ofs] + TST rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG) + @BNE 5432f + @MOVS rscratch2,rscratch2 + MOVEQS rscratch2,rscratch2 + BNE 5432f +@ CPU.WaitAddress = NULL; + @MOV rscratch,#0 + @STR rscratch,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN +@ if (Settings.SA1) +@ S9xSA1ExecuteDuringSleep (); : TODO + +@ CPU.Cycles = CPU.NextEvent; + LDR reg_cycles,[reg_cpu_var,#NextEvent_ofs] + @LDR r0,[reg_cpu_var,#APUExecuting_ofs] + @MOVS r0,r0 + @BEQ 5431f +@ if (IAPU.APUExecuting) +/* { + ICPU.CPUExecuting = FALSE; + do + { + APU_EXECUTE1(); + } while (APU.Cycles < CPU.NextEvent); + ICPU.CPUExecuting = TRUE; + } + */ + asmAPU_EXECUTE2 + B 5431f +@.pool +5432: +/* else + if (CPU.WaitCounter >= 2) + CPU.WaitCounter = 1; + else + CPU.WaitCounter--; +*/ + CMP rscratch2,#1 + MOVHI rscratch2,#1 + @SUBLS rscratch2,rscratch2,#1 + MOVLS rscratch2,#0 + STR rscratch2,[reg_cpu_var,#WaitCounter_ofs] +5431: + +.endm +.macro BranchCheck0 + /*in rsctach : OpAddress + /*destroy rscratch2*/ + tst rstatus, #MASK_BRANCHSKIP + @beq 1110f + bicne rstatus, rstatus, #MASK_BRANCHSKIP + subne rscratch2, rpc, regpcbase + cmpne rscratch2, rscratch + bhi 1111f + + @LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + @MOVS rscratch2,rscratch2 + @BEQ 1110f + @MOV rscratch2,#0 + @STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + @SUB rscratch2,rpc,regpcbase + @ if( CPU.PC - CPU.PCBase > OpAddress) return; + @CMP rscratch2,rscratch + @BHI 1111f +1110: +.endm +.macro BranchCheck1 + /*in rsctach : OpAddress + /*destroy rscratch2*/ + tst rstatus, #MASK_BRANCHSKIP + @beq 1110f + bicne rstatus, rstatus, #MASK_BRANCHSKIP + subne rscratch2, rpc, regpcbase + cmpne rscratch2, rscratch + bhi 1111f + + @LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + @MOVS rscratch2,rscratch2 + @BEQ 1110f + @MOV rscratch2,#0 + @STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + @SUB rscratch2,rpc,regpcbase + @ if( CPU.PC - CPU.PCBase > OpAddress) return; + @CMP rscratch2,rscratch + @BHI 1111f +1110: +.endm +.macro BranchCheck2 + /*in rsctach : OpAddress + /*destroy rscratch2*/ + tst rstatus, #MASK_BRANCHSKIP + @beq 1110f + bicne rstatus, rstatus, #MASK_BRANCHSKIP + subne rscratch2, rpc, regpcbase + cmpne rscratch2, rscratch + bhi 1111f + + @LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + @MOVS rscratch2,rscratch2 + @BEQ 1110f + @MOV rscratch2,#0 + @STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + @SUB rscratch2,rpc,regpcbase + @ if( CPU.PC - CPU.PCBase > OpAddress) return; + @CMP rscratch2,rscratch + @BHI 1111f + 1110: +.endm + +.macro S9xSetPCBase + @ in : rscratch (0x00hhmmll) + @PREPARE_C_CALL + @BL asm_S9xSetPCBase + @RESTORE_C_CALL + @LDR rpc,[reg_cpu_var,#PC_ofs] + @LDR regpcbase,[reg_cpu_var,#PCBase_ofs] + mov r3, pc @ r3 = return address + b asmS9xSetPCBase + @return address +.endm + +.macro S9xFixCycles + TST rstatus,#MASK_EMUL + LDRNE rscratch, = jumptable1 @ Mode 0 : M=1,X=1 + BNE 991111f + @ EMULATION=0 + TST rstatus,#MASK_MEM + BEQ 991112f + @ MEMORY=1 + TST rstatus,#MASK_INDEX + @ INDEX=1 @ Mode 0 : M=1,X=1 + LDRNE rscratch, = jumptable1 + @ INDEX=0 @ Mode 1 : M=1,X=0 + LDREQ rscratch, = jumptable2 + B 991111f +991112: @ MEMORY=0 + TST rstatus,#MASK_INDEX + @ INDEX=1 @ Mode 3 : M=0,X=1 + LDRNE rscratch, = jumptable4 + @ INDEX=0 @ Mode 2 : M=0,X=0 + LDREQ rscratch, = jumptable3 +991111: + STR rscratch,[reg_cpu_var,#asm_OPTABLE_ofs] +.endm +/* +.macro S9xOpcode_NMI + SAVE_REGS + PREPARE_C_CALL_LIGHT + BL asm_S9xOpcode_NMI + RESTORE_C_CALL_LIGHT + LOAD_REGS +.endm +.macro S9xOpcode_IRQ + SAVE_REGS + PREPARE_C_CALL_LIGHT + BL asm_S9xOpcode_IRQ + RESTORE_C_CALL_LIGHT + LOAD_REGS +.endm +*/ +@--> +.macro S9xDoHBlankProcessing + SAVE_REGS + PREPARE_C_CALL_LIGHT +@ BL asm_S9xDoHBlankProcessing + BL S9xDoHBlankProcessing @ let's go straight to number one + RESTORE_C_CALL_LIGHT + LOAD_REGS +.endm + +/********************************/ +.macro EXEC_OP + LDR R1,[reg_cpu_var,#asm_OPTABLE_ofs] + STR rpc,[reg_cpu_var,#PCAtOpcodeStart_ofs] + @ADD1MEM + @ldr r3, [reg_cpu_var, #MemSpeed_ofs] + ldrb r0, [rpc], #1 + @add reg_cycles, reg_cycles, r3 + and r3, rstatus, #MEMSPEED_MASK + add reg_cycles, reg_cycles, r3, lsr #MEMSPEED_SHIFT + + @LDRB R0, [rpc], #1 + + LDR PC, [R1,R0, LSL #2] +.endm +.macro NEXTOPCODE + LDR rscratch,[reg_cpu_var,#NextEvent_ofs] + CMP reg_cycles,rscratch + BLT mainLoop + S9xDoHBlankProcessing + B mainLoop + .pool +.endm + +@ #include "os9x_65c816_mac_mem.h" +.macro S9xGetWord + @ in : rscratch (0x00hhmmll) + @ out : rscratch (0xhhll0000) + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 + MOV R0, R0, LSL #16 +.endm +.macro S9xGetWordLow + @ in : rscratch (0x00hhmmll) + @ out : rscratch (0x0000hhll) + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 +.endm +.macro S9xGetWordRegStatus reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xhhll0000) + @ flags have to be updated with read value + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 + MOVS \reg, R0, LSL #16 +.endm +.macro S9xGetWordRegNS reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xhhll0000) + @ DOES NOT DESTROY rscratch (R0) + STMFD R13!,{R0} + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 + MOV \reg, R0, LSL #16 + LDMFD R13!,{R0} +.endm +.macro S9xGetWordLowRegNS reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xhhll0000) + @ DOES NOT DESTROY rscratch (R0) + STMFD R13!,{R0} + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 + MOV \reg, R0 + LDMFD R13!,{R0} +.endm + +.macro S9xGetByte + @ in : rscratch (0x00hhmmll) + @ out : rscratch (0xll000000) + STMFD R13!,{PC} @ Push return address + B asmS9xGetByte + MOV R0,R0 + MOV R0, R0, LSL #24 +.endm +.macro S9xGetByteLow + @ in : rscratch (0x00hhmmll) + @ out : rscratch (0x000000ll) + STMFD R13!,{PC} + B asmS9xGetByte + MOV R0,R0 +.endm +.macro S9xGetByteRegStatus reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xll000000) + @ flags have to be updated with read value + STMFD R13!,{PC} @ Push return address + B asmS9xGetByte + MOV R0,R0 + MOVS \reg, R0, LSL #24 +.endm +.macro S9xGetByteRegNS reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xll000000) + @ DOES NOT DESTROY rscratch (R0) + STMFD R13!,{R0} + STMFD R13!,{PC} @ Push return address + B asmS9xGetByte + MOV R0,R0 + MOVS \reg, R0, LSL #24 + LDMFD R13!,{R0} +.endm +.macro S9xGetByteLowRegNS reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0x000000ll) + @ DOES NOT DESTROY rscratch (R0) + STMFD R13!,{R0} + STMFD R13!,{PC} @ Push return address + B asmS9xGetByte + MOV R0,R0 + MOVS \reg, R0 + LDMFD R13!,{R0} +.endm + +.macro S9xSetWord regValue + @ in : regValue (0xhhll0000) + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,\regValue, LSR #16 + B asmS9xSetWord + MOV R0,R0 +.endm +.macro S9xSetWordZero + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,#0 + B asmS9xSetWord + MOV R0,R0 +.endm +.macro S9xSetWordLow regValue + @ in : regValue (0x0000hhll) + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,\regValue + B asmS9xSetWord + MOV R0,R0 +.endm +.macro S9xSetByte regValue + @ in : regValue (0xll000000) + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,\regValue, LSR #24 + B asmS9xSetByte + MOV R0,R0 +.endm +.macro S9xSetByteZero + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,#0 + B asmS9xSetByte + MOV R0,R0 +.endm +.macro S9xSetByteLow regValue + @ in : regValue (0x000000ll) + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,\regValue + B asmS9xSetByte + MOV R0,R0 +.endm + +.macro doMainLoop + @ save registers + STMFD R13!,{R4-R11,LR} + @ init pointer to CPUvar structure + MOV reg_cpu_var,R0 + @ init registers + LOAD_REGS + @ get cpu mode from flag and init jump table + S9xFixCycles + +mainLoop: + @ APU Execute + asmAPU_EXECUTE + + @ Test Flags + LDR rscratch,[reg_cpu_var,#Flags_ofs] + MOVS rscratch,rscratch + BNE CPUFlags_set @ If flags => check for irq/nmi/scan_keys... + + EXEC_OP @ Execute next opcode + +CPUFlags_set: @ Check flags (!=0) + TST rscratch,#NMI_FLAG @ Check NMI + BEQ CPUFlagsNMI_FLAG_cleared + LDR rscratch2,[reg_cpu_var,#NMICycleCount_ofs] + SUBS rscratch2,rscratch2,#1 + STR rscratch2,[reg_cpu_var,#NMICycleCount_ofs] + BNE CPUFlagsNMI_FLAG_cleared + BIC rscratch,rscratch,#NMI_FLAG + STR rscratch,[reg_cpu_var,#Flags_ofs] + LDRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs] + MOVS rscratch2,rscratch2 + BEQ NotCPUaitingForInterruptNMI + MOV rscratch2,#0 + ADD rpc,rpc,#1 + STRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs] +NotCPUaitingForInterruptNMI: + S9xOpcode_NMI + LDR rscratch,[reg_cpu_var,#Flags_ofs] +CPUFlagsNMI_FLAG_cleared: + TST rscratch,#IRQ_PENDING_FLAG @ Check IRQ_PENDING_FLAG + BEQ CPUFlagsIRQ_PENDING_FLAG_cleared + LDR rscratch2,[reg_cpu_var,#IRQCycleCount_ofs] + MOVS rscratch2,rscratch2 + BNE CPUIRQCycleCount_NotZero + LDRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs] + MOVS rscratch2,rscratch2 + BEQ NotCPUaitingForInterruptIRQ + MOV rscratch2,#0 + ADD rpc,rpc,#1 + STRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs] +NotCPUaitingForInterruptIRQ: + LDRB rscratch2,[reg_cpu_var,#IRQActive_ofs] + MOVS rscratch2,rscratch2 + BEQ CPUIRQActive_cleared + TST rstatus,#MASK_IRQ + BNE CPUFlagsIRQ_PENDING_FLAG_cleared + S9xOpcode_IRQ + LDR rscratch,[reg_cpu_var,#Flags_ofs] + B CPUFlagsIRQ_PENDING_FLAG_cleared +CPUIRQActive_cleared: + BIC rscratch,rscratch,#IRQ_PENDING_FLAG + STR rscratch,[reg_cpu_var,#Flags_ofs] + B CPUFlagsIRQ_PENDING_FLAG_cleared +CPUIRQCycleCount_NotZero: + SUB rscratch2,rscratch2,#1 + STR rscratch2,[reg_cpu_var,#IRQCycleCount_ofs] +CPUFlagsIRQ_PENDING_FLAG_cleared: + + TST rscratch,#SCAN_KEYS_FLAG @ Check SCAN_KEYS_FLAG + BNE endmainLoop + + EXEC_OP @ Execute next opcode + +endmainLoop: + + /*Registers.PC = CPU.PC - CPU.PCBase; + S9xPackStatus (); + APURegisters.PC = IAPU.PC - IAPU.RAM; + S9xAPUPackStatus (); + + if (CPU.Flags & SCAN_KEYS_FLAG) + { + S9xSyncSpeed (); + CPU.Flags &= ~SCAN_KEYS_FLAG; + } */ +/********end*/ + SAVE_REGS + LDMFD R13!,{R4-R11,pc} + /*MOV PC,LR*/ + /*bx lr*/ + +.endm + +.macro doTestOpcode + @ save registers + STMFD R13!,{R4-R11,LR} + @ init pointer to CPUvar structure + MOV reg_cpu_var,R0 + @ init registers + LOAD_REGS + @ get cpu mode from flag and init jump table + S9xFixCycles + + EXEC_OP +.endm diff --git a/src/os9x_65c816_def.h b/src/os9x_65c816_def.h new file mode 100644 index 0000000..a078bca --- /dev/null +++ b/src/os9x_65c816_def.h @@ -0,0 +1,76 @@ +//#define __PALMOS__ + +//#define __TESTING__ + +#define MAP_LAST 12 + +#define regA R11 //format : 0xhhll0000 or 0xll000000 +#define rstatus R4 //format : 0xff800000 +#define regDBank R4 //format : 0x000000ll +#define regX R5 //format : 0xhhll0000 or 0xll000000 +#define regY R6 //format : 0xhhll0000 or 0xll000000 + +#define rpc R7 //32bits address +#define regD R8 //format : 0xhhll0000 +#define regPBank R8 //format : 0x000000ll +#define regCycles R9 //32bits counter +#define regS R10 //format : 0x0000hhll + +#define rscratch R0 //format : 0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD +#define regopcode R0 //format : 0x000000ll +#define rscratch2 R1 //format : 0xhhll for calculation and value +#define rscratch3 R2 // +#define rscratch4 R3 //?????? + + +#define rscratch5 R5 //?????? +#define rscratch6 R6 //?????? +#define rscratch7 R8 //?????? +#define rscratch8 R9 //?????? +#define rscratch9 R10 //?????? + +#define regpcbase R12 //32bits address + +#define regCPUvar R14 + + + +//not used +//R13 //Pointer 32 bit on a struct. + +//R15 = pc (sic!) + + +/*#define Carry 1 +#define Zero 2 +#define IRQ 4 +#define Decimal 8 +#define IndexFlag 16 +#define MemoryFlag 32 +#define Overflow 64 +#define Negative 128 +#define Emulation 256*/ + +#define STATUS_SHIFTER 24 +#define MASK_EMUL (1<<(STATUS_SHIFTER-1)) +#define MASK_SHIFTER_CARRY (STATUS_SHIFTER+1) +#define MASK_CARRY (1<<(STATUS_SHIFTER)) //0 +#define MASK_ZERO (2<<(STATUS_SHIFTER)) //1 +#define MASK_IRQ (4<<(STATUS_SHIFTER)) //2 +#define MASK_DECIMAL (8<<(STATUS_SHIFTER)) //3 +#define MASK_INDEX (16<<(STATUS_SHIFTER)) //4 //1 +#define MASK_MEM (32<<(STATUS_SHIFTER)) //5 //2 +#define MASK_OVERFLOW (64<<(STATUS_SHIFTER)) //6 //4 +#define MASK_NEG (128<<(STATUS_SHIFTER))//7 //8 + +#define ONE_CYCLE 6 +#define SLOW_ONE_CYCLE 8 + +#define NMI_FLAG (1 << 7) +#define IRQ_PENDING_FLAG (1 << 11) +#define SCAN_KEYS_FLAG (1 << 4) + + +#define MEMMAP_BLOCK_SIZE (0x1000) +#define MEMMAP_SHIFT 12 +#define MEMMAP_MASK (0xFFF) diff --git a/src/os9x_65c816_global.s b/src/os9x_65c816_global.s new file mode 100644 index 0000000..ac6daee --- /dev/null +++ b/src/os9x_65c816_global.s @@ -0,0 +1,1126 @@ + .DATA + .align 4 + .include "os9x_65c816_common.s" + +.globl asmS9xGetByte +.globl asmS9xGetWord +.globl asmS9xSetByte +.globl asmS9xSetWord +.globl asmS9xSetPCBase +@ input: r0 : address +@ return: rpc, regpcbase +@ uint8 asmS9xSetPCBase(uint32 address); +asmS9xSetPCBase: + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + mov r1, r0, lsr #MEMMAP_SHIFT + + + @ R2 <= Map[block] (GetAddress) + ldr r2, [reg_cpu_var, #Map_ofs] + bic r1, r1, #0xFF000 + + ldr regpcbase, [r2, r1, lsl #2] + bic r0, r0, #0xff0000 @ Address & 0xffff + + cmp regpcbase, #MAP_LAST + blo SPCBSpecial + + ldr r2, [reg_cpu_var, #MemorySpeed_ofs] + bic rstatus, rstatus, #MEMSPEED_MASK + ldr r1, [r2, r1, lsl #2] + add rpc, regpcbase, r0 + str r1, [reg_cpu_var, #MemSpeed_ofs] + orr rstatus, rstatus, r1, lsl #MEMSPEED_SHIFT + + bx r3 + + +SPCBSpecial: + + ldr pc, [pc, regpcbase, lsl #2] + mov r0, r0 @ nop, for align + .long SPCB_PPU + .long SPCB_CPU + .long SPCB_DSP + .long SPCB_LOROM_SRAM + .long SPCB_HIROM_SRAM + .long SPCB_LOROM_SRAM + .long SPCB_LOROM_SRAM + .long SPCB_C4 + .long SPCB_BWRAM + .long SPCB_LOROM_SRAM + .long SPCB_LOROM_SRAM + .long SPCB_LOROM_SRAM +/* + MAP_PPU 0 + MAP_CPU 1 + MAP_DSP 2 + MAP_LOROM_SRAM 3 + MAP_HIROM_SRAM 4 + MAP_NONE 5 + MAP_DEBUG 6 + MAP_C4 7 + MAP_BWRAM 8 + MAP_BWRAM_BITMAP 9 + MAP_BWRAM_BITMAP2 10 + MAP_SA1RAM 11 + MAP_LAST 12 +*/ + +vMemory: + .word Memory + +SPCB_PPU: + @CPU.PCBase = Memory.FillRAM - 0x2000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_fillram] + + sub regpcbase, regpcbase, #0x2000 + add rpc, regpcbase, r0 + + mov r0, #ONE_CYCLE + bic rstatus, rstatus, #MEMSPEED_MASK + str r0, [reg_cpu_var, #MemSpeed_ofs] + orr rstatus, rstatus, r0, lsl #MEMSPEED_SHIFT + + @return; + bx r3 + @------------------- + +SPCB_CPU: + @CPU.PCBase = Memory.FillRAM - 0x4000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_fillram] + + sub regpcbase, regpcbase, #0x4000 + add rpc, regpcbase, r0 + + mov r0, #ONE_CYCLE + bic rstatus, rstatus, #MEMSPEED_MASK + str r0, [reg_cpu_var, #MemSpeed_ofs] + orr rstatus, rstatus, r0, lsl #MEMSPEED_SHIFT + + @return; + bx r3 + @------------------- + +SPCB_DSP: + @CPU.PCBase = Memory.FillRAM - 0x6000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_fillram] + + sub regpcbase, regpcbase, #0x6000 + add rpc, regpcbase, r0 + + mov r0, #SLOW_ONE_CYCLE + bic rstatus, rstatus, #MEMSPEED_MASK + str r0, [reg_cpu_var, #MemSpeed_ofs] + orr rstatus, rstatus, r0, lsl #MEMSPEED_SHIFT + + @return; + bx r3 + @------------------- + +SPCB_LOROM_SRAM: + @CPU.PCBase = Memory.SRAM; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_sram] + + add rpc, regpcbase, r0 + + mov r0, #SLOW_ONE_CYCLE + bic rstatus, rstatus, #MEMSPEED_MASK + str r0, [reg_cpu_var, #MemSpeed_ofs] + orr rstatus, rstatus, r0, lsl #MEMSPEED_SHIFT + + @return; + bx r3 + @------------------- + +SPCB_HIROM_SRAM: + @CPU.PCBase = Memory.SRAM - 0x6000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_sram] + + sub regpcbase, regpcbase, #0x6000 + add rpc, regpcbase, r0 + + mov r0, #SLOW_ONE_CYCLE + bic rstatus, rstatus, #MEMSPEED_MASK + str r0, [reg_cpu_var, #MemSpeed_ofs] + orr rstatus, rstatus, r0, lsl #MEMSPEED_SHIFT + + @return; + bx r3 + @------------------- + +SPCB_C4: + @CPU.PCBase = Memory.C4RAM - 0x6000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + ldr r1, vMemory + ldr regpcbase, [r1, #_c4ram] + + sub regpcbase, regpcbase, #0x6000 + add rpc, regpcbase, r0 + + mov r0, #SLOW_ONE_CYCLE + bic rstatus, rstatus, #MEMSPEED_MASK + str r0, [reg_cpu_var, #MemSpeed_ofs] + orr rstatus, rstatus, r0, lsl #MEMSPEED_SHIFT + + @return; + bx r3 + @------------------- + +SPCB_BWRAM: + @CPU.PCBase = Memory.BWRAM - 0x6000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + ldr r1, vMemory + ldr regpcbase, [r1, #_bwram] + + sub regpcbase, regpcbase, #0x6000 + add rpc, regpcbase, r0 + + mov r0, #SLOW_ONE_CYCLE + bic rstatus, rstatus, #MEMSPEED_MASK + str r0, [reg_cpu_var, #MemSpeed_ofs] + orr rstatus, rstatus, r0, lsl #MEMSPEED_SHIFT + + @return; + bx r3 + @------------------- + + +@ uint8 aaS9xGetByte(uint32 address); +asmS9xGetByte: + @ in : R0 = 0x00hhmmll + @ out : R0 = 0x000000ll + @ DESTROYED : R1,R2,R3 + @ UPDATE : reg_cycles + @ R1 <= block + MOV R1,R0,LSR #MEMMAP_SHIFT + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + BIC R1,R1,#0xFF000 + @ R2 <= Map[block] (GetAddress) + LDR R2,[reg_cpu_var,#Map_ofs] + LDR R2,[R2,R1,LSL #2] + CMP R2,#MAP_LAST + BLO GBSpecial @ special + @ Direct ROM/RAM acess + @ R2 <= GetAddress + Address & 0xFFFF + @ R3 <= MemorySpeed[block] + LDR R3,[reg_cpu_var,#MemorySpeed_ofs] + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + LDR R3,[R3,R1, lsl #2] + @ADD R2,R2,R0,LSR #16 + add r2, r2, r0 + @ Update CPU.Cycles + ADD reg_cycles,reg_cycles,R3 + @ R3 = BlockIsRAM[block] + LDR R3,[reg_cpu_var,#BlockIsRAM_ofs] + @ Get value to return + LDRB R3,[R3,R1] + LDRB R0,[R2] + MOVS R3,R3 + @ if BlockIsRAM => update for CPUShutdown + LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs] + orrne rstatus, rstatus, #MASK_SHUTDOWN + STRNE R1,[reg_cpu_var,#WaitAddress_ofs] + + + LDMFD R13!,{PC} @ Return +GBSpecial: + + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 @ nop, for align + .long GBPPU + .long GBCPU + .long GBDSP + .long GBLSRAM + .long GBHSRAM + .long GBNONE + .long GBDEBUG + .long GBC4 + .long GBBWRAM + .long GBNONE + .long GBNONE + .long GBNONE + /*.long GB7ROM + .long GB7RAM + .long GB7SRM*/ +GBPPU: + @ InDMA ? + LDRB R1,[reg_cpu_var,#InDMA_ofs] + @MOV R0,R0,LSL #16 @ S9xGetPPU(Address&0xFFFF); + bic r0, r0, #0xff0000 + MOVS R1,R1 + ADDEQ reg_cycles,reg_cycles,#ONE_CYCLE @ No -> update Cycles + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + + str rstatus, [reg_cpu_var, #rstatus_ofs] + PREPARE_C_CALL + BL S9xGetPPU + RESTORE_C_CALL + ldr rstatus, [reg_cpu_var, #rstatus_ofs] + + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GBCPU: + ADD reg_cycles,reg_cycles,#ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF); + bic r0, r0, #0xff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetCPU + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return + +GBDSP: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF); + bic r0, r0, #0x0ff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + + ldr reg_cycles, [reg_cpu_var, #DSPGet_ofs] + PREPARE_C_CALL + blx reg_cycles + @BL S9xGetDSP + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GBLSRAM: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + LDR R2,[reg_cpu_var,#SRAMMask] + LDR R1,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + LDRB R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} +GB7SRM: +GBHSRAM: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + + MOV R1,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R1,R1,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R0,R2,R1 + LDR R2,[reg_cpu_var,#SRAMMask] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDR R1,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + LDRB R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} @ return +GB7ROM: +GB7RAM: +GBNONE: + MOV R0,R0,LSR #8 + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + AND R0,R0,#0xFF + LDMFD R13!,{PC} +@ GBDEBUG: + /*ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + MOV R0,#0 + LDMFD R13!,{PC}*/ +GBC4: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF); + bic r0, r0, #0xff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetC4 + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GBDEBUG: +GBBWRAM: + MOV R0,R0,LSL #17 + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + MOV R0,R0,LSR #17 @ Address&0x7FFF + LDR R1,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + LDRB R0,[R0,R1] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + LDMFD R13!,{PC} + + +@ uint16 aaS9xGetWord(uint32 address); +asmS9xGetWord: + @ in : R0 = 0x00hhmmll + @ out : R0 = 0x000000ll + @ DESTROYED : R1,R2,R3 + @ UPDATE : reg_cycles + + + MOV R1,R0,LSL #19 + ADDS R1,R1,#0x80000 + @ if = 0x1FFF => 0 + BNE GW_NotBoundary + + STMFD R13!,{R0} + STMFD R13!,{PC} + B asmS9xGetByte + MOV R0,R0 + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + STMFD R13!,{PC} + B asmS9xGetByte + MOV R0,R0 + LDMFD R13!,{R1} + ORR R0,R1,R0,LSL #8 + LDMFD R13!,{PC} + +GW_NotBoundary: + + @ R1 <= block + MOV R1,R0,LSR #MEMMAP_SHIFT + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + BIC R1,R1,#0xFF000 + @ R2 <= Map[block] (GetAddress) + LDR R2,[reg_cpu_var,#Map_ofs] + LDR R2,[R2,R1,LSL #2] + CMP R2,#MAP_LAST + BLO GWSpecial @ special + @ Direct ROM/RAM acess + + TST R0,#1 + BNE GW_Not_Aligned1 + @ R2 <= GetAddress + Address & 0xFFFF + @ R3 <= MemorySpeed[block] + LDR R3,[reg_cpu_var,#MemorySpeed_ofs] + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + LDR R3,[R3,R1, lsl #2] + @MOV R0,R0,LSR #16 + @ Update CPU.Cycles + ADD reg_cycles,reg_cycles,R3, LSL #1 + @ R3 = BlockIsRAM[block] + LDR R3,[reg_cpu_var,#BlockIsRAM_ofs] + @ Get value to return + LDRH R0,[R2,R0] + LDRB R3,[R3,R1] + MOVS R3,R3 + @ if BlockIsRAM => update for CPUShutdown + LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs] + orrne rstatus, rstatus, #MASK_SHUTDOWN + STRNE R1,[reg_cpu_var,#WaitAddress_ofs] + + LDMFD R13!,{PC} @ Return +GW_Not_Aligned1: + + MOV R0,R0,LSL #16 + ADD R3,R0,#0x10000 + LDRB R3,[R2,R3,LSR #16] @ GetAddress+ (Address+1)&0xFFFF + LDRB R0,[R2,R0,LSR #16] @ GetAddress+ Address&0xFFFF + ORR R0,R0,R3,LSL #8 + + @ if BlockIsRAM => update for CPUShutdown + LDR R3,[reg_cpu_var,#BlockIsRAM_ofs] + LDR R2,[reg_cpu_var,#MemorySpeed_ofs] + LDRB R3,[R3,R1] @ R3 = BlockIsRAM[block] + LDR R2,[R2,R1, lsl #2] @ R2 <= MemorySpeed[block] + MOVS R3,R3 @ IsRAM ? CPUShutdown stuff + LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs] + orrne rstatus, rstatus, #MASK_SHUTDOWN + STRNE R1,[reg_cpu_var,#WaitAddress_ofs] + ADD reg_cycles,reg_cycles,R2, LSL #1 @ Update CPU.Cycles + LDMFD R13!,{PC} @ Return +GWSpecial: + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 @ nop, for align + .long GWPPU + .long GWCPU + .long GWDSP + .long GWLSRAM + .long GWHSRAM + .long GWNONE + .long GWDEBUG + .long GWC4 + .long GWBWRAM + .long GWNONE + .long GWNONE + .long GWNONE + /*.long GW7ROM + .long GW7RAM + .long GW7SRM*/ +/* MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM, + MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP, + MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/ + +GWPPU: + @ InDMA ? + LDRB R1,[reg_cpu_var,#InDMA_ofs] + @MOV R0,R0,LSL #16 @ S9xGetPPU(Address&0xFFFF); + bic r0, r0, #0xff0000 + MOVS R1,R1 + ADDEQ reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ No -> update Cycles + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + + str rstatus, [reg_cpu_var, #rstatus_ofs] + PREPARE_C_CALL_R0 + BL S9xGetPPU + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + @ BIC R0,R0,#0x10000 + BL S9xGetPPU + RESTORE_C_CALL_R1 + ldr rstatus, [reg_cpu_var, #rstatus_ofs] + + ORR R0,R1,R0,LSL #8 + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GWCPU: + ADD reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF); + bic r0, r0, #0xff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + PREPARE_C_CALL_R0 + BL S9xGetCPU + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + @ BIC R0,R0,#0x10000 + BL S9xGetCPU + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GWDSP: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF); + bic r0, r0, #0x0ff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + + ldr reg_cycles, [reg_cpu_var, #DSPGet_ofs] + PREPARE_C_CALL_R0 + blx reg_cycles + @BL S9xGetDSP + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + @ BIC R0,R0,#0x10000 + @BL S9xGetDSP + blx reg_cycles + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GWLSRAM: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + + TST R0,#1 + BNE GW_Not_Aligned2 + LDR R2,[reg_cpu_var,#SRAMMask] + LDR R1,[reg_cpu_var,#SRAM] + AND R3,R2,R0 @ Address&SRAMMask + LDRH R0,[R3,R1] @ *Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} @ return +GW_Not_Aligned2: + LDR R2,[reg_cpu_var,#SRAMMask] + LDR R1,[reg_cpu_var,#SRAM] + AND R3,R2,R0 @ Address&SRAMMask + ADD R0,R0,#1 + AND R2,R0,R2 @ Address&SRAMMask + LDRB R3,[R1,R3] @ *Memory.SRAM + Address&SRAMMask + LDRB R2,[R1,R2] @ *Memory.SRAM + Address&SRAMMask + ORR R0,R3,R2,LSL #8 + LDMFD R13!,{PC} @ return +GW7SRM: +GWHSRAM: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + + TST R0,#1 + BNE GW_Not_Aligned3 + + MOV R1,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R1,R1,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R0,R2,R1 + LDR R2,[reg_cpu_var,#SRAMMask] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + + LDR R1,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + LDRH R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} @ return + +GW_Not_Aligned3: + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R2,R2,R3 + ADD R0,R0,#1 + SUB R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + MOV R3,R0,LSL #17 + AND R0,R0,#0xF0000 + MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF + MOV R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3) + ADD R0,R0,R3 + LDR R3,[reg_cpu_var,#SRAMMask] @ reload mask + SUB R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3)) + AND R2,R3,R2 @ Address...&SRAMMask + AND R0,R3,R0 @ (Address+1...)&SRAMMask + + LDR R3,[reg_cpu_var,#SRAM] + LDRB R0,[R0,R3] @ *Memory.SRAM + (Address...)&SRAMMask + LDRB R2,[R2,R3] @ *Memory.SRAM + (Address+1...)&SRAMMask + ORR R0,R2,R0,LSL #8 + + LDMFD R13!,{PC} @ return +GW7ROM: +GW7RAM: +GWNONE: + MOV R0,R0,LSL #16 + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + MOV R0,R0,LSR #24 + ORR R0,R0,R0,LSL #8 + LDMFD R13!,{PC} +GWDEBUG: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + MOV R0,#0 + LDMFD R13!,{PC} +GWC4: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF); + bic r0, r0, #0xff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + PREPARE_C_CALL_R0 + BL S9xGetC4 + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + @ BIC R0,R0,#0x10000 + BL S9xGetC4 + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GWBWRAM: + TST R0,#1 + BNE GW_Not_Aligned4 + MOV R0,R0,LSL #17 + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + MOV R0,R0,LSR #17 @ Address&0x7FFF + LDR R1,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + LDRH R0,[R1,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + LDMFD R13!,{PC} @ return +GW_Not_Aligned4: + MOV R0,R0,LSL #17 + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + ADD R3,R0,#0x20000 + MOV R0,R0,LSR #17 @ Address&0x7FFF + MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF + LDR R1,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + SUB R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000) + LDRB R0,[R1,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + LDRB R3,[R1,R3] @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000) + ORR R0,R0,R3,LSL #8 + LDMFD R13!,{PC} @ return + + + + +@ void aaS9xSetByte(uint32 address,uint8 val); +asmS9xSetByte: + @ in : R0=0x00hhmmll R1=0x000000ll + @ DESTROYED : R0,R1,R2,R3 + @ UPDATE : reg_cycles + @ cpu shutdown + @MOV R2,#0 + @STR R2,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + + @ + + @ R3 <= block + MOV R3,R0,LSR #MEMMAP_SHIFT + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + BIC R3,R3,#0xFF000 + @ R2 <= Map[block] (SetAddress) + LDR R2,[reg_cpu_var,#WriteMap_ofs] + LDR R2,[R2,R3,LSL #2] + CMP R2,#MAP_LAST + BLO SBSpecial @ special + @ Direct ROM/RAM acess + + @ R2 <= SetAddress + Address & 0xFFFF + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + @ADD R2,R2,R0,LSR #16 + add r2, r2, r0 + LDR R0,[reg_cpu_var,#MemorySpeed_ofs] + @ Set byte + STRB R1,[R2] + @ R0 <= MemorySpeed[block] + LDR R0,[R0,R3, lsl #2] + @ Update CPU.Cycles + ADD reg_cycles,reg_cycles,R0 + @ CPUShutdown + @ only SA1 here : TODO + @ Return + LDMFD R13!,{PC} +SBSpecial: + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 @ nop, for align + .long SBPPU + .long SBCPU + .long SBDSP + .long SBLSRAM + .long SBHSRAM + .long SBNONE + .long SBDEBUG + .long SBC4 + .long SBBWRAM + .long SBNONE + .long SBNONE + .long SBNONE + /*.long SB7ROM + .long SB7RAM + .long SB7SRM*/ +SBPPU: + @ InDMA ? + LDRB R2,[reg_cpu_var,#InDMA_ofs] + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + MOVS R2,R2 + ADDEQ reg_cycles,reg_cycles,#ONE_CYCLE @ No -> update Cycles + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetPPU + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SBCPU: + ADD reg_cycles,reg_cycles,#ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetCPU + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SBDSP: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 + bic r0, r0, #0x0ff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + ldr reg_cycles, [reg_cpu_var, #DSPSet_ofs] + MOV R1,R12 + blx reg_cycles + @BL S9xSetDSP + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SBLSRAM: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + LDR R2,[reg_cpu_var,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} @ return if SRAMMask=0 + LDR R3,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SB7SRM: +SBHSRAM: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R0,R2,R3 + + LDR R2,[reg_cpu_var,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} @ return if SRAMMask=0 + + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDR R3,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SB7ROM: +SB7RAM: +SBNONE: +SBDEBUG: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + LDMFD R13!,{PC} +SBC4: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetC4 + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SBBWRAM: + MOV R0,R0,LSL #17 + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + MOV R0,R0,LSR #17 @ Address&0x7FFF + LDR R2,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + STRB R1,[R0,R2] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + + LDMFD R13!,{PC} + + + +@ void aaS9xSetWord(uint32 address,uint16 val); +asmS9xSetWord: + @ in : R0 = 0x00hhmmll R1=0x0000hhll + @ DESTROYED : R0,R1,R2,R3 + @ UPDATE : reg_cycles + @ R1 <= block + + MOV R2,R0,LSL #19 + ADDS R2,R2,#0x80000 + @ if = 0x1FFF => 0 + BNE SW_NotBoundary + + STMFD R13!,{R0,R1} + STMFD R13!,{PC} + B asmS9xSetByte + MOV R0,R0 + LDMFD R13!,{R0,R1} + ADD R0,R0,#1 + MOV R1,R1,LSR #8 + STMFD R13!,{PC} + B asmS9xSetByte + MOV R0,R0 + + LDMFD R13!,{PC} + +SW_NotBoundary: + + @MOV R2,#0 + @STR R2,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + + @ + @ R3 <= block + MOV R3,R0,LSR #MEMMAP_SHIFT + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + BIC R3,R3,#0xFF000 + @ R2 <= Map[block] (SetAddress) + LDR R2,[reg_cpu_var,#WriteMap_ofs] + LDR R2,[R2,R3,LSL #2] + CMP R2,#MAP_LAST + BLO SWSpecial @ special + @ Direct ROM/RAM acess + + + @ check if address is 16bits aligned or not + TST R0,#1 + BNE SW_not_aligned1 + @ aligned + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + @ADD R2,R2,R0,LSR #16 @ address & 0xFFFF + SetAddress + add r2, r2, r0 + LDR R0,[reg_cpu_var,#MemorySpeed_ofs] + @ Set word + STRH R1,[R2] + @ R1 <= MemorySpeed[block] + LDR R0,[R0,R3, lsl #2] + @ Update CPU.Cycles + ADD reg_cycles,reg_cycles,R0, LSL #1 + @ CPUShutdown + @ only SA1 here : TODO + @ Return + LDMFD R13!,{PC} + +SW_not_aligned1: + @ R1 = (Address&0xFFFF)<<16 + MOV R0,R0,LSL #16 + @ First write @address + STRB R1,[R2,R0,LSR #16] + ADD R0,R0,#0x10000 + MOV R1,R1,LSR #8 + @ Second write @address+1 + STRB R1,[R2,R0,LSR #16] + @ R1 <= MemorySpeed[block] + LDR R0,[reg_cpu_var,#MemorySpeed_ofs] + LDR R0,[R0,R3, lsl #2] + @ Update CPU.Cycles + ADD reg_cycles,reg_cycles,R0,LSL #1 + @ CPUShutdown + @ only SA1 here : TODO + @ Return + LDMFD R13!,{PC} +SWSpecial: + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 @ nop, for align + .long SWPPU + .long SWCPU + .long SWDSP + .long SWLSRAM + .long SWHSRAM + .long SWNONE + .long SWDEBUG + .long SWC4 + .long SWBWRAM + .long SWNONE + .long SWNONE + .long SWNONE + /*.long SW7ROM + .long SW7RAM + .long SW7SRM*/ +SWPPU: + @ InDMA ? + LDRB R2,[reg_cpu_var,#InDMA_ofs] + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + MOVS R2,R2 + ADDEQ reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ No -> update Cycles + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetPPU + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetPPU + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SWCPU: + ADD reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ update Cycles + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetCPU + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetCPU + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SWDSP: + ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 + bic r0, r0, #0x0ff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + ldr reg_cycles, [reg_cpu_var, #DSPSet_ofs] + PREPARE_C_CALL_R0R1 + blx reg_cycles + @BL S9xSetDSP + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + blx reg_cycles + @BL S9xSetDSP + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SWLSRAM: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + LDR R2,[reg_cpu_var,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} @ return if SRAMMask=0 + + AND R3,R2,R0 @ Address&SRAMMask + TST R0,#1 + BNE SW_not_aligned2 + @ aligned + LDR R0,[reg_cpu_var,#SRAM] + STRH R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW_not_aligned2: + + ADD R0,R0,#1 + AND R2,R2,R0 @ (Address+1)&SRAMMask + LDR R0,[reg_cpu_var,#SRAM] + STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + MOV R1,R1,LSR #8 + STRB R1,[R0,R2] @ *Memory.SRAM + (Address+1)&SRAMMask + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW7SRM: +SWHSRAM: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + + LDR R2,[reg_cpu_var,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} @ return if SRAMMask=0 + + TST R0,#1 + BNE SW_not_aligned3 + @ aligned + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R0,R2,R3 + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDR R2,[reg_cpu_var,#SRAMMask] + LDR R3,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + STRH R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW_not_aligned3: + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R2,R2,R3 + SUB R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + + ADD R0,R0,#1 + MOV R3,R0,LSL #17 + AND R0,R0,#0xF0000 + MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF + MOV R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3) + ADD R0,R0,R3 + LDR R3,[reg_cpu_var,#SRAMMask] @ reload mask + SUB R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3)) + AND R2,R3,R2 @ Address...&SRAMMask + AND R0,R3,R0 @ (Address+1...)&SRAMMask + + LDR R3,[reg_cpu_var,#SRAM] + STRB R1,[R2,R3] @ *Memory.SRAM + (Address...)&SRAMMask + MOV R1,R1,LSR #8 + STRB R1,[R0,R3] @ *Memory.SRAM + (Address+1...)&SRAMMask + + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW7ROM: +SW7RAM: +SWNONE: +SWDEBUG: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + LDMFD R13!,{PC} @ return +SWC4: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + @MOV R0,R0,LSL #16 + bic r0, r0, #0xff0000 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetC4 + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetC4 + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SWBWRAM: + ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + TST R0,#1 + BNE SW_not_aligned4 + @ aligned + MOV R0,R0,LSL #17 + LDR R2,[reg_cpu_var,#BWRAM] + MOV R0,R0,LSR #17 @ Address&0x7FFF + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + MOV R3,#1 + STRH R1,[R0,R2] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + STRB R3,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW_not_aligned4: + MOV R0,R0,LSL #17 + ADD R3,R0,#0x20000 + MOV R0,R0,LSR #17 @ Address&0x7FFF + MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF + LDR R2,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + SUB R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000) + STRB R1,[R2,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + MOV R1,R1,LSR #8 + STRB R1,[R2,R3] @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000) + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return + + + + + diff --git a/src/os9x_65c816_global_armv4.s b/src/os9x_65c816_global_armv4.s new file mode 100644 index 0000000..13fa1e2 --- /dev/null +++ b/src/os9x_65c816_global_armv4.s @@ -0,0 +1,6 @@ +.macro blx reg + mov lr, pc + mov pc, \reg +.endm + +.include "os9x_65c816_global.s" diff --git a/src/os9x_65c816_mac_gen.h b/src/os9x_65c816_mac_gen.h new file mode 100644 index 0000000..eaeddc9 --- /dev/null +++ b/src/os9x_65c816_mac_gen.h @@ -0,0 +1,595 @@ + +/*****************************************************************/ +/* Offset in SCPUState structure */ +/*****************************************************************/ +#define Flags_ofs 0 +#define BranchSkip_ofs 4 +#define NMIActive_ofs 5 +#define IRQActive_ofs 6 +#define WaitingForInterrupt_ofs 7 +#define InDMA_ofs 8 +#define WhichEvent 9 +#define SRAMModified_ofs 10 +#define BRKTriggered_ofs 11 +#define PC_ofs 12 +#define PCBase_ofs 16 + +#define PCAtOpcodeStart_ofs 20 + +#define WaitAddress_ofs 24 + +#define WaitCounter_ofs 28 +#define Cycles_ofs 32 +#define NextEvent_ofs 36 +#define V_Counter_ofs 40 +#define MemSpeed_ofs 44 +#define MemSpeedx2_ofs 48 +#define FastROMSpeed_ofs 52 +#define AutoSaveTimer_ofs 56 +#define NMITriggerPoint_ofs 60 +#define NMICycleCount_ofs 64 +#define IRQCycleCount_ofs 68 + +#define RPB_ofs 72 +#define RDB_ofs 73 +#define RP_ofs 74 +#define RA_ofs 76 +#define RAH_ofs RA_ofs+1 +#define RD_ofs 78 +#define RS_ofs 80 +#define RX_ofs 82 +#define RY_ofs 84 +#define RPC_ofs 86 + + +#define asm_OPTABLE_ofs 88 +#define TriedInterleavedMode2_ofs 92 + + + +#define Map_ofs 96 +#define WriteMap_ofs 100 +#define MemorySpeed_ofs 104 +#define BlockIsRAM_ofs 108 +#define SRAM 112 +#define BWRAM 116 +#define SRAMMask 120 + +#define APUExecuting_ofs 122 + +#define PALMOS_R9_ofs 124 +#define PALMOS_R10_ofs 128 +/*****************************************************************/ + + +#ifdef __PALMOS__ +/* prepare */ +.macro PREPARE_C_CALL + STMFD R13!,{R9,R10,R12,R14} + LDR R9,[regCPUvar,#PALMOS_R9_ofs] + LDR R10,[regCPUvar,#PALMOS_R10_ofs] +.endm +.macro PREPARE_C_CALL_R0 + STMFD R13!,{R0,R9,R10,R12,R14} + LDR R9,[regCPUvar,#PALMOS_R9_ofs] + LDR R10,[regCPUvar,#PALMOS_R10_ofs] +.endm +.macro PREPARE_C_CALL_R0R1 + STMFD R13!,{R0,R1,R9,R10,R12,R14} + LDR R9,[regCPUvar,#PALMOS_R9_ofs] + LDR R10,[regCPUvar,#PALMOS_R10_ofs] +.endm +.macro PREPARE_C_CALL_LIGHT + STMFD R13!,{R14} + LDR R9,[regCPUvar,#PALMOS_R9_ofs] + LDR R10,[regCPUvar,#PALMOS_R10_ofs] +.endm +.macro PREPARE_C_CALL_LIGHTR12 + STMFD R13!,{R9,R10,R12,R14} + LDR R9,[regCPUvar,#PALMOS_R9_ofs] + LDR R10,[regCPUvar,#PALMOS_R10_ofs] +.endm +/* restore */ +.macro RESTORE_C_CALL + LDMFD R13!,{R9,R10,R12,R14} + +.endm +.macro RESTORE_C_CALL_R0 + LDMFD R13!,{R0,R9,R10,R12,R14} +.endm +.macro RESTORE_C_CALL_R1 + LDMFD R13!,{R1,R9,R10,R12,R14} +.endm +.macro RESTORE_C_CALL_LIGHT + LDMFD R13!,{R14} +.endm +.macro RESTORE_C_CALL_LIGHTR12 + LDMFD R13!,{R9,R10,R12,R14} +.endm +#else +/* prepare */ +.macro PREPARE_C_CALL + STMFD R13!,{R12,R14} +.endm +.macro PREPARE_C_CALL_R0 + STMFD R13!,{R0,R12,R14} +.endm +.macro PREPARE_C_CALL_R0R1 + STMFD R13!,{R0,R1,R12,R14} +.endm +.macro PREPARE_C_CALL_LIGHT + STMFD R13!,{R14} +.endm +.macro PREPARE_C_CALL_LIGHTR12 + STMFD R13!,{R12,R14} +.endm +/* restore */ +.macro RESTORE_C_CALL + LDMFD R13!,{R12,R14} +.endm +.macro RESTORE_C_CALL_R0 + LDMFD R13!,{R0,R12,R14} +.endm +.macro RESTORE_C_CALL_R1 + LDMFD R13!,{R1,R12,R14} +.endm +.macro RESTORE_C_CALL_LIGHT + LDMFD R13!,{R14} +.endm +.macro RESTORE_C_CALL_LIGHTR12 + LDMFD R13!,{R12,R14} +.endm +#endif + +//-------------- +.macro LOAD_REGS + //regD & regPBank share the same register + LDRB regPBank,[regCPUvar,#RPB_ofs] + LDRH rscratch,[regCPUvar,#RD_ofs] + ORR regD,regD,rscratch, LSL #16 + //rstatus & regDBank share the same register + LDRB regDBank,[regCPUvar,#RDB_ofs] + LDRH rscratch,[regCPUvar,#RP_ofs] + ORRS rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER + //if Carry set, then EMULATION bit was set + ORRCS rstatus,rstatus,#MASK_EMUL + // + LDRH regA,[regCPUvar,#RA_ofs] + LDRH regX,[regCPUvar,#RX_ofs] + LDRH regY,[regCPUvar,#RY_ofs] + LDRH regS,[regCPUvar,#RS_ofs] + //Shift X,Y & A according to the current mode (INDEX, MEMORY bits) + TST rstatus,#MASK_INDEX + MOVNE regX,regX,LSL #24 + MOVNE regY,regY,LSL #24 + MOVEQ regX,regX,LSL #16 + MOVEQ regY,regY,LSL #16 + TST rstatus,#MASK_MEM + MOVNE regA,regA,LSL #24 + MOVEQ regA,regA,LSL #16 + + LDR regpcbase,[regCPUvar,#PCBase_ofs] + LDR rpc,[regCPUvar,#PC_ofs] + LDR regCycles,[regCPUvar,#Cycles_ofs] +.endm + + +.macro SAVE_REGS + //regD & regPBank is same register + STRB regPBank,[regCPUvar,#RPB_ofs] + MOV rscratch,regD, LSR #16 + STRH rscratch,[regCPUvar,#RD_ofs] + //rstatus & regDBank is same register + STRB regDBank,[regCPUvar,#RDB_ofs] + MOVS rscratch, rstatus, LSR #STATUS_SHIFTER + ORRCS rscratch,rscratch,#0x100 //EMULATION bit + STRH rscratch,[regCPUvar,#RP_ofs] + // + //Shift X,Y & A according to the current mode (INDEX, MEMORY bits) + TST rstatus,#MASK_INDEX + MOVNE rscratch,regX,LSR #24 + MOVNE rscratch2,regY,LSR #24 + MOVEQ rscratch,regX,LSR #16 + MOVEQ rscratch2,regY,LSR #16 + STRH rscratch,[regCPUvar,#RX_ofs] + STRH rscratch2,[regCPUvar,#RY_ofs] + TST rstatus,#MASK_MEM + LDRNEH rscratch,[regCPUvar,#RA_ofs] + BICNE rscratch,rscratch,#0xFF + ORRNE rscratch,rscratch,regA,LSR #24 + MOVEQ rscratch,regA,LSR #16 + STRH rscratch,[regCPUvar,#RA_ofs] + + STRH regS,[regCPUvar,#RS_ofs] + STR regpcbase,[regCPUvar,#PCBase_ofs] + STR rpc,[regCPUvar,#PC_ofs] + + STR regCycles,[regCPUvar,#Cycles_ofs] +.endm + +/*****************************************************************/ +.macro ADD1CYCLE + add regCycles,regCycles, #ONE_CYCLE +.endm +.macro ADD1CYCLENE + addne regCycles,regCycles, #ONE_CYCLE +.endm +.macro ADD1CYCLEEQ + addeq regCycles,regCycles, #ONE_CYCLE +.endm + +.macro ADD2CYCLE + add regCycles,regCycles, #(ONE_CYCLE*2) +.endm +.macro ADD2CYCLENE + addne regCycles,regCycles, #(ONE_CYCLE*2) +.endm +.macro ADD2CYCLE2MEM + ldr rscratch,[regCPUvar,#MemSpeed_ofs] + add regCycles,regCycles, #(ONE_CYCLE*2) + add regCycles, regCycles, rscratch, LSL #1 +.endm +.macro ADD2CYCLE1MEM + ldr rscratch,[regCPUvar,#MemSpeed_ofs] + add regCycles,regCycles, #(ONE_CYCLE*2) + add regCycles, regCycles, rscratch +.endm + +.macro ADD3CYCLE + add regCycles,regCycles, #(ONE_CYCLE*3) +.endm + +.macro ADD1CYCLE1MEM + ldr rscratch,[regCPUvar,#MemSpeed_ofs] + add regCycles,regCycles, #ONE_CYCLE + add regCycles, regCycles, rscratch +.endm + +.macro ADD1CYCLE2MEM + ldr rscratch,[regCPUvar,#MemSpeed_ofs] + add regCycles,regCycles, #ONE_CYCLE + add regCycles, regCycles, rscratch, lsl #1 +.endm + +.macro ADD1MEM + ldr rscratch,[regCPUvar,#MemSpeed_ofs] + add regCycles, regCycles, rscratch +.endm + +.macro ADD2MEM + ldr rscratch,[regCPUvar,#MemSpeed_ofs] + add regCycles, regCycles, rscratch, lsl #1 +.endm + +.macro ADD3MEM + ldr rscratch,[regCPUvar,#MemSpeed_ofs] + add regCycles, rscratch, regCycles + add regCycles, regCycles, rscratch, lsl #1 +.endm + +/**************/ +.macro ClearDecimal + BIC rstatus,rstatus,#MASK_DECIMAL +.endm +.macro SetDecimal + ORR rstatus,rstatus,#MASK_DECIMAL +.endm +.macro SetIRQ + ORR rstatus,rstatus,#MASK_IRQ +.endm +.macro ClearIRQ + BIC rstatus,rstatus,#MASK_IRQ +.endm + +.macro CPUShutdown +//if (Settings.Shutdown && CPU.PC == CPU.WaitAddress) + LDR rscratch,[regCPUvar,#WaitAddress_ofs] + CMP rpc,rscratch + BNE 5431f +//if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG))) + LDR rscratch,[regCPUvar,#Flags_ofs] + LDR rscratch2,[regCPUvar,#WaitCounter_ofs] + TST rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG) + BNE 5432f + MOVS rscratch2,rscratch2 + BNE 5432f +//CPU.WaitAddress = NULL; + MOV rscratch,#0 + STR rscratch,[regCPUvar,#WaitAddress_ofs] +//if (Settings.SA1) +// S9xSA1ExecuteDuringSleep (); : TODO + +// CPU.Cycles = CPU.NextEvent; + LDR regCycles,[regCPUvar,#NextEvent_ofs] + LDRB r0,[regCPUvar,#APUExecuting_ofs] + MOVS r0,r0 + BEQ 5431f +// if (IAPU.APUExecuting) +/* { + ICPU.CPUExecuting = FALSE; + do + { + APU_EXECUTE1(); + } while (APU.Cycles < CPU.NextEvent); + ICPU.CPUExecuting = TRUE; + } + */ + asmAPU_EXECUTE2 + B 5431f +.pool +5432: +/* else + if (CPU.WaitCounter >= 2) + CPU.WaitCounter = 1; + else + CPU.WaitCounter--; +*/ + CMP rscratch2,#1 + MOVHI rscratch2,#1 + //SUBLS rscratch2,rscratch2,#1 + MOVLS rscratch2,#0 + STR rscratch2,[regCPUvar,#WaitCounter_ofs] +5431: + +.endm +.macro BranchCheck0 + /*in rsctach : OpAddress + /*destroy rscratch2*/ + LDRB rscratch2,[regCPUvar,#BranchSkip_ofs] + MOVS rscratch2,rscratch2 + BEQ 1110f + MOV rscratch2,#0 + STRB rscratch2,[regCPUvar,#BranchSkip_ofs] + SUB rscratch2,rpc,regpcbase + //if( CPU.PC - CPU.PCBase > OpAddress) return; + CMP rscratch2,rscratch + BHI 1111f +1110: +.endm +.macro BranchCheck1 + /*in rsctach : OpAddress + /*destroy rscratch2*/ + LDRB rscratch2,[regCPUvar,#BranchSkip_ofs] + MOVS rscratch2,rscratch2 + BEQ 1110f + MOV rscratch2,#0 + STRB rscratch2,[regCPUvar,#BranchSkip_ofs] + SUB rscratch2,rpc,regpcbase + //if( CPU.PC - CPU.PCBase > OpAddress) return; + CMP rscratch2,rscratch + BHI 1111f +1110: +.endm +.macro BranchCheck2 + /*in rsctach : OpAddress + /*destroy rscratch2*/ + LDRB rscratch2,[regCPUvar,#BranchSkip_ofs] + MOVS rscratch2,rscratch2 + BEQ 1110f + MOV rscratch2,#0 + STRB rscratch2,[regCPUvar,#BranchSkip_ofs] + SUB rscratch2,rpc,regpcbase + //if( CPU.PC - CPU.PCBase > OpAddress) return; + CMP rscratch2,rscratch + BHI 1111f +1110: +.endm + +.macro S9xSetPCBase + // in : rscratch (0x00hhmmll) + PREPARE_C_CALL + BL asm_S9xSetPCBase + RESTORE_C_CALL + LDR rpc,[regCPUvar,#PC_ofs] + LDR regpcbase,[regCPUvar,#PCBase_ofs] +.endm + +.macro S9xFixCycles +#ifdef __PALMOS__ + LDR rscratch2,[regCPUvar,#PALMOS_R10_ofs] +#endif + TST rstatus,#MASK_EMUL + LDRNE rscratch, = jumptable1 //Mode 0 : M=1,X=1 + BNE 991111f + //EMULATION=0 + TST rstatus,#MASK_MEM + BEQ 991112f + //MEMORY=1 + TST rstatus,#MASK_INDEX + //INDEX=1 //Mode 0 : M=1,X=1 + LDRNE rscratch, = jumptable1 + //INDEX=0 //Mode 1 : M=1,X=0 + LDREQ rscratch, = jumptable2 + B 991111f +991112: //MEMORY=0 + TST rstatus,#MASK_INDEX + //INDEX=1 //Mode 3 : M=0,X=1 + LDRNE rscratch, = jumptable4 + //INDEX=0 //Mode 2 : M=0,X=0 + LDREQ rscratch, = jumptable3 +991111: +#ifdef __PALMOS__ + ADD rscratch,rscratch,rscratch2 +#endif + STR rscratch,[regCPUvar,#asm_OPTABLE_ofs] +.endm +.macro S9xOpcode_NMI + SAVE_REGS + PREPARE_C_CALL_LIGHT + BL asm_S9xOpcode_NMI + RESTORE_C_CALL_LIGHT + LOAD_REGS +.endm +.macro S9xOpcode_IRQ + SAVE_REGS + PREPARE_C_CALL_LIGHT + BL asm_S9xOpcode_IRQ + RESTORE_C_CALL_LIGHT + LOAD_REGS +.endm +.macro S9xDoHBlankProcessing + SAVE_REGS + PREPARE_C_CALL_LIGHT + BL asm_S9xDoHBlankProcessing + RESTORE_C_CALL_LIGHT + LOAD_REGS +.endm + +/********************************/ +.macro EXEC_OP + LDR R1,[regCPUvar,#asm_OPTABLE_ofs] + STR rpc,[regCPUvar,#PCAtOpcodeStart_ofs] + ADD1MEM + LDRB R0, [rpc], #1 + +#ifdef __PALMOS__ + LDR R2,[regCPUvar,#PALMOS_R10_ofs] + LDR R3,[R1,R0,LSL #2] + ADD PC,R2,R3 +#else + LDR PC, [R1,R0, LSL #2] +#endif +.endm +.macro NEXTOPCODE +#ifdef __TESTING__ + B endmainLoop +#endif + LDR rscratch,[regCPUvar,#NextEvent_ofs] + CMP regCycles,rscratch + BLT mainLoop + S9xDoHBlankProcessing + B mainLoop +.endm + +.macro asmAPU_EXECUTE + LDRB R0,[regCPUvar,#APUExecuting_ofs] + MOVS R0,R0 + BEQ 43210f + //SAVE_REGS + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL_LIGHTR12 + BL asm_APU_EXECUTE + RESTORE_C_CALL_LIGHTR12 + LDR regCycles,[regCPUvar,#Cycles_ofs] + //LOAD_REGS + //S9xFixCycles +43210: +.endm + +.macro asmAPU_EXECUTE2 + //SAVE_REGS + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL_LIGHTR12 + BL asm_APU_EXECUTE2 + RESTORE_C_CALL_LIGHTR12 + LDR regCycles,[regCPUvar,#Cycles_ofs] + //LOAD_REGS +.endm + + +//void asmMainLoop(asm_cpu_var_t *asmcpuPtr); +asmMainLoop: + //save registers + STMFD R13!,{R4-R11,LR} + //init pointer to CPUvar structure + MOV regCPUvar,R0 + //init registers + LOAD_REGS + //get cpu mode from flag and init jump table + S9xFixCycles +mainLoop: + //APU Execute + asmAPU_EXECUTE + + //Test Flags + LDR rscratch,[regCPUvar,#Flags_ofs] + MOVS rscratch,rscratch + BNE CPUFlags_set //If flags => check for irq/nmi/scan_keys... + + EXEC_OP //Execute next opcode + +CPUFlags_set: //Check flags (!=0) + TST rscratch,#NMI_FLAG //Check NMI + BEQ CPUFlagsNMI_FLAG_cleared + LDR rscratch2,[regCPUvar,#NMICycleCount_ofs] + SUBS rscratch2,rscratch2,#1 + STR rscratch2,[regCPUvar,#NMICycleCount_ofs] + BNE CPUFlagsNMI_FLAG_cleared + BIC rscratch,rscratch,#NMI_FLAG + STR rscratch,[regCPUvar,#Flags_ofs] + LDRB rscratch2,[regCPUvar,#WaitingForInterrupt_ofs] + MOVS rscratch2,rscratch2 + BEQ NotCPUaitingForInterruptNMI + MOV rscratch2,#0 + ADD rpc,rpc,#1 + STRB rscratch2,[regCPUvar,#WaitingForInterrupt_ofs] +NotCPUaitingForInterruptNMI: + S9xOpcode_NMI + LDR rscratch,[regCPUvar,#Flags_ofs] +CPUFlagsNMI_FLAG_cleared: + TST rscratch,#IRQ_PENDING_FLAG //Check IRQ_PENDING_FLAG + BEQ CPUFlagsIRQ_PENDING_FLAG_cleared + LDR rscratch2,[regCPUvar,#IRQCycleCount_ofs] + MOVS rscratch2,rscratch2 + BNE CPUIRQCycleCount_NotZero + LDRB rscratch2,[regCPUvar,#WaitingForInterrupt_ofs] + MOVS rscratch2,rscratch2 + BEQ NotCPUaitingForInterruptIRQ + MOV rscratch2,#0 + ADD rpc,rpc,#1 + STRB rscratch2,[regCPUvar,#WaitingForInterrupt_ofs] +NotCPUaitingForInterruptIRQ: + LDRB rscratch2,[regCPUvar,#IRQActive_ofs] + MOVS rscratch2,rscratch2 + BEQ CPUIRQActive_cleared + TST rstatus,#MASK_IRQ + BNE CPUFlagsIRQ_PENDING_FLAG_cleared + S9xOpcode_IRQ + LDR rscratch,[regCPUvar,#Flags_ofs] + B CPUFlagsIRQ_PENDING_FLAG_cleared +CPUIRQActive_cleared: + BIC rscratch,rscratch,#IRQ_PENDING_FLAG + STR rscratch,[regCPUvar,#Flags_ofs] + B CPUFlagsIRQ_PENDING_FLAG_cleared +CPUIRQCycleCount_NotZero: + SUB rscratch2,rscratch2,#1 + STR rscratch2,[regCPUvar,#IRQCycleCount_ofs] +CPUFlagsIRQ_PENDING_FLAG_cleared: + + TST rscratch,#SCAN_KEYS_FLAG //Check SCAN_KEYS_FLAG + BNE endmainLoop + + EXEC_OP //Execute next opcode + +endmainLoop: + /*Registers.PC = CPU.PC - CPU.PCBase; + S9xPackStatus (); + APURegisters.PC = IAPU.PC - IAPU.RAM; + S9xAPUPackStatus (); + + if (CPU.Flags & SCAN_KEYS_FLAG) + { + S9xSyncSpeed (); + CPU.Flags &= ~SCAN_KEYS_FLAG; + } */ +/********end*/ + SAVE_REGS + LDMFD R13!,{R4-R11,LR} + MOV PC,LR + + +.pool + +//void test_opcode(struct asm_cpu_var *asm_var); +test_opcode: + //save registers + STMFD R13!,{R4-R11,LR} + //init pointer to CPUvar structure + MOV regCPUvar,R0 + //init registers + LOAD_REGS + //get cpu mode from flag and init jump table + S9xFixCycles + + EXEC_OP +.pool diff --git a/src/os9x_65c816_mac_mem.h b/src/os9x_65c816_mac_mem.h new file mode 100644 index 0000000..c2863d8 --- /dev/null +++ b/src/os9x_65c816_mac_mem.h @@ -0,0 +1,1599 @@ +/***************************************************************** + +*****************************************************************/ + +//#define _C_GB_ +//#define _C_GW_ +//#define _C_SB_ +//#define _C_SW_ + +.macro S9xGetWord + // in : rscratch (0x00hhmmll) + // out : rscratch (0xhhll0000) +#ifdef _C_GW_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL + BL asm_S9xGetWord + RESTORE_C_CALL + MOV R0, R0, LSL #16 + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + B asmS9xGetWord + MOV R0,R0 + MOV R0, R0, LSL #16 +#endif +.endm +.macro S9xGetWordLow + // in : rscratch (0x00hhmmll) + // out : rscratch (0x0000hhll) +#ifdef _C_GW_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL + BL asm_S9xGetWord + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + B asmS9xGetWord + MOV R0,R0 +#endif +.endm +.macro S9xGetWordRegStatus reg + // in : rscratch (0x00hhmmll) + // out : reg (0xhhll0000) + // flags have to be updated with read value +#ifdef _C_GW_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL + BL asm_S9xGetWord + RESTORE_C_CALL + MOVS \reg, R0, LSL #16 + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + B asmS9xGetWord + MOV R0,R0 + MOVS \reg, R0, LSL #16 +#endif +.endm +.macro S9xGetWordRegNS reg + // in : rscratch (0x00hhmmll) + // out : reg (0xhhll0000) + // DOES NOT DESTROY rscratch (R0) +#ifdef _C_GW_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL_R0 + BL asm_S9xGetWord + MOV \reg, R0, LSL #16 + RESTORE_C_CALL_R0 + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{R0} + STMFD R13!,{PC} //Push return address + B asmS9xGetWord + MOV R0,R0 + MOV \reg, R0, LSL #16 + LDMFD R13!,{R0} +#endif +.endm +.macro S9xGetWordLowRegNS reg + // in : rscratch (0x00hhmmll) + // out : reg (0xhhll0000) + // DOES NOT DESTROY rscratch (R0) +#ifdef _C_GW_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL_R0 + BL asm_S9xGetWord + MOV \reg, R0 + RESTORE_C_CALL_R0 + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{R0} + STMFD R13!,{PC} //Push return address + B asmS9xGetWord + MOV R0,R0 + MOV \reg, R0 + LDMFD R13!,{R0} +#endif +.endm + +.macro S9xGetByte + // in : rscratch (0x00hhmmll) + // out : rscratch (0xll000000) +#ifdef _C_GB_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL + BL asm_S9xGetByte + RESTORE_C_CALL + MOV R0, R0, LSL #24 + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + B asmS9xGetByte + MOV R0,R0 + MOV R0, R0, LSL #24 +#endif +.endm +.macro S9xGetByteLow + // in : rscratch (0x00hhmmll) + // out : rscratch (0x000000ll) +#ifdef _C_GB_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL + BL asm_S9xGetByte + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} + B asmS9xGetByte + MOV R0,R0 +#endif +.endm +.macro S9xGetByteRegStatus reg + // in : rscratch (0x00hhmmll) + // out : reg (0xll000000) + // flags have to be updated with read value +#ifdef _C_GB_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL + BL asm_S9xGetByte + RESTORE_C_CALL + MOVS \reg, R0, LSL #24 + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + B asmS9xGetByte + MOV R0,R0 + MOVS \reg, R0, LSL #24 +#endif +.endm +.macro S9xGetByteRegNS reg + // in : rscratch (0x00hhmmll) + // out : reg (0xll000000) + // DOES NOT DESTROY rscratch (R0) +#ifdef _C_GB_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL_R0 + BL asm_S9xGetByte + MOV \reg, R0, LSL #24 + RESTORE_C_CALL_R0 + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{R0} + STMFD R13!,{PC} //Push return address + B asmS9xGetByte + MOV R0,R0 + MOVS \reg, R0, LSL #24 + LDMFD R13!,{R0} +#endif +.endm +.macro S9xGetByteLowRegNS reg + // in : rscratch (0x00hhmmll) + // out : reg (0x000000ll) + // DOES NOT DESTROY rscratch (R0) +#ifdef _C_GB_ + STR regCycles,[regCPUvar,#Cycles_ofs] + PREPARE_C_CALL_R0 + BL asm_S9xGetByte + MOV \reg, R0, LSL #24 + RESTORE_C_CALL_R0 + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{R0} + STMFD R13!,{PC} //Push return address + B asmS9xGetByte + MOV R0,R0 + MOVS \reg, R0 + LDMFD R13!,{R0} +#endif +.endm + +.macro S9xSetWord regValue + // in : regValue (0xhhll0000) + // in : rscratch=address (0x00hhmmll) +#ifdef _C_SW_ + STR regCycles,[regCPUvar,#Cycles_ofs] + MOV R1,\regValue, LSR #16 + PREPARE_C_CALL + BL asm_S9xSetWord + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + MOV R1,\regValue, LSR #16 + B asmS9xSetWord + MOV R0,R0 +#endif +.endm +.macro S9xSetWordZero + // in : rscratch=address (0x00hhmmll) +#ifdef _C_SW_ + STR regCycles,[regCPUvar,#Cycles_ofs] + MOV R1,#0 + PREPARE_C_CALL + BL asm_S9xSetWord + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + MOV R1,#0 + B asmS9xSetWord + MOV R0,R0 +#endif +.endm +.macro S9xSetWordLow regValue + // in : regValue (0x0000hhll) + // in : rscratch=address (0x00hhmmll) +#ifdef _C_SW_ + STR regCycles,[regCPUvar,#Cycles_ofs] + MOV R1,\regValue + PREPARE_C_CALL + BL asm_S9xSetWord + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + MOV R1,\regValue + B asmS9xSetWord + MOV R0,R0 +#endif +.endm +.macro S9xSetByte regValue + // in : regValue (0xll000000) + // in : rscratch=address (0x00hhmmll) +#ifdef _C_SB_ + STR regCycles,[regCPUvar,#Cycles_ofs] + MOV R1,\regValue, LSR #24 + PREPARE_C_CALL + BL asm_S9xSetByte + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + MOV R1,\regValue, LSR #24 + B asmS9xSetByte + MOV R0,R0 +#endif +.endm +.macro S9xSetByteZero + // in : rscratch=address (0x00hhmmll) +#ifdef _C_SB_ + STR regCycles,[regCPUvar,#Cycles_ofs] + MOV R1,#0 + PREPARE_C_CALL + BL asm_S9xSetByte + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + MOV R1,#0 + B asmS9xSetByte + MOV R0,R0 +#endif +.endm +.macro S9xSetByteLow regValue + // in : regValue (0x000000ll) + // in : rscratch=address (0x00hhmmll) +#ifdef _C_SB_ + STR regCycles,[regCPUvar,#Cycles_ofs] + MOV R1,\regValue + PREPARE_C_CALL + BL asm_S9xSetByte + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] +#else + STMFD R13!,{PC} //Push return address + MOV R1,\regValue + B asmS9xSetByte + MOV R0,R0 +#endif +.endm + + +// =========================================== +// =========================================== +// Adressing mode +// =========================================== +// =========================================== + + +.macro Absolute + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc],#2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, regDBank, LSL #16 +.endm +.macro AbsoluteIndexedIndirectX0 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ADD rscratch , regX, rscratch, LSL #16 + MOV rscratch , rscratch, LSR #16 + ORR rscratch , rscratch, regPBank, LSL #16 + S9xGetWordLow + +.endm +.macro AbsoluteIndexedIndirectX1 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ADD rscratch , rscratch, regX, LSR #24 + BIC rscratch , rscratch, #0x00FF0000 + ORR rscratch , rscratch, regPBank, LSL #16 + S9xGetWordLow + +.endm +.macro AbsoluteIndirectLong + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch, #2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 +.endm +.macro AbsoluteIndirect + ADD2MEM + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + S9xGetWordLow + ORR rscratch , rscratch, regPBank, LSL #16 +.endm +.macro AbsoluteIndexedX0 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, regDBank, LSL #16 + ADD rscratch , rscratch, regX, LSR #16 +.endm +.macro AbsoluteIndexedX1 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, regDBank, LSL #16 + ADD rscratch , rscratch, regX, LSR #24 +.endm + + +.macro AbsoluteIndexedY0 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, regDBank, LSL #16 + ADD rscratch , rscratch, regY, LSR #16 +.endm +.macro AbsoluteIndexedY1 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, regDBank, LSL #16 + ADD rscratch , rscratch, regY, LSR #24 +.endm +.macro AbsoluteLong + ADD3MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + LDRB rscratch2 , [rpc], #1 + ORR rscratch , rscratch, rscratch2, LSL #16 +.endm + + +.macro AbsoluteLongIndexedX0 + ADD3MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + LDRB rscratch2 , [rpc], #1 + ORR rscratch , rscratch, rscratch2, LSL #16 + ADD rscratch , rscratch, regX, LSR #16 + BIC rscratch, rscratch, #0xFF000000 +.endm +.macro AbsoluteLongIndexedX1 + ADD3MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + LDRB rscratch2 , [rpc], #1 + ORR rscratch , rscratch, rscratch2, LSL #16 + ADD rscratch , rscratch, regX, LSR #24 + BIC rscratch, rscratch, #0xFF000000 +.endm +.macro Direct + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , regD, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndirect + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , regD, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch , rscratch, regDBank, LSL #16 +.endm +.macro DirectIndirectLong + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , regD, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch,#2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 +.endm +.macro DirectIndirectIndexed0 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , regD, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch, rscratch,regDBank, LSL #16 + ADD rscratch, rscratch,regY, LSR #16 +.endm +.macro DirectIndirectIndexed1 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , regD, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch, rscratch,regDBank, LSL #16 + ADD rscratch, rscratch,regY, LSR #24 +.endm +.macro DirectIndirectIndexedLong0 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , regD, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch,#2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 + ADD rscratch, rscratch,regY, LSR #16 +.endm +.macro DirectIndirectIndexedLong1 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , regD, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch,#2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 + ADD rscratch, rscratch,regY, LSR #24 +.endm +.macro DirectIndexedIndirect0 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , regD , regX + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch , rscratch , regDBank, LSL #16 +.endm +.macro DirectIndexedIndirect1 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , regD , regX, LSR #8 + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch , rscratch , regDBank, LSL #16 +.endm +.macro DirectIndexedX0 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , regD , regX + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndexedX1 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , regD , regX, LSR #8 + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndexedY0 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , regD , regY + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndexedY1 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , regD , regY, LSR #8 + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro Immediate8 + ADD rscratch, rpc, regPBank, LSL #16 + SUB rscratch, rscratch, regpcbase + ADD rpc, rpc, #1 +.endm +.macro Immediate16 + ADD rscratch, rpc, regPBank, LSL #16 + SUB rscratch, rscratch, regpcbase + ADD rpc, rpc, #2 +.endm +.macro asmRelative + ADD1MEM + LDRSB rscratch , [rpc],#1 + ADD rscratch , rscratch , rpc + SUB rscratch , rscratch, regpcbase + BIC rscratch,rscratch,#0x00FF0000 + BIC rscratch,rscratch,#0xFF000000 +.endm +.macro asmRelativeLong + ADD1CYCLE2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + SUB rscratch2 , rpc, regpcbase + ADD rscratch , rscratch2, rscratch + BIC rscratch,rscratch,#0x00FF0000 +.endm + + +.macro StackasmRelative + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , rscratch, regS + BIC rscratch,rscratch,#0x00FF0000 +.endm +.macro StackasmRelativeIndirectIndexed0 + ADD2CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , rscratch, regS + BIC rscratch,rscratch,#0x00FF0000 + S9xGetWordLow + ORR rscratch , rscratch, regDBank, LSL #16 + ADD rscratch , rscratch, regY, LSR #16 + BIC rscratch, rscratch, #0xFF000000 +.endm +.macro StackasmRelativeIndirectIndexed1 + ADD2CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , rscratch, regS + BIC rscratch,rscratch,#0x00FF0000 + S9xGetWordLow + ORR rscratch , rscratch, regDBank, LSL #16 + ADD rscratch , rscratch, regY, LSR #24 + BIC rscratch, rscratch, #0xFF000000 +.endm + + +/****************************************/ +.macro PushB reg + MOV rscratch,regS + S9xSetByte \reg + SUB regS,regS,#1 +.endm +.macro PushBLow reg + MOV rscratch,regS + S9xSetByteLow \reg + SUB regS,regS,#1 +.endm +.macro PushWLow reg + SUB rscratch,regS,#1 + S9xSetWordLow \reg + SUB regS,regS,#2 +.endm +.macro PushWrLow + MOV rscratch2,rscratch + SUB rscratch,regS,#1 + S9xSetWordLow rscratch2 + SUB regS,regS,#2 +.endm +.macro PushW reg + SUB rscratch,regS,#1 + S9xSetWord \reg + SUB regS,regS,#2 +.endm + +/********/ + +.macro PullB reg + ADD rscratch,regS,#1 + S9xGetByteLow + ADD regS,regS,#1 + MOV \reg,rscratch,LSL #24 +.endm +.macro PullBr + ADD rscratch,regS,#1 + S9xGetByte + ADD regS,regS,#1 +.endm +.macro PullBLow reg + ADD rscratch,regS,#1 + S9xGetByteLow + ADD regS,regS,#1 + MOV \reg,rscratch +.endm +.macro PullBrLow + ADD rscratch,regS,#1 + S9xGetByteLow + ADD regS,regS,#1 +.endm +.macro PullW reg + ADD rscratch,regS,#1 + S9xGetWordLow + ADD regS,regS,#2 + MOV \reg,rscratch,LSL #16 +.endm + +.macro PullWLow reg + ADD rscratch,regS,#1 + S9xGetWordLow + ADD regS,regS,#2 + MOV \reg,rscratch +.endm + + +/*****************/ +.macro PullBS reg + ADD rscratch,regS,#1 + S9xGetByteLow + ADD regS,regS,#1 + MOVS \reg,rscratch,LSL #24 +.endm +.macro PullBrS + ADD rscratch,regS,#1 + S9xGetByteLow + ADD regS,regS,#1 + MOVS rscratch,rscratch,LSL #24 +.endm +.macro PullBLowS reg + ADD rscratch,regS,#1 + S9xGetByteLow + ADD regS,regS,#1 + MOVS \reg,rscratch +.endm +.macro PullBrLowS + ADD rscratch,regS,#1 + S9xGetByteLow + ADD regS,regS,#1 + MOVS rscratch,rscratch +.endm +.macro PullWS reg + ADD rscratch,regS,#1 + S9xGetWordLow + ADD regS,regS,#2 + MOVS \reg,rscratch, LSL #16 +.endm +.macro PullWrS + ADD rscratch,regS,#1 + S9xGetWordLow + ADD regS,regS,#2 + MOVS rscratch,rscratch, LSL #16 +.endm +.macro PullWLowS reg + ADD rscratch,regS,#1 + S9xGetWordLow + ADD regS,regS,#2 + MOVS \reg,rscratch +.endm +.macro PullWrLowS + ADD rscratch,regS,#1 + S9xGetWordLow + ADD regS,regS,#2 + MOVS rscratch,rscratch +.endm + + +.globl asmS9xGetByte +.globl asmS9xGetWord +.globl asmS9xSetByte +.globl asmS9xSetWord + +//uint8 aaS9xGetByte(uint32 address); +asmS9xGetByte: + // in : R0 = 0x00hhmmll + // out : R0 = 0x000000ll + // DESTROYED : R1,R2,R3 + // UPDATE : regCycles + //R1 <= block + MOV R1,R0,LSR #MEMMAP_SHIFT + //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + //R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + //so AND MEMMAP_MASK is BIC 0xFF000 + BIC R1,R1,#0xFF000 + //R2 <= Map[block] (GetAddress) + LDR R2,[regCPUvar,#Map_ofs] + LDR R2,[R2,R1,LSL #2] + CMP R2,#MAP_LAST + BLO GBSpecial //special + // Direct ROM/RAM acess + //R2 <= GetAddress + Address & 0xFFFF + //R3 <= MemorySpeed[block] + LDR R3,[regCPUvar,#MemorySpeed_ofs] + MOV R0,R0,LSL #16 + LDRB R3,[R3,R1] + ADD R2,R2,R0,LSR #16 + //Update CPU.Cycles + ADD regCycles,regCycles,R3 + //R3 = BlockIsRAM[block] + LDR R3,[regCPUvar,#BlockIsRAM_ofs] + //Get value to return + LDRB R0,[R2] + LDRB R3,[R3,R1] + MOVS R3,R3 + // if BlockIsRAM => update for CPUShutdown + LDRNE R1,[regCPUvar,#PCAtOpcodeStart_ofs] + STRNE R1,[regCPUvar,#WaitAddress_ofs] + + LDMFD R13!,{PC} //Return +GBSpecial: + +#ifdef __PALMOS__ + LDR R3,[regCPUvar,#PALMOS_R10_ofs] + LDR R2,[PC,R2,LSL #2] + ADD PC,R2,R3 +#else + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 //nop, for align +#endif + .long GBPPU + .long GBCPU + .long GBDSP + .long GBLSRAM + .long GBHSRAM + .long GBNONE + .long GBDEBUG + .long GBC4 + .long GBBWRAM + .long GBNONE + .long GBNONE + .long GBNONE + /*.long GB7ROM + .long GB7RAM + .long GB7SRM*/ +GBPPU: + //InDMA ? + LDRB R1,[regCPUvar,#InDMA_ofs] + MOVS R1,R1 + ADDEQ regCycles,regCycles,#ONE_CYCLE //No -> update Cycles + MOV R0,R0,LSL #16 //S9xGetPPU(Address&0xFFFF); + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetPPU + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +GBCPU: + ADD regCycles,regCycles,#ONE_CYCLE //update Cycles + MOV R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF); + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetCPU + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +GBDSP: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + MOV R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF); + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetDSP + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +GBLSRAM: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + LDRH R2,[regCPUvar,#SRAMMask] + LDR R1,[regCPUvar,#SRAM] + AND R0,R2,R0 //Address&SRAMMask + LDRB R0,[R1,R0] //*Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} +GB7SRM: +GBHSRAM: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + + MOV R1,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R1,R1,LSR #17 //Address&0x7FFF + MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3) + ADD R0,R2,R1 + LDRH R2,[regCPUvar,#SRAMMask] + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDR R1,[regCPUvar,#SRAM] + AND R0,R2,R0 //Address&SRAMMask + LDRB R0,[R1,R0] //*Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} //return +GB7ROM: +GB7RAM: +GBNONE: + MOV R0,R0,LSR #8 + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + AND R0,R0,#0xFF + LDMFD R13!,{PC} +//GBDEBUG: + /*ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + MOV R0,#0 + LDMFD R13!,{PC}*/ +GBC4: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + MOV R0,R0,LSL #16 //S9xGetC4(Address&0xFFFF); + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetC4 + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +GBDEBUG: +GBBWRAM: + MOV R0,R0,LSL #17 + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + MOV R0,R0,LSR #17 //Address&0x7FFF + LDR R1,[regCPUvar,#BWRAM] + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000) + LDRB R0,[R0,R1] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + LDMFD R13!,{PC} + + +//uint16 aaS9xGetWord(uint32 address); +asmS9xGetWord: + // in : R0 = 0x00hhmmll + // out : R0 = 0x000000ll + // DESTROYED : R1,R2,R3 + // UPDATE : regCycles + + + MOV R1,R0,LSL #19 + ADDS R1,R1,#0x80000 + //if = 0x1FFF => 0 + BNE GW_NotBoundary + + STMFD R13!,{R0} + STMFD R13!,{PC} + B asmS9xGetByte + MOV R0,R0 + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + STMFD R13!,{PC} + B asmS9xGetByte + MOV R0,R0 + LDMFD R13!,{R1} + ORR R0,R1,R0,LSL #8 + LDMFD R13!,{PC} + +GW_NotBoundary: + + //R1 <= block + MOV R1,R0,LSR #MEMMAP_SHIFT + //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + //R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + //so AND MEMMAP_MASK is BIC 0xFF000 + BIC R1,R1,#0xFF000 + //R2 <= Map[block] (GetAddress) + LDR R2,[regCPUvar,#Map_ofs] + LDR R2,[R2,R1,LSL #2] + CMP R2,#MAP_LAST + BLO GWSpecial //special + // Direct ROM/RAM acess + + TST R0,#1 + BNE GW_Not_Aligned1 + //R2 <= GetAddress + Address & 0xFFFF + //R3 <= MemorySpeed[block] + LDR R3,[regCPUvar,#MemorySpeed_ofs] + MOV R0,R0,LSL #16 + LDRB R3,[R3,R1] + MOV R0,R0,LSR #16 + //Update CPU.Cycles + ADD regCycles,regCycles,R3, LSL #1 + //R3 = BlockIsRAM[block] + LDR R3,[regCPUvar,#BlockIsRAM_ofs] + //Get value to return + LDRH R0,[R2,R0] + LDRB R3,[R3,R1] + MOVS R3,R3 + // if BlockIsRAM => update for CPUShutdown + LDRNE R1,[regCPUvar,#PCAtOpcodeStart_ofs] + STRNE R1,[regCPUvar,#WaitAddress_ofs] + + LDMFD R13!,{PC} //Return +GW_Not_Aligned1: + + MOV R0,R0,LSL #16 + ADD R3,R0,#0x10000 + LDRB R3,[R2,R3,LSR #16] //GetAddress+ (Address+1)&0xFFFF + LDRB R0,[R2,R0,LSR #16] //GetAddress+ Address&0xFFFF + ORR R0,R0,R3,LSL #8 + + // if BlockIsRAM => update for CPUShutdown + LDR R3,[regCPUvar,#BlockIsRAM_ofs] + LDR R2,[regCPUvar,#MemorySpeed_ofs] + LDRB R3,[R3,R1] //R3 = BlockIsRAM[block] + LDRB R2,[R2,R1] //R2 <= MemorySpeed[block] + MOVS R3,R3 //IsRAM ? CPUShutdown stuff + LDRNE R1,[regCPUvar,#PCAtOpcodeStart_ofs] + STRNE R1,[regCPUvar,#WaitAddress_ofs] + ADD regCycles,regCycles,R2, LSL #1 //Update CPU.Cycles + LDMFD R13!,{PC} //Return +GWSpecial: +#ifdef __PALMOS__ + LDR R3,[regCPUvar,#PALMOS_R10_ofs] + LDR R2,[PC,R2,LSL #2] + ADD PC,R2,R3 +#else + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 //nop, for align +#endif + .long GWPPU + .long GWCPU + .long GWDSP + .long GWLSRAM + .long GWHSRAM + .long GWNONE + .long GWDEBUG + .long GWC4 + .long GWBWRAM + .long GWNONE + .long GWNONE + .long GWNONE + /*.long GW7ROM + .long GW7RAM + .long GW7SRM*/ +/* MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM, + MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP, + MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/ + +GWPPU: + //InDMA ? + LDRB R1,[regCPUvar,#InDMA_ofs] + MOVS R1,R1 + ADDEQ regCycles,regCycles,#(ONE_CYCLE*2) //No -> update Cycles + MOV R0,R0,LSL #16 //S9xGetPPU(Address&0xFFFF); + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL_R0 + BL S9xGetPPU + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + //BIC R0,R0,#0x10000 + BL S9xGetPPU + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +GWCPU: + ADD regCycles,regCycles,#(ONE_CYCLE*2) //update Cycles + MOV R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF); + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL_R0 + BL S9xGetCPU + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + //BIC R0,R0,#0x10000 + BL S9xGetCPU + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +GWDSP: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + MOV R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF); + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL_R0 + BL S9xGetDSP + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + //BIC R0,R0,#0x10000 + BL S9xGetDSP + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +GWLSRAM: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + + TST R0,#1 + BNE GW_Not_Aligned2 + LDRH R2,[regCPUvar,#SRAMMask] + LDR R1,[regCPUvar,#SRAM] + AND R3,R2,R0 //Address&SRAMMask + LDRH R0,[R3,R1] //*Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} //return +GW_Not_Aligned2: + LDRH R2,[regCPUvar,#SRAMMask] + LDR R1,[regCPUvar,#SRAM] + AND R3,R2,R0 //Address&SRAMMask + ADD R0,R0,#1 + AND R2,R0,R2 //Address&SRAMMask + LDRB R3,[R1,R3] //*Memory.SRAM + Address&SRAMMask + LDRB R2,[R1,R2] //*Memory.SRAM + Address&SRAMMask + ORR R0,R3,R2,LSL #8 + LDMFD R13!,{PC} //return +GW7SRM: +GWHSRAM: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + + TST R0,#1 + BNE GW_Not_Aligned3 + + MOV R1,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R1,R1,LSR #17 //Address&0x7FFF + MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3) + ADD R0,R2,R1 + LDRH R2,[regCPUvar,#SRAMMask] + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDR R1,[regCPUvar,#SRAM] + AND R0,R2,R0 //Address&SRAMMask + LDRH R0,[R1,R0] //*Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} //return + +GW_Not_Aligned3: + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 //Address&0x7FFF + MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3) + ADD R2,R2,R3 + ADD R0,R0,#1 + SUB R2,R2,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + MOV R3,R0,LSL #17 + AND R0,R0,#0xF0000 + MOV R3,R3,LSR #17 //(Address+1)&0x7FFF + MOV R0,R0,LSR #3 //((Address+1)&0xF0000 >> 3) + ADD R0,R0,R3 + LDRH R3,[regCPUvar,#SRAMMask] //reload mask + SUB R0,R0,#0x6000 //(((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3)) + AND R2,R3,R2 //Address...&SRAMMask + AND R0,R3,R0 //(Address+1...)&SRAMMask + + LDR R3,[regCPUvar,#SRAM] + LDRB R0,[R0,R3] //*Memory.SRAM + (Address...)&SRAMMask + LDRB R2,[R2,R3] //*Memory.SRAM + (Address+1...)&SRAMMask + ORR R0,R2,R0,LSL #8 + + LDMFD R13!,{PC} //return +GW7ROM: +GW7RAM: +GWNONE: + MOV R0,R0,LSL #16 + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + MOV R0,R0,LSR #24 + ORR R0,R0,R0,LSL #8 + LDMFD R13!,{PC} +GWDEBUG: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + MOV R0,#0 + LDMFD R13!,{PC} +GWC4: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + MOV R0,R0,LSL #16 //S9xGetC4(Address&0xFFFF); + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL_R0 + BL S9xGetC4 + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + //BIC R0,R0,#0x10000 + BL S9xGetC4 + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +GWBWRAM: + TST R0,#1 + BNE GW_Not_Aligned4 + MOV R0,R0,LSL #17 + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + MOV R0,R0,LSR #17 //Address&0x7FFF + LDR R1,[regCPUvar,#BWRAM] + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000) + LDRH R0,[R1,R0] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + LDMFD R13!,{PC} //return +GW_Not_Aligned4: + MOV R0,R0,LSL #17 + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + ADD R3,R0,#0x20000 + MOV R0,R0,LSR #17 //Address&0x7FFF + MOV R3,R3,LSR #17 //(Address+1)&0x7FFF + LDR R1,[regCPUvar,#BWRAM] + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000) + SUB R3,R3,#0x6000 //(((Address+1) & 0x7fff) - 0x6000) + LDRB R0,[R1,R0] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + LDRB R3,[R1,R3] //*Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000) + ORR R0,R0,R3,LSL #8 + LDMFD R13!,{PC} //return + +.pool + + +//void aaS9xSetByte(uint32 address,uint8 val); +asmS9xSetByte: + // in : R0=0x00hhmmll R1=0x000000ll + // DESTROYED : R0,R1,R2,R3 + // UPDATE : regCycles + //cpu shutdown + MOV R2,#0 + STR R2,[regCPUvar,#WaitAddress_ofs] + // + + //R3 <= block + MOV R3,R0,LSR #MEMMAP_SHIFT + //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + //R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + //so AND MEMMAP_MASK is BIC 0xFF000 + BIC R3,R3,#0xFF000 + //R2 <= Map[block] (SetAddress) + LDR R2,[regCPUvar,#WriteMap_ofs] + LDR R2,[R2,R3,LSL #2] + CMP R2,#MAP_LAST + BLO SBSpecial //special + // Direct ROM/RAM acess + + //R2 <= SetAddress + Address & 0xFFFF + MOV R0,R0,LSL #16 + ADD R2,R2,R0,LSR #16 + LDR R0,[regCPUvar,#MemorySpeed_ofs] + //Set byte + STRB R1,[R2] + //R0 <= MemorySpeed[block] + LDRB R0,[R0,R3] + //Update CPU.Cycles + ADD regCycles,regCycles,R0 + //CPUShutdown + //only SA1 here : TODO + //Return + LDMFD R13!,{PC} +SBSpecial: +#ifdef __PALMOS__ + LDR R3,[regCPUvar,#PALMOS_R10_ofs] + LDR R2,[PC,R2,LSL #2] + ADD PC,R2,R3 +#else + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 //nop, for align +#endif + .long SBPPU + .long SBCPU + .long SBDSP + .long SBLSRAM + .long SBHSRAM + .long SBNONE + .long SBDEBUG + .long SBC4 + .long SBBWRAM + .long SBNONE + .long SBNONE + .long SBNONE + /*.long SB7ROM + .long SB7RAM + .long SB7SRM*/ +SBPPU: + //InDMA ? + LDRB R2,[regCPUvar,#InDMA_ofs] + MOVS R2,R2 + ADDEQ regCycles,regCycles,#ONE_CYCLE //No -> update Cycles + MOV R0,R0,LSL #16 + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetPPU + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +SBCPU: + ADD regCycles,regCycles,#ONE_CYCLE //update Cycles + MOV R0,R0,LSL #16 + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 //Address&0xFFFF + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetCPU + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +SBDSP: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + MOV R0,R0,LSL #16 + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 //Address&0xFFFF + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetDSP + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +SBLSRAM: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + LDRH R2,[regCPUvar,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} //return if SRAMMask=0 + LDR R3,[regCPUvar,#SRAM] + AND R0,R2,R0 //Address&SRAMMask + STRB R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask + + MOV R0,#1 + STRB R0,[regCPUvar,#SRAMModified_ofs] + LDMFD R13!,{PC} //return +SB7SRM: +SBHSRAM: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 //Address&0x7FFF + MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3) + ADD R0,R2,R3 + + LDRH R2,[regCPUvar,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} //return if SRAMMask=0 + + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDR R3,[regCPUvar,#SRAM] + AND R0,R2,R0 //Address&SRAMMask + STRB R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask + + MOV R0,#1 + STRB R0,[regCPUvar,#SRAMModified_ofs] + LDMFD R13!,{PC} //return +SB7ROM: +SB7RAM: +SBNONE: +SBDEBUG: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + LDMFD R13!,{PC} +SBC4: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + MOV R0,R0,LSL #16 + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 //Address&0xFFFF + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetC4 + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +SBBWRAM: + MOV R0,R0,LSL #17 + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + MOV R0,R0,LSR #17 //Address&0x7FFF + LDR R2,[regCPUvar,#BWRAM] + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000) + STRB R1,[R0,R2] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + + MOV R0,#1 + STRB R0,[regCPUvar,#SRAMModified_ofs] + + LDMFD R13!,{PC} + + + +//void aaS9xSetWord(uint32 address,uint16 val); +asmS9xSetWord: + // in : R0 = 0x00hhmmll R1=0x0000hhll + // DESTROYED : R0,R1,R2,R3 + // UPDATE : regCycles + //R1 <= block + + MOV R2,R0,LSL #19 + ADDS R2,R2,#0x80000 + //if = 0x1FFF => 0 + BNE SW_NotBoundary + + STMFD R13!,{R0,R1} + STMFD R13!,{PC} + B asmS9xSetByte + MOV R0,R0 + LDMFD R13!,{R0,R1} + ADD R0,R0,#1 + MOV R1,R1,LSR #8 + STMFD R13!,{PC} + B asmS9xSetByte + MOV R0,R0 + + LDMFD R13!,{PC} + +SW_NotBoundary: + + MOV R2,#0 + STR R2,[regCPUvar,#WaitAddress_ofs] + // + //R3 <= block + MOV R3,R0,LSR #MEMMAP_SHIFT + //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + //R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + //so AND MEMMAP_MASK is BIC 0xFF000 + BIC R3,R3,#0xFF000 + //R2 <= Map[block] (SetAddress) + LDR R2,[regCPUvar,#WriteMap_ofs] + LDR R2,[R2,R3,LSL #2] + CMP R2,#MAP_LAST + BLO SWSpecial //special + // Direct ROM/RAM acess + + + //check if address is 16bits aligned or not + TST R0,#1 + BNE SW_not_aligned1 + //aligned + MOV R0,R0,LSL #16 + ADD R2,R2,R0,LSR #16 //address & 0xFFFF + SetAddress + LDR R0,[regCPUvar,#MemorySpeed_ofs] + //Set word + STRH R1,[R2] + //R1 <= MemorySpeed[block] + LDRB R0,[R0,R3] + //Update CPU.Cycles + ADD regCycles,regCycles,R0, LSL #1 + //CPUShutdown + //only SA1 here : TODO + //Return + LDMFD R13!,{PC} + +SW_not_aligned1: + //R1 = (Address&0xFFFF)<<16 + MOV R0,R0,LSL #16 + //First write @address + STRB R1,[R2,R0,LSR #16] + ADD R0,R0,#0x10000 + MOV R1,R1,LSR #8 + //Second write @address+1 + STRB R1,[R2,R0,LSR #16] + //R1 <= MemorySpeed[block] + LDR R0,[regCPUvar,#MemorySpeed_ofs] + LDRB R0,[R0,R3] + //Update CPU.Cycles + ADD regCycles,regCycles,R0,LSL #1 + //CPUShutdown + //only SA1 here : TODO + //Return + LDMFD R13!,{PC} +SWSpecial: +#ifdef __PALMOS__ + LDR R3,[regCPUvar,#PALMOS_R10_ofs] + LDR R2,[PC,R2,LSL #2] + ADD PC,R2,R3 +#else + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 //nop, for align +#endif + .long SWPPU + .long SWCPU + .long SWDSP + .long SWLSRAM + .long SWHSRAM + .long SWNONE + .long SWDEBUG + .long SWC4 + .long SWBWRAM + .long SWNONE + .long SWNONE + .long SWNONE + /*.long SW7ROM + .long SW7RAM + .long SW7SRM*/ +SWPPU: + //InDMA ? + LDRB R2,[regCPUvar,#InDMA_ofs] + MOVS R2,R2 + ADDEQ regCycles,regCycles,#(ONE_CYCLE*2) //No -> update Cycles + MOV R0,R0,LSL #16 + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetPPU + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetPPU + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +SWCPU: + ADD regCycles,regCycles,#(ONE_CYCLE*2) //update Cycles + MOV R0,R0,LSL #16 + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 //Address&0xFFFF + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetCPU + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetCPU + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +SWDSP: + ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles + MOV R0,R0,LSL #16 + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 //Address&0xFFFF + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetDSP + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetDSP + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +SWLSRAM: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + LDRH R2,[regCPUvar,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} //return if SRAMMask=0 + + AND R3,R2,R0 //Address&SRAMMask + TST R0,#1 + BNE SW_not_aligned2 + //aligned + LDR R0,[regCPUvar,#SRAM] + STRH R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask + MOV R0,#1 + STRB R0,[regCPUvar,#SRAMModified_ofs] + LDMFD R13!,{PC} //return +SW_not_aligned2: + + ADD R0,R0,#1 + AND R2,R2,R0 //(Address+1)&SRAMMask + LDR R0,[regCPUvar,#SRAM] + STRB R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask + MOV R1,R1,LSR #8 + STRB R1,[R0,R2] //*Memory.SRAM + (Address+1)&SRAMMask + MOV R0,#1 + STRB R0,[regCPUvar,#SRAMModified_ofs] + LDMFD R13!,{PC} //return +SW7SRM: +SWHSRAM: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + + LDRH R2,[regCPUvar,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} //return if SRAMMask=0 + + TST R0,#1 + BNE SW_not_aligned3 + //aligned + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 //Address&0x7FFF + MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3) + ADD R0,R2,R3 + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDRH R2,[regCPUvar,#SRAMMask] + LDR R3,[regCPUvar,#SRAM] + AND R0,R2,R0 //Address&SRAMMask + STRH R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask + MOV R0,#1 + STRB R0,[regCPUvar,#SRAMModified_ofs] + LDMFD R13!,{PC} //return +SW_not_aligned3: + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 //Address&0x7FFF + MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3) + ADD R2,R2,R3 + SUB R2,R2,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + + ADD R0,R0,#1 + MOV R3,R0,LSL #17 + AND R0,R0,#0xF0000 + MOV R3,R3,LSR #17 //(Address+1)&0x7FFF + MOV R0,R0,LSR #3 //((Address+1)&0xF0000 >> 3) + ADD R0,R0,R3 + LDRH R3,[regCPUvar,#SRAMMask] //reload mask + SUB R0,R0,#0x6000 //(((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3)) + AND R2,R3,R2 //Address...&SRAMMask + AND R0,R3,R0 //(Address+1...)&SRAMMask + + LDR R3,[regCPUvar,#SRAM] + STRB R1,[R2,R3] //*Memory.SRAM + (Address...)&SRAMMask + MOV R1,R1,LSR #8 + STRB R1,[R0,R3] //*Memory.SRAM + (Address+1...)&SRAMMask + + MOV R0,#1 + STRB R0,[regCPUvar,#SRAMModified_ofs] + LDMFD R13!,{PC} //return +SW7ROM: +SW7RAM: +SWNONE: +SWDEBUG: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + LDMFD R13!,{PC} //return +SWC4: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + MOV R0,R0,LSL #16 + STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles + MOV R0,R0,LSR #16 //Address&0xFFFF + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetC4 + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetC4 + RESTORE_C_CALL + LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles + LDMFD R13!,{PC} //Return +SWBWRAM: + ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles + TST R0,#1 + BNE SW_not_aligned4 + //aligned + MOV R0,R0,LSL #17 + LDR R2,[regCPUvar,#BWRAM] + MOV R0,R0,LSR #17 //Address&0x7FFF + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000) + MOV R3,#1 + STRH R1,[R0,R2] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + STRB R3,[regCPUvar,#SRAMModified_ofs] + LDMFD R13!,{PC} //return +SW_not_aligned4: + MOV R0,R0,LSL #17 + ADD R3,R0,#0x20000 + MOV R0,R0,LSR #17 //Address&0x7FFF + MOV R3,R3,LSR #17 //(Address+1)&0x7FFF + LDR R2,[regCPUvar,#BWRAM] + SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000) + SUB R3,R3,#0x6000 //(((Address+1) & 0x7fff) - 0x6000) + STRB R1,[R2,R0] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + MOV R1,R1,LSR #8 + STRB R1,[R2,R3] //*Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000) + MOV R0,#1 + STRB R0,[regCPUvar,#SRAMModified_ofs] + LDMFD R13!,{PC} //return + + +.pool diff --git a/src/os9x_65c816_mac_op.h b/src/os9x_65c816_mac_op.h new file mode 100644 index 0000000..3dcbfaa --- /dev/null +++ b/src/os9x_65c816_mac_op.h @@ -0,0 +1,2408 @@ +/***************************************************************** + FLAGS +*****************************************************************/ + +.macro UPDATE_C + // CC : ARM Carry Clear + BICCC rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero + // CS : ARM Carry Set + ORRCS rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one +.endm +.macro UPDATE_Z + // NE : ARM Zero Clear + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + // EQ : ARM Zero Set + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one +.endm +.macro UPDATE_ZN + // NE : ARM Zero Clear + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + // EQ : ARM Zero Set + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one + // PL : ARM Neg Clear + BICPL rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero + // MI : ARM Neg Set + ORRMI rstatus, rstatus, #MASK_NEG // 1 : OR mask 00000100000 : set N to one +.endm + +/***************************************************************** + OPCODES_MAC +*****************************************************************/ + + + + +.macro ADC8 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + S9xGetByte + + + STMFD R13!,{rscratch} + MOV rscratch4,#0x0F000000 + //rscratch2=xxW1xxxxxxxxxxxx + AND rscratch2, rscratch, rscratch4 + //rscratch=xxW2xxxxxxxxxxxx + AND rscratch, rscratch4, rscratch, LSR #4 + //rscratch3=xxA2xxxxxxxxxxxx + AND rscratch3, rscratch4, regA, LSR #4 + //rscratch4=xxA1xxxxxxxxxxxx + AND rscratch4,regA,rscratch4 + //R1=A1+W1+CARRY + TST rstatus, #MASK_CARRY + ADDNE rscratch2, rscratch2, #0x01000000 + ADD rscratch2,rscratch2,rscratch4 + // if R1 > 9 + CMP rscratch2, #0x09000000 + // then R1 -= 10 + SUBGT rscratch2, rscratch2, #0x0A000000 + // then A2++ + ADDGT rscratch3, rscratch3, #0x01000000 + // R2 = A2+W2 + ADD rscratch3, rscratch3, rscratch + // if R2 > 9 + CMP rscratch3, #0x09000000 + // then R2 -= 10// + SUBGT rscratch3, rscratch3, #0x0A000000 + // then SetCarry() + ORRGT rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one + // else ClearCarry() + BICLE rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero + // gather rscratch3 and rscratch2 into ans8 + // rscratch3 : 0R2000000 + // rscratch2 : 0R1000000 + // -> 0xR2R1000000 + ORR rscratch2, rscratch2, rscratch3, LSL #4 + LDMFD R13!,{rscratch} + //only last bit + AND rscratch,rscratch,#0x80000000 + // (register.AL ^ Work8) + EORS rscratch3, regA, rscratch + BICNE rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero + BNE 1112f + // (Work8 ^ Ans8) + EORS rscratch3, rscratch2, rscratch + // & 0x80 + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one +1112: + MOVS regA, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetByteLow + MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY + SUBCS rscratch, rscratch, #0x100 + ADCS regA, regA, rscratch, ROR #8 + //OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + //Carry + UPDATE_C + //clear lower part + ANDS regA, regA, #0xFF000000 + //Update flag + UPDATE_ZN +1113: +.endm +/* TO TEST */ +.macro ADC16 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + S9xGetWord + + //rscratch = W3W2W1W0........ + LDR rscratch4, = 0x0F0F0000 + // rscratch2 = xxW2xxW0xxxxxx + // rscratch3 = xxW3xxW1xxxxxx + AND rscratch2, rscratch4, rscratch + AND rscratch3, rscratch4, rscratch, LSR #4 + // rscratch2 = xxW3xxW1xxW2xxW0 + ORR rscratch2, rscratch3, rscratch2, LSR #16 + // rscratch3 = xxA2xxA0xxxxxx + // rscratch4 = xxA3xxA1xxxxxx + // rscratch2 = xxA3xxA1xxA2xxA0 + AND rscratch3, rscratch4, regA + AND rscratch4, rscratch4, regA, LSR #4 + ORR rscratch3, rscratch4, rscratch3, LSR #16 + ADD rscratch2, rscratch3, rscratch2 + LDR rscratch4, = 0x0F0F0000 + // rscratch2 = A + W + TST rstatus, #MASK_CARRY + ADDNE rscratch2, rscratch2, #0x1 + // rscratch2 = A + W + C + //A0 + AND rscratch3, rscratch2, #0x0000001F + CMP rscratch3, #0x00000009 + ADDHI rscratch2, rscratch2, #0x00010000 + SUBHI rscratch2, rscratch2, #0x0000000A + //A1 + AND rscratch3, rscratch2, #0x001F0000 + CMP rscratch3, #0x00090000 + ADDHI rscratch2, rscratch2, #0x00000100 + SUBHI rscratch2, rscratch2, #0x000A0000 + //A2 + AND rscratch3, rscratch2, #0x00001F00 + CMP rscratch3, #0x00000900 + SUBHI rscratch2, rscratch2, #0x00000A00 + ADDHI rscratch2, rscratch2, #0x01000000 + //A3 + AND rscratch3, rscratch2, #0x1F000000 + CMP rscratch3, #0x09000000 + SUBHI rscratch2, rscratch2, #0x0A000000 + //SetCarry + ORRHI rstatus, rstatus, #MASK_CARRY + //ClearCarry + BICLS rstatus, rstatus, #MASK_CARRY + //rscratch2 = xxR3xxR1xxR2xxR0 + //Pack result + //rscratch3 = xxR3xxR1xxxxxxxx + AND rscratch3, rscratch4, rscratch2 + //rscratch2 = xxR2xxR0xxxxxxxx + AND rscratch2, rscratch4, rscratch2,LSL #16 + //rscratch2 = R3R2R1R0xxxxxxxx + ORR rscratch2, rscratch2,rscratch3,LSL #4 +//only last bit + AND rscratch,rscratch,#0x80000000 + // (register.AL ^ Work8) + EORS rscratch3, regA, rscratch + BICNE rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero + BNE 1112f + // (Work8 ^ Ans8) + EORS rscratch3, rscratch2, rscratch + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one +1112: + MOVS regA, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetWordLow + MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY + SUBCS rscratch, rscratch, #0x10000 + ADCS regA, regA,rscratch, ROR #16 + //OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + MOV regA, regA, LSR #16 + //Carry + UPDATE_C + //clear lower parts + MOVS regA, regA, LSL #16 + //Update flag + UPDATE_ZN +1113: +.endm + + +.macro AND16 + S9xGetWord + ANDS regA, regA, rscratch + UPDATE_ZN +.endm +.macro AND8 + S9xGetByte + ANDS regA, regA, rscratch + UPDATE_ZN +.endm +.macro A_ASL8 + // 7 instr + MOVS regA, regA, LSL #1 + UPDATE_C + UPDATE_ZN + ADD1CYCLE +.endm +.macro A_ASL16 + // 7 instr + MOVS regA, regA, LSL #1 + UPDATE_C + UPDATE_ZN + ADD1CYCLE +.endm +.macro ASL16 + S9xGetWordRegNS rscratch2 // do not destroy Opadress in rscratch + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_C + UPDATE_ZN + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro ASL8 + S9xGetByteRegNS rscratch2 // do not destroy Opadress in rscratch + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_C + UPDATE_ZN + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro BIT8 + S9xGetByte + MOVS rscratch2, rscratch, LSL #1 + // Trick in ASM : shift one more bit : ARM C = Snes N + // ARM N = Snes V + // If Carry Set, then Set Neg in SNES + BICCC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set C to zero + ORRCS rstatus, rstatus, #MASK_NEG // 1 : OR mask 00000100000 : set C to one + // If Neg Set, then Set Overflow in SNES + BICPL rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set N to zero + ORRMI rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set N to one + + // Now do a real AND with A register + // Set Zero Flag, bit test + ANDS rscratch2, regA, rscratch + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one +.endm + +.macro BIT16 + S9xGetWord + MOVS rscratch2, rscratch, LSL #1 + // Trick in ASM : shift one more bit : ARM C = Snes N + // ARM N = Snes V + // If Carry Set, then Set Neg in SNES + BICCC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero + ORRCS rstatus, rstatus, #MASK_NEG // 1 : OR mask 00000100000 : set N to one + // If Neg Set, then Set Overflow in SNES + BICPL rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero + ORRMI rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one + // Now do a real AND with A register + // Set Zero Flag, bit test + ANDS rscratch2, regA, rscratch + // Bit set ->Z=0->xxxNE Clear flag + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + // Bit clear->Z=1->xxxEQ Set flag + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one +.endm +.macro CMP8 + S9xGetByte + SUBS rscratch2,regA,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + +.endm +.macro CMP16 + S9xGetWord + SUBS rscratch2,regA,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + +.endm +.macro CMX16 + S9xGetWord + SUBS rscratch2,regX,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro CMX8 + S9xGetByte + SUBS rscratch2,regX,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro CMY16 + S9xGetWord + SUBS rscratch2,regY,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro CMY8 + S9xGetByte + SUBS rscratch2,regY,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro A_DEC8 + MOV rscratch,#0 + SUBS regA, regA, #0x01000000 + STR rscratch,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro A_DEC16 + MOV rscratch,#0 + SUBS regA, regA, #0x00010000 + STR rscratch,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro DEC16 + S9xGetWordRegNS rscratch2 // do not destroy Opadress in rscratch + MOV rscratch3,#0 + SUBS rscratch2, rscratch2, #0x00010000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro DEC8 + S9xGetByteRegNS rscratch2 // do not destroy Opadress in rscratch + MOV rscratch3,#0 + SUBS rscratch2, rscratch2, #0x01000000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro EOR16 + S9xGetWord + EORS regA, regA, rscratch + UPDATE_ZN +.endm +.macro EOR8 + S9xGetByte + EORS regA, regA, rscratch + UPDATE_ZN +.endm +.macro A_INC8 + MOV rscratch3,#0 + ADDS regA, regA, #0x01000000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro A_INC16 + MOV rscratch3,#0 + ADDS regA, regA, #0x00010000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro INC16 + S9xGetWordRegNS rscratch2 + MOV rscratch3,#0 + ADDS rscratch2, rscratch2, #0x00010000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro INC8 + S9xGetByteRegNS rscratch2 + MOV rscratch3,#0 + ADDS rscratch2, rscratch2, #0x01000000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro LDA16 + S9xGetWordRegStatus regA + UPDATE_ZN +.endm +.macro LDA8 + S9xGetByteRegStatus regA + UPDATE_ZN +.endm +.macro LDX16 + S9xGetWordRegStatus regX + UPDATE_ZN +.endm +.macro LDX8 + S9xGetByteRegStatus regX + UPDATE_ZN +.endm +.macro LDY16 + S9xGetWordRegStatus regY + UPDATE_ZN +.endm +.macro LDY8 + S9xGetByteRegStatus regY + UPDATE_ZN +.endm +.macro A_LSR16 + BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero + MOVS regA, regA, LSR #17 // hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll + // Update Zero + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + MOV regA, regA, LSL #16 // -> 0lllllll 00000000 00000000 00000000 + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one + // Note : the two MOV are included between instruction, to optimize + // the pipeline. + UPDATE_C + ADD1CYCLE +.endm +.macro A_LSR8 + BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero + MOVS regA, regA, LSR #25 // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll + // Update Zero + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + MOV regA, regA, LSL #24 // -> 00000000 00000000 00000000 0lllllll + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one + // Note : the two MOV are included between instruction, to optimize + // the pipeline. + UPDATE_C + ADD1CYCLE +.endm +.macro LSR16 + S9xGetWordRegNS rscratch2 + // N set to zero by >> 1 LSR + BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero + MOVS rscratch2, rscratch2, LSR #17 // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll + // Update Carry + BICCC rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero + ORRCS rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one + // Update Zero + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one + S9xSetWordLow rscratch2 + ADD1CYCLE +.endm +.macro LSR8 + S9xGetByteRegNS rscratch2 + // N set to zero by >> 1 LSR + BIC rstatus, rstatus, #MASK_NEG // 0 : AND mask 11111011111 : set N to zero + MOVS rscratch2, rscratch2, LSR #25 // llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll + // Update Carry + BICCC rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero + ORRCS rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one + // Update Zero + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one + S9xSetByteLow rscratch2 + ADD1CYCLE +.endm +.macro ORA8 + S9xGetByte + ORRS regA, regA, rscratch + UPDATE_ZN +.endm +.macro ORA16 + S9xGetWord + ORRS regA, regA, rscratch + UPDATE_ZN +.endm +.macro A_ROL16 + TST rstatus, #MASK_CARRY + ORRNE regA, regA, #0x00008000 + MOVS regA, regA, LSL #1 + UPDATE_ZN + UPDATE_C + ADD1CYCLE +.endm +.macro A_ROL8 + TST rstatus, #MASK_CARRY + ORRNE regA, regA, #0x00800000 + MOVS regA, regA, LSL #1 + UPDATE_ZN + UPDATE_C + ADD1CYCLE +.endm +.macro ROL16 + S9xGetWordRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00008000 + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_ZN + UPDATE_C + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro ROL8 + S9xGetByteRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00800000 + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_ZN + UPDATE_C + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro A_ROR16 + MOV regA,regA, LSR #16 + TST rstatus, #MASK_CARRY + ORRNE regA, regA, #0x00010000 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS regA,regA,LSR #1 + UPDATE_C + UPDATE_Z + MOV regA,regA, LSL #16 + ADD1CYCLE +.endm +.macro A_ROR8 + MOV regA,regA, LSR #24 + TST rstatus, #MASK_CARRY + ORRNE regA, regA, #0x00000100 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS regA,regA,LSR #1 + UPDATE_C + UPDATE_Z + MOV regA,regA, LSL #24 + ADD1CYCLE +.endm +.macro ROR16 + S9xGetWordLowRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00010000 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS rscratch2,rscratch2,LSR #1 + UPDATE_C + UPDATE_Z + S9xSetWordLow rscratch2 + ADD1CYCLE + +.endm +.macro ROR8 + S9xGetByteLowRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00000100 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS rscratch2,rscratch2,LSR #1 + UPDATE_C + UPDATE_Z + S9xSetByteLow rscratch2 + ADD1CYCLE +.endm + +.macro SBC16 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + //TODO + S9xGetWord + + STMFD R13!,{rscratch5,rscratch6,rscratch7,rscratch8,rscratch9} + MOV rscratch9,#0x000F0000 + //rscratch2=xxxxxxW1xxxxxxxxxx + !Carry + //rscratch3=xxxxxxW2xxxxxxxxxx + //rscratch4=xxxxxxW3xxxxxxxxxx + //rscratch5=xxxxxxW4xxxxxxxxxx + AND rscratch2, rscratch9, rscratch + TST rstatus, #MASK_CARRY + ADDEQ rscratch2, rscratch2, #0x00010000 //W1=W1+!Carry + AND rscratch3, rscratch9, rscratch, LSR #4 + AND rscratch4, rscratch9, rscratch, LSR #8 + AND rscratch5, rscratch9, rscratch, LSR #12 + + //rscratch6=xxxxxxA1xxxxxxxxxx + //rscratch7=xxxxxxA2xxxxxxxxxx + //rscratch8=xxxxxxA3xxxxxxxxxx + //rscratch9=xxxxxxA4xxxxxxxxxx + AND rscratch6, rscratch9, regA + AND rscratch7, rscratch9, regA, LSR #4 + AND rscratch8, rscratch9, regA, LSR #8 + AND rscratch9, rscratch9, regA, LSR #12 + + SUB rscratch2,rscratch6,rscratch2 //R1=A1-W1-!Carry + CMP rscratch2, #0x00090000 // if R1 > 9 + ADDHI rscratch2, rscratch2, #0x000A0000 // then R1 += 10 + ADDHI rscratch3, rscratch3, #0x00010000 // then (W2++) + SUB rscratch3,rscratch7,rscratch3 //R2=A2-W2 + CMP rscratch3, #0x00090000 // if R2 > 9 + ADDHI rscratch3, rscratch3, #0x000A0000 // then R2 += 10 + ADDHI rscratch4, rscratch4, #0x00010000 // then (W3++) + SUB rscratch4,rscratch8,rscratch4 //R3=A3-W3 + CMP rscratch4, #0x00090000 // if R3 > 9 + ADDHI rscratch4, rscratch4, #0x000A0000 // then R3 += 10 + ADDHI rscratch5, rscratch5, #0x00010000 // then (W3++) + SUB rscratch5,rscratch9,rscratch5 //R4=A4-W4 + CMP rscratch5, #0x00090000 // if R4 > 9 + ADDHI rscratch5, rscratch5, #0x000A0000 // then R4 += 10 + BICHI rstatus, rstatus, #MASK_CARRY // then ClearCarry + ORRLS rstatus, rstatus, #MASK_CARRY // else SetCarry + + MOV rscratch9,#0x000F0000 + AND rscratch2,rscratch9,rscratch2 + AND rscratch3,rscratch9,rscratch3 + AND rscratch4,rscratch9,rscratch4 + AND rscratch5,rscratch9,rscratch5 + ORR rscratch2,rscratch2,rscratch3,LSL #4 + ORR rscratch2,rscratch2,rscratch4,LSL #8 + ORR rscratch2,rscratch2,rscratch5,LSL #12 + + LDMFD R13!,{rscratch5,rscratch6,rscratch7,rscratch8,rscratch9} + //only last bit + AND regA,regA,#0x80000000 + // (register.A.W ^ Work8) + EORS rscratch3, regA, rscratch + BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero + BEQ 1112f + // (register.A.W ^ Ans8) + EORS rscratch3, regA, rscratch2 + // & 0x80 + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one +1112: + MOVS regA, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetWordLow + MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY + SBCS regA, regA, rscratch, LSL #16 + //OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + MOV regA, regA, LSR #16 + //Carry + UPDATE_C + MOVS regA, regA, LSL #16 + //Update flag + UPDATE_ZN +1113: +.endm + +.macro SBC8 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + S9xGetByte + STMFD R13!,{rscratch} + MOV rscratch4,#0x0F000000 + //rscratch2=xxW1xxxxxxxxxxxx + AND rscratch2, rscratch, rscratch4 + //rscratch=xxW2xxxxxxxxxxxx + AND rscratch, rscratch4, rscratch, LSR #4 + //rscratch3=xxA2xxxxxxxxxxxx + AND rscratch3, rscratch4, regA, LSR #4 + //rscratch4=xxA1xxxxxxxxxxxx + AND rscratch4,regA,rscratch4 + //R1=A1-W1-!CARRY + TST rstatus, #MASK_CARRY + ADDEQ rscratch2, rscratch2, #0x01000000 + SUB rscratch2,rscratch4,rscratch2 + // if R1 > 9 + CMP rscratch2, #0x09000000 + // then R1 += 10 + ADDHI rscratch2, rscratch2, #0x0A000000 + // then A2-- (W2++) + ADDHI rscratch, rscratch, #0x01000000 + // R2=A2-W2 + SUB rscratch3, rscratch3, rscratch + // if R2 > 9 + CMP rscratch3, #0x09000000 + // then R2 -= 10// + ADDHI rscratch3, rscratch3, #0x0A000000 + // then SetCarry() + BICHI rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one + // else ClearCarry() + ORRLS rstatus, rstatus, #MASK_CARRY // 0 : AND mask 11111011111 : set C to zero + // gather rscratch3 and rscratch2 into ans8 + AND rscratch3,rscratch3,#0x0F000000 + AND rscratch2,rscratch2,#0x0F000000 + // rscratch3 : 0R2000000 + // rscratch2 : 0R1000000 + // -> 0xR2R1000000 + ORR rscratch2, rscratch2, rscratch3, LSL #4 + LDMFD R13!,{rscratch} + //only last bit + AND regA,regA,#0x80000000 + // (register.AL ^ Work8) + EORS rscratch3, regA, rscratch + BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero + BEQ 1112f + // (register.AL ^ Ans8) + EORS rscratch3, regA, rscratch2 + // & 0x80 + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW // 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW // 1 : OR mask 00000100000 : set V to one +1112: + MOVS regA, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetByteLow + MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY + SBCS regA, regA, rscratch, LSL #24 + //OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + //Carry + UPDATE_C + //Update flag + ANDS regA, regA, #0xFF000000 + UPDATE_ZN +1113: +.endm + +.macro STA16 + S9xSetWord regA +.endm +.macro STA8 + S9xSetByte regA +.endm +.macro STX16 + S9xSetWord regX +.endm +.macro STX8 + S9xSetByte regX +.endm +.macro STY16 + S9xSetWord regY +.endm +.macro STY8 + S9xSetByte regY +.endm +.macro STZ16 + S9xSetWordZero +.endm +.macro STZ8 + S9xSetByteZero +.endm +.macro TSB16 + S9xGetWordRegNS rscratch2 + TST regA, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one + ORR rscratch2, regA, rscratch2 + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro TSB8 + S9xGetByteRegNS rscratch2 + TST regA, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one + ORR rscratch2, regA, rscratch2 + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro TRB16 + S9xGetWordRegNS rscratch2 + TST regA, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one + MVN rscratch3, regA + AND rscratch2, rscratch3, rscratch2 + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro TRB8 + S9xGetByteRegNS rscratch2 + TST regA, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO // 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO // 1 : OR mask 00000100000 : set Z to one + MVN rscratch3, regA + AND rscratch2, rscratch3, rscratch2 + S9xSetByte rscratch2 + ADD1CYCLE +.endm +/**************************************************************************/ + + +/**************************************************************************/ + +.macro Op09M0 /*ORA*/ + LDRB rscratch2, [rpc,#1] + LDRB rscratch, [rpc], #2 + ORR rscratch2,rscratch,rscratch2,LSL #8 + ORRS regA,regA,rscratch2,LSL #16 + UPDATE_ZN + ADD2MEM +.endm +.macro Op09M1 /*ORA*/ + LDRB rscratch, [rpc], #1 + ORRS regA,regA,rscratch,LSL #24 + UPDATE_ZN + ADD1MEM +.endm +/***********************************************************************/ +.macro Op90 /*BCC*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_CARRY + BNE 1111f + ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro OpB0 /*BCS*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_CARRY + BEQ 1111f + ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro OpF0 /*BEQ*/ + asmRelative + BranchCheck2 + TST rstatus, #MASK_ZERO + BEQ 1111f + ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro OpD0 /*BNE*/ + asmRelative + BranchCheck1 + TST rstatus, #MASK_ZERO + BNE 1111f + ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op30 /*BMI*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_NEG + BEQ 1111f + ADD rpc, rscratch, regpcbase // rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op10 /*BPL*/ + asmRelative + BranchCheck1 + TST rstatus, #MASK_NEG // neg, z!=0, NE + BNE 1111f + ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op50 /*BVC*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_OVERFLOW // neg, z!=0, NE + BNE 1111f + ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op70 /*BVS*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_OVERFLOW // neg, z!=0, NE + BEQ 1111f + ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op80 /*BRA*/ + asmRelative + ADD rpc, rscratch, regpcbase // rpc = OpAddress + PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +/*******************************************************************************************/ +/************************************************************/ +/* SetFlag Instructions ********************************************************************** */ +.macro Op38 /*SEC*/ + ORR rstatus, rstatus, #MASK_CARRY // 1 : OR mask 00000100000 : set C to one + ADD1CYCLE +.endm +.macro OpF8 /*SED*/ + SetDecimal + ADD1CYCLE +.endm +.macro Op78 /*SEI*/ + SetIRQ + ADD1CYCLE +.endm + + +/****************************************************************************************/ +/* ClearFlag Instructions ******************************************************************** */ +.macro Op18 /*CLC*/ + BIC rstatus, rstatus, #MASK_CARRY + ADD1CYCLE +.endm +.macro OpD8 /*CLD*/ + ClearDecimal + ADD1CYCLE +.endm +.macro Op58 /*CLI*/ + ClearIRQ + ADD1CYCLE + //CHECK_FOR_IRQ +.endm +.macro OpB8 /*CLV*/ + BIC rstatus, rstatus, #MASK_OVERFLOW + ADD1CYCLE +.endm + +/******************************************************************************************/ +/* DEX/DEY *********************************************************************************** */ + +.macro OpCAX1 /*DEX*/ + MOV rscratch3,#0 + SUBS regX, regX, #0x01000000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpCAX0 /*DEX*/ + MOV rscratch3,#0 + SUBS regX, regX, #0x00010000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op88X1 /*DEY*/ + MOV rscratch3,#0 + SUBS regY, regY, #0x01000000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op88X0 /*DEY*/ + MOV rscratch3,#0 + SUBS regY, regY, #0x00010000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm + +/******************************************************************************************/ +/* INX/INY *********************************************************************************** */ +.macro OpE8X1 + MOV rscratch3,#0 + ADDS regX, regX, #0x01000000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpE8X0 + MOV rscratch3,#0 + ADDS regX, regX, #0x00010000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpC8X1 + MOV rscratch3,#0 + ADDS regY, regY, #0x01000000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpC8X0 + MOV rscratch3,#0 + ADDS regY, regY, #0x00010000 + STR rscratch3,[regCPUvar,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm + +/**********************************************************************************************/ + +/* NOP *************************************************************************************** */ +.macro OpEA + ADD1CYCLE +.endm + +/**************************************************************************/ +/* PUSH Instructions **************************************************** */ +.macro OpF4 + Absolute + PushWrLow +.endm +.macro OpD4 + DirectIndirect + PushWrLow +.endm +.macro Op62 + asmRelativeLong + PushWrLow +.endm +.macro Op48M0 + PushW regA + ADD1CYCLE +.endm +.macro Op48M1 + PushB regA + ADD1CYCLE +.endm +.macro Op8B + AND rscratch2, regDBank, #0xFF + PushBLow rscratch2 + ADD1CYCLE +.endm +.macro Op0B + PushW regD + ADD1CYCLE +.endm +.macro Op4B + PushBlow regPBank + ADD1CYCLE +.endm +.macro Op08 + PushB rstatus + ADD1CYCLE +.endm +.macro OpDAX1 + PushB regX + ADD1CYCLE +.endm +.macro OpDAX0 + PushW regX + ADD1CYCLE +.endm +.macro Op5AX1 + PushB regY + ADD1CYCLE +.endm +.macro Op5AX0 + PushW regY + ADD1CYCLE +.endm +/**************************************************************************/ +/* PULL Instructions **************************************************** */ +.macro Op68M1 + PullBS regA + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op68M0 + PullWS regA + UPDATE_ZN + ADD2CYCLE +.endm +.macro OpAB + BIC regDBank,regDBank, #0xFF + PullBrS + ORR regDBank,regDBank,rscratch, LSR #24 + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op2B + BIC regD,regD, #0xFF000000 + BIC regD,regD, #0x00FF0000 + PullWrS + ORR regD,rscratch,regD + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op28X1M1 /*PLP*/ + //INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + //INDEX clear & was set : 8->16 + MOVEQ regX,regX,LSR #8 + MOVEQ regY,regY,LSR #8 + TST rstatus, #MASK_MEM + //MEMORY cleared & was set : 8->16 + LDREQB rscratch,[regCPUvar,#RAH_ofs] + MOVEQ regA,regA,LSR #8 + ORREQ regA,regA,rscratch, LSL #24 + S9xFixCycles + ADD2CYCLE +.endm +.macro Op28X0M1 /*PLP*/ + //INDEX cleared, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + //INDEX set & was cleared : 16->8 + MOVNE regX,regX,LSL #8 + MOVNE regY,regY,LSL #8 + TST rstatus, #MASK_MEM + //MEMORY cleared & was set : 8->16 + LDREQB rscratch,[regCPUvar,#RAH_ofs] + MOVEQ regA,regA,LSR #8 + ORREQ regA,regA,rscratch, LSL #24 + S9xFixCycles + ADD2CYCLE +.endm +.macro Op28X1M0 /*PLP*/ + //INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + //INDEX clear & was set : 8->16 + MOVEQ regX,regX,LSR #8 + MOVEQ regY,regY,LSR #8 + TST rstatus, #MASK_MEM + //MEMORY set & was cleared : 16->8 + MOVNE rscratch,regA,LSR #24 + MOVNE regA,regA,LSL #8 + STRNEB rscratch,[regCPUvar,#RAH_ofs] + S9xFixCycles + ADD2CYCLE +.endm +.macro Op28X0M0 /*PLP*/ + //INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + //INDEX set & was cleared : 16->8 + MOVNE regX,regX,LSL #8 + MOVNE regY,regY,LSL #8 + TST rstatus, #MASK_MEM + //MEMORY set & was cleared : 16->8 + MOVNE rscratch,regA,LSR #24 + MOVNE regA,regA,LSL #8 + STRNEB rscratch,[regCPUvar,#RAH_ofs] + S9xFixCycles + ADD2CYCLE +.endm +.macro OpFAX1 + PullBS regX + UPDATE_ZN + ADD2CYCLE +.endm +.macro OpFAX0 + PullWS regX + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op7AX1 + PullBS regY + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op7AX0 + PullWS regY + UPDATE_ZN + ADD2CYCLE +.endm + +/**********************************************************************************************/ +/* Transfer Instructions ********************************************************************* */ +.macro OpAAX1M1 /*TAX8*/ + MOVS regX, regA + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpAAX0M1 /*TAX16*/ + LDRB regX, [regCPUvar,#RAH_ofs] + MOV regX, regX,LSL #24 + ORRS regX, regX,regA, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpAAX1M0 /*TAX8*/ + MOVS regX, regA, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpAAX0M0 /*TAX16*/ + MOVS regX, regA + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X1M1 /*TAY8*/ + MOVS regY, regA + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X0M1 /*TAY16*/ + LDRB regY, [regCPUvar,#RAH_ofs] + MOV regY, regY,LSL #24 + ORRS regY, regY,regA, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X1M0 /*TAY8*/ + MOVS regY, regA, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X0M0 /*TAY16*/ + MOVS regY, regA + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op5BM1 + LDRB rscratch, [regCPUvar,#RAH_ofs] + MOV regD,regD,LSL #16 + MOV rscratch,rscratch,LSL #24 + ORRS rscratch,rscratch,regA, LSR #8 + UPDATE_ZN + ORR regD,rscratch,regD,LSR #16 + ADD1CYCLE +.endm +.macro Op5BM0 + MOV regD,regD,LSL #16 + MOVS regA,regA + UPDATE_ZN + ORR regD,regA,regD,LSR #16 + ADD1CYCLE +.endm +.macro Op1BM1 + TST rstatus, #MASK_EMUL + MOVNE regS, regA, LSR #24 + ORRNE regS, regS, #0x100 + LDREQB regS, [regCPUvar,#RAH_ofs] + ORREQ regS, regS, regA + MOVEQ regS, regS, ROR #24 + ADD1CYCLE +.endm +.macro Op1BM0 + MOV regS, regA, LSR #16 + ADD1CYCLE +.endm +.macro Op7BM1 + MOVS regA, regD, ASR #16 + UPDATE_ZN + MOV rscratch,regA,LSR #8 + MOV regA,regA, LSL #24 + STRB rscratch, [regCPUvar,#RAH_ofs] + ADD1CYCLE +.endm +.macro Op7BM0 + MOVS regA, regD, ASR #16 + UPDATE_ZN + MOV regA,regA, LSL #16 + ADD1CYCLE +.endm +.macro Op3BM1 + MOV rscratch,regS, LSR #8 + MOVS regA, regS, LSL #16 + STRB rscratch, [regCPUvar,#RAH_ofs] + UPDATE_ZN + MOV regA,regA, LSL #8 + ADD1CYCLE +.endm +.macro Op3BM0 + MOVS regA, regS, LSL #16 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBAX1 + MOVS regX, regS, LSL #24 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBAX0 + MOVS regX, regS, LSL #16 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM1X1 + MOVS regA, regX + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM1X0 + MOVS regA, regX, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM0X1 + MOVS regA, regX, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM0X0 + MOVS regA, regX + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op9AX1 + MOV regS, regX, LSR #24 + TST rstatus, #MASK_EMUL + ORRNE regS, regS, #0x100 + ADD1CYCLE +.endm +.macro Op9AX0 + MOV regS, regX, LSR #16 + ADD1CYCLE +.endm +.macro Op9BX1 + MOVS regY, regX + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op9BX0 + MOVS regY, regX + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M1X1 + MOVS regA, regY + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M1X0 + MOVS regA, regY, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M0X1 + MOVS regA, regY, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M0X0 + MOVS regA, regY + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBBX1 + MOVS regX, regY + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBBX0 + MOVS regX, regY + UPDATE_ZN + ADD1CYCLE +.endm + +/**********************************************************************************************/ +/* XCE *************************************************************************************** */ + +.macro OpFB + TST rstatus,#MASK_CARRY + BEQ 1111f + //CARRY is set + TST rstatus,#MASK_EMUL + BNE 1112f + //EMUL is cleared + BIC rstatus,rstatus,#(MASK_CARRY) + TST rstatus,#MASK_INDEX + //X & Y were 16bits before + MOVEQ regX,regX,LSL #8 + MOVEQ regY,regY,LSL #8 + TST rstatus,#MASK_MEM + //A was 16bits before + //save AH + MOVEQ rscratch,regA,LSR #24 + STREQB rscratch,[regCPUvar,#RAH_ofs] + MOVEQ regA,regA,LSL #8 + ORR rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX) + AND regS,regS,#0xFF + ORR regS,regS,#0x100 + B 1113f +1112: + //EMUL is set + TST rstatus,#MASK_INDEX + //X & Y were 16bits before + MOVEQ regX,regX,LSL #8 + MOVEQ regY,regY,LSL #8 + TST rstatus,#MASK_MEM + //A was 16bits before + //save AH + MOVEQ rscratch,regA,LSR #24 + STREQB rscratch,[regCPUvar,#RAH_ofs] + MOVEQ regA,regA,LSL #8 + ORR rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX) + AND regS,regS,#0xFF + ORR regS,regS,#0x100 + B 1113f +1111: + //CARRY is cleared + TST rstatus,#MASK_EMUL + BEQ 1115f + //EMUL was set : X,Y & A were 8bits + //Now have to check MEMORY & INDEX for potential conversions to 16bits + TST rstatus,#MASK_INDEX + // X & Y are now 16bits + MOVEQ regX,regX,LSR #8 + MOVEQ regY,regY,LSR #8 + TST rstatus,#MASK_MEM + // A is now 16bits + MOVEQ regA,regA,LSR #8 + //restore AH + LDREQB rscratch,[regCPUvar,#RAH_ofs] + ORREQ regA,regA,rscratch,LSL #24 +1115: + BIC rstatus,rstatus,#(MASK_EMUL) + ORR rstatus,rstatus,#(MASK_CARRY) +1113: + ADD1CYCLE + S9xFixCycles +.endm + +/*******************************************************************************/ +/* BRK *************************************************************************/ +.macro Op00 /*BRK*/ + MOV rscratch,#1 + STRB rscratch,[regCPUvar,#BRKTriggered_ofs] + + TST rstatus, #MASK_EMUL + // EQ is flag to zero (!CheckEmu) + BNE 2001f//elseOp00 + PushBLow regPBank + SUB rscratch, rpc, regpcbase + ADD rscratch2, rscratch, #1 + PushWLow rscratch2 + // PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC regPBank, regPBank, #0xFF + MOV rscratch, #0xE6 + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD2CYCLE + B 2002f//endOp00 +2001://elseOp00 + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + // PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC regPBank,regPBank, #0xFF + MOV rscratch, #0xFE + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD1CYCLE +2002://endOp00 +.endm + + +/**********************************************************************************************/ +/* BRL ************************************************************************************** */ +.macro Op82 /*BRL*/ + asmRelativeLong + ORR rscratch, rscratch, regPBank, LSL #16 + S9xSetPCBase +.endm +/**********************************************************************************************/ +/* IRQ *************************************************************************************** */ +//void S9xOpcode_IRQ (void) +/* + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40)) + S9xSetPCBase (Memory.FillRAM [0x220e] | + (Memory.FillRAM [0x220f] << 8)); + else + S9xSetPCBase (S9xGetWord (0xFFEE)); + CPU.Cycles += TWO_CYCLES; + } + else + { + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40)) + S9xSetPCBase (Memory.FillRAM [0x220e] | + (Memory.FillRAM [0x220f] << 8)); + else + S9xSetPCBase (S9xGetWord (0xFFFE)); + CPU.Cycles += ONE_CYCLE; + } + } +*/ + +/**********************************************************************************************/ +/* NMI *************************************************************************************** */ +//void S9xOpcode_NMI (void) +/*{ + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20)) + S9xSetPCBase (Memory.FillRAM [0x220c] | + (Memory.FillRAM [0x220d] << 8)); + else + S9xSetPCBase (S9xGetWord (0xFFEA)); + CPU.Cycles += TWO_CYCLES; + } + else + { + PushW (CPU.PC - CPU.PCBase); + S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + ICPU.ShiftedPB = 0; + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20)) + S9xSetPCBase (Memory.FillRAM [0x220c] | + (Memory.FillRAM [0x220d] << 8)); + else + S9xSetPCBase (S9xGetWord (0xFFFA)); + CPU.Cycles += ONE_CYCLE; + } +} +*/ + +/**********************************************************************************************/ +/* COP *************************************************************************************** */ +.macro Op02 /*COP*/ + TST rstatus, #MASK_EMUL + // EQ is flag to zero (!CheckEmu) + BNE 2021f//elseOp02 + PushBLow regPBank + SUB rscratch, rpc, regpcbase + ADD rscratch2, rscratch, #1 + PushWLow rscratch2 + // PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC regPBank, regPBank,#0xFF + MOV rscratch, #0xE4 + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD2CYCLE + B 2022f//endOp02 +2021://elseOp02 + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + // PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC regPBank,regPBank, #0xFF + MOV rscratch, #0xF4 + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD1CYCLE +2022://endOp02 +.endm + +/**********************************************************************************************/ +/* JML *************************************************************************************** */ +.macro OpDC + AbsoluteIndirectLong + BIC regPBank,regPBank,#0xFF + ORR regPBank,regPBank, rscratch, LSR #16 + S9xSetPCBase + ADD2CYCLE +.endm +.macro Op5C + AbsoluteLong + BIC regPBank,regPBank,#0xFF + ORR regPBank,regPBank, rscratch, LSR #16 + S9xSetPCBase +.endm + +/**********************************************************************************************/ +/* JMP *************************************************************************************** */ +.macro Op4C + Absolute + BIC rscratch, rscratch, #0xFF0000 + ORR rscratch, rscratch, regPBank, LSL #16 + S9xSetPCBase + CPUShutdown +.endm +.macro Op6C + AbsoluteIndirect + BIC rscratch, rscratch, #0xFF0000 + ORR rscratch, rscratch, regPBank, LSL #16 + S9xSetPCBase +.endm +.macro Op7C + ADD rscratch, rscratch, regPBank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm + +/**********************************************************************************************/ +/* JSL/RTL *********************************************************************************** */ +.macro Op22 + PushBlow regPBank + SUB rscratch, rpc, regpcbase + //SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #2 + PushWlow rscratch2 + AbsoluteLong + BIC regPBank,regPBank,#0xFF + ORR regPBank, regPBank, rscratch, LSR #16 + S9xSetPCBase +.endm +.macro Op6B + PullWLow rpc + BIC regPBank,regPBank,#0xFF + PullBrLow + ORR regPBank, regPBank, rscratch + ADD rscratch, rpc, #1 + BIC rscratch, rscratch,#0xFF0000 + ORR rscratch, rscratch, regPBank, LSL #16 + S9xSetPCBase + ADD2CYCLE +.endm +/**********************************************************************************************/ +/* JSR/RTS *********************************************************************************** */ +.macro Op20 + SUB rscratch, rpc, regpcbase + //SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #1 + PushWlow rscratch2 + Absolute + BIC rscratch, rscratch, #0xFF0000 + ORR rscratch, rscratch, regPBank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm +.macro OpFCX0 + SUB rscratch, rpc, regpcbase + //SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #1 + PushWlow rscratch2 + AbsoluteIndexedIndirectX0 + ORR rscratch, rscratch, regPBank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm +.macro OpFCX1 + SUB rscratch, rpc, regpcbase + //SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #1 + PushWlow rscratch2 + AbsoluteIndexedIndirectX1 + ORR rscratch, rscratch, regPBank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm +.macro Op60 + PullWLow rpc + ADD rscratch, rpc, #1 + BIC rscratch, rscratch,#0x10000 + ORR rscratch, rscratch, regPBank, LSL #16 + S9xSetPCBase + ADD3CYCLE +.endm + +/**********************************************************************************************/ +/* MVN/MVP *********************************************************************************** */ +.macro Op54X1M1 + //Save RegStatus = regDBank >> 24 + MOV rscratch, regDBank, LSR #16 + LDRB regDBank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + //Restore RegStatus = regDBank >> 24 + ORR regDBank, regDBank, rscratch, LSL #16 + MOV rscratch , regX, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , regY, LSR #24 + ORR rscratch , rscratch, regDBank, LSL #16 + S9xSetByteLow rscratch2 + //load 16bits A + LDRB rscratch,[regCPUvar,#RAH_ofs] + MOV regA,regA,LSR #8 + ORR regA,regA,rscratch, LSL #24 + ADD regX, regX, #0x01000000 + SUB regA, regA, #0x00010000 + ADD regY, regY, #0x01000000 + CMP regA, #0xFFFF0000 + SUBNE rpc, rpc, #3 + //update AH + MOV rscratch, regA, LSR #24 + MOV regA,regA,LSL #8 + STRB rscratch,[regCPUvar,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op54X1M0 + //Save RegStatus = regDBank >> 24 + MOV rscratch, regDBank, LSR #16 + LDRB regDBank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + //Restore RegStatus = regDBank >> 24 + ORR regDBank, regDBank, rscratch, LSL #16 + MOV rscratch , regX, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , regY, LSR #24 + ORR rscratch , rscratch, regDBank, LSL #16 + S9xSetByteLow rscratch2 + ADD regX, regX, #0x01000000 + SUB regA, regA, #0x00010000 + ADD regY, regY, #0x01000000 + CMP regA, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm +.macro Op54X0M1 + //Save RegStatus = regDBank >> 24 + MOV rscratch, regDBank, LSR #16 + LDRB regDBank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + //Restore RegStatus = regDBank >> 24 + ORR regDBank, regDBank, rscratch, LSL #16 + MOV rscratch , regX, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , regY, LSR #16 + ORR rscratch , rscratch, regDBank, LSL #16 + S9xSetByteLow rscratch2 + //load 16bits A + LDRB rscratch,[regCPUvar,#RAH_ofs] + MOV regA,regA,LSR #8 + ORR regA,regA,rscratch, LSL #24 + ADD regX, regX, #0x00010000 + SUB regA, regA, #0x00010000 + ADD regY, regY, #0x00010000 + CMP regA, #0xFFFF0000 + SUBNE rpc, rpc, #3 + //update AH + MOV rscratch, regA, LSR #24 + MOV regA,regA,LSL #8 + STRB rscratch,[regCPUvar,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op54X0M0 + //Save RegStatus = regDBank >> 24 + MOV rscratch, regDBank, LSR #16 + LDRB regDBank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + //Restore RegStatus = regDBank >> 24 + ORR regDBank, regDBank, rscratch, LSL #16 + MOV rscratch , regX, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , regY, LSR #16 + ORR rscratch , rscratch, regDBank, LSL #16 + S9xSetByteLow rscratch2 + ADD regX, regX, #0x00010000 + SUB regA, regA, #0x00010000 + ADD regY, regY, #0x00010000 + CMP regA, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm + +.macro Op44X1M1 + //Save RegStatus = regDBank >> 24 + MOV rscratch, regDBank, LSR #16 + LDRB regDBank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + //Restore RegStatus = regDBank >> 24 + ORR regDBank, regDBank, rscratch, LSL #16 + MOV rscratch , regX, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , regY, LSR #24 + ORR rscratch , rscratch, regDBank, LSL #16 + S9xSetByteLow rscratch2 + //load 16bits A + LDRB rscratch,[regCPUvar,#RAH_ofs] + MOV regA,regA,LSR #8 + ORR regA,regA,rscratch, LSL #24 + SUB regX, regX, #0x01000000 + SUB regA, regA, #0x00010000 + SUB regY, regY, #0x01000000 + CMP regA, #0xFFFF0000 + SUBNE rpc, rpc, #3 + //update AH + MOV rscratch, regA, LSR #24 + MOV regA,regA,LSL #8 + STRB rscratch,[regCPUvar,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op44X1M0 + //Save RegStatus = regDBank >> 24 + MOV rscratch, regDBank, LSR #16 + LDRB regDBank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + //Restore RegStatus = regDBank >> 24 + ORR regDBank, regDBank, rscratch, LSL #16 + MOV rscratch , regX, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , regY, LSR #24 + ORR rscratch , rscratch, regDBank, LSL #16 + S9xSetByteLow rscratch2 + SUB regX, regX, #0x01000000 + SUB regA, regA, #0x00010000 + SUB regY, regY, #0x01000000 + CMP regA, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm +.macro Op44X0M1 + //Save RegStatus = regDBank >> 24 + MOV rscratch, regDBank, LSR #16 + LDRB regDBank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + //Restore RegStatus = regDBank >> 24 + ORR regDBank, regDBank, rscratch, LSL #16 + MOV rscratch , regX, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , regY, LSR #16 + ORR rscratch , rscratch, regDBank, LSL #16 + S9xSetByteLow rscratch2 + //load 16bits A + LDRB rscratch,[regCPUvar,#RAH_ofs] + MOV regA,regA,LSR #8 + ORR regA,regA,rscratch, LSL #24 + SUB regX, regX, #0x00010000 + SUB regA, regA, #0x00010000 + SUB regY, regY, #0x00010000 + CMP regA, #0xFFFF0000 + SUBNE rpc, rpc, #3 + //update AH + MOV rscratch, regA, LSR #24 + MOV regA,regA,LSL #8 + STRB rscratch,[regCPUvar,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op44X0M0 + //Save RegStatus = regDBank >> 24 + MOV rscratch, regDBank, LSR #16 + LDRB regDBank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + //Restore RegStatus = regDBank >> 24 + ORR regDBank, regDBank, rscratch, LSL #16 + MOV rscratch , regX, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , regY, LSR #16 + ORR rscratch , rscratch, regDBank, LSL #16 + S9xSetByteLow rscratch2 + SUB regX, regX, #0x00010000 + SUB regA, regA, #0x00010000 + SUB regY, regY, #0x00010000 + CMP regA, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm + +/**********************************************************************************************/ +/* REP/SEP *********************************************************************************** */ +.macro OpC2 + // status&=~(*rpc++); + // so possible changes are : + // INDEX = 1 -> 0 : X,Y 8bits -> 16bits + // MEM = 1 -> 0 : A 8bits -> 16bits + //SAVE OLD status for MASK_INDEX & MASK_MEM comparison + MOV rscratch3, rstatus + LDRB rscratch, [rpc], #1 + MVN rscratch, rscratch + AND rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER) + TST rstatus,#MASK_EMUL + BEQ 1111f + //emulation mode on : no changes since it was on before opcode + //just be sure to reset MEM & INDEX accordingly + ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX) + B 1112f +1111: + //NOT in Emulation mode, check INDEX & MEMORY bits + //Now check INDEX + TST rscratch3,#MASK_INDEX + BEQ 1113f + // X & Y were 8bit before + TST rstatus,#MASK_INDEX + BNE 1113f + // X & Y are now 16bits + MOV regX,regX,LSR #8 + MOV regY,regY,LSR #8 +1113: //X & Y still in 16bits + //Now check MEMORY + TST rscratch3,#MASK_MEM + BEQ 1112f + // A was 8bit before + TST rstatus,#MASK_MEM + BNE 1112f + // A is now 16bits + MOV regA,regA,LSR #8 + //restore AH + LDREQB rscratch,[regCPUvar,#RAH_ofs] + ORREQ regA,regA,rscratch,LSL #24 +1112: + S9xFixCycles + ADD1CYCLE1MEM +.endm +.macro OpE2 + // status|=*rpc++; + // so possible changes are : + // INDEX = 0 -> 1 : X,Y 16bits -> 8bits + // MEM = 0 -> 1 : A 16bits -> 8bits + //SAVE OLD status for MASK_INDEX & MASK_MEM comparison + MOV rscratch3, rstatus + LDRB rscratch, [rpc], #1 + ORR rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER + TST rstatus,#MASK_EMUL + BEQ 10111f + //emulation mode on : no changes sinc eit was on before opcode + //just be sure to have mem & index set accordingly + ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX) + B 10112f +10111: + //NOT in Emulation mode, check INDEX & MEMORY bits + //Now check INDEX + TST rscratch3,#MASK_INDEX + BNE 10113f + // X & Y were 16bit before + TST rstatus,#MASK_INDEX + BEQ 10113f + // X & Y are now 8bits + MOV regX,regX,LSL #8 + MOV regY,regY,LSL #8 +10113: //X & Y still in 16bits + //Now check MEMORY + TST rscratch3,#MASK_MEM + BNE 10112f + // A was 16bit before + TST rstatus,#MASK_MEM + BEQ 10112f + // A is now 8bits + // save AH + MOV rscratch,regA,LSR #24 + MOV regA,regA,LSL #8 + STRB rscratch,[regCPUvar,#RAH_ofs] +10112: + S9xFixCycles + ADD1CYCLE1MEM +.endm + +/**********************************************************************************************/ +/* XBA *************************************************************************************** */ +.macro OpEBM1 + //A is 8bits + ADD rscratch,regCPUvar,#RAH_ofs + MOV regA,regA, LSR #24 + SWPB regA,regA,[rscratch] + MOVS regA,regA, LSL #24 + UPDATE_ZN + ADD2CYCLE +.endm +.macro OpEBM0 + //A is 16bits + MOV rscratch, regA, ROR #24 // ll0000hh + ORR rscratch, rscratch, regA, LSR #8// ll0000hh + 00hhll00 -> llhhllhh + MOV regA, rscratch, LSL #16// llhhllhh -> llhh0000 + MOVS rscratch,rscratch,LSL #24 //to set Z & N flags with AL + UPDATE_ZN + ADD2CYCLE +.endm + + +/**********************************************************************************************/ +/* RTI *************************************************************************************** */ +.macro Op40X1M1 + //INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC regPBank,regPBank,#0xFF + ORR regPBank,regPBank,rscratch +2401: + ADD rscratch, rpc, regPBank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + //INDEX cleared & was set : 8->16 + MOVEQ regX,regX,LSR #8 + MOVEQ regY,regY,LSR #8 + TST rstatus, #MASK_MEM + //MEMORY cleared & was set : 8->16 + LDREQB rscratch,[regCPUvar,#RAH_ofs] + MOVEQ regA,regA,LSR #8 + ORREQ regA,regA,rscratch, LSL #24 + ADD2CYCLE + S9xFixCycles +.endm +.macro Op40X0M1 + //INDEX cleared, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC regPBank,regPBank,#0xFF + ORR regPBank,regPBank,rscratch +2401: + ADD rscratch, rpc, regPBank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + //INDEX set & was cleared : 16->8 + MOVNE regX,regX,LSL #8 + MOVNE regY,regY,LSL #8 + TST rstatus, #MASK_MEM + //MEMORY cleared & was set : 8->16 + LDREQB rscratch,[regCPUvar,#RAH_ofs] + MOVEQ regA,regA,LSR #8 + ORREQ regA,regA,rscratch, LSL #24 + ADD2CYCLE + S9xFixCycles +.endm +.macro Op40X1M0 + //INDEX set, MEMORY cleared + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC regPBank,regPBank,#0xFF + ORR regPBank,regPBank,rscratch +2401: + ADD rscratch, rpc, regPBank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + //INDEX cleared & was set : 8->16 + MOVEQ regX,regX,LSR #8 + MOVEQ regY,regY,LSR #8 + TST rstatus, #MASK_MEM + //MEMORY set & was cleared : 16->8 + MOVNE rscratch,regA,LSR #24 + MOVNE regA,regA,LSL #8 + STRNEB rscratch,[regCPUvar,#RAH_ofs] + ADD2CYCLE + S9xFixCycles +.endm +.macro Op40X0M0 + //INDEX cleared, MEMORY cleared + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC regPBank,regPBank,#0xFF + ORR regPBank,regPBank,rscratch +2401: + ADD rscratch, rpc, regPBank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + //INDEX set & was cleared : 16->8 + MOVNE regX,regX,LSL #8 + MOVNE regY,regY,LSL #8 + TST rstatus, #MASK_MEM + //MEMORY set & was cleared : 16->8 + //MEMORY set & was cleared : 16->8 + MOVNE rscratch,regA,LSR #24 + MOVNE regA,regA,LSL #8 + STRNEB rscratch,[regCPUvar,#RAH_ofs] + ADD2CYCLE + S9xFixCycles +.endm + + +/**********************************************************************************************/ +/* STP/WAI/DB ******************************************************************************** */ +// WAI +.macro OpCB /*WAI*/ + LDRB rscratch,[regCPUvar,#IRQActive_ofs] + MOVS rscratch,rscratch + //(CPU.IRQActive) + ADD2CYCLENE + BNE 1234f +/* + CPU.WaitingForInterrupt = TRUE; + CPU.PC--;*/ + MOV rscratch,#1 + SUB rpc,rpc,#1 +/* + CPU.Cycles = CPU.NextEvent; +*/ + STRB rscratch,[regCPUvar,#WaitingForInterrupt_ofs] + LDR regCycles,[regCPUvar,#NextEvent_ofs] +/* + if (IAPU.APUExecuting) + { + ICPU.CPUExecuting = FALSE; + do + { + APU_EXECUTE1 (); + } while (APU.Cycles < CPU.NextEvent); + ICPU.CPUExecuting = TRUE; + } +*/ + LDRB rscratch,[regCPUvar,#APUExecuting_ofs] + MOVS rscratch,rscratch + BEQ 1234f + asmAPU_EXECUTE2 + +1234: +.endm +.macro OpDB /*STP*/ + SUB rpc,rpc,#1 + //CPU.Flags |= DEBUG_MODE_FLAG; +.endm +.macro Op42 /*Reserved Snes9X*/ +.endm + +/**********************************************************************************************/ +/* AND ******************************************************************************** */ +.macro Op29M1 + LDRB rscratch , [rpc], #1 + ANDS regA , regA, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro Op29M0 + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + ANDS regA , regA, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + + + + + + + + + + + + + + + +/**********************************************************************************************/ +/* EOR ******************************************************************************** */ +.macro Op49M0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2,LSL #8 + EORS regA, regA, rscratch,LSL #16 + UPDATE_ZN + ADD2MEM +.endm + + +.macro Op49M1 + LDRB rscratch , [rpc], #1 + EORS regA, regA, rscratch,LSL #24 + UPDATE_ZN + ADD1MEM +.endm + + +/**********************************************************************************************/ +/* STA *************************************************************************************** */ +.macro Op81M1 + STA8 + //TST rstatus, #MASK_INDEX + //ADD1CYCLENE +.endm +.macro Op81M0 + STA16 + //TST rstatus, #MASK_INDEX + //ADD1CYCLENE +.endm + + +/**********************************************************************************************/ +/* BIT *************************************************************************************** */ +.macro Op89M1 + LDRB rscratch , [rpc], #1 + TST regA, rscratch, LSL #24 + UPDATE_Z + ADD1MEM +.endm +.macro Op89M0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + TST regA, rscratch, LSL #16 + UPDATE_Z + ADD2MEM +.endm + + + + + + +/**********************************************************************************************/ +/* LDY *************************************************************************************** */ +.macro OpA0X1 + LDRB rscratch , [rpc], #1 + MOVS regY, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro OpA0X0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + MOVS regY, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* LDX *************************************************************************************** */ +.macro OpA2X1 + LDRB rscratch , [rpc], #1 + MOVS regX, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro OpA2X0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + MOVS regX, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* LDA *************************************************************************************** */ +.macro OpA9M1 + LDRB rscratch , [rpc], #1 + MOVS regA, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro OpA9M0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + MOVS regA, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* CMY *************************************************************************************** */ +.macro OpC0X1 + LDRB rscratch , [rpc], #1 + SUBS rscratch2 , regY , rscratch, LSL #24 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD1MEM +.endm +.macro OpC0X0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + SUBS rscratch2 , regY, rscratch, LSL #16 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD2MEM +.endm + + + + + +/**********************************************************************************************/ +/* CMP *************************************************************************************** */ +.macro OpC9M1 + LDRB rscratch , [rpc], #1 + SUBS rscratch2 , regA , rscratch, LSL #24 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD1MEM +.endm +.macro OpC9M0 + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + SUBS rscratch2 , regA, rscratch, LSL #16 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* CMX *************************************************************************************** */ +.macro OpE0X1 + LDRB rscratch , [rpc], #1 + SUBS rscratch2 , regX , rscratch, LSL #24 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD1MEM +.endm +.macro OpE0X0 + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + SUBS rscratch2 , regX, rscratch, LSL #16 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD2MEM +.endm + +/* + + +CLI_OPE_REC_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @treasuryDate, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @accountingDate, 103) + +CLI_OPE_Nos_Ope_Layer0 + n.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + n.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +CLI_OPE_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +Ecrans: +------ + + +[GNV] : utilisation de la lard (laccdate) pour afficher les openings. + +nécessité d'avoir des valeurs dans l'opening pour date tréso=date compta=laccdate + +[Accounting rec] : si laccdate pas bonne (pas = BD-1) -> message warning et pas de donnée +sinon : + +données nécessaires : opening date tréso=date compta=laccdate=BD-1 + +données nécessaires : opening date tréso=date compta=laccdate-1 + +données nécessaires : opening date tréso=laccdate-1 et date compta=laccdate + */ + + +/* + + + + + +*/ diff --git a/src/os9x_65c816_opcodes.s b/src/os9x_65c816_opcodes.s new file mode 100644 index 0000000..6c3cc96 --- /dev/null +++ b/src/os9x_65c816_opcodes.s @@ -0,0 +1,2976 @@ +@ =========================================== +@ =========================================== +@ Adressing mode +@ =========================================== +@ =========================================== + + +.macro Absolute + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc],#2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 +.endm +.macro AbsoluteIndexedIndirectX0 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ADD rscratch , reg_x, rscratch, LSL #16 + MOV rscratch , rscratch, LSR #16 + ORR rscratch , rscratch, reg_p_bank, LSL #16 + S9xGetWordLow + +.endm +.macro AbsoluteIndexedIndirectX1 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ADD rscratch , rscratch, reg_x, LSR #24 + BIC rscratch , rscratch, #0x00FF0000 + ORR rscratch , rscratch, reg_p_bank, LSL #16 + S9xGetWordLow + +.endm +.macro AbsoluteIndirectLong + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch, #2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 +.endm +.macro AbsoluteIndirect + ADD2MEM + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + S9xGetWordLow + ORR rscratch , rscratch, reg_p_bank, LSL #16 +.endm +.macro AbsoluteIndexedX0 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_x, LSR #16 +.endm +.macro AbsoluteIndexedX1 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_x, LSR #24 +.endm + + +.macro AbsoluteIndexedY0 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_y, LSR #16 +.endm +.macro AbsoluteIndexedY1 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_y, LSR #24 +.endm +.macro AbsoluteLong + ADD3MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + LDRB rscratch2 , [rpc], #1 + ORR rscratch , rscratch, rscratch2, LSL #16 +.endm + + +.macro AbsoluteLongIndexedX0 + ADD3MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + LDRB rscratch2 , [rpc], #1 + ORR rscratch , rscratch, rscratch2, LSL #16 + ADD rscratch , rscratch, reg_x, LSR #16 + BIC rscratch, rscratch, #0xFF000000 +.endm +.macro AbsoluteLongIndexedX1 + ADD3MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + LDRB rscratch2 , [rpc], #1 + ORR rscratch , rscratch, rscratch2, LSL #16 + ADD rscratch , rscratch, reg_x, LSR #24 + BIC rscratch, rscratch, #0xFF000000 +.endm +.macro Direct + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndirect + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch , rscratch, reg_d_bank, LSL #16 +.endm +.macro DirectIndirectLong + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch,#2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 +.endm +.macro DirectIndirectIndexed0 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch, rscratch,reg_d_bank, LSL #16 + ADD rscratch, rscratch,reg_y, LSR #16 +.endm +.macro DirectIndirectIndexed1 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch, rscratch,reg_d_bank, LSL #16 + ADD rscratch, rscratch,reg_y, LSR #24 +.endm +.macro DirectIndirectIndexedLong0 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch,#2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 + + ADD rscratch, rscratch,reg_y, LSR #16 +.endm +.macro DirectIndirectIndexedLong1 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch,#2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 + ADD rscratch, rscratch,reg_y, LSR #24 +.endm +.macro DirectIndexedIndirect0 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_x + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch , rscratch , reg_d_bank, LSL #16 +.endm +.macro DirectIndexedIndirect1 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_x, LSR #8 + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch , rscratch , reg_d_bank, LSL #16 +.endm +.macro DirectIndexedX0 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_x + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndexedX1 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_x, LSR #8 + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndexedY0 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_y + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndexedY1 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_y, LSR #8 + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro Immediate8 + ADD rscratch, rpc, reg_p_bank, LSL #16 + SUB rscratch, rscratch, regpcbase + ADD rpc, rpc, #1 +.endm +.macro Immediate16 + ADD rscratch, rpc, reg_p_bank, LSL #16 + SUB rscratch, rscratch, regpcbase + ADD rpc, rpc, #2 +.endm +.macro asmRelative + ADD1MEM + LDRSB rscratch , [rpc],#1 + ADD rscratch , rscratch , rpc + SUB rscratch , rscratch, regpcbase + BIC rscratch,rscratch,#0x00FF0000 + BIC rscratch,rscratch,#0xFF000000 +.endm +.macro asmRelativeLong + ADD1CYCLE2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + SUB rscratch2 , rpc, regpcbase + ADD rscratch , rscratch2, rscratch + BIC rscratch,rscratch,#0x00FF0000 +.endm + + +.macro StackasmRelative + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , rscratch, reg_s + BIC rscratch,rscratch,#0x00FF0000 +.endm +.macro StackasmRelativeIndirectIndexed0 + ADD2CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , rscratch, reg_s + BIC rscratch,rscratch,#0x00FF0000 + S9xGetWordLow + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_y, LSR #16 + BIC rscratch, rscratch, #0xFF000000 +.endm +.macro StackasmRelativeIndirectIndexed1 + ADD2CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , rscratch, reg_s + BIC rscratch,rscratch,#0x00FF0000 + S9xGetWordLow + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_y, LSR #24 + BIC rscratch, rscratch, #0xFF000000 +.endm + + +/****************************************/ +.macro PushB reg + MOV rscratch,reg_s + S9xSetByte \reg + SUB reg_s,reg_s,#1 +.endm +.macro PushBLow reg + MOV rscratch,reg_s + S9xSetByteLow \reg + SUB reg_s,reg_s,#1 +.endm +.macro PushWLow reg + SUB rscratch,reg_s,#1 + S9xSetWordLow \reg + SUB reg_s,reg_s,#2 +.endm +.macro PushWrLow + MOV rscratch2,rscratch + SUB rscratch,reg_s,#1 + S9xSetWordLow rscratch2 + SUB reg_s,reg_s,#2 +.endm +.macro PushW reg + SUB rscratch,reg_s,#1 + S9xSetWord \reg + SUB reg_s,reg_s,#2 +.endm + +/********/ + +.macro PullB reg + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOV \reg,rscratch,LSL #24 +.endm +.macro PullBr + ADD rscratch,reg_s,#1 + S9xGetByte + ADD reg_s,reg_s,#1 +.endm +.macro PullBLow reg + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOV \reg,rscratch +.endm +.macro PullBrLow + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 +.endm +.macro PullW reg + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOV \reg,rscratch,LSL #16 +.endm + +.macro PullWLow reg + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOV \reg,rscratch +.endm + + +/*****************/ +.macro PullBS reg + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOVS \reg,rscratch,LSL #24 +.endm +.macro PullBrS + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOVS rscratch,rscratch,LSL #24 +.endm +.macro PullBLowS reg + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOVS \reg,rscratch +.endm +.macro PullBrLowS + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOVS rscratch,rscratch +.endm +.macro PullWS reg + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOVS \reg,rscratch, LSL #16 +.endm +.macro PullWrS + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOVS rscratch,rscratch, LSL #16 +.endm +.macro PullWLowS reg + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOVS \reg,rscratch +.endm +.macro PullWrLowS + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOVS rscratch,rscratch +.endm + + +/***************************************************************** + FLAGS +*****************************************************************/ + +.macro UPDATE_C + @ CC : ARM Carry Clear + BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + @ CS : ARM Carry Set + ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one +.endm +.macro UPDATE_Z + @ NE : ARM Zero Clear + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + @ EQ : ARM Zero Set + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one +.endm +.macro UPDATE_ZN + @ NE : ARM Zero Clear + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + @ EQ : ARM Zero Set + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + @ PL : ARM Neg Clear + BICPL rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + @ MI : ARM Neg Set + ORRMI rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set N to one +.endm + +/***************************************************************** + OPCODES_MAC +*****************************************************************/ + + + + +.macro ADC8 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + S9xGetByte + + + STMFD R13!,{rscratch} + MOV rscratch4,#0x0F000000 + @ rscratch2=xxW1xxxxxxxxxxxx + AND rscratch2, rscratch, rscratch4 + @ rscratch=xxW2xxxxxxxxxxxx + AND rscratch, rscratch4, rscratch, LSR #4 + @ rscratch3=xxA2xxxxxxxxxxxx + AND rscratch3, rscratch4, reg_a, LSR #4 + @ rscratch4=xxA1xxxxxxxxxxxx + AND rscratch4,reg_a,rscratch4 + @ R1=A1+W1+CARRY + TST rstatus, #MASK_CARRY + ADDNE rscratch2, rscratch2, #0x01000000 + ADD rscratch2,rscratch2,rscratch4 + @ if R1 > 9 + CMP rscratch2, #0x09000000 + @ then R1 -= 10 + SUBGT rscratch2, rscratch2, #0x0A000000 + @ then A2++ + ADDGT rscratch3, rscratch3, #0x01000000 + @ R2 = A2+W2 + ADD rscratch3, rscratch3, rscratch + @ if R2 > 9 + CMP rscratch3, #0x09000000 + @ then R2 -= 10@ + SUBGT rscratch3, rscratch3, #0x0A000000 + @ then SetCarry() + ORRGT rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + @ else ClearCarry() + BICLE rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + @ gather rscratch3 and rscratch2 into ans8 + @ rscratch3 : 0R2000000 + @ rscratch2 : 0R1000000 + @ -> 0xR2R1000000 + ORR rscratch2, rscratch2, rscratch3, LSL #4 + LDMFD R13!,{rscratch} + @ only last bit + AND rscratch,rscratch,#0x80000000 + @ (register.AL ^ Work8) + EORS rscratch3, reg_a, rscratch + BICNE rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + BNE 1112f + @ (Work8 ^ Ans8) + EORS rscratch3, rscratch2, rscratch + @ & 0x80 + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one +1112: + MOVS reg_a, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetByteLow + MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY + SUBCS rscratch, rscratch, #0x100 + ADCS reg_a, reg_a, rscratch, ROR #8 + @ OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + @ Carry + UPDATE_C + @ clear lower part + ANDS reg_a, reg_a, #0xFF000000 + @ Update flag + UPDATE_ZN +1113: +.endm +/* TO TEST */ +.macro ADC16 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + S9xGetWord + + @ rscratch = W3W2W1W0........ + LDR rscratch4, = 0x0F0F0000 + @ rscratch2 = xxW2xxW0xxxxxx + @ rscratch3 = xxW3xxW1xxxxxx + AND rscratch2, rscratch4, rscratch + AND rscratch3, rscratch4, rscratch, LSR #4 + @ rscratch2 = xxW3xxW1xxW2xxW0 + ORR rscratch2, rscratch3, rscratch2, LSR #16 + @ rscratch3 = xxA2xxA0xxxxxx + @ rscratch4 = xxA3xxA1xxxxxx + @ rscratch2 = xxA3xxA1xxA2xxA0 + AND rscratch3, rscratch4, reg_a + AND rscratch4, rscratch4, reg_a, LSR #4 + ORR rscratch3, rscratch4, rscratch3, LSR #16 + ADD rscratch2, rscratch3, rscratch2 + LDR rscratch4, = 0x0F0F0000 + @ rscratch2 = A + W + TST rstatus, #MASK_CARRY + ADDNE rscratch2, rscratch2, #0x1 + @ rscratch2 = A + W + C + @ A0 + AND rscratch3, rscratch2, #0x0000001F + CMP rscratch3, #0x00000009 + ADDHI rscratch2, rscratch2, #0x00010000 + SUBHI rscratch2, rscratch2, #0x0000000A + @ A1 + AND rscratch3, rscratch2, #0x001F0000 + CMP rscratch3, #0x00090000 + ADDHI rscratch2, rscratch2, #0x00000100 + SUBHI rscratch2, rscratch2, #0x000A0000 + @ A2 + AND rscratch3, rscratch2, #0x00001F00 + CMP rscratch3, #0x00000900 + SUBHI rscratch2, rscratch2, #0x00000A00 + ADDHI rscratch2, rscratch2, #0x01000000 + @ A3 + AND rscratch3, rscratch2, #0x1F000000 + CMP rscratch3, #0x09000000 + SUBHI rscratch2, rscratch2, #0x0A000000 + @ SetCarry + ORRHI rstatus, rstatus, #MASK_CARRY + @ ClearCarry + BICLS rstatus, rstatus, #MASK_CARRY + @ rscratch2 = xxR3xxR1xxR2xxR0 + @ Pack result + @ rscratch3 = xxR3xxR1xxxxxxxx + AND rscratch3, rscratch4, rscratch2 + @ rscratch2 = xxR2xxR0xxxxxxxx + AND rscratch2, rscratch4, rscratch2,LSL #16 + @ rscratch2 = R3R2R1R0xxxxxxxx + ORR rscratch2, rscratch2,rscratch3,LSL #4 +@ only last bit + AND rscratch,rscratch,#0x80000000 + @ (register.AL ^ Work8) + EORS rscratch3, reg_a, rscratch + BICNE rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + BNE 1112f + @ (Work8 ^ Ans8) + EORS rscratch3, rscratch2, rscratch + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one +1112: + MOVS reg_a, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetWordLow + MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY + SUBCS rscratch, rscratch, #0x10000 + ADCS reg_a, reg_a,rscratch, ROR #16 + @ OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + MOV reg_a, reg_a, LSR #16 + @ Carry + UPDATE_C + @ clear lower parts + MOVS reg_a, reg_a, LSL #16 + @ Update flag + UPDATE_ZN +1113: +.endm + + +.macro AND16 + S9xGetWord + ANDS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro AND8 + S9xGetByte + ANDS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro A_ASL8 + @ 7 instr + MOVS reg_a, reg_a, LSL #1 + UPDATE_C + UPDATE_ZN + ADD1CYCLE +.endm +.macro A_ASL16 + @ 7 instr + MOVS reg_a, reg_a, LSL #1 + UPDATE_C + UPDATE_ZN + ADD1CYCLE +.endm +.macro ASL16 + S9xGetWordRegNS rscratch2 @ do not destroy Opadress in rscratch + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_C + UPDATE_ZN + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro ASL8 + S9xGetByteRegNS rscratch2 @ do not destroy Opadress in rscratch + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_C + UPDATE_ZN + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro BIT8 + S9xGetByte + MOVS rscratch2, rscratch, LSL #1 + @ Trick in ASM : shift one more bit : ARM C = Snes N + @ ARM N = Snes V + @ If Carry Set, then Set Neg in SNES + BICCC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set C to zero + ORRCS rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set C to one + @ If Neg Set, then Set Overflow in SNES + BICPL rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set N to zero + ORRMI rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set N to one + + @ Now do a real AND with A register + @ Set Zero Flag, bit test + ANDS rscratch2, reg_a, rscratch + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one +.endm + +.macro BIT16 + S9xGetWord + MOVS rscratch2, rscratch, LSL #1 + @ Trick in ASM : shift one more bit : ARM C = Snes N + @ ARM N = Snes V + @ If Carry Set, then Set Neg in SNES + BICCC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + ORRCS rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set N to one + @ If Neg Set, then Set Overflow in SNES + BICPL rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRMI rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one + @ Now do a real AND with A register + @ Set Zero Flag, bit test + ANDS rscratch2, reg_a, rscratch + @ Bit set ->Z=0->xxxNE Clear flag + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + @ Bit clear->Z=1->xxxEQ Set flag + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one +.endm +.macro CMP8 + S9xGetByte + SUBS rscratch2,reg_a,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + +.endm +.macro CMP16 + S9xGetWord + SUBS rscratch2,reg_a,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + +.endm +.macro CMX16 + S9xGetWord + SUBS rscratch2,reg_x,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro CMX8 + S9xGetByte + SUBS rscratch2,reg_x,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro CMY16 + S9xGetWord + SUBS rscratch2,reg_y,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro CMY8 + S9xGetByte + SUBS rscratch2,reg_y,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro A_DEC8 + @MOV rscratch,#0 + SUBS reg_a, reg_a, #0x01000000 + @STR rscratch,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro A_DEC16 + @MOV rscratch,#0 + SUBS reg_a, reg_a, #0x00010000 + @STR rscratch,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro DEC16 + S9xGetWordRegNS rscratch2 @ do not destroy Opadress in rscratch + @MOV rscratch3,#0 + SUBS rscratch2, rscratch2, #0x00010000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro DEC8 + S9xGetByteRegNS rscratch2 @ do not destroy Opadress in rscratch + @MOV rscratch3,#0 + SUBS rscratch2, rscratch2, #0x01000000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro EOR16 + S9xGetWord + EORS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro EOR8 + S9xGetByte + EORS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro A_INC8 + @MOV rscratch3,#0 + ADDS reg_a, reg_a, #0x01000000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro A_INC16 + @MOV rscratch3,#0 + ADDS reg_a, reg_a, #0x00010000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro INC16 + S9xGetWordRegNS rscratch2 + @MOV rscratch3,#0 + ADDS rscratch2, rscratch2, #0x00010000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro INC8 + S9xGetByteRegNS rscratch2 + @MOV rscratch3,#0 + ADDS rscratch2, rscratch2, #0x01000000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro LDA16 + S9xGetWordRegStatus reg_a + UPDATE_ZN +.endm +.macro LDA8 + S9xGetByteRegStatus reg_a + UPDATE_ZN +.endm +.macro LDX16 + S9xGetWordRegStatus reg_x + UPDATE_ZN +.endm +.macro LDX8 + S9xGetByteRegStatus reg_x + UPDATE_ZN +.endm +.macro LDY16 + S9xGetWordRegStatus reg_y + UPDATE_ZN +.endm +.macro LDY8 + S9xGetByteRegStatus reg_y + UPDATE_ZN +.endm +.macro A_LSR16 + BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + MOVS reg_a, reg_a, LSR #17 @ hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll + @ Update Zero + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + MOV reg_a, reg_a, LSL #16 @ -> 0lllllll 00000000 00000000 00000000 + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + @ Note : the two MOV are included between instruction, to optimize + @ the pipeline. + UPDATE_C + ADD1CYCLE +.endm +.macro A_LSR8 + BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + MOVS reg_a, reg_a, LSR #25 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll + @ Update Zero + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + MOV reg_a, reg_a, LSL #24 @ -> 00000000 00000000 00000000 0lllllll + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + @ Note : the two MOV are included between instruction, to optimize + @ the pipeline. + UPDATE_C + ADD1CYCLE +.endm +.macro LSR16 + S9xGetWordRegNS rscratch2 + @ N set to zero by >> 1 LSR + BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + MOVS rscratch2, rscratch2, LSR #17 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll + @ Update Carry + BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + @ Update Zero + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + S9xSetWordLow rscratch2 + ADD1CYCLE +.endm +.macro LSR8 + S9xGetByteRegNS rscratch2 + @ N set to zero by >> 1 LSR + BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + MOVS rscratch2, rscratch2, LSR #25 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll + @ Update Carry + BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + @ Update Zero + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + S9xSetByteLow rscratch2 + ADD1CYCLE +.endm +.macro ORA8 + S9xGetByte + ORRS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro ORA16 + S9xGetWord + ORRS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro A_ROL16 + TST rstatus, #MASK_CARRY + ORRNE reg_a, reg_a, #0x00008000 + MOVS reg_a, reg_a, LSL #1 + UPDATE_ZN + UPDATE_C + ADD1CYCLE +.endm +.macro A_ROL8 + TST rstatus, #MASK_CARRY + ORRNE reg_a, reg_a, #0x00800000 + MOVS reg_a, reg_a, LSL #1 + UPDATE_ZN + UPDATE_C + ADD1CYCLE +.endm +.macro ROL16 + S9xGetWordRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00008000 + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_ZN + UPDATE_C + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro ROL8 + S9xGetByteRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00800000 + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_ZN + UPDATE_C + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro A_ROR16 + MOV reg_a,reg_a, LSR #16 + TST rstatus, #MASK_CARRY + ORRNE reg_a, reg_a, #0x00010000 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS reg_a,reg_a,LSR #1 + UPDATE_C + UPDATE_Z + MOV reg_a,reg_a, LSL #16 + ADD1CYCLE +.endm +.macro A_ROR8 + MOV reg_a,reg_a, LSR #24 + TST rstatus, #MASK_CARRY + ORRNE reg_a, reg_a, #0x00000100 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS reg_a,reg_a,LSR #1 + UPDATE_C + UPDATE_Z + MOV reg_a,reg_a, LSL #24 + ADD1CYCLE +.endm +.macro ROR16 + S9xGetWordLowRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00010000 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS rscratch2,rscratch2,LSR #1 + UPDATE_C + UPDATE_Z + S9xSetWordLow rscratch2 + ADD1CYCLE + +.endm +.macro ROR8 + S9xGetByteLowRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00000100 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS rscratch2,rscratch2,LSR #1 + UPDATE_C + UPDATE_Z + S9xSetByteLow rscratch2 + ADD1CYCLE +.endm + +.macro SBC16 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + @ TODO + S9xGetWord + + STMFD R13!,{rscratch9} + MOV rscratch9,#0x000F0000 + @ rscratch2 - result + @ rscratch3 - scratch + @ rscratch4 - scratch + @ rscratch9 - pattern + + AND rscratch2, rscratch, #0x000F0000 + TST rstatus, #MASK_CARRY + ADDEQ rscratch2, rscratch2, #0x00010000 @ W1=W1+!Carry + AND rscratch4, reg_a, #0x000F0000 + SUB rscratch2, rscratch4,rscratch2 @ R1=A1-W1-!Carry + CMP rscratch2, #0x00090000 @ if R1 > 9 + ADDHI rscratch2, rscratch2, #0x000A0000 @ then R1 += 10 + AND rscratch2, rscratch2, #0x000F0000 + + AND rscratch3, rscratch9, rscratch, LSR #4 + ADDHI rscratch3, rscratch3, #0x00010000 @ then (W2++) + + AND rscratch4, rscratch9, reg_a, LSR #4 + SUB rscratch3, rscratch4, rscratch3 @ R2=A2-W2 + CMP rscratch3, #0x00090000 @ if R2 > 9 + ADDHI rscratch3, rscratch3, #0x000A0000 @ then R2 += 10 + AND rscratch3, rscratch3, #0x000F0000 + ORR rscratch2, rscratch2, rscratch3,LSL #4 + + AND rscratch3, rscratch9, rscratch, LSR #8 + ADDHI rscratch3, rscratch3, #0x00010000 @ then (W3++) + + AND rscratch4, rscratch9, reg_a, LSR #8 + SUB rscratch3, rscratch4, rscratch3 @ R3=A3-W3 + CMP rscratch3, #0x00090000 @ if R3 > 9 + ADDHI rscratch3, rscratch3, #0x000A0000 @ then R3 += 10 + AND rscratch3, rscratch3, #0x000F0000 + ORR rscratch2, rscratch2, rscratch3,LSL #8 + + AND rscratch3, rscratch9, rscratch, LSR #12 + ADDHI rscratch3, rscratch3, #0x00010000 @ then (W3++) + + AND rscratch4, rscratch9, reg_a, LSR #12 + SUB rscratch3, rscratch4, rscratch3 @ R4=A4-W4 + CMP rscratch3, #0x00090000 @ if R4 > 9 + ADDHI rscratch3, rscratch3, #0x000A0000 @ then R4 += 10 + BICHI rstatus, rstatus, #MASK_CARRY @ then ClearCarry + ORRLS rstatus, rstatus, #MASK_CARRY @ else SetCarry + + AND rscratch3,rscratch3,#0x000F0000 + ORR rscratch2,rscratch2,rscratch3,LSL #12 + + LDMFD R13!,{rscratch9} + @ only last bit + AND reg_a,reg_a,#0x80000000 + @ (register.A.W ^ Work8) + EORS rscratch3, reg_a, rscratch + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + BEQ 1112f + @ (register.A.W ^ Ans8) + EORS rscratch3, reg_a, rscratch2 + @ & 0x80 + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one +1112: + MOVS reg_a, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetWordLow + MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY + SBCS reg_a, reg_a, rscratch, LSL #16 + @ OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + MOV reg_a, reg_a, LSR #16 + @ Carry + UPDATE_C + MOVS reg_a, reg_a, LSL #16 + @ Update flag + UPDATE_ZN +1113: +.endm + +.macro SBC8 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + S9xGetByte + STMFD R13!,{rscratch} + MOV rscratch4,#0x0F000000 + @ rscratch2=xxW1xxxxxxxxxxxx + AND rscratch2, rscratch, rscratch4 + @ rscratch=xxW2xxxxxxxxxxxx + AND rscratch, rscratch4, rscratch, LSR #4 + @ rscratch3=xxA2xxxxxxxxxxxx + AND rscratch3, rscratch4, reg_a, LSR #4 + @ rscratch4=xxA1xxxxxxxxxxxx + AND rscratch4,reg_a,rscratch4 + @ R1=A1-W1-!CARRY + TST rstatus, #MASK_CARRY + ADDEQ rscratch2, rscratch2, #0x01000000 + SUB rscratch2,rscratch4,rscratch2 + @ if R1 > 9 + CMP rscratch2, #0x09000000 + @ then R1 += 10 + ADDHI rscratch2, rscratch2, #0x0A000000 + @ then A2-- (W2++) + ADDHI rscratch, rscratch, #0x01000000 + @ R2=A2-W2 + SUB rscratch3, rscratch3, rscratch + @ if R2 > 9 + CMP rscratch3, #0x09000000 + @ then R2 -= 10@ + ADDHI rscratch3, rscratch3, #0x0A000000 + @ then SetCarry() + BICHI rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + @ else ClearCarry() + ORRLS rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + @ gather rscratch3 and rscratch2 into ans8 + AND rscratch3,rscratch3,#0x0F000000 + AND rscratch2,rscratch2,#0x0F000000 + @ rscratch3 : 0R2000000 + @ rscratch2 : 0R1000000 + @ -> 0xR2R1000000 + ORR rscratch2, rscratch2, rscratch3, LSL #4 + LDMFD R13!,{rscratch} + @ only last bit + AND reg_a,reg_a,#0x80000000 + @ (register.AL ^ Work8) + EORS rscratch3, reg_a, rscratch + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + BEQ 1112f + @ (register.AL ^ Ans8) + EORS rscratch3, reg_a, rscratch2 + @ & 0x80 + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one +1112: + MOVS reg_a, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetByteLow + MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY + SBCS reg_a, reg_a, rscratch, LSL #24 + @ OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + @ Carry + UPDATE_C + @ Update flag + ANDS reg_a, reg_a, #0xFF000000 + UPDATE_ZN +1113: +.endm + +.macro STA16 + S9xSetWord reg_a +.endm +.macro STA8 + S9xSetByte reg_a +.endm +.macro STX16 + S9xSetWord reg_x +.endm +.macro STX8 + S9xSetByte reg_x +.endm +.macro STY16 + S9xSetWord reg_y +.endm +.macro STY8 + S9xSetByte reg_y +.endm +.macro STZ16 + S9xSetWordZero +.endm +.macro STZ8 + S9xSetByteZero +.endm +.macro TSB16 + S9xGetWordRegNS rscratch2 + TST reg_a, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + ORR rscratch2, reg_a, rscratch2 + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro TSB8 + S9xGetByteRegNS rscratch2 + TST reg_a, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + ORR rscratch2, reg_a, rscratch2 + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro TRB16 + S9xGetWordRegNS rscratch2 + TST reg_a, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + MVN rscratch3, reg_a + AND rscratch2, rscratch3, rscratch2 + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro TRB8 + S9xGetByteRegNS rscratch2 + TST reg_a, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + MVN rscratch3, reg_a + AND rscratch2, rscratch3, rscratch2 + S9xSetByte rscratch2 + ADD1CYCLE +.endm +/**************************************************************************/ + + +/**************************************************************************/ + +.macro Op09M0 /*ORA*/ + LDRB rscratch2, [rpc,#1] + LDRB rscratch, [rpc], #2 + ORR rscratch2,rscratch,rscratch2,LSL #8 + ORRS reg_a,reg_a,rscratch2,LSL #16 + UPDATE_ZN + ADD2MEM +.endm +.macro Op09M1 /*ORA*/ + LDRB rscratch, [rpc], #1 + ORRS reg_a,reg_a,rscratch,LSL #24 + UPDATE_ZN + ADD1MEM +.endm +/***********************************************************************/ +.macro Op90 /*BCC*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_CARRY + BNE 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +1111: +.endm +.macro OpB0 /*BCS*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_CARRY + BEQ 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +1111: +.endm +.macro OpF0 /*BEQ*/ + asmRelative + BranchCheck2 + TST rstatus, #MASK_ZERO + BEQ 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +1111: +.endm +.macro OpD0 /*BNE*/ + asmRelative + BranchCheck1 + TST rstatus, #MASK_ZERO + BNE 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +1111: +.endm +.macro Op30 /*BMI*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_NEG + BEQ 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +1111: +.endm +.macro Op10 /*BPL*/ + asmRelative + BranchCheck1 + TST rstatus, #MASK_NEG @ neg, z!=0, NE + BNE 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLEX 1 + CPUShutdown +1111: +.endm +.macro Op50 /*BVC*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE + BNE 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLEX 1 + CPUShutdown +1111: +.endm +.macro Op70 /*BVS*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE + BEQ 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLEX 1 + CPUShutdown +1111: +.endm +.macro Op80 /*BRA*/ + asmRelative + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLEX 1 + CPUShutdown +1111: +.endm +/*******************************************************************************************/ +/************************************************************/ +/* SetFlag Instructions ********************************************************************** */ +.macro Op38 /*SEC*/ + ORR rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + ADD1CYCLE +.endm +.macro OpF8 /*SED*/ + SetDecimal + ADD1CYCLE +.endm +.macro Op78 /*SEI*/ + SetIRQ + ADD1CYCLE +.endm + + +/****************************************************************************************/ +/* ClearFlag Instructions ******************************************************************** */ +.macro Op18 /*CLC*/ + BIC rstatus, rstatus, #MASK_CARRY + ADD1CYCLE +.endm +.macro OpD8 /*CLD*/ + ClearDecimal + ADD1CYCLE +.endm +.macro Op58 /*CLI*/ + ClearIRQ + ADD1CYCLE + @ CHECK_FOR_IRQ +.endm +.macro OpB8 /*CLV*/ + BIC rstatus, rstatus, #MASK_OVERFLOW + ADD1CYCLE +.endm + +/******************************************************************************************/ +/* DEX/DEY *********************************************************************************** */ + +.macro OpCAX1 /*DEX*/ + @MOV rscratch3,#0 + SUBS reg_x, reg_x, #0x01000000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpCAX0 /*DEX*/ + @MOV rscratch3,#0 + SUBS reg_x, reg_x, #0x00010000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op88X1 /*DEY*/ + @MOV rscratch3,#0 + SUBS reg_y, reg_y, #0x01000000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op88X0 /*DEY*/ + @MOV rscratch3,#0 + SUBS reg_y, reg_y, #0x00010000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm + +/******************************************************************************************/ +/* INX/INY *********************************************************************************** */ +.macro OpE8X1 + @MOV rscratch3,#0 + ADDS reg_x, reg_x, #0x01000000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpE8X0 + @MOV rscratch3,#0 + ADDS reg_x, reg_x, #0x00010000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpC8X1 + @MOV rscratch3,#0 + ADDS reg_y, reg_y, #0x01000000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpC8X0 + @MOV rscratch3,#0 + ADDS reg_y, reg_y, #0x00010000 + @STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + bic rstatus, rstatus, #MASK_SHUTDOWN + UPDATE_ZN + ADD1CYCLE +.endm + +/**********************************************************************************************/ + +/* NOP *************************************************************************************** */ +.macro OpEA + ADD1CYCLE +.endm + +/**************************************************************************/ +/* PUSH Instructions **************************************************** */ +.macro OpF4 + Absolute + PushWrLow +.endm +.macro OpD4 + DirectIndirect + PushWrLow +.endm +.macro Op62 + asmRelativeLong + PushWrLow +.endm +.macro Op48M0 + PushW reg_a + ADD1CYCLE +.endm +.macro Op48M1 + PushB reg_a + ADD1CYCLE +.endm +.macro Op8B + AND rscratch2, reg_d_bank, #0xFF + PushBLow rscratch2 + ADD1CYCLE +.endm +.macro Op0B + PushW reg_d + ADD1CYCLE +.endm +.macro Op4B + PushBlow reg_p_bank + ADD1CYCLE +.endm +.macro Op08 + PushB rstatus + ADD1CYCLE +.endm +.macro OpDAX1 + PushB reg_x + ADD1CYCLE +.endm +.macro OpDAX0 + PushW reg_x + ADD1CYCLE +.endm +.macro Op5AX1 + PushB reg_y + ADD1CYCLE +.endm +.macro Op5AX0 + PushW reg_y + ADD1CYCLE +.endm +/**************************************************************************/ +/* PULL Instructions **************************************************** */ +.macro Op68M1 + PullBS reg_a + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op68M0 + PullWS reg_a + UPDATE_ZN + ADD2CYCLE +.endm +.macro OpAB + BIC reg_d_bank,reg_d_bank, #0xFF + PullBrS + ORR reg_d_bank,reg_d_bank,rscratch, LSR #24 + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op2B + BIC reg_d,reg_d, #0xFF000000 + BIC reg_d,reg_d, #0x00FF0000 + PullWrS + ORR reg_d,rscratch,reg_d + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op28X1M1 /*PLP*/ + @ INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + @ INDEX clear & was set : 8->16 + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus, #MASK_MEM + @ MEMORY cleared & was set : 8->16 + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSR #8 + ORREQ reg_a,reg_a,rscratch, LSL #24 + S9xFixCycles + ADD2CYCLE +.endm +.macro Op28X0M1 /*PLP*/ + @ INDEX cleared, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + @ INDEX set & was cleared : 16->8 + MOVNE reg_x,reg_x,LSL #8 + MOVNE reg_y,reg_y,LSL #8 + TST rstatus, #MASK_MEM + @ MEMORY cleared & was set : 8->16 + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSR #8 + ORREQ reg_a,reg_a,rscratch, LSL #24 + S9xFixCycles + ADD2CYCLE +.endm +.macro Op28X1M0 /*PLP*/ + @ INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + @ INDEX clear & was set : 8->16 + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus, #MASK_MEM + @ MEMORY set & was cleared : 16->8 + MOVNE rscratch,reg_a,LSR #24 + MOVNE reg_a,reg_a,LSL #8 + STRNEB rscratch,[reg_cpu_var,#RAH_ofs] + S9xFixCycles + ADD2CYCLE +.endm +.macro Op28X0M0 /*PLP*/ + @ INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + @ INDEX set & was cleared : 16->8 + MOVNE reg_x,reg_x,LSL #8 + MOVNE reg_y,reg_y,LSL #8 + TST rstatus, #MASK_MEM + @ MEMORY set & was cleared : 16->8 + MOVNE rscratch,reg_a,LSR #24 + MOVNE reg_a,reg_a,LSL #8 + STRNEB rscratch,[reg_cpu_var,#RAH_ofs] + S9xFixCycles + ADD2CYCLE +.endm +.macro OpFAX1 + PullBS reg_x + UPDATE_ZN + ADD2CYCLE +.endm +.macro OpFAX0 + PullWS reg_x + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op7AX1 + PullBS reg_y + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op7AX0 + PullWS reg_y + UPDATE_ZN + ADD2CYCLE +.endm + +/**********************************************************************************************/ +/* Transfer Instructions ********************************************************************* */ +.macro OpAAX1M1 /*TAX8*/ + MOVS reg_x, reg_a + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpAAX0M1 /*TAX16*/ + LDRB reg_x, [reg_cpu_var,#RAH_ofs] + MOV reg_x, reg_x,LSL #24 + ORRS reg_x, reg_x,reg_a, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpAAX1M0 /*TAX8*/ + MOVS reg_x, reg_a, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpAAX0M0 /*TAX16*/ + MOVS reg_x, reg_a + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X1M1 /*TAY8*/ + MOVS reg_y, reg_a + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X0M1 /*TAY16*/ + LDRB reg_y, [reg_cpu_var,#RAH_ofs] + MOV reg_y, reg_y,LSL #24 + ORRS reg_y, reg_y,reg_a, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X1M0 /*TAY8*/ + MOVS reg_y, reg_a, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X0M0 /*TAY16*/ + MOVS reg_y, reg_a + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op5BM1 + LDRB rscratch, [reg_cpu_var,#RAH_ofs] + MOV reg_d,reg_d,LSL #16 + MOV rscratch,rscratch,LSL #24 + ORRS rscratch,rscratch,reg_a, LSR #8 + UPDATE_ZN + ORR reg_d,rscratch,reg_d,LSR #16 + ADD1CYCLE +.endm +.macro Op5BM0 + MOV reg_d,reg_d,LSL #16 + MOVS reg_a,reg_a + UPDATE_ZN + ORR reg_d,reg_a,reg_d,LSR #16 + ADD1CYCLE +.endm +.macro Op1BM1 + TST rstatus, #MASK_EMUL + MOVNE reg_s, reg_a, LSR #24 + ORRNE reg_s, reg_s, #0x100 + LDREQB reg_s, [reg_cpu_var,#RAH_ofs] + ORREQ reg_s, reg_s, reg_a + MOVEQ reg_s, reg_s, ROR #24 + ADD1CYCLE +.endm +.macro Op1BM0 + MOV reg_s, reg_a, LSR #16 + ADD1CYCLE +.endm +.macro Op7BM1 + MOVS reg_a, reg_d, ASR #16 + UPDATE_ZN + MOV rscratch,reg_a,LSR #8 + MOV reg_a,reg_a, LSL #24 + STRB rscratch, [reg_cpu_var,#RAH_ofs] + ADD1CYCLE +.endm +.macro Op7BM0 + MOVS reg_a, reg_d, ASR #16 + UPDATE_ZN + MOV reg_a,reg_a, LSL #16 + ADD1CYCLE +.endm +.macro Op3BM1 + MOV rscratch,reg_s, LSR #8 + MOVS reg_a, reg_s, LSL #16 + STRB rscratch, [reg_cpu_var,#RAH_ofs] + UPDATE_ZN + MOV reg_a,reg_a, LSL #8 + ADD1CYCLE +.endm +.macro Op3BM0 + MOVS reg_a, reg_s, LSL #16 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBAX1 + MOVS reg_x, reg_s, LSL #24 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBAX0 + MOVS reg_x, reg_s, LSL #16 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM1X1 + MOVS reg_a, reg_x + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM1X0 + MOVS reg_a, reg_x, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM0X1 + MOVS reg_a, reg_x, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM0X0 + MOVS reg_a, reg_x + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op9AX1 + MOV reg_s, reg_x, LSR #24 + + TST rstatus, #MASK_EMUL + ORRNE reg_s, reg_s, #0x100 + ADD1CYCLE +.endm +.macro Op9AX0 + MOV reg_s, reg_x, LSR #16 + ADD1CYCLE +.endm +.macro Op9BX1 + MOVS reg_y, reg_x + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op9BX0 + MOVS reg_y, reg_x + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M1X1 + MOVS reg_a, reg_y + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M1X0 + MOVS reg_a, reg_y, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M0X1 + MOVS reg_a, reg_y, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M0X0 + MOVS reg_a, reg_y + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBBX1 + MOVS reg_x, reg_y + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBBX0 + MOVS reg_x, reg_y + UPDATE_ZN + ADD1CYCLE +.endm + +/**********************************************************************************************/ +/* XCE *************************************************************************************** */ + +.macro OpFB + TST rstatus,#MASK_CARRY + BEQ 1111f + @ CARRY is set + TST rstatus,#MASK_EMUL + BNE 1112f + @ EMUL is cleared + BIC rstatus,rstatus,#(MASK_CARRY) + TST rstatus,#MASK_INDEX + @ X & Y were 16bits before + MOVEQ reg_x,reg_x,LSL #8 + MOVEQ reg_y,reg_y,LSL #8 + TST rstatus,#MASK_MEM + @ A was 16bits before + @ save AH + MOVEQ rscratch,reg_a,LSR #24 + STREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSL #8 + ORR rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX) + AND reg_s,reg_s,#0xFF + ORR reg_s,reg_s,#0x100 + B 1113f +1112: + @ EMUL is set + TST rstatus,#MASK_INDEX + @ X & Y were 16bits before + MOVEQ reg_x,reg_x,LSL #8 + MOVEQ reg_y,reg_y,LSL #8 + TST rstatus,#MASK_MEM + @ A was 16bits before + @ save AH + MOVEQ rscratch,reg_a,LSR #24 + STREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSL #8 + ORR rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX) + AND reg_s,reg_s,#0xFF + ORR reg_s,reg_s,#0x100 + B 1113f +1111: + @ CARRY is cleared + TST rstatus,#MASK_EMUL + BEQ 1115f + @ EMUL was set : X,Y & A were 8bits + @ Now have to check MEMORY & INDEX for potential conversions to 16bits + TST rstatus,#MASK_INDEX + @ X & Y are now 16bits + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus,#MASK_MEM + @ A is now 16bits + MOVEQ reg_a,reg_a,LSR #8 + @ restore AH + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + ORREQ reg_a,reg_a,rscratch,LSL #24 +1115: + BIC rstatus,rstatus,#(MASK_EMUL) + ORR rstatus,rstatus,#(MASK_CARRY) +1113: + ADD1CYCLE + S9xFixCycles +.endm + +/*******************************************************************************/ +/* BRK *************************************************************************/ +.macro Op00 /*BRK*/ + MOV rscratch,#1 + STRB rscratch,[reg_cpu_var,#BRKTriggered_ofs] + + TST rstatus, #MASK_EMUL + @ EQ is flag to zero (!CheckEmu) + BNE 2001f@ elseOp00 + PushBLow reg_p_bank + SUB rscratch, rpc, regpcbase + ADD rscratch2, rscratch, #1 + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank, reg_p_bank, #0xFF + MOV rscratch, #0xE6 + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD2CYCLEX 8 + B 2002f@ endOp00 +2001:@ elseOp00 + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank,reg_p_bank, #0xFF + MOV rscratch, #0xFE + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD1CYCLEX 6 +2002:@ endOp00 +.endm + + +/**********************************************************************************************/ +/* BRL ************************************************************************************** */ +.macro Op82 /*BRL*/ + asmRelativeLong + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase +.endm +/**********************************************************************************************/ +/* IRQ *************************************************************************************** */ +@ void S9xOpcode_IRQ (void) +.macro S9xOpcode_IRQ @ IRQ + TST rstatus, #MASK_EMUL + @ EQ is flag to zero (!CheckEmu) + BNE 2121f@ elseOp02 + PushBLow reg_p_bank + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank, reg_p_bank,#0xFF + MOV rscratch, #0xEE + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + @ADD2CYCLE + ADD2CYCLEX 8 + B 2122f +2121:@ else + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank,reg_p_bank, #0xFF + MOV rscratch, #0xFE + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + @ADD1CYCLE + ADD1CYCLEX 6 +2122: +.endm + +/* +void asm_S9xOpcode_IRQ(void) +{ + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + S9xSetPCBase (S9xGetWord (0xFFEE)); + CPU.Cycles += TWO_CYCLES; + } + else + { + PushW (CPU.PC - CPU.PCBase); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + S9xSetPCBase (S9xGetWord (0xFFFE)); + CPU.Cycles += ONE_CYCLE; + } +} +*/ + +/**********************************************************************************************/ +/* NMI *************************************************************************************** */ +@ void S9xOpcode_NMI (void) +.macro S9xOpcode_NMI @ NMI + TST rstatus, #MASK_EMUL + @ EQ is flag to zero (!CheckEmu) + BNE 2123f@ elseOp02 + PushBLow reg_p_bank + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank, reg_p_bank,#0xFF + MOV rscratch, #0xEA + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + @ADD2CYCLE + ADD2CYCLEX 8 + B 2124f +2123:@ else + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank,reg_p_bank, #0xFF + MOV rscratch, #0xFA + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + @ADD1CYCLE + ADD1CYCLEX 6 +2124: +.endm +/* +void asm_S9xOpcode_NMI(void) +{ + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + S9xSetPCBase (S9xGetWord (0xFFEA)); + CPU.Cycles += TWO_CYCLES; + } + else + { + PushW (CPU.PC - CPU.PCBase); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + S9xSetPCBase (S9xGetWord (0xFFFA)); + CPU.Cycles += ONE_CYCLE; + } +} +*/ + +/**********************************************************************************************/ +/* COP *************************************************************************************** */ +.macro Op02 /*COP*/ + TST rstatus, #MASK_EMUL + @ EQ is flag to zero (!CheckEmu) + BNE 2021f@ elseOp02 + PushBLow reg_p_bank + SUB rscratch, rpc, regpcbase + ADD rscratch2, rscratch, #1 + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank, reg_p_bank,#0xFF + MOV rscratch, #0xE4 + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD2CYCLEX 8 + B 2022f@ endOp02 +2021:@ elseOp02 + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank,reg_p_bank, #0xFF + MOV rscratch, #0xF4 + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD1CYCLEX 6 +2022:@ endOp02 +.endm + +/**********************************************************************************************/ +/* JML *************************************************************************************** */ +.macro OpDC + AbsoluteIndirectLong + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank, rscratch, LSR #16 + S9xSetPCBase + ADD2CYCLE +.endm +.macro Op5C + AbsoluteLong + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank, rscratch, LSR #16 + S9xSetPCBase +.endm + +/**********************************************************************************************/ +/* JMP *************************************************************************************** */ +.macro Op4C + Absolute + BIC rscratch, rscratch, #0xFF0000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + CPUShutdown +.endm +.macro Op6C + AbsoluteIndirect + BIC rscratch, rscratch, #0xFF0000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase +.endm +.macro Op7C + ADD rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm + +/**********************************************************************************************/ +/* JSL/RTL *********************************************************************************** */ +.macro Op22 + PushBlow reg_p_bank + SUB rscratch, rpc, regpcbase + @ SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #2 + PushWlow rscratch2 + AbsoluteLong + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank, reg_p_bank, rscratch, LSR #16 + S9xSetPCBase +.endm +.macro Op6B + PullWLow rpc + BIC reg_p_bank,reg_p_bank,#0xFF + PullBrLow + ORR reg_p_bank, reg_p_bank, rscratch + ADD rscratch, rpc, #1 + BIC rscratch, rscratch,#0xFF0000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD2CYCLE +.endm +/**********************************************************************************************/ +/* JSR/RTS *********************************************************************************** */ +.macro Op20 + SUB rscratch, rpc, regpcbase + @ SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #1 + PushWlow rscratch2 + Absolute + BIC rscratch, rscratch, #0xFF0000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm +.macro OpFCX0 + SUB rscratch, rpc, regpcbase + @ SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #1 + PushWlow rscratch2 + AbsoluteIndexedIndirectX0 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm +.macro OpFCX1 + SUB rscratch, rpc, regpcbase + @ SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #1 + PushWlow rscratch2 + AbsoluteIndexedIndirectX1 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm +.macro Op60 + PullWLow rpc + ADD rscratch, rpc, #1 + BIC rscratch, rscratch,#0x10000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD3CYCLE +.endm + +/**********************************************************************************************/ +/* MVN/MVP *********************************************************************************** */ +.macro Op54X1M1 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #24 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + @ load 16bits A + LDRB rscratch,[reg_cpu_var,#RAH_ofs] + MOV reg_a,reg_a,LSR #8 + ORR reg_a,reg_a,rscratch, LSL #24 + ADD reg_x, reg_x, #0x01000000 + SUB reg_a, reg_a, #0x00010000 + ADD reg_y, reg_y, #0x01000000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + @ update AH + MOV rscratch, reg_a, LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op54X1M0 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #24 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + ADD reg_x, reg_x, #0x01000000 + SUB reg_a, reg_a, #0x00010000 + ADD reg_y, reg_y, #0x01000000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm +.macro Op54X0M1 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #16 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + @ load 16bits A + LDRB rscratch,[reg_cpu_var,#RAH_ofs] + MOV reg_a,reg_a,LSR #8 + ORR reg_a,reg_a,rscratch, LSL #24 + ADD reg_x, reg_x, #0x00010000 + SUB reg_a, reg_a, #0x00010000 + ADD reg_y, reg_y, #0x00010000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + @ update AH + MOV rscratch, reg_a, LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op54X0M0 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #16 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + ADD reg_x, reg_x, #0x00010000 + SUB reg_a, reg_a, #0x00010000 + ADD reg_y, reg_y, #0x00010000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm + +.macro Op44X1M1 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #24 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + @ load 16bits A + LDRB rscratch,[reg_cpu_var,#RAH_ofs] + MOV reg_a,reg_a,LSR #8 + ORR reg_a,reg_a,rscratch, LSL #24 + SUB reg_x, reg_x, #0x01000000 + SUB reg_a, reg_a, #0x00010000 + SUB reg_y, reg_y, #0x01000000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + @ update AH + MOV rscratch, reg_a, LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op44X1M0 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #24 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + SUB reg_x, reg_x, #0x01000000 + SUB reg_a, reg_a, #0x00010000 + SUB reg_y, reg_y, #0x01000000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm +.macro Op44X0M1 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #16 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + @ load 16bits A + LDRB rscratch,[reg_cpu_var,#RAH_ofs] + MOV reg_a,reg_a,LSR #8 + ORR reg_a,reg_a,rscratch, LSL #24 + SUB reg_x, reg_x, #0x00010000 + SUB reg_a, reg_a, #0x00010000 + SUB reg_y, reg_y, #0x00010000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + @ update AH + MOV rscratch, reg_a, LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op44X0M0 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #16 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + SUB reg_x, reg_x, #0x00010000 + SUB reg_a, reg_a, #0x00010000 + SUB reg_y, reg_y, #0x00010000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm + +/**********************************************************************************************/ +/* REP/SEP *********************************************************************************** */ +.macro OpC2 + @ status&=~(*rpc++); + @ so possible changes are : + @ INDEX = 1 -> 0 : X,Y 8bits -> 16bits + @ MEM = 1 -> 0 : A 8bits -> 16bits + @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison + MOV rscratch3, rstatus + LDRB rscratch, [rpc], #1 + MVN rscratch, rscratch + AND rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER) + TST rstatus,#MASK_EMUL + BEQ 1111f + @ emulation mode on : no changes since it was on before opcode + @ just be sure to reset MEM & INDEX accordingly + ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX) + B 1112f +1111: + @ NOT in Emulation mode, check INDEX & MEMORY bits + @ Now check INDEX + TST rscratch3,#MASK_INDEX + BEQ 1113f + @ X & Y were 8bit before + TST rstatus,#MASK_INDEX + BNE 1113f + @ X & Y are now 16bits + MOV reg_x,reg_x,LSR #8 + MOV reg_y,reg_y,LSR #8 +1113: @ X & Y still in 16bits + @ Now check MEMORY + TST rscratch3,#MASK_MEM + BEQ 1112f + @ A was 8bit before + TST rstatus,#MASK_MEM + BNE 1112f + @ A is now 16bits + MOV reg_a,reg_a,LSR #8 + @ restore AH + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + ORREQ reg_a,reg_a,rscratch,LSL #24 +1112: + S9xFixCycles + ADD1CYCLE1MEM +.endm +.macro OpE2 + @ status|=*rpc++; + @ so possible changes are : + @ INDEX = 0 -> 1 : X,Y 16bits -> 8bits + @ MEM = 0 -> 1 : A 16bits -> 8bits + @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison + MOV rscratch3, rstatus + LDRB rscratch, [rpc], #1 + ORR rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER + TST rstatus,#MASK_EMUL + BEQ 10111f + @ emulation mode on : no changes sinc eit was on before opcode + @ just be sure to have mem & index set accordingly + ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX) + B 10112f +10111: + @ NOT in Emulation mode, check INDEX & MEMORY bits + @ Now check INDEX + TST rscratch3,#MASK_INDEX + BNE 10113f + @ X & Y were 16bit before + TST rstatus,#MASK_INDEX + BEQ 10113f + @ X & Y are now 8bits + MOV reg_x,reg_x,LSL #8 + MOV reg_y,reg_y,LSL #8 +10113: @ X & Y still in 16bits + @ Now check MEMORY + TST rscratch3,#MASK_MEM + BNE 10112f + @ A was 16bit before + TST rstatus,#MASK_MEM + BEQ 10112f + @ A is now 8bits + @ save AH + MOV rscratch,reg_a,LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] +10112: + S9xFixCycles + ADD1CYCLE1MEM +.endm + +/**********************************************************************************************/ +/* XBA *************************************************************************************** */ +.macro OpEBM1 + @ A is 8bits + ADD rscratch,reg_cpu_var,#RAH_ofs + MOV reg_a,reg_a, LSR #24 + SWPB reg_a,reg_a,[rscratch] + MOVS reg_a,reg_a, LSL #24 + UPDATE_ZN + ADD2CYCLE +.endm +.macro OpEBM0 + @ A is 16bits + MOV rscratch, reg_a, ROR #24 @ ll0000hh + ORR rscratch, rscratch, reg_a, LSR #8@ ll0000hh + 00hhll00 -> llhhllhh + MOV reg_a, rscratch, LSL #16@ llhhllhh -> llhh0000 + MOVS rscratch,rscratch,LSL #24 @ to set Z & N flags with AL + UPDATE_ZN + ADD2CYCLE +.endm + + +/**********************************************************************************************/ +/* RTI *************************************************************************************** */ +.macro Op40X1M1 + @ INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank,rscratch +2401: + ADD rscratch, rpc, reg_p_bank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + @ INDEX cleared & was set : 8->16 + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus, #MASK_MEM + @ MEMORY cleared & was set : 8->16 + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSR #8 + ORREQ reg_a,reg_a,rscratch, LSL #24 + ADD2CYCLE + S9xFixCycles +.endm +.macro Op40X0M1 + @ INDEX cleared, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank,rscratch +2401: + ADD rscratch, rpc, reg_p_bank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + @ INDEX set & was cleared : 16->8 + MOVNE reg_x,reg_x,LSL #8 + MOVNE reg_y,reg_y,LSL #8 + TST rstatus, #MASK_MEM + @ MEMORY cleared & was set : 8->16 + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSR #8 + ORREQ reg_a,reg_a,rscratch, LSL #24 + ADD2CYCLE + S9xFixCycles +.endm +.macro Op40X1M0 + @ INDEX set, MEMORY cleared + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank,rscratch +2401: + ADD rscratch, rpc, reg_p_bank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + @ INDEX cleared & was set : 8->16 + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus, #MASK_MEM + @ MEMORY set & was cleared : 16->8 + MOVNE rscratch,reg_a,LSR #24 + MOVNE reg_a,reg_a,LSL #8 + STRNEB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE + S9xFixCycles +.endm +.macro Op40X0M0 + @ INDEX cleared, MEMORY cleared + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank,rscratch +2401: + ADD rscratch, rpc, reg_p_bank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + @ INDEX set & was cleared : 16->8 + MOVNE reg_x,reg_x,LSL #8 + MOVNE reg_y,reg_y,LSL #8 + TST rstatus, #MASK_MEM + @ MEMORY set & was cleared : 16->8 + @ MEMORY set & was cleared : 16->8 + MOVNE rscratch,reg_a,LSR #24 + MOVNE reg_a,reg_a,LSL #8 + STRNEB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE + S9xFixCycles +.endm + + +/**********************************************************************************************/ +/* STP/WAI/DB ******************************************************************************** */ +@ WAI +.macro OpCB /*WAI*/ + LDRB rscratch,[reg_cpu_var,#IRQActive_ofs] + MOVS rscratch,rscratch + @ (CPU.IRQActive) + ADD2CYCLENEX 2 + BNE 1234f +/* + CPU.WaitingForInterrupt = TRUE; + CPU.PC--;*/ + MOV rscratch,#1 + SUB rpc,rpc,#1 +/* + CPU.Cycles = CPU.NextEvent; +*/ + STRB rscratch,[reg_cpu_var,#WaitingForInterrupt_ofs] + LDR reg_cycles,[reg_cpu_var,#NextEvent_ofs] +/* + if (IAPU.APUExecuting) + { + ICPU.CPUExecuting = FALSE; + do + { + APU_EXECUTE1 (); + } while (APU.Cycles < CPU.NextEvent); + ICPU.CPUExecuting = TRUE; + } +*/ + @LDR rscratch,[reg_cpu_var,#APUExecuting_ofs] + @MOVS rscratch,rscratch + @BEQ 1234f + asmAPU_EXECUTE2 + +1234: +.endm +.macro OpDB /*STP*/ + SUB rpc,rpc,#1 + @ CPU.Flags |= DEBUG_MODE_FLAG; +.endm +.macro Op42 /*Reserved Snes9X*/ +/* Used for speedhacks in snesadvance.dat */ + + @mov rscratch, #0 + @str rscratch, [reg_cpu_var, #WaitAddress_ofs] @ CPU.WaitAddress = NULL + bic rstatus, rstatus, #MASK_SHUTDOWN + + ldr reg_cycles, [reg_cpu_var,#NextEvent_ofs] @ CPU.Cycles = CPU.NextEvent + + asmAPU_EXECUTE2 + + ldrb rscratch2, [rpc], #1 @ rscratch2 <= *CPU.PC++; + ADD1MEM + @ signed char s9xInt8=0xF0|(b&0xF); + orr rscratch, rscratch2, #0xf0 + mov rscratch, rscratch, asl #25 + mov rscratch, rscratch, asr #25 + + @ OpAddress = ((int) (CPU.PC - CPU.PCBase) + s9xInt8) & 0xffff; + sub rscratch3, rpc, regpcbase + add rscratch, rscratch3, rscratch + bic rscratch, rscratch, #0x00ff0000 + bic rscratch, rscratch, #0xff000000 + + mov rscratch2, rscratch2, lsr #4 + + ldr pc, [pc, rscratch2, lsl #2] + mov r0, r0 @ nop + .word Op42_none + .word Op42_10 + .word Op42_none + .word Op42_30 + .word Op42_none + .word Op42_50 + .word Op42_none + .word Op42_70 + .word Op42_80 + .word Op42_90 + .word Op42_none + .word Op42_B0 + .word Op42_none + .word Op42_D0 + .word Op42_none + .word Op42_F0 +.endm + +Op42_none: + NEXTOPCODE +Op42_10: @ BPL + BranchCheck1 + TST rstatus, #MASK_NEG @ neg, z!=0, NE + BNE nob_10 + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLEX 1 + CPUShutdown +nob_10: + NEXTOPCODE +Op42_30: @ BMI + BranchCheck0 + TST rstatus, #MASK_NEG + BEQ nob_30 + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +nob_30: + NEXTOPCODE +Op42_50: @ BVC + BranchCheck0 + TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE + BNE nob_50 + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLEX 1 + CPUShutdown +nob_50: + NEXTOPCODE +Op42_70: @ BVS + BranchCheck0 + TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE + BEQ nob_70 + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLEX 1 + CPUShutdown +nob_70: + NEXTOPCODE +Op42_80: @ BRA + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLEX 1 + CPUShutdown + NEXTOPCODE +Op42_90: @ BCC + BranchCheck0 + TST rstatus, #MASK_CARRY + BNE nob_90 + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +nob_90: + NEXTOPCODE +Op42_B0: @ BCS + BranchCheck0 + TST rstatus, #MASK_CARRY + BEQ nob_B0 + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +nob_B0: + NEXTOPCODE +Op42_D0: @ BNE + BranchCheck1 + TST rstatus, #MASK_ZERO + BNE nob_D0 + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +nob_D0: + NEXTOPCODE +Op42_F0: @ BEQ + BranchCheck2 + TST rstatus, #MASK_ZERO + BEQ nob_F0 + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLEX 1 + CPUShutdown +nob_F0: + NEXTOPCODE + + +/**********************************************************************************************/ +/* AND ******************************************************************************** */ +.macro Op29M1 + LDRB rscratch , [rpc], #1 + ANDS reg_a , reg_a, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro Op29M0 + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + ANDS reg_a , reg_a, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + + + + + + + + + + + + + + + +/**********************************************************************************************/ +/* EOR ******************************************************************************** */ +.macro Op49M0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2,LSL #8 + EORS reg_a, reg_a, rscratch,LSL #16 + UPDATE_ZN + ADD2MEM +.endm + + +.macro Op49M1 + LDRB rscratch , [rpc], #1 + EORS reg_a, reg_a, rscratch,LSL #24 + UPDATE_ZN + ADD1MEM +.endm + + +/**********************************************************************************************/ +/* STA *************************************************************************************** */ +.macro Op81M1 + STA8 + @ TST rstatus, #MASK_INDEX + @ ADD1CYCLENE +.endm +.macro Op81M0 + STA16 + @ TST rstatus, #MASK_INDEX + @ ADD1CYCLENE +.endm + + +/**********************************************************************************************/ +/* BIT *************************************************************************************** */ +.macro Op89M1 + LDRB rscratch , [rpc], #1 + TST reg_a, rscratch, LSL #24 + UPDATE_Z + ADD1MEM +.endm +.macro Op89M0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + TST reg_a, rscratch, LSL #16 + UPDATE_Z + ADD2MEM +.endm + + + + + + +/**********************************************************************************************/ +/* LDY *************************************************************************************** */ +.macro OpA0X1 + LDRB rscratch , [rpc], #1 + MOVS reg_y, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro OpA0X0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + MOVS reg_y, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* LDX *************************************************************************************** */ +.macro OpA2X1 + LDRB rscratch , [rpc], #1 + MOVS reg_x, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro OpA2X0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + MOVS reg_x, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* LDA *************************************************************************************** */ +.macro OpA9M1 + LDRB rscratch , [rpc], #1 + MOVS reg_a, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro OpA9M0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + MOVS reg_a, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* CMY *************************************************************************************** */ +.macro OpC0X1 + LDRB rscratch , [rpc], #1 + SUBS rscratch2 , reg_y , rscratch, LSL #24 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD1MEM +.endm +.macro OpC0X0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + SUBS rscratch2 , reg_y, rscratch, LSL #16 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD2MEM +.endm + + + + + +/**********************************************************************************************/ +/* CMP *************************************************************************************** */ +.macro OpC9M1 + LDRB rscratch , [rpc], #1 + SUBS rscratch2 , reg_a , rscratch, LSL #24 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD1MEM +.endm +.macro OpC9M0 + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + SUBS rscratch2 , reg_a, rscratch, LSL #16 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* CMX *************************************************************************************** */ +.macro OpE0X1 + LDRB rscratch , [rpc], #1 + SUBS rscratch2 , reg_x , rscratch, LSL #24 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD1MEM +.endm +.macro OpE0X0 + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + SUBS rscratch2 , reg_x, rscratch, LSL #16 + BICCC rstatus, rstatus, #MASK_CARRY + + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD2MEM +.endm + diff --git a/src/os9x_65c816_spcasm.s b/src/os9x_65c816_spcasm.s new file mode 100644 index 0000000..3eebba9 --- /dev/null +++ b/src/os9x_65c816_spcasm.s @@ -0,0 +1,4927 @@ + .DATA +/**************************************************************** +****************************************************************/ + .align 4 + .include "os9x_65c816_common.s" + + +.macro asmAPU_EXECUTE + LDR R0,[reg_cpu_var,#APUExecuting_ofs] + CMP R0,#1 @ spc700 enabled, hack mode off + BNE 43210f + LDR R0,[reg_cpu_var,#APU_Cycles] + SUBS R0,reg_cycles,R0 + BMI 43210f + PREPARE_C_CALL_LIGHTR12 + BL spc700_execute + RESTORE_C_CALL_LIGHTR12 + SUB R0,reg_cycles,R0 @ sub cycles left + STR R0,[reg_cpu_var,#APU_Cycles] +43210: +.endm + +.macro asmAPU_EXECUTE2 + LDR R0,[reg_cpu_var,#APUExecuting_ofs] + CMP R0,#1 @ spc700 enabled, hack mode off + BNE 43211f + SUBS R0,reg_cycles,R0 @ reg_cycles == NextEvent + BLE 43211f + PREPARE_C_CALL_LIGHTR12 + BL spc700_execute + RESTORE_C_CALL_LIGHTR12 + SUB R0,reg_cycles,R0 @ sub cycles left + STR R0,[reg_cpu_var,#APU_Cycles] +43211: +.endm + + .include "os9x_65c816_opcodes.s" + + +/* + + +CLI_OPE_REC_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @treasuryDate, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @accountingDate, 103) + +CLI_OPE_Nos_Ope_Layer0 + n.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + n.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +CLI_OPE_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +Ecrans: +------ + + +[GNV] : utilisation de la lard (laccdate) pour afficher les openings. + +nécessité d'avoir des valeurs dans l'opening pour date tréso=date compta=laccdate + +[Accounting rec] : si laccdate pas bonne (pas = BD-1) -> message warning et pas de donnée +sinon : + +données nécessaires : opening date tréso=date compta=laccdate=BD-1 + +données nécessaires : opening date tréso=date compta=laccdate-1 + +données nécessaires : opening date tréso=laccdate-1 et date compta=laccdate + */ + + + +/**************************************************************** + GLOBAL +****************************************************************/ + @.globl test_opcode + .globl asmMainLoop_spcAsm + + +@ void asmMainLoop(asm_cpu_var_t *asmcpuPtr); +asmMainLoop_spcAsm: + doMainLoop +.pool + +/* +@ void test_opcode(struct asm_cpu_var *asm_var); +test_opcode: + doTestOpcode +.pool +*/ +/***************************************************************** + ASM CODE +*****************************************************************/ + + +jumptable1: .long Op00mod1 + .long Op01M1mod1 + .long Op02mod1 + .long Op03M1mod1 + .long Op04M1mod1 + .long Op05M1mod1 + .long Op06M1mod1 + .long Op07M1mod1 + .long Op08mod1 + .long Op09M1mod1 + .long Op0AM1mod1 + .long Op0Bmod1 + .long Op0CM1mod1 + .long Op0DM1mod1 + .long Op0EM1mod1 + .long Op0FM1mod1 + .long Op10mod1 + .long Op11M1mod1 + .long Op12M1mod1 + .long Op13M1mod1 + .long Op14M1mod1 + .long Op15M1mod1 + .long Op16M1mod1 + .long Op17M1mod1 + .long Op18mod1 + .long Op19M1mod1 + .long Op1AM1mod1 + .long Op1Bmod1 + .long Op1CM1mod1 + .long Op1DM1mod1 + .long Op1EM1mod1 + .long Op1FM1mod1 + .long Op20mod1 + .long Op21M1mod1 + .long Op22mod1 + .long Op23M1mod1 + .long Op24M1mod1 + .long Op25M1mod1 + .long Op26M1mod1 + .long Op27M1mod1 + .long Op28mod1 + .long Op29M1mod1 + .long Op2AM1mod1 + .long Op2Bmod1 + .long Op2CM1mod1 + .long Op2DM1mod1 + .long Op2EM1mod1 + .long Op2FM1mod1 + .long Op30mod1 + .long Op31M1mod1 + .long Op32M1mod1 + .long Op33M1mod1 + .long Op34M1mod1 + .long Op35M1mod1 + .long Op36M1mod1 + .long Op37M1mod1 + .long Op38mod1 + .long Op39M1mod1 + .long Op3AM1mod1 + .long Op3Bmod1 + .long Op3CM1mod1 + .long Op3DM1mod1 + .long Op3EM1mod1 + .long Op3FM1mod1 + .long Op40mod1 + .long Op41M1mod1 + .long Op42mod1 + .long Op43M1mod1 + .long Op44X1mod1 + .long Op45M1mod1 + .long Op46M1mod1 + .long Op47M1mod1 + .long Op48M1mod1 + .long Op49M1mod1 + .long Op4AM1mod1 + .long Op4Bmod1 + .long Op4Cmod1 + .long Op4DM1mod1 + .long Op4EM1mod1 + .long Op4FM1mod1 + .long Op50mod1 + .long Op51M1mod1 + .long Op52M1mod1 + .long Op53M1mod1 + .long Op54X1mod1 + .long Op55M1mod1 + .long Op56M1mod1 + .long Op57M1mod1 + .long Op58mod1 + .long Op59M1mod1 + .long Op5AX1mod1 + .long Op5Bmod1 + .long Op5Cmod1 + .long Op5DM1mod1 + .long Op5EM1mod1 + .long Op5FM1mod1 + .long Op60mod1 + .long Op61M1mod1 + .long Op62mod1 + .long Op63M1mod1 + .long Op64M1mod1 + .long Op65M1mod1 + .long Op66M1mod1 + .long Op67M1mod1 + .long Op68M1mod1 + .long Op69M1mod1 + .long Op6AM1mod1 + .long Op6Bmod1 + .long Op6Cmod1 + .long Op6DM1mod1 + .long Op6EM1mod1 + .long Op6FM1mod1 + .long Op70mod1 + .long Op71M1mod1 + .long Op72M1mod1 + .long Op73M1mod1 + .long Op74M1mod1 + .long Op75M1mod1 + .long Op76M1mod1 + .long Op77M1mod1 + .long Op78mod1 + .long Op79M1mod1 + .long Op7AX1mod1 + .long Op7Bmod1 + .long Op7Cmod1 + .long Op7DM1mod1 + .long Op7EM1mod1 + .long Op7FM1mod1 + .long Op80mod1 + .long Op81M1mod1 + .long Op82mod1 + .long Op83M1mod1 + .long Op84X1mod1 + .long Op85M1mod1 + .long Op86X1mod1 + .long Op87M1mod1 + .long Op88X1mod1 + .long Op89M1mod1 + .long Op8AM1mod1 + .long Op8Bmod1 + .long Op8CX1mod1 + .long Op8DM1mod1 + .long Op8EX1mod1 + .long Op8FM1mod1 + .long Op90mod1 + .long Op91M1mod1 + .long Op92M1mod1 + .long Op93M1mod1 + .long Op94X1mod1 + .long Op95M1mod1 + .long Op96X1mod1 + .long Op97M1mod1 + .long Op98M1mod1 + .long Op99M1mod1 + .long Op9Amod1 + .long Op9BX1mod1 + + .long Op9CM1mod1 + .long Op9DM1mod1 + .long Op9EM1mod1 + .long Op9FM1mod1 + .long OpA0X1mod1 + .long OpA1M1mod1 + .long OpA2X1mod1 + .long OpA3M1mod1 + .long OpA4X1mod1 + .long OpA5M1mod1 + .long OpA6X1mod1 + .long OpA7M1mod1 + .long OpA8X1mod1 + .long OpA9M1mod1 + .long OpAAX1mod1 + .long OpABmod1 + .long OpACX1mod1 + .long OpADM1mod1 + .long OpAEX1mod1 + .long OpAFM1mod1 + .long OpB0mod1 + .long OpB1M1mod1 + .long OpB2M1mod1 + .long OpB3M1mod1 + .long OpB4X1mod1 + .long OpB5M1mod1 + .long OpB6X1mod1 + .long OpB7M1mod1 + .long OpB8mod1 + .long OpB9M1mod1 + .long OpBAX1mod1 + .long OpBBX1mod1 + .long OpBCX1mod1 + .long OpBDM1mod1 + .long OpBEX1mod1 + .long OpBFM1mod1 + .long OpC0X1mod1 + .long OpC1M1mod1 + .long OpC2mod1 + .long OpC3M1mod1 + .long OpC4X1mod1 + .long OpC5M1mod1 + .long OpC6M1mod1 + .long OpC7M1mod1 + .long OpC8X1mod1 + .long OpC9M1mod1 + .long OpCAX1mod1 + .long OpCBmod1 + .long OpCCX1mod1 + .long OpCDM1mod1 + .long OpCEM1mod1 + .long OpCFM1mod1 + .long OpD0mod1 + .long OpD1M1mod1 + .long OpD2M1mod1 + .long OpD3M1mod1 + .long OpD4mod1 + .long OpD5M1mod1 + .long OpD6M1mod1 + .long OpD7M1mod1 + .long OpD8mod1 + .long OpD9M1mod1 + .long OpDAX1mod1 + .long OpDBmod1 + .long OpDCmod1 + .long OpDDM1mod1 + .long OpDEM1mod1 + .long OpDFM1mod1 + .long OpE0X1mod1 + .long OpE1M1mod1 + .long OpE2mod1 + .long OpE3M1mod1 + .long OpE4X1mod1 + .long OpE5M1mod1 + .long OpE6M1mod1 + .long OpE7M1mod1 + .long OpE8X1mod1 + .long OpE9M1mod1 + .long OpEAmod1 + .long OpEBmod1 + .long OpECX1mod1 + .long OpEDM1mod1 + .long OpEEM1mod1 + .long OpEFM1mod1 + .long OpF0mod1 + .long OpF1M1mod1 + .long OpF2M1mod1 + .long OpF3M1mod1 + .long OpF4mod1 + .long OpF5M1mod1 + .long OpF6M1mod1 + .long OpF7M1mod1 + .long OpF8mod1 + .long OpF9M1mod1 + .long OpFAX1mod1 + .long OpFBmod1 + .long OpFCmod1 + .long OpFDM1mod1 + .long OpFEM1mod1 + .long OpFFM1mod1 + +Op00mod1: +lbl00mod1: Op00 + NEXTOPCODE +Op01M1mod1: +lbl01mod1a: DirectIndexedIndirect1 +lbl01mod1b: ORA8 + NEXTOPCODE +Op02mod1: +lbl02mod1: Op02 + NEXTOPCODE +Op03M1mod1: +lbl03mod1a: StackasmRelative +lbl03mod1b: ORA8 + NEXTOPCODE +Op04M1mod1: +lbl04mod1a: Direct +lbl04mod1b: TSB8 + NEXTOPCODE +Op05M1mod1: +lbl05mod1a: Direct +lbl05mod1b: ORA8 + NEXTOPCODE +Op06M1mod1: +lbl06mod1a: Direct +lbl06mod1b: ASL8 + NEXTOPCODE +Op07M1mod1: +lbl07mod1a: DirectIndirectLong +lbl07mod1b: ORA8 + NEXTOPCODE +Op08mod1: +lbl08mod1: Op08 + NEXTOPCODE +Op09M1mod1: +lbl09mod1: Op09M1 + NEXTOPCODE +Op0AM1mod1: +lbl0Amod1a: A_ASL8 + NEXTOPCODE +Op0Bmod1: +lbl0Bmod1: Op0B + NEXTOPCODE +Op0CM1mod1: +lbl0Cmod1a: Absolute +lbl0Cmod1b: TSB8 + NEXTOPCODE +Op0DM1mod1: +lbl0Dmod1a: Absolute +lbl0Dmod1b: ORA8 + NEXTOPCODE +Op0EM1mod1: +lbl0Emod1a: Absolute +lbl0Emod1b: ASL8 + NEXTOPCODE +Op0FM1mod1: +lbl0Fmod1a: AbsoluteLong +lbl0Fmod1b: ORA8 + NEXTOPCODE +Op10mod1: +lbl10mod1: Op10 + NEXTOPCODE +Op11M1mod1: +lbl11mod1a: DirectIndirectIndexed1 +lbl11mod1b: ORA8 + NEXTOPCODE +Op12M1mod1: +lbl12mod1a: DirectIndirect +lbl12mod1b: ORA8 + NEXTOPCODE +Op13M1mod1: + +lbl13mod1a: StackasmRelativeIndirectIndexed1 +lbl13mod1b: ORA8 + NEXTOPCODE +Op14M1mod1: +lbl14mod1a: Direct +lbl14mod1b: TRB8 + NEXTOPCODE +Op15M1mod1: +lbl15mod1a: DirectIndexedX1 +lbl15mod1b: ORA8 + NEXTOPCODE +Op16M1mod1: +lbl16mod1a: DirectIndexedX1 +lbl16mod1b: ASL8 + NEXTOPCODE +Op17M1mod1: +lbl17mod1a: DirectIndirectIndexedLong1 +lbl17mod1b: ORA8 + NEXTOPCODE +Op18mod1: +lbl18mod1: Op18 + NEXTOPCODE +Op19M1mod1: +lbl19mod1a: AbsoluteIndexedY1 +lbl19mod1b: ORA8 + NEXTOPCODE +Op1AM1mod1: +lbl1Amod1a: A_INC8 + NEXTOPCODE +Op1Bmod1: +lbl1Bmod1: Op1BM1 + NEXTOPCODE +Op1CM1mod1: +lbl1Cmod1a: Absolute +lbl1Cmod1b: TRB8 + NEXTOPCODE +Op1DM1mod1: +lbl1Dmod1a: AbsoluteIndexedX1 +lbl1Dmod1b: ORA8 + NEXTOPCODE +Op1EM1mod1: +lbl1Emod1a: AbsoluteIndexedX1 +lbl1Emod1b: ASL8 + NEXTOPCODE +Op1FM1mod1: +lbl1Fmod1a: AbsoluteLongIndexedX1 +lbl1Fmod1b: ORA8 + NEXTOPCODE +Op20mod1: +lbl20mod1: Op20 + NEXTOPCODE +Op21M1mod1: +lbl21mod1a: DirectIndexedIndirect1 +lbl21mod1b: AND8 + NEXTOPCODE +Op22mod1: +lbl22mod1: Op22 + NEXTOPCODE +Op23M1mod1: +lbl23mod1a: StackasmRelative +lbl23mod1b: AND8 + NEXTOPCODE +Op24M1mod1: +lbl24mod1a: Direct +lbl24mod1b: BIT8 + NEXTOPCODE +Op25M1mod1: +lbl25mod1a: Direct +lbl25mod1b: AND8 + NEXTOPCODE +Op26M1mod1: +lbl26mod1a: Direct +lbl26mod1b: ROL8 + NEXTOPCODE +Op27M1mod1: +lbl27mod1a: DirectIndirectLong +lbl27mod1b: AND8 + NEXTOPCODE +Op28mod1: +lbl28mod1: Op28X1M1 + NEXTOPCODE +.pool +Op29M1mod1: +lbl29mod1: Op29M1 + NEXTOPCODE +Op2AM1mod1: +lbl2Amod1a: A_ROL8 + NEXTOPCODE +Op2Bmod1: +lbl2Bmod1: Op2B + NEXTOPCODE +Op2CM1mod1: +lbl2Cmod1a: Absolute +lbl2Cmod1b: BIT8 + NEXTOPCODE +Op2DM1mod1: +lbl2Dmod1a: Absolute +lbl2Dmod1b: AND8 + NEXTOPCODE +Op2EM1mod1: +lbl2Emod1a: Absolute +lbl2Emod1b: ROL8 + NEXTOPCODE +Op2FM1mod1: +lbl2Fmod1a: AbsoluteLong +lbl2Fmod1b: AND8 + NEXTOPCODE +Op30mod1: +lbl30mod1: Op30 + NEXTOPCODE +Op31M1mod1: +lbl31mod1a: DirectIndirectIndexed1 +lbl31mod1b: AND8 + NEXTOPCODE +Op32M1mod1: +lbl32mod1a: DirectIndirect +lbl32mod1b: AND8 + NEXTOPCODE +Op33M1mod1: +lbl33mod1a: StackasmRelativeIndirectIndexed1 +lbl33mod1b: AND8 + NEXTOPCODE +Op34M1mod1: +lbl34mod1a: DirectIndexedX1 +lbl34mod1b: BIT8 + NEXTOPCODE +Op35M1mod1: +lbl35mod1a: DirectIndexedX1 +lbl35mod1b: AND8 + NEXTOPCODE +Op36M1mod1: +lbl36mod1a: DirectIndexedX1 +lbl36mod1b: ROL8 + NEXTOPCODE +Op37M1mod1: +lbl37mod1a: DirectIndirectIndexedLong1 +lbl37mod1b: AND8 + NEXTOPCODE +Op38mod1: +lbl38mod1: Op38 + NEXTOPCODE +Op39M1mod1: +lbl39mod1a: AbsoluteIndexedY1 +lbl39mod1b: AND8 + NEXTOPCODE +Op3AM1mod1: +lbl3Amod1a: A_DEC8 + NEXTOPCODE +Op3Bmod1: +lbl3Bmod1: Op3BM1 + NEXTOPCODE +Op3CM1mod1: +lbl3Cmod1a: AbsoluteIndexedX1 +lbl3Cmod1b: BIT8 + NEXTOPCODE +Op3DM1mod1: +lbl3Dmod1a: AbsoluteIndexedX1 +lbl3Dmod1b: AND8 + NEXTOPCODE +Op3EM1mod1: +lbl3Emod1a: AbsoluteIndexedX1 +lbl3Emod1b: ROL8 + NEXTOPCODE +Op3FM1mod1: +lbl3Fmod1a: AbsoluteLongIndexedX1 +lbl3Fmod1b: AND8 + NEXTOPCODE +Op40mod1: +lbl40mod1: Op40X1M1 + NEXTOPCODE +.pool +Op41M1mod1: +lbl41mod1a: DirectIndexedIndirect1 +lbl41mod1b: EOR8 + NEXTOPCODE +Op42mod1: +lbl42mod1: Op42 + NEXTOPCODE +Op43M1mod1: +lbl43mod1a: StackasmRelative +lbl43mod1b: EOR8 + NEXTOPCODE +Op44X1mod1: +lbl44mod1: Op44X1M1 + NEXTOPCODE +Op45M1mod1: +lbl45mod1a: Direct +lbl45mod1b: EOR8 + NEXTOPCODE +Op46M1mod1: +lbl46mod1a: Direct +lbl46mod1b: LSR8 + NEXTOPCODE +Op47M1mod1: +lbl47mod1a: DirectIndirectLong +lbl47mod1b: EOR8 + NEXTOPCODE +Op48M1mod1: +lbl48mod1: Op48M1 + NEXTOPCODE +Op49M1mod1: +lbl49mod1: Op49M1 + NEXTOPCODE +Op4AM1mod1: +lbl4Amod1a: A_LSR8 + NEXTOPCODE +Op4Bmod1: +lbl4Bmod1: Op4B + NEXTOPCODE +Op4Cmod1: +lbl4Cmod1: Op4C + NEXTOPCODE +Op4DM1mod1: +lbl4Dmod1a: Absolute +lbl4Dmod1b: EOR8 + NEXTOPCODE +Op4EM1mod1: +lbl4Emod1a: Absolute +lbl4Emod1b: LSR8 + NEXTOPCODE +Op4FM1mod1: +lbl4Fmod1a: AbsoluteLong +lbl4Fmod1b: EOR8 + NEXTOPCODE +Op50mod1: +lbl50mod1: Op50 + NEXTOPCODE +Op51M1mod1: +lbl51mod1a: DirectIndirectIndexed1 +lbl51mod1b: EOR8 + NEXTOPCODE +Op52M1mod1: +lbl52mod1a: DirectIndirect +lbl52mod1b: EOR8 + NEXTOPCODE +Op53M1mod1: +lbl53mod1a: StackasmRelativeIndirectIndexed1 +lbl53mod1b: EOR8 + NEXTOPCODE +Op54X1mod1: +lbl54mod1: Op54X1M1 + NEXTOPCODE +Op55M1mod1: +lbl55mod1a: DirectIndexedX1 +lbl55mod1b: EOR8 + NEXTOPCODE +Op56M1mod1: +lbl56mod1a: DirectIndexedX1 +lbl56mod1b: LSR8 + NEXTOPCODE +Op57M1mod1: +lbl57mod1a: DirectIndirectIndexedLong1 +lbl57mod1b: EOR8 + NEXTOPCODE +Op58mod1: +lbl58mod1: Op58 + NEXTOPCODE +Op59M1mod1: +lbl59mod1a: AbsoluteIndexedY1 +lbl59mod1b: EOR8 + NEXTOPCODE +Op5AX1mod1: +lbl5Amod1: Op5AX1 + NEXTOPCODE +Op5Bmod1: +lbl5Bmod1: Op5BM1 + NEXTOPCODE +Op5Cmod1: +lbl5Cmod1: Op5C + NEXTOPCODE +Op5DM1mod1: +lbl5Dmod1a: AbsoluteIndexedX1 +lbl5Dmod1b: EOR8 + NEXTOPCODE +Op5EM1mod1: +lbl5Emod1a: AbsoluteIndexedX1 +lbl5Emod1b: LSR8 + NEXTOPCODE +Op5FM1mod1: +lbl5Fmod1a: AbsoluteLongIndexedX1 +lbl5Fmod1b: EOR8 + NEXTOPCODE +Op60mod1: +lbl60mod1: Op60 + NEXTOPCODE +Op61M1mod1: +lbl61mod1a: DirectIndexedIndirect1 +lbl61mod1b: ADC8 + NEXTOPCODE +Op62mod1: +lbl62mod1: Op62 + NEXTOPCODE +Op63M1mod1: +lbl63mod1a: StackasmRelative +lbl63mod1b: ADC8 + NEXTOPCODE +Op64M1mod1: +lbl64mod1a: Direct +lbl64mod1b: STZ8 + NEXTOPCODE +Op65M1mod1: +lbl65mod1a: Direct +lbl65mod1b: ADC8 + NEXTOPCODE +Op66M1mod1: +lbl66mod1a: Direct +lbl66mod1b: ROR8 + NEXTOPCODE +Op67M1mod1: +lbl67mod1a: DirectIndirectLong +lbl67mod1b: ADC8 + + NEXTOPCODE + +Op68M1mod1: +lbl68mod1: Op68M1 + NEXTOPCODE +Op69M1mod1: +lbl69mod1a: Immediate8 +lbl69mod1b: ADC8 + NEXTOPCODE +Op6AM1mod1: +lbl6Amod1a: A_ROR8 + NEXTOPCODE +Op6Bmod1: +lbl6Bmod1: Op6B + NEXTOPCODE +Op6Cmod1: +lbl6Cmod1: Op6C + NEXTOPCODE +Op6DM1mod1: +lbl6Dmod1a: Absolute +lbl6Dmod1b: ADC8 + NEXTOPCODE +Op6EM1mod1: + + +lbl6Emod1a: Absolute +lbl6Emod1b: ROR8 + NEXTOPCODE +Op6FM1mod1: +lbl6Fmod1a: AbsoluteLong +lbl6Fmod1b: ADC8 + NEXTOPCODE +Op70mod1: +lbl70mod1: Op70 + NEXTOPCODE +Op71M1mod1: +lbl71mod1a: DirectIndirectIndexed1 +lbl71mod1b: ADC8 + NEXTOPCODE +Op72M1mod1: +lbl72mod1a: DirectIndirect +lbl72mod1b: ADC8 + NEXTOPCODE +Op73M1mod1: +lbl73mod1a: StackasmRelativeIndirectIndexed1 +lbl73mod1b: ADC8 + NEXTOPCODE + +Op74M1mod1: +lbl74mod1a: DirectIndexedX1 +lbl74mod1b: STZ8 + NEXTOPCODE +Op75M1mod1: +lbl75mod1a: DirectIndexedX1 +lbl75mod1b: ADC8 + NEXTOPCODE +Op76M1mod1: +lbl76mod1a: DirectIndexedX1 +lbl76mod1b: ROR8 + NEXTOPCODE +Op77M1mod1: +lbl77mod1a: DirectIndirectIndexedLong1 +lbl77mod1b: ADC8 + NEXTOPCODE +Op78mod1: +lbl78mod1: Op78 + NEXTOPCODE +Op79M1mod1: +lbl79mod1a: AbsoluteIndexedY1 +lbl79mod1b: ADC8 + NEXTOPCODE +Op7AX1mod1: +lbl7Amod1: Op7AX1 + NEXTOPCODE +Op7Bmod1: +lbl7Bmod1: Op7BM1 + NEXTOPCODE +Op7Cmod1: +lbl7Cmod1: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE +Op7DM1mod1: +lbl7Dmod1a: AbsoluteIndexedX1 +lbl7Dmod1b: ADC8 + NEXTOPCODE +Op7EM1mod1: +lbl7Emod1a: AbsoluteIndexedX1 +lbl7Emod1b: ROR8 + NEXTOPCODE +Op7FM1mod1: +lbl7Fmod1a: AbsoluteLongIndexedX1 +lbl7Fmod1b: ADC8 + NEXTOPCODE + + +Op80mod1: +lbl80mod1: Op80 + NEXTOPCODE +Op81M1mod1: +lbl81mod1a: DirectIndexedIndirect1 +lbl81mod1b: Op81M1 + NEXTOPCODE +Op82mod1: +lbl82mod1: Op82 + NEXTOPCODE +Op83M1mod1: +lbl83mod1a: StackasmRelative +lbl83mod1b: STA8 + NEXTOPCODE +Op84X1mod1: +lbl84mod1a: Direct +lbl84mod1b: STY8 + NEXTOPCODE +Op85M1mod1: +lbl85mod1a: Direct +lbl85mod1b: STA8 + NEXTOPCODE +Op86X1mod1: +lbl86mod1a: Direct +lbl86mod1b: STX8 + NEXTOPCODE +Op87M1mod1: +lbl87mod1a: DirectIndirectLong +lbl87mod1b: STA8 + NEXTOPCODE +Op88X1mod1: +lbl88mod1: Op88X1 + NEXTOPCODE +Op89M1mod1: +lbl89mod1: Op89M1 + NEXTOPCODE +Op8AM1mod1: +lbl8Amod1: Op8AM1X1 + NEXTOPCODE +Op8Bmod1: +lbl8Bmod1: Op8B + NEXTOPCODE +Op8CX1mod1: +lbl8Cmod1a: Absolute +lbl8Cmod1b: STY8 + NEXTOPCODE +Op8DM1mod1: +lbl8Dmod1a: Absolute +lbl8Dmod1b: STA8 + NEXTOPCODE +Op8EX1mod1: +lbl8Emod1a: Absolute +lbl8Emod1b: STX8 + NEXTOPCODE +Op8FM1mod1: +lbl8Fmod1a: AbsoluteLong +lbl8Fmod1b: STA8 + NEXTOPCODE +Op90mod1: +lbl90mod1: Op90 + NEXTOPCODE +Op91M1mod1: +lbl91mod1a: DirectIndirectIndexed1 +lbl91mod1b: STA8 + NEXTOPCODE +Op92M1mod1: +lbl92mod1a: DirectIndirect +lbl92mod1b: STA8 + NEXTOPCODE +Op93M1mod1: +lbl93mod1a: StackasmRelativeIndirectIndexed1 +lbl93mod1b: STA8 + NEXTOPCODE +Op94X1mod1: +lbl94mod1a: DirectIndexedX1 +lbl94mod1b: STY8 + NEXTOPCODE +Op95M1mod1: +lbl95mod1a: DirectIndexedX1 +lbl95mod1b: STA8 + NEXTOPCODE +Op96X1mod1: +lbl96mod1a: DirectIndexedY1 +lbl96mod1b: STX8 + NEXTOPCODE +Op97M1mod1: +lbl97mod1a: DirectIndirectIndexedLong1 +lbl97mod1b: STA8 + NEXTOPCODE +Op98M1mod1: +lbl98mod1: Op98M1X1 + NEXTOPCODE +Op99M1mod1: +lbl99mod1a: AbsoluteIndexedY1 +lbl99mod1b: STA8 + NEXTOPCODE +Op9Amod1: +lbl9Amod1: Op9AX1 + NEXTOPCODE +Op9BX1mod1: +lbl9Bmod1: Op9BX1 + NEXTOPCODE +Op9CM1mod1: +lbl9Cmod1a: Absolute +lbl9Cmod1b: STZ8 + NEXTOPCODE +Op9DM1mod1: +lbl9Dmod1a: AbsoluteIndexedX1 +lbl9Dmod1b: STA8 + NEXTOPCODE +Op9EM1mod1: +lbl9Emod1: AbsoluteIndexedX1 + STZ8 + NEXTOPCODE +Op9FM1mod1: +lbl9Fmod1a: AbsoluteLongIndexedX1 +lbl9Fmod1b: STA8 + NEXTOPCODE +OpA0X1mod1: +lblA0mod1: OpA0X1 + NEXTOPCODE +OpA1M1mod1: +lblA1mod1a: DirectIndexedIndirect1 +lblA1mod1b: LDA8 + NEXTOPCODE +OpA2X1mod1: +lblA2mod1: OpA2X1 + NEXTOPCODE +OpA3M1mod1: +lblA3mod1a: StackasmRelative +lblA3mod1b: LDA8 + NEXTOPCODE +OpA4X1mod1: +lblA4mod1a: Direct +lblA4mod1b: LDY8 + NEXTOPCODE +OpA5M1mod1: +lblA5mod1a: Direct +lblA5mod1b: LDA8 + NEXTOPCODE +OpA6X1mod1: +lblA6mod1a: Direct +lblA6mod1b: LDX8 + NEXTOPCODE +OpA7M1mod1: +lblA7mod1a: DirectIndirectLong +lblA7mod1b: LDA8 + NEXTOPCODE +OpA8X1mod1: +lblA8mod1: OpA8X1M1 + NEXTOPCODE +OpA9M1mod1: +lblA9mod1: OpA9M1 + NEXTOPCODE +OpAAX1mod1: +lblAAmod1: OpAAX1M1 + NEXTOPCODE +OpABmod1: +lblABmod1: OpAB + NEXTOPCODE +OpACX1mod1: +lblACmod1a: Absolute +lblACmod1b: LDY8 + NEXTOPCODE +OpADM1mod1: +lblADmod1a: Absolute +lblADmod1b: LDA8 + NEXTOPCODE +OpAEX1mod1: +lblAEmod1a: Absolute +lblAEmod1b: LDX8 + NEXTOPCODE +OpAFM1mod1: +lblAFmod1a: AbsoluteLong +lblAFmod1b: LDA8 + NEXTOPCODE +OpB0mod1: +lblB0mod1: OpB0 + NEXTOPCODE +OpB1M1mod1: +lblB1mod1a: DirectIndirectIndexed1 +lblB1mod1b: LDA8 + NEXTOPCODE +OpB2M1mod1: +lblB2mod1a: DirectIndirect +lblB2mod1b: LDA8 + NEXTOPCODE +OpB3M1mod1: +lblB3mod1a: StackasmRelativeIndirectIndexed1 +lblB3mod1b: LDA8 + NEXTOPCODE +OpB4X1mod1: +lblB4mod1a: DirectIndexedX1 +lblB4mod1b: LDY8 + NEXTOPCODE +OpB5M1mod1: +lblB5mod1a: DirectIndexedX1 +lblB5mod1b: LDA8 + NEXTOPCODE +OpB6X1mod1: +lblB6mod1a: DirectIndexedY1 +lblB6mod1b: LDX8 + NEXTOPCODE +OpB7M1mod1: +lblB7mod1a: DirectIndirectIndexedLong1 +lblB7mod1b: LDA8 + NEXTOPCODE +OpB8mod1: +lblB8mod1: OpB8 + NEXTOPCODE +OpB9M1mod1: +lblB9mod1a: AbsoluteIndexedY1 +lblB9mod1b: LDA8 + NEXTOPCODE +OpBAX1mod1: +lblBAmod1: OpBAX1 + NEXTOPCODE +OpBBX1mod1: +lblBBmod1: OpBBX1 + NEXTOPCODE +OpBCX1mod1: +lblBCmod1a: AbsoluteIndexedX1 +lblBCmod1b: LDY8 + NEXTOPCODE +OpBDM1mod1: +lblBDmod1a: AbsoluteIndexedX1 +lblBDmod1b: LDA8 + NEXTOPCODE +OpBEX1mod1: +lblBEmod1a: AbsoluteIndexedY1 +lblBEmod1b: LDX8 + NEXTOPCODE +OpBFM1mod1: +lblBFmod1a: AbsoluteLongIndexedX1 +lblBFmod1b: LDA8 + NEXTOPCODE +OpC0X1mod1: +lblC0mod1: OpC0X1 + NEXTOPCODE +OpC1M1mod1: +lblC1mod1a: DirectIndexedIndirect1 +lblC1mod1b: CMP8 + NEXTOPCODE +OpC2mod1: +lblC2mod1: OpC2 + NEXTOPCODE +.pool +OpC3M1mod1: +lblC3mod1a: StackasmRelative +lblC3mod1b: CMP8 + NEXTOPCODE +OpC4X1mod1: +lblC4mod1a: Direct +lblC4mod1b: CMY8 + NEXTOPCODE +OpC5M1mod1: +lblC5mod1a: Direct +lblC5mod1b: CMP8 + NEXTOPCODE +OpC6M1mod1: +lblC6mod1a: Direct +lblC6mod1b: DEC8 + NEXTOPCODE +OpC7M1mod1: +lblC7mod1a: DirectIndirectLong +lblC7mod1b: CMP8 + NEXTOPCODE +OpC8X1mod1: +lblC8mod1: OpC8X1 + NEXTOPCODE +OpC9M1mod1: +lblC9mod1: OpC9M1 + NEXTOPCODE +OpCAX1mod1: +lblCAmod1: OpCAX1 + NEXTOPCODE +OpCBmod1: +lblCBmod1: OpCB + NEXTOPCODE +OpCCX1mod1: +lblCCmod1a: Absolute +lblCCmod1b: CMY8 + NEXTOPCODE +OpCDM1mod1: +lblCDmod1a: Absolute +lblCDmod1b: CMP8 + NEXTOPCODE +OpCEM1mod1: +lblCEmod1a: Absolute +lblCEmod1b: DEC8 + NEXTOPCODE +OpCFM1mod1: +lblCFmod1a: AbsoluteLong +lblCFmod1b: CMP8 + NEXTOPCODE +OpD0mod1: +lblD0mod1: OpD0 + NEXTOPCODE +OpD1M1mod1: +lblD1mod1a: DirectIndirectIndexed1 +lblD1mod1b: CMP8 + NEXTOPCODE +OpD2M1mod1: +lblD2mod1a: DirectIndirect +lblD2mod1b: CMP8 + NEXTOPCODE +OpD3M1mod1: +lblD3mod1a: StackasmRelativeIndirectIndexed1 +lblD3mod1b: CMP8 + + NEXTOPCODE +OpD4mod1: +lblD4mod1: OpD4 + NEXTOPCODE +OpD5M1mod1: +lblD5mod1a: DirectIndexedX1 +lblD5mod1b: CMP8 + NEXTOPCODE +OpD6M1mod1: +lblD6mod1a: DirectIndexedX1 +lblD6mod1b: DEC8 + NEXTOPCODE +OpD7M1mod1: +lblD7mod1a: DirectIndirectIndexedLong1 +lblD7mod1b: CMP8 + NEXTOPCODE +OpD8mod1: +lblD8mod1: OpD8 + NEXTOPCODE +OpD9M1mod1: +lblD9mod1a: AbsoluteIndexedY1 +lblD9mod1b: CMP8 + NEXTOPCODE +OpDAX1mod1: +lblDAmod1: OpDAX1 + NEXTOPCODE +OpDBmod1: +lblDBmod1: OpDB + NEXTOPCODE +OpDCmod1: +lblDCmod1: OpDC + NEXTOPCODE +OpDDM1mod1: +lblDDmod1a: AbsoluteIndexedX1 +lblDDmod1b: CMP8 + NEXTOPCODE +OpDEM1mod1: +lblDEmod1a: AbsoluteIndexedX1 +lblDEmod1b: DEC8 + NEXTOPCODE +OpDFM1mod1: +lblDFmod1a: AbsoluteLongIndexedX1 +lblDFmod1b: CMP8 + NEXTOPCODE +OpE0X1mod1: +lblE0mod1: OpE0X1 + NEXTOPCODE +OpE1M1mod1: +lblE1mod1a: DirectIndexedIndirect1 +lblE1mod1b: SBC8 + NEXTOPCODE +OpE2mod1: +lblE2mod1: OpE2 + NEXTOPCODE +.pool +OpE3M1mod1: +lblE3mod1a: StackasmRelative +lblE3mod1b: SBC8 + NEXTOPCODE +OpE4X1mod1: +lblE4mod1a: Direct +lblE4mod1b: CMX8 + NEXTOPCODE +OpE5M1mod1: +lblE5mod1a: Direct +lblE5mod1b: SBC8 + NEXTOPCODE +OpE6M1mod1: +lblE6mod1a: Direct +lblE6mod1b: INC8 + NEXTOPCODE +OpE7M1mod1: +lblE7mod1a: DirectIndirectLong +lblE7mod1b: SBC8 + NEXTOPCODE +OpE8X1mod1: +lblE8mod1: OpE8X1 + NEXTOPCODE +OpE9M1mod1: +lblE9mod1a: Immediate8 +lblE9mod1b: SBC8 + NEXTOPCODE +OpEAmod1: +lblEAmod1: OpEA + NEXTOPCODE +OpEBmod1: +lblEBmod1: OpEBM1 + NEXTOPCODE +OpECX1mod1: +lblECmod1a: Absolute +lblECmod1b: CMX8 + NEXTOPCODE +OpEDM1mod1: +lblEDmod1a: Absolute +lblEDmod1b: SBC8 + NEXTOPCODE +OpEEM1mod1: +lblEEmod1a: Absolute +lblEEmod1b: INC8 + NEXTOPCODE +OpEFM1mod1: +lblEFmod1a: AbsoluteLong +lblEFmod1b: SBC8 + NEXTOPCODE +OpF0mod1: +lblF0mod1: OpF0 + NEXTOPCODE +OpF1M1mod1: +lblF1mod1a: DirectIndirectIndexed1 +lblF1mod1b: SBC8 + NEXTOPCODE +OpF2M1mod1: +lblF2mod1a: DirectIndirect +lblF2mod1b: SBC8 + NEXTOPCODE +OpF3M1mod1: +lblF3mod1a: StackasmRelativeIndirectIndexed1 +lblF3mod1b: SBC8 + NEXTOPCODE +OpF4mod1: +lblF4mod1: OpF4 + NEXTOPCODE +OpF5M1mod1: +lblF5mod1a: DirectIndexedX1 +lblF5mod1b: SBC8 + NEXTOPCODE +OpF6M1mod1: +lblF6mod1a: DirectIndexedX1 +lblF6mod1b: INC8 + NEXTOPCODE +OpF7M1mod1: +lblF7mod1a: DirectIndirectIndexedLong1 +lblF7mod1b: SBC8 + NEXTOPCODE +OpF8mod1: +lblF8mod1: OpF8 + NEXTOPCODE +OpF9M1mod1: +lblF9mod1a: AbsoluteIndexedY1 +lblF9mod1b: SBC8 + NEXTOPCODE +OpFAX1mod1: +lblFAmod1: OpFAX1 + NEXTOPCODE +OpFBmod1: +lblFBmod1: OpFB + NEXTOPCODE +OpFCmod1: +lblFCmod1: OpFCX1 + NEXTOPCODE +OpFDM1mod1: +lblFDmod1a: AbsoluteIndexedX1 +lblFDmod1b: SBC8 + NEXTOPCODE +OpFEM1mod1: +lblFEmod1a: AbsoluteIndexedX1 +lblFEmod1b: INC8 + NEXTOPCODE +OpFFM1mod1: +lblFFmod1a: AbsoluteLongIndexedX1 +lblFFmod1b: SBC8 + NEXTOPCODE +.pool + + +jumptable2: .long Op00mod2 + .long Op01M1mod2 + .long Op02mod2 + .long Op03M1mod2 + .long Op04M1mod2 + .long Op05M1mod2 + .long Op06M1mod2 + .long Op07M1mod2 + .long Op08mod2 + .long Op09M1mod2 + .long Op0AM1mod2 + .long Op0Bmod2 + .long Op0CM1mod2 + .long Op0DM1mod2 + .long Op0EM1mod2 + .long Op0FM1mod2 + .long Op10mod2 + .long Op11M1mod2 + .long Op12M1mod2 + .long Op13M1mod2 + .long Op14M1mod2 + .long Op15M1mod2 + .long Op16M1mod2 + .long Op17M1mod2 + .long Op18mod2 + .long Op19M1mod2 + .long Op1AM1mod2 + .long Op1Bmod2 + .long Op1CM1mod2 + .long Op1DM1mod2 + .long Op1EM1mod2 + .long Op1FM1mod2 + .long Op20mod2 + .long Op21M1mod2 + .long Op22mod2 + .long Op23M1mod2 + .long Op24M1mod2 + .long Op25M1mod2 + .long Op26M1mod2 + .long Op27M1mod2 + .long Op28mod2 + .long Op29M1mod2 + .long Op2AM1mod2 + .long Op2Bmod2 + .long Op2CM1mod2 + .long Op2DM1mod2 + .long Op2EM1mod2 + .long Op2FM1mod2 + .long Op30mod2 + .long Op31M1mod2 + .long Op32M1mod2 + .long Op33M1mod2 + .long Op34M1mod2 + .long Op35M1mod2 + .long Op36M1mod2 + .long Op37M1mod2 + .long Op38mod2 + .long Op39M1mod2 + .long Op3AM1mod2 + .long Op3Bmod2 + .long Op3CM1mod2 + .long Op3DM1mod2 + .long Op3EM1mod2 + .long Op3FM1mod2 + .long Op40mod2 + .long Op41M1mod2 + .long Op42mod2 + .long Op43M1mod2 + .long Op44X0mod2 + .long Op45M1mod2 + .long Op46M1mod2 + .long Op47M1mod2 + .long Op48M1mod2 + .long Op49M1mod2 + .long Op4AM1mod2 + .long Op4Bmod2 + .long Op4Cmod2 + .long Op4DM1mod2 + .long Op4EM1mod2 + .long Op4FM1mod2 + .long Op50mod2 + .long Op51M1mod2 + .long Op52M1mod2 + .long Op53M1mod2 + .long Op54X0mod2 + .long Op55M1mod2 + .long Op56M1mod2 + .long Op57M1mod2 + .long Op58mod2 + .long Op59M1mod2 + .long Op5AX0mod2 + .long Op5Bmod2 + .long Op5Cmod2 + .long Op5DM1mod2 + .long Op5EM1mod2 + .long Op5FM1mod2 + .long Op60mod2 + .long Op61M1mod2 + .long Op62mod2 + .long Op63M1mod2 + .long Op64M1mod2 + .long Op65M1mod2 + .long Op66M1mod2 + .long Op67M1mod2 + .long Op68M1mod2 + .long Op69M1mod2 + .long Op6AM1mod2 + .long Op6Bmod2 + .long Op6Cmod2 + .long Op6DM1mod2 + .long Op6EM1mod2 + .long Op6FM1mod2 + .long Op70mod2 + .long Op71M1mod2 + .long Op72M1mod2 + .long Op73M1mod2 + .long Op74M1mod2 + .long Op75M1mod2 + .long Op76M1mod2 + .long Op77M1mod2 + .long Op78mod2 + .long Op79M1mod2 + .long Op7AX0mod2 + .long Op7Bmod2 + .long Op7Cmod2 + .long Op7DM1mod2 + .long Op7EM1mod2 + .long Op7FM1mod2 + .long Op80mod2 + .long Op81M1mod2 + .long Op82mod2 + .long Op83M1mod2 + .long Op84X0mod2 + .long Op85M1mod2 + .long Op86X0mod2 + .long Op87M1mod2 + .long Op88X0mod2 + .long Op89M1mod2 + .long Op8AM1mod2 + .long Op8Bmod2 + .long Op8CX0mod2 + .long Op8DM1mod2 + .long Op8EX0mod2 + .long Op8FM1mod2 + .long Op90mod2 + .long Op91M1mod2 + .long Op92M1mod2 + .long Op93M1mod2 + .long Op94X0mod2 + .long Op95M1mod2 + .long Op96X0mod2 + .long Op97M1mod2 + .long Op98M1mod2 + .long Op99M1mod2 + .long Op9Amod2 + .long Op9BX0mod2 + .long Op9CM1mod2 + .long Op9DM1mod2 + .long Op9EM1mod2 + .long Op9FM1mod2 + .long OpA0X0mod2 + .long OpA1M1mod2 + .long OpA2X0mod2 + .long OpA3M1mod2 + .long OpA4X0mod2 + .long OpA5M1mod2 + .long OpA6X0mod2 + .long OpA7M1mod2 + .long OpA8X0mod2 + .long OpA9M1mod2 + .long OpAAX0mod2 + .long OpABmod2 + .long OpACX0mod2 + .long OpADM1mod2 + .long OpAEX0mod2 + .long OpAFM1mod2 + .long OpB0mod2 + .long OpB1M1mod2 + .long OpB2M1mod2 + .long OpB3M1mod2 + .long OpB4X0mod2 + .long OpB5M1mod2 + .long OpB6X0mod2 + .long OpB7M1mod2 + .long OpB8mod2 + .long OpB9M1mod2 + .long OpBAX0mod2 + .long OpBBX0mod2 + .long OpBCX0mod2 + .long OpBDM1mod2 + .long OpBEX0mod2 + .long OpBFM1mod2 + .long OpC0X0mod2 + .long OpC1M1mod2 + .long OpC2mod2 + .long OpC3M1mod2 + .long OpC4X0mod2 + .long OpC5M1mod2 + .long OpC6M1mod2 + .long OpC7M1mod2 + .long OpC8X0mod2 + .long OpC9M1mod2 + .long OpCAX0mod2 + .long OpCBmod2 + .long OpCCX0mod2 + .long OpCDM1mod2 + .long OpCEM1mod2 + .long OpCFM1mod2 + .long OpD0mod2 + .long OpD1M1mod2 + .long OpD2M1mod2 + .long OpD3M1mod2 + .long OpD4mod2 + .long OpD5M1mod2 + .long OpD6M1mod2 + .long OpD7M1mod2 + .long OpD8mod2 + .long OpD9M1mod2 + .long OpDAX0mod2 + .long OpDBmod2 + .long OpDCmod2 + .long OpDDM1mod2 + .long OpDEM1mod2 + .long OpDFM1mod2 + .long OpE0X0mod2 + .long OpE1M1mod2 + .long OpE2mod2 + .long OpE3M1mod2 + .long OpE4X0mod2 + .long OpE5M1mod2 + .long OpE6M1mod2 + .long OpE7M1mod2 + .long OpE8X0mod2 + .long OpE9M1mod2 + .long OpEAmod2 + .long OpEBmod2 + .long OpECX0mod2 + .long OpEDM1mod2 + .long OpEEM1mod2 + .long OpEFM1mod2 + .long OpF0mod2 + .long OpF1M1mod2 + .long OpF2M1mod2 + .long OpF3M1mod2 + .long OpF4mod2 + .long OpF5M1mod2 + .long OpF6M1mod2 + .long OpF7M1mod2 + .long OpF8mod2 + .long OpF9M1mod2 + .long OpFAX0mod2 + .long OpFBmod2 + .long OpFCmod2 + .long OpFDM1mod2 + .long OpFEM1mod2 + .long OpFFM1mod2 +Op00mod2: +lbl00mod2: Op00 + NEXTOPCODE +Op01M1mod2: +lbl01mod2a: DirectIndexedIndirect0 +lbl01mod2b: ORA8 + NEXTOPCODE +Op02mod2: +lbl02mod2: Op02 + NEXTOPCODE +Op03M1mod2: +lbl03mod2a: StackasmRelative +lbl03mod2b: ORA8 + NEXTOPCODE +Op04M1mod2: +lbl04mod2a: Direct +lbl04mod2b: TSB8 + NEXTOPCODE +Op05M1mod2: +lbl05mod2a: Direct +lbl05mod2b: ORA8 + NEXTOPCODE +Op06M1mod2: +lbl06mod2a: Direct +lbl06mod2b: ASL8 + NEXTOPCODE +Op07M1mod2: +lbl07mod2a: DirectIndirectLong +lbl07mod2b: ORA8 + NEXTOPCODE +Op08mod2: + +lbl08mod2: Op08 + NEXTOPCODE +Op09M1mod2: +lbl09mod2: Op09M1 + NEXTOPCODE +Op0AM1mod2: +lbl0Amod2a: A_ASL8 + NEXTOPCODE +Op0Bmod2: +lbl0Bmod2: Op0B + NEXTOPCODE +Op0CM1mod2: +lbl0Cmod2a: Absolute +lbl0Cmod2b: TSB8 + NEXTOPCODE +Op0DM1mod2: +lbl0Dmod2a: Absolute +lbl0Dmod2b: ORA8 + NEXTOPCODE +Op0EM1mod2: +lbl0Emod2a: Absolute +lbl0Emod2b: ASL8 + NEXTOPCODE +Op0FM1mod2: +lbl0Fmod2a: AbsoluteLong +lbl0Fmod2b: ORA8 + NEXTOPCODE +Op10mod2: +lbl10mod2: Op10 + NEXTOPCODE +Op11M1mod2: +lbl11mod2a: DirectIndirectIndexed0 +lbl11mod2b: ORA8 + NEXTOPCODE +Op12M1mod2: +lbl12mod2a: DirectIndirect +lbl12mod2b: ORA8 + NEXTOPCODE +Op13M1mod2: +lbl13mod2a: StackasmRelativeIndirectIndexed0 +lbl13mod2b: ORA8 + NEXTOPCODE +Op14M1mod2: +lbl14mod2a: Direct +lbl14mod2b: TRB8 + NEXTOPCODE +Op15M1mod2: +lbl15mod2a: DirectIndexedX0 +lbl15mod2b: ORA8 + NEXTOPCODE +Op16M1mod2: +lbl16mod2a: DirectIndexedX0 +lbl16mod2b: ASL8 + NEXTOPCODE +Op17M1mod2: +lbl17mod2a: DirectIndirectIndexedLong0 +lbl17mod2b: ORA8 + NEXTOPCODE +Op18mod2: +lbl18mod2: Op18 + NEXTOPCODE +Op19M1mod2: +lbl19mod2a: AbsoluteIndexedY0 +lbl19mod2b: ORA8 + NEXTOPCODE +Op1AM1mod2: +lbl1Amod2a: A_INC8 + NEXTOPCODE +Op1Bmod2: +lbl1Bmod2: Op1BM1 + NEXTOPCODE +Op1CM1mod2: +lbl1Cmod2a: Absolute +lbl1Cmod2b: TRB8 + NEXTOPCODE +Op1DM1mod2: +lbl1Dmod2a: AbsoluteIndexedX0 +lbl1Dmod2b: ORA8 + NEXTOPCODE +Op1EM1mod2: +lbl1Emod2a: AbsoluteIndexedX0 +lbl1Emod2b: ASL8 + NEXTOPCODE +Op1FM1mod2: +lbl1Fmod2a: AbsoluteLongIndexedX0 +lbl1Fmod2b: ORA8 + NEXTOPCODE +Op20mod2: +lbl20mod2: Op20 + NEXTOPCODE +Op21M1mod2: +lbl21mod2a: DirectIndexedIndirect0 +lbl21mod2b: AND8 + NEXTOPCODE +Op22mod2: +lbl22mod2: Op22 + NEXTOPCODE +Op23M1mod2: +lbl23mod2a: StackasmRelative +lbl23mod2b: AND8 + NEXTOPCODE +Op24M1mod2: +lbl24mod2a: Direct +lbl24mod2b: BIT8 + NEXTOPCODE +Op25M1mod2: +lbl25mod2a: Direct +lbl25mod2b: AND8 + NEXTOPCODE +Op26M1mod2: +lbl26mod2a: Direct +lbl26mod2b: ROL8 + NEXTOPCODE +Op27M1mod2: +lbl27mod2a: DirectIndirectLong +lbl27mod2b: AND8 + NEXTOPCODE +Op28mod2: +lbl28mod2: Op28X0M1 + NEXTOPCODE +.pool +Op29M1mod2: +lbl29mod2: Op29M1 + NEXTOPCODE +Op2AM1mod2: +lbl2Amod2a: A_ROL8 + NEXTOPCODE +Op2Bmod2: +lbl2Bmod2: Op2B + NEXTOPCODE +Op2CM1mod2: +lbl2Cmod2a: Absolute +lbl2Cmod2b: BIT8 + NEXTOPCODE +Op2DM1mod2: +lbl2Dmod2a: Absolute +lbl2Dmod2b: AND8 + NEXTOPCODE +Op2EM1mod2: +lbl2Emod2a: Absolute +lbl2Emod2b: ROL8 + NEXTOPCODE +Op2FM1mod2: +lbl2Fmod2a: AbsoluteLong +lbl2Fmod2b: AND8 + NEXTOPCODE +Op30mod2: +lbl30mod2: Op30 + NEXTOPCODE +Op31M1mod2: +lbl31mod2a: DirectIndirectIndexed0 +lbl31mod2b: AND8 + NEXTOPCODE +Op32M1mod2: +lbl32mod2a: DirectIndirect +lbl32mod2b: AND8 + NEXTOPCODE +Op33M1mod2: +lbl33mod2a: StackasmRelativeIndirectIndexed0 +lbl33mod2b: AND8 + NEXTOPCODE +Op34M1mod2: +lbl34mod2a: DirectIndexedX0 +lbl34mod2b: BIT8 + NEXTOPCODE +Op35M1mod2: +lbl35mod2a: DirectIndexedX0 +lbl35mod2b: AND8 + NEXTOPCODE +Op36M1mod2: +lbl36mod2a: DirectIndexedX0 +lbl36mod2b: ROL8 + NEXTOPCODE +Op37M1mod2: +lbl37mod2a: DirectIndirectIndexedLong0 +lbl37mod2b: AND8 + NEXTOPCODE +Op38mod2: +lbl38mod2: Op38 + NEXTOPCODE +Op39M1mod2: +lbl39mod2a: AbsoluteIndexedY0 +lbl39mod2b: AND8 + NEXTOPCODE +Op3AM1mod2: +lbl3Amod2a: A_DEC8 + NEXTOPCODE +Op3Bmod2: +lbl3Bmod2: Op3BM1 + NEXTOPCODE +Op3CM1mod2: +lbl3Cmod2a: AbsoluteIndexedX0 +lbl3Cmod2b: BIT8 + NEXTOPCODE +Op3DM1mod2: +lbl3Dmod2a: AbsoluteIndexedX0 +lbl3Dmod2b: AND8 + NEXTOPCODE +Op3EM1mod2: +lbl3Emod2a: AbsoluteIndexedX0 +lbl3Emod2b: ROL8 + NEXTOPCODE +Op3FM1mod2: +lbl3Fmod2a: AbsoluteLongIndexedX0 +lbl3Fmod2b: AND8 + NEXTOPCODE +Op40mod2: +lbl40mod2: Op40X0M1 + NEXTOPCODE +.pool +Op41M1mod2: +lbl41mod2a: DirectIndexedIndirect0 +lbl41mod2b: EOR8 + NEXTOPCODE +Op42mod2: +lbl42mod2: Op42 + NEXTOPCODE +Op43M1mod2: +lbl43mod2a: StackasmRelative +lbl43mod2b: EOR8 + NEXTOPCODE +Op44X0mod2: +lbl44mod2: Op44X0M1 + NEXTOPCODE +Op45M1mod2: +lbl45mod2a: Direct +lbl45mod2b: EOR8 + NEXTOPCODE +Op46M1mod2: +lbl46mod2a: Direct +lbl46mod2b: LSR8 + NEXTOPCODE +Op47M1mod2: +lbl47mod2a: DirectIndirectLong +lbl47mod2b: EOR8 + NEXTOPCODE +Op48M1mod2: +lbl48mod2: Op48M1 + NEXTOPCODE +Op49M1mod2: +lbl49mod2: Op49M1 + NEXTOPCODE +Op4AM1mod2: +lbl4Amod2a: A_LSR8 + NEXTOPCODE +Op4Bmod2: +lbl4Bmod2: Op4B + NEXTOPCODE +Op4Cmod2: +lbl4Cmod2: Op4C + NEXTOPCODE +Op4DM1mod2: +lbl4Dmod2a: Absolute +lbl4Dmod2b: EOR8 + NEXTOPCODE +Op4EM1mod2: +lbl4Emod2a: Absolute +lbl4Emod2b: LSR8 + NEXTOPCODE +Op4FM1mod2: +lbl4Fmod2a: AbsoluteLong +lbl4Fmod2b: EOR8 + NEXTOPCODE +Op50mod2: +lbl50mod2: Op50 + NEXTOPCODE +Op51M1mod2: +lbl51mod2a: DirectIndirectIndexed0 +lbl51mod2b: EOR8 + NEXTOPCODE +Op52M1mod2: +lbl52mod2a: DirectIndirect +lbl52mod2b: EOR8 + NEXTOPCODE +Op53M1mod2: +lbl53mod2a: StackasmRelativeIndirectIndexed0 +lbl53mod2b: EOR8 + NEXTOPCODE +Op54X0mod2: +lbl54mod2: Op54X0M1 + NEXTOPCODE +Op55M1mod2: +lbl55mod2a: DirectIndexedX0 +lbl55mod2b: EOR8 + NEXTOPCODE +Op56M1mod2: +lbl56mod2a: DirectIndexedX0 +lbl56mod2b: LSR8 + NEXTOPCODE +Op57M1mod2: +lbl57mod2a: DirectIndirectIndexedLong0 +lbl57mod2b: EOR8 + NEXTOPCODE +Op58mod2: +lbl58mod2: Op58 + NEXTOPCODE +Op59M1mod2: +lbl59mod2a: AbsoluteIndexedY0 +lbl59mod2b: EOR8 + NEXTOPCODE +Op5AX0mod2: +lbl5Amod2: Op5AX0 + NEXTOPCODE +Op5Bmod2: +lbl5Bmod2: Op5BM1 + NEXTOPCODE +Op5Cmod2: +lbl5Cmod2: Op5C + NEXTOPCODE +Op5DM1mod2: +lbl5Dmod2a: AbsoluteIndexedX0 +lbl5Dmod2b: EOR8 + NEXTOPCODE +Op5EM1mod2: +lbl5Emod2a: AbsoluteIndexedX0 +lbl5Emod2b: LSR8 + NEXTOPCODE +Op5FM1mod2: +lbl5Fmod2a: AbsoluteLongIndexedX0 +lbl5Fmod2b: EOR8 + NEXTOPCODE +Op60mod2: +lbl60mod2: Op60 + NEXTOPCODE +Op61M1mod2: +lbl61mod2a: DirectIndexedIndirect0 +lbl61mod2b: ADC8 + NEXTOPCODE +Op62mod2: +lbl62mod2: Op62 + NEXTOPCODE +Op63M1mod2: +lbl63mod2a: StackasmRelative +lbl63mod2b: ADC8 + NEXTOPCODE +Op64M1mod2: +lbl64mod2a: Direct +lbl64mod2b: STZ8 + NEXTOPCODE +Op65M1mod2: +lbl65mod2a: Direct +lbl65mod2b: ADC8 + NEXTOPCODE +Op66M1mod2: +lbl66mod2a: Direct +lbl66mod2b: ROR8 + NEXTOPCODE +Op67M1mod2: +lbl67mod2a: DirectIndirectLong +lbl67mod2b: ADC8 + NEXTOPCODE +Op68M1mod2: +lbl68mod2: Op68M1 + NEXTOPCODE +Op69M1mod2: +lbl69mod2a: Immediate8 +lbl69mod2b: ADC8 + NEXTOPCODE +Op6AM1mod2: +lbl6Amod2a: A_ROR8 + NEXTOPCODE +Op6Bmod2: +lbl6Bmod2: Op6B + NEXTOPCODE +Op6Cmod2: +lbl6Cmod2: Op6C + NEXTOPCODE +Op6DM1mod2: +lbl6Dmod2a: Absolute +lbl6Dmod2b: ADC8 + NEXTOPCODE +Op6EM1mod2: +lbl6Emod2a: Absolute +lbl6Emod2b: ROR8 + NEXTOPCODE +Op6FM1mod2: +lbl6Fmod2a: AbsoluteLong +lbl6Fmod2b: ADC8 + NEXTOPCODE +Op70mod2: +lbl70mod2: Op70 + NEXTOPCODE +Op71M1mod2: +lbl71mod2a: DirectIndirectIndexed0 +lbl71mod2b: ADC8 + NEXTOPCODE +Op72M1mod2: +lbl72mod2a: DirectIndirect +lbl72mod2b: ADC8 + NEXTOPCODE +Op73M1mod2: +lbl73mod2a: StackasmRelativeIndirectIndexed0 +lbl73mod2b: ADC8 + NEXTOPCODE +Op74M1mod2: +lbl74mod2a: DirectIndexedX0 +lbl74mod2b: STZ8 + NEXTOPCODE +Op75M1mod2: +lbl75mod2a: DirectIndexedX0 +lbl75mod2b: ADC8 + NEXTOPCODE +Op76M1mod2: +lbl76mod2a: DirectIndexedX0 +lbl76mod2b: ROR8 + NEXTOPCODE +Op77M1mod2: +lbl77mod2a: DirectIndirectIndexedLong0 +lbl77mod2b: ADC8 + NEXTOPCODE +Op78mod2: +lbl78mod2: Op78 + NEXTOPCODE +Op79M1mod2: +lbl79mod2a: AbsoluteIndexedY0 +lbl79mod2b: ADC8 + NEXTOPCODE +Op7AX0mod2: +lbl7Amod2: Op7AX0 + NEXTOPCODE +Op7Bmod2: +lbl7Bmod2: Op7BM1 + NEXTOPCODE +Op7Cmod2: +lbl7Cmod2: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE +Op7DM1mod2: +lbl7Dmod2a: AbsoluteIndexedX0 +lbl7Dmod2b: ADC8 + NEXTOPCODE +Op7EM1mod2: +lbl7Emod2a: AbsoluteIndexedX0 +lbl7Emod2b: ROR8 + NEXTOPCODE +Op7FM1mod2: +lbl7Fmod2a: AbsoluteLongIndexedX0 +lbl7Fmod2b: ADC8 + NEXTOPCODE + + +Op80mod2: +lbl80mod2: Op80 + NEXTOPCODE +Op81M1mod2: +lbl81mod2a: DirectIndexedIndirect0 +lbl81mod2b: Op81M1 + NEXTOPCODE +Op82mod2: +lbl82mod2: Op82 + NEXTOPCODE +Op83M1mod2: +lbl83mod2a: StackasmRelative +lbl83mod2b: STA8 + NEXTOPCODE +Op84X0mod2: +lbl84mod2a: Direct +lbl84mod2b: STY16 + NEXTOPCODE +Op85M1mod2: +lbl85mod2a: Direct +lbl85mod2b: STA8 + NEXTOPCODE +Op86X0mod2: +lbl86mod2a: Direct +lbl86mod2b: STX16 + NEXTOPCODE +Op87M1mod2: +lbl87mod2a: DirectIndirectLong +lbl87mod2b: STA8 + NEXTOPCODE +Op88X0mod2: +lbl88mod2: Op88X0 + NEXTOPCODE +Op89M1mod2: +lbl89mod2: Op89M1 + NEXTOPCODE +Op8AM1mod2: +lbl8Amod2: Op8AM1X0 + NEXTOPCODE +Op8Bmod2: +lbl8Bmod2: Op8B + NEXTOPCODE +Op8CX0mod2: +lbl8Cmod2a: Absolute +lbl8Cmod2b: STY16 + NEXTOPCODE +Op8DM1mod2: +lbl8Dmod2a: Absolute +lbl8Dmod2b: STA8 + NEXTOPCODE +Op8EX0mod2: +lbl8Emod2a: Absolute +lbl8Emod2b: STX16 + NEXTOPCODE +Op8FM1mod2: +lbl8Fmod2a: AbsoluteLong +lbl8Fmod2b: STA8 + NEXTOPCODE +Op90mod2: +lbl90mod2: Op90 + NEXTOPCODE +Op91M1mod2: +lbl91mod2a: DirectIndirectIndexed0 +lbl91mod2b: STA8 + NEXTOPCODE +Op92M1mod2: +lbl92mod2a: DirectIndirect +lbl92mod2b: STA8 + NEXTOPCODE +Op93M1mod2: +lbl93mod2a: StackasmRelativeIndirectIndexed0 +lbl93mod2b: STA8 + NEXTOPCODE +Op94X0mod2: +lbl94mod2a: DirectIndexedX0 +lbl94mod2b: STY16 + NEXTOPCODE +Op95M1mod2: + +lbl95mod2a: DirectIndexedX0 +lbl95mod2b: STA8 + NEXTOPCODE +Op96X0mod2: +lbl96mod2a: DirectIndexedY0 +lbl96mod2b: STX16 + NEXTOPCODE +Op97M1mod2: +lbl97mod2a: DirectIndirectIndexedLong0 +lbl97mod2b: STA8 + NEXTOPCODE +Op98M1mod2: +lbl98mod2: Op98M1X0 + NEXTOPCODE +Op99M1mod2: +lbl99mod2a: AbsoluteIndexedY0 +lbl99mod2b: STA8 + NEXTOPCODE +Op9Amod2: +lbl9Amod2: Op9AX0 + NEXTOPCODE +Op9BX0mod2: +lbl9Bmod2: Op9BX0 + NEXTOPCODE +Op9CM1mod2: +lbl9Cmod2a: Absolute +lbl9Cmod2b: STZ8 + NEXTOPCODE +Op9DM1mod2: +lbl9Dmod2a: AbsoluteIndexedX0 +lbl9Dmod2b: STA8 + NEXTOPCODE +Op9EM1mod2: +lbl9Emod2: AbsoluteIndexedX0 + STZ8 + NEXTOPCODE +Op9FM1mod2: +lbl9Fmod2a: AbsoluteLongIndexedX0 +lbl9Fmod2b: STA8 + NEXTOPCODE +OpA0X0mod2: +lblA0mod2: OpA0X0 + NEXTOPCODE +OpA1M1mod2: +lblA1mod2a: DirectIndexedIndirect0 +lblA1mod2b: LDA8 + NEXTOPCODE +OpA2X0mod2: +lblA2mod2: OpA2X0 + NEXTOPCODE +OpA3M1mod2: +lblA3mod2a: StackasmRelative +lblA3mod2b: LDA8 + NEXTOPCODE +OpA4X0mod2: +lblA4mod2a: Direct +lblA4mod2b: LDY16 + NEXTOPCODE +OpA5M1mod2: +lblA5mod2a: Direct +lblA5mod2b: LDA8 + NEXTOPCODE +OpA6X0mod2: +lblA6mod2a: Direct +lblA6mod2b: LDX16 + NEXTOPCODE +OpA7M1mod2: +lblA7mod2a: DirectIndirectLong +lblA7mod2b: LDA8 + NEXTOPCODE +OpA8X0mod2: +lblA8mod2: OpA8X0M1 + NEXTOPCODE +OpA9M1mod2: +lblA9mod2: OpA9M1 + NEXTOPCODE +OpAAX0mod2: +lblAAmod2: OpAAX0M1 + NEXTOPCODE +OpABmod2: +lblABmod2: OpAB + NEXTOPCODE +OpACX0mod2: +lblACmod2a: Absolute +lblACmod2b: LDY16 + NEXTOPCODE +OpADM1mod2: +lblADmod2a: Absolute +lblADmod2b: LDA8 + NEXTOPCODE +OpAEX0mod2: +lblAEmod2a: Absolute +lblAEmod2b: LDX16 + NEXTOPCODE +OpAFM1mod2: +lblAFmod2a: AbsoluteLong +lblAFmod2b: LDA8 + NEXTOPCODE +OpB0mod2: +lblB0mod2: OpB0 + NEXTOPCODE +OpB1M1mod2: +lblB1mod2a: DirectIndirectIndexed0 +lblB1mod2b: LDA8 + NEXTOPCODE +OpB2M1mod2: +lblB2mod2a: DirectIndirect +lblB2mod2b: LDA8 + NEXTOPCODE +OpB3M1mod2: +lblB3mod2a: StackasmRelativeIndirectIndexed0 +lblB3mod2b: LDA8 + NEXTOPCODE +OpB4X0mod2: +lblB4mod2a: DirectIndexedX0 +lblB4mod2b: LDY16 + NEXTOPCODE +OpB5M1mod2: +lblB5mod2a: DirectIndexedX0 +lblB5mod2b: LDA8 + NEXTOPCODE +OpB6X0mod2: +lblB6mod2a: DirectIndexedY0 +lblB6mod2b: LDX16 + NEXTOPCODE +OpB7M1mod2: +lblB7mod2a: DirectIndirectIndexedLong0 +lblB7mod2b: LDA8 + NEXTOPCODE +OpB8mod2: +lblB8mod2: OpB8 + NEXTOPCODE +OpB9M1mod2: +lblB9mod2a: AbsoluteIndexedY0 +lblB9mod2b: LDA8 + NEXTOPCODE +OpBAX0mod2: +lblBAmod2: OpBAX0 + NEXTOPCODE +OpBBX0mod2: +lblBBmod2: OpBBX0 + NEXTOPCODE +OpBCX0mod2: +lblBCmod2a: AbsoluteIndexedX0 +lblBCmod2b: LDY16 + NEXTOPCODE +OpBDM1mod2: +lblBDmod2a: AbsoluteIndexedX0 +lblBDmod2b: LDA8 + NEXTOPCODE +OpBEX0mod2: +lblBEmod2a: AbsoluteIndexedY0 +lblBEmod2b: LDX16 + NEXTOPCODE +OpBFM1mod2: +lblBFmod2a: AbsoluteLongIndexedX0 +lblBFmod2b: LDA8 + NEXTOPCODE +OpC0X0mod2: +lblC0mod2: OpC0X0 + NEXTOPCODE +OpC1M1mod2: +lblC1mod2a: DirectIndexedIndirect0 +lblC1mod2b: CMP8 + NEXTOPCODE +OpC2mod2: +lblC2mod2: OpC2 + NEXTOPCODE +.pool +OpC3M1mod2: +lblC3mod2a: StackasmRelative +lblC3mod2b: CMP8 + NEXTOPCODE +OpC4X0mod2: +lblC4mod2a: Direct +lblC4mod2b: CMY16 + NEXTOPCODE +OpC5M1mod2: +lblC5mod2a: Direct +lblC5mod2b: CMP8 + NEXTOPCODE +OpC6M1mod2: +lblC6mod2a: Direct +lblC6mod2b: DEC8 + NEXTOPCODE +OpC7M1mod2: +lblC7mod2a: DirectIndirectLong +lblC7mod2b: CMP8 + NEXTOPCODE +OpC8X0mod2: +lblC8mod2: OpC8X0 + NEXTOPCODE +OpC9M1mod2: +lblC9mod2: OpC9M1 + NEXTOPCODE +OpCAX0mod2: +lblCAmod2: OpCAX0 + NEXTOPCODE +OpCBmod2: +lblCBmod2: OpCB + NEXTOPCODE +OpCCX0mod2: +lblCCmod2a: Absolute +lblCCmod2b: CMY16 + NEXTOPCODE +OpCDM1mod2: +lblCDmod2a: Absolute +lblCDmod2b: CMP8 + NEXTOPCODE +OpCEM1mod2: +lblCEmod2a: Absolute +lblCEmod2b: DEC8 + NEXTOPCODE +OpCFM1mod2: +lblCFmod2a: AbsoluteLong +lblCFmod2b: CMP8 + NEXTOPCODE +OpD0mod2: +lblD0mod2: OpD0 + NEXTOPCODE +OpD1M1mod2: +lblD1mod2a: DirectIndirectIndexed0 +lblD1mod2b: CMP8 + NEXTOPCODE +OpD2M1mod2: +lblD2mod2a: DirectIndirect +lblD2mod2b: CMP8 + NEXTOPCODE +OpD3M1mod2: +lblD3mod2a: StackasmRelativeIndirectIndexed0 +lblD3mod2b: CMP8 + NEXTOPCODE +OpD4mod2: +lblD4mod2: OpD4 + NEXTOPCODE +OpD5M1mod2: +lblD5mod2a: DirectIndexedX0 +lblD5mod2b: CMP8 + NEXTOPCODE +OpD6M1mod2: +lblD6mod2a: DirectIndexedX0 +lblD6mod2b: DEC8 + NEXTOPCODE +OpD7M1mod2: +lblD7mod2a: DirectIndirectIndexedLong0 +lblD7mod2b: CMP8 + NEXTOPCODE +OpD8mod2: +lblD8mod2: OpD8 + NEXTOPCODE +OpD9M1mod2: +lblD9mod2a: AbsoluteIndexedY0 +lblD9mod2b: CMP8 + NEXTOPCODE +OpDAX0mod2: +lblDAmod2: OpDAX0 + NEXTOPCODE +OpDBmod2: +lblDBmod2: OpDB + NEXTOPCODE +OpDCmod2: +lblDCmod2: OpDC + NEXTOPCODE +OpDDM1mod2: +lblDDmod2a: AbsoluteIndexedX0 +lblDDmod2b: CMP8 + NEXTOPCODE +OpDEM1mod2: +lblDEmod2a: AbsoluteIndexedX0 +lblDEmod2b: DEC8 + NEXTOPCODE +OpDFM1mod2: +lblDFmod2a: AbsoluteLongIndexedX0 +lblDFmod2b: CMP8 + NEXTOPCODE +OpE0X0mod2: +lblE0mod2: OpE0X0 + NEXTOPCODE +OpE1M1mod2: +lblE1mod2a: DirectIndexedIndirect0 +lblE1mod2b: SBC8 + NEXTOPCODE +OpE2mod2: +lblE2mod2: OpE2 + NEXTOPCODE +.pool +OpE3M1mod2: +lblE3mod2a: StackasmRelative +lblE3mod2b: SBC8 + NEXTOPCODE +OpE4X0mod2: +lblE4mod2a: Direct +lblE4mod2b: CMX16 + NEXTOPCODE +OpE5M1mod2: +lblE5mod2a: Direct +lblE5mod2b: SBC8 + NEXTOPCODE +OpE6M1mod2: +lblE6mod2a: Direct +lblE6mod2b: INC8 + NEXTOPCODE +OpE7M1mod2: +lblE7mod2a: DirectIndirectLong +lblE7mod2b: SBC8 + NEXTOPCODE +OpE8X0mod2: +lblE8mod2: OpE8X0 + NEXTOPCODE +OpE9M1mod2: +lblE9mod2a: Immediate8 +lblE9mod2b: SBC8 + NEXTOPCODE +OpEAmod2: +lblEAmod2: OpEA + NEXTOPCODE +OpEBmod2: +lblEBmod2: OpEBM1 + NEXTOPCODE +OpECX0mod2: +lblECmod2a: Absolute +lblECmod2b: CMX16 + NEXTOPCODE +OpEDM1mod2: +lblEDmod2a: Absolute +lblEDmod2b: SBC8 + NEXTOPCODE +OpEEM1mod2: +lblEEmod2a: Absolute +lblEEmod2b: INC8 + NEXTOPCODE +OpEFM1mod2: +lblEFmod2a: AbsoluteLong +lblEFmod2b: SBC8 + NEXTOPCODE +OpF0mod2: +lblF0mod2: OpF0 + NEXTOPCODE +OpF1M1mod2: +lblF1mod2a: DirectIndirectIndexed0 +lblF1mod2b: SBC8 + NEXTOPCODE +OpF2M1mod2: +lblF2mod2a: DirectIndirect +lblF2mod2b: SBC8 + NEXTOPCODE +OpF3M1mod2: +lblF3mod2a: StackasmRelativeIndirectIndexed0 +lblF3mod2b: SBC8 + NEXTOPCODE +OpF4mod2: +lblF4mod2: OpF4 + NEXTOPCODE +OpF5M1mod2: +lblF5mod2a: DirectIndexedX0 +lblF5mod2b: SBC8 + NEXTOPCODE +OpF6M1mod2: +lblF6mod2a: DirectIndexedX0 +lblF6mod2b: INC8 + NEXTOPCODE +OpF7M1mod2: +lblF7mod2a: DirectIndirectIndexedLong0 +lblF7mod2b: SBC8 + NEXTOPCODE +OpF8mod2: +lblF8mod2: OpF8 + NEXTOPCODE +OpF9M1mod2: +lblF9mod2a: AbsoluteIndexedY0 +lblF9mod2b: SBC8 + NEXTOPCODE +OpFAX0mod2: +lblFAmod2: OpFAX0 + NEXTOPCODE +OpFBmod2: +lblFBmod2: OpFB + NEXTOPCODE +OpFCmod2: +lblFCmod2: OpFCX0 + NEXTOPCODE +OpFDM1mod2: +lblFDmod2a: AbsoluteIndexedX0 +lblFDmod2b: SBC8 + NEXTOPCODE +OpFEM1mod2: +lblFEmod2a: AbsoluteIndexedX0 +lblFEmod2b: INC8 + NEXTOPCODE +OpFFM1mod2: +lblFFmod2a: AbsoluteLongIndexedX0 +lblFFmod2b: SBC8 + NEXTOPCODE + +.pool + + +jumptable3: .long Op00mod3 + .long Op01M0mod3 + .long Op02mod3 + .long Op03M0mod3 + .long Op04M0mod3 + .long Op05M0mod3 + .long Op06M0mod3 + .long Op07M0mod3 + .long Op08mod3 + .long Op09M0mod3 + .long Op0AM0mod3 + .long Op0Bmod3 + .long Op0CM0mod3 + .long Op0DM0mod3 + .long Op0EM0mod3 + .long Op0FM0mod3 + .long Op10mod3 + .long Op11M0mod3 + .long Op12M0mod3 + .long Op13M0mod3 + .long Op14M0mod3 + .long Op15M0mod3 + .long Op16M0mod3 + .long Op17M0mod3 + .long Op18mod3 + .long Op19M0mod3 + .long Op1AM0mod3 + .long Op1Bmod3 + .long Op1CM0mod3 + .long Op1DM0mod3 + .long Op1EM0mod3 + .long Op1FM0mod3 + .long Op20mod3 + .long Op21M0mod3 + .long Op22mod3 + .long Op23M0mod3 + .long Op24M0mod3 + .long Op25M0mod3 + .long Op26M0mod3 + .long Op27M0mod3 + .long Op28mod3 + .long Op29M0mod3 + .long Op2AM0mod3 + .long Op2Bmod3 + .long Op2CM0mod3 + .long Op2DM0mod3 + .long Op2EM0mod3 + .long Op2FM0mod3 + .long Op30mod3 + .long Op31M0mod3 + .long Op32M0mod3 + .long Op33M0mod3 + .long Op34M0mod3 + .long Op35M0mod3 + .long Op36M0mod3 + .long Op37M0mod3 + .long Op38mod3 + .long Op39M0mod3 + .long Op3AM0mod3 + .long Op3Bmod3 + .long Op3CM0mod3 + .long Op3DM0mod3 + .long Op3EM0mod3 + .long Op3FM0mod3 + .long Op40mod3 + .long Op41M0mod3 + .long Op42mod3 + .long Op43M0mod3 + .long Op44X0mod3 + .long Op45M0mod3 + .long Op46M0mod3 + .long Op47M0mod3 + .long Op48M0mod3 + .long Op49M0mod3 + .long Op4AM0mod3 + .long Op4Bmod3 + .long Op4Cmod3 + .long Op4DM0mod3 + .long Op4EM0mod3 + .long Op4FM0mod3 + .long Op50mod3 + .long Op51M0mod3 + .long Op52M0mod3 + .long Op53M0mod3 + .long Op54X0mod3 + .long Op55M0mod3 + .long Op56M0mod3 + .long Op57M0mod3 + .long Op58mod3 + .long Op59M0mod3 + .long Op5AX0mod3 + .long Op5Bmod3 + .long Op5Cmod3 + .long Op5DM0mod3 + .long Op5EM0mod3 + .long Op5FM0mod3 + .long Op60mod3 + .long Op61M0mod3 + .long Op62mod3 + .long Op63M0mod3 + .long Op64M0mod3 + .long Op65M0mod3 + .long Op66M0mod3 + .long Op67M0mod3 + .long Op68M0mod3 + .long Op69M0mod3 + .long Op6AM0mod3 + .long Op6Bmod3 + .long Op6Cmod3 + .long Op6DM0mod3 + .long Op6EM0mod3 + .long Op6FM0mod3 + .long Op70mod3 + .long Op71M0mod3 + .long Op72M0mod3 + .long Op73M0mod3 + .long Op74M0mod3 + .long Op75M0mod3 + .long Op76M0mod3 + .long Op77M0mod3 + .long Op78mod3 + .long Op79M0mod3 + .long Op7AX0mod3 + .long Op7Bmod3 + .long Op7Cmod3 + .long Op7DM0mod3 + .long Op7EM0mod3 + .long Op7FM0mod3 + .long Op80mod3 + .long Op81M0mod3 + .long Op82mod3 + .long Op83M0mod3 + .long Op84X0mod3 + .long Op85M0mod3 + .long Op86X0mod3 + .long Op87M0mod3 + .long Op88X0mod3 + .long Op89M0mod3 + .long Op8AM0mod3 + .long Op8Bmod3 + .long Op8CX0mod3 + .long Op8DM0mod3 + .long Op8EX0mod3 + .long Op8FM0mod3 + .long Op90mod3 + .long Op91M0mod3 + .long Op92M0mod3 + .long Op93M0mod3 + .long Op94X0mod3 + .long Op95M0mod3 + .long Op96X0mod3 + .long Op97M0mod3 + .long Op98M0mod3 + .long Op99M0mod3 + .long Op9Amod3 + .long Op9BX0mod3 + .long Op9CM0mod3 + .long Op9DM0mod3 + .long Op9EM0mod3 + .long Op9FM0mod3 + .long OpA0X0mod3 + .long OpA1M0mod3 + .long OpA2X0mod3 + .long OpA3M0mod3 + .long OpA4X0mod3 + .long OpA5M0mod3 + .long OpA6X0mod3 + .long OpA7M0mod3 + .long OpA8X0mod3 + .long OpA9M0mod3 + .long OpAAX0mod3 + .long OpABmod3 + .long OpACX0mod3 + .long OpADM0mod3 + .long OpAEX0mod3 + .long OpAFM0mod3 + .long OpB0mod3 + .long OpB1M0mod3 + .long OpB2M0mod3 + .long OpB3M0mod3 + .long OpB4X0mod3 + .long OpB5M0mod3 + .long OpB6X0mod3 + .long OpB7M0mod3 + .long OpB8mod3 + .long OpB9M0mod3 + .long OpBAX0mod3 + .long OpBBX0mod3 + .long OpBCX0mod3 + .long OpBDM0mod3 + .long OpBEX0mod3 + .long OpBFM0mod3 + .long OpC0X0mod3 + .long OpC1M0mod3 + .long OpC2mod3 + .long OpC3M0mod3 + .long OpC4X0mod3 + .long OpC5M0mod3 + .long OpC6M0mod3 + .long OpC7M0mod3 + .long OpC8X0mod3 + .long OpC9M0mod3 + .long OpCAX0mod3 + .long OpCBmod3 + .long OpCCX0mod3 + .long OpCDM0mod3 + .long OpCEM0mod3 + .long OpCFM0mod3 + .long OpD0mod3 + .long OpD1M0mod3 + .long OpD2M0mod3 + .long OpD3M0mod3 + .long OpD4mod3 + .long OpD5M0mod3 + .long OpD6M0mod3 + .long OpD7M0mod3 + .long OpD8mod3 + .long OpD9M0mod3 + .long OpDAX0mod3 + .long OpDBmod3 + .long OpDCmod3 + .long OpDDM0mod3 + .long OpDEM0mod3 + .long OpDFM0mod3 + .long OpE0X0mod3 + .long OpE1M0mod3 + .long OpE2mod3 + .long OpE3M0mod3 + .long OpE4X0mod3 + .long OpE5M0mod3 + .long OpE6M0mod3 + .long OpE7M0mod3 + .long OpE8X0mod3 + .long OpE9M0mod3 + .long OpEAmod3 + .long OpEBmod3 + .long OpECX0mod3 + .long OpEDM0mod3 + .long OpEEM0mod3 + .long OpEFM0mod3 + .long OpF0mod3 + .long OpF1M0mod3 + .long OpF2M0mod3 + .long OpF3M0mod3 + .long OpF4mod3 + .long OpF5M0mod3 + .long OpF6M0mod3 + .long OpF7M0mod3 + .long OpF8mod3 + .long OpF9M0mod3 + .long OpFAX0mod3 + .long OpFBmod3 + .long OpFCmod3 + .long OpFDM0mod3 + .long OpFEM0mod3 + .long OpFFM0mod3 +Op00mod3: +lbl00mod3: Op00 + NEXTOPCODE +Op01M0mod3: +lbl01mod3a: DirectIndexedIndirect0 +lbl01mod3b: ORA16 + NEXTOPCODE +Op02mod3: +lbl02mod3: Op02 + NEXTOPCODE +Op03M0mod3: +lbl03mod3a: StackasmRelative +lbl03mod3b: ORA16 + NEXTOPCODE +Op04M0mod3: +lbl04mod3a: Direct +lbl04mod3b: TSB16 + NEXTOPCODE +Op05M0mod3: +lbl05mod3a: Direct +lbl05mod3b: ORA16 + NEXTOPCODE +Op06M0mod3: +lbl06mod3a: Direct +lbl06mod3b: ASL16 + NEXTOPCODE +Op07M0mod3: +lbl07mod3a: DirectIndirectLong +lbl07mod3b: ORA16 + NEXTOPCODE +Op08mod3: +lbl08mod3: Op08 + NEXTOPCODE +Op09M0mod3: +lbl09mod3: Op09M0 + NEXTOPCODE +Op0AM0mod3: +lbl0Amod3a: A_ASL16 + NEXTOPCODE +Op0Bmod3: +lbl0Bmod3: Op0B + NEXTOPCODE +Op0CM0mod3: +lbl0Cmod3a: Absolute +lbl0Cmod3b: TSB16 + NEXTOPCODE +Op0DM0mod3: +lbl0Dmod3a: Absolute +lbl0Dmod3b: ORA16 + NEXTOPCODE +Op0EM0mod3: +lbl0Emod3a: Absolute +lbl0Emod3b: ASL16 + NEXTOPCODE +Op0FM0mod3: +lbl0Fmod3a: AbsoluteLong +lbl0Fmod3b: ORA16 + NEXTOPCODE +Op10mod3: +lbl10mod3: Op10 + NEXTOPCODE +Op11M0mod3: +lbl11mod3a: DirectIndirectIndexed0 +lbl11mod3b: ORA16 + NEXTOPCODE +Op12M0mod3: +lbl12mod3a: DirectIndirect +lbl12mod3b: ORA16 + NEXTOPCODE +Op13M0mod3: +lbl13mod3a: StackasmRelativeIndirectIndexed0 +lbl13mod3b: ORA16 + NEXTOPCODE +Op14M0mod3: +lbl14mod3a: Direct +lbl14mod3b: TRB16 + NEXTOPCODE +Op15M0mod3: +lbl15mod3a: DirectIndexedX0 +lbl15mod3b: ORA16 + NEXTOPCODE +Op16M0mod3: +lbl16mod3a: DirectIndexedX0 +lbl16mod3b: ASL16 + NEXTOPCODE +Op17M0mod3: +lbl17mod3a: DirectIndirectIndexedLong0 +lbl17mod3b: ORA16 + NEXTOPCODE +Op18mod3: +lbl18mod3: Op18 + NEXTOPCODE +Op19M0mod3: +lbl19mod3a: AbsoluteIndexedY0 +lbl19mod3b: ORA16 + NEXTOPCODE +Op1AM0mod3: +lbl1Amod3a: A_INC16 + NEXTOPCODE +Op1Bmod3: +lbl1Bmod3: Op1BM0 + NEXTOPCODE +Op1CM0mod3: +lbl1Cmod3a: Absolute +lbl1Cmod3b: TRB16 + NEXTOPCODE +Op1DM0mod3: +lbl1Dmod3a: AbsoluteIndexedX0 +lbl1Dmod3b: ORA16 + NEXTOPCODE +Op1EM0mod3: +lbl1Emod3a: AbsoluteIndexedX0 +lbl1Emod3b: ASL16 + NEXTOPCODE +Op1FM0mod3: +lbl1Fmod3a: AbsoluteLongIndexedX0 +lbl1Fmod3b: ORA16 + NEXTOPCODE +Op20mod3: +lbl20mod3: Op20 + NEXTOPCODE +Op21M0mod3: +lbl21mod3a: DirectIndexedIndirect0 +lbl21mod3b: AND16 + NEXTOPCODE +Op22mod3: +lbl22mod3: Op22 + NEXTOPCODE +Op23M0mod3: +lbl23mod3a: StackasmRelative +lbl23mod3b: AND16 + NEXTOPCODE +Op24M0mod3: +lbl24mod3a: Direct +lbl24mod3b: BIT16 + NEXTOPCODE +Op25M0mod3: +lbl25mod3a: Direct +lbl25mod3b: AND16 + NEXTOPCODE +Op26M0mod3: +lbl26mod3a: Direct +lbl26mod3b: ROL16 + NEXTOPCODE +Op27M0mod3: +lbl27mod3a: DirectIndirectLong + +lbl27mod3b: AND16 + NEXTOPCODE +Op28mod3: +lbl28mod3: Op28X0M0 + NEXTOPCODE +.pool +Op29M0mod3: +lbl29mod3: Op29M0 + NEXTOPCODE +Op2AM0mod3: +lbl2Amod3a: A_ROL16 + NEXTOPCODE +Op2Bmod3: +lbl2Bmod3: Op2B + NEXTOPCODE +Op2CM0mod3: +lbl2Cmod3a: Absolute +lbl2Cmod3b: BIT16 + NEXTOPCODE +Op2DM0mod3: +lbl2Dmod3a: Absolute +lbl2Dmod3b: AND16 + NEXTOPCODE +Op2EM0mod3: +lbl2Emod3a: Absolute +lbl2Emod3b: ROL16 + NEXTOPCODE +Op2FM0mod3: +lbl2Fmod3a: AbsoluteLong +lbl2Fmod3b: AND16 + NEXTOPCODE +Op30mod3: +lbl30mod3: Op30 + NEXTOPCODE +Op31M0mod3: +lbl31mod3a: DirectIndirectIndexed0 +lbl31mod3b: AND16 + NEXTOPCODE +Op32M0mod3: +lbl32mod3a: DirectIndirect +lbl32mod3b: AND16 + NEXTOPCODE +Op33M0mod3: +lbl33mod3a: StackasmRelativeIndirectIndexed0 +lbl33mod3b: AND16 + NEXTOPCODE +Op34M0mod3: +lbl34mod3a: DirectIndexedX0 +lbl34mod3b: BIT16 + NEXTOPCODE +Op35M0mod3: +lbl35mod3a: DirectIndexedX0 +lbl35mod3b: AND16 + NEXTOPCODE +Op36M0mod3: +lbl36mod3a: DirectIndexedX0 +lbl36mod3b: ROL16 + NEXTOPCODE +Op37M0mod3: +lbl37mod3a: DirectIndirectIndexedLong0 +lbl37mod3b: AND16 + NEXTOPCODE +Op38mod3: +lbl38mod3: Op38 + NEXTOPCODE +Op39M0mod3: +lbl39mod3a: AbsoluteIndexedY0 +lbl39mod3b: AND16 + NEXTOPCODE +Op3AM0mod3: +lbl3Amod3a: A_DEC16 + NEXTOPCODE +Op3Bmod3: +lbl3Bmod3: Op3BM0 + NEXTOPCODE +Op3CM0mod3: +lbl3Cmod3a: AbsoluteIndexedX0 +lbl3Cmod3b: BIT16 + NEXTOPCODE +Op3DM0mod3: +lbl3Dmod3a: AbsoluteIndexedX0 +lbl3Dmod3b: AND16 + NEXTOPCODE +Op3EM0mod3: +lbl3Emod3a: AbsoluteIndexedX0 +lbl3Emod3b: ROL16 + NEXTOPCODE +Op3FM0mod3: +lbl3Fmod3a: AbsoluteLongIndexedX0 +lbl3Fmod3b: AND16 + NEXTOPCODE +Op40mod3: +lbl40mod3: Op40X0M0 + NEXTOPCODE +.pool +Op41M0mod3: +lbl41mod3a: DirectIndexedIndirect0 +lbl41mod3b: EOR16 + NEXTOPCODE +Op42mod3: +lbl42mod3: Op42 + NEXTOPCODE +Op43M0mod3: +lbl43mod3a: StackasmRelative +lbl43mod3b: EOR16 + NEXTOPCODE +Op44X0mod3: +lbl44mod3: Op44X0M0 + NEXTOPCODE +Op45M0mod3: +lbl45mod3a: Direct +lbl45mod3b: EOR16 + NEXTOPCODE +Op46M0mod3: +lbl46mod3a: Direct +lbl46mod3b: LSR16 + NEXTOPCODE +Op47M0mod3: +lbl47mod3a: DirectIndirectLong +lbl47mod3b: EOR16 + NEXTOPCODE +Op48M0mod3: +lbl48mod3: Op48M0 + NEXTOPCODE +Op49M0mod3: +lbl49mod3: Op49M0 + NEXTOPCODE +Op4AM0mod3: +lbl4Amod3a: A_LSR16 + NEXTOPCODE +Op4Bmod3: +lbl4Bmod3: Op4B + NEXTOPCODE +Op4Cmod3: +lbl4Cmod3: Op4C + NEXTOPCODE +Op4DM0mod3: +lbl4Dmod3a: Absolute +lbl4Dmod3b: EOR16 + NEXTOPCODE +Op4EM0mod3: +lbl4Emod3a: Absolute +lbl4Emod3b: LSR16 + NEXTOPCODE +Op4FM0mod3: +lbl4Fmod3a: AbsoluteLong +lbl4Fmod3b: EOR16 + NEXTOPCODE +Op50mod3: +lbl50mod3: Op50 + NEXTOPCODE +Op51M0mod3: +lbl51mod3a: DirectIndirectIndexed0 +lbl51mod3b: EOR16 + NEXTOPCODE +Op52M0mod3: +lbl52mod3a: DirectIndirect +lbl52mod3b: EOR16 + NEXTOPCODE +Op53M0mod3: +lbl53mod3a: StackasmRelativeIndirectIndexed0 +lbl53mod3b: EOR16 + NEXTOPCODE +Op54X0mod3: +lbl54mod3: Op54X0M0 + NEXTOPCODE +Op55M0mod3: +lbl55mod3a: DirectIndexedX0 +lbl55mod3b: EOR16 + NEXTOPCODE +Op56M0mod3: +lbl56mod3a: DirectIndexedX0 +lbl56mod3b: LSR16 + NEXTOPCODE +Op57M0mod3: +lbl57mod3a: DirectIndirectIndexedLong0 +lbl57mod3b: EOR16 + NEXTOPCODE +Op58mod3: +lbl58mod3: Op58 + NEXTOPCODE +Op59M0mod3: +lbl59mod3a: AbsoluteIndexedY0 +lbl59mod3b: EOR16 + NEXTOPCODE +Op5AX0mod3: +lbl5Amod3: Op5AX0 + NEXTOPCODE +Op5Bmod3: +lbl5Bmod3: Op5BM0 + NEXTOPCODE +Op5Cmod3: +lbl5Cmod3: Op5C + NEXTOPCODE +Op5DM0mod3: +lbl5Dmod3a: AbsoluteIndexedX0 +lbl5Dmod3b: EOR16 + NEXTOPCODE +Op5EM0mod3: +lbl5Emod3a: AbsoluteIndexedX0 +lbl5Emod3b: LSR16 + NEXTOPCODE +Op5FM0mod3: +lbl5Fmod3a: AbsoluteLongIndexedX0 +lbl5Fmod3b: EOR16 + NEXTOPCODE +Op60mod3: +lbl60mod3: Op60 + NEXTOPCODE +Op61M0mod3: +lbl61mod3a: DirectIndexedIndirect0 +lbl61mod3b: ADC16 + NEXTOPCODE +Op62mod3: +lbl62mod3: Op62 + NEXTOPCODE +Op63M0mod3: +lbl63mod3a: StackasmRelative +lbl63mod3b: ADC16 + NEXTOPCODE +.pool +Op64M0mod3: +lbl64mod3a: Direct +lbl64mod3b: STZ16 + NEXTOPCODE +Op65M0mod3: +lbl65mod3a: Direct +lbl65mod3b: ADC16 + NEXTOPCODE +.pool +Op66M0mod3: +lbl66mod3a: Direct +lbl66mod3b: ROR16 + NEXTOPCODE +Op67M0mod3: +lbl67mod3a: DirectIndirectLong +lbl67mod3b: ADC16 + NEXTOPCODE +.pool +Op68M0mod3: +lbl68mod3: Op68M0 + NEXTOPCODE +Op69M0mod3: +lbl69mod3a: Immediate16 +lbl69mod3b: ADC16 + NEXTOPCODE +.pool +Op6AM0mod3: +lbl6Amod3a: A_ROR16 + NEXTOPCODE +Op6Bmod3: +lbl6Bmod3: Op6B + NEXTOPCODE +Op6Cmod3: +lbl6Cmod3: Op6C + NEXTOPCODE +Op6DM0mod3: +lbl6Dmod3a: Absolute +lbl6Dmod3b: ADC16 + NEXTOPCODE +Op6EM0mod3: +lbl6Emod3a: Absolute +lbl6Emod3b: ROR16 + NEXTOPCODE +Op6FM0mod3: +lbl6Fmod3a: AbsoluteLong +lbl6Fmod3b: ADC16 + NEXTOPCODE +Op70mod3: +lbl70mod3: Op70 + NEXTOPCODE +Op71M0mod3: +lbl71mod3a: DirectIndirectIndexed0 +lbl71mod3b: ADC16 + NEXTOPCODE +Op72M0mod3: +lbl72mod3a: DirectIndirect +lbl72mod3b: ADC16 + NEXTOPCODE +Op73M0mod3: +lbl73mod3a: StackasmRelativeIndirectIndexed0 +lbl73mod3b: ADC16 + NEXTOPCODE +.pool +Op74M0mod3: +lbl74mod3a: DirectIndexedX0 +lbl74mod3b: STZ16 + NEXTOPCODE +Op75M0mod3: +lbl75mod3a: DirectIndexedX0 +lbl75mod3b: ADC16 + NEXTOPCODE +.pool +Op76M0mod3: +lbl76mod3a: DirectIndexedX0 +lbl76mod3b: ROR16 + NEXTOPCODE +Op77M0mod3: +lbl77mod3a: DirectIndirectIndexedLong0 +lbl77mod3b: ADC16 + NEXTOPCODE +Op78mod3: +lbl78mod3: Op78 + NEXTOPCODE +Op79M0mod3: +lbl79mod3a: AbsoluteIndexedY0 +lbl79mod3b: ADC16 + NEXTOPCODE +Op7AX0mod3: +lbl7Amod3: Op7AX0 + NEXTOPCODE +Op7Bmod3: +lbl7Bmod3: Op7BM0 + NEXTOPCODE +Op7Cmod3: +lbl7Cmod3: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE +Op7DM0mod3: +lbl7Dmod3a: AbsoluteIndexedX0 +lbl7Dmod3b: ADC16 + NEXTOPCODE +Op7EM0mod3: +lbl7Emod3a: AbsoluteIndexedX0 +lbl7Emod3b: ROR16 + NEXTOPCODE +Op7FM0mod3: +lbl7Fmod3a: AbsoluteLongIndexedX0 +lbl7Fmod3b: ADC16 + NEXTOPCODE +.pool +Op80mod3: +lbl80mod3: Op80 + NEXTOPCODE +Op81M0mod3: +lbl81mod3a: DirectIndexedIndirect0 +lbl81mod3b: Op81M0 + NEXTOPCODE +Op82mod3: +lbl82mod3: Op82 + NEXTOPCODE +Op83M0mod3: +lbl83mod3a: StackasmRelative +lbl83mod3b: STA16 + NEXTOPCODE +Op84X0mod3: +lbl84mod3a: Direct +lbl84mod3b: STY16 + NEXTOPCODE +Op85M0mod3: +lbl85mod3a: Direct +lbl85mod3b: STA16 + NEXTOPCODE +Op86X0mod3: +lbl86mod3a: Direct +lbl86mod3b: STX16 + NEXTOPCODE +Op87M0mod3: +lbl87mod3a: DirectIndirectLong +lbl87mod3b: STA16 + NEXTOPCODE +Op88X0mod3: +lbl88mod3: Op88X0 + NEXTOPCODE +Op89M0mod3: +lbl89mod3: Op89M0 + NEXTOPCODE +Op8AM0mod3: +lbl8Amod3: Op8AM0X0 + NEXTOPCODE +Op8Bmod3: +lbl8Bmod3: Op8B + NEXTOPCODE +Op8CX0mod3: +lbl8Cmod3a: Absolute +lbl8Cmod3b: STY16 + NEXTOPCODE +Op8DM0mod3: +lbl8Dmod3a: Absolute +lbl8Dmod3b: STA16 + NEXTOPCODE +Op8EX0mod3: +lbl8Emod3a: Absolute +lbl8Emod3b: STX16 + NEXTOPCODE +Op8FM0mod3: +lbl8Fmod3a: AbsoluteLong +lbl8Fmod3b: STA16 + NEXTOPCODE +Op90mod3: +lbl90mod3: Op90 + NEXTOPCODE +Op91M0mod3: +lbl91mod3a: DirectIndirectIndexed0 +lbl91mod3b: STA16 + NEXTOPCODE +Op92M0mod3: +lbl92mod3a: DirectIndirect +lbl92mod3b: STA16 + NEXTOPCODE +Op93M0mod3: +lbl93mod3a: StackasmRelativeIndirectIndexed0 +lbl93mod3b: STA16 + NEXTOPCODE +Op94X0mod3: +lbl94mod3a: DirectIndexedX0 +lbl94mod3b: STY16 + NEXTOPCODE +Op95M0mod3: +lbl95mod3a: DirectIndexedX0 +lbl95mod3b: STA16 + NEXTOPCODE +Op96X0mod3: +lbl96mod3a: DirectIndexedY0 +lbl96mod3b: STX16 + NEXTOPCODE +Op97M0mod3: +lbl97mod3a: DirectIndirectIndexedLong0 +lbl97mod3b: STA16 + NEXTOPCODE +Op98M0mod3: +lbl98mod3: Op98M0X0 + NEXTOPCODE +Op99M0mod3: +lbl99mod3a: AbsoluteIndexedY0 +lbl99mod3b: STA16 + NEXTOPCODE +Op9Amod3: +lbl9Amod3: Op9AX0 + NEXTOPCODE +Op9BX0mod3: +lbl9Bmod3: Op9BX0 + NEXTOPCODE +Op9CM0mod3: +lbl9Cmod3a: Absolute +lbl9Cmod3b: STZ16 + NEXTOPCODE +Op9DM0mod3: +lbl9Dmod3a: AbsoluteIndexedX0 +lbl9Dmod3b: STA16 + NEXTOPCODE +Op9EM0mod3: +lbl9Emod3: AbsoluteIndexedX0 + STZ16 + NEXTOPCODE +Op9FM0mod3: +lbl9Fmod3a: AbsoluteLongIndexedX0 +lbl9Fmod3b: STA16 + NEXTOPCODE +OpA0X0mod3: +lblA0mod3: OpA0X0 + NEXTOPCODE +OpA1M0mod3: +lblA1mod3a: DirectIndexedIndirect0 +lblA1mod3b: LDA16 + NEXTOPCODE +OpA2X0mod3: +lblA2mod3: OpA2X0 + NEXTOPCODE +OpA3M0mod3: +lblA3mod3a: StackasmRelative +lblA3mod3b: LDA16 + NEXTOPCODE +OpA4X0mod3: +lblA4mod3a: Direct +lblA4mod3b: LDY16 + NEXTOPCODE +OpA5M0mod3: +lblA5mod3a: Direct +lblA5mod3b: LDA16 + NEXTOPCODE +OpA6X0mod3: +lblA6mod3a: Direct +lblA6mod3b: LDX16 + NEXTOPCODE +OpA7M0mod3: +lblA7mod3a: DirectIndirectLong +lblA7mod3b: LDA16 + NEXTOPCODE +OpA8X0mod3: +lblA8mod3: OpA8X0M0 + NEXTOPCODE +OpA9M0mod3: +lblA9mod3: OpA9M0 + NEXTOPCODE +OpAAX0mod3: +lblAAmod3: OpAAX0M0 + NEXTOPCODE +OpABmod3: +lblABmod3: OpAB + NEXTOPCODE +OpACX0mod3: +lblACmod3a: Absolute +lblACmod3b: LDY16 + NEXTOPCODE +OpADM0mod3: +lblADmod3a: Absolute +lblADmod3b: LDA16 + NEXTOPCODE +OpAEX0mod3: +lblAEmod3a: Absolute +lblAEmod3b: LDX16 + NEXTOPCODE +OpAFM0mod3: +lblAFmod3a: AbsoluteLong +lblAFmod3b: LDA16 + NEXTOPCODE +OpB0mod3: +lblB0mod3: OpB0 + NEXTOPCODE +OpB1M0mod3: +lblB1mod3a: DirectIndirectIndexed0 +lblB1mod3b: LDA16 + NEXTOPCODE +OpB2M0mod3: +lblB2mod3a: DirectIndirect +lblB2mod3b: LDA16 + NEXTOPCODE +OpB3M0mod3: +lblB3mod3a: StackasmRelativeIndirectIndexed0 +lblB3mod3b: LDA16 + NEXTOPCODE +OpB4X0mod3: +lblB4mod3a: DirectIndexedX0 +lblB4mod3b: LDY16 + NEXTOPCODE +OpB5M0mod3: +lblB5mod3a: DirectIndexedX0 +lblB5mod3b: LDA16 + NEXTOPCODE +OpB6X0mod3: +lblB6mod3a: DirectIndexedY0 +lblB6mod3b: LDX16 + NEXTOPCODE +OpB7M0mod3: +lblB7mod3a: DirectIndirectIndexedLong0 +lblB7mod3b: LDA16 + NEXTOPCODE +OpB8mod3: +lblB8mod3: OpB8 + NEXTOPCODE +OpB9M0mod3: +lblB9mod3a: AbsoluteIndexedY0 +lblB9mod3b: LDA16 + NEXTOPCODE +OpBAX0mod3: +lblBAmod3: OpBAX0 + NEXTOPCODE +OpBBX0mod3: +lblBBmod3: OpBBX0 + NEXTOPCODE +OpBCX0mod3: +lblBCmod3a: AbsoluteIndexedX0 +lblBCmod3b: LDY16 + NEXTOPCODE +OpBDM0mod3: +lblBDmod3a: AbsoluteIndexedX0 +lblBDmod3b: LDA16 + NEXTOPCODE +OpBEX0mod3: +lblBEmod3a: AbsoluteIndexedY0 +lblBEmod3b: LDX16 + NEXTOPCODE +OpBFM0mod3: +lblBFmod3a: AbsoluteLongIndexedX0 +lblBFmod3b: LDA16 + NEXTOPCODE +OpC0X0mod3: +lblC0mod3: OpC0X0 + NEXTOPCODE +OpC1M0mod3: +lblC1mod3a: DirectIndexedIndirect0 +lblC1mod3b: CMP16 + NEXTOPCODE +OpC2mod3: +lblC2mod3: OpC2 + NEXTOPCODE +.pool +OpC3M0mod3: +lblC3mod3a: StackasmRelative +lblC3mod3b: CMP16 + NEXTOPCODE +OpC4X0mod3: +lblC4mod3a: Direct +lblC4mod3b: CMY16 + NEXTOPCODE +OpC5M0mod3: +lblC5mod3a: Direct +lblC5mod3b: CMP16 + NEXTOPCODE +OpC6M0mod3: +lblC6mod3a: Direct +lblC6mod3b: DEC16 + NEXTOPCODE +OpC7M0mod3: +lblC7mod3a: DirectIndirectLong +lblC7mod3b: CMP16 + NEXTOPCODE +OpC8X0mod3: +lblC8mod3: OpC8X0 + NEXTOPCODE +OpC9M0mod3: +lblC9mod3: OpC9M0 + NEXTOPCODE +OpCAX0mod3: +lblCAmod3: OpCAX0 + NEXTOPCODE +OpCBmod3: +lblCBmod3: OpCB + NEXTOPCODE +OpCCX0mod3: +lblCCmod3a: Absolute +lblCCmod3b: CMY16 + NEXTOPCODE +OpCDM0mod3: +lblCDmod3a: Absolute +lblCDmod3b: CMP16 + NEXTOPCODE +OpCEM0mod3: +lblCEmod3a: Absolute +lblCEmod3b: DEC16 + NEXTOPCODE +OpCFM0mod3: +lblCFmod3a: AbsoluteLong +lblCFmod3b: CMP16 + NEXTOPCODE +OpD0mod3: +lblD0mod3: OpD0 + NEXTOPCODE +OpD1M0mod3: +lblD1mod3a: DirectIndirectIndexed0 +lblD1mod3b: CMP16 + NEXTOPCODE +OpD2M0mod3: +lblD2mod3a: DirectIndirect +lblD2mod3b: CMP16 + NEXTOPCODE +OpD3M0mod3: +lblD3mod3a: StackasmRelativeIndirectIndexed0 +lblD3mod3b: CMP16 + NEXTOPCODE +OpD4mod3: +lblD4mod3: OpD4 + NEXTOPCODE +OpD5M0mod3: +lblD5mod3a: DirectIndexedX0 +lblD5mod3b: CMP16 + NEXTOPCODE +OpD6M0mod3: +lblD6mod3a: DirectIndexedX0 +lblD6mod3b: DEC16 + NEXTOPCODE +OpD7M0mod3: +lblD7mod3a: DirectIndirectIndexedLong0 +lblD7mod3b: CMP16 + NEXTOPCODE +OpD8mod3: +lblD8mod3: OpD8 + NEXTOPCODE +OpD9M0mod3: +lblD9mod3a: AbsoluteIndexedY0 +lblD9mod3b: CMP16 + NEXTOPCODE +OpDAX0mod3: +lblDAmod3: OpDAX0 + NEXTOPCODE +OpDBmod3: +lblDBmod3: OpDB + NEXTOPCODE +OpDCmod3: +lblDCmod3: OpDC + NEXTOPCODE +OpDDM0mod3: +lblDDmod3a: AbsoluteIndexedX0 +lblDDmod3b: CMP16 + NEXTOPCODE +OpDEM0mod3: +lblDEmod3a: AbsoluteIndexedX0 +lblDEmod3b: DEC16 + NEXTOPCODE +OpDFM0mod3: +lblDFmod3a: AbsoluteLongIndexedX0 +lblDFmod3b: CMP16 + NEXTOPCODE +OpE0X0mod3: +lblE0mod3: OpE0X0 + NEXTOPCODE +OpE1M0mod3: +lblE1mod3a: DirectIndexedIndirect0 +lblE1mod3b: SBC16 + NEXTOPCODE +OpE2mod3: +lblE2mod3: OpE2 + NEXTOPCODE +.pool +OpE3M0mod3: +lblE3mod3a: StackasmRelative +lblE3mod3b: SBC16 + NEXTOPCODE +OpE4X0mod3: +lblE4mod3a: Direct +lblE4mod3b: CMX16 + NEXTOPCODE +OpE5M0mod3: +lblE5mod3a: Direct +lblE5mod3b: SBC16 + NEXTOPCODE +OpE6M0mod3: +lblE6mod3a: Direct +lblE6mod3b: INC16 + NEXTOPCODE +OpE7M0mod3: +lblE7mod3a: DirectIndirectLong +lblE7mod3b: SBC16 + NEXTOPCODE +OpE8X0mod3: +lblE8mod3: OpE8X0 + NEXTOPCODE +OpE9M0mod3: +lblE9mod3a: Immediate16 +lblE9mod3b: SBC16 + NEXTOPCODE +OpEAmod3: +lblEAmod3: OpEA + NEXTOPCODE +OpEBmod3: +lblEBmod3: OpEBM0 + NEXTOPCODE +OpECX0mod3: +lblECmod3a: Absolute +lblECmod3b: CMX16 + NEXTOPCODE +OpEDM0mod3: +lblEDmod3a: Absolute +lblEDmod3b: SBC16 + NEXTOPCODE +OpEEM0mod3: +lblEEmod3a: Absolute +lblEEmod3b: INC16 + NEXTOPCODE +OpEFM0mod3: +lblEFmod3a: AbsoluteLong +lblEFmod3b: SBC16 + NEXTOPCODE +OpF0mod3: +lblF0mod3: OpF0 + NEXTOPCODE +OpF1M0mod3: +lblF1mod3a: DirectIndirectIndexed0 +lblF1mod3b: SBC16 + NEXTOPCODE +OpF2M0mod3: +lblF2mod3a: DirectIndirect +lblF2mod3b: SBC16 + NEXTOPCODE +OpF3M0mod3: +lblF3mod3a: StackasmRelativeIndirectIndexed0 +lblF3mod3b: SBC16 + NEXTOPCODE +OpF4mod3: +lblF4mod3: OpF4 + NEXTOPCODE +OpF5M0mod3: +lblF5mod3a: DirectIndexedX0 +lblF5mod3b: SBC16 + NEXTOPCODE +OpF6M0mod3: +lblF6mod3a: DirectIndexedX0 +lblF6mod3b: INC16 + NEXTOPCODE +OpF7M0mod3: +lblF7mod3a: DirectIndirectIndexedLong0 +lblF7mod3b: SBC16 + NEXTOPCODE +OpF8mod3: +lblF8mod3: OpF8 + NEXTOPCODE +OpF9M0mod3: +lblF9mod3a: AbsoluteIndexedY0 +lblF9mod3b: SBC16 + NEXTOPCODE +OpFAX0mod3: +lblFAmod3: OpFAX0 + NEXTOPCODE +OpFBmod3: +lblFBmod3: OpFB + NEXTOPCODE +OpFCmod3: +lblFCmod3: OpFCX0 + NEXTOPCODE +OpFDM0mod3: +lblFDmod3a: AbsoluteIndexedX0 +lblFDmod3b: SBC16 + NEXTOPCODE +OpFEM0mod3: +lblFEmod3a: AbsoluteIndexedX0 +lblFEmod3b: INC16 + NEXTOPCODE +OpFFM0mod3: +lblFFmod3a: AbsoluteLongIndexedX0 +lblFFmod3b: SBC16 + NEXTOPCODE +.pool + +jumptable4: .long Op00mod4 + .long Op01M0mod4 + .long Op02mod4 + .long Op03M0mod4 + .long Op04M0mod4 + .long Op05M0mod4 + .long Op06M0mod4 + .long Op07M0mod4 + .long Op08mod4 + .long Op09M0mod4 + .long Op0AM0mod4 + .long Op0Bmod4 + .long Op0CM0mod4 + .long Op0DM0mod4 + .long Op0EM0mod4 + .long Op0FM0mod4 + .long Op10mod4 + .long Op11M0mod4 + .long Op12M0mod4 + .long Op13M0mod4 + .long Op14M0mod4 + .long Op15M0mod4 + .long Op16M0mod4 + .long Op17M0mod4 + .long Op18mod4 + .long Op19M0mod4 + .long Op1AM0mod4 + .long Op1Bmod4 + .long Op1CM0mod4 + .long Op1DM0mod4 + .long Op1EM0mod4 + .long Op1FM0mod4 + .long Op20mod4 + .long Op21M0mod4 + .long Op22mod4 + .long Op23M0mod4 + .long Op24M0mod4 + .long Op25M0mod4 + .long Op26M0mod4 + .long Op27M0mod4 + .long Op28mod4 + .long Op29M0mod4 + .long Op2AM0mod4 + .long Op2Bmod4 + .long Op2CM0mod4 + .long Op2DM0mod4 + .long Op2EM0mod4 + .long Op2FM0mod4 + .long Op30mod4 + .long Op31M0mod4 + .long Op32M0mod4 + .long Op33M0mod4 + .long Op34M0mod4 + .long Op35M0mod4 + .long Op36M0mod4 + .long Op37M0mod4 + .long Op38mod4 + .long Op39M0mod4 + .long Op3AM0mod4 + .long Op3Bmod4 + .long Op3CM0mod4 + .long Op3DM0mod4 + .long Op3EM0mod4 + .long Op3FM0mod4 + .long Op40mod4 + .long Op41M0mod4 + .long Op42mod4 + .long Op43M0mod4 + .long Op44X1mod4 + .long Op45M0mod4 + .long Op46M0mod4 + .long Op47M0mod4 + .long Op48M0mod4 + .long Op49M0mod4 + .long Op4AM0mod4 + .long Op4Bmod4 + .long Op4Cmod4 + .long Op4DM0mod4 + .long Op4EM0mod4 + .long Op4FM0mod4 + .long Op50mod4 + .long Op51M0mod4 + .long Op52M0mod4 + .long Op53M0mod4 + .long Op54X1mod4 + .long Op55M0mod4 + .long Op56M0mod4 + .long Op57M0mod4 + .long Op58mod4 + .long Op59M0mod4 + .long Op5AX1mod4 + .long Op5Bmod4 + .long Op5Cmod4 + .long Op5DM0mod4 + .long Op5EM0mod4 + .long Op5FM0mod4 + .long Op60mod4 + .long Op61M0mod4 + .long Op62mod4 + .long Op63M0mod4 + .long Op64M0mod4 + .long Op65M0mod4 + .long Op66M0mod4 + .long Op67M0mod4 + .long Op68M0mod4 + .long Op69M0mod4 + .long Op6AM0mod4 + .long Op6Bmod4 + .long Op6Cmod4 + .long Op6DM0mod4 + .long Op6EM0mod4 + .long Op6FM0mod4 + .long Op70mod4 + .long Op71M0mod4 + .long Op72M0mod4 + .long Op73M0mod4 + .long Op74M0mod4 + .long Op75M0mod4 + .long Op76M0mod4 + .long Op77M0mod4 + .long Op78mod4 + .long Op79M0mod4 + .long Op7AX1mod4 + .long Op7Bmod4 + .long Op7Cmod4 + .long Op7DM0mod4 + .long Op7EM0mod4 + .long Op7FM0mod4 + .long Op80mod4 + .long Op81M0mod4 + .long Op82mod4 + .long Op83M0mod4 + .long Op84X1mod4 + .long Op85M0mod4 + .long Op86X1mod4 + .long Op87M0mod4 + .long Op88X1mod4 + .long Op89M0mod4 + .long Op8AM0mod4 + .long Op8Bmod4 + .long Op8CX1mod4 + .long Op8DM0mod4 + .long Op8EX1mod4 + .long Op8FM0mod4 + .long Op90mod4 + .long Op91M0mod4 + .long Op92M0mod4 + .long Op93M0mod4 + .long Op94X1mod4 + .long Op95M0mod4 + .long Op96X1mod4 + .long Op97M0mod4 + .long Op98M0mod4 + .long Op99M0mod4 + .long Op9Amod4 + .long Op9BX1mod4 + .long Op9CM0mod4 + .long Op9DM0mod4 + + .long Op9EM0mod4 + .long Op9FM0mod4 + .long OpA0X1mod4 + .long OpA1M0mod4 + .long OpA2X1mod4 + .long OpA3M0mod4 + .long OpA4X1mod4 + .long OpA5M0mod4 + .long OpA6X1mod4 + .long OpA7M0mod4 + .long OpA8X1mod4 + .long OpA9M0mod4 + .long OpAAX1mod4 + .long OpABmod4 + .long OpACX1mod4 + .long OpADM0mod4 + .long OpAEX1mod4 + .long OpAFM0mod4 + .long OpB0mod4 + .long OpB1M0mod4 + .long OpB2M0mod4 + .long OpB3M0mod4 + .long OpB4X1mod4 + .long OpB5M0mod4 + .long OpB6X1mod4 + .long OpB7M0mod4 + .long OpB8mod4 + .long OpB9M0mod4 + .long OpBAX1mod4 + .long OpBBX1mod4 + .long OpBCX1mod4 + .long OpBDM0mod4 + .long OpBEX1mod4 + .long OpBFM0mod4 + .long OpC0X1mod4 + .long OpC1M0mod4 + .long OpC2mod4 + .long OpC3M0mod4 + .long OpC4X1mod4 + .long OpC5M0mod4 + .long OpC6M0mod4 + .long OpC7M0mod4 + .long OpC8X1mod4 + .long OpC9M0mod4 + .long OpCAX1mod4 + .long OpCBmod4 + .long OpCCX1mod4 + .long OpCDM0mod4 + .long OpCEM0mod4 + .long OpCFM0mod4 + .long OpD0mod4 + .long OpD1M0mod4 + .long OpD2M0mod4 + .long OpD3M0mod4 + .long OpD4mod4 + .long OpD5M0mod4 + .long OpD6M0mod4 + .long OpD7M0mod4 + .long OpD8mod4 + .long OpD9M0mod4 + .long OpDAX1mod4 + .long OpDBmod4 + .long OpDCmod4 + .long OpDDM0mod4 + .long OpDEM0mod4 + .long OpDFM0mod4 + .long OpE0X1mod4 + .long OpE1M0mod4 + .long OpE2mod4 + .long OpE3M0mod4 + .long OpE4X1mod4 + .long OpE5M0mod4 + .long OpE6M0mod4 + .long OpE7M0mod4 + .long OpE8X1mod4 + .long OpE9M0mod4 + .long OpEAmod4 + .long OpEBmod4 + .long OpECX1mod4 + .long OpEDM0mod4 + .long OpEEM0mod4 + .long OpEFM0mod4 + .long OpF0mod4 + .long OpF1M0mod4 + .long OpF2M0mod4 + .long OpF3M0mod4 + .long OpF4mod4 + .long OpF5M0mod4 + .long OpF6M0mod4 + .long OpF7M0mod4 + .long OpF8mod4 + .long OpF9M0mod4 + .long OpFAX1mod4 + .long OpFBmod4 + .long OpFCmod4 + .long OpFDM0mod4 + .long OpFEM0mod4 + .long OpFFM0mod4 +Op00mod4: +lbl00mod4: Op00 + NEXTOPCODE +Op01M0mod4: +lbl01mod4a: DirectIndexedIndirect1 +lbl01mod4b: ORA16 + NEXTOPCODE +Op02mod4: +lbl02mod4: Op02 + NEXTOPCODE +Op03M0mod4: +lbl03mod4a: StackasmRelative +lbl03mod4b: ORA16 + NEXTOPCODE +Op04M0mod4: +lbl04mod4a: Direct +lbl04mod4b: TSB16 + NEXTOPCODE +Op05M0mod4: +lbl05mod4a: Direct +lbl05mod4b: ORA16 + NEXTOPCODE +Op06M0mod4: +lbl06mod4a: Direct +lbl06mod4b: ASL16 + NEXTOPCODE +Op07M0mod4: +lbl07mod4a: DirectIndirectLong +lbl07mod4b: ORA16 + NEXTOPCODE +Op08mod4: +lbl08mod4: Op08 + NEXTOPCODE +Op09M0mod4: +lbl09mod4: Op09M0 + NEXTOPCODE +Op0AM0mod4: +lbl0Amod4a: A_ASL16 + NEXTOPCODE +Op0Bmod4: +lbl0Bmod4: Op0B + NEXTOPCODE +Op0CM0mod4: +lbl0Cmod4a: Absolute +lbl0Cmod4b: TSB16 + NEXTOPCODE +Op0DM0mod4: +lbl0Dmod4a: Absolute +lbl0Dmod4b: ORA16 + NEXTOPCODE +Op0EM0mod4: +lbl0Emod4a: Absolute +lbl0Emod4b: ASL16 + NEXTOPCODE +Op0FM0mod4: +lbl0Fmod4a: AbsoluteLong +lbl0Fmod4b: ORA16 + NEXTOPCODE +Op10mod4: +lbl10mod4: Op10 + NEXTOPCODE +Op11M0mod4: +lbl11mod4a: DirectIndirectIndexed1 +lbl11mod4b: ORA16 + NEXTOPCODE +Op12M0mod4: +lbl12mod4a: DirectIndirect +lbl12mod4b: ORA16 + NEXTOPCODE +Op13M0mod4: +lbl13mod4a: StackasmRelativeIndirectIndexed1 +lbl13mod4b: ORA16 + NEXTOPCODE +Op14M0mod4: +lbl14mod4a: Direct +lbl14mod4b: TRB16 + NEXTOPCODE +Op15M0mod4: +lbl15mod4a: DirectIndexedX1 +lbl15mod4b: ORA16 + NEXTOPCODE +Op16M0mod4: +lbl16mod4a: DirectIndexedX1 +lbl16mod4b: ASL16 + NEXTOPCODE +Op17M0mod4: +lbl17mod4a: DirectIndirectIndexedLong1 +lbl17mod4b: ORA16 + NEXTOPCODE +Op18mod4: +lbl18mod4: Op18 + NEXTOPCODE +Op19M0mod4: +lbl19mod4a: AbsoluteIndexedY1 +lbl19mod4b: ORA16 + NEXTOPCODE +Op1AM0mod4: +lbl1Amod4a: A_INC16 + NEXTOPCODE +Op1Bmod4: +lbl1Bmod4: Op1BM0 + NEXTOPCODE +Op1CM0mod4: +lbl1Cmod4a: Absolute +lbl1Cmod4b: TRB16 + NEXTOPCODE +Op1DM0mod4: +lbl1Dmod4a: AbsoluteIndexedX1 +lbl1Dmod4b: ORA16 + NEXTOPCODE +Op1EM0mod4: +lbl1Emod4a: AbsoluteIndexedX1 +lbl1Emod4b: ASL16 + NEXTOPCODE +Op1FM0mod4: +lbl1Fmod4a: AbsoluteLongIndexedX1 +lbl1Fmod4b: ORA16 + NEXTOPCODE +Op20mod4: +lbl20mod4: Op20 + NEXTOPCODE +Op21M0mod4: +lbl21mod4a: DirectIndexedIndirect1 +lbl21mod4b: AND16 + NEXTOPCODE +Op22mod4: +lbl22mod4: Op22 + NEXTOPCODE +Op23M0mod4: +lbl23mod4a: StackasmRelative +lbl23mod4b: AND16 + NEXTOPCODE +Op24M0mod4: +lbl24mod4a: Direct +lbl24mod4b: BIT16 + NEXTOPCODE +Op25M0mod4: +lbl25mod4a: Direct +lbl25mod4b: AND16 + NEXTOPCODE +Op26M0mod4: +lbl26mod4a: Direct +lbl26mod4b: ROL16 + NEXTOPCODE +Op27M0mod4: +lbl27mod4a: DirectIndirectLong +lbl27mod4b: AND16 + NEXTOPCODE +Op28mod4: +lbl28mod4: Op28X1M0 + NEXTOPCODE +.pool +Op29M0mod4: +lbl29mod4: Op29M0 + NEXTOPCODE +Op2AM0mod4: +lbl2Amod4a: A_ROL16 + NEXTOPCODE +Op2Bmod4: +lbl2Bmod4: Op2B + NEXTOPCODE +Op2CM0mod4: +lbl2Cmod4a: Absolute +lbl2Cmod4b: BIT16 + NEXTOPCODE +Op2DM0mod4: +lbl2Dmod4a: Absolute +lbl2Dmod4b: AND16 + NEXTOPCODE +Op2EM0mod4: +lbl2Emod4a: Absolute +lbl2Emod4b: ROL16 + NEXTOPCODE +Op2FM0mod4: +lbl2Fmod4a: AbsoluteLong +lbl2Fmod4b: AND16 + NEXTOPCODE +Op30mod4: +lbl30mod4: Op30 + NEXTOPCODE +Op31M0mod4: +lbl31mod4a: DirectIndirectIndexed1 +lbl31mod4b: AND16 + NEXTOPCODE +Op32M0mod4: +lbl32mod4a: DirectIndirect +lbl32mod4b: AND16 + NEXTOPCODE +Op33M0mod4: +lbl33mod4a: StackasmRelativeIndirectIndexed1 +lbl33mod4b: AND16 + NEXTOPCODE +Op34M0mod4: +lbl34mod4a: DirectIndexedX1 +lbl34mod4b: BIT16 + NEXTOPCODE +Op35M0mod4: +lbl35mod4a: DirectIndexedX1 +lbl35mod4b: AND16 + NEXTOPCODE +Op36M0mod4: +lbl36mod4a: DirectIndexedX1 +lbl36mod4b: ROL16 + NEXTOPCODE +Op37M0mod4: +lbl37mod4a: DirectIndirectIndexedLong1 +lbl37mod4b: AND16 + NEXTOPCODE +Op38mod4: +lbl38mod4: Op38 + NEXTOPCODE +Op39M0mod4: +lbl39mod4a: AbsoluteIndexedY1 +lbl39mod4b: AND16 + NEXTOPCODE +Op3AM0mod4: +lbl3Amod4a: A_DEC16 + NEXTOPCODE +Op3Bmod4: +lbl3Bmod4: Op3BM0 + NEXTOPCODE +Op3CM0mod4: +lbl3Cmod4a: AbsoluteIndexedX1 +lbl3Cmod4b: BIT16 + NEXTOPCODE +Op3DM0mod4: +lbl3Dmod4a: AbsoluteIndexedX1 +lbl3Dmod4b: AND16 + NEXTOPCODE +Op3EM0mod4: +lbl3Emod4a: AbsoluteIndexedX1 +lbl3Emod4b: ROL16 + NEXTOPCODE +Op3FM0mod4: +lbl3Fmod4a: AbsoluteLongIndexedX1 +lbl3Fmod4b: AND16 + NEXTOPCODE +Op40mod4: +lbl40mod4: Op40X1M0 + NEXTOPCODE +.pool +Op41M0mod4: +lbl41mod4a: DirectIndexedIndirect1 +lbl41mod4b: EOR16 + NEXTOPCODE +Op42mod4: +lbl42mod4: Op42 + NEXTOPCODE +Op43M0mod4: +lbl43mod4a: StackasmRelative +lbl43mod4b: EOR16 + NEXTOPCODE +Op44X1mod4: +lbl44mod4: Op44X1M0 + NEXTOPCODE +Op45M0mod4: +lbl45mod4a: Direct +lbl45mod4b: EOR16 + NEXTOPCODE +Op46M0mod4: +lbl46mod4a: Direct +lbl46mod4b: LSR16 + NEXTOPCODE +Op47M0mod4: +lbl47mod4a: DirectIndirectLong +lbl47mod4b: EOR16 + NEXTOPCODE +Op48M0mod4: +lbl48mod4: Op48M0 + NEXTOPCODE +Op49M0mod4: +lbl49mod4: Op49M0 + NEXTOPCODE +Op4AM0mod4: +lbl4Amod4a: A_LSR16 + NEXTOPCODE +Op4Bmod4: +lbl4Bmod4: Op4B + NEXTOPCODE +Op4Cmod4: +lbl4Cmod4: Op4C + NEXTOPCODE +Op4DM0mod4: +lbl4Dmod4a: Absolute +lbl4Dmod4b: EOR16 + NEXTOPCODE +Op4EM0mod4: +lbl4Emod4a: Absolute +lbl4Emod4b: LSR16 + NEXTOPCODE +Op4FM0mod4: +lbl4Fmod4a: AbsoluteLong +lbl4Fmod4b: EOR16 + NEXTOPCODE +Op50mod4: +lbl50mod4: Op50 + NEXTOPCODE +Op51M0mod4: +lbl51mod4a: DirectIndirectIndexed1 +lbl51mod4b: EOR16 + NEXTOPCODE +Op52M0mod4: +lbl52mod4a: DirectIndirect +lbl52mod4b: EOR16 + NEXTOPCODE +Op53M0mod4: +lbl53mod4a: StackasmRelativeIndirectIndexed1 +lbl53mod4b: EOR16 + NEXTOPCODE + +Op54X1mod4: +lbl54mod4: Op54X1M0 + NEXTOPCODE +Op55M0mod4: +lbl55mod4a: DirectIndexedX1 +lbl55mod4b: EOR16 + NEXTOPCODE +Op56M0mod4: +lbl56mod4a: DirectIndexedX1 +lbl56mod4b: LSR16 + NEXTOPCODE +Op57M0mod4: +lbl57mod4a: DirectIndirectIndexedLong1 +lbl57mod4b: EOR16 + NEXTOPCODE +Op58mod4: +lbl58mod4: Op58 + NEXTOPCODE +Op59M0mod4: +lbl59mod4a: AbsoluteIndexedY1 +lbl59mod4b: EOR16 + NEXTOPCODE +Op5AX1mod4: +lbl5Amod4: Op5AX1 + NEXTOPCODE +Op5Bmod4: +lbl5Bmod4: Op5BM0 + NEXTOPCODE +Op5Cmod4: +lbl5Cmod4: Op5C + NEXTOPCODE +Op5DM0mod4: +lbl5Dmod4a: AbsoluteIndexedX1 +lbl5Dmod4b: EOR16 + NEXTOPCODE +Op5EM0mod4: +lbl5Emod4a: AbsoluteIndexedX1 +lbl5Emod4b: LSR16 + NEXTOPCODE +Op5FM0mod4: +lbl5Fmod4a: AbsoluteLongIndexedX1 +lbl5Fmod4b: EOR16 + NEXTOPCODE +Op60mod4: +lbl60mod4: Op60 + NEXTOPCODE +Op61M0mod4: +lbl61mod4a: DirectIndexedIndirect1 +lbl61mod4b: ADC16 + NEXTOPCODE +Op62mod4: +lbl62mod4: Op62 + NEXTOPCODE +Op63M0mod4: +lbl63mod4a: StackasmRelative +lbl63mod4b: ADC16 + NEXTOPCODE +.pool +Op64M0mod4: +lbl64mod4a: Direct +lbl64mod4b: STZ16 + NEXTOPCODE +Op65M0mod4: +lbl65mod4a: Direct +lbl65mod4b: ADC16 + NEXTOPCODE +.pool +Op66M0mod4: +lbl66mod4a: Direct +lbl66mod4b: ROR16 + NEXTOPCODE +Op67M0mod4: +lbl67mod4a: DirectIndirectLong +lbl67mod4b: ADC16 + NEXTOPCODE +.pool +Op68M0mod4: +lbl68mod4: Op68M0 + NEXTOPCODE +Op69M0mod4: +lbl69mod4a: Immediate16 +lbl69mod4b: ADC16 + NEXTOPCODE +.pool +Op6AM0mod4: +lbl6Amod4a: A_ROR16 + NEXTOPCODE +Op6Bmod4: +lbl6Bmod4: Op6B + NEXTOPCODE +Op6Cmod4: +lbl6Cmod4: Op6C + NEXTOPCODE +Op6DM0mod4: +lbl6Dmod4a: Absolute +lbl6Dmod4b: ADC16 + NEXTOPCODE +Op6EM0mod4: +lbl6Emod4a: Absolute +lbl6Emod4b: ROR16 + NEXTOPCODE +Op6FM0mod4: +lbl6Fmod4a: AbsoluteLong +lbl6Fmod4b: ADC16 + NEXTOPCODE +Op70mod4: +lbl70mod4: Op70 + NEXTOPCODE +Op71M0mod4: +lbl71mod4a: DirectIndirectIndexed1 +lbl71mod4b: ADC16 + NEXTOPCODE +Op72M0mod4: +lbl72mod4a: DirectIndirect +lbl72mod4b: ADC16 + NEXTOPCODE +Op73M0mod4: +lbl73mod4a: StackasmRelativeIndirectIndexed1 +lbl73mod4b: ADC16 + NEXTOPCODE +.pool +Op74M0mod4: +lbl74mod4a: DirectIndexedX1 +lbl74mod4b: STZ16 + NEXTOPCODE +Op75M0mod4: +lbl75mod4a: DirectIndexedX1 +lbl75mod4b: ADC16 + NEXTOPCODE +.pool +Op76M0mod4: +lbl76mod4a: DirectIndexedX1 +lbl76mod4b: ROR16 + NEXTOPCODE +Op77M0mod4: +lbl77mod4a: DirectIndirectIndexedLong1 +lbl77mod4b: ADC16 + NEXTOPCODE +Op78mod4: +lbl78mod4: Op78 + NEXTOPCODE +Op79M0mod4: +lbl79mod4a: AbsoluteIndexedY1 +lbl79mod4b: ADC16 + NEXTOPCODE +Op7AX1mod4: +lbl7Amod4: Op7AX1 + NEXTOPCODE +Op7Bmod4: +lbl7Bmod4: Op7BM0 + NEXTOPCODE +Op7Cmod4: +lbl7Cmod4: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE +Op7DM0mod4: +lbl7Dmod4a: AbsoluteIndexedX1 +lbl7Dmod4b: ADC16 + NEXTOPCODE +Op7EM0mod4: +lbl7Emod4a: AbsoluteIndexedX1 +lbl7Emod4b: ROR16 + NEXTOPCODE +Op7FM0mod4: +lbl7Fmod4a: AbsoluteLongIndexedX1 +lbl7Fmod4b: ADC16 + NEXTOPCODE +.pool +Op80mod4: +lbl80mod4: Op80 + NEXTOPCODE +Op81M0mod4: +lbl81mod4a: DirectIndexedIndirect1 +lbl81mod4b: Op81M0 + NEXTOPCODE +Op82mod4: +lbl82mod4: Op82 + NEXTOPCODE +Op83M0mod4: +lbl83mod4a: StackasmRelative +lbl83mod4b: STA16 + NEXTOPCODE +Op84X1mod4: +lbl84mod4a: Direct +lbl84mod4b: STY8 + NEXTOPCODE +Op85M0mod4: +lbl85mod4a: Direct +lbl85mod4b: STA16 + NEXTOPCODE +Op86X1mod4: +lbl86mod4a: Direct +lbl86mod4b: STX8 + NEXTOPCODE +Op87M0mod4: +lbl87mod4a: DirectIndirectLong +lbl87mod4b: STA16 + NEXTOPCODE +Op88X1mod4: +lbl88mod4: Op88X1 + NEXTOPCODE +Op89M0mod4: +lbl89mod4: Op89M0 + NEXTOPCODE +Op8AM0mod4: +lbl8Amod4: Op8AM0X1 + NEXTOPCODE +Op8Bmod4: +lbl8Bmod4: Op8B + NEXTOPCODE +Op8CX1mod4: +lbl8Cmod4a: Absolute +lbl8Cmod4b: STY8 + NEXTOPCODE +Op8DM0mod4: +lbl8Dmod4a: Absolute +lbl8Dmod4b: STA16 + NEXTOPCODE +Op8EX1mod4: +lbl8Emod4a: Absolute +lbl8Emod4b: STX8 + NEXTOPCODE +Op8FM0mod4: +lbl8Fmod4a: AbsoluteLong +lbl8Fmod4b: STA16 + NEXTOPCODE +Op90mod4: +lbl90mod4: Op90 + NEXTOPCODE +Op91M0mod4: +lbl91mod4a: DirectIndirectIndexed1 +lbl91mod4b: STA16 + NEXTOPCODE +Op92M0mod4: +lbl92mod4a: DirectIndirect +lbl92mod4b: STA16 + NEXTOPCODE +Op93M0mod4: +lbl93mod4a: StackasmRelativeIndirectIndexed1 +lbl93mod4b: STA16 + NEXTOPCODE +Op94X1mod4: +lbl94mod4a: DirectIndexedX1 +lbl94mod4b: STY8 + NEXTOPCODE +Op95M0mod4: +lbl95mod4a: DirectIndexedX1 +lbl95mod4b: STA16 + NEXTOPCODE +Op96X1mod4: +lbl96mod4a: DirectIndexedY1 +lbl96mod4b: STX8 + NEXTOPCODE +Op97M0mod4: +lbl97mod4a: DirectIndirectIndexedLong1 +lbl97mod4b: STA16 + NEXTOPCODE +Op98M0mod4: +lbl98mod4: Op98M0X1 + NEXTOPCODE +Op99M0mod4: +lbl99mod4a: AbsoluteIndexedY1 +lbl99mod4b: STA16 + NEXTOPCODE +Op9Amod4: +lbl9Amod4: Op9AX1 + NEXTOPCODE +Op9BX1mod4: +lbl9Bmod4: Op9BX1 + NEXTOPCODE +Op9CM0mod4: +lbl9Cmod4a: Absolute +lbl9Cmod4b: STZ16 + NEXTOPCODE +Op9DM0mod4: +lbl9Dmod4a: AbsoluteIndexedX1 +lbl9Dmod4b: STA16 + NEXTOPCODE +Op9EM0mod4: +lbl9Emod4: AbsoluteIndexedX1 + STZ16 + NEXTOPCODE +Op9FM0mod4: +lbl9Fmod4a: AbsoluteLongIndexedX1 +lbl9Fmod4b: STA16 + NEXTOPCODE +OpA0X1mod4: +lblA0mod4: OpA0X1 + NEXTOPCODE +OpA1M0mod4: +lblA1mod4a: DirectIndexedIndirect1 +lblA1mod4b: LDA16 + NEXTOPCODE +OpA2X1mod4: +lblA2mod4: OpA2X1 + NEXTOPCODE +OpA3M0mod4: +lblA3mod4a: StackasmRelative +lblA3mod4b: LDA16 + NEXTOPCODE +OpA4X1mod4: +lblA4mod4a: Direct +lblA4mod4b: LDY8 + NEXTOPCODE +OpA5M0mod4: +lblA5mod4a: Direct +lblA5mod4b: LDA16 + NEXTOPCODE +OpA6X1mod4: +lblA6mod4a: Direct +lblA6mod4b: LDX8 + NEXTOPCODE +OpA7M0mod4: +lblA7mod4a: DirectIndirectLong +lblA7mod4b: LDA16 + NEXTOPCODE +OpA8X1mod4: +lblA8mod4: OpA8X1M0 + NEXTOPCODE +OpA9M0mod4: +lblA9mod4: OpA9M0 + NEXTOPCODE +OpAAX1mod4: +lblAAmod4: OpAAX1M0 + NEXTOPCODE +OpABmod4: +lblABmod4: OpAB + NEXTOPCODE +OpACX1mod4: +lblACmod4a: Absolute +lblACmod4b: LDY8 + NEXTOPCODE +OpADM0mod4: +lblADmod4a: Absolute +lblADmod4b: LDA16 + NEXTOPCODE +OpAEX1mod4: +lblAEmod4a: Absolute +lblAEmod4b: LDX8 + NEXTOPCODE +OpAFM0mod4: +lblAFmod4a: AbsoluteLong +lblAFmod4b: LDA16 + NEXTOPCODE +OpB0mod4: +lblB0mod4: OpB0 + NEXTOPCODE +OpB1M0mod4: +lblB1mod4a: DirectIndirectIndexed1 +lblB1mod4b: LDA16 + NEXTOPCODE +OpB2M0mod4: +lblB2mod4a: DirectIndirect +lblB2mod4b: LDA16 + NEXTOPCODE +OpB3M0mod4: +lblB3mod4a: StackasmRelativeIndirectIndexed1 +lblB3mod4b: LDA16 + NEXTOPCODE +OpB4X1mod4: +lblB4mod4a: DirectIndexedX1 +lblB4mod4b: LDY8 + NEXTOPCODE +OpB5M0mod4: +lblB5mod4a: DirectIndexedX1 +lblB5mod4b: LDA16 + NEXTOPCODE +OpB6X1mod4: +lblB6mod4a: DirectIndexedY1 +lblB6mod4b: LDX8 + NEXTOPCODE +OpB7M0mod4: +lblB7mod4a: DirectIndirectIndexedLong1 +lblB7mod4b: LDA16 + NEXTOPCODE +OpB8mod4: +lblB8mod4: OpB8 + NEXTOPCODE +OpB9M0mod4: +lblB9mod4a: AbsoluteIndexedY1 +lblB9mod4b: LDA16 + NEXTOPCODE +OpBAX1mod4: +lblBAmod4: OpBAX1 + NEXTOPCODE +OpBBX1mod4: +lblBBmod4: OpBBX1 + NEXTOPCODE +OpBCX1mod4: +lblBCmod4a: AbsoluteIndexedX1 +lblBCmod4b: LDY8 + NEXTOPCODE +OpBDM0mod4: +lblBDmod4a: AbsoluteIndexedX1 +lblBDmod4b: LDA16 + NEXTOPCODE +OpBEX1mod4: +lblBEmod4a: AbsoluteIndexedY1 +lblBEmod4b: LDX8 + NEXTOPCODE +OpBFM0mod4: +lblBFmod4a: AbsoluteLongIndexedX1 +lblBFmod4b: LDA16 + NEXTOPCODE +OpC0X1mod4: +lblC0mod4: OpC0X1 + NEXTOPCODE +OpC1M0mod4: +lblC1mod4a: DirectIndexedIndirect1 +lblC1mod4b: CMP16 + NEXTOPCODE +OpC2mod4: +lblC2mod4: OpC2 + NEXTOPCODE +.pool +OpC3M0mod4: +lblC3mod4a: StackasmRelative +lblC3mod4b: CMP16 + NEXTOPCODE +OpC4X1mod4: +lblC4mod4a: Direct +lblC4mod4b: CMY8 + NEXTOPCODE +OpC5M0mod4: +lblC5mod4a: Direct +lblC5mod4b: CMP16 + NEXTOPCODE +OpC6M0mod4: +lblC6mod4a: Direct +lblC6mod4b: DEC16 + NEXTOPCODE +OpC7M0mod4: +lblC7mod4a: DirectIndirectLong +lblC7mod4b: CMP16 + NEXTOPCODE +OpC8X1mod4: +lblC8mod4: OpC8X1 + NEXTOPCODE +OpC9M0mod4: +lblC9mod4: OpC9M0 + NEXTOPCODE +OpCAX1mod4: +lblCAmod4: OpCAX1 + NEXTOPCODE +OpCBmod4: +lblCBmod4: OpCB + NEXTOPCODE +OpCCX1mod4: +lblCCmod4a: Absolute +lblCCmod4b: CMY8 + NEXTOPCODE +OpCDM0mod4: +lblCDmod4a: Absolute +lblCDmod4b: CMP16 + NEXTOPCODE +OpCEM0mod4: +lblCEmod4a: Absolute +lblCEmod4b: DEC16 + NEXTOPCODE +OpCFM0mod4: +lblCFmod4a: AbsoluteLong +lblCFmod4b: CMP16 + NEXTOPCODE +OpD0mod4: +lblD0mod4: OpD0 + NEXTOPCODE +OpD1M0mod4: +lblD1mod4a: DirectIndirectIndexed1 +lblD1mod4b: CMP16 + + NEXTOPCODE +OpD2M0mod4: +lblD2mod4a: DirectIndirect +lblD2mod4b: CMP16 + NEXTOPCODE +OpD3M0mod4: +lblD3mod4a: StackasmRelativeIndirectIndexed1 +lblD3mod4b: CMP16 + NEXTOPCODE +OpD4mod4: +lblD4mod4: OpD4 + NEXTOPCODE +OpD5M0mod4: +lblD5mod4a: DirectIndexedX1 +lblD5mod4b: CMP16 + NEXTOPCODE +OpD6M0mod4: +lblD6mod4a: DirectIndexedX1 +lblD6mod4b: DEC16 + NEXTOPCODE +OpD7M0mod4: +lblD7mod4a: DirectIndirectIndexedLong1 +lblD7mod4b: CMP16 + NEXTOPCODE +OpD8mod4: +lblD8mod4: OpD8 + NEXTOPCODE +OpD9M0mod4: +lblD9mod4a: AbsoluteIndexedY1 +lblD9mod4b: CMP16 + NEXTOPCODE +OpDAX1mod4: +lblDAmod4: OpDAX1 + NEXTOPCODE +OpDBmod4: +lblDBmod4: OpDB + NEXTOPCODE +OpDCmod4: +lblDCmod4: OpDC + NEXTOPCODE +OpDDM0mod4: +lblDDmod4a: AbsoluteIndexedX1 +lblDDmod4b: CMP16 + NEXTOPCODE +OpDEM0mod4: +lblDEmod4a: AbsoluteIndexedX1 +lblDEmod4b: DEC16 + NEXTOPCODE +OpDFM0mod4: +lblDFmod4a: AbsoluteLongIndexedX1 +lblDFmod4b: CMP16 + NEXTOPCODE +OpE0X1mod4: +lblE0mod4: OpE0X1 + NEXTOPCODE +OpE1M0mod4: +lblE1mod4a: DirectIndexedIndirect1 +lblE1mod4b: SBC16 + NEXTOPCODE +OpE2mod4: +lblE2mod4: OpE2 + NEXTOPCODE +.pool +OpE3M0mod4: +lblE3mod4a: StackasmRelative +lblE3mod4b: SBC16 + NEXTOPCODE +OpE4X1mod4: +lblE4mod4a: Direct +lblE4mod4b: CMX8 + NEXTOPCODE +OpE5M0mod4: +lblE5mod4a: Direct +lblE5mod4b: SBC16 + NEXTOPCODE +OpE6M0mod4: +lblE6mod4a: Direct +lblE6mod4b: INC16 + NEXTOPCODE +OpE7M0mod4: +lblE7mod4a: DirectIndirectLong +lblE7mod4b: SBC16 + NEXTOPCODE +OpE8X1mod4: +lblE8mod4: OpE8X1 + NEXTOPCODE +OpE9M0mod4: +lblE9mod4a: Immediate16 +lblE9mod4b: SBC16 + NEXTOPCODE +OpEAmod4: +lblEAmod4: OpEA + NEXTOPCODE +OpEBmod4: +lblEBmod4: OpEBM0 + NEXTOPCODE +OpECX1mod4: +lblECmod4a: Absolute +lblECmod4b: CMX8 + NEXTOPCODE +OpEDM0mod4: +lblEDmod4a: Absolute +lblEDmod4b: SBC16 + NEXTOPCODE +OpEEM0mod4: +lblEEmod4a: Absolute +lblEEmod4b: INC16 + NEXTOPCODE +OpEFM0mod4: +lblEFmod4a: AbsoluteLong +lblEFmod4b: SBC16 + NEXTOPCODE +OpF0mod4: +lblF0mod4: OpF0 + NEXTOPCODE +OpF1M0mod4: +lblF1mod4a: DirectIndirectIndexed1 +lblF1mod4b: SBC16 + NEXTOPCODE +OpF2M0mod4: +lblF2mod4a: DirectIndirect +lblF2mod4b: SBC16 + NEXTOPCODE +OpF3M0mod4: +lblF3mod4a: StackasmRelativeIndirectIndexed1 +lblF3mod4b: SBC16 + NEXTOPCODE +OpF4mod4: +lblF4mod4: OpF4 + NEXTOPCODE +OpF5M0mod4: +lblF5mod4a: DirectIndexedX1 +lblF5mod4b: SBC16 + NEXTOPCODE +OpF6M0mod4: +lblF6mod4a: DirectIndexedX1 +lblF6mod4b: INC16 + NEXTOPCODE +OpF7M0mod4: +lblF7mod4a: DirectIndirectIndexedLong1 +lblF7mod4b: SBC16 + NEXTOPCODE +OpF8mod4: +lblF8mod4: OpF8 + NEXTOPCODE +OpF9M0mod4: +lblF9mod4a: AbsoluteIndexedY1 +lblF9mod4b: SBC16 + NEXTOPCODE +OpFAX1mod4: +lblFAmod4: OpFAX1 + NEXTOPCODE +OpFBmod4: +lblFBmod4: OpFB + NEXTOPCODE +OpFCmod4: +lblFCmod4: OpFCX1 + NEXTOPCODE +OpFDM0mod4: +lblFDmod4a: AbsoluteIndexedX1 +lblFDmod4b: SBC16 + NEXTOPCODE +OpFEM0mod4: +lblFEmod4a: AbsoluteIndexedX1 +lblFEmod4b: INC16 + NEXTOPCODE +OpFFM0mod4: +lblFFmod4a: AbsoluteLongIndexedX1 +lblFFmod4b: SBC16 + NEXTOPCODE + + + .pool + diff --git a/src/os9x_65c816_spcasm.s.last b/src/os9x_65c816_spcasm.s.last new file mode 100644 index 0000000..3eebba9 --- /dev/null +++ b/src/os9x_65c816_spcasm.s.last @@ -0,0 +1,4927 @@ + .DATA +/**************************************************************** +****************************************************************/ + .align 4 + .include "os9x_65c816_common.s" + + +.macro asmAPU_EXECUTE + LDR R0,[reg_cpu_var,#APUExecuting_ofs] + CMP R0,#1 @ spc700 enabled, hack mode off + BNE 43210f + LDR R0,[reg_cpu_var,#APU_Cycles] + SUBS R0,reg_cycles,R0 + BMI 43210f + PREPARE_C_CALL_LIGHTR12 + BL spc700_execute + RESTORE_C_CALL_LIGHTR12 + SUB R0,reg_cycles,R0 @ sub cycles left + STR R0,[reg_cpu_var,#APU_Cycles] +43210: +.endm + +.macro asmAPU_EXECUTE2 + LDR R0,[reg_cpu_var,#APUExecuting_ofs] + CMP R0,#1 @ spc700 enabled, hack mode off + BNE 43211f + SUBS R0,reg_cycles,R0 @ reg_cycles == NextEvent + BLE 43211f + PREPARE_C_CALL_LIGHTR12 + BL spc700_execute + RESTORE_C_CALL_LIGHTR12 + SUB R0,reg_cycles,R0 @ sub cycles left + STR R0,[reg_cpu_var,#APU_Cycles] +43211: +.endm + + .include "os9x_65c816_opcodes.s" + + +/* + + +CLI_OPE_REC_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @treasuryDate, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @accountingDate, 103) + +CLI_OPE_Nos_Ope_Layer0 + n.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + n.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +CLI_OPE_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +Ecrans: +------ + + +[GNV] : utilisation de la lard (laccdate) pour afficher les openings. + +nécessité d'avoir des valeurs dans l'opening pour date tréso=date compta=laccdate + +[Accounting rec] : si laccdate pas bonne (pas = BD-1) -> message warning et pas de donnée +sinon : + +données nécessaires : opening date tréso=date compta=laccdate=BD-1 + +données nécessaires : opening date tréso=date compta=laccdate-1 + +données nécessaires : opening date tréso=laccdate-1 et date compta=laccdate + */ + + + +/**************************************************************** + GLOBAL +****************************************************************/ + @.globl test_opcode + .globl asmMainLoop_spcAsm + + +@ void asmMainLoop(asm_cpu_var_t *asmcpuPtr); +asmMainLoop_spcAsm: + doMainLoop +.pool + +/* +@ void test_opcode(struct asm_cpu_var *asm_var); +test_opcode: + doTestOpcode +.pool +*/ +/***************************************************************** + ASM CODE +*****************************************************************/ + + +jumptable1: .long Op00mod1 + .long Op01M1mod1 + .long Op02mod1 + .long Op03M1mod1 + .long Op04M1mod1 + .long Op05M1mod1 + .long Op06M1mod1 + .long Op07M1mod1 + .long Op08mod1 + .long Op09M1mod1 + .long Op0AM1mod1 + .long Op0Bmod1 + .long Op0CM1mod1 + .long Op0DM1mod1 + .long Op0EM1mod1 + .long Op0FM1mod1 + .long Op10mod1 + .long Op11M1mod1 + .long Op12M1mod1 + .long Op13M1mod1 + .long Op14M1mod1 + .long Op15M1mod1 + .long Op16M1mod1 + .long Op17M1mod1 + .long Op18mod1 + .long Op19M1mod1 + .long Op1AM1mod1 + .long Op1Bmod1 + .long Op1CM1mod1 + .long Op1DM1mod1 + .long Op1EM1mod1 + .long Op1FM1mod1 + .long Op20mod1 + .long Op21M1mod1 + .long Op22mod1 + .long Op23M1mod1 + .long Op24M1mod1 + .long Op25M1mod1 + .long Op26M1mod1 + .long Op27M1mod1 + .long Op28mod1 + .long Op29M1mod1 + .long Op2AM1mod1 + .long Op2Bmod1 + .long Op2CM1mod1 + .long Op2DM1mod1 + .long Op2EM1mod1 + .long Op2FM1mod1 + .long Op30mod1 + .long Op31M1mod1 + .long Op32M1mod1 + .long Op33M1mod1 + .long Op34M1mod1 + .long Op35M1mod1 + .long Op36M1mod1 + .long Op37M1mod1 + .long Op38mod1 + .long Op39M1mod1 + .long Op3AM1mod1 + .long Op3Bmod1 + .long Op3CM1mod1 + .long Op3DM1mod1 + .long Op3EM1mod1 + .long Op3FM1mod1 + .long Op40mod1 + .long Op41M1mod1 + .long Op42mod1 + .long Op43M1mod1 + .long Op44X1mod1 + .long Op45M1mod1 + .long Op46M1mod1 + .long Op47M1mod1 + .long Op48M1mod1 + .long Op49M1mod1 + .long Op4AM1mod1 + .long Op4Bmod1 + .long Op4Cmod1 + .long Op4DM1mod1 + .long Op4EM1mod1 + .long Op4FM1mod1 + .long Op50mod1 + .long Op51M1mod1 + .long Op52M1mod1 + .long Op53M1mod1 + .long Op54X1mod1 + .long Op55M1mod1 + .long Op56M1mod1 + .long Op57M1mod1 + .long Op58mod1 + .long Op59M1mod1 + .long Op5AX1mod1 + .long Op5Bmod1 + .long Op5Cmod1 + .long Op5DM1mod1 + .long Op5EM1mod1 + .long Op5FM1mod1 + .long Op60mod1 + .long Op61M1mod1 + .long Op62mod1 + .long Op63M1mod1 + .long Op64M1mod1 + .long Op65M1mod1 + .long Op66M1mod1 + .long Op67M1mod1 + .long Op68M1mod1 + .long Op69M1mod1 + .long Op6AM1mod1 + .long Op6Bmod1 + .long Op6Cmod1 + .long Op6DM1mod1 + .long Op6EM1mod1 + .long Op6FM1mod1 + .long Op70mod1 + .long Op71M1mod1 + .long Op72M1mod1 + .long Op73M1mod1 + .long Op74M1mod1 + .long Op75M1mod1 + .long Op76M1mod1 + .long Op77M1mod1 + .long Op78mod1 + .long Op79M1mod1 + .long Op7AX1mod1 + .long Op7Bmod1 + .long Op7Cmod1 + .long Op7DM1mod1 + .long Op7EM1mod1 + .long Op7FM1mod1 + .long Op80mod1 + .long Op81M1mod1 + .long Op82mod1 + .long Op83M1mod1 + .long Op84X1mod1 + .long Op85M1mod1 + .long Op86X1mod1 + .long Op87M1mod1 + .long Op88X1mod1 + .long Op89M1mod1 + .long Op8AM1mod1 + .long Op8Bmod1 + .long Op8CX1mod1 + .long Op8DM1mod1 + .long Op8EX1mod1 + .long Op8FM1mod1 + .long Op90mod1 + .long Op91M1mod1 + .long Op92M1mod1 + .long Op93M1mod1 + .long Op94X1mod1 + .long Op95M1mod1 + .long Op96X1mod1 + .long Op97M1mod1 + .long Op98M1mod1 + .long Op99M1mod1 + .long Op9Amod1 + .long Op9BX1mod1 + + .long Op9CM1mod1 + .long Op9DM1mod1 + .long Op9EM1mod1 + .long Op9FM1mod1 + .long OpA0X1mod1 + .long OpA1M1mod1 + .long OpA2X1mod1 + .long OpA3M1mod1 + .long OpA4X1mod1 + .long OpA5M1mod1 + .long OpA6X1mod1 + .long OpA7M1mod1 + .long OpA8X1mod1 + .long OpA9M1mod1 + .long OpAAX1mod1 + .long OpABmod1 + .long OpACX1mod1 + .long OpADM1mod1 + .long OpAEX1mod1 + .long OpAFM1mod1 + .long OpB0mod1 + .long OpB1M1mod1 + .long OpB2M1mod1 + .long OpB3M1mod1 + .long OpB4X1mod1 + .long OpB5M1mod1 + .long OpB6X1mod1 + .long OpB7M1mod1 + .long OpB8mod1 + .long OpB9M1mod1 + .long OpBAX1mod1 + .long OpBBX1mod1 + .long OpBCX1mod1 + .long OpBDM1mod1 + .long OpBEX1mod1 + .long OpBFM1mod1 + .long OpC0X1mod1 + .long OpC1M1mod1 + .long OpC2mod1 + .long OpC3M1mod1 + .long OpC4X1mod1 + .long OpC5M1mod1 + .long OpC6M1mod1 + .long OpC7M1mod1 + .long OpC8X1mod1 + .long OpC9M1mod1 + .long OpCAX1mod1 + .long OpCBmod1 + .long OpCCX1mod1 + .long OpCDM1mod1 + .long OpCEM1mod1 + .long OpCFM1mod1 + .long OpD0mod1 + .long OpD1M1mod1 + .long OpD2M1mod1 + .long OpD3M1mod1 + .long OpD4mod1 + .long OpD5M1mod1 + .long OpD6M1mod1 + .long OpD7M1mod1 + .long OpD8mod1 + .long OpD9M1mod1 + .long OpDAX1mod1 + .long OpDBmod1 + .long OpDCmod1 + .long OpDDM1mod1 + .long OpDEM1mod1 + .long OpDFM1mod1 + .long OpE0X1mod1 + .long OpE1M1mod1 + .long OpE2mod1 + .long OpE3M1mod1 + .long OpE4X1mod1 + .long OpE5M1mod1 + .long OpE6M1mod1 + .long OpE7M1mod1 + .long OpE8X1mod1 + .long OpE9M1mod1 + .long OpEAmod1 + .long OpEBmod1 + .long OpECX1mod1 + .long OpEDM1mod1 + .long OpEEM1mod1 + .long OpEFM1mod1 + .long OpF0mod1 + .long OpF1M1mod1 + .long OpF2M1mod1 + .long OpF3M1mod1 + .long OpF4mod1 + .long OpF5M1mod1 + .long OpF6M1mod1 + .long OpF7M1mod1 + .long OpF8mod1 + .long OpF9M1mod1 + .long OpFAX1mod1 + .long OpFBmod1 + .long OpFCmod1 + .long OpFDM1mod1 + .long OpFEM1mod1 + .long OpFFM1mod1 + +Op00mod1: +lbl00mod1: Op00 + NEXTOPCODE +Op01M1mod1: +lbl01mod1a: DirectIndexedIndirect1 +lbl01mod1b: ORA8 + NEXTOPCODE +Op02mod1: +lbl02mod1: Op02 + NEXTOPCODE +Op03M1mod1: +lbl03mod1a: StackasmRelative +lbl03mod1b: ORA8 + NEXTOPCODE +Op04M1mod1: +lbl04mod1a: Direct +lbl04mod1b: TSB8 + NEXTOPCODE +Op05M1mod1: +lbl05mod1a: Direct +lbl05mod1b: ORA8 + NEXTOPCODE +Op06M1mod1: +lbl06mod1a: Direct +lbl06mod1b: ASL8 + NEXTOPCODE +Op07M1mod1: +lbl07mod1a: DirectIndirectLong +lbl07mod1b: ORA8 + NEXTOPCODE +Op08mod1: +lbl08mod1: Op08 + NEXTOPCODE +Op09M1mod1: +lbl09mod1: Op09M1 + NEXTOPCODE +Op0AM1mod1: +lbl0Amod1a: A_ASL8 + NEXTOPCODE +Op0Bmod1: +lbl0Bmod1: Op0B + NEXTOPCODE +Op0CM1mod1: +lbl0Cmod1a: Absolute +lbl0Cmod1b: TSB8 + NEXTOPCODE +Op0DM1mod1: +lbl0Dmod1a: Absolute +lbl0Dmod1b: ORA8 + NEXTOPCODE +Op0EM1mod1: +lbl0Emod1a: Absolute +lbl0Emod1b: ASL8 + NEXTOPCODE +Op0FM1mod1: +lbl0Fmod1a: AbsoluteLong +lbl0Fmod1b: ORA8 + NEXTOPCODE +Op10mod1: +lbl10mod1: Op10 + NEXTOPCODE +Op11M1mod1: +lbl11mod1a: DirectIndirectIndexed1 +lbl11mod1b: ORA8 + NEXTOPCODE +Op12M1mod1: +lbl12mod1a: DirectIndirect +lbl12mod1b: ORA8 + NEXTOPCODE +Op13M1mod1: + +lbl13mod1a: StackasmRelativeIndirectIndexed1 +lbl13mod1b: ORA8 + NEXTOPCODE +Op14M1mod1: +lbl14mod1a: Direct +lbl14mod1b: TRB8 + NEXTOPCODE +Op15M1mod1: +lbl15mod1a: DirectIndexedX1 +lbl15mod1b: ORA8 + NEXTOPCODE +Op16M1mod1: +lbl16mod1a: DirectIndexedX1 +lbl16mod1b: ASL8 + NEXTOPCODE +Op17M1mod1: +lbl17mod1a: DirectIndirectIndexedLong1 +lbl17mod1b: ORA8 + NEXTOPCODE +Op18mod1: +lbl18mod1: Op18 + NEXTOPCODE +Op19M1mod1: +lbl19mod1a: AbsoluteIndexedY1 +lbl19mod1b: ORA8 + NEXTOPCODE +Op1AM1mod1: +lbl1Amod1a: A_INC8 + NEXTOPCODE +Op1Bmod1: +lbl1Bmod1: Op1BM1 + NEXTOPCODE +Op1CM1mod1: +lbl1Cmod1a: Absolute +lbl1Cmod1b: TRB8 + NEXTOPCODE +Op1DM1mod1: +lbl1Dmod1a: AbsoluteIndexedX1 +lbl1Dmod1b: ORA8 + NEXTOPCODE +Op1EM1mod1: +lbl1Emod1a: AbsoluteIndexedX1 +lbl1Emod1b: ASL8 + NEXTOPCODE +Op1FM1mod1: +lbl1Fmod1a: AbsoluteLongIndexedX1 +lbl1Fmod1b: ORA8 + NEXTOPCODE +Op20mod1: +lbl20mod1: Op20 + NEXTOPCODE +Op21M1mod1: +lbl21mod1a: DirectIndexedIndirect1 +lbl21mod1b: AND8 + NEXTOPCODE +Op22mod1: +lbl22mod1: Op22 + NEXTOPCODE +Op23M1mod1: +lbl23mod1a: StackasmRelative +lbl23mod1b: AND8 + NEXTOPCODE +Op24M1mod1: +lbl24mod1a: Direct +lbl24mod1b: BIT8 + NEXTOPCODE +Op25M1mod1: +lbl25mod1a: Direct +lbl25mod1b: AND8 + NEXTOPCODE +Op26M1mod1: +lbl26mod1a: Direct +lbl26mod1b: ROL8 + NEXTOPCODE +Op27M1mod1: +lbl27mod1a: DirectIndirectLong +lbl27mod1b: AND8 + NEXTOPCODE +Op28mod1: +lbl28mod1: Op28X1M1 + NEXTOPCODE +.pool +Op29M1mod1: +lbl29mod1: Op29M1 + NEXTOPCODE +Op2AM1mod1: +lbl2Amod1a: A_ROL8 + NEXTOPCODE +Op2Bmod1: +lbl2Bmod1: Op2B + NEXTOPCODE +Op2CM1mod1: +lbl2Cmod1a: Absolute +lbl2Cmod1b: BIT8 + NEXTOPCODE +Op2DM1mod1: +lbl2Dmod1a: Absolute +lbl2Dmod1b: AND8 + NEXTOPCODE +Op2EM1mod1: +lbl2Emod1a: Absolute +lbl2Emod1b: ROL8 + NEXTOPCODE +Op2FM1mod1: +lbl2Fmod1a: AbsoluteLong +lbl2Fmod1b: AND8 + NEXTOPCODE +Op30mod1: +lbl30mod1: Op30 + NEXTOPCODE +Op31M1mod1: +lbl31mod1a: DirectIndirectIndexed1 +lbl31mod1b: AND8 + NEXTOPCODE +Op32M1mod1: +lbl32mod1a: DirectIndirect +lbl32mod1b: AND8 + NEXTOPCODE +Op33M1mod1: +lbl33mod1a: StackasmRelativeIndirectIndexed1 +lbl33mod1b: AND8 + NEXTOPCODE +Op34M1mod1: +lbl34mod1a: DirectIndexedX1 +lbl34mod1b: BIT8 + NEXTOPCODE +Op35M1mod1: +lbl35mod1a: DirectIndexedX1 +lbl35mod1b: AND8 + NEXTOPCODE +Op36M1mod1: +lbl36mod1a: DirectIndexedX1 +lbl36mod1b: ROL8 + NEXTOPCODE +Op37M1mod1: +lbl37mod1a: DirectIndirectIndexedLong1 +lbl37mod1b: AND8 + NEXTOPCODE +Op38mod1: +lbl38mod1: Op38 + NEXTOPCODE +Op39M1mod1: +lbl39mod1a: AbsoluteIndexedY1 +lbl39mod1b: AND8 + NEXTOPCODE +Op3AM1mod1: +lbl3Amod1a: A_DEC8 + NEXTOPCODE +Op3Bmod1: +lbl3Bmod1: Op3BM1 + NEXTOPCODE +Op3CM1mod1: +lbl3Cmod1a: AbsoluteIndexedX1 +lbl3Cmod1b: BIT8 + NEXTOPCODE +Op3DM1mod1: +lbl3Dmod1a: AbsoluteIndexedX1 +lbl3Dmod1b: AND8 + NEXTOPCODE +Op3EM1mod1: +lbl3Emod1a: AbsoluteIndexedX1 +lbl3Emod1b: ROL8 + NEXTOPCODE +Op3FM1mod1: +lbl3Fmod1a: AbsoluteLongIndexedX1 +lbl3Fmod1b: AND8 + NEXTOPCODE +Op40mod1: +lbl40mod1: Op40X1M1 + NEXTOPCODE +.pool +Op41M1mod1: +lbl41mod1a: DirectIndexedIndirect1 +lbl41mod1b: EOR8 + NEXTOPCODE +Op42mod1: +lbl42mod1: Op42 + NEXTOPCODE +Op43M1mod1: +lbl43mod1a: StackasmRelative +lbl43mod1b: EOR8 + NEXTOPCODE +Op44X1mod1: +lbl44mod1: Op44X1M1 + NEXTOPCODE +Op45M1mod1: +lbl45mod1a: Direct +lbl45mod1b: EOR8 + NEXTOPCODE +Op46M1mod1: +lbl46mod1a: Direct +lbl46mod1b: LSR8 + NEXTOPCODE +Op47M1mod1: +lbl47mod1a: DirectIndirectLong +lbl47mod1b: EOR8 + NEXTOPCODE +Op48M1mod1: +lbl48mod1: Op48M1 + NEXTOPCODE +Op49M1mod1: +lbl49mod1: Op49M1 + NEXTOPCODE +Op4AM1mod1: +lbl4Amod1a: A_LSR8 + NEXTOPCODE +Op4Bmod1: +lbl4Bmod1: Op4B + NEXTOPCODE +Op4Cmod1: +lbl4Cmod1: Op4C + NEXTOPCODE +Op4DM1mod1: +lbl4Dmod1a: Absolute +lbl4Dmod1b: EOR8 + NEXTOPCODE +Op4EM1mod1: +lbl4Emod1a: Absolute +lbl4Emod1b: LSR8 + NEXTOPCODE +Op4FM1mod1: +lbl4Fmod1a: AbsoluteLong +lbl4Fmod1b: EOR8 + NEXTOPCODE +Op50mod1: +lbl50mod1: Op50 + NEXTOPCODE +Op51M1mod1: +lbl51mod1a: DirectIndirectIndexed1 +lbl51mod1b: EOR8 + NEXTOPCODE +Op52M1mod1: +lbl52mod1a: DirectIndirect +lbl52mod1b: EOR8 + NEXTOPCODE +Op53M1mod1: +lbl53mod1a: StackasmRelativeIndirectIndexed1 +lbl53mod1b: EOR8 + NEXTOPCODE +Op54X1mod1: +lbl54mod1: Op54X1M1 + NEXTOPCODE +Op55M1mod1: +lbl55mod1a: DirectIndexedX1 +lbl55mod1b: EOR8 + NEXTOPCODE +Op56M1mod1: +lbl56mod1a: DirectIndexedX1 +lbl56mod1b: LSR8 + NEXTOPCODE +Op57M1mod1: +lbl57mod1a: DirectIndirectIndexedLong1 +lbl57mod1b: EOR8 + NEXTOPCODE +Op58mod1: +lbl58mod1: Op58 + NEXTOPCODE +Op59M1mod1: +lbl59mod1a: AbsoluteIndexedY1 +lbl59mod1b: EOR8 + NEXTOPCODE +Op5AX1mod1: +lbl5Amod1: Op5AX1 + NEXTOPCODE +Op5Bmod1: +lbl5Bmod1: Op5BM1 + NEXTOPCODE +Op5Cmod1: +lbl5Cmod1: Op5C + NEXTOPCODE +Op5DM1mod1: +lbl5Dmod1a: AbsoluteIndexedX1 +lbl5Dmod1b: EOR8 + NEXTOPCODE +Op5EM1mod1: +lbl5Emod1a: AbsoluteIndexedX1 +lbl5Emod1b: LSR8 + NEXTOPCODE +Op5FM1mod1: +lbl5Fmod1a: AbsoluteLongIndexedX1 +lbl5Fmod1b: EOR8 + NEXTOPCODE +Op60mod1: +lbl60mod1: Op60 + NEXTOPCODE +Op61M1mod1: +lbl61mod1a: DirectIndexedIndirect1 +lbl61mod1b: ADC8 + NEXTOPCODE +Op62mod1: +lbl62mod1: Op62 + NEXTOPCODE +Op63M1mod1: +lbl63mod1a: StackasmRelative +lbl63mod1b: ADC8 + NEXTOPCODE +Op64M1mod1: +lbl64mod1a: Direct +lbl64mod1b: STZ8 + NEXTOPCODE +Op65M1mod1: +lbl65mod1a: Direct +lbl65mod1b: ADC8 + NEXTOPCODE +Op66M1mod1: +lbl66mod1a: Direct +lbl66mod1b: ROR8 + NEXTOPCODE +Op67M1mod1: +lbl67mod1a: DirectIndirectLong +lbl67mod1b: ADC8 + + NEXTOPCODE + +Op68M1mod1: +lbl68mod1: Op68M1 + NEXTOPCODE +Op69M1mod1: +lbl69mod1a: Immediate8 +lbl69mod1b: ADC8 + NEXTOPCODE +Op6AM1mod1: +lbl6Amod1a: A_ROR8 + NEXTOPCODE +Op6Bmod1: +lbl6Bmod1: Op6B + NEXTOPCODE +Op6Cmod1: +lbl6Cmod1: Op6C + NEXTOPCODE +Op6DM1mod1: +lbl6Dmod1a: Absolute +lbl6Dmod1b: ADC8 + NEXTOPCODE +Op6EM1mod1: + + +lbl6Emod1a: Absolute +lbl6Emod1b: ROR8 + NEXTOPCODE +Op6FM1mod1: +lbl6Fmod1a: AbsoluteLong +lbl6Fmod1b: ADC8 + NEXTOPCODE +Op70mod1: +lbl70mod1: Op70 + NEXTOPCODE +Op71M1mod1: +lbl71mod1a: DirectIndirectIndexed1 +lbl71mod1b: ADC8 + NEXTOPCODE +Op72M1mod1: +lbl72mod1a: DirectIndirect +lbl72mod1b: ADC8 + NEXTOPCODE +Op73M1mod1: +lbl73mod1a: StackasmRelativeIndirectIndexed1 +lbl73mod1b: ADC8 + NEXTOPCODE + +Op74M1mod1: +lbl74mod1a: DirectIndexedX1 +lbl74mod1b: STZ8 + NEXTOPCODE +Op75M1mod1: +lbl75mod1a: DirectIndexedX1 +lbl75mod1b: ADC8 + NEXTOPCODE +Op76M1mod1: +lbl76mod1a: DirectIndexedX1 +lbl76mod1b: ROR8 + NEXTOPCODE +Op77M1mod1: +lbl77mod1a: DirectIndirectIndexedLong1 +lbl77mod1b: ADC8 + NEXTOPCODE +Op78mod1: +lbl78mod1: Op78 + NEXTOPCODE +Op79M1mod1: +lbl79mod1a: AbsoluteIndexedY1 +lbl79mod1b: ADC8 + NEXTOPCODE +Op7AX1mod1: +lbl7Amod1: Op7AX1 + NEXTOPCODE +Op7Bmod1: +lbl7Bmod1: Op7BM1 + NEXTOPCODE +Op7Cmod1: +lbl7Cmod1: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE +Op7DM1mod1: +lbl7Dmod1a: AbsoluteIndexedX1 +lbl7Dmod1b: ADC8 + NEXTOPCODE +Op7EM1mod1: +lbl7Emod1a: AbsoluteIndexedX1 +lbl7Emod1b: ROR8 + NEXTOPCODE +Op7FM1mod1: +lbl7Fmod1a: AbsoluteLongIndexedX1 +lbl7Fmod1b: ADC8 + NEXTOPCODE + + +Op80mod1: +lbl80mod1: Op80 + NEXTOPCODE +Op81M1mod1: +lbl81mod1a: DirectIndexedIndirect1 +lbl81mod1b: Op81M1 + NEXTOPCODE +Op82mod1: +lbl82mod1: Op82 + NEXTOPCODE +Op83M1mod1: +lbl83mod1a: StackasmRelative +lbl83mod1b: STA8 + NEXTOPCODE +Op84X1mod1: +lbl84mod1a: Direct +lbl84mod1b: STY8 + NEXTOPCODE +Op85M1mod1: +lbl85mod1a: Direct +lbl85mod1b: STA8 + NEXTOPCODE +Op86X1mod1: +lbl86mod1a: Direct +lbl86mod1b: STX8 + NEXTOPCODE +Op87M1mod1: +lbl87mod1a: DirectIndirectLong +lbl87mod1b: STA8 + NEXTOPCODE +Op88X1mod1: +lbl88mod1: Op88X1 + NEXTOPCODE +Op89M1mod1: +lbl89mod1: Op89M1 + NEXTOPCODE +Op8AM1mod1: +lbl8Amod1: Op8AM1X1 + NEXTOPCODE +Op8Bmod1: +lbl8Bmod1: Op8B + NEXTOPCODE +Op8CX1mod1: +lbl8Cmod1a: Absolute +lbl8Cmod1b: STY8 + NEXTOPCODE +Op8DM1mod1: +lbl8Dmod1a: Absolute +lbl8Dmod1b: STA8 + NEXTOPCODE +Op8EX1mod1: +lbl8Emod1a: Absolute +lbl8Emod1b: STX8 + NEXTOPCODE +Op8FM1mod1: +lbl8Fmod1a: AbsoluteLong +lbl8Fmod1b: STA8 + NEXTOPCODE +Op90mod1: +lbl90mod1: Op90 + NEXTOPCODE +Op91M1mod1: +lbl91mod1a: DirectIndirectIndexed1 +lbl91mod1b: STA8 + NEXTOPCODE +Op92M1mod1: +lbl92mod1a: DirectIndirect +lbl92mod1b: STA8 + NEXTOPCODE +Op93M1mod1: +lbl93mod1a: StackasmRelativeIndirectIndexed1 +lbl93mod1b: STA8 + NEXTOPCODE +Op94X1mod1: +lbl94mod1a: DirectIndexedX1 +lbl94mod1b: STY8 + NEXTOPCODE +Op95M1mod1: +lbl95mod1a: DirectIndexedX1 +lbl95mod1b: STA8 + NEXTOPCODE +Op96X1mod1: +lbl96mod1a: DirectIndexedY1 +lbl96mod1b: STX8 + NEXTOPCODE +Op97M1mod1: +lbl97mod1a: DirectIndirectIndexedLong1 +lbl97mod1b: STA8 + NEXTOPCODE +Op98M1mod1: +lbl98mod1: Op98M1X1 + NEXTOPCODE +Op99M1mod1: +lbl99mod1a: AbsoluteIndexedY1 +lbl99mod1b: STA8 + NEXTOPCODE +Op9Amod1: +lbl9Amod1: Op9AX1 + NEXTOPCODE +Op9BX1mod1: +lbl9Bmod1: Op9BX1 + NEXTOPCODE +Op9CM1mod1: +lbl9Cmod1a: Absolute +lbl9Cmod1b: STZ8 + NEXTOPCODE +Op9DM1mod1: +lbl9Dmod1a: AbsoluteIndexedX1 +lbl9Dmod1b: STA8 + NEXTOPCODE +Op9EM1mod1: +lbl9Emod1: AbsoluteIndexedX1 + STZ8 + NEXTOPCODE +Op9FM1mod1: +lbl9Fmod1a: AbsoluteLongIndexedX1 +lbl9Fmod1b: STA8 + NEXTOPCODE +OpA0X1mod1: +lblA0mod1: OpA0X1 + NEXTOPCODE +OpA1M1mod1: +lblA1mod1a: DirectIndexedIndirect1 +lblA1mod1b: LDA8 + NEXTOPCODE +OpA2X1mod1: +lblA2mod1: OpA2X1 + NEXTOPCODE +OpA3M1mod1: +lblA3mod1a: StackasmRelative +lblA3mod1b: LDA8 + NEXTOPCODE +OpA4X1mod1: +lblA4mod1a: Direct +lblA4mod1b: LDY8 + NEXTOPCODE +OpA5M1mod1: +lblA5mod1a: Direct +lblA5mod1b: LDA8 + NEXTOPCODE +OpA6X1mod1: +lblA6mod1a: Direct +lblA6mod1b: LDX8 + NEXTOPCODE +OpA7M1mod1: +lblA7mod1a: DirectIndirectLong +lblA7mod1b: LDA8 + NEXTOPCODE +OpA8X1mod1: +lblA8mod1: OpA8X1M1 + NEXTOPCODE +OpA9M1mod1: +lblA9mod1: OpA9M1 + NEXTOPCODE +OpAAX1mod1: +lblAAmod1: OpAAX1M1 + NEXTOPCODE +OpABmod1: +lblABmod1: OpAB + NEXTOPCODE +OpACX1mod1: +lblACmod1a: Absolute +lblACmod1b: LDY8 + NEXTOPCODE +OpADM1mod1: +lblADmod1a: Absolute +lblADmod1b: LDA8 + NEXTOPCODE +OpAEX1mod1: +lblAEmod1a: Absolute +lblAEmod1b: LDX8 + NEXTOPCODE +OpAFM1mod1: +lblAFmod1a: AbsoluteLong +lblAFmod1b: LDA8 + NEXTOPCODE +OpB0mod1: +lblB0mod1: OpB0 + NEXTOPCODE +OpB1M1mod1: +lblB1mod1a: DirectIndirectIndexed1 +lblB1mod1b: LDA8 + NEXTOPCODE +OpB2M1mod1: +lblB2mod1a: DirectIndirect +lblB2mod1b: LDA8 + NEXTOPCODE +OpB3M1mod1: +lblB3mod1a: StackasmRelativeIndirectIndexed1 +lblB3mod1b: LDA8 + NEXTOPCODE +OpB4X1mod1: +lblB4mod1a: DirectIndexedX1 +lblB4mod1b: LDY8 + NEXTOPCODE +OpB5M1mod1: +lblB5mod1a: DirectIndexedX1 +lblB5mod1b: LDA8 + NEXTOPCODE +OpB6X1mod1: +lblB6mod1a: DirectIndexedY1 +lblB6mod1b: LDX8 + NEXTOPCODE +OpB7M1mod1: +lblB7mod1a: DirectIndirectIndexedLong1 +lblB7mod1b: LDA8 + NEXTOPCODE +OpB8mod1: +lblB8mod1: OpB8 + NEXTOPCODE +OpB9M1mod1: +lblB9mod1a: AbsoluteIndexedY1 +lblB9mod1b: LDA8 + NEXTOPCODE +OpBAX1mod1: +lblBAmod1: OpBAX1 + NEXTOPCODE +OpBBX1mod1: +lblBBmod1: OpBBX1 + NEXTOPCODE +OpBCX1mod1: +lblBCmod1a: AbsoluteIndexedX1 +lblBCmod1b: LDY8 + NEXTOPCODE +OpBDM1mod1: +lblBDmod1a: AbsoluteIndexedX1 +lblBDmod1b: LDA8 + NEXTOPCODE +OpBEX1mod1: +lblBEmod1a: AbsoluteIndexedY1 +lblBEmod1b: LDX8 + NEXTOPCODE +OpBFM1mod1: +lblBFmod1a: AbsoluteLongIndexedX1 +lblBFmod1b: LDA8 + NEXTOPCODE +OpC0X1mod1: +lblC0mod1: OpC0X1 + NEXTOPCODE +OpC1M1mod1: +lblC1mod1a: DirectIndexedIndirect1 +lblC1mod1b: CMP8 + NEXTOPCODE +OpC2mod1: +lblC2mod1: OpC2 + NEXTOPCODE +.pool +OpC3M1mod1: +lblC3mod1a: StackasmRelative +lblC3mod1b: CMP8 + NEXTOPCODE +OpC4X1mod1: +lblC4mod1a: Direct +lblC4mod1b: CMY8 + NEXTOPCODE +OpC5M1mod1: +lblC5mod1a: Direct +lblC5mod1b: CMP8 + NEXTOPCODE +OpC6M1mod1: +lblC6mod1a: Direct +lblC6mod1b: DEC8 + NEXTOPCODE +OpC7M1mod1: +lblC7mod1a: DirectIndirectLong +lblC7mod1b: CMP8 + NEXTOPCODE +OpC8X1mod1: +lblC8mod1: OpC8X1 + NEXTOPCODE +OpC9M1mod1: +lblC9mod1: OpC9M1 + NEXTOPCODE +OpCAX1mod1: +lblCAmod1: OpCAX1 + NEXTOPCODE +OpCBmod1: +lblCBmod1: OpCB + NEXTOPCODE +OpCCX1mod1: +lblCCmod1a: Absolute +lblCCmod1b: CMY8 + NEXTOPCODE +OpCDM1mod1: +lblCDmod1a: Absolute +lblCDmod1b: CMP8 + NEXTOPCODE +OpCEM1mod1: +lblCEmod1a: Absolute +lblCEmod1b: DEC8 + NEXTOPCODE +OpCFM1mod1: +lblCFmod1a: AbsoluteLong +lblCFmod1b: CMP8 + NEXTOPCODE +OpD0mod1: +lblD0mod1: OpD0 + NEXTOPCODE +OpD1M1mod1: +lblD1mod1a: DirectIndirectIndexed1 +lblD1mod1b: CMP8 + NEXTOPCODE +OpD2M1mod1: +lblD2mod1a: DirectIndirect +lblD2mod1b: CMP8 + NEXTOPCODE +OpD3M1mod1: +lblD3mod1a: StackasmRelativeIndirectIndexed1 +lblD3mod1b: CMP8 + + NEXTOPCODE +OpD4mod1: +lblD4mod1: OpD4 + NEXTOPCODE +OpD5M1mod1: +lblD5mod1a: DirectIndexedX1 +lblD5mod1b: CMP8 + NEXTOPCODE +OpD6M1mod1: +lblD6mod1a: DirectIndexedX1 +lblD6mod1b: DEC8 + NEXTOPCODE +OpD7M1mod1: +lblD7mod1a: DirectIndirectIndexedLong1 +lblD7mod1b: CMP8 + NEXTOPCODE +OpD8mod1: +lblD8mod1: OpD8 + NEXTOPCODE +OpD9M1mod1: +lblD9mod1a: AbsoluteIndexedY1 +lblD9mod1b: CMP8 + NEXTOPCODE +OpDAX1mod1: +lblDAmod1: OpDAX1 + NEXTOPCODE +OpDBmod1: +lblDBmod1: OpDB + NEXTOPCODE +OpDCmod1: +lblDCmod1: OpDC + NEXTOPCODE +OpDDM1mod1: +lblDDmod1a: AbsoluteIndexedX1 +lblDDmod1b: CMP8 + NEXTOPCODE +OpDEM1mod1: +lblDEmod1a: AbsoluteIndexedX1 +lblDEmod1b: DEC8 + NEXTOPCODE +OpDFM1mod1: +lblDFmod1a: AbsoluteLongIndexedX1 +lblDFmod1b: CMP8 + NEXTOPCODE +OpE0X1mod1: +lblE0mod1: OpE0X1 + NEXTOPCODE +OpE1M1mod1: +lblE1mod1a: DirectIndexedIndirect1 +lblE1mod1b: SBC8 + NEXTOPCODE +OpE2mod1: +lblE2mod1: OpE2 + NEXTOPCODE +.pool +OpE3M1mod1: +lblE3mod1a: StackasmRelative +lblE3mod1b: SBC8 + NEXTOPCODE +OpE4X1mod1: +lblE4mod1a: Direct +lblE4mod1b: CMX8 + NEXTOPCODE +OpE5M1mod1: +lblE5mod1a: Direct +lblE5mod1b: SBC8 + NEXTOPCODE +OpE6M1mod1: +lblE6mod1a: Direct +lblE6mod1b: INC8 + NEXTOPCODE +OpE7M1mod1: +lblE7mod1a: DirectIndirectLong +lblE7mod1b: SBC8 + NEXTOPCODE +OpE8X1mod1: +lblE8mod1: OpE8X1 + NEXTOPCODE +OpE9M1mod1: +lblE9mod1a: Immediate8 +lblE9mod1b: SBC8 + NEXTOPCODE +OpEAmod1: +lblEAmod1: OpEA + NEXTOPCODE +OpEBmod1: +lblEBmod1: OpEBM1 + NEXTOPCODE +OpECX1mod1: +lblECmod1a: Absolute +lblECmod1b: CMX8 + NEXTOPCODE +OpEDM1mod1: +lblEDmod1a: Absolute +lblEDmod1b: SBC8 + NEXTOPCODE +OpEEM1mod1: +lblEEmod1a: Absolute +lblEEmod1b: INC8 + NEXTOPCODE +OpEFM1mod1: +lblEFmod1a: AbsoluteLong +lblEFmod1b: SBC8 + NEXTOPCODE +OpF0mod1: +lblF0mod1: OpF0 + NEXTOPCODE +OpF1M1mod1: +lblF1mod1a: DirectIndirectIndexed1 +lblF1mod1b: SBC8 + NEXTOPCODE +OpF2M1mod1: +lblF2mod1a: DirectIndirect +lblF2mod1b: SBC8 + NEXTOPCODE +OpF3M1mod1: +lblF3mod1a: StackasmRelativeIndirectIndexed1 +lblF3mod1b: SBC8 + NEXTOPCODE +OpF4mod1: +lblF4mod1: OpF4 + NEXTOPCODE +OpF5M1mod1: +lblF5mod1a: DirectIndexedX1 +lblF5mod1b: SBC8 + NEXTOPCODE +OpF6M1mod1: +lblF6mod1a: DirectIndexedX1 +lblF6mod1b: INC8 + NEXTOPCODE +OpF7M1mod1: +lblF7mod1a: DirectIndirectIndexedLong1 +lblF7mod1b: SBC8 + NEXTOPCODE +OpF8mod1: +lblF8mod1: OpF8 + NEXTOPCODE +OpF9M1mod1: +lblF9mod1a: AbsoluteIndexedY1 +lblF9mod1b: SBC8 + NEXTOPCODE +OpFAX1mod1: +lblFAmod1: OpFAX1 + NEXTOPCODE +OpFBmod1: +lblFBmod1: OpFB + NEXTOPCODE +OpFCmod1: +lblFCmod1: OpFCX1 + NEXTOPCODE +OpFDM1mod1: +lblFDmod1a: AbsoluteIndexedX1 +lblFDmod1b: SBC8 + NEXTOPCODE +OpFEM1mod1: +lblFEmod1a: AbsoluteIndexedX1 +lblFEmod1b: INC8 + NEXTOPCODE +OpFFM1mod1: +lblFFmod1a: AbsoluteLongIndexedX1 +lblFFmod1b: SBC8 + NEXTOPCODE +.pool + + +jumptable2: .long Op00mod2 + .long Op01M1mod2 + .long Op02mod2 + .long Op03M1mod2 + .long Op04M1mod2 + .long Op05M1mod2 + .long Op06M1mod2 + .long Op07M1mod2 + .long Op08mod2 + .long Op09M1mod2 + .long Op0AM1mod2 + .long Op0Bmod2 + .long Op0CM1mod2 + .long Op0DM1mod2 + .long Op0EM1mod2 + .long Op0FM1mod2 + .long Op10mod2 + .long Op11M1mod2 + .long Op12M1mod2 + .long Op13M1mod2 + .long Op14M1mod2 + .long Op15M1mod2 + .long Op16M1mod2 + .long Op17M1mod2 + .long Op18mod2 + .long Op19M1mod2 + .long Op1AM1mod2 + .long Op1Bmod2 + .long Op1CM1mod2 + .long Op1DM1mod2 + .long Op1EM1mod2 + .long Op1FM1mod2 + .long Op20mod2 + .long Op21M1mod2 + .long Op22mod2 + .long Op23M1mod2 + .long Op24M1mod2 + .long Op25M1mod2 + .long Op26M1mod2 + .long Op27M1mod2 + .long Op28mod2 + .long Op29M1mod2 + .long Op2AM1mod2 + .long Op2Bmod2 + .long Op2CM1mod2 + .long Op2DM1mod2 + .long Op2EM1mod2 + .long Op2FM1mod2 + .long Op30mod2 + .long Op31M1mod2 + .long Op32M1mod2 + .long Op33M1mod2 + .long Op34M1mod2 + .long Op35M1mod2 + .long Op36M1mod2 + .long Op37M1mod2 + .long Op38mod2 + .long Op39M1mod2 + .long Op3AM1mod2 + .long Op3Bmod2 + .long Op3CM1mod2 + .long Op3DM1mod2 + .long Op3EM1mod2 + .long Op3FM1mod2 + .long Op40mod2 + .long Op41M1mod2 + .long Op42mod2 + .long Op43M1mod2 + .long Op44X0mod2 + .long Op45M1mod2 + .long Op46M1mod2 + .long Op47M1mod2 + .long Op48M1mod2 + .long Op49M1mod2 + .long Op4AM1mod2 + .long Op4Bmod2 + .long Op4Cmod2 + .long Op4DM1mod2 + .long Op4EM1mod2 + .long Op4FM1mod2 + .long Op50mod2 + .long Op51M1mod2 + .long Op52M1mod2 + .long Op53M1mod2 + .long Op54X0mod2 + .long Op55M1mod2 + .long Op56M1mod2 + .long Op57M1mod2 + .long Op58mod2 + .long Op59M1mod2 + .long Op5AX0mod2 + .long Op5Bmod2 + .long Op5Cmod2 + .long Op5DM1mod2 + .long Op5EM1mod2 + .long Op5FM1mod2 + .long Op60mod2 + .long Op61M1mod2 + .long Op62mod2 + .long Op63M1mod2 + .long Op64M1mod2 + .long Op65M1mod2 + .long Op66M1mod2 + .long Op67M1mod2 + .long Op68M1mod2 + .long Op69M1mod2 + .long Op6AM1mod2 + .long Op6Bmod2 + .long Op6Cmod2 + .long Op6DM1mod2 + .long Op6EM1mod2 + .long Op6FM1mod2 + .long Op70mod2 + .long Op71M1mod2 + .long Op72M1mod2 + .long Op73M1mod2 + .long Op74M1mod2 + .long Op75M1mod2 + .long Op76M1mod2 + .long Op77M1mod2 + .long Op78mod2 + .long Op79M1mod2 + .long Op7AX0mod2 + .long Op7Bmod2 + .long Op7Cmod2 + .long Op7DM1mod2 + .long Op7EM1mod2 + .long Op7FM1mod2 + .long Op80mod2 + .long Op81M1mod2 + .long Op82mod2 + .long Op83M1mod2 + .long Op84X0mod2 + .long Op85M1mod2 + .long Op86X0mod2 + .long Op87M1mod2 + .long Op88X0mod2 + .long Op89M1mod2 + .long Op8AM1mod2 + .long Op8Bmod2 + .long Op8CX0mod2 + .long Op8DM1mod2 + .long Op8EX0mod2 + .long Op8FM1mod2 + .long Op90mod2 + .long Op91M1mod2 + .long Op92M1mod2 + .long Op93M1mod2 + .long Op94X0mod2 + .long Op95M1mod2 + .long Op96X0mod2 + .long Op97M1mod2 + .long Op98M1mod2 + .long Op99M1mod2 + .long Op9Amod2 + .long Op9BX0mod2 + .long Op9CM1mod2 + .long Op9DM1mod2 + .long Op9EM1mod2 + .long Op9FM1mod2 + .long OpA0X0mod2 + .long OpA1M1mod2 + .long OpA2X0mod2 + .long OpA3M1mod2 + .long OpA4X0mod2 + .long OpA5M1mod2 + .long OpA6X0mod2 + .long OpA7M1mod2 + .long OpA8X0mod2 + .long OpA9M1mod2 + .long OpAAX0mod2 + .long OpABmod2 + .long OpACX0mod2 + .long OpADM1mod2 + .long OpAEX0mod2 + .long OpAFM1mod2 + .long OpB0mod2 + .long OpB1M1mod2 + .long OpB2M1mod2 + .long OpB3M1mod2 + .long OpB4X0mod2 + .long OpB5M1mod2 + .long OpB6X0mod2 + .long OpB7M1mod2 + .long OpB8mod2 + .long OpB9M1mod2 + .long OpBAX0mod2 + .long OpBBX0mod2 + .long OpBCX0mod2 + .long OpBDM1mod2 + .long OpBEX0mod2 + .long OpBFM1mod2 + .long OpC0X0mod2 + .long OpC1M1mod2 + .long OpC2mod2 + .long OpC3M1mod2 + .long OpC4X0mod2 + .long OpC5M1mod2 + .long OpC6M1mod2 + .long OpC7M1mod2 + .long OpC8X0mod2 + .long OpC9M1mod2 + .long OpCAX0mod2 + .long OpCBmod2 + .long OpCCX0mod2 + .long OpCDM1mod2 + .long OpCEM1mod2 + .long OpCFM1mod2 + .long OpD0mod2 + .long OpD1M1mod2 + .long OpD2M1mod2 + .long OpD3M1mod2 + .long OpD4mod2 + .long OpD5M1mod2 + .long OpD6M1mod2 + .long OpD7M1mod2 + .long OpD8mod2 + .long OpD9M1mod2 + .long OpDAX0mod2 + .long OpDBmod2 + .long OpDCmod2 + .long OpDDM1mod2 + .long OpDEM1mod2 + .long OpDFM1mod2 + .long OpE0X0mod2 + .long OpE1M1mod2 + .long OpE2mod2 + .long OpE3M1mod2 + .long OpE4X0mod2 + .long OpE5M1mod2 + .long OpE6M1mod2 + .long OpE7M1mod2 + .long OpE8X0mod2 + .long OpE9M1mod2 + .long OpEAmod2 + .long OpEBmod2 + .long OpECX0mod2 + .long OpEDM1mod2 + .long OpEEM1mod2 + .long OpEFM1mod2 + .long OpF0mod2 + .long OpF1M1mod2 + .long OpF2M1mod2 + .long OpF3M1mod2 + .long OpF4mod2 + .long OpF5M1mod2 + .long OpF6M1mod2 + .long OpF7M1mod2 + .long OpF8mod2 + .long OpF9M1mod2 + .long OpFAX0mod2 + .long OpFBmod2 + .long OpFCmod2 + .long OpFDM1mod2 + .long OpFEM1mod2 + .long OpFFM1mod2 +Op00mod2: +lbl00mod2: Op00 + NEXTOPCODE +Op01M1mod2: +lbl01mod2a: DirectIndexedIndirect0 +lbl01mod2b: ORA8 + NEXTOPCODE +Op02mod2: +lbl02mod2: Op02 + NEXTOPCODE +Op03M1mod2: +lbl03mod2a: StackasmRelative +lbl03mod2b: ORA8 + NEXTOPCODE +Op04M1mod2: +lbl04mod2a: Direct +lbl04mod2b: TSB8 + NEXTOPCODE +Op05M1mod2: +lbl05mod2a: Direct +lbl05mod2b: ORA8 + NEXTOPCODE +Op06M1mod2: +lbl06mod2a: Direct +lbl06mod2b: ASL8 + NEXTOPCODE +Op07M1mod2: +lbl07mod2a: DirectIndirectLong +lbl07mod2b: ORA8 + NEXTOPCODE +Op08mod2: + +lbl08mod2: Op08 + NEXTOPCODE +Op09M1mod2: +lbl09mod2: Op09M1 + NEXTOPCODE +Op0AM1mod2: +lbl0Amod2a: A_ASL8 + NEXTOPCODE +Op0Bmod2: +lbl0Bmod2: Op0B + NEXTOPCODE +Op0CM1mod2: +lbl0Cmod2a: Absolute +lbl0Cmod2b: TSB8 + NEXTOPCODE +Op0DM1mod2: +lbl0Dmod2a: Absolute +lbl0Dmod2b: ORA8 + NEXTOPCODE +Op0EM1mod2: +lbl0Emod2a: Absolute +lbl0Emod2b: ASL8 + NEXTOPCODE +Op0FM1mod2: +lbl0Fmod2a: AbsoluteLong +lbl0Fmod2b: ORA8 + NEXTOPCODE +Op10mod2: +lbl10mod2: Op10 + NEXTOPCODE +Op11M1mod2: +lbl11mod2a: DirectIndirectIndexed0 +lbl11mod2b: ORA8 + NEXTOPCODE +Op12M1mod2: +lbl12mod2a: DirectIndirect +lbl12mod2b: ORA8 + NEXTOPCODE +Op13M1mod2: +lbl13mod2a: StackasmRelativeIndirectIndexed0 +lbl13mod2b: ORA8 + NEXTOPCODE +Op14M1mod2: +lbl14mod2a: Direct +lbl14mod2b: TRB8 + NEXTOPCODE +Op15M1mod2: +lbl15mod2a: DirectIndexedX0 +lbl15mod2b: ORA8 + NEXTOPCODE +Op16M1mod2: +lbl16mod2a: DirectIndexedX0 +lbl16mod2b: ASL8 + NEXTOPCODE +Op17M1mod2: +lbl17mod2a: DirectIndirectIndexedLong0 +lbl17mod2b: ORA8 + NEXTOPCODE +Op18mod2: +lbl18mod2: Op18 + NEXTOPCODE +Op19M1mod2: +lbl19mod2a: AbsoluteIndexedY0 +lbl19mod2b: ORA8 + NEXTOPCODE +Op1AM1mod2: +lbl1Amod2a: A_INC8 + NEXTOPCODE +Op1Bmod2: +lbl1Bmod2: Op1BM1 + NEXTOPCODE +Op1CM1mod2: +lbl1Cmod2a: Absolute +lbl1Cmod2b: TRB8 + NEXTOPCODE +Op1DM1mod2: +lbl1Dmod2a: AbsoluteIndexedX0 +lbl1Dmod2b: ORA8 + NEXTOPCODE +Op1EM1mod2: +lbl1Emod2a: AbsoluteIndexedX0 +lbl1Emod2b: ASL8 + NEXTOPCODE +Op1FM1mod2: +lbl1Fmod2a: AbsoluteLongIndexedX0 +lbl1Fmod2b: ORA8 + NEXTOPCODE +Op20mod2: +lbl20mod2: Op20 + NEXTOPCODE +Op21M1mod2: +lbl21mod2a: DirectIndexedIndirect0 +lbl21mod2b: AND8 + NEXTOPCODE +Op22mod2: +lbl22mod2: Op22 + NEXTOPCODE +Op23M1mod2: +lbl23mod2a: StackasmRelative +lbl23mod2b: AND8 + NEXTOPCODE +Op24M1mod2: +lbl24mod2a: Direct +lbl24mod2b: BIT8 + NEXTOPCODE +Op25M1mod2: +lbl25mod2a: Direct +lbl25mod2b: AND8 + NEXTOPCODE +Op26M1mod2: +lbl26mod2a: Direct +lbl26mod2b: ROL8 + NEXTOPCODE +Op27M1mod2: +lbl27mod2a: DirectIndirectLong +lbl27mod2b: AND8 + NEXTOPCODE +Op28mod2: +lbl28mod2: Op28X0M1 + NEXTOPCODE +.pool +Op29M1mod2: +lbl29mod2: Op29M1 + NEXTOPCODE +Op2AM1mod2: +lbl2Amod2a: A_ROL8 + NEXTOPCODE +Op2Bmod2: +lbl2Bmod2: Op2B + NEXTOPCODE +Op2CM1mod2: +lbl2Cmod2a: Absolute +lbl2Cmod2b: BIT8 + NEXTOPCODE +Op2DM1mod2: +lbl2Dmod2a: Absolute +lbl2Dmod2b: AND8 + NEXTOPCODE +Op2EM1mod2: +lbl2Emod2a: Absolute +lbl2Emod2b: ROL8 + NEXTOPCODE +Op2FM1mod2: +lbl2Fmod2a: AbsoluteLong +lbl2Fmod2b: AND8 + NEXTOPCODE +Op30mod2: +lbl30mod2: Op30 + NEXTOPCODE +Op31M1mod2: +lbl31mod2a: DirectIndirectIndexed0 +lbl31mod2b: AND8 + NEXTOPCODE +Op32M1mod2: +lbl32mod2a: DirectIndirect +lbl32mod2b: AND8 + NEXTOPCODE +Op33M1mod2: +lbl33mod2a: StackasmRelativeIndirectIndexed0 +lbl33mod2b: AND8 + NEXTOPCODE +Op34M1mod2: +lbl34mod2a: DirectIndexedX0 +lbl34mod2b: BIT8 + NEXTOPCODE +Op35M1mod2: +lbl35mod2a: DirectIndexedX0 +lbl35mod2b: AND8 + NEXTOPCODE +Op36M1mod2: +lbl36mod2a: DirectIndexedX0 +lbl36mod2b: ROL8 + NEXTOPCODE +Op37M1mod2: +lbl37mod2a: DirectIndirectIndexedLong0 +lbl37mod2b: AND8 + NEXTOPCODE +Op38mod2: +lbl38mod2: Op38 + NEXTOPCODE +Op39M1mod2: +lbl39mod2a: AbsoluteIndexedY0 +lbl39mod2b: AND8 + NEXTOPCODE +Op3AM1mod2: +lbl3Amod2a: A_DEC8 + NEXTOPCODE +Op3Bmod2: +lbl3Bmod2: Op3BM1 + NEXTOPCODE +Op3CM1mod2: +lbl3Cmod2a: AbsoluteIndexedX0 +lbl3Cmod2b: BIT8 + NEXTOPCODE +Op3DM1mod2: +lbl3Dmod2a: AbsoluteIndexedX0 +lbl3Dmod2b: AND8 + NEXTOPCODE +Op3EM1mod2: +lbl3Emod2a: AbsoluteIndexedX0 +lbl3Emod2b: ROL8 + NEXTOPCODE +Op3FM1mod2: +lbl3Fmod2a: AbsoluteLongIndexedX0 +lbl3Fmod2b: AND8 + NEXTOPCODE +Op40mod2: +lbl40mod2: Op40X0M1 + NEXTOPCODE +.pool +Op41M1mod2: +lbl41mod2a: DirectIndexedIndirect0 +lbl41mod2b: EOR8 + NEXTOPCODE +Op42mod2: +lbl42mod2: Op42 + NEXTOPCODE +Op43M1mod2: +lbl43mod2a: StackasmRelative +lbl43mod2b: EOR8 + NEXTOPCODE +Op44X0mod2: +lbl44mod2: Op44X0M1 + NEXTOPCODE +Op45M1mod2: +lbl45mod2a: Direct +lbl45mod2b: EOR8 + NEXTOPCODE +Op46M1mod2: +lbl46mod2a: Direct +lbl46mod2b: LSR8 + NEXTOPCODE +Op47M1mod2: +lbl47mod2a: DirectIndirectLong +lbl47mod2b: EOR8 + NEXTOPCODE +Op48M1mod2: +lbl48mod2: Op48M1 + NEXTOPCODE +Op49M1mod2: +lbl49mod2: Op49M1 + NEXTOPCODE +Op4AM1mod2: +lbl4Amod2a: A_LSR8 + NEXTOPCODE +Op4Bmod2: +lbl4Bmod2: Op4B + NEXTOPCODE +Op4Cmod2: +lbl4Cmod2: Op4C + NEXTOPCODE +Op4DM1mod2: +lbl4Dmod2a: Absolute +lbl4Dmod2b: EOR8 + NEXTOPCODE +Op4EM1mod2: +lbl4Emod2a: Absolute +lbl4Emod2b: LSR8 + NEXTOPCODE +Op4FM1mod2: +lbl4Fmod2a: AbsoluteLong +lbl4Fmod2b: EOR8 + NEXTOPCODE +Op50mod2: +lbl50mod2: Op50 + NEXTOPCODE +Op51M1mod2: +lbl51mod2a: DirectIndirectIndexed0 +lbl51mod2b: EOR8 + NEXTOPCODE +Op52M1mod2: +lbl52mod2a: DirectIndirect +lbl52mod2b: EOR8 + NEXTOPCODE +Op53M1mod2: +lbl53mod2a: StackasmRelativeIndirectIndexed0 +lbl53mod2b: EOR8 + NEXTOPCODE +Op54X0mod2: +lbl54mod2: Op54X0M1 + NEXTOPCODE +Op55M1mod2: +lbl55mod2a: DirectIndexedX0 +lbl55mod2b: EOR8 + NEXTOPCODE +Op56M1mod2: +lbl56mod2a: DirectIndexedX0 +lbl56mod2b: LSR8 + NEXTOPCODE +Op57M1mod2: +lbl57mod2a: DirectIndirectIndexedLong0 +lbl57mod2b: EOR8 + NEXTOPCODE +Op58mod2: +lbl58mod2: Op58 + NEXTOPCODE +Op59M1mod2: +lbl59mod2a: AbsoluteIndexedY0 +lbl59mod2b: EOR8 + NEXTOPCODE +Op5AX0mod2: +lbl5Amod2: Op5AX0 + NEXTOPCODE +Op5Bmod2: +lbl5Bmod2: Op5BM1 + NEXTOPCODE +Op5Cmod2: +lbl5Cmod2: Op5C + NEXTOPCODE +Op5DM1mod2: +lbl5Dmod2a: AbsoluteIndexedX0 +lbl5Dmod2b: EOR8 + NEXTOPCODE +Op5EM1mod2: +lbl5Emod2a: AbsoluteIndexedX0 +lbl5Emod2b: LSR8 + NEXTOPCODE +Op5FM1mod2: +lbl5Fmod2a: AbsoluteLongIndexedX0 +lbl5Fmod2b: EOR8 + NEXTOPCODE +Op60mod2: +lbl60mod2: Op60 + NEXTOPCODE +Op61M1mod2: +lbl61mod2a: DirectIndexedIndirect0 +lbl61mod2b: ADC8 + NEXTOPCODE +Op62mod2: +lbl62mod2: Op62 + NEXTOPCODE +Op63M1mod2: +lbl63mod2a: StackasmRelative +lbl63mod2b: ADC8 + NEXTOPCODE +Op64M1mod2: +lbl64mod2a: Direct +lbl64mod2b: STZ8 + NEXTOPCODE +Op65M1mod2: +lbl65mod2a: Direct +lbl65mod2b: ADC8 + NEXTOPCODE +Op66M1mod2: +lbl66mod2a: Direct +lbl66mod2b: ROR8 + NEXTOPCODE +Op67M1mod2: +lbl67mod2a: DirectIndirectLong +lbl67mod2b: ADC8 + NEXTOPCODE +Op68M1mod2: +lbl68mod2: Op68M1 + NEXTOPCODE +Op69M1mod2: +lbl69mod2a: Immediate8 +lbl69mod2b: ADC8 + NEXTOPCODE +Op6AM1mod2: +lbl6Amod2a: A_ROR8 + NEXTOPCODE +Op6Bmod2: +lbl6Bmod2: Op6B + NEXTOPCODE +Op6Cmod2: +lbl6Cmod2: Op6C + NEXTOPCODE +Op6DM1mod2: +lbl6Dmod2a: Absolute +lbl6Dmod2b: ADC8 + NEXTOPCODE +Op6EM1mod2: +lbl6Emod2a: Absolute +lbl6Emod2b: ROR8 + NEXTOPCODE +Op6FM1mod2: +lbl6Fmod2a: AbsoluteLong +lbl6Fmod2b: ADC8 + NEXTOPCODE +Op70mod2: +lbl70mod2: Op70 + NEXTOPCODE +Op71M1mod2: +lbl71mod2a: DirectIndirectIndexed0 +lbl71mod2b: ADC8 + NEXTOPCODE +Op72M1mod2: +lbl72mod2a: DirectIndirect +lbl72mod2b: ADC8 + NEXTOPCODE +Op73M1mod2: +lbl73mod2a: StackasmRelativeIndirectIndexed0 +lbl73mod2b: ADC8 + NEXTOPCODE +Op74M1mod2: +lbl74mod2a: DirectIndexedX0 +lbl74mod2b: STZ8 + NEXTOPCODE +Op75M1mod2: +lbl75mod2a: DirectIndexedX0 +lbl75mod2b: ADC8 + NEXTOPCODE +Op76M1mod2: +lbl76mod2a: DirectIndexedX0 +lbl76mod2b: ROR8 + NEXTOPCODE +Op77M1mod2: +lbl77mod2a: DirectIndirectIndexedLong0 +lbl77mod2b: ADC8 + NEXTOPCODE +Op78mod2: +lbl78mod2: Op78 + NEXTOPCODE +Op79M1mod2: +lbl79mod2a: AbsoluteIndexedY0 +lbl79mod2b: ADC8 + NEXTOPCODE +Op7AX0mod2: +lbl7Amod2: Op7AX0 + NEXTOPCODE +Op7Bmod2: +lbl7Bmod2: Op7BM1 + NEXTOPCODE +Op7Cmod2: +lbl7Cmod2: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE +Op7DM1mod2: +lbl7Dmod2a: AbsoluteIndexedX0 +lbl7Dmod2b: ADC8 + NEXTOPCODE +Op7EM1mod2: +lbl7Emod2a: AbsoluteIndexedX0 +lbl7Emod2b: ROR8 + NEXTOPCODE +Op7FM1mod2: +lbl7Fmod2a: AbsoluteLongIndexedX0 +lbl7Fmod2b: ADC8 + NEXTOPCODE + + +Op80mod2: +lbl80mod2: Op80 + NEXTOPCODE +Op81M1mod2: +lbl81mod2a: DirectIndexedIndirect0 +lbl81mod2b: Op81M1 + NEXTOPCODE +Op82mod2: +lbl82mod2: Op82 + NEXTOPCODE +Op83M1mod2: +lbl83mod2a: StackasmRelative +lbl83mod2b: STA8 + NEXTOPCODE +Op84X0mod2: +lbl84mod2a: Direct +lbl84mod2b: STY16 + NEXTOPCODE +Op85M1mod2: +lbl85mod2a: Direct +lbl85mod2b: STA8 + NEXTOPCODE +Op86X0mod2: +lbl86mod2a: Direct +lbl86mod2b: STX16 + NEXTOPCODE +Op87M1mod2: +lbl87mod2a: DirectIndirectLong +lbl87mod2b: STA8 + NEXTOPCODE +Op88X0mod2: +lbl88mod2: Op88X0 + NEXTOPCODE +Op89M1mod2: +lbl89mod2: Op89M1 + NEXTOPCODE +Op8AM1mod2: +lbl8Amod2: Op8AM1X0 + NEXTOPCODE +Op8Bmod2: +lbl8Bmod2: Op8B + NEXTOPCODE +Op8CX0mod2: +lbl8Cmod2a: Absolute +lbl8Cmod2b: STY16 + NEXTOPCODE +Op8DM1mod2: +lbl8Dmod2a: Absolute +lbl8Dmod2b: STA8 + NEXTOPCODE +Op8EX0mod2: +lbl8Emod2a: Absolute +lbl8Emod2b: STX16 + NEXTOPCODE +Op8FM1mod2: +lbl8Fmod2a: AbsoluteLong +lbl8Fmod2b: STA8 + NEXTOPCODE +Op90mod2: +lbl90mod2: Op90 + NEXTOPCODE +Op91M1mod2: +lbl91mod2a: DirectIndirectIndexed0 +lbl91mod2b: STA8 + NEXTOPCODE +Op92M1mod2: +lbl92mod2a: DirectIndirect +lbl92mod2b: STA8 + NEXTOPCODE +Op93M1mod2: +lbl93mod2a: StackasmRelativeIndirectIndexed0 +lbl93mod2b: STA8 + NEXTOPCODE +Op94X0mod2: +lbl94mod2a: DirectIndexedX0 +lbl94mod2b: STY16 + NEXTOPCODE +Op95M1mod2: + +lbl95mod2a: DirectIndexedX0 +lbl95mod2b: STA8 + NEXTOPCODE +Op96X0mod2: +lbl96mod2a: DirectIndexedY0 +lbl96mod2b: STX16 + NEXTOPCODE +Op97M1mod2: +lbl97mod2a: DirectIndirectIndexedLong0 +lbl97mod2b: STA8 + NEXTOPCODE +Op98M1mod2: +lbl98mod2: Op98M1X0 + NEXTOPCODE +Op99M1mod2: +lbl99mod2a: AbsoluteIndexedY0 +lbl99mod2b: STA8 + NEXTOPCODE +Op9Amod2: +lbl9Amod2: Op9AX0 + NEXTOPCODE +Op9BX0mod2: +lbl9Bmod2: Op9BX0 + NEXTOPCODE +Op9CM1mod2: +lbl9Cmod2a: Absolute +lbl9Cmod2b: STZ8 + NEXTOPCODE +Op9DM1mod2: +lbl9Dmod2a: AbsoluteIndexedX0 +lbl9Dmod2b: STA8 + NEXTOPCODE +Op9EM1mod2: +lbl9Emod2: AbsoluteIndexedX0 + STZ8 + NEXTOPCODE +Op9FM1mod2: +lbl9Fmod2a: AbsoluteLongIndexedX0 +lbl9Fmod2b: STA8 + NEXTOPCODE +OpA0X0mod2: +lblA0mod2: OpA0X0 + NEXTOPCODE +OpA1M1mod2: +lblA1mod2a: DirectIndexedIndirect0 +lblA1mod2b: LDA8 + NEXTOPCODE +OpA2X0mod2: +lblA2mod2: OpA2X0 + NEXTOPCODE +OpA3M1mod2: +lblA3mod2a: StackasmRelative +lblA3mod2b: LDA8 + NEXTOPCODE +OpA4X0mod2: +lblA4mod2a: Direct +lblA4mod2b: LDY16 + NEXTOPCODE +OpA5M1mod2: +lblA5mod2a: Direct +lblA5mod2b: LDA8 + NEXTOPCODE +OpA6X0mod2: +lblA6mod2a: Direct +lblA6mod2b: LDX16 + NEXTOPCODE +OpA7M1mod2: +lblA7mod2a: DirectIndirectLong +lblA7mod2b: LDA8 + NEXTOPCODE +OpA8X0mod2: +lblA8mod2: OpA8X0M1 + NEXTOPCODE +OpA9M1mod2: +lblA9mod2: OpA9M1 + NEXTOPCODE +OpAAX0mod2: +lblAAmod2: OpAAX0M1 + NEXTOPCODE +OpABmod2: +lblABmod2: OpAB + NEXTOPCODE +OpACX0mod2: +lblACmod2a: Absolute +lblACmod2b: LDY16 + NEXTOPCODE +OpADM1mod2: +lblADmod2a: Absolute +lblADmod2b: LDA8 + NEXTOPCODE +OpAEX0mod2: +lblAEmod2a: Absolute +lblAEmod2b: LDX16 + NEXTOPCODE +OpAFM1mod2: +lblAFmod2a: AbsoluteLong +lblAFmod2b: LDA8 + NEXTOPCODE +OpB0mod2: +lblB0mod2: OpB0 + NEXTOPCODE +OpB1M1mod2: +lblB1mod2a: DirectIndirectIndexed0 +lblB1mod2b: LDA8 + NEXTOPCODE +OpB2M1mod2: +lblB2mod2a: DirectIndirect +lblB2mod2b: LDA8 + NEXTOPCODE +OpB3M1mod2: +lblB3mod2a: StackasmRelativeIndirectIndexed0 +lblB3mod2b: LDA8 + NEXTOPCODE +OpB4X0mod2: +lblB4mod2a: DirectIndexedX0 +lblB4mod2b: LDY16 + NEXTOPCODE +OpB5M1mod2: +lblB5mod2a: DirectIndexedX0 +lblB5mod2b: LDA8 + NEXTOPCODE +OpB6X0mod2: +lblB6mod2a: DirectIndexedY0 +lblB6mod2b: LDX16 + NEXTOPCODE +OpB7M1mod2: +lblB7mod2a: DirectIndirectIndexedLong0 +lblB7mod2b: LDA8 + NEXTOPCODE +OpB8mod2: +lblB8mod2: OpB8 + NEXTOPCODE +OpB9M1mod2: +lblB9mod2a: AbsoluteIndexedY0 +lblB9mod2b: LDA8 + NEXTOPCODE +OpBAX0mod2: +lblBAmod2: OpBAX0 + NEXTOPCODE +OpBBX0mod2: +lblBBmod2: OpBBX0 + NEXTOPCODE +OpBCX0mod2: +lblBCmod2a: AbsoluteIndexedX0 +lblBCmod2b: LDY16 + NEXTOPCODE +OpBDM1mod2: +lblBDmod2a: AbsoluteIndexedX0 +lblBDmod2b: LDA8 + NEXTOPCODE +OpBEX0mod2: +lblBEmod2a: AbsoluteIndexedY0 +lblBEmod2b: LDX16 + NEXTOPCODE +OpBFM1mod2: +lblBFmod2a: AbsoluteLongIndexedX0 +lblBFmod2b: LDA8 + NEXTOPCODE +OpC0X0mod2: +lblC0mod2: OpC0X0 + NEXTOPCODE +OpC1M1mod2: +lblC1mod2a: DirectIndexedIndirect0 +lblC1mod2b: CMP8 + NEXTOPCODE +OpC2mod2: +lblC2mod2: OpC2 + NEXTOPCODE +.pool +OpC3M1mod2: +lblC3mod2a: StackasmRelative +lblC3mod2b: CMP8 + NEXTOPCODE +OpC4X0mod2: +lblC4mod2a: Direct +lblC4mod2b: CMY16 + NEXTOPCODE +OpC5M1mod2: +lblC5mod2a: Direct +lblC5mod2b: CMP8 + NEXTOPCODE +OpC6M1mod2: +lblC6mod2a: Direct +lblC6mod2b: DEC8 + NEXTOPCODE +OpC7M1mod2: +lblC7mod2a: DirectIndirectLong +lblC7mod2b: CMP8 + NEXTOPCODE +OpC8X0mod2: +lblC8mod2: OpC8X0 + NEXTOPCODE +OpC9M1mod2: +lblC9mod2: OpC9M1 + NEXTOPCODE +OpCAX0mod2: +lblCAmod2: OpCAX0 + NEXTOPCODE +OpCBmod2: +lblCBmod2: OpCB + NEXTOPCODE +OpCCX0mod2: +lblCCmod2a: Absolute +lblCCmod2b: CMY16 + NEXTOPCODE +OpCDM1mod2: +lblCDmod2a: Absolute +lblCDmod2b: CMP8 + NEXTOPCODE +OpCEM1mod2: +lblCEmod2a: Absolute +lblCEmod2b: DEC8 + NEXTOPCODE +OpCFM1mod2: +lblCFmod2a: AbsoluteLong +lblCFmod2b: CMP8 + NEXTOPCODE +OpD0mod2: +lblD0mod2: OpD0 + NEXTOPCODE +OpD1M1mod2: +lblD1mod2a: DirectIndirectIndexed0 +lblD1mod2b: CMP8 + NEXTOPCODE +OpD2M1mod2: +lblD2mod2a: DirectIndirect +lblD2mod2b: CMP8 + NEXTOPCODE +OpD3M1mod2: +lblD3mod2a: StackasmRelativeIndirectIndexed0 +lblD3mod2b: CMP8 + NEXTOPCODE +OpD4mod2: +lblD4mod2: OpD4 + NEXTOPCODE +OpD5M1mod2: +lblD5mod2a: DirectIndexedX0 +lblD5mod2b: CMP8 + NEXTOPCODE +OpD6M1mod2: +lblD6mod2a: DirectIndexedX0 +lblD6mod2b: DEC8 + NEXTOPCODE +OpD7M1mod2: +lblD7mod2a: DirectIndirectIndexedLong0 +lblD7mod2b: CMP8 + NEXTOPCODE +OpD8mod2: +lblD8mod2: OpD8 + NEXTOPCODE +OpD9M1mod2: +lblD9mod2a: AbsoluteIndexedY0 +lblD9mod2b: CMP8 + NEXTOPCODE +OpDAX0mod2: +lblDAmod2: OpDAX0 + NEXTOPCODE +OpDBmod2: +lblDBmod2: OpDB + NEXTOPCODE +OpDCmod2: +lblDCmod2: OpDC + NEXTOPCODE +OpDDM1mod2: +lblDDmod2a: AbsoluteIndexedX0 +lblDDmod2b: CMP8 + NEXTOPCODE +OpDEM1mod2: +lblDEmod2a: AbsoluteIndexedX0 +lblDEmod2b: DEC8 + NEXTOPCODE +OpDFM1mod2: +lblDFmod2a: AbsoluteLongIndexedX0 +lblDFmod2b: CMP8 + NEXTOPCODE +OpE0X0mod2: +lblE0mod2: OpE0X0 + NEXTOPCODE +OpE1M1mod2: +lblE1mod2a: DirectIndexedIndirect0 +lblE1mod2b: SBC8 + NEXTOPCODE +OpE2mod2: +lblE2mod2: OpE2 + NEXTOPCODE +.pool +OpE3M1mod2: +lblE3mod2a: StackasmRelative +lblE3mod2b: SBC8 + NEXTOPCODE +OpE4X0mod2: +lblE4mod2a: Direct +lblE4mod2b: CMX16 + NEXTOPCODE +OpE5M1mod2: +lblE5mod2a: Direct +lblE5mod2b: SBC8 + NEXTOPCODE +OpE6M1mod2: +lblE6mod2a: Direct +lblE6mod2b: INC8 + NEXTOPCODE +OpE7M1mod2: +lblE7mod2a: DirectIndirectLong +lblE7mod2b: SBC8 + NEXTOPCODE +OpE8X0mod2: +lblE8mod2: OpE8X0 + NEXTOPCODE +OpE9M1mod2: +lblE9mod2a: Immediate8 +lblE9mod2b: SBC8 + NEXTOPCODE +OpEAmod2: +lblEAmod2: OpEA + NEXTOPCODE +OpEBmod2: +lblEBmod2: OpEBM1 + NEXTOPCODE +OpECX0mod2: +lblECmod2a: Absolute +lblECmod2b: CMX16 + NEXTOPCODE +OpEDM1mod2: +lblEDmod2a: Absolute +lblEDmod2b: SBC8 + NEXTOPCODE +OpEEM1mod2: +lblEEmod2a: Absolute +lblEEmod2b: INC8 + NEXTOPCODE +OpEFM1mod2: +lblEFmod2a: AbsoluteLong +lblEFmod2b: SBC8 + NEXTOPCODE +OpF0mod2: +lblF0mod2: OpF0 + NEXTOPCODE +OpF1M1mod2: +lblF1mod2a: DirectIndirectIndexed0 +lblF1mod2b: SBC8 + NEXTOPCODE +OpF2M1mod2: +lblF2mod2a: DirectIndirect +lblF2mod2b: SBC8 + NEXTOPCODE +OpF3M1mod2: +lblF3mod2a: StackasmRelativeIndirectIndexed0 +lblF3mod2b: SBC8 + NEXTOPCODE +OpF4mod2: +lblF4mod2: OpF4 + NEXTOPCODE +OpF5M1mod2: +lblF5mod2a: DirectIndexedX0 +lblF5mod2b: SBC8 + NEXTOPCODE +OpF6M1mod2: +lblF6mod2a: DirectIndexedX0 +lblF6mod2b: INC8 + NEXTOPCODE +OpF7M1mod2: +lblF7mod2a: DirectIndirectIndexedLong0 +lblF7mod2b: SBC8 + NEXTOPCODE +OpF8mod2: +lblF8mod2: OpF8 + NEXTOPCODE +OpF9M1mod2: +lblF9mod2a: AbsoluteIndexedY0 +lblF9mod2b: SBC8 + NEXTOPCODE +OpFAX0mod2: +lblFAmod2: OpFAX0 + NEXTOPCODE +OpFBmod2: +lblFBmod2: OpFB + NEXTOPCODE +OpFCmod2: +lblFCmod2: OpFCX0 + NEXTOPCODE +OpFDM1mod2: +lblFDmod2a: AbsoluteIndexedX0 +lblFDmod2b: SBC8 + NEXTOPCODE +OpFEM1mod2: +lblFEmod2a: AbsoluteIndexedX0 +lblFEmod2b: INC8 + NEXTOPCODE +OpFFM1mod2: +lblFFmod2a: AbsoluteLongIndexedX0 +lblFFmod2b: SBC8 + NEXTOPCODE + +.pool + + +jumptable3: .long Op00mod3 + .long Op01M0mod3 + .long Op02mod3 + .long Op03M0mod3 + .long Op04M0mod3 + .long Op05M0mod3 + .long Op06M0mod3 + .long Op07M0mod3 + .long Op08mod3 + .long Op09M0mod3 + .long Op0AM0mod3 + .long Op0Bmod3 + .long Op0CM0mod3 + .long Op0DM0mod3 + .long Op0EM0mod3 + .long Op0FM0mod3 + .long Op10mod3 + .long Op11M0mod3 + .long Op12M0mod3 + .long Op13M0mod3 + .long Op14M0mod3 + .long Op15M0mod3 + .long Op16M0mod3 + .long Op17M0mod3 + .long Op18mod3 + .long Op19M0mod3 + .long Op1AM0mod3 + .long Op1Bmod3 + .long Op1CM0mod3 + .long Op1DM0mod3 + .long Op1EM0mod3 + .long Op1FM0mod3 + .long Op20mod3 + .long Op21M0mod3 + .long Op22mod3 + .long Op23M0mod3 + .long Op24M0mod3 + .long Op25M0mod3 + .long Op26M0mod3 + .long Op27M0mod3 + .long Op28mod3 + .long Op29M0mod3 + .long Op2AM0mod3 + .long Op2Bmod3 + .long Op2CM0mod3 + .long Op2DM0mod3 + .long Op2EM0mod3 + .long Op2FM0mod3 + .long Op30mod3 + .long Op31M0mod3 + .long Op32M0mod3 + .long Op33M0mod3 + .long Op34M0mod3 + .long Op35M0mod3 + .long Op36M0mod3 + .long Op37M0mod3 + .long Op38mod3 + .long Op39M0mod3 + .long Op3AM0mod3 + .long Op3Bmod3 + .long Op3CM0mod3 + .long Op3DM0mod3 + .long Op3EM0mod3 + .long Op3FM0mod3 + .long Op40mod3 + .long Op41M0mod3 + .long Op42mod3 + .long Op43M0mod3 + .long Op44X0mod3 + .long Op45M0mod3 + .long Op46M0mod3 + .long Op47M0mod3 + .long Op48M0mod3 + .long Op49M0mod3 + .long Op4AM0mod3 + .long Op4Bmod3 + .long Op4Cmod3 + .long Op4DM0mod3 + .long Op4EM0mod3 + .long Op4FM0mod3 + .long Op50mod3 + .long Op51M0mod3 + .long Op52M0mod3 + .long Op53M0mod3 + .long Op54X0mod3 + .long Op55M0mod3 + .long Op56M0mod3 + .long Op57M0mod3 + .long Op58mod3 + .long Op59M0mod3 + .long Op5AX0mod3 + .long Op5Bmod3 + .long Op5Cmod3 + .long Op5DM0mod3 + .long Op5EM0mod3 + .long Op5FM0mod3 + .long Op60mod3 + .long Op61M0mod3 + .long Op62mod3 + .long Op63M0mod3 + .long Op64M0mod3 + .long Op65M0mod3 + .long Op66M0mod3 + .long Op67M0mod3 + .long Op68M0mod3 + .long Op69M0mod3 + .long Op6AM0mod3 + .long Op6Bmod3 + .long Op6Cmod3 + .long Op6DM0mod3 + .long Op6EM0mod3 + .long Op6FM0mod3 + .long Op70mod3 + .long Op71M0mod3 + .long Op72M0mod3 + .long Op73M0mod3 + .long Op74M0mod3 + .long Op75M0mod3 + .long Op76M0mod3 + .long Op77M0mod3 + .long Op78mod3 + .long Op79M0mod3 + .long Op7AX0mod3 + .long Op7Bmod3 + .long Op7Cmod3 + .long Op7DM0mod3 + .long Op7EM0mod3 + .long Op7FM0mod3 + .long Op80mod3 + .long Op81M0mod3 + .long Op82mod3 + .long Op83M0mod3 + .long Op84X0mod3 + .long Op85M0mod3 + .long Op86X0mod3 + .long Op87M0mod3 + .long Op88X0mod3 + .long Op89M0mod3 + .long Op8AM0mod3 + .long Op8Bmod3 + .long Op8CX0mod3 + .long Op8DM0mod3 + .long Op8EX0mod3 + .long Op8FM0mod3 + .long Op90mod3 + .long Op91M0mod3 + .long Op92M0mod3 + .long Op93M0mod3 + .long Op94X0mod3 + .long Op95M0mod3 + .long Op96X0mod3 + .long Op97M0mod3 + .long Op98M0mod3 + .long Op99M0mod3 + .long Op9Amod3 + .long Op9BX0mod3 + .long Op9CM0mod3 + .long Op9DM0mod3 + .long Op9EM0mod3 + .long Op9FM0mod3 + .long OpA0X0mod3 + .long OpA1M0mod3 + .long OpA2X0mod3 + .long OpA3M0mod3 + .long OpA4X0mod3 + .long OpA5M0mod3 + .long OpA6X0mod3 + .long OpA7M0mod3 + .long OpA8X0mod3 + .long OpA9M0mod3 + .long OpAAX0mod3 + .long OpABmod3 + .long OpACX0mod3 + .long OpADM0mod3 + .long OpAEX0mod3 + .long OpAFM0mod3 + .long OpB0mod3 + .long OpB1M0mod3 + .long OpB2M0mod3 + .long OpB3M0mod3 + .long OpB4X0mod3 + .long OpB5M0mod3 + .long OpB6X0mod3 + .long OpB7M0mod3 + .long OpB8mod3 + .long OpB9M0mod3 + .long OpBAX0mod3 + .long OpBBX0mod3 + .long OpBCX0mod3 + .long OpBDM0mod3 + .long OpBEX0mod3 + .long OpBFM0mod3 + .long OpC0X0mod3 + .long OpC1M0mod3 + .long OpC2mod3 + .long OpC3M0mod3 + .long OpC4X0mod3 + .long OpC5M0mod3 + .long OpC6M0mod3 + .long OpC7M0mod3 + .long OpC8X0mod3 + .long OpC9M0mod3 + .long OpCAX0mod3 + .long OpCBmod3 + .long OpCCX0mod3 + .long OpCDM0mod3 + .long OpCEM0mod3 + .long OpCFM0mod3 + .long OpD0mod3 + .long OpD1M0mod3 + .long OpD2M0mod3 + .long OpD3M0mod3 + .long OpD4mod3 + .long OpD5M0mod3 + .long OpD6M0mod3 + .long OpD7M0mod3 + .long OpD8mod3 + .long OpD9M0mod3 + .long OpDAX0mod3 + .long OpDBmod3 + .long OpDCmod3 + .long OpDDM0mod3 + .long OpDEM0mod3 + .long OpDFM0mod3 + .long OpE0X0mod3 + .long OpE1M0mod3 + .long OpE2mod3 + .long OpE3M0mod3 + .long OpE4X0mod3 + .long OpE5M0mod3 + .long OpE6M0mod3 + .long OpE7M0mod3 + .long OpE8X0mod3 + .long OpE9M0mod3 + .long OpEAmod3 + .long OpEBmod3 + .long OpECX0mod3 + .long OpEDM0mod3 + .long OpEEM0mod3 + .long OpEFM0mod3 + .long OpF0mod3 + .long OpF1M0mod3 + .long OpF2M0mod3 + .long OpF3M0mod3 + .long OpF4mod3 + .long OpF5M0mod3 + .long OpF6M0mod3 + .long OpF7M0mod3 + .long OpF8mod3 + .long OpF9M0mod3 + .long OpFAX0mod3 + .long OpFBmod3 + .long OpFCmod3 + .long OpFDM0mod3 + .long OpFEM0mod3 + .long OpFFM0mod3 +Op00mod3: +lbl00mod3: Op00 + NEXTOPCODE +Op01M0mod3: +lbl01mod3a: DirectIndexedIndirect0 +lbl01mod3b: ORA16 + NEXTOPCODE +Op02mod3: +lbl02mod3: Op02 + NEXTOPCODE +Op03M0mod3: +lbl03mod3a: StackasmRelative +lbl03mod3b: ORA16 + NEXTOPCODE +Op04M0mod3: +lbl04mod3a: Direct +lbl04mod3b: TSB16 + NEXTOPCODE +Op05M0mod3: +lbl05mod3a: Direct +lbl05mod3b: ORA16 + NEXTOPCODE +Op06M0mod3: +lbl06mod3a: Direct +lbl06mod3b: ASL16 + NEXTOPCODE +Op07M0mod3: +lbl07mod3a: DirectIndirectLong +lbl07mod3b: ORA16 + NEXTOPCODE +Op08mod3: +lbl08mod3: Op08 + NEXTOPCODE +Op09M0mod3: +lbl09mod3: Op09M0 + NEXTOPCODE +Op0AM0mod3: +lbl0Amod3a: A_ASL16 + NEXTOPCODE +Op0Bmod3: +lbl0Bmod3: Op0B + NEXTOPCODE +Op0CM0mod3: +lbl0Cmod3a: Absolute +lbl0Cmod3b: TSB16 + NEXTOPCODE +Op0DM0mod3: +lbl0Dmod3a: Absolute +lbl0Dmod3b: ORA16 + NEXTOPCODE +Op0EM0mod3: +lbl0Emod3a: Absolute +lbl0Emod3b: ASL16 + NEXTOPCODE +Op0FM0mod3: +lbl0Fmod3a: AbsoluteLong +lbl0Fmod3b: ORA16 + NEXTOPCODE +Op10mod3: +lbl10mod3: Op10 + NEXTOPCODE +Op11M0mod3: +lbl11mod3a: DirectIndirectIndexed0 +lbl11mod3b: ORA16 + NEXTOPCODE +Op12M0mod3: +lbl12mod3a: DirectIndirect +lbl12mod3b: ORA16 + NEXTOPCODE +Op13M0mod3: +lbl13mod3a: StackasmRelativeIndirectIndexed0 +lbl13mod3b: ORA16 + NEXTOPCODE +Op14M0mod3: +lbl14mod3a: Direct +lbl14mod3b: TRB16 + NEXTOPCODE +Op15M0mod3: +lbl15mod3a: DirectIndexedX0 +lbl15mod3b: ORA16 + NEXTOPCODE +Op16M0mod3: +lbl16mod3a: DirectIndexedX0 +lbl16mod3b: ASL16 + NEXTOPCODE +Op17M0mod3: +lbl17mod3a: DirectIndirectIndexedLong0 +lbl17mod3b: ORA16 + NEXTOPCODE +Op18mod3: +lbl18mod3: Op18 + NEXTOPCODE +Op19M0mod3: +lbl19mod3a: AbsoluteIndexedY0 +lbl19mod3b: ORA16 + NEXTOPCODE +Op1AM0mod3: +lbl1Amod3a: A_INC16 + NEXTOPCODE +Op1Bmod3: +lbl1Bmod3: Op1BM0 + NEXTOPCODE +Op1CM0mod3: +lbl1Cmod3a: Absolute +lbl1Cmod3b: TRB16 + NEXTOPCODE +Op1DM0mod3: +lbl1Dmod3a: AbsoluteIndexedX0 +lbl1Dmod3b: ORA16 + NEXTOPCODE +Op1EM0mod3: +lbl1Emod3a: AbsoluteIndexedX0 +lbl1Emod3b: ASL16 + NEXTOPCODE +Op1FM0mod3: +lbl1Fmod3a: AbsoluteLongIndexedX0 +lbl1Fmod3b: ORA16 + NEXTOPCODE +Op20mod3: +lbl20mod3: Op20 + NEXTOPCODE +Op21M0mod3: +lbl21mod3a: DirectIndexedIndirect0 +lbl21mod3b: AND16 + NEXTOPCODE +Op22mod3: +lbl22mod3: Op22 + NEXTOPCODE +Op23M0mod3: +lbl23mod3a: StackasmRelative +lbl23mod3b: AND16 + NEXTOPCODE +Op24M0mod3: +lbl24mod3a: Direct +lbl24mod3b: BIT16 + NEXTOPCODE +Op25M0mod3: +lbl25mod3a: Direct +lbl25mod3b: AND16 + NEXTOPCODE +Op26M0mod3: +lbl26mod3a: Direct +lbl26mod3b: ROL16 + NEXTOPCODE +Op27M0mod3: +lbl27mod3a: DirectIndirectLong + +lbl27mod3b: AND16 + NEXTOPCODE +Op28mod3: +lbl28mod3: Op28X0M0 + NEXTOPCODE +.pool +Op29M0mod3: +lbl29mod3: Op29M0 + NEXTOPCODE +Op2AM0mod3: +lbl2Amod3a: A_ROL16 + NEXTOPCODE +Op2Bmod3: +lbl2Bmod3: Op2B + NEXTOPCODE +Op2CM0mod3: +lbl2Cmod3a: Absolute +lbl2Cmod3b: BIT16 + NEXTOPCODE +Op2DM0mod3: +lbl2Dmod3a: Absolute +lbl2Dmod3b: AND16 + NEXTOPCODE +Op2EM0mod3: +lbl2Emod3a: Absolute +lbl2Emod3b: ROL16 + NEXTOPCODE +Op2FM0mod3: +lbl2Fmod3a: AbsoluteLong +lbl2Fmod3b: AND16 + NEXTOPCODE +Op30mod3: +lbl30mod3: Op30 + NEXTOPCODE +Op31M0mod3: +lbl31mod3a: DirectIndirectIndexed0 +lbl31mod3b: AND16 + NEXTOPCODE +Op32M0mod3: +lbl32mod3a: DirectIndirect +lbl32mod3b: AND16 + NEXTOPCODE +Op33M0mod3: +lbl33mod3a: StackasmRelativeIndirectIndexed0 +lbl33mod3b: AND16 + NEXTOPCODE +Op34M0mod3: +lbl34mod3a: DirectIndexedX0 +lbl34mod3b: BIT16 + NEXTOPCODE +Op35M0mod3: +lbl35mod3a: DirectIndexedX0 +lbl35mod3b: AND16 + NEXTOPCODE +Op36M0mod3: +lbl36mod3a: DirectIndexedX0 +lbl36mod3b: ROL16 + NEXTOPCODE +Op37M0mod3: +lbl37mod3a: DirectIndirectIndexedLong0 +lbl37mod3b: AND16 + NEXTOPCODE +Op38mod3: +lbl38mod3: Op38 + NEXTOPCODE +Op39M0mod3: +lbl39mod3a: AbsoluteIndexedY0 +lbl39mod3b: AND16 + NEXTOPCODE +Op3AM0mod3: +lbl3Amod3a: A_DEC16 + NEXTOPCODE +Op3Bmod3: +lbl3Bmod3: Op3BM0 + NEXTOPCODE +Op3CM0mod3: +lbl3Cmod3a: AbsoluteIndexedX0 +lbl3Cmod3b: BIT16 + NEXTOPCODE +Op3DM0mod3: +lbl3Dmod3a: AbsoluteIndexedX0 +lbl3Dmod3b: AND16 + NEXTOPCODE +Op3EM0mod3: +lbl3Emod3a: AbsoluteIndexedX0 +lbl3Emod3b: ROL16 + NEXTOPCODE +Op3FM0mod3: +lbl3Fmod3a: AbsoluteLongIndexedX0 +lbl3Fmod3b: AND16 + NEXTOPCODE +Op40mod3: +lbl40mod3: Op40X0M0 + NEXTOPCODE +.pool +Op41M0mod3: +lbl41mod3a: DirectIndexedIndirect0 +lbl41mod3b: EOR16 + NEXTOPCODE +Op42mod3: +lbl42mod3: Op42 + NEXTOPCODE +Op43M0mod3: +lbl43mod3a: StackasmRelative +lbl43mod3b: EOR16 + NEXTOPCODE +Op44X0mod3: +lbl44mod3: Op44X0M0 + NEXTOPCODE +Op45M0mod3: +lbl45mod3a: Direct +lbl45mod3b: EOR16 + NEXTOPCODE +Op46M0mod3: +lbl46mod3a: Direct +lbl46mod3b: LSR16 + NEXTOPCODE +Op47M0mod3: +lbl47mod3a: DirectIndirectLong +lbl47mod3b: EOR16 + NEXTOPCODE +Op48M0mod3: +lbl48mod3: Op48M0 + NEXTOPCODE +Op49M0mod3: +lbl49mod3: Op49M0 + NEXTOPCODE +Op4AM0mod3: +lbl4Amod3a: A_LSR16 + NEXTOPCODE +Op4Bmod3: +lbl4Bmod3: Op4B + NEXTOPCODE +Op4Cmod3: +lbl4Cmod3: Op4C + NEXTOPCODE +Op4DM0mod3: +lbl4Dmod3a: Absolute +lbl4Dmod3b: EOR16 + NEXTOPCODE +Op4EM0mod3: +lbl4Emod3a: Absolute +lbl4Emod3b: LSR16 + NEXTOPCODE +Op4FM0mod3: +lbl4Fmod3a: AbsoluteLong +lbl4Fmod3b: EOR16 + NEXTOPCODE +Op50mod3: +lbl50mod3: Op50 + NEXTOPCODE +Op51M0mod3: +lbl51mod3a: DirectIndirectIndexed0 +lbl51mod3b: EOR16 + NEXTOPCODE +Op52M0mod3: +lbl52mod3a: DirectIndirect +lbl52mod3b: EOR16 + NEXTOPCODE +Op53M0mod3: +lbl53mod3a: StackasmRelativeIndirectIndexed0 +lbl53mod3b: EOR16 + NEXTOPCODE +Op54X0mod3: +lbl54mod3: Op54X0M0 + NEXTOPCODE +Op55M0mod3: +lbl55mod3a: DirectIndexedX0 +lbl55mod3b: EOR16 + NEXTOPCODE +Op56M0mod3: +lbl56mod3a: DirectIndexedX0 +lbl56mod3b: LSR16 + NEXTOPCODE +Op57M0mod3: +lbl57mod3a: DirectIndirectIndexedLong0 +lbl57mod3b: EOR16 + NEXTOPCODE +Op58mod3: +lbl58mod3: Op58 + NEXTOPCODE +Op59M0mod3: +lbl59mod3a: AbsoluteIndexedY0 +lbl59mod3b: EOR16 + NEXTOPCODE +Op5AX0mod3: +lbl5Amod3: Op5AX0 + NEXTOPCODE +Op5Bmod3: +lbl5Bmod3: Op5BM0 + NEXTOPCODE +Op5Cmod3: +lbl5Cmod3: Op5C + NEXTOPCODE +Op5DM0mod3: +lbl5Dmod3a: AbsoluteIndexedX0 +lbl5Dmod3b: EOR16 + NEXTOPCODE +Op5EM0mod3: +lbl5Emod3a: AbsoluteIndexedX0 +lbl5Emod3b: LSR16 + NEXTOPCODE +Op5FM0mod3: +lbl5Fmod3a: AbsoluteLongIndexedX0 +lbl5Fmod3b: EOR16 + NEXTOPCODE +Op60mod3: +lbl60mod3: Op60 + NEXTOPCODE +Op61M0mod3: +lbl61mod3a: DirectIndexedIndirect0 +lbl61mod3b: ADC16 + NEXTOPCODE +Op62mod3: +lbl62mod3: Op62 + NEXTOPCODE +Op63M0mod3: +lbl63mod3a: StackasmRelative +lbl63mod3b: ADC16 + NEXTOPCODE +.pool +Op64M0mod3: +lbl64mod3a: Direct +lbl64mod3b: STZ16 + NEXTOPCODE +Op65M0mod3: +lbl65mod3a: Direct +lbl65mod3b: ADC16 + NEXTOPCODE +.pool +Op66M0mod3: +lbl66mod3a: Direct +lbl66mod3b: ROR16 + NEXTOPCODE +Op67M0mod3: +lbl67mod3a: DirectIndirectLong +lbl67mod3b: ADC16 + NEXTOPCODE +.pool +Op68M0mod3: +lbl68mod3: Op68M0 + NEXTOPCODE +Op69M0mod3: +lbl69mod3a: Immediate16 +lbl69mod3b: ADC16 + NEXTOPCODE +.pool +Op6AM0mod3: +lbl6Amod3a: A_ROR16 + NEXTOPCODE +Op6Bmod3: +lbl6Bmod3: Op6B + NEXTOPCODE +Op6Cmod3: +lbl6Cmod3: Op6C + NEXTOPCODE +Op6DM0mod3: +lbl6Dmod3a: Absolute +lbl6Dmod3b: ADC16 + NEXTOPCODE +Op6EM0mod3: +lbl6Emod3a: Absolute +lbl6Emod3b: ROR16 + NEXTOPCODE +Op6FM0mod3: +lbl6Fmod3a: AbsoluteLong +lbl6Fmod3b: ADC16 + NEXTOPCODE +Op70mod3: +lbl70mod3: Op70 + NEXTOPCODE +Op71M0mod3: +lbl71mod3a: DirectIndirectIndexed0 +lbl71mod3b: ADC16 + NEXTOPCODE +Op72M0mod3: +lbl72mod3a: DirectIndirect +lbl72mod3b: ADC16 + NEXTOPCODE +Op73M0mod3: +lbl73mod3a: StackasmRelativeIndirectIndexed0 +lbl73mod3b: ADC16 + NEXTOPCODE +.pool +Op74M0mod3: +lbl74mod3a: DirectIndexedX0 +lbl74mod3b: STZ16 + NEXTOPCODE +Op75M0mod3: +lbl75mod3a: DirectIndexedX0 +lbl75mod3b: ADC16 + NEXTOPCODE +.pool +Op76M0mod3: +lbl76mod3a: DirectIndexedX0 +lbl76mod3b: ROR16 + NEXTOPCODE +Op77M0mod3: +lbl77mod3a: DirectIndirectIndexedLong0 +lbl77mod3b: ADC16 + NEXTOPCODE +Op78mod3: +lbl78mod3: Op78 + NEXTOPCODE +Op79M0mod3: +lbl79mod3a: AbsoluteIndexedY0 +lbl79mod3b: ADC16 + NEXTOPCODE +Op7AX0mod3: +lbl7Amod3: Op7AX0 + NEXTOPCODE +Op7Bmod3: +lbl7Bmod3: Op7BM0 + NEXTOPCODE +Op7Cmod3: +lbl7Cmod3: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE +Op7DM0mod3: +lbl7Dmod3a: AbsoluteIndexedX0 +lbl7Dmod3b: ADC16 + NEXTOPCODE +Op7EM0mod3: +lbl7Emod3a: AbsoluteIndexedX0 +lbl7Emod3b: ROR16 + NEXTOPCODE +Op7FM0mod3: +lbl7Fmod3a: AbsoluteLongIndexedX0 +lbl7Fmod3b: ADC16 + NEXTOPCODE +.pool +Op80mod3: +lbl80mod3: Op80 + NEXTOPCODE +Op81M0mod3: +lbl81mod3a: DirectIndexedIndirect0 +lbl81mod3b: Op81M0 + NEXTOPCODE +Op82mod3: +lbl82mod3: Op82 + NEXTOPCODE +Op83M0mod3: +lbl83mod3a: StackasmRelative +lbl83mod3b: STA16 + NEXTOPCODE +Op84X0mod3: +lbl84mod3a: Direct +lbl84mod3b: STY16 + NEXTOPCODE +Op85M0mod3: +lbl85mod3a: Direct +lbl85mod3b: STA16 + NEXTOPCODE +Op86X0mod3: +lbl86mod3a: Direct +lbl86mod3b: STX16 + NEXTOPCODE +Op87M0mod3: +lbl87mod3a: DirectIndirectLong +lbl87mod3b: STA16 + NEXTOPCODE +Op88X0mod3: +lbl88mod3: Op88X0 + NEXTOPCODE +Op89M0mod3: +lbl89mod3: Op89M0 + NEXTOPCODE +Op8AM0mod3: +lbl8Amod3: Op8AM0X0 + NEXTOPCODE +Op8Bmod3: +lbl8Bmod3: Op8B + NEXTOPCODE +Op8CX0mod3: +lbl8Cmod3a: Absolute +lbl8Cmod3b: STY16 + NEXTOPCODE +Op8DM0mod3: +lbl8Dmod3a: Absolute +lbl8Dmod3b: STA16 + NEXTOPCODE +Op8EX0mod3: +lbl8Emod3a: Absolute +lbl8Emod3b: STX16 + NEXTOPCODE +Op8FM0mod3: +lbl8Fmod3a: AbsoluteLong +lbl8Fmod3b: STA16 + NEXTOPCODE +Op90mod3: +lbl90mod3: Op90 + NEXTOPCODE +Op91M0mod3: +lbl91mod3a: DirectIndirectIndexed0 +lbl91mod3b: STA16 + NEXTOPCODE +Op92M0mod3: +lbl92mod3a: DirectIndirect +lbl92mod3b: STA16 + NEXTOPCODE +Op93M0mod3: +lbl93mod3a: StackasmRelativeIndirectIndexed0 +lbl93mod3b: STA16 + NEXTOPCODE +Op94X0mod3: +lbl94mod3a: DirectIndexedX0 +lbl94mod3b: STY16 + NEXTOPCODE +Op95M0mod3: +lbl95mod3a: DirectIndexedX0 +lbl95mod3b: STA16 + NEXTOPCODE +Op96X0mod3: +lbl96mod3a: DirectIndexedY0 +lbl96mod3b: STX16 + NEXTOPCODE +Op97M0mod3: +lbl97mod3a: DirectIndirectIndexedLong0 +lbl97mod3b: STA16 + NEXTOPCODE +Op98M0mod3: +lbl98mod3: Op98M0X0 + NEXTOPCODE +Op99M0mod3: +lbl99mod3a: AbsoluteIndexedY0 +lbl99mod3b: STA16 + NEXTOPCODE +Op9Amod3: +lbl9Amod3: Op9AX0 + NEXTOPCODE +Op9BX0mod3: +lbl9Bmod3: Op9BX0 + NEXTOPCODE +Op9CM0mod3: +lbl9Cmod3a: Absolute +lbl9Cmod3b: STZ16 + NEXTOPCODE +Op9DM0mod3: +lbl9Dmod3a: AbsoluteIndexedX0 +lbl9Dmod3b: STA16 + NEXTOPCODE +Op9EM0mod3: +lbl9Emod3: AbsoluteIndexedX0 + STZ16 + NEXTOPCODE +Op9FM0mod3: +lbl9Fmod3a: AbsoluteLongIndexedX0 +lbl9Fmod3b: STA16 + NEXTOPCODE +OpA0X0mod3: +lblA0mod3: OpA0X0 + NEXTOPCODE +OpA1M0mod3: +lblA1mod3a: DirectIndexedIndirect0 +lblA1mod3b: LDA16 + NEXTOPCODE +OpA2X0mod3: +lblA2mod3: OpA2X0 + NEXTOPCODE +OpA3M0mod3: +lblA3mod3a: StackasmRelative +lblA3mod3b: LDA16 + NEXTOPCODE +OpA4X0mod3: +lblA4mod3a: Direct +lblA4mod3b: LDY16 + NEXTOPCODE +OpA5M0mod3: +lblA5mod3a: Direct +lblA5mod3b: LDA16 + NEXTOPCODE +OpA6X0mod3: +lblA6mod3a: Direct +lblA6mod3b: LDX16 + NEXTOPCODE +OpA7M0mod3: +lblA7mod3a: DirectIndirectLong +lblA7mod3b: LDA16 + NEXTOPCODE +OpA8X0mod3: +lblA8mod3: OpA8X0M0 + NEXTOPCODE +OpA9M0mod3: +lblA9mod3: OpA9M0 + NEXTOPCODE +OpAAX0mod3: +lblAAmod3: OpAAX0M0 + NEXTOPCODE +OpABmod3: +lblABmod3: OpAB + NEXTOPCODE +OpACX0mod3: +lblACmod3a: Absolute +lblACmod3b: LDY16 + NEXTOPCODE +OpADM0mod3: +lblADmod3a: Absolute +lblADmod3b: LDA16 + NEXTOPCODE +OpAEX0mod3: +lblAEmod3a: Absolute +lblAEmod3b: LDX16 + NEXTOPCODE +OpAFM0mod3: +lblAFmod3a: AbsoluteLong +lblAFmod3b: LDA16 + NEXTOPCODE +OpB0mod3: +lblB0mod3: OpB0 + NEXTOPCODE +OpB1M0mod3: +lblB1mod3a: DirectIndirectIndexed0 +lblB1mod3b: LDA16 + NEXTOPCODE +OpB2M0mod3: +lblB2mod3a: DirectIndirect +lblB2mod3b: LDA16 + NEXTOPCODE +OpB3M0mod3: +lblB3mod3a: StackasmRelativeIndirectIndexed0 +lblB3mod3b: LDA16 + NEXTOPCODE +OpB4X0mod3: +lblB4mod3a: DirectIndexedX0 +lblB4mod3b: LDY16 + NEXTOPCODE +OpB5M0mod3: +lblB5mod3a: DirectIndexedX0 +lblB5mod3b: LDA16 + NEXTOPCODE +OpB6X0mod3: +lblB6mod3a: DirectIndexedY0 +lblB6mod3b: LDX16 + NEXTOPCODE +OpB7M0mod3: +lblB7mod3a: DirectIndirectIndexedLong0 +lblB7mod3b: LDA16 + NEXTOPCODE +OpB8mod3: +lblB8mod3: OpB8 + NEXTOPCODE +OpB9M0mod3: +lblB9mod3a: AbsoluteIndexedY0 +lblB9mod3b: LDA16 + NEXTOPCODE +OpBAX0mod3: +lblBAmod3: OpBAX0 + NEXTOPCODE +OpBBX0mod3: +lblBBmod3: OpBBX0 + NEXTOPCODE +OpBCX0mod3: +lblBCmod3a: AbsoluteIndexedX0 +lblBCmod3b: LDY16 + NEXTOPCODE +OpBDM0mod3: +lblBDmod3a: AbsoluteIndexedX0 +lblBDmod3b: LDA16 + NEXTOPCODE +OpBEX0mod3: +lblBEmod3a: AbsoluteIndexedY0 +lblBEmod3b: LDX16 + NEXTOPCODE +OpBFM0mod3: +lblBFmod3a: AbsoluteLongIndexedX0 +lblBFmod3b: LDA16 + NEXTOPCODE +OpC0X0mod3: +lblC0mod3: OpC0X0 + NEXTOPCODE +OpC1M0mod3: +lblC1mod3a: DirectIndexedIndirect0 +lblC1mod3b: CMP16 + NEXTOPCODE +OpC2mod3: +lblC2mod3: OpC2 + NEXTOPCODE +.pool +OpC3M0mod3: +lblC3mod3a: StackasmRelative +lblC3mod3b: CMP16 + NEXTOPCODE +OpC4X0mod3: +lblC4mod3a: Direct +lblC4mod3b: CMY16 + NEXTOPCODE +OpC5M0mod3: +lblC5mod3a: Direct +lblC5mod3b: CMP16 + NEXTOPCODE +OpC6M0mod3: +lblC6mod3a: Direct +lblC6mod3b: DEC16 + NEXTOPCODE +OpC7M0mod3: +lblC7mod3a: DirectIndirectLong +lblC7mod3b: CMP16 + NEXTOPCODE +OpC8X0mod3: +lblC8mod3: OpC8X0 + NEXTOPCODE +OpC9M0mod3: +lblC9mod3: OpC9M0 + NEXTOPCODE +OpCAX0mod3: +lblCAmod3: OpCAX0 + NEXTOPCODE +OpCBmod3: +lblCBmod3: OpCB + NEXTOPCODE +OpCCX0mod3: +lblCCmod3a: Absolute +lblCCmod3b: CMY16 + NEXTOPCODE +OpCDM0mod3: +lblCDmod3a: Absolute +lblCDmod3b: CMP16 + NEXTOPCODE +OpCEM0mod3: +lblCEmod3a: Absolute +lblCEmod3b: DEC16 + NEXTOPCODE +OpCFM0mod3: +lblCFmod3a: AbsoluteLong +lblCFmod3b: CMP16 + NEXTOPCODE +OpD0mod3: +lblD0mod3: OpD0 + NEXTOPCODE +OpD1M0mod3: +lblD1mod3a: DirectIndirectIndexed0 +lblD1mod3b: CMP16 + NEXTOPCODE +OpD2M0mod3: +lblD2mod3a: DirectIndirect +lblD2mod3b: CMP16 + NEXTOPCODE +OpD3M0mod3: +lblD3mod3a: StackasmRelativeIndirectIndexed0 +lblD3mod3b: CMP16 + NEXTOPCODE +OpD4mod3: +lblD4mod3: OpD4 + NEXTOPCODE +OpD5M0mod3: +lblD5mod3a: DirectIndexedX0 +lblD5mod3b: CMP16 + NEXTOPCODE +OpD6M0mod3: +lblD6mod3a: DirectIndexedX0 +lblD6mod3b: DEC16 + NEXTOPCODE +OpD7M0mod3: +lblD7mod3a: DirectIndirectIndexedLong0 +lblD7mod3b: CMP16 + NEXTOPCODE +OpD8mod3: +lblD8mod3: OpD8 + NEXTOPCODE +OpD9M0mod3: +lblD9mod3a: AbsoluteIndexedY0 +lblD9mod3b: CMP16 + NEXTOPCODE +OpDAX0mod3: +lblDAmod3: OpDAX0 + NEXTOPCODE +OpDBmod3: +lblDBmod3: OpDB + NEXTOPCODE +OpDCmod3: +lblDCmod3: OpDC + NEXTOPCODE +OpDDM0mod3: +lblDDmod3a: AbsoluteIndexedX0 +lblDDmod3b: CMP16 + NEXTOPCODE +OpDEM0mod3: +lblDEmod3a: AbsoluteIndexedX0 +lblDEmod3b: DEC16 + NEXTOPCODE +OpDFM0mod3: +lblDFmod3a: AbsoluteLongIndexedX0 +lblDFmod3b: CMP16 + NEXTOPCODE +OpE0X0mod3: +lblE0mod3: OpE0X0 + NEXTOPCODE +OpE1M0mod3: +lblE1mod3a: DirectIndexedIndirect0 +lblE1mod3b: SBC16 + NEXTOPCODE +OpE2mod3: +lblE2mod3: OpE2 + NEXTOPCODE +.pool +OpE3M0mod3: +lblE3mod3a: StackasmRelative +lblE3mod3b: SBC16 + NEXTOPCODE +OpE4X0mod3: +lblE4mod3a: Direct +lblE4mod3b: CMX16 + NEXTOPCODE +OpE5M0mod3: +lblE5mod3a: Direct +lblE5mod3b: SBC16 + NEXTOPCODE +OpE6M0mod3: +lblE6mod3a: Direct +lblE6mod3b: INC16 + NEXTOPCODE +OpE7M0mod3: +lblE7mod3a: DirectIndirectLong +lblE7mod3b: SBC16 + NEXTOPCODE +OpE8X0mod3: +lblE8mod3: OpE8X0 + NEXTOPCODE +OpE9M0mod3: +lblE9mod3a: Immediate16 +lblE9mod3b: SBC16 + NEXTOPCODE +OpEAmod3: +lblEAmod3: OpEA + NEXTOPCODE +OpEBmod3: +lblEBmod3: OpEBM0 + NEXTOPCODE +OpECX0mod3: +lblECmod3a: Absolute +lblECmod3b: CMX16 + NEXTOPCODE +OpEDM0mod3: +lblEDmod3a: Absolute +lblEDmod3b: SBC16 + NEXTOPCODE +OpEEM0mod3: +lblEEmod3a: Absolute +lblEEmod3b: INC16 + NEXTOPCODE +OpEFM0mod3: +lblEFmod3a: AbsoluteLong +lblEFmod3b: SBC16 + NEXTOPCODE +OpF0mod3: +lblF0mod3: OpF0 + NEXTOPCODE +OpF1M0mod3: +lblF1mod3a: DirectIndirectIndexed0 +lblF1mod3b: SBC16 + NEXTOPCODE +OpF2M0mod3: +lblF2mod3a: DirectIndirect +lblF2mod3b: SBC16 + NEXTOPCODE +OpF3M0mod3: +lblF3mod3a: StackasmRelativeIndirectIndexed0 +lblF3mod3b: SBC16 + NEXTOPCODE +OpF4mod3: +lblF4mod3: OpF4 + NEXTOPCODE +OpF5M0mod3: +lblF5mod3a: DirectIndexedX0 +lblF5mod3b: SBC16 + NEXTOPCODE +OpF6M0mod3: +lblF6mod3a: DirectIndexedX0 +lblF6mod3b: INC16 + NEXTOPCODE +OpF7M0mod3: +lblF7mod3a: DirectIndirectIndexedLong0 +lblF7mod3b: SBC16 + NEXTOPCODE +OpF8mod3: +lblF8mod3: OpF8 + NEXTOPCODE +OpF9M0mod3: +lblF9mod3a: AbsoluteIndexedY0 +lblF9mod3b: SBC16 + NEXTOPCODE +OpFAX0mod3: +lblFAmod3: OpFAX0 + NEXTOPCODE +OpFBmod3: +lblFBmod3: OpFB + NEXTOPCODE +OpFCmod3: +lblFCmod3: OpFCX0 + NEXTOPCODE +OpFDM0mod3: +lblFDmod3a: AbsoluteIndexedX0 +lblFDmod3b: SBC16 + NEXTOPCODE +OpFEM0mod3: +lblFEmod3a: AbsoluteIndexedX0 +lblFEmod3b: INC16 + NEXTOPCODE +OpFFM0mod3: +lblFFmod3a: AbsoluteLongIndexedX0 +lblFFmod3b: SBC16 + NEXTOPCODE +.pool + +jumptable4: .long Op00mod4 + .long Op01M0mod4 + .long Op02mod4 + .long Op03M0mod4 + .long Op04M0mod4 + .long Op05M0mod4 + .long Op06M0mod4 + .long Op07M0mod4 + .long Op08mod4 + .long Op09M0mod4 + .long Op0AM0mod4 + .long Op0Bmod4 + .long Op0CM0mod4 + .long Op0DM0mod4 + .long Op0EM0mod4 + .long Op0FM0mod4 + .long Op10mod4 + .long Op11M0mod4 + .long Op12M0mod4 + .long Op13M0mod4 + .long Op14M0mod4 + .long Op15M0mod4 + .long Op16M0mod4 + .long Op17M0mod4 + .long Op18mod4 + .long Op19M0mod4 + .long Op1AM0mod4 + .long Op1Bmod4 + .long Op1CM0mod4 + .long Op1DM0mod4 + .long Op1EM0mod4 + .long Op1FM0mod4 + .long Op20mod4 + .long Op21M0mod4 + .long Op22mod4 + .long Op23M0mod4 + .long Op24M0mod4 + .long Op25M0mod4 + .long Op26M0mod4 + .long Op27M0mod4 + .long Op28mod4 + .long Op29M0mod4 + .long Op2AM0mod4 + .long Op2Bmod4 + .long Op2CM0mod4 + .long Op2DM0mod4 + .long Op2EM0mod4 + .long Op2FM0mod4 + .long Op30mod4 + .long Op31M0mod4 + .long Op32M0mod4 + .long Op33M0mod4 + .long Op34M0mod4 + .long Op35M0mod4 + .long Op36M0mod4 + .long Op37M0mod4 + .long Op38mod4 + .long Op39M0mod4 + .long Op3AM0mod4 + .long Op3Bmod4 + .long Op3CM0mod4 + .long Op3DM0mod4 + .long Op3EM0mod4 + .long Op3FM0mod4 + .long Op40mod4 + .long Op41M0mod4 + .long Op42mod4 + .long Op43M0mod4 + .long Op44X1mod4 + .long Op45M0mod4 + .long Op46M0mod4 + .long Op47M0mod4 + .long Op48M0mod4 + .long Op49M0mod4 + .long Op4AM0mod4 + .long Op4Bmod4 + .long Op4Cmod4 + .long Op4DM0mod4 + .long Op4EM0mod4 + .long Op4FM0mod4 + .long Op50mod4 + .long Op51M0mod4 + .long Op52M0mod4 + .long Op53M0mod4 + .long Op54X1mod4 + .long Op55M0mod4 + .long Op56M0mod4 + .long Op57M0mod4 + .long Op58mod4 + .long Op59M0mod4 + .long Op5AX1mod4 + .long Op5Bmod4 + .long Op5Cmod4 + .long Op5DM0mod4 + .long Op5EM0mod4 + .long Op5FM0mod4 + .long Op60mod4 + .long Op61M0mod4 + .long Op62mod4 + .long Op63M0mod4 + .long Op64M0mod4 + .long Op65M0mod4 + .long Op66M0mod4 + .long Op67M0mod4 + .long Op68M0mod4 + .long Op69M0mod4 + .long Op6AM0mod4 + .long Op6Bmod4 + .long Op6Cmod4 + .long Op6DM0mod4 + .long Op6EM0mod4 + .long Op6FM0mod4 + .long Op70mod4 + .long Op71M0mod4 + .long Op72M0mod4 + .long Op73M0mod4 + .long Op74M0mod4 + .long Op75M0mod4 + .long Op76M0mod4 + .long Op77M0mod4 + .long Op78mod4 + .long Op79M0mod4 + .long Op7AX1mod4 + .long Op7Bmod4 + .long Op7Cmod4 + .long Op7DM0mod4 + .long Op7EM0mod4 + .long Op7FM0mod4 + .long Op80mod4 + .long Op81M0mod4 + .long Op82mod4 + .long Op83M0mod4 + .long Op84X1mod4 + .long Op85M0mod4 + .long Op86X1mod4 + .long Op87M0mod4 + .long Op88X1mod4 + .long Op89M0mod4 + .long Op8AM0mod4 + .long Op8Bmod4 + .long Op8CX1mod4 + .long Op8DM0mod4 + .long Op8EX1mod4 + .long Op8FM0mod4 + .long Op90mod4 + .long Op91M0mod4 + .long Op92M0mod4 + .long Op93M0mod4 + .long Op94X1mod4 + .long Op95M0mod4 + .long Op96X1mod4 + .long Op97M0mod4 + .long Op98M0mod4 + .long Op99M0mod4 + .long Op9Amod4 + .long Op9BX1mod4 + .long Op9CM0mod4 + .long Op9DM0mod4 + + .long Op9EM0mod4 + .long Op9FM0mod4 + .long OpA0X1mod4 + .long OpA1M0mod4 + .long OpA2X1mod4 + .long OpA3M0mod4 + .long OpA4X1mod4 + .long OpA5M0mod4 + .long OpA6X1mod4 + .long OpA7M0mod4 + .long OpA8X1mod4 + .long OpA9M0mod4 + .long OpAAX1mod4 + .long OpABmod4 + .long OpACX1mod4 + .long OpADM0mod4 + .long OpAEX1mod4 + .long OpAFM0mod4 + .long OpB0mod4 + .long OpB1M0mod4 + .long OpB2M0mod4 + .long OpB3M0mod4 + .long OpB4X1mod4 + .long OpB5M0mod4 + .long OpB6X1mod4 + .long OpB7M0mod4 + .long OpB8mod4 + .long OpB9M0mod4 + .long OpBAX1mod4 + .long OpBBX1mod4 + .long OpBCX1mod4 + .long OpBDM0mod4 + .long OpBEX1mod4 + .long OpBFM0mod4 + .long OpC0X1mod4 + .long OpC1M0mod4 + .long OpC2mod4 + .long OpC3M0mod4 + .long OpC4X1mod4 + .long OpC5M0mod4 + .long OpC6M0mod4 + .long OpC7M0mod4 + .long OpC8X1mod4 + .long OpC9M0mod4 + .long OpCAX1mod4 + .long OpCBmod4 + .long OpCCX1mod4 + .long OpCDM0mod4 + .long OpCEM0mod4 + .long OpCFM0mod4 + .long OpD0mod4 + .long OpD1M0mod4 + .long OpD2M0mod4 + .long OpD3M0mod4 + .long OpD4mod4 + .long OpD5M0mod4 + .long OpD6M0mod4 + .long OpD7M0mod4 + .long OpD8mod4 + .long OpD9M0mod4 + .long OpDAX1mod4 + .long OpDBmod4 + .long OpDCmod4 + .long OpDDM0mod4 + .long OpDEM0mod4 + .long OpDFM0mod4 + .long OpE0X1mod4 + .long OpE1M0mod4 + .long OpE2mod4 + .long OpE3M0mod4 + .long OpE4X1mod4 + .long OpE5M0mod4 + .long OpE6M0mod4 + .long OpE7M0mod4 + .long OpE8X1mod4 + .long OpE9M0mod4 + .long OpEAmod4 + .long OpEBmod4 + .long OpECX1mod4 + .long OpEDM0mod4 + .long OpEEM0mod4 + .long OpEFM0mod4 + .long OpF0mod4 + .long OpF1M0mod4 + .long OpF2M0mod4 + .long OpF3M0mod4 + .long OpF4mod4 + .long OpF5M0mod4 + .long OpF6M0mod4 + .long OpF7M0mod4 + .long OpF8mod4 + .long OpF9M0mod4 + .long OpFAX1mod4 + .long OpFBmod4 + .long OpFCmod4 + .long OpFDM0mod4 + .long OpFEM0mod4 + .long OpFFM0mod4 +Op00mod4: +lbl00mod4: Op00 + NEXTOPCODE +Op01M0mod4: +lbl01mod4a: DirectIndexedIndirect1 +lbl01mod4b: ORA16 + NEXTOPCODE +Op02mod4: +lbl02mod4: Op02 + NEXTOPCODE +Op03M0mod4: +lbl03mod4a: StackasmRelative +lbl03mod4b: ORA16 + NEXTOPCODE +Op04M0mod4: +lbl04mod4a: Direct +lbl04mod4b: TSB16 + NEXTOPCODE +Op05M0mod4: +lbl05mod4a: Direct +lbl05mod4b: ORA16 + NEXTOPCODE +Op06M0mod4: +lbl06mod4a: Direct +lbl06mod4b: ASL16 + NEXTOPCODE +Op07M0mod4: +lbl07mod4a: DirectIndirectLong +lbl07mod4b: ORA16 + NEXTOPCODE +Op08mod4: +lbl08mod4: Op08 + NEXTOPCODE +Op09M0mod4: +lbl09mod4: Op09M0 + NEXTOPCODE +Op0AM0mod4: +lbl0Amod4a: A_ASL16 + NEXTOPCODE +Op0Bmod4: +lbl0Bmod4: Op0B + NEXTOPCODE +Op0CM0mod4: +lbl0Cmod4a: Absolute +lbl0Cmod4b: TSB16 + NEXTOPCODE +Op0DM0mod4: +lbl0Dmod4a: Absolute +lbl0Dmod4b: ORA16 + NEXTOPCODE +Op0EM0mod4: +lbl0Emod4a: Absolute +lbl0Emod4b: ASL16 + NEXTOPCODE +Op0FM0mod4: +lbl0Fmod4a: AbsoluteLong +lbl0Fmod4b: ORA16 + NEXTOPCODE +Op10mod4: +lbl10mod4: Op10 + NEXTOPCODE +Op11M0mod4: +lbl11mod4a: DirectIndirectIndexed1 +lbl11mod4b: ORA16 + NEXTOPCODE +Op12M0mod4: +lbl12mod4a: DirectIndirect +lbl12mod4b: ORA16 + NEXTOPCODE +Op13M0mod4: +lbl13mod4a: StackasmRelativeIndirectIndexed1 +lbl13mod4b: ORA16 + NEXTOPCODE +Op14M0mod4: +lbl14mod4a: Direct +lbl14mod4b: TRB16 + NEXTOPCODE +Op15M0mod4: +lbl15mod4a: DirectIndexedX1 +lbl15mod4b: ORA16 + NEXTOPCODE +Op16M0mod4: +lbl16mod4a: DirectIndexedX1 +lbl16mod4b: ASL16 + NEXTOPCODE +Op17M0mod4: +lbl17mod4a: DirectIndirectIndexedLong1 +lbl17mod4b: ORA16 + NEXTOPCODE +Op18mod4: +lbl18mod4: Op18 + NEXTOPCODE +Op19M0mod4: +lbl19mod4a: AbsoluteIndexedY1 +lbl19mod4b: ORA16 + NEXTOPCODE +Op1AM0mod4: +lbl1Amod4a: A_INC16 + NEXTOPCODE +Op1Bmod4: +lbl1Bmod4: Op1BM0 + NEXTOPCODE +Op1CM0mod4: +lbl1Cmod4a: Absolute +lbl1Cmod4b: TRB16 + NEXTOPCODE +Op1DM0mod4: +lbl1Dmod4a: AbsoluteIndexedX1 +lbl1Dmod4b: ORA16 + NEXTOPCODE +Op1EM0mod4: +lbl1Emod4a: AbsoluteIndexedX1 +lbl1Emod4b: ASL16 + NEXTOPCODE +Op1FM0mod4: +lbl1Fmod4a: AbsoluteLongIndexedX1 +lbl1Fmod4b: ORA16 + NEXTOPCODE +Op20mod4: +lbl20mod4: Op20 + NEXTOPCODE +Op21M0mod4: +lbl21mod4a: DirectIndexedIndirect1 +lbl21mod4b: AND16 + NEXTOPCODE +Op22mod4: +lbl22mod4: Op22 + NEXTOPCODE +Op23M0mod4: +lbl23mod4a: StackasmRelative +lbl23mod4b: AND16 + NEXTOPCODE +Op24M0mod4: +lbl24mod4a: Direct +lbl24mod4b: BIT16 + NEXTOPCODE +Op25M0mod4: +lbl25mod4a: Direct +lbl25mod4b: AND16 + NEXTOPCODE +Op26M0mod4: +lbl26mod4a: Direct +lbl26mod4b: ROL16 + NEXTOPCODE +Op27M0mod4: +lbl27mod4a: DirectIndirectLong +lbl27mod4b: AND16 + NEXTOPCODE +Op28mod4: +lbl28mod4: Op28X1M0 + NEXTOPCODE +.pool +Op29M0mod4: +lbl29mod4: Op29M0 + NEXTOPCODE +Op2AM0mod4: +lbl2Amod4a: A_ROL16 + NEXTOPCODE +Op2Bmod4: +lbl2Bmod4: Op2B + NEXTOPCODE +Op2CM0mod4: +lbl2Cmod4a: Absolute +lbl2Cmod4b: BIT16 + NEXTOPCODE +Op2DM0mod4: +lbl2Dmod4a: Absolute +lbl2Dmod4b: AND16 + NEXTOPCODE +Op2EM0mod4: +lbl2Emod4a: Absolute +lbl2Emod4b: ROL16 + NEXTOPCODE +Op2FM0mod4: +lbl2Fmod4a: AbsoluteLong +lbl2Fmod4b: AND16 + NEXTOPCODE +Op30mod4: +lbl30mod4: Op30 + NEXTOPCODE +Op31M0mod4: +lbl31mod4a: DirectIndirectIndexed1 +lbl31mod4b: AND16 + NEXTOPCODE +Op32M0mod4: +lbl32mod4a: DirectIndirect +lbl32mod4b: AND16 + NEXTOPCODE +Op33M0mod4: +lbl33mod4a: StackasmRelativeIndirectIndexed1 +lbl33mod4b: AND16 + NEXTOPCODE +Op34M0mod4: +lbl34mod4a: DirectIndexedX1 +lbl34mod4b: BIT16 + NEXTOPCODE +Op35M0mod4: +lbl35mod4a: DirectIndexedX1 +lbl35mod4b: AND16 + NEXTOPCODE +Op36M0mod4: +lbl36mod4a: DirectIndexedX1 +lbl36mod4b: ROL16 + NEXTOPCODE +Op37M0mod4: +lbl37mod4a: DirectIndirectIndexedLong1 +lbl37mod4b: AND16 + NEXTOPCODE +Op38mod4: +lbl38mod4: Op38 + NEXTOPCODE +Op39M0mod4: +lbl39mod4a: AbsoluteIndexedY1 +lbl39mod4b: AND16 + NEXTOPCODE +Op3AM0mod4: +lbl3Amod4a: A_DEC16 + NEXTOPCODE +Op3Bmod4: +lbl3Bmod4: Op3BM0 + NEXTOPCODE +Op3CM0mod4: +lbl3Cmod4a: AbsoluteIndexedX1 +lbl3Cmod4b: BIT16 + NEXTOPCODE +Op3DM0mod4: +lbl3Dmod4a: AbsoluteIndexedX1 +lbl3Dmod4b: AND16 + NEXTOPCODE +Op3EM0mod4: +lbl3Emod4a: AbsoluteIndexedX1 +lbl3Emod4b: ROL16 + NEXTOPCODE +Op3FM0mod4: +lbl3Fmod4a: AbsoluteLongIndexedX1 +lbl3Fmod4b: AND16 + NEXTOPCODE +Op40mod4: +lbl40mod4: Op40X1M0 + NEXTOPCODE +.pool +Op41M0mod4: +lbl41mod4a: DirectIndexedIndirect1 +lbl41mod4b: EOR16 + NEXTOPCODE +Op42mod4: +lbl42mod4: Op42 + NEXTOPCODE +Op43M0mod4: +lbl43mod4a: StackasmRelative +lbl43mod4b: EOR16 + NEXTOPCODE +Op44X1mod4: +lbl44mod4: Op44X1M0 + NEXTOPCODE +Op45M0mod4: +lbl45mod4a: Direct +lbl45mod4b: EOR16 + NEXTOPCODE +Op46M0mod4: +lbl46mod4a: Direct +lbl46mod4b: LSR16 + NEXTOPCODE +Op47M0mod4: +lbl47mod4a: DirectIndirectLong +lbl47mod4b: EOR16 + NEXTOPCODE +Op48M0mod4: +lbl48mod4: Op48M0 + NEXTOPCODE +Op49M0mod4: +lbl49mod4: Op49M0 + NEXTOPCODE +Op4AM0mod4: +lbl4Amod4a: A_LSR16 + NEXTOPCODE +Op4Bmod4: +lbl4Bmod4: Op4B + NEXTOPCODE +Op4Cmod4: +lbl4Cmod4: Op4C + NEXTOPCODE +Op4DM0mod4: +lbl4Dmod4a: Absolute +lbl4Dmod4b: EOR16 + NEXTOPCODE +Op4EM0mod4: +lbl4Emod4a: Absolute +lbl4Emod4b: LSR16 + NEXTOPCODE +Op4FM0mod4: +lbl4Fmod4a: AbsoluteLong +lbl4Fmod4b: EOR16 + NEXTOPCODE +Op50mod4: +lbl50mod4: Op50 + NEXTOPCODE +Op51M0mod4: +lbl51mod4a: DirectIndirectIndexed1 +lbl51mod4b: EOR16 + NEXTOPCODE +Op52M0mod4: +lbl52mod4a: DirectIndirect +lbl52mod4b: EOR16 + NEXTOPCODE +Op53M0mod4: +lbl53mod4a: StackasmRelativeIndirectIndexed1 +lbl53mod4b: EOR16 + NEXTOPCODE + +Op54X1mod4: +lbl54mod4: Op54X1M0 + NEXTOPCODE +Op55M0mod4: +lbl55mod4a: DirectIndexedX1 +lbl55mod4b: EOR16 + NEXTOPCODE +Op56M0mod4: +lbl56mod4a: DirectIndexedX1 +lbl56mod4b: LSR16 + NEXTOPCODE +Op57M0mod4: +lbl57mod4a: DirectIndirectIndexedLong1 +lbl57mod4b: EOR16 + NEXTOPCODE +Op58mod4: +lbl58mod4: Op58 + NEXTOPCODE +Op59M0mod4: +lbl59mod4a: AbsoluteIndexedY1 +lbl59mod4b: EOR16 + NEXTOPCODE +Op5AX1mod4: +lbl5Amod4: Op5AX1 + NEXTOPCODE +Op5Bmod4: +lbl5Bmod4: Op5BM0 + NEXTOPCODE +Op5Cmod4: +lbl5Cmod4: Op5C + NEXTOPCODE +Op5DM0mod4: +lbl5Dmod4a: AbsoluteIndexedX1 +lbl5Dmod4b: EOR16 + NEXTOPCODE +Op5EM0mod4: +lbl5Emod4a: AbsoluteIndexedX1 +lbl5Emod4b: LSR16 + NEXTOPCODE +Op5FM0mod4: +lbl5Fmod4a: AbsoluteLongIndexedX1 +lbl5Fmod4b: EOR16 + NEXTOPCODE +Op60mod4: +lbl60mod4: Op60 + NEXTOPCODE +Op61M0mod4: +lbl61mod4a: DirectIndexedIndirect1 +lbl61mod4b: ADC16 + NEXTOPCODE +Op62mod4: +lbl62mod4: Op62 + NEXTOPCODE +Op63M0mod4: +lbl63mod4a: StackasmRelative +lbl63mod4b: ADC16 + NEXTOPCODE +.pool +Op64M0mod4: +lbl64mod4a: Direct +lbl64mod4b: STZ16 + NEXTOPCODE +Op65M0mod4: +lbl65mod4a: Direct +lbl65mod4b: ADC16 + NEXTOPCODE +.pool +Op66M0mod4: +lbl66mod4a: Direct +lbl66mod4b: ROR16 + NEXTOPCODE +Op67M0mod4: +lbl67mod4a: DirectIndirectLong +lbl67mod4b: ADC16 + NEXTOPCODE +.pool +Op68M0mod4: +lbl68mod4: Op68M0 + NEXTOPCODE +Op69M0mod4: +lbl69mod4a: Immediate16 +lbl69mod4b: ADC16 + NEXTOPCODE +.pool +Op6AM0mod4: +lbl6Amod4a: A_ROR16 + NEXTOPCODE +Op6Bmod4: +lbl6Bmod4: Op6B + NEXTOPCODE +Op6Cmod4: +lbl6Cmod4: Op6C + NEXTOPCODE +Op6DM0mod4: +lbl6Dmod4a: Absolute +lbl6Dmod4b: ADC16 + NEXTOPCODE +Op6EM0mod4: +lbl6Emod4a: Absolute +lbl6Emod4b: ROR16 + NEXTOPCODE +Op6FM0mod4: +lbl6Fmod4a: AbsoluteLong +lbl6Fmod4b: ADC16 + NEXTOPCODE +Op70mod4: +lbl70mod4: Op70 + NEXTOPCODE +Op71M0mod4: +lbl71mod4a: DirectIndirectIndexed1 +lbl71mod4b: ADC16 + NEXTOPCODE +Op72M0mod4: +lbl72mod4a: DirectIndirect +lbl72mod4b: ADC16 + NEXTOPCODE +Op73M0mod4: +lbl73mod4a: StackasmRelativeIndirectIndexed1 +lbl73mod4b: ADC16 + NEXTOPCODE +.pool +Op74M0mod4: +lbl74mod4a: DirectIndexedX1 +lbl74mod4b: STZ16 + NEXTOPCODE +Op75M0mod4: +lbl75mod4a: DirectIndexedX1 +lbl75mod4b: ADC16 + NEXTOPCODE +.pool +Op76M0mod4: +lbl76mod4a: DirectIndexedX1 +lbl76mod4b: ROR16 + NEXTOPCODE +Op77M0mod4: +lbl77mod4a: DirectIndirectIndexedLong1 +lbl77mod4b: ADC16 + NEXTOPCODE +Op78mod4: +lbl78mod4: Op78 + NEXTOPCODE +Op79M0mod4: +lbl79mod4a: AbsoluteIndexedY1 +lbl79mod4b: ADC16 + NEXTOPCODE +Op7AX1mod4: +lbl7Amod4: Op7AX1 + NEXTOPCODE +Op7Bmod4: +lbl7Bmod4: Op7BM0 + NEXTOPCODE +Op7Cmod4: +lbl7Cmod4: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE +Op7DM0mod4: +lbl7Dmod4a: AbsoluteIndexedX1 +lbl7Dmod4b: ADC16 + NEXTOPCODE +Op7EM0mod4: +lbl7Emod4a: AbsoluteIndexedX1 +lbl7Emod4b: ROR16 + NEXTOPCODE +Op7FM0mod4: +lbl7Fmod4a: AbsoluteLongIndexedX1 +lbl7Fmod4b: ADC16 + NEXTOPCODE +.pool +Op80mod4: +lbl80mod4: Op80 + NEXTOPCODE +Op81M0mod4: +lbl81mod4a: DirectIndexedIndirect1 +lbl81mod4b: Op81M0 + NEXTOPCODE +Op82mod4: +lbl82mod4: Op82 + NEXTOPCODE +Op83M0mod4: +lbl83mod4a: StackasmRelative +lbl83mod4b: STA16 + NEXTOPCODE +Op84X1mod4: +lbl84mod4a: Direct +lbl84mod4b: STY8 + NEXTOPCODE +Op85M0mod4: +lbl85mod4a: Direct +lbl85mod4b: STA16 + NEXTOPCODE +Op86X1mod4: +lbl86mod4a: Direct +lbl86mod4b: STX8 + NEXTOPCODE +Op87M0mod4: +lbl87mod4a: DirectIndirectLong +lbl87mod4b: STA16 + NEXTOPCODE +Op88X1mod4: +lbl88mod4: Op88X1 + NEXTOPCODE +Op89M0mod4: +lbl89mod4: Op89M0 + NEXTOPCODE +Op8AM0mod4: +lbl8Amod4: Op8AM0X1 + NEXTOPCODE +Op8Bmod4: +lbl8Bmod4: Op8B + NEXTOPCODE +Op8CX1mod4: +lbl8Cmod4a: Absolute +lbl8Cmod4b: STY8 + NEXTOPCODE +Op8DM0mod4: +lbl8Dmod4a: Absolute +lbl8Dmod4b: STA16 + NEXTOPCODE +Op8EX1mod4: +lbl8Emod4a: Absolute +lbl8Emod4b: STX8 + NEXTOPCODE +Op8FM0mod4: +lbl8Fmod4a: AbsoluteLong +lbl8Fmod4b: STA16 + NEXTOPCODE +Op90mod4: +lbl90mod4: Op90 + NEXTOPCODE +Op91M0mod4: +lbl91mod4a: DirectIndirectIndexed1 +lbl91mod4b: STA16 + NEXTOPCODE +Op92M0mod4: +lbl92mod4a: DirectIndirect +lbl92mod4b: STA16 + NEXTOPCODE +Op93M0mod4: +lbl93mod4a: StackasmRelativeIndirectIndexed1 +lbl93mod4b: STA16 + NEXTOPCODE +Op94X1mod4: +lbl94mod4a: DirectIndexedX1 +lbl94mod4b: STY8 + NEXTOPCODE +Op95M0mod4: +lbl95mod4a: DirectIndexedX1 +lbl95mod4b: STA16 + NEXTOPCODE +Op96X1mod4: +lbl96mod4a: DirectIndexedY1 +lbl96mod4b: STX8 + NEXTOPCODE +Op97M0mod4: +lbl97mod4a: DirectIndirectIndexedLong1 +lbl97mod4b: STA16 + NEXTOPCODE +Op98M0mod4: +lbl98mod4: Op98M0X1 + NEXTOPCODE +Op99M0mod4: +lbl99mod4a: AbsoluteIndexedY1 +lbl99mod4b: STA16 + NEXTOPCODE +Op9Amod4: +lbl9Amod4: Op9AX1 + NEXTOPCODE +Op9BX1mod4: +lbl9Bmod4: Op9BX1 + NEXTOPCODE +Op9CM0mod4: +lbl9Cmod4a: Absolute +lbl9Cmod4b: STZ16 + NEXTOPCODE +Op9DM0mod4: +lbl9Dmod4a: AbsoluteIndexedX1 +lbl9Dmod4b: STA16 + NEXTOPCODE +Op9EM0mod4: +lbl9Emod4: AbsoluteIndexedX1 + STZ16 + NEXTOPCODE +Op9FM0mod4: +lbl9Fmod4a: AbsoluteLongIndexedX1 +lbl9Fmod4b: STA16 + NEXTOPCODE +OpA0X1mod4: +lblA0mod4: OpA0X1 + NEXTOPCODE +OpA1M0mod4: +lblA1mod4a: DirectIndexedIndirect1 +lblA1mod4b: LDA16 + NEXTOPCODE +OpA2X1mod4: +lblA2mod4: OpA2X1 + NEXTOPCODE +OpA3M0mod4: +lblA3mod4a: StackasmRelative +lblA3mod4b: LDA16 + NEXTOPCODE +OpA4X1mod4: +lblA4mod4a: Direct +lblA4mod4b: LDY8 + NEXTOPCODE +OpA5M0mod4: +lblA5mod4a: Direct +lblA5mod4b: LDA16 + NEXTOPCODE +OpA6X1mod4: +lblA6mod4a: Direct +lblA6mod4b: LDX8 + NEXTOPCODE +OpA7M0mod4: +lblA7mod4a: DirectIndirectLong +lblA7mod4b: LDA16 + NEXTOPCODE +OpA8X1mod4: +lblA8mod4: OpA8X1M0 + NEXTOPCODE +OpA9M0mod4: +lblA9mod4: OpA9M0 + NEXTOPCODE +OpAAX1mod4: +lblAAmod4: OpAAX1M0 + NEXTOPCODE +OpABmod4: +lblABmod4: OpAB + NEXTOPCODE +OpACX1mod4: +lblACmod4a: Absolute +lblACmod4b: LDY8 + NEXTOPCODE +OpADM0mod4: +lblADmod4a: Absolute +lblADmod4b: LDA16 + NEXTOPCODE +OpAEX1mod4: +lblAEmod4a: Absolute +lblAEmod4b: LDX8 + NEXTOPCODE +OpAFM0mod4: +lblAFmod4a: AbsoluteLong +lblAFmod4b: LDA16 + NEXTOPCODE +OpB0mod4: +lblB0mod4: OpB0 + NEXTOPCODE +OpB1M0mod4: +lblB1mod4a: DirectIndirectIndexed1 +lblB1mod4b: LDA16 + NEXTOPCODE +OpB2M0mod4: +lblB2mod4a: DirectIndirect +lblB2mod4b: LDA16 + NEXTOPCODE +OpB3M0mod4: +lblB3mod4a: StackasmRelativeIndirectIndexed1 +lblB3mod4b: LDA16 + NEXTOPCODE +OpB4X1mod4: +lblB4mod4a: DirectIndexedX1 +lblB4mod4b: LDY8 + NEXTOPCODE +OpB5M0mod4: +lblB5mod4a: DirectIndexedX1 +lblB5mod4b: LDA16 + NEXTOPCODE +OpB6X1mod4: +lblB6mod4a: DirectIndexedY1 +lblB6mod4b: LDX8 + NEXTOPCODE +OpB7M0mod4: +lblB7mod4a: DirectIndirectIndexedLong1 +lblB7mod4b: LDA16 + NEXTOPCODE +OpB8mod4: +lblB8mod4: OpB8 + NEXTOPCODE +OpB9M0mod4: +lblB9mod4a: AbsoluteIndexedY1 +lblB9mod4b: LDA16 + NEXTOPCODE +OpBAX1mod4: +lblBAmod4: OpBAX1 + NEXTOPCODE +OpBBX1mod4: +lblBBmod4: OpBBX1 + NEXTOPCODE +OpBCX1mod4: +lblBCmod4a: AbsoluteIndexedX1 +lblBCmod4b: LDY8 + NEXTOPCODE +OpBDM0mod4: +lblBDmod4a: AbsoluteIndexedX1 +lblBDmod4b: LDA16 + NEXTOPCODE +OpBEX1mod4: +lblBEmod4a: AbsoluteIndexedY1 +lblBEmod4b: LDX8 + NEXTOPCODE +OpBFM0mod4: +lblBFmod4a: AbsoluteLongIndexedX1 +lblBFmod4b: LDA16 + NEXTOPCODE +OpC0X1mod4: +lblC0mod4: OpC0X1 + NEXTOPCODE +OpC1M0mod4: +lblC1mod4a: DirectIndexedIndirect1 +lblC1mod4b: CMP16 + NEXTOPCODE +OpC2mod4: +lblC2mod4: OpC2 + NEXTOPCODE +.pool +OpC3M0mod4: +lblC3mod4a: StackasmRelative +lblC3mod4b: CMP16 + NEXTOPCODE +OpC4X1mod4: +lblC4mod4a: Direct +lblC4mod4b: CMY8 + NEXTOPCODE +OpC5M0mod4: +lblC5mod4a: Direct +lblC5mod4b: CMP16 + NEXTOPCODE +OpC6M0mod4: +lblC6mod4a: Direct +lblC6mod4b: DEC16 + NEXTOPCODE +OpC7M0mod4: +lblC7mod4a: DirectIndirectLong +lblC7mod4b: CMP16 + NEXTOPCODE +OpC8X1mod4: +lblC8mod4: OpC8X1 + NEXTOPCODE +OpC9M0mod4: +lblC9mod4: OpC9M0 + NEXTOPCODE +OpCAX1mod4: +lblCAmod4: OpCAX1 + NEXTOPCODE +OpCBmod4: +lblCBmod4: OpCB + NEXTOPCODE +OpCCX1mod4: +lblCCmod4a: Absolute +lblCCmod4b: CMY8 + NEXTOPCODE +OpCDM0mod4: +lblCDmod4a: Absolute +lblCDmod4b: CMP16 + NEXTOPCODE +OpCEM0mod4: +lblCEmod4a: Absolute +lblCEmod4b: DEC16 + NEXTOPCODE +OpCFM0mod4: +lblCFmod4a: AbsoluteLong +lblCFmod4b: CMP16 + NEXTOPCODE +OpD0mod4: +lblD0mod4: OpD0 + NEXTOPCODE +OpD1M0mod4: +lblD1mod4a: DirectIndirectIndexed1 +lblD1mod4b: CMP16 + + NEXTOPCODE +OpD2M0mod4: +lblD2mod4a: DirectIndirect +lblD2mod4b: CMP16 + NEXTOPCODE +OpD3M0mod4: +lblD3mod4a: StackasmRelativeIndirectIndexed1 +lblD3mod4b: CMP16 + NEXTOPCODE +OpD4mod4: +lblD4mod4: OpD4 + NEXTOPCODE +OpD5M0mod4: +lblD5mod4a: DirectIndexedX1 +lblD5mod4b: CMP16 + NEXTOPCODE +OpD6M0mod4: +lblD6mod4a: DirectIndexedX1 +lblD6mod4b: DEC16 + NEXTOPCODE +OpD7M0mod4: +lblD7mod4a: DirectIndirectIndexedLong1 +lblD7mod4b: CMP16 + NEXTOPCODE +OpD8mod4: +lblD8mod4: OpD8 + NEXTOPCODE +OpD9M0mod4: +lblD9mod4a: AbsoluteIndexedY1 +lblD9mod4b: CMP16 + NEXTOPCODE +OpDAX1mod4: +lblDAmod4: OpDAX1 + NEXTOPCODE +OpDBmod4: +lblDBmod4: OpDB + NEXTOPCODE +OpDCmod4: +lblDCmod4: OpDC + NEXTOPCODE +OpDDM0mod4: +lblDDmod4a: AbsoluteIndexedX1 +lblDDmod4b: CMP16 + NEXTOPCODE +OpDEM0mod4: +lblDEmod4a: AbsoluteIndexedX1 +lblDEmod4b: DEC16 + NEXTOPCODE +OpDFM0mod4: +lblDFmod4a: AbsoluteLongIndexedX1 +lblDFmod4b: CMP16 + NEXTOPCODE +OpE0X1mod4: +lblE0mod4: OpE0X1 + NEXTOPCODE +OpE1M0mod4: +lblE1mod4a: DirectIndexedIndirect1 +lblE1mod4b: SBC16 + NEXTOPCODE +OpE2mod4: +lblE2mod4: OpE2 + NEXTOPCODE +.pool +OpE3M0mod4: +lblE3mod4a: StackasmRelative +lblE3mod4b: SBC16 + NEXTOPCODE +OpE4X1mod4: +lblE4mod4a: Direct +lblE4mod4b: CMX8 + NEXTOPCODE +OpE5M0mod4: +lblE5mod4a: Direct +lblE5mod4b: SBC16 + NEXTOPCODE +OpE6M0mod4: +lblE6mod4a: Direct +lblE6mod4b: INC16 + NEXTOPCODE +OpE7M0mod4: +lblE7mod4a: DirectIndirectLong +lblE7mod4b: SBC16 + NEXTOPCODE +OpE8X1mod4: +lblE8mod4: OpE8X1 + NEXTOPCODE +OpE9M0mod4: +lblE9mod4a: Immediate16 +lblE9mod4b: SBC16 + NEXTOPCODE +OpEAmod4: +lblEAmod4: OpEA + NEXTOPCODE +OpEBmod4: +lblEBmod4: OpEBM0 + NEXTOPCODE +OpECX1mod4: +lblECmod4a: Absolute +lblECmod4b: CMX8 + NEXTOPCODE +OpEDM0mod4: +lblEDmod4a: Absolute +lblEDmod4b: SBC16 + NEXTOPCODE +OpEEM0mod4: +lblEEmod4a: Absolute +lblEEmod4b: INC16 + NEXTOPCODE +OpEFM0mod4: +lblEFmod4a: AbsoluteLong +lblEFmod4b: SBC16 + NEXTOPCODE +OpF0mod4: +lblF0mod4: OpF0 + NEXTOPCODE +OpF1M0mod4: +lblF1mod4a: DirectIndirectIndexed1 +lblF1mod4b: SBC16 + NEXTOPCODE +OpF2M0mod4: +lblF2mod4a: DirectIndirect +lblF2mod4b: SBC16 + NEXTOPCODE +OpF3M0mod4: +lblF3mod4a: StackasmRelativeIndirectIndexed1 +lblF3mod4b: SBC16 + NEXTOPCODE +OpF4mod4: +lblF4mod4: OpF4 + NEXTOPCODE +OpF5M0mod4: +lblF5mod4a: DirectIndexedX1 +lblF5mod4b: SBC16 + NEXTOPCODE +OpF6M0mod4: +lblF6mod4a: DirectIndexedX1 +lblF6mod4b: INC16 + NEXTOPCODE +OpF7M0mod4: +lblF7mod4a: DirectIndirectIndexedLong1 +lblF7mod4b: SBC16 + NEXTOPCODE +OpF8mod4: +lblF8mod4: OpF8 + NEXTOPCODE +OpF9M0mod4: +lblF9mod4a: AbsoluteIndexedY1 +lblF9mod4b: SBC16 + NEXTOPCODE +OpFAX1mod4: +lblFAmod4: OpFAX1 + NEXTOPCODE +OpFBmod4: +lblFBmod4: OpFB + NEXTOPCODE +OpFCmod4: +lblFCmod4: OpFCX1 + NEXTOPCODE +OpFDM0mod4: +lblFDmod4a: AbsoluteIndexedX1 +lblFDmod4b: SBC16 + NEXTOPCODE +OpFEM0mod4: +lblFEmod4a: AbsoluteIndexedX1 +lblFEmod4b: INC16 + NEXTOPCODE +OpFFM0mod4: +lblFFmod4a: AbsoluteLongIndexedX1 +lblFFmod4b: SBC16 + NEXTOPCODE + + + .pool + diff --git a/src/os9x_65c816_spcc.s b/src/os9x_65c816_spcc.s new file mode 100644 index 0000000..eadcd15 --- /dev/null +++ b/src/os9x_65c816_spcc.s @@ -0,0 +1,4990 @@ + .DATA +/**************************************************************** +****************************************************************/ + .align 4 + .include "os9x_65c816_common.s" + +.equ IAPU_PC_offs, 52 + +.macro asmAPU_EXECUTE + ldr r0, [reg_cpu_var, #APUExecuting_ofs] + ldr r1, [reg_cpu_var, #APU_Cycles] + cmp r0, #1 @ spc700 enabled, hack mode off + bne 43210f + + cmp r1, reg_cycles + bge 43210f + + + stmfd r13!, {r4, r12, r14} + mov r4, reg_cpu_var +55555: + ldr r0, =IAPU + ldr r2, =S9xAPUCycles + ldr r0, [r0, #IAPU_PC_offs] @ r0 = IAPU.PC + ldr r3, =S9xApuOpcodes + ldrb r0, [r0] @ r0 = APU Opcode + + add lr, pc, #(3*4) @ set return point + + ldr r2, [r2, r0, lsl #2] + add r1, r1, r2 + str r1, [r4, #APU_Cycles] @ CPU.APU_Cycles += S9xAPUCycles [*IAPU.PC] + + ldr pc, [r3, r0, lsl #2] @ (*S9xApuOpcodes[*IAPU.PC]) (); + @ return point + + ldr r1, [r4, #APU_Cycles] + cmp r1, reg_cycles + blt 55555b + + ldmfd r13!, {r4, r12, r14} + +43210: +.endm + +.macro asmAPU_EXECUTE2 + ldr r0, [reg_cpu_var, #APUExecuting_ofs] + ldr r1, [reg_cpu_var, #APU_Cycles] + cmp r0, #1 @ spc700 enabled, hack mode off + bne 43211f + + cmp r1, reg_cycles + bge 43211f + + + stmfd r13!, {r4, r12, r14} + mov r4, reg_cpu_var +55555: + ldr r0, =IAPU + ldr r2, =S9xAPUCycles + ldr r0, [r0, #IAPU_PC_offs] @ r0 = IAPU.PC + ldr r3, =S9xApuOpcodes + ldrb r0, [r0] @ r0 = APU Opcode + + add lr, pc, #(3*4) @ set return point + + ldr r2, [r2, r0, lsl #2] + add r1, r1, r2 + str r1, [r4, #APU_Cycles] @ CPU.APU_Cycles += S9xAPUCycles [*IAPU.PC] + + ldr pc, [r3, r0, lsl #2] @ (*S9xApuOpcodes[*IAPU.PC]) (); + @ return point + + ldr r1, [r4, #APU_Cycles] + cmp r1, reg_cycles + blt 55555b + + ldmfd r13!, {r4, r12, r14} + +43211: +.endm +/* +.macro asmAPU_EXECUTE2 + LDR R0,[reg_cpu_var,#APUExecuting_ofs] + CMP R0, #1 @ spc700 enabled, hack mode off + BNE 43211f + PREPARE_C_CALL_LIGHTR12 + mov r0, reg_cycles + bl APU_EXECUTE4ASM + RESTORE_C_CALL_LIGHTR12 +43211: +.endm +*/ + + .include "os9x_65c816_opcodes.s" + + +/* + + +CLI_OPE_REC_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @treasuryDate, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @accountingDate, 103) + +CLI_OPE_Nos_Ope_Layer0 + n.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + n.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +CLI_OPE_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +Ecrans: +------ + + +[GNV] : utilisation de la lard (laccdate) pour afficher les openings. + +nécessité d'avoir des valeurs dans l'opening pour date tréso=date compta=laccdate + +[Accounting rec] : si laccdate pas bonne (pas = BD-1) -> message warning et pas de donnée +sinon : + +données nécessaires : opening date tréso=date compta=laccdate=BD-1 + +données nécessaires : opening date tréso=date compta=laccdate-1 + +données nécessaires : opening date tréso=laccdate-1 et date compta=laccdate + */ + + + +/**************************************************************** + GLOBAL +****************************************************************/ + @.globl test_opcode + .globl asmMainLoop_spcC + + +@ void asmMainLoop(asm_cpu_var_t *asmcpuPtr); +asmMainLoop_spcC: + doMainLoop + + +.pool + +/* +@ void test_opcode(struct asm_cpu_var *asm_var); +test_opcode: + doTestOpcode +.pool + +*/ + +/***************************************************************** + ASM CODE +*****************************************************************/ + + +jumptable1: .long Op00mod1 + .long Op01M1mod1 + .long Op02mod1 + .long Op03M1mod1 + .long Op04M1mod1 + .long Op05M1mod1 + .long Op06M1mod1 + .long Op07M1mod1 + .long Op08mod1 + .long Op09M1mod1 + .long Op0AM1mod1 + .long Op0Bmod1 + .long Op0CM1mod1 + .long Op0DM1mod1 + .long Op0EM1mod1 + .long Op0FM1mod1 + .long Op10mod1 + .long Op11M1mod1 + .long Op12M1mod1 + .long Op13M1mod1 + .long Op14M1mod1 + .long Op15M1mod1 + .long Op16M1mod1 + .long Op17M1mod1 + .long Op18mod1 + .long Op19M1mod1 + .long Op1AM1mod1 + .long Op1Bmod1 + .long Op1CM1mod1 + .long Op1DM1mod1 + .long Op1EM1mod1 + .long Op1FM1mod1 + .long Op20mod1 + .long Op21M1mod1 + .long Op22mod1 + .long Op23M1mod1 + .long Op24M1mod1 + .long Op25M1mod1 + .long Op26M1mod1 + .long Op27M1mod1 + .long Op28mod1 + .long Op29M1mod1 + .long Op2AM1mod1 + .long Op2Bmod1 + .long Op2CM1mod1 + .long Op2DM1mod1 + .long Op2EM1mod1 + .long Op2FM1mod1 + .long Op30mod1 + .long Op31M1mod1 + .long Op32M1mod1 + .long Op33M1mod1 + .long Op34M1mod1 + .long Op35M1mod1 + .long Op36M1mod1 + .long Op37M1mod1 + .long Op38mod1 + .long Op39M1mod1 + .long Op3AM1mod1 + .long Op3Bmod1 + .long Op3CM1mod1 + .long Op3DM1mod1 + .long Op3EM1mod1 + .long Op3FM1mod1 + .long Op40mod1 + .long Op41M1mod1 + .long Op42mod1 + .long Op43M1mod1 + .long Op44X1mod1 + .long Op45M1mod1 + .long Op46M1mod1 + .long Op47M1mod1 + .long Op48M1mod1 + .long Op49M1mod1 + .long Op4AM1mod1 + .long Op4Bmod1 + .long Op4Cmod1 + .long Op4DM1mod1 + .long Op4EM1mod1 + .long Op4FM1mod1 + .long Op50mod1 + .long Op51M1mod1 + .long Op52M1mod1 + .long Op53M1mod1 + .long Op54X1mod1 + .long Op55M1mod1 + .long Op56M1mod1 + .long Op57M1mod1 + .long Op58mod1 + .long Op59M1mod1 + .long Op5AX1mod1 + .long Op5Bmod1 + .long Op5Cmod1 + .long Op5DM1mod1 + .long Op5EM1mod1 + .long Op5FM1mod1 + .long Op60mod1 + .long Op61M1mod1 + .long Op62mod1 + .long Op63M1mod1 + .long Op64M1mod1 + .long Op65M1mod1 + .long Op66M1mod1 + .long Op67M1mod1 + .long Op68M1mod1 + .long Op69M1mod1 + .long Op6AM1mod1 + .long Op6Bmod1 + .long Op6Cmod1 + .long Op6DM1mod1 + .long Op6EM1mod1 + .long Op6FM1mod1 + .long Op70mod1 + .long Op71M1mod1 + .long Op72M1mod1 + .long Op73M1mod1 + .long Op74M1mod1 + .long Op75M1mod1 + .long Op76M1mod1 + .long Op77M1mod1 + .long Op78mod1 + .long Op79M1mod1 + .long Op7AX1mod1 + .long Op7Bmod1 + .long Op7Cmod1 + .long Op7DM1mod1 + .long Op7EM1mod1 + .long Op7FM1mod1 + .long Op80mod1 + .long Op81M1mod1 + .long Op82mod1 + .long Op83M1mod1 + .long Op84X1mod1 + .long Op85M1mod1 + .long Op86X1mod1 + .long Op87M1mod1 + .long Op88X1mod1 + .long Op89M1mod1 + .long Op8AM1mod1 + .long Op8Bmod1 + .long Op8CX1mod1 + .long Op8DM1mod1 + .long Op8EX1mod1 + .long Op8FM1mod1 + .long Op90mod1 + .long Op91M1mod1 + .long Op92M1mod1 + .long Op93M1mod1 + .long Op94X1mod1 + .long Op95M1mod1 + .long Op96X1mod1 + .long Op97M1mod1 + .long Op98M1mod1 + .long Op99M1mod1 + .long Op9Amod1 + .long Op9BX1mod1 + + .long Op9CM1mod1 + .long Op9DM1mod1 + .long Op9EM1mod1 + .long Op9FM1mod1 + .long OpA0X1mod1 + .long OpA1M1mod1 + .long OpA2X1mod1 + .long OpA3M1mod1 + .long OpA4X1mod1 + .long OpA5M1mod1 + .long OpA6X1mod1 + .long OpA7M1mod1 + .long OpA8X1mod1 + .long OpA9M1mod1 + .long OpAAX1mod1 + .long OpABmod1 + .long OpACX1mod1 + .long OpADM1mod1 + .long OpAEX1mod1 + .long OpAFM1mod1 + .long OpB0mod1 + .long OpB1M1mod1 + .long OpB2M1mod1 + .long OpB3M1mod1 + .long OpB4X1mod1 + .long OpB5M1mod1 + .long OpB6X1mod1 + .long OpB7M1mod1 + .long OpB8mod1 + .long OpB9M1mod1 + .long OpBAX1mod1 + .long OpBBX1mod1 + .long OpBCX1mod1 + .long OpBDM1mod1 + .long OpBEX1mod1 + .long OpBFM1mod1 + .long OpC0X1mod1 + .long OpC1M1mod1 + .long OpC2mod1 + .long OpC3M1mod1 + .long OpC4X1mod1 + .long OpC5M1mod1 + .long OpC6M1mod1 + .long OpC7M1mod1 + .long OpC8X1mod1 + .long OpC9M1mod1 + .long OpCAX1mod1 + .long OpCBmod1 + .long OpCCX1mod1 + .long OpCDM1mod1 + .long OpCEM1mod1 + .long OpCFM1mod1 + .long OpD0mod1 + .long OpD1M1mod1 + .long OpD2M1mod1 + .long OpD3M1mod1 + .long OpD4mod1 + .long OpD5M1mod1 + .long OpD6M1mod1 + .long OpD7M1mod1 + .long OpD8mod1 + .long OpD9M1mod1 + .long OpDAX1mod1 + .long OpDBmod1 + .long OpDCmod1 + .long OpDDM1mod1 + .long OpDEM1mod1 + .long OpDFM1mod1 + .long OpE0X1mod1 + .long OpE1M1mod1 + .long OpE2mod1 + .long OpE3M1mod1 + .long OpE4X1mod1 + .long OpE5M1mod1 + .long OpE6M1mod1 + .long OpE7M1mod1 + .long OpE8X1mod1 + .long OpE9M1mod1 + .long OpEAmod1 + .long OpEBmod1 + .long OpECX1mod1 + .long OpEDM1mod1 + .long OpEEM1mod1 + .long OpEFM1mod1 + .long OpF0mod1 + .long OpF1M1mod1 + .long OpF2M1mod1 + .long OpF3M1mod1 + .long OpF4mod1 + .long OpF5M1mod1 + .long OpF6M1mod1 + .long OpF7M1mod1 + .long OpF8mod1 + .long OpF9M1mod1 + .long OpFAX1mod1 + .long OpFBmod1 + .long OpFCmod1 + .long OpFDM1mod1 + .long OpFEM1mod1 + .long OpFFM1mod1 + +Op00mod1: +lbl00mod1: Op00 + NEXTOPCODE +Op01M1mod1: +lbl01mod1a: DirectIndexedIndirect1 +lbl01mod1b: ORA8 + NEXTOPCODE +Op02mod1: +lbl02mod1: Op02 + NEXTOPCODE +Op03M1mod1: +lbl03mod1a: StackasmRelative +lbl03mod1b: ORA8 + NEXTOPCODE +Op04M1mod1: +lbl04mod1a: Direct +lbl04mod1b: TSB8 + NEXTOPCODE +Op05M1mod1: +lbl05mod1a: Direct +lbl05mod1b: ORA8 + NEXTOPCODE +Op06M1mod1: +lbl06mod1a: Direct +lbl06mod1b: ASL8 + NEXTOPCODE +Op07M1mod1: +lbl07mod1a: DirectIndirectLong +lbl07mod1b: ORA8 + NEXTOPCODE +Op08mod1: +lbl08mod1: Op08 + NEXTOPCODE +Op09M1mod1: +lbl09mod1: Op09M1 + NEXTOPCODE +Op0AM1mod1: +lbl0Amod1a: A_ASL8 + NEXTOPCODE +Op0Bmod1: +lbl0Bmod1: Op0B + NEXTOPCODE +Op0CM1mod1: +lbl0Cmod1a: Absolute +lbl0Cmod1b: TSB8 + NEXTOPCODE +Op0DM1mod1: +lbl0Dmod1a: Absolute +lbl0Dmod1b: ORA8 + NEXTOPCODE +Op0EM1mod1: +lbl0Emod1a: Absolute +lbl0Emod1b: ASL8 + NEXTOPCODE +Op0FM1mod1: +lbl0Fmod1a: AbsoluteLong +lbl0Fmod1b: ORA8 + NEXTOPCODE +Op10mod1: +lbl10mod1: Op10 + NEXTOPCODE +Op11M1mod1: +lbl11mod1a: DirectIndirectIndexed1 +lbl11mod1b: ORA8 + NEXTOPCODE +Op12M1mod1: +lbl12mod1a: DirectIndirect +lbl12mod1b: ORA8 + NEXTOPCODE +Op13M1mod1: + +lbl13mod1a: StackasmRelativeIndirectIndexed1 +lbl13mod1b: ORA8 + NEXTOPCODE +Op14M1mod1: +lbl14mod1a: Direct +lbl14mod1b: TRB8 + NEXTOPCODE +Op15M1mod1: +lbl15mod1a: DirectIndexedX1 +lbl15mod1b: ORA8 + NEXTOPCODE +Op16M1mod1: +lbl16mod1a: DirectIndexedX1 +lbl16mod1b: ASL8 + NEXTOPCODE +Op17M1mod1: +lbl17mod1a: DirectIndirectIndexedLong1 +lbl17mod1b: ORA8 + NEXTOPCODE +Op18mod1: +lbl18mod1: Op18 + NEXTOPCODE +Op19M1mod1: +lbl19mod1a: AbsoluteIndexedY1 +lbl19mod1b: ORA8 + NEXTOPCODE +Op1AM1mod1: +lbl1Amod1a: A_INC8 + NEXTOPCODE +Op1Bmod1: +lbl1Bmod1: Op1BM1 + NEXTOPCODE +Op1CM1mod1: +lbl1Cmod1a: Absolute +lbl1Cmod1b: TRB8 + NEXTOPCODE +Op1DM1mod1: +lbl1Dmod1a: AbsoluteIndexedX1 +lbl1Dmod1b: ORA8 + NEXTOPCODE +Op1EM1mod1: +lbl1Emod1a: AbsoluteIndexedX1 +lbl1Emod1b: ASL8 + NEXTOPCODE +Op1FM1mod1: +lbl1Fmod1a: AbsoluteLongIndexedX1 +lbl1Fmod1b: ORA8 + NEXTOPCODE +Op20mod1: +lbl20mod1: Op20 + NEXTOPCODE +Op21M1mod1: +lbl21mod1a: DirectIndexedIndirect1 +lbl21mod1b: AND8 + NEXTOPCODE +Op22mod1: +lbl22mod1: Op22 + NEXTOPCODE +Op23M1mod1: +lbl23mod1a: StackasmRelative +lbl23mod1b: AND8 + NEXTOPCODE +Op24M1mod1: +lbl24mod1a: Direct +lbl24mod1b: BIT8 + NEXTOPCODE +Op25M1mod1: +lbl25mod1a: Direct +lbl25mod1b: AND8 + NEXTOPCODE +Op26M1mod1: +lbl26mod1a: Direct +lbl26mod1b: ROL8 + NEXTOPCODE +Op27M1mod1: +lbl27mod1a: DirectIndirectLong +lbl27mod1b: AND8 + NEXTOPCODE +Op28mod1: +lbl28mod1: Op28X1M1 + NEXTOPCODE +.pool +Op29M1mod1: +lbl29mod1: Op29M1 + NEXTOPCODE +Op2AM1mod1: +lbl2Amod1a: A_ROL8 + NEXTOPCODE +Op2Bmod1: +lbl2Bmod1: Op2B + NEXTOPCODE +Op2CM1mod1: +lbl2Cmod1a: Absolute +lbl2Cmod1b: BIT8 + NEXTOPCODE +Op2DM1mod1: +lbl2Dmod1a: Absolute +lbl2Dmod1b: AND8 + NEXTOPCODE +Op2EM1mod1: +lbl2Emod1a: Absolute +lbl2Emod1b: ROL8 + NEXTOPCODE +Op2FM1mod1: +lbl2Fmod1a: AbsoluteLong +lbl2Fmod1b: AND8 + NEXTOPCODE +Op30mod1: +lbl30mod1: Op30 + NEXTOPCODE +Op31M1mod1: +lbl31mod1a: DirectIndirectIndexed1 +lbl31mod1b: AND8 + NEXTOPCODE +Op32M1mod1: +lbl32mod1a: DirectIndirect +lbl32mod1b: AND8 + NEXTOPCODE +Op33M1mod1: +lbl33mod1a: StackasmRelativeIndirectIndexed1 +lbl33mod1b: AND8 + NEXTOPCODE +Op34M1mod1: +lbl34mod1a: DirectIndexedX1 +lbl34mod1b: BIT8 + NEXTOPCODE +Op35M1mod1: +lbl35mod1a: DirectIndexedX1 +lbl35mod1b: AND8 + NEXTOPCODE +Op36M1mod1: +lbl36mod1a: DirectIndexedX1 +lbl36mod1b: ROL8 + NEXTOPCODE +Op37M1mod1: +lbl37mod1a: DirectIndirectIndexedLong1 +lbl37mod1b: AND8 + NEXTOPCODE +Op38mod1: +lbl38mod1: Op38 + NEXTOPCODE +Op39M1mod1: +lbl39mod1a: AbsoluteIndexedY1 +lbl39mod1b: AND8 + NEXTOPCODE +Op3AM1mod1: +lbl3Amod1a: A_DEC8 + NEXTOPCODE +Op3Bmod1: +lbl3Bmod1: Op3BM1 + NEXTOPCODE +Op3CM1mod1: +lbl3Cmod1a: AbsoluteIndexedX1 +lbl3Cmod1b: BIT8 + NEXTOPCODE +Op3DM1mod1: +lbl3Dmod1a: AbsoluteIndexedX1 +lbl3Dmod1b: AND8 + NEXTOPCODE +Op3EM1mod1: +lbl3Emod1a: AbsoluteIndexedX1 +lbl3Emod1b: ROL8 + NEXTOPCODE +Op3FM1mod1: +lbl3Fmod1a: AbsoluteLongIndexedX1 +lbl3Fmod1b: AND8 + NEXTOPCODE +Op40mod1: +lbl40mod1: Op40X1M1 + NEXTOPCODE +.pool +Op41M1mod1: +lbl41mod1a: DirectIndexedIndirect1 +lbl41mod1b: EOR8 + NEXTOPCODE +Op42mod1: +lbl42mod1: Op42 + NEXTOPCODE +Op43M1mod1: +lbl43mod1a: StackasmRelative +lbl43mod1b: EOR8 + NEXTOPCODE +Op44X1mod1: +lbl44mod1: Op44X1M1 + NEXTOPCODE +Op45M1mod1: +lbl45mod1a: Direct +lbl45mod1b: EOR8 + NEXTOPCODE +Op46M1mod1: +lbl46mod1a: Direct +lbl46mod1b: LSR8 + NEXTOPCODE +Op47M1mod1: +lbl47mod1a: DirectIndirectLong +lbl47mod1b: EOR8 + NEXTOPCODE +Op48M1mod1: +lbl48mod1: Op48M1 + NEXTOPCODE +Op49M1mod1: +lbl49mod1: Op49M1 + NEXTOPCODE +Op4AM1mod1: +lbl4Amod1a: A_LSR8 + NEXTOPCODE +Op4Bmod1: +lbl4Bmod1: Op4B + NEXTOPCODE +Op4Cmod1: +lbl4Cmod1: Op4C + NEXTOPCODE +Op4DM1mod1: +lbl4Dmod1a: Absolute +lbl4Dmod1b: EOR8 + NEXTOPCODE +Op4EM1mod1: +lbl4Emod1a: Absolute +lbl4Emod1b: LSR8 + NEXTOPCODE +Op4FM1mod1: +lbl4Fmod1a: AbsoluteLong +lbl4Fmod1b: EOR8 + NEXTOPCODE +Op50mod1: +lbl50mod1: Op50 + NEXTOPCODE +Op51M1mod1: +lbl51mod1a: DirectIndirectIndexed1 +lbl51mod1b: EOR8 + NEXTOPCODE +Op52M1mod1: +lbl52mod1a: DirectIndirect +lbl52mod1b: EOR8 + NEXTOPCODE +Op53M1mod1: +lbl53mod1a: StackasmRelativeIndirectIndexed1 +lbl53mod1b: EOR8 + NEXTOPCODE +Op54X1mod1: +lbl54mod1: Op54X1M1 + NEXTOPCODE +Op55M1mod1: +lbl55mod1a: DirectIndexedX1 +lbl55mod1b: EOR8 + NEXTOPCODE +Op56M1mod1: +lbl56mod1a: DirectIndexedX1 +lbl56mod1b: LSR8 + NEXTOPCODE +Op57M1mod1: +lbl57mod1a: DirectIndirectIndexedLong1 +lbl57mod1b: EOR8 + NEXTOPCODE +Op58mod1: +lbl58mod1: Op58 + NEXTOPCODE +Op59M1mod1: +lbl59mod1a: AbsoluteIndexedY1 +lbl59mod1b: EOR8 + NEXTOPCODE +Op5AX1mod1: +lbl5Amod1: Op5AX1 + NEXTOPCODE +Op5Bmod1: +lbl5Bmod1: Op5BM1 + NEXTOPCODE +Op5Cmod1: +lbl5Cmod1: Op5C + NEXTOPCODE +Op5DM1mod1: +lbl5Dmod1a: AbsoluteIndexedX1 +lbl5Dmod1b: EOR8 + NEXTOPCODE +Op5EM1mod1: +lbl5Emod1a: AbsoluteIndexedX1 +lbl5Emod1b: LSR8 + NEXTOPCODE +Op5FM1mod1: +lbl5Fmod1a: AbsoluteLongIndexedX1 +lbl5Fmod1b: EOR8 + NEXTOPCODE +Op60mod1: +lbl60mod1: Op60 + NEXTOPCODE +Op61M1mod1: +lbl61mod1a: DirectIndexedIndirect1 +lbl61mod1b: ADC8 + NEXTOPCODE +Op62mod1: +lbl62mod1: Op62 + NEXTOPCODE +Op63M1mod1: +lbl63mod1a: StackasmRelative +lbl63mod1b: ADC8 + NEXTOPCODE +Op64M1mod1: +lbl64mod1a: Direct +lbl64mod1b: STZ8 + NEXTOPCODE +Op65M1mod1: +lbl65mod1a: Direct +lbl65mod1b: ADC8 + NEXTOPCODE +Op66M1mod1: +lbl66mod1a: Direct +lbl66mod1b: ROR8 + NEXTOPCODE +Op67M1mod1: +lbl67mod1a: DirectIndirectLong +lbl67mod1b: ADC8 + + NEXTOPCODE + +Op68M1mod1: +lbl68mod1: Op68M1 + NEXTOPCODE +Op69M1mod1: +lbl69mod1a: Immediate8 +lbl69mod1b: ADC8 + NEXTOPCODE +Op6AM1mod1: +lbl6Amod1a: A_ROR8 + NEXTOPCODE +Op6Bmod1: +lbl6Bmod1: Op6B + NEXTOPCODE +Op6Cmod1: +lbl6Cmod1: Op6C + NEXTOPCODE +Op6DM1mod1: +lbl6Dmod1a: Absolute +lbl6Dmod1b: ADC8 + NEXTOPCODE +Op6EM1mod1: + + +lbl6Emod1a: Absolute +lbl6Emod1b: ROR8 + NEXTOPCODE +Op6FM1mod1: +lbl6Fmod1a: AbsoluteLong +lbl6Fmod1b: ADC8 + NEXTOPCODE +Op70mod1: +lbl70mod1: Op70 + NEXTOPCODE +Op71M1mod1: +lbl71mod1a: DirectIndirectIndexed1 +lbl71mod1b: ADC8 + NEXTOPCODE +Op72M1mod1: +lbl72mod1a: DirectIndirect +lbl72mod1b: ADC8 + NEXTOPCODE +Op73M1mod1: +lbl73mod1a: StackasmRelativeIndirectIndexed1 +lbl73mod1b: ADC8 + NEXTOPCODE + +Op74M1mod1: +lbl74mod1a: DirectIndexedX1 +lbl74mod1b: STZ8 + NEXTOPCODE +Op75M1mod1: +lbl75mod1a: DirectIndexedX1 +lbl75mod1b: ADC8 + NEXTOPCODE +Op76M1mod1: +lbl76mod1a: DirectIndexedX1 +lbl76mod1b: ROR8 + NEXTOPCODE +Op77M1mod1: +lbl77mod1a: DirectIndirectIndexedLong1 +lbl77mod1b: ADC8 + NEXTOPCODE +Op78mod1: +lbl78mod1: Op78 + NEXTOPCODE +Op79M1mod1: +lbl79mod1a: AbsoluteIndexedY1 +lbl79mod1b: ADC8 + NEXTOPCODE +Op7AX1mod1: +lbl7Amod1: Op7AX1 + NEXTOPCODE +Op7Bmod1: +lbl7Bmod1: Op7BM1 + NEXTOPCODE +Op7Cmod1: +lbl7Cmod1: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE +Op7DM1mod1: +lbl7Dmod1a: AbsoluteIndexedX1 +lbl7Dmod1b: ADC8 + NEXTOPCODE +Op7EM1mod1: +lbl7Emod1a: AbsoluteIndexedX1 +lbl7Emod1b: ROR8 + NEXTOPCODE +Op7FM1mod1: +lbl7Fmod1a: AbsoluteLongIndexedX1 +lbl7Fmod1b: ADC8 + NEXTOPCODE + + +Op80mod1: +lbl80mod1: Op80 + NEXTOPCODE +Op81M1mod1: +lbl81mod1a: DirectIndexedIndirect1 +lbl81mod1b: Op81M1 + NEXTOPCODE +Op82mod1: +lbl82mod1: Op82 + NEXTOPCODE +Op83M1mod1: +lbl83mod1a: StackasmRelative +lbl83mod1b: STA8 + NEXTOPCODE +Op84X1mod1: +lbl84mod1a: Direct +lbl84mod1b: STY8 + NEXTOPCODE +Op85M1mod1: +lbl85mod1a: Direct +lbl85mod1b: STA8 + NEXTOPCODE +Op86X1mod1: +lbl86mod1a: Direct +lbl86mod1b: STX8 + NEXTOPCODE +Op87M1mod1: +lbl87mod1a: DirectIndirectLong +lbl87mod1b: STA8 + NEXTOPCODE +Op88X1mod1: +lbl88mod1: Op88X1 + NEXTOPCODE +Op89M1mod1: +lbl89mod1: Op89M1 + NEXTOPCODE +Op8AM1mod1: +lbl8Amod1: Op8AM1X1 + NEXTOPCODE +Op8Bmod1: +lbl8Bmod1: Op8B + NEXTOPCODE +Op8CX1mod1: +lbl8Cmod1a: Absolute +lbl8Cmod1b: STY8 + NEXTOPCODE +Op8DM1mod1: +lbl8Dmod1a: Absolute +lbl8Dmod1b: STA8 + NEXTOPCODE +Op8EX1mod1: +lbl8Emod1a: Absolute +lbl8Emod1b: STX8 + NEXTOPCODE +Op8FM1mod1: +lbl8Fmod1a: AbsoluteLong +lbl8Fmod1b: STA8 + NEXTOPCODE +Op90mod1: +lbl90mod1: Op90 + NEXTOPCODE +Op91M1mod1: +lbl91mod1a: DirectIndirectIndexed1 +lbl91mod1b: STA8 + NEXTOPCODE +Op92M1mod1: +lbl92mod1a: DirectIndirect +lbl92mod1b: STA8 + NEXTOPCODE +Op93M1mod1: +lbl93mod1a: StackasmRelativeIndirectIndexed1 +lbl93mod1b: STA8 + NEXTOPCODE +Op94X1mod1: +lbl94mod1a: DirectIndexedX1 +lbl94mod1b: STY8 + NEXTOPCODE +Op95M1mod1: +lbl95mod1a: DirectIndexedX1 +lbl95mod1b: STA8 + NEXTOPCODE +Op96X1mod1: +lbl96mod1a: DirectIndexedY1 +lbl96mod1b: STX8 + NEXTOPCODE +Op97M1mod1: +lbl97mod1a: DirectIndirectIndexedLong1 +lbl97mod1b: STA8 + NEXTOPCODE +Op98M1mod1: +lbl98mod1: Op98M1X1 + NEXTOPCODE +Op99M1mod1: +lbl99mod1a: AbsoluteIndexedY1 +lbl99mod1b: STA8 + NEXTOPCODE +Op9Amod1: +lbl9Amod1: Op9AX1 + NEXTOPCODE +Op9BX1mod1: +lbl9Bmod1: Op9BX1 + NEXTOPCODE +Op9CM1mod1: +lbl9Cmod1a: Absolute +lbl9Cmod1b: STZ8 + NEXTOPCODE +Op9DM1mod1: +lbl9Dmod1a: AbsoluteIndexedX1 +lbl9Dmod1b: STA8 + NEXTOPCODE +Op9EM1mod1: +lbl9Emod1: AbsoluteIndexedX1 + STZ8 + NEXTOPCODE +Op9FM1mod1: +lbl9Fmod1a: AbsoluteLongIndexedX1 +lbl9Fmod1b: STA8 + NEXTOPCODE +OpA0X1mod1: +lblA0mod1: OpA0X1 + NEXTOPCODE +OpA1M1mod1: +lblA1mod1a: DirectIndexedIndirect1 +lblA1mod1b: LDA8 + NEXTOPCODE +OpA2X1mod1: +lblA2mod1: OpA2X1 + NEXTOPCODE +OpA3M1mod1: +lblA3mod1a: StackasmRelative +lblA3mod1b: LDA8 + NEXTOPCODE +OpA4X1mod1: +lblA4mod1a: Direct +lblA4mod1b: LDY8 + NEXTOPCODE +OpA5M1mod1: +lblA5mod1a: Direct +lblA5mod1b: LDA8 + NEXTOPCODE +OpA6X1mod1: +lblA6mod1a: Direct +lblA6mod1b: LDX8 + NEXTOPCODE +OpA7M1mod1: +lblA7mod1a: DirectIndirectLong +lblA7mod1b: LDA8 + NEXTOPCODE +OpA8X1mod1: +lblA8mod1: OpA8X1M1 + NEXTOPCODE +OpA9M1mod1: +lblA9mod1: OpA9M1 + NEXTOPCODE +OpAAX1mod1: +lblAAmod1: OpAAX1M1 + NEXTOPCODE +OpABmod1: +lblABmod1: OpAB + NEXTOPCODE +OpACX1mod1: +lblACmod1a: Absolute +lblACmod1b: LDY8 + NEXTOPCODE +OpADM1mod1: +lblADmod1a: Absolute +lblADmod1b: LDA8 + NEXTOPCODE +OpAEX1mod1: +lblAEmod1a: Absolute +lblAEmod1b: LDX8 + NEXTOPCODE +OpAFM1mod1: +lblAFmod1a: AbsoluteLong +lblAFmod1b: LDA8 + NEXTOPCODE +OpB0mod1: +lblB0mod1: OpB0 + NEXTOPCODE +OpB1M1mod1: +lblB1mod1a: DirectIndirectIndexed1 +lblB1mod1b: LDA8 + NEXTOPCODE +OpB2M1mod1: +lblB2mod1a: DirectIndirect +lblB2mod1b: LDA8 + NEXTOPCODE +OpB3M1mod1: +lblB3mod1a: StackasmRelativeIndirectIndexed1 +lblB3mod1b: LDA8 + NEXTOPCODE +OpB4X1mod1: +lblB4mod1a: DirectIndexedX1 +lblB4mod1b: LDY8 + NEXTOPCODE +OpB5M1mod1: +lblB5mod1a: DirectIndexedX1 +lblB5mod1b: LDA8 + NEXTOPCODE +OpB6X1mod1: +lblB6mod1a: DirectIndexedY1 +lblB6mod1b: LDX8 + NEXTOPCODE +OpB7M1mod1: +lblB7mod1a: DirectIndirectIndexedLong1 +lblB7mod1b: LDA8 + NEXTOPCODE +OpB8mod1: +lblB8mod1: OpB8 + NEXTOPCODE +OpB9M1mod1: +lblB9mod1a: AbsoluteIndexedY1 +lblB9mod1b: LDA8 + NEXTOPCODE +OpBAX1mod1: +lblBAmod1: OpBAX1 + NEXTOPCODE +OpBBX1mod1: +lblBBmod1: OpBBX1 + NEXTOPCODE +OpBCX1mod1: +lblBCmod1a: AbsoluteIndexedX1 +lblBCmod1b: LDY8 + NEXTOPCODE +OpBDM1mod1: +lblBDmod1a: AbsoluteIndexedX1 +lblBDmod1b: LDA8 + NEXTOPCODE +OpBEX1mod1: +lblBEmod1a: AbsoluteIndexedY1 +lblBEmod1b: LDX8 + NEXTOPCODE +OpBFM1mod1: +lblBFmod1a: AbsoluteLongIndexedX1 +lblBFmod1b: LDA8 + NEXTOPCODE +OpC0X1mod1: +lblC0mod1: OpC0X1 + NEXTOPCODE +OpC1M1mod1: +lblC1mod1a: DirectIndexedIndirect1 +lblC1mod1b: CMP8 + NEXTOPCODE +OpC2mod1: +lblC2mod1: OpC2 + NEXTOPCODE +.pool +OpC3M1mod1: +lblC3mod1a: StackasmRelative +lblC3mod1b: CMP8 + NEXTOPCODE +OpC4X1mod1: +lblC4mod1a: Direct +lblC4mod1b: CMY8 + NEXTOPCODE +OpC5M1mod1: +lblC5mod1a: Direct +lblC5mod1b: CMP8 + NEXTOPCODE +OpC6M1mod1: +lblC6mod1a: Direct +lblC6mod1b: DEC8 + NEXTOPCODE +OpC7M1mod1: +lblC7mod1a: DirectIndirectLong +lblC7mod1b: CMP8 + NEXTOPCODE +OpC8X1mod1: +lblC8mod1: OpC8X1 + NEXTOPCODE +OpC9M1mod1: +lblC9mod1: OpC9M1 + NEXTOPCODE +OpCAX1mod1: +lblCAmod1: OpCAX1 + NEXTOPCODE +OpCBmod1: +lblCBmod1: OpCB + NEXTOPCODE +OpCCX1mod1: +lblCCmod1a: Absolute +lblCCmod1b: CMY8 + NEXTOPCODE +OpCDM1mod1: +lblCDmod1a: Absolute +lblCDmod1b: CMP8 + NEXTOPCODE +OpCEM1mod1: +lblCEmod1a: Absolute +lblCEmod1b: DEC8 + NEXTOPCODE +OpCFM1mod1: +lblCFmod1a: AbsoluteLong +lblCFmod1b: CMP8 + NEXTOPCODE +OpD0mod1: +lblD0mod1: OpD0 + NEXTOPCODE +OpD1M1mod1: +lblD1mod1a: DirectIndirectIndexed1 +lblD1mod1b: CMP8 + NEXTOPCODE +OpD2M1mod1: +lblD2mod1a: DirectIndirect +lblD2mod1b: CMP8 + NEXTOPCODE +OpD3M1mod1: +lblD3mod1a: StackasmRelativeIndirectIndexed1 +lblD3mod1b: CMP8 + + NEXTOPCODE +OpD4mod1: +lblD4mod1: OpD4 + NEXTOPCODE +OpD5M1mod1: +lblD5mod1a: DirectIndexedX1 +lblD5mod1b: CMP8 + NEXTOPCODE +OpD6M1mod1: +lblD6mod1a: DirectIndexedX1 +lblD6mod1b: DEC8 + NEXTOPCODE +OpD7M1mod1: +lblD7mod1a: DirectIndirectIndexedLong1 +lblD7mod1b: CMP8 + NEXTOPCODE +OpD8mod1: +lblD8mod1: OpD8 + NEXTOPCODE +OpD9M1mod1: +lblD9mod1a: AbsoluteIndexedY1 +lblD9mod1b: CMP8 + NEXTOPCODE +OpDAX1mod1: +lblDAmod1: OpDAX1 + NEXTOPCODE +OpDBmod1: +lblDBmod1: OpDB + NEXTOPCODE +OpDCmod1: +lblDCmod1: OpDC + NEXTOPCODE +OpDDM1mod1: +lblDDmod1a: AbsoluteIndexedX1 +lblDDmod1b: CMP8 + NEXTOPCODE +OpDEM1mod1: +lblDEmod1a: AbsoluteIndexedX1 +lblDEmod1b: DEC8 + NEXTOPCODE +OpDFM1mod1: +lblDFmod1a: AbsoluteLongIndexedX1 +lblDFmod1b: CMP8 + NEXTOPCODE +OpE0X1mod1: +lblE0mod1: OpE0X1 + NEXTOPCODE +OpE1M1mod1: +lblE1mod1a: DirectIndexedIndirect1 +lblE1mod1b: SBC8 + NEXTOPCODE +OpE2mod1: +lblE2mod1: OpE2 + NEXTOPCODE +.pool +OpE3M1mod1: +lblE3mod1a: StackasmRelative +lblE3mod1b: SBC8 + NEXTOPCODE +OpE4X1mod1: +lblE4mod1a: Direct +lblE4mod1b: CMX8 + NEXTOPCODE +OpE5M1mod1: +lblE5mod1a: Direct +lblE5mod1b: SBC8 + NEXTOPCODE +OpE6M1mod1: +lblE6mod1a: Direct +lblE6mod1b: INC8 + NEXTOPCODE +OpE7M1mod1: +lblE7mod1a: DirectIndirectLong +lblE7mod1b: SBC8 + NEXTOPCODE +OpE8X1mod1: +lblE8mod1: OpE8X1 + NEXTOPCODE +OpE9M1mod1: +lblE9mod1a: Immediate8 +lblE9mod1b: SBC8 + NEXTOPCODE +OpEAmod1: +lblEAmod1: OpEA + NEXTOPCODE +OpEBmod1: +lblEBmod1: OpEBM1 + NEXTOPCODE +OpECX1mod1: +lblECmod1a: Absolute +lblECmod1b: CMX8 + NEXTOPCODE +OpEDM1mod1: +lblEDmod1a: Absolute +lblEDmod1b: SBC8 + NEXTOPCODE +OpEEM1mod1: +lblEEmod1a: Absolute +lblEEmod1b: INC8 + NEXTOPCODE +OpEFM1mod1: +lblEFmod1a: AbsoluteLong +lblEFmod1b: SBC8 + NEXTOPCODE +OpF0mod1: +lblF0mod1: OpF0 + NEXTOPCODE +OpF1M1mod1: +lblF1mod1a: DirectIndirectIndexed1 +lblF1mod1b: SBC8 + NEXTOPCODE +OpF2M1mod1: +lblF2mod1a: DirectIndirect +lblF2mod1b: SBC8 + NEXTOPCODE +OpF3M1mod1: +lblF3mod1a: StackasmRelativeIndirectIndexed1 +lblF3mod1b: SBC8 + NEXTOPCODE +OpF4mod1: +lblF4mod1: OpF4 + NEXTOPCODE +OpF5M1mod1: +lblF5mod1a: DirectIndexedX1 +lblF5mod1b: SBC8 + NEXTOPCODE +OpF6M1mod1: +lblF6mod1a: DirectIndexedX1 +lblF6mod1b: INC8 + NEXTOPCODE +OpF7M1mod1: +lblF7mod1a: DirectIndirectIndexedLong1 +lblF7mod1b: SBC8 + NEXTOPCODE +OpF8mod1: +lblF8mod1: OpF8 + NEXTOPCODE +OpF9M1mod1: +lblF9mod1a: AbsoluteIndexedY1 +lblF9mod1b: SBC8 + NEXTOPCODE +OpFAX1mod1: +lblFAmod1: OpFAX1 + NEXTOPCODE +OpFBmod1: +lblFBmod1: OpFB + NEXTOPCODE +OpFCmod1: +lblFCmod1: OpFCX1 + NEXTOPCODE +OpFDM1mod1: +lblFDmod1a: AbsoluteIndexedX1 +lblFDmod1b: SBC8 + NEXTOPCODE +OpFEM1mod1: +lblFEmod1a: AbsoluteIndexedX1 +lblFEmod1b: INC8 + NEXTOPCODE +OpFFM1mod1: +lblFFmod1a: AbsoluteLongIndexedX1 +lblFFmod1b: SBC8 + NEXTOPCODE +.pool + + +jumptable2: .long Op00mod2 + .long Op01M1mod2 + .long Op02mod2 + .long Op03M1mod2 + .long Op04M1mod2 + .long Op05M1mod2 + .long Op06M1mod2 + .long Op07M1mod2 + .long Op08mod2 + .long Op09M1mod2 + .long Op0AM1mod2 + .long Op0Bmod2 + .long Op0CM1mod2 + .long Op0DM1mod2 + .long Op0EM1mod2 + .long Op0FM1mod2 + .long Op10mod2 + .long Op11M1mod2 + .long Op12M1mod2 + .long Op13M1mod2 + .long Op14M1mod2 + .long Op15M1mod2 + .long Op16M1mod2 + .long Op17M1mod2 + .long Op18mod2 + .long Op19M1mod2 + .long Op1AM1mod2 + .long Op1Bmod2 + .long Op1CM1mod2 + .long Op1DM1mod2 + .long Op1EM1mod2 + .long Op1FM1mod2 + .long Op20mod2 + .long Op21M1mod2 + .long Op22mod2 + .long Op23M1mod2 + .long Op24M1mod2 + .long Op25M1mod2 + .long Op26M1mod2 + .long Op27M1mod2 + .long Op28mod2 + .long Op29M1mod2 + .long Op2AM1mod2 + .long Op2Bmod2 + .long Op2CM1mod2 + .long Op2DM1mod2 + .long Op2EM1mod2 + .long Op2FM1mod2 + .long Op30mod2 + .long Op31M1mod2 + .long Op32M1mod2 + .long Op33M1mod2 + .long Op34M1mod2 + .long Op35M1mod2 + .long Op36M1mod2 + .long Op37M1mod2 + .long Op38mod2 + .long Op39M1mod2 + .long Op3AM1mod2 + .long Op3Bmod2 + .long Op3CM1mod2 + .long Op3DM1mod2 + .long Op3EM1mod2 + .long Op3FM1mod2 + .long Op40mod2 + .long Op41M1mod2 + .long Op42mod2 + .long Op43M1mod2 + .long Op44X0mod2 + .long Op45M1mod2 + .long Op46M1mod2 + .long Op47M1mod2 + .long Op48M1mod2 + .long Op49M1mod2 + .long Op4AM1mod2 + .long Op4Bmod2 + .long Op4Cmod2 + .long Op4DM1mod2 + .long Op4EM1mod2 + .long Op4FM1mod2 + .long Op50mod2 + .long Op51M1mod2 + .long Op52M1mod2 + .long Op53M1mod2 + .long Op54X0mod2 + .long Op55M1mod2 + .long Op56M1mod2 + .long Op57M1mod2 + .long Op58mod2 + .long Op59M1mod2 + .long Op5AX0mod2 + .long Op5Bmod2 + .long Op5Cmod2 + .long Op5DM1mod2 + .long Op5EM1mod2 + .long Op5FM1mod2 + .long Op60mod2 + .long Op61M1mod2 + .long Op62mod2 + .long Op63M1mod2 + .long Op64M1mod2 + .long Op65M1mod2 + .long Op66M1mod2 + .long Op67M1mod2 + .long Op68M1mod2 + .long Op69M1mod2 + .long Op6AM1mod2 + .long Op6Bmod2 + .long Op6Cmod2 + .long Op6DM1mod2 + .long Op6EM1mod2 + .long Op6FM1mod2 + .long Op70mod2 + .long Op71M1mod2 + .long Op72M1mod2 + .long Op73M1mod2 + .long Op74M1mod2 + .long Op75M1mod2 + .long Op76M1mod2 + .long Op77M1mod2 + .long Op78mod2 + .long Op79M1mod2 + .long Op7AX0mod2 + .long Op7Bmod2 + .long Op7Cmod2 + .long Op7DM1mod2 + .long Op7EM1mod2 + .long Op7FM1mod2 + .long Op80mod2 + .long Op81M1mod2 + .long Op82mod2 + .long Op83M1mod2 + .long Op84X0mod2 + .long Op85M1mod2 + .long Op86X0mod2 + .long Op87M1mod2 + .long Op88X0mod2 + .long Op89M1mod2 + .long Op8AM1mod2 + .long Op8Bmod2 + .long Op8CX0mod2 + .long Op8DM1mod2 + .long Op8EX0mod2 + .long Op8FM1mod2 + .long Op90mod2 + .long Op91M1mod2 + .long Op92M1mod2 + .long Op93M1mod2 + .long Op94X0mod2 + .long Op95M1mod2 + .long Op96X0mod2 + .long Op97M1mod2 + .long Op98M1mod2 + .long Op99M1mod2 + .long Op9Amod2 + .long Op9BX0mod2 + .long Op9CM1mod2 + .long Op9DM1mod2 + .long Op9EM1mod2 + .long Op9FM1mod2 + .long OpA0X0mod2 + .long OpA1M1mod2 + .long OpA2X0mod2 + .long OpA3M1mod2 + .long OpA4X0mod2 + .long OpA5M1mod2 + .long OpA6X0mod2 + .long OpA7M1mod2 + .long OpA8X0mod2 + .long OpA9M1mod2 + .long OpAAX0mod2 + .long OpABmod2 + .long OpACX0mod2 + .long OpADM1mod2 + .long OpAEX0mod2 + .long OpAFM1mod2 + .long OpB0mod2 + .long OpB1M1mod2 + .long OpB2M1mod2 + .long OpB3M1mod2 + .long OpB4X0mod2 + .long OpB5M1mod2 + .long OpB6X0mod2 + .long OpB7M1mod2 + .long OpB8mod2 + .long OpB9M1mod2 + .long OpBAX0mod2 + .long OpBBX0mod2 + .long OpBCX0mod2 + .long OpBDM1mod2 + .long OpBEX0mod2 + .long OpBFM1mod2 + .long OpC0X0mod2 + .long OpC1M1mod2 + .long OpC2mod2 + .long OpC3M1mod2 + .long OpC4X0mod2 + .long OpC5M1mod2 + .long OpC6M1mod2 + .long OpC7M1mod2 + .long OpC8X0mod2 + .long OpC9M1mod2 + .long OpCAX0mod2 + .long OpCBmod2 + .long OpCCX0mod2 + .long OpCDM1mod2 + .long OpCEM1mod2 + .long OpCFM1mod2 + .long OpD0mod2 + .long OpD1M1mod2 + .long OpD2M1mod2 + .long OpD3M1mod2 + .long OpD4mod2 + .long OpD5M1mod2 + .long OpD6M1mod2 + .long OpD7M1mod2 + .long OpD8mod2 + .long OpD9M1mod2 + .long OpDAX0mod2 + .long OpDBmod2 + .long OpDCmod2 + .long OpDDM1mod2 + .long OpDEM1mod2 + .long OpDFM1mod2 + .long OpE0X0mod2 + .long OpE1M1mod2 + .long OpE2mod2 + .long OpE3M1mod2 + .long OpE4X0mod2 + .long OpE5M1mod2 + .long OpE6M1mod2 + .long OpE7M1mod2 + .long OpE8X0mod2 + .long OpE9M1mod2 + .long OpEAmod2 + .long OpEBmod2 + .long OpECX0mod2 + .long OpEDM1mod2 + .long OpEEM1mod2 + .long OpEFM1mod2 + .long OpF0mod2 + .long OpF1M1mod2 + .long OpF2M1mod2 + .long OpF3M1mod2 + .long OpF4mod2 + .long OpF5M1mod2 + .long OpF6M1mod2 + .long OpF7M1mod2 + .long OpF8mod2 + .long OpF9M1mod2 + .long OpFAX0mod2 + .long OpFBmod2 + .long OpFCmod2 + .long OpFDM1mod2 + .long OpFEM1mod2 + .long OpFFM1mod2 +Op00mod2: +lbl00mod2: Op00 + NEXTOPCODE +Op01M1mod2: +lbl01mod2a: DirectIndexedIndirect0 +lbl01mod2b: ORA8 + NEXTOPCODE +Op02mod2: +lbl02mod2: Op02 + NEXTOPCODE +Op03M1mod2: +lbl03mod2a: StackasmRelative +lbl03mod2b: ORA8 + NEXTOPCODE +Op04M1mod2: +lbl04mod2a: Direct +lbl04mod2b: TSB8 + NEXTOPCODE +Op05M1mod2: +lbl05mod2a: Direct +lbl05mod2b: ORA8 + NEXTOPCODE +Op06M1mod2: +lbl06mod2a: Direct +lbl06mod2b: ASL8 + NEXTOPCODE +Op07M1mod2: +lbl07mod2a: DirectIndirectLong +lbl07mod2b: ORA8 + NEXTOPCODE +Op08mod2: + +lbl08mod2: Op08 + NEXTOPCODE +Op09M1mod2: +lbl09mod2: Op09M1 + NEXTOPCODE +Op0AM1mod2: +lbl0Amod2a: A_ASL8 + NEXTOPCODE +Op0Bmod2: +lbl0Bmod2: Op0B + NEXTOPCODE +Op0CM1mod2: +lbl0Cmod2a: Absolute +lbl0Cmod2b: TSB8 + NEXTOPCODE +Op0DM1mod2: +lbl0Dmod2a: Absolute +lbl0Dmod2b: ORA8 + NEXTOPCODE +Op0EM1mod2: +lbl0Emod2a: Absolute +lbl0Emod2b: ASL8 + NEXTOPCODE +Op0FM1mod2: +lbl0Fmod2a: AbsoluteLong +lbl0Fmod2b: ORA8 + NEXTOPCODE +Op10mod2: +lbl10mod2: Op10 + NEXTOPCODE +Op11M1mod2: +lbl11mod2a: DirectIndirectIndexed0 +lbl11mod2b: ORA8 + NEXTOPCODE +Op12M1mod2: +lbl12mod2a: DirectIndirect +lbl12mod2b: ORA8 + NEXTOPCODE +Op13M1mod2: +lbl13mod2a: StackasmRelativeIndirectIndexed0 +lbl13mod2b: ORA8 + NEXTOPCODE +Op14M1mod2: +lbl14mod2a: Direct +lbl14mod2b: TRB8 + NEXTOPCODE +Op15M1mod2: +lbl15mod2a: DirectIndexedX0 +lbl15mod2b: ORA8 + NEXTOPCODE +Op16M1mod2: +lbl16mod2a: DirectIndexedX0 +lbl16mod2b: ASL8 + NEXTOPCODE +Op17M1mod2: +lbl17mod2a: DirectIndirectIndexedLong0 +lbl17mod2b: ORA8 + NEXTOPCODE +Op18mod2: +lbl18mod2: Op18 + NEXTOPCODE +Op19M1mod2: +lbl19mod2a: AbsoluteIndexedY0 +lbl19mod2b: ORA8 + NEXTOPCODE +Op1AM1mod2: +lbl1Amod2a: A_INC8 + NEXTOPCODE +Op1Bmod2: +lbl1Bmod2: Op1BM1 + NEXTOPCODE +Op1CM1mod2: +lbl1Cmod2a: Absolute +lbl1Cmod2b: TRB8 + NEXTOPCODE +Op1DM1mod2: +lbl1Dmod2a: AbsoluteIndexedX0 +lbl1Dmod2b: ORA8 + NEXTOPCODE +Op1EM1mod2: +lbl1Emod2a: AbsoluteIndexedX0 +lbl1Emod2b: ASL8 + NEXTOPCODE +Op1FM1mod2: +lbl1Fmod2a: AbsoluteLongIndexedX0 +lbl1Fmod2b: ORA8 + NEXTOPCODE +Op20mod2: +lbl20mod2: Op20 + NEXTOPCODE +Op21M1mod2: +lbl21mod2a: DirectIndexedIndirect0 +lbl21mod2b: AND8 + NEXTOPCODE +Op22mod2: +lbl22mod2: Op22 + NEXTOPCODE +Op23M1mod2: +lbl23mod2a: StackasmRelative +lbl23mod2b: AND8 + NEXTOPCODE +Op24M1mod2: +lbl24mod2a: Direct +lbl24mod2b: BIT8 + NEXTOPCODE +Op25M1mod2: +lbl25mod2a: Direct +lbl25mod2b: AND8 + NEXTOPCODE +Op26M1mod2: +lbl26mod2a: Direct +lbl26mod2b: ROL8 + NEXTOPCODE +Op27M1mod2: +lbl27mod2a: DirectIndirectLong +lbl27mod2b: AND8 + NEXTOPCODE +Op28mod2: +lbl28mod2: Op28X0M1 + NEXTOPCODE +.pool +Op29M1mod2: +lbl29mod2: Op29M1 + NEXTOPCODE +Op2AM1mod2: +lbl2Amod2a: A_ROL8 + NEXTOPCODE +Op2Bmod2: +lbl2Bmod2: Op2B + NEXTOPCODE +Op2CM1mod2: +lbl2Cmod2a: Absolute +lbl2Cmod2b: BIT8 + NEXTOPCODE +Op2DM1mod2: +lbl2Dmod2a: Absolute +lbl2Dmod2b: AND8 + NEXTOPCODE +Op2EM1mod2: +lbl2Emod2a: Absolute +lbl2Emod2b: ROL8 + NEXTOPCODE +Op2FM1mod2: +lbl2Fmod2a: AbsoluteLong +lbl2Fmod2b: AND8 + NEXTOPCODE +Op30mod2: +lbl30mod2: Op30 + NEXTOPCODE +Op31M1mod2: +lbl31mod2a: DirectIndirectIndexed0 +lbl31mod2b: AND8 + NEXTOPCODE +Op32M1mod2: +lbl32mod2a: DirectIndirect +lbl32mod2b: AND8 + NEXTOPCODE +Op33M1mod2: +lbl33mod2a: StackasmRelativeIndirectIndexed0 +lbl33mod2b: AND8 + NEXTOPCODE +Op34M1mod2: +lbl34mod2a: DirectIndexedX0 +lbl34mod2b: BIT8 + NEXTOPCODE +Op35M1mod2: +lbl35mod2a: DirectIndexedX0 +lbl35mod2b: AND8 + NEXTOPCODE +Op36M1mod2: +lbl36mod2a: DirectIndexedX0 +lbl36mod2b: ROL8 + NEXTOPCODE +Op37M1mod2: +lbl37mod2a: DirectIndirectIndexedLong0 +lbl37mod2b: AND8 + NEXTOPCODE +Op38mod2: +lbl38mod2: Op38 + NEXTOPCODE +Op39M1mod2: +lbl39mod2a: AbsoluteIndexedY0 +lbl39mod2b: AND8 + NEXTOPCODE +Op3AM1mod2: +lbl3Amod2a: A_DEC8 + NEXTOPCODE +Op3Bmod2: +lbl3Bmod2: Op3BM1 + NEXTOPCODE +Op3CM1mod2: +lbl3Cmod2a: AbsoluteIndexedX0 +lbl3Cmod2b: BIT8 + NEXTOPCODE +Op3DM1mod2: +lbl3Dmod2a: AbsoluteIndexedX0 +lbl3Dmod2b: AND8 + NEXTOPCODE +Op3EM1mod2: +lbl3Emod2a: AbsoluteIndexedX0 +lbl3Emod2b: ROL8 + NEXTOPCODE +Op3FM1mod2: +lbl3Fmod2a: AbsoluteLongIndexedX0 +lbl3Fmod2b: AND8 + NEXTOPCODE +Op40mod2: +lbl40mod2: Op40X0M1 + NEXTOPCODE +.pool +Op41M1mod2: +lbl41mod2a: DirectIndexedIndirect0 +lbl41mod2b: EOR8 + NEXTOPCODE +Op42mod2: +lbl42mod2: Op42 + NEXTOPCODE +Op43M1mod2: +lbl43mod2a: StackasmRelative +lbl43mod2b: EOR8 + NEXTOPCODE +Op44X0mod2: +lbl44mod2: Op44X0M1 + NEXTOPCODE +Op45M1mod2: +lbl45mod2a: Direct +lbl45mod2b: EOR8 + NEXTOPCODE +Op46M1mod2: +lbl46mod2a: Direct +lbl46mod2b: LSR8 + NEXTOPCODE +Op47M1mod2: +lbl47mod2a: DirectIndirectLong +lbl47mod2b: EOR8 + NEXTOPCODE +Op48M1mod2: +lbl48mod2: Op48M1 + NEXTOPCODE +Op49M1mod2: +lbl49mod2: Op49M1 + NEXTOPCODE +Op4AM1mod2: +lbl4Amod2a: A_LSR8 + NEXTOPCODE +Op4Bmod2: +lbl4Bmod2: Op4B + NEXTOPCODE +Op4Cmod2: +lbl4Cmod2: Op4C + NEXTOPCODE +Op4DM1mod2: +lbl4Dmod2a: Absolute +lbl4Dmod2b: EOR8 + NEXTOPCODE +Op4EM1mod2: +lbl4Emod2a: Absolute +lbl4Emod2b: LSR8 + NEXTOPCODE +Op4FM1mod2: +lbl4Fmod2a: AbsoluteLong +lbl4Fmod2b: EOR8 + NEXTOPCODE +Op50mod2: +lbl50mod2: Op50 + NEXTOPCODE +Op51M1mod2: +lbl51mod2a: DirectIndirectIndexed0 +lbl51mod2b: EOR8 + NEXTOPCODE +Op52M1mod2: +lbl52mod2a: DirectIndirect +lbl52mod2b: EOR8 + NEXTOPCODE +Op53M1mod2: +lbl53mod2a: StackasmRelativeIndirectIndexed0 +lbl53mod2b: EOR8 + NEXTOPCODE +Op54X0mod2: +lbl54mod2: Op54X0M1 + NEXTOPCODE +Op55M1mod2: +lbl55mod2a: DirectIndexedX0 +lbl55mod2b: EOR8 + NEXTOPCODE +Op56M1mod2: +lbl56mod2a: DirectIndexedX0 +lbl56mod2b: LSR8 + NEXTOPCODE +Op57M1mod2: +lbl57mod2a: DirectIndirectIndexedLong0 +lbl57mod2b: EOR8 + NEXTOPCODE +Op58mod2: +lbl58mod2: Op58 + NEXTOPCODE +Op59M1mod2: +lbl59mod2a: AbsoluteIndexedY0 +lbl59mod2b: EOR8 + NEXTOPCODE +Op5AX0mod2: +lbl5Amod2: Op5AX0 + NEXTOPCODE +Op5Bmod2: +lbl5Bmod2: Op5BM1 + NEXTOPCODE +Op5Cmod2: +lbl5Cmod2: Op5C + NEXTOPCODE +Op5DM1mod2: +lbl5Dmod2a: AbsoluteIndexedX0 +lbl5Dmod2b: EOR8 + NEXTOPCODE +Op5EM1mod2: +lbl5Emod2a: AbsoluteIndexedX0 +lbl5Emod2b: LSR8 + NEXTOPCODE +Op5FM1mod2: +lbl5Fmod2a: AbsoluteLongIndexedX0 +lbl5Fmod2b: EOR8 + NEXTOPCODE +Op60mod2: +lbl60mod2: Op60 + NEXTOPCODE +Op61M1mod2: +lbl61mod2a: DirectIndexedIndirect0 +lbl61mod2b: ADC8 + NEXTOPCODE +Op62mod2: +lbl62mod2: Op62 + NEXTOPCODE +Op63M1mod2: +lbl63mod2a: StackasmRelative +lbl63mod2b: ADC8 + NEXTOPCODE +Op64M1mod2: +lbl64mod2a: Direct +lbl64mod2b: STZ8 + NEXTOPCODE +Op65M1mod2: +lbl65mod2a: Direct +lbl65mod2b: ADC8 + NEXTOPCODE +Op66M1mod2: +lbl66mod2a: Direct +lbl66mod2b: ROR8 + NEXTOPCODE +Op67M1mod2: +lbl67mod2a: DirectIndirectLong +lbl67mod2b: ADC8 + NEXTOPCODE +Op68M1mod2: +lbl68mod2: Op68M1 + NEXTOPCODE +Op69M1mod2: +lbl69mod2a: Immediate8 +lbl69mod2b: ADC8 + NEXTOPCODE +Op6AM1mod2: +lbl6Amod2a: A_ROR8 + NEXTOPCODE +Op6Bmod2: +lbl6Bmod2: Op6B + NEXTOPCODE +Op6Cmod2: +lbl6Cmod2: Op6C + NEXTOPCODE +Op6DM1mod2: +lbl6Dmod2a: Absolute +lbl6Dmod2b: ADC8 + NEXTOPCODE +Op6EM1mod2: +lbl6Emod2a: Absolute +lbl6Emod2b: ROR8 + NEXTOPCODE +Op6FM1mod2: +lbl6Fmod2a: AbsoluteLong +lbl6Fmod2b: ADC8 + NEXTOPCODE +Op70mod2: +lbl70mod2: Op70 + NEXTOPCODE +Op71M1mod2: +lbl71mod2a: DirectIndirectIndexed0 +lbl71mod2b: ADC8 + NEXTOPCODE +Op72M1mod2: +lbl72mod2a: DirectIndirect +lbl72mod2b: ADC8 + NEXTOPCODE +Op73M1mod2: +lbl73mod2a: StackasmRelativeIndirectIndexed0 +lbl73mod2b: ADC8 + NEXTOPCODE +Op74M1mod2: +lbl74mod2a: DirectIndexedX0 +lbl74mod2b: STZ8 + NEXTOPCODE +Op75M1mod2: +lbl75mod2a: DirectIndexedX0 +lbl75mod2b: ADC8 + NEXTOPCODE +Op76M1mod2: +lbl76mod2a: DirectIndexedX0 +lbl76mod2b: ROR8 + NEXTOPCODE +Op77M1mod2: +lbl77mod2a: DirectIndirectIndexedLong0 +lbl77mod2b: ADC8 + NEXTOPCODE +Op78mod2: +lbl78mod2: Op78 + NEXTOPCODE +Op79M1mod2: +lbl79mod2a: AbsoluteIndexedY0 +lbl79mod2b: ADC8 + NEXTOPCODE +Op7AX0mod2: +lbl7Amod2: Op7AX0 + NEXTOPCODE +Op7Bmod2: +lbl7Bmod2: Op7BM1 + NEXTOPCODE +Op7Cmod2: +lbl7Cmod2: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE +Op7DM1mod2: +lbl7Dmod2a: AbsoluteIndexedX0 +lbl7Dmod2b: ADC8 + NEXTOPCODE +Op7EM1mod2: +lbl7Emod2a: AbsoluteIndexedX0 +lbl7Emod2b: ROR8 + NEXTOPCODE +Op7FM1mod2: +lbl7Fmod2a: AbsoluteLongIndexedX0 +lbl7Fmod2b: ADC8 + NEXTOPCODE + + +Op80mod2: +lbl80mod2: Op80 + NEXTOPCODE +Op81M1mod2: +lbl81mod2a: DirectIndexedIndirect0 +lbl81mod2b: Op81M1 + NEXTOPCODE +Op82mod2: +lbl82mod2: Op82 + NEXTOPCODE +Op83M1mod2: +lbl83mod2a: StackasmRelative +lbl83mod2b: STA8 + NEXTOPCODE +Op84X0mod2: +lbl84mod2a: Direct +lbl84mod2b: STY16 + NEXTOPCODE +Op85M1mod2: +lbl85mod2a: Direct +lbl85mod2b: STA8 + NEXTOPCODE +Op86X0mod2: +lbl86mod2a: Direct +lbl86mod2b: STX16 + NEXTOPCODE +Op87M1mod2: +lbl87mod2a: DirectIndirectLong +lbl87mod2b: STA8 + NEXTOPCODE +Op88X0mod2: +lbl88mod2: Op88X0 + NEXTOPCODE +Op89M1mod2: +lbl89mod2: Op89M1 + NEXTOPCODE +Op8AM1mod2: +lbl8Amod2: Op8AM1X0 + NEXTOPCODE +Op8Bmod2: +lbl8Bmod2: Op8B + NEXTOPCODE +Op8CX0mod2: +lbl8Cmod2a: Absolute +lbl8Cmod2b: STY16 + NEXTOPCODE +Op8DM1mod2: +lbl8Dmod2a: Absolute +lbl8Dmod2b: STA8 + NEXTOPCODE +Op8EX0mod2: +lbl8Emod2a: Absolute +lbl8Emod2b: STX16 + NEXTOPCODE +Op8FM1mod2: +lbl8Fmod2a: AbsoluteLong +lbl8Fmod2b: STA8 + NEXTOPCODE +Op90mod2: +lbl90mod2: Op90 + NEXTOPCODE +Op91M1mod2: +lbl91mod2a: DirectIndirectIndexed0 +lbl91mod2b: STA8 + NEXTOPCODE +Op92M1mod2: +lbl92mod2a: DirectIndirect +lbl92mod2b: STA8 + NEXTOPCODE +Op93M1mod2: +lbl93mod2a: StackasmRelativeIndirectIndexed0 +lbl93mod2b: STA8 + NEXTOPCODE +Op94X0mod2: +lbl94mod2a: DirectIndexedX0 +lbl94mod2b: STY16 + NEXTOPCODE +Op95M1mod2: + +lbl95mod2a: DirectIndexedX0 +lbl95mod2b: STA8 + NEXTOPCODE +Op96X0mod2: +lbl96mod2a: DirectIndexedY0 +lbl96mod2b: STX16 + NEXTOPCODE +Op97M1mod2: +lbl97mod2a: DirectIndirectIndexedLong0 +lbl97mod2b: STA8 + NEXTOPCODE +Op98M1mod2: +lbl98mod2: Op98M1X0 + NEXTOPCODE +Op99M1mod2: +lbl99mod2a: AbsoluteIndexedY0 +lbl99mod2b: STA8 + NEXTOPCODE +Op9Amod2: +lbl9Amod2: Op9AX0 + NEXTOPCODE +Op9BX0mod2: +lbl9Bmod2: Op9BX0 + NEXTOPCODE +Op9CM1mod2: +lbl9Cmod2a: Absolute +lbl9Cmod2b: STZ8 + NEXTOPCODE +Op9DM1mod2: +lbl9Dmod2a: AbsoluteIndexedX0 +lbl9Dmod2b: STA8 + NEXTOPCODE +Op9EM1mod2: +lbl9Emod2: AbsoluteIndexedX0 + STZ8 + NEXTOPCODE +Op9FM1mod2: +lbl9Fmod2a: AbsoluteLongIndexedX0 +lbl9Fmod2b: STA8 + NEXTOPCODE +OpA0X0mod2: +lblA0mod2: OpA0X0 + NEXTOPCODE +OpA1M1mod2: +lblA1mod2a: DirectIndexedIndirect0 +lblA1mod2b: LDA8 + NEXTOPCODE +OpA2X0mod2: +lblA2mod2: OpA2X0 + NEXTOPCODE +OpA3M1mod2: +lblA3mod2a: StackasmRelative +lblA3mod2b: LDA8 + NEXTOPCODE +OpA4X0mod2: +lblA4mod2a: Direct +lblA4mod2b: LDY16 + NEXTOPCODE +OpA5M1mod2: +lblA5mod2a: Direct +lblA5mod2b: LDA8 + NEXTOPCODE +OpA6X0mod2: +lblA6mod2a: Direct +lblA6mod2b: LDX16 + NEXTOPCODE +OpA7M1mod2: +lblA7mod2a: DirectIndirectLong +lblA7mod2b: LDA8 + NEXTOPCODE +OpA8X0mod2: +lblA8mod2: OpA8X0M1 + NEXTOPCODE +OpA9M1mod2: +lblA9mod2: OpA9M1 + NEXTOPCODE +OpAAX0mod2: +lblAAmod2: OpAAX0M1 + NEXTOPCODE +OpABmod2: +lblABmod2: OpAB + NEXTOPCODE +OpACX0mod2: +lblACmod2a: Absolute +lblACmod2b: LDY16 + NEXTOPCODE +OpADM1mod2: +lblADmod2a: Absolute +lblADmod2b: LDA8 + NEXTOPCODE +OpAEX0mod2: +lblAEmod2a: Absolute +lblAEmod2b: LDX16 + NEXTOPCODE +OpAFM1mod2: +lblAFmod2a: AbsoluteLong +lblAFmod2b: LDA8 + NEXTOPCODE +OpB0mod2: +lblB0mod2: OpB0 + NEXTOPCODE +OpB1M1mod2: +lblB1mod2a: DirectIndirectIndexed0 +lblB1mod2b: LDA8 + NEXTOPCODE +OpB2M1mod2: +lblB2mod2a: DirectIndirect +lblB2mod2b: LDA8 + NEXTOPCODE +OpB3M1mod2: +lblB3mod2a: StackasmRelativeIndirectIndexed0 +lblB3mod2b: LDA8 + NEXTOPCODE +OpB4X0mod2: +lblB4mod2a: DirectIndexedX0 +lblB4mod2b: LDY16 + NEXTOPCODE +OpB5M1mod2: +lblB5mod2a: DirectIndexedX0 +lblB5mod2b: LDA8 + NEXTOPCODE +OpB6X0mod2: +lblB6mod2a: DirectIndexedY0 +lblB6mod2b: LDX16 + NEXTOPCODE +OpB7M1mod2: +lblB7mod2a: DirectIndirectIndexedLong0 +lblB7mod2b: LDA8 + NEXTOPCODE +OpB8mod2: +lblB8mod2: OpB8 + NEXTOPCODE +OpB9M1mod2: +lblB9mod2a: AbsoluteIndexedY0 +lblB9mod2b: LDA8 + NEXTOPCODE +OpBAX0mod2: +lblBAmod2: OpBAX0 + NEXTOPCODE +OpBBX0mod2: +lblBBmod2: OpBBX0 + NEXTOPCODE +OpBCX0mod2: +lblBCmod2a: AbsoluteIndexedX0 +lblBCmod2b: LDY16 + NEXTOPCODE +OpBDM1mod2: +lblBDmod2a: AbsoluteIndexedX0 +lblBDmod2b: LDA8 + NEXTOPCODE +OpBEX0mod2: +lblBEmod2a: AbsoluteIndexedY0 +lblBEmod2b: LDX16 + NEXTOPCODE +OpBFM1mod2: +lblBFmod2a: AbsoluteLongIndexedX0 +lblBFmod2b: LDA8 + NEXTOPCODE +OpC0X0mod2: +lblC0mod2: OpC0X0 + NEXTOPCODE +OpC1M1mod2: +lblC1mod2a: DirectIndexedIndirect0 +lblC1mod2b: CMP8 + NEXTOPCODE +OpC2mod2: +lblC2mod2: OpC2 + NEXTOPCODE +.pool +OpC3M1mod2: +lblC3mod2a: StackasmRelative +lblC3mod2b: CMP8 + NEXTOPCODE +OpC4X0mod2: +lblC4mod2a: Direct +lblC4mod2b: CMY16 + NEXTOPCODE +OpC5M1mod2: +lblC5mod2a: Direct +lblC5mod2b: CMP8 + NEXTOPCODE +OpC6M1mod2: +lblC6mod2a: Direct +lblC6mod2b: DEC8 + NEXTOPCODE +OpC7M1mod2: +lblC7mod2a: DirectIndirectLong +lblC7mod2b: CMP8 + NEXTOPCODE +OpC8X0mod2: +lblC8mod2: OpC8X0 + NEXTOPCODE +OpC9M1mod2: +lblC9mod2: OpC9M1 + NEXTOPCODE +OpCAX0mod2: +lblCAmod2: OpCAX0 + NEXTOPCODE +OpCBmod2: +lblCBmod2: OpCB + NEXTOPCODE +OpCCX0mod2: +lblCCmod2a: Absolute +lblCCmod2b: CMY16 + NEXTOPCODE +OpCDM1mod2: +lblCDmod2a: Absolute +lblCDmod2b: CMP8 + NEXTOPCODE +OpCEM1mod2: +lblCEmod2a: Absolute +lblCEmod2b: DEC8 + NEXTOPCODE +OpCFM1mod2: +lblCFmod2a: AbsoluteLong +lblCFmod2b: CMP8 + NEXTOPCODE +OpD0mod2: +lblD0mod2: OpD0 + NEXTOPCODE +OpD1M1mod2: +lblD1mod2a: DirectIndirectIndexed0 +lblD1mod2b: CMP8 + NEXTOPCODE +OpD2M1mod2: +lblD2mod2a: DirectIndirect +lblD2mod2b: CMP8 + NEXTOPCODE +OpD3M1mod2: +lblD3mod2a: StackasmRelativeIndirectIndexed0 +lblD3mod2b: CMP8 + NEXTOPCODE +OpD4mod2: +lblD4mod2: OpD4 + NEXTOPCODE +OpD5M1mod2: +lblD5mod2a: DirectIndexedX0 +lblD5mod2b: CMP8 + NEXTOPCODE +OpD6M1mod2: +lblD6mod2a: DirectIndexedX0 +lblD6mod2b: DEC8 + NEXTOPCODE +OpD7M1mod2: +lblD7mod2a: DirectIndirectIndexedLong0 +lblD7mod2b: CMP8 + NEXTOPCODE +OpD8mod2: +lblD8mod2: OpD8 + NEXTOPCODE +OpD9M1mod2: +lblD9mod2a: AbsoluteIndexedY0 +lblD9mod2b: CMP8 + NEXTOPCODE +OpDAX0mod2: +lblDAmod2: OpDAX0 + NEXTOPCODE +OpDBmod2: +lblDBmod2: OpDB + NEXTOPCODE +OpDCmod2: +lblDCmod2: OpDC + NEXTOPCODE +OpDDM1mod2: +lblDDmod2a: AbsoluteIndexedX0 +lblDDmod2b: CMP8 + NEXTOPCODE +OpDEM1mod2: +lblDEmod2a: AbsoluteIndexedX0 +lblDEmod2b: DEC8 + NEXTOPCODE +OpDFM1mod2: +lblDFmod2a: AbsoluteLongIndexedX0 +lblDFmod2b: CMP8 + NEXTOPCODE +OpE0X0mod2: +lblE0mod2: OpE0X0 + NEXTOPCODE +OpE1M1mod2: +lblE1mod2a: DirectIndexedIndirect0 +lblE1mod2b: SBC8 + NEXTOPCODE +OpE2mod2: +lblE2mod2: OpE2 + NEXTOPCODE +.pool +OpE3M1mod2: +lblE3mod2a: StackasmRelative +lblE3mod2b: SBC8 + NEXTOPCODE +OpE4X0mod2: +lblE4mod2a: Direct +lblE4mod2b: CMX16 + NEXTOPCODE +OpE5M1mod2: +lblE5mod2a: Direct +lblE5mod2b: SBC8 + NEXTOPCODE +OpE6M1mod2: +lblE6mod2a: Direct +lblE6mod2b: INC8 + NEXTOPCODE +OpE7M1mod2: +lblE7mod2a: DirectIndirectLong +lblE7mod2b: SBC8 + NEXTOPCODE +OpE8X0mod2: +lblE8mod2: OpE8X0 + NEXTOPCODE +OpE9M1mod2: +lblE9mod2a: Immediate8 +lblE9mod2b: SBC8 + NEXTOPCODE +OpEAmod2: +lblEAmod2: OpEA + NEXTOPCODE +OpEBmod2: +lblEBmod2: OpEBM1 + NEXTOPCODE +OpECX0mod2: +lblECmod2a: Absolute +lblECmod2b: CMX16 + NEXTOPCODE +OpEDM1mod2: +lblEDmod2a: Absolute +lblEDmod2b: SBC8 + NEXTOPCODE +OpEEM1mod2: +lblEEmod2a: Absolute +lblEEmod2b: INC8 + NEXTOPCODE +OpEFM1mod2: +lblEFmod2a: AbsoluteLong +lblEFmod2b: SBC8 + NEXTOPCODE +OpF0mod2: +lblF0mod2: OpF0 + NEXTOPCODE +OpF1M1mod2: +lblF1mod2a: DirectIndirectIndexed0 +lblF1mod2b: SBC8 + NEXTOPCODE +OpF2M1mod2: +lblF2mod2a: DirectIndirect +lblF2mod2b: SBC8 + NEXTOPCODE +OpF3M1mod2: +lblF3mod2a: StackasmRelativeIndirectIndexed0 +lblF3mod2b: SBC8 + NEXTOPCODE +OpF4mod2: +lblF4mod2: OpF4 + NEXTOPCODE +OpF5M1mod2: +lblF5mod2a: DirectIndexedX0 +lblF5mod2b: SBC8 + NEXTOPCODE +OpF6M1mod2: +lblF6mod2a: DirectIndexedX0 +lblF6mod2b: INC8 + NEXTOPCODE +OpF7M1mod2: +lblF7mod2a: DirectIndirectIndexedLong0 +lblF7mod2b: SBC8 + NEXTOPCODE +OpF8mod2: +lblF8mod2: OpF8 + NEXTOPCODE +OpF9M1mod2: +lblF9mod2a: AbsoluteIndexedY0 +lblF9mod2b: SBC8 + NEXTOPCODE +OpFAX0mod2: +lblFAmod2: OpFAX0 + NEXTOPCODE +OpFBmod2: +lblFBmod2: OpFB + NEXTOPCODE +OpFCmod2: +lblFCmod2: OpFCX0 + NEXTOPCODE +OpFDM1mod2: +lblFDmod2a: AbsoluteIndexedX0 +lblFDmod2b: SBC8 + NEXTOPCODE +OpFEM1mod2: +lblFEmod2a: AbsoluteIndexedX0 +lblFEmod2b: INC8 + NEXTOPCODE +OpFFM1mod2: +lblFFmod2a: AbsoluteLongIndexedX0 +lblFFmod2b: SBC8 + NEXTOPCODE + +.pool + + +jumptable3: .long Op00mod3 + .long Op01M0mod3 + .long Op02mod3 + .long Op03M0mod3 + .long Op04M0mod3 + .long Op05M0mod3 + .long Op06M0mod3 + .long Op07M0mod3 + .long Op08mod3 + .long Op09M0mod3 + .long Op0AM0mod3 + .long Op0Bmod3 + .long Op0CM0mod3 + .long Op0DM0mod3 + .long Op0EM0mod3 + .long Op0FM0mod3 + .long Op10mod3 + .long Op11M0mod3 + .long Op12M0mod3 + .long Op13M0mod3 + .long Op14M0mod3 + .long Op15M0mod3 + .long Op16M0mod3 + .long Op17M0mod3 + .long Op18mod3 + .long Op19M0mod3 + .long Op1AM0mod3 + .long Op1Bmod3 + .long Op1CM0mod3 + .long Op1DM0mod3 + .long Op1EM0mod3 + .long Op1FM0mod3 + .long Op20mod3 + .long Op21M0mod3 + .long Op22mod3 + .long Op23M0mod3 + .long Op24M0mod3 + .long Op25M0mod3 + .long Op26M0mod3 + .long Op27M0mod3 + .long Op28mod3 + .long Op29M0mod3 + .long Op2AM0mod3 + .long Op2Bmod3 + .long Op2CM0mod3 + .long Op2DM0mod3 + .long Op2EM0mod3 + .long Op2FM0mod3 + .long Op30mod3 + .long Op31M0mod3 + .long Op32M0mod3 + .long Op33M0mod3 + .long Op34M0mod3 + .long Op35M0mod3 + .long Op36M0mod3 + .long Op37M0mod3 + .long Op38mod3 + .long Op39M0mod3 + .long Op3AM0mod3 + .long Op3Bmod3 + .long Op3CM0mod3 + .long Op3DM0mod3 + .long Op3EM0mod3 + .long Op3FM0mod3 + .long Op40mod3 + .long Op41M0mod3 + .long Op42mod3 + .long Op43M0mod3 + .long Op44X0mod3 + .long Op45M0mod3 + .long Op46M0mod3 + .long Op47M0mod3 + .long Op48M0mod3 + .long Op49M0mod3 + .long Op4AM0mod3 + .long Op4Bmod3 + .long Op4Cmod3 + .long Op4DM0mod3 + .long Op4EM0mod3 + .long Op4FM0mod3 + .long Op50mod3 + .long Op51M0mod3 + .long Op52M0mod3 + .long Op53M0mod3 + .long Op54X0mod3 + .long Op55M0mod3 + .long Op56M0mod3 + .long Op57M0mod3 + .long Op58mod3 + .long Op59M0mod3 + .long Op5AX0mod3 + .long Op5Bmod3 + .long Op5Cmod3 + .long Op5DM0mod3 + .long Op5EM0mod3 + .long Op5FM0mod3 + .long Op60mod3 + .long Op61M0mod3 + .long Op62mod3 + .long Op63M0mod3 + .long Op64M0mod3 + .long Op65M0mod3 + .long Op66M0mod3 + .long Op67M0mod3 + .long Op68M0mod3 + .long Op69M0mod3 + .long Op6AM0mod3 + .long Op6Bmod3 + .long Op6Cmod3 + .long Op6DM0mod3 + .long Op6EM0mod3 + .long Op6FM0mod3 + .long Op70mod3 + .long Op71M0mod3 + .long Op72M0mod3 + .long Op73M0mod3 + .long Op74M0mod3 + .long Op75M0mod3 + .long Op76M0mod3 + .long Op77M0mod3 + .long Op78mod3 + .long Op79M0mod3 + .long Op7AX0mod3 + .long Op7Bmod3 + .long Op7Cmod3 + .long Op7DM0mod3 + .long Op7EM0mod3 + .long Op7FM0mod3 + .long Op80mod3 + .long Op81M0mod3 + .long Op82mod3 + .long Op83M0mod3 + .long Op84X0mod3 + .long Op85M0mod3 + .long Op86X0mod3 + .long Op87M0mod3 + .long Op88X0mod3 + .long Op89M0mod3 + .long Op8AM0mod3 + .long Op8Bmod3 + .long Op8CX0mod3 + .long Op8DM0mod3 + .long Op8EX0mod3 + .long Op8FM0mod3 + .long Op90mod3 + .long Op91M0mod3 + .long Op92M0mod3 + .long Op93M0mod3 + .long Op94X0mod3 + .long Op95M0mod3 + .long Op96X0mod3 + .long Op97M0mod3 + .long Op98M0mod3 + .long Op99M0mod3 + .long Op9Amod3 + .long Op9BX0mod3 + .long Op9CM0mod3 + .long Op9DM0mod3 + .long Op9EM0mod3 + .long Op9FM0mod3 + .long OpA0X0mod3 + .long OpA1M0mod3 + .long OpA2X0mod3 + .long OpA3M0mod3 + .long OpA4X0mod3 + .long OpA5M0mod3 + .long OpA6X0mod3 + .long OpA7M0mod3 + .long OpA8X0mod3 + .long OpA9M0mod3 + .long OpAAX0mod3 + .long OpABmod3 + .long OpACX0mod3 + .long OpADM0mod3 + .long OpAEX0mod3 + .long OpAFM0mod3 + .long OpB0mod3 + .long OpB1M0mod3 + .long OpB2M0mod3 + .long OpB3M0mod3 + .long OpB4X0mod3 + .long OpB5M0mod3 + .long OpB6X0mod3 + .long OpB7M0mod3 + .long OpB8mod3 + .long OpB9M0mod3 + .long OpBAX0mod3 + .long OpBBX0mod3 + .long OpBCX0mod3 + .long OpBDM0mod3 + .long OpBEX0mod3 + .long OpBFM0mod3 + .long OpC0X0mod3 + .long OpC1M0mod3 + .long OpC2mod3 + .long OpC3M0mod3 + .long OpC4X0mod3 + .long OpC5M0mod3 + .long OpC6M0mod3 + .long OpC7M0mod3 + .long OpC8X0mod3 + .long OpC9M0mod3 + .long OpCAX0mod3 + .long OpCBmod3 + .long OpCCX0mod3 + .long OpCDM0mod3 + .long OpCEM0mod3 + .long OpCFM0mod3 + .long OpD0mod3 + .long OpD1M0mod3 + .long OpD2M0mod3 + .long OpD3M0mod3 + .long OpD4mod3 + .long OpD5M0mod3 + .long OpD6M0mod3 + .long OpD7M0mod3 + .long OpD8mod3 + .long OpD9M0mod3 + .long OpDAX0mod3 + .long OpDBmod3 + .long OpDCmod3 + .long OpDDM0mod3 + .long OpDEM0mod3 + .long OpDFM0mod3 + .long OpE0X0mod3 + .long OpE1M0mod3 + .long OpE2mod3 + .long OpE3M0mod3 + .long OpE4X0mod3 + .long OpE5M0mod3 + .long OpE6M0mod3 + .long OpE7M0mod3 + .long OpE8X0mod3 + .long OpE9M0mod3 + .long OpEAmod3 + .long OpEBmod3 + .long OpECX0mod3 + .long OpEDM0mod3 + .long OpEEM0mod3 + .long OpEFM0mod3 + .long OpF0mod3 + .long OpF1M0mod3 + .long OpF2M0mod3 + .long OpF3M0mod3 + .long OpF4mod3 + .long OpF5M0mod3 + .long OpF6M0mod3 + .long OpF7M0mod3 + .long OpF8mod3 + .long OpF9M0mod3 + .long OpFAX0mod3 + .long OpFBmod3 + .long OpFCmod3 + .long OpFDM0mod3 + .long OpFEM0mod3 + .long OpFFM0mod3 +Op00mod3: +lbl00mod3: Op00 + NEXTOPCODE +Op01M0mod3: +lbl01mod3a: DirectIndexedIndirect0 +lbl01mod3b: ORA16 + NEXTOPCODE +Op02mod3: +lbl02mod3: Op02 + NEXTOPCODE +Op03M0mod3: +lbl03mod3a: StackasmRelative +lbl03mod3b: ORA16 + NEXTOPCODE +Op04M0mod3: +lbl04mod3a: Direct +lbl04mod3b: TSB16 + NEXTOPCODE +Op05M0mod3: +lbl05mod3a: Direct +lbl05mod3b: ORA16 + NEXTOPCODE +Op06M0mod3: +lbl06mod3a: Direct +lbl06mod3b: ASL16 + NEXTOPCODE +Op07M0mod3: +lbl07mod3a: DirectIndirectLong +lbl07mod3b: ORA16 + NEXTOPCODE +Op08mod3: +lbl08mod3: Op08 + NEXTOPCODE +Op09M0mod3: +lbl09mod3: Op09M0 + NEXTOPCODE +Op0AM0mod3: +lbl0Amod3a: A_ASL16 + NEXTOPCODE +Op0Bmod3: +lbl0Bmod3: Op0B + NEXTOPCODE +Op0CM0mod3: +lbl0Cmod3a: Absolute +lbl0Cmod3b: TSB16 + NEXTOPCODE +Op0DM0mod3: +lbl0Dmod3a: Absolute +lbl0Dmod3b: ORA16 + NEXTOPCODE +Op0EM0mod3: +lbl0Emod3a: Absolute +lbl0Emod3b: ASL16 + NEXTOPCODE +Op0FM0mod3: +lbl0Fmod3a: AbsoluteLong +lbl0Fmod3b: ORA16 + NEXTOPCODE +Op10mod3: +lbl10mod3: Op10 + NEXTOPCODE +Op11M0mod3: +lbl11mod3a: DirectIndirectIndexed0 +lbl11mod3b: ORA16 + NEXTOPCODE +Op12M0mod3: +lbl12mod3a: DirectIndirect +lbl12mod3b: ORA16 + NEXTOPCODE +Op13M0mod3: +lbl13mod3a: StackasmRelativeIndirectIndexed0 +lbl13mod3b: ORA16 + NEXTOPCODE +Op14M0mod3: +lbl14mod3a: Direct +lbl14mod3b: TRB16 + NEXTOPCODE +Op15M0mod3: +lbl15mod3a: DirectIndexedX0 +lbl15mod3b: ORA16 + NEXTOPCODE +Op16M0mod3: +lbl16mod3a: DirectIndexedX0 +lbl16mod3b: ASL16 + NEXTOPCODE +Op17M0mod3: +lbl17mod3a: DirectIndirectIndexedLong0 +lbl17mod3b: ORA16 + NEXTOPCODE +Op18mod3: +lbl18mod3: Op18 + NEXTOPCODE +Op19M0mod3: +lbl19mod3a: AbsoluteIndexedY0 +lbl19mod3b: ORA16 + NEXTOPCODE +Op1AM0mod3: +lbl1Amod3a: A_INC16 + NEXTOPCODE +Op1Bmod3: +lbl1Bmod3: Op1BM0 + NEXTOPCODE +Op1CM0mod3: +lbl1Cmod3a: Absolute +lbl1Cmod3b: TRB16 + NEXTOPCODE +Op1DM0mod3: +lbl1Dmod3a: AbsoluteIndexedX0 +lbl1Dmod3b: ORA16 + NEXTOPCODE +Op1EM0mod3: +lbl1Emod3a: AbsoluteIndexedX0 +lbl1Emod3b: ASL16 + NEXTOPCODE +Op1FM0mod3: +lbl1Fmod3a: AbsoluteLongIndexedX0 +lbl1Fmod3b: ORA16 + NEXTOPCODE +Op20mod3: +lbl20mod3: Op20 + NEXTOPCODE +Op21M0mod3: +lbl21mod3a: DirectIndexedIndirect0 +lbl21mod3b: AND16 + NEXTOPCODE +Op22mod3: +lbl22mod3: Op22 + NEXTOPCODE +Op23M0mod3: +lbl23mod3a: StackasmRelative +lbl23mod3b: AND16 + NEXTOPCODE +Op24M0mod3: +lbl24mod3a: Direct +lbl24mod3b: BIT16 + NEXTOPCODE +Op25M0mod3: +lbl25mod3a: Direct +lbl25mod3b: AND16 + NEXTOPCODE +Op26M0mod3: +lbl26mod3a: Direct +lbl26mod3b: ROL16 + NEXTOPCODE +Op27M0mod3: +lbl27mod3a: DirectIndirectLong + +lbl27mod3b: AND16 + NEXTOPCODE +Op28mod3: +lbl28mod3: Op28X0M0 + NEXTOPCODE +.pool +Op29M0mod3: +lbl29mod3: Op29M0 + NEXTOPCODE +Op2AM0mod3: +lbl2Amod3a: A_ROL16 + NEXTOPCODE +Op2Bmod3: +lbl2Bmod3: Op2B + NEXTOPCODE +Op2CM0mod3: +lbl2Cmod3a: Absolute +lbl2Cmod3b: BIT16 + NEXTOPCODE +Op2DM0mod3: +lbl2Dmod3a: Absolute +lbl2Dmod3b: AND16 + NEXTOPCODE +Op2EM0mod3: +lbl2Emod3a: Absolute +lbl2Emod3b: ROL16 + NEXTOPCODE +Op2FM0mod3: +lbl2Fmod3a: AbsoluteLong +lbl2Fmod3b: AND16 + NEXTOPCODE +Op30mod3: +lbl30mod3: Op30 + NEXTOPCODE +Op31M0mod3: +lbl31mod3a: DirectIndirectIndexed0 +lbl31mod3b: AND16 + NEXTOPCODE +Op32M0mod3: +lbl32mod3a: DirectIndirect +lbl32mod3b: AND16 + NEXTOPCODE +Op33M0mod3: +lbl33mod3a: StackasmRelativeIndirectIndexed0 +lbl33mod3b: AND16 + NEXTOPCODE +Op34M0mod3: +lbl34mod3a: DirectIndexedX0 +lbl34mod3b: BIT16 + NEXTOPCODE +Op35M0mod3: +lbl35mod3a: DirectIndexedX0 +lbl35mod3b: AND16 + NEXTOPCODE +Op36M0mod3: +lbl36mod3a: DirectIndexedX0 +lbl36mod3b: ROL16 + NEXTOPCODE +Op37M0mod3: +lbl37mod3a: DirectIndirectIndexedLong0 +lbl37mod3b: AND16 + NEXTOPCODE +Op38mod3: +lbl38mod3: Op38 + NEXTOPCODE +Op39M0mod3: +lbl39mod3a: AbsoluteIndexedY0 +lbl39mod3b: AND16 + NEXTOPCODE +Op3AM0mod3: +lbl3Amod3a: A_DEC16 + NEXTOPCODE +Op3Bmod3: +lbl3Bmod3: Op3BM0 + NEXTOPCODE +Op3CM0mod3: +lbl3Cmod3a: AbsoluteIndexedX0 +lbl3Cmod3b: BIT16 + NEXTOPCODE +Op3DM0mod3: +lbl3Dmod3a: AbsoluteIndexedX0 +lbl3Dmod3b: AND16 + NEXTOPCODE +Op3EM0mod3: +lbl3Emod3a: AbsoluteIndexedX0 +lbl3Emod3b: ROL16 + NEXTOPCODE +Op3FM0mod3: +lbl3Fmod3a: AbsoluteLongIndexedX0 +lbl3Fmod3b: AND16 + NEXTOPCODE +Op40mod3: +lbl40mod3: Op40X0M0 + NEXTOPCODE +.pool +Op41M0mod3: +lbl41mod3a: DirectIndexedIndirect0 +lbl41mod3b: EOR16 + NEXTOPCODE +Op42mod3: +lbl42mod3: Op42 + NEXTOPCODE +Op43M0mod3: +lbl43mod3a: StackasmRelative +lbl43mod3b: EOR16 + NEXTOPCODE +Op44X0mod3: +lbl44mod3: Op44X0M0 + NEXTOPCODE +Op45M0mod3: +lbl45mod3a: Direct +lbl45mod3b: EOR16 + NEXTOPCODE +Op46M0mod3: +lbl46mod3a: Direct +lbl46mod3b: LSR16 + NEXTOPCODE +Op47M0mod3: +lbl47mod3a: DirectIndirectLong +lbl47mod3b: EOR16 + NEXTOPCODE +Op48M0mod3: +lbl48mod3: Op48M0 + NEXTOPCODE +Op49M0mod3: +lbl49mod3: Op49M0 + NEXTOPCODE +Op4AM0mod3: +lbl4Amod3a: A_LSR16 + NEXTOPCODE +Op4Bmod3: +lbl4Bmod3: Op4B + NEXTOPCODE +Op4Cmod3: +lbl4Cmod3: Op4C + NEXTOPCODE +Op4DM0mod3: +lbl4Dmod3a: Absolute +lbl4Dmod3b: EOR16 + NEXTOPCODE +Op4EM0mod3: +lbl4Emod3a: Absolute +lbl4Emod3b: LSR16 + NEXTOPCODE +Op4FM0mod3: +lbl4Fmod3a: AbsoluteLong +lbl4Fmod3b: EOR16 + NEXTOPCODE +Op50mod3: +lbl50mod3: Op50 + NEXTOPCODE +Op51M0mod3: +lbl51mod3a: DirectIndirectIndexed0 +lbl51mod3b: EOR16 + NEXTOPCODE +Op52M0mod3: +lbl52mod3a: DirectIndirect +lbl52mod3b: EOR16 + NEXTOPCODE +Op53M0mod3: +lbl53mod3a: StackasmRelativeIndirectIndexed0 +lbl53mod3b: EOR16 + NEXTOPCODE +Op54X0mod3: +lbl54mod3: Op54X0M0 + NEXTOPCODE +Op55M0mod3: +lbl55mod3a: DirectIndexedX0 +lbl55mod3b: EOR16 + NEXTOPCODE +Op56M0mod3: +lbl56mod3a: DirectIndexedX0 +lbl56mod3b: LSR16 + NEXTOPCODE +Op57M0mod3: +lbl57mod3a: DirectIndirectIndexedLong0 +lbl57mod3b: EOR16 + NEXTOPCODE +Op58mod3: +lbl58mod3: Op58 + NEXTOPCODE +Op59M0mod3: +lbl59mod3a: AbsoluteIndexedY0 +lbl59mod3b: EOR16 + NEXTOPCODE +Op5AX0mod3: +lbl5Amod3: Op5AX0 + NEXTOPCODE +Op5Bmod3: +lbl5Bmod3: Op5BM0 + NEXTOPCODE +Op5Cmod3: +lbl5Cmod3: Op5C + NEXTOPCODE +Op5DM0mod3: +lbl5Dmod3a: AbsoluteIndexedX0 +lbl5Dmod3b: EOR16 + NEXTOPCODE +Op5EM0mod3: +lbl5Emod3a: AbsoluteIndexedX0 +lbl5Emod3b: LSR16 + NEXTOPCODE +Op5FM0mod3: +lbl5Fmod3a: AbsoluteLongIndexedX0 +lbl5Fmod3b: EOR16 + NEXTOPCODE +Op60mod3: +lbl60mod3: Op60 + NEXTOPCODE +Op61M0mod3: +lbl61mod3a: DirectIndexedIndirect0 +lbl61mod3b: ADC16 + NEXTOPCODE +Op62mod3: +lbl62mod3: Op62 + NEXTOPCODE +Op63M0mod3: +lbl63mod3a: StackasmRelative +lbl63mod3b: ADC16 + NEXTOPCODE +.pool +Op64M0mod3: +lbl64mod3a: Direct +lbl64mod3b: STZ16 + NEXTOPCODE +Op65M0mod3: +lbl65mod3a: Direct +lbl65mod3b: ADC16 + NEXTOPCODE +.pool +Op66M0mod3: +lbl66mod3a: Direct +lbl66mod3b: ROR16 + NEXTOPCODE +Op67M0mod3: +lbl67mod3a: DirectIndirectLong +lbl67mod3b: ADC16 + NEXTOPCODE +.pool +Op68M0mod3: +lbl68mod3: Op68M0 + NEXTOPCODE +Op69M0mod3: +lbl69mod3a: Immediate16 +lbl69mod3b: ADC16 + NEXTOPCODE +.pool +Op6AM0mod3: +lbl6Amod3a: A_ROR16 + NEXTOPCODE +Op6Bmod3: +lbl6Bmod3: Op6B + NEXTOPCODE +Op6Cmod3: +lbl6Cmod3: Op6C + NEXTOPCODE +Op6DM0mod3: +lbl6Dmod3a: Absolute +lbl6Dmod3b: ADC16 + NEXTOPCODE +Op6EM0mod3: +lbl6Emod3a: Absolute +lbl6Emod3b: ROR16 + NEXTOPCODE +Op6FM0mod3: +lbl6Fmod3a: AbsoluteLong +lbl6Fmod3b: ADC16 + NEXTOPCODE +Op70mod3: +lbl70mod3: Op70 + NEXTOPCODE +Op71M0mod3: +lbl71mod3a: DirectIndirectIndexed0 +lbl71mod3b: ADC16 + NEXTOPCODE +Op72M0mod3: +lbl72mod3a: DirectIndirect +lbl72mod3b: ADC16 + NEXTOPCODE +Op73M0mod3: +lbl73mod3a: StackasmRelativeIndirectIndexed0 +lbl73mod3b: ADC16 + NEXTOPCODE +.pool +Op74M0mod3: +lbl74mod3a: DirectIndexedX0 +lbl74mod3b: STZ16 + NEXTOPCODE +Op75M0mod3: +lbl75mod3a: DirectIndexedX0 +lbl75mod3b: ADC16 + NEXTOPCODE +.pool +Op76M0mod3: +lbl76mod3a: DirectIndexedX0 +lbl76mod3b: ROR16 + NEXTOPCODE +Op77M0mod3: +lbl77mod3a: DirectIndirectIndexedLong0 +lbl77mod3b: ADC16 + NEXTOPCODE +Op78mod3: +lbl78mod3: Op78 + NEXTOPCODE +Op79M0mod3: +lbl79mod3a: AbsoluteIndexedY0 +lbl79mod3b: ADC16 + NEXTOPCODE +Op7AX0mod3: +lbl7Amod3: Op7AX0 + NEXTOPCODE +Op7Bmod3: +lbl7Bmod3: Op7BM0 + NEXTOPCODE +Op7Cmod3: +lbl7Cmod3: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE +Op7DM0mod3: +lbl7Dmod3a: AbsoluteIndexedX0 +lbl7Dmod3b: ADC16 + NEXTOPCODE +Op7EM0mod3: +lbl7Emod3a: AbsoluteIndexedX0 +lbl7Emod3b: ROR16 + NEXTOPCODE +Op7FM0mod3: +lbl7Fmod3a: AbsoluteLongIndexedX0 +lbl7Fmod3b: ADC16 + NEXTOPCODE +.pool +Op80mod3: +lbl80mod3: Op80 + NEXTOPCODE +Op81M0mod3: +lbl81mod3a: DirectIndexedIndirect0 +lbl81mod3b: Op81M0 + NEXTOPCODE +Op82mod3: +lbl82mod3: Op82 + NEXTOPCODE +Op83M0mod3: +lbl83mod3a: StackasmRelative +lbl83mod3b: STA16 + NEXTOPCODE +Op84X0mod3: +lbl84mod3a: Direct +lbl84mod3b: STY16 + NEXTOPCODE +Op85M0mod3: +lbl85mod3a: Direct +lbl85mod3b: STA16 + NEXTOPCODE +Op86X0mod3: +lbl86mod3a: Direct +lbl86mod3b: STX16 + NEXTOPCODE +Op87M0mod3: +lbl87mod3a: DirectIndirectLong +lbl87mod3b: STA16 + NEXTOPCODE +Op88X0mod3: +lbl88mod3: Op88X0 + NEXTOPCODE +Op89M0mod3: +lbl89mod3: Op89M0 + NEXTOPCODE +Op8AM0mod3: +lbl8Amod3: Op8AM0X0 + NEXTOPCODE +Op8Bmod3: +lbl8Bmod3: Op8B + NEXTOPCODE +Op8CX0mod3: +lbl8Cmod3a: Absolute +lbl8Cmod3b: STY16 + NEXTOPCODE +Op8DM0mod3: +lbl8Dmod3a: Absolute +lbl8Dmod3b: STA16 + NEXTOPCODE +Op8EX0mod3: +lbl8Emod3a: Absolute +lbl8Emod3b: STX16 + NEXTOPCODE +Op8FM0mod3: +lbl8Fmod3a: AbsoluteLong +lbl8Fmod3b: STA16 + NEXTOPCODE +Op90mod3: +lbl90mod3: Op90 + NEXTOPCODE +Op91M0mod3: +lbl91mod3a: DirectIndirectIndexed0 +lbl91mod3b: STA16 + NEXTOPCODE +Op92M0mod3: +lbl92mod3a: DirectIndirect +lbl92mod3b: STA16 + NEXTOPCODE +Op93M0mod3: +lbl93mod3a: StackasmRelativeIndirectIndexed0 +lbl93mod3b: STA16 + NEXTOPCODE +Op94X0mod3: +lbl94mod3a: DirectIndexedX0 +lbl94mod3b: STY16 + NEXTOPCODE +Op95M0mod3: +lbl95mod3a: DirectIndexedX0 +lbl95mod3b: STA16 + NEXTOPCODE +Op96X0mod3: +lbl96mod3a: DirectIndexedY0 +lbl96mod3b: STX16 + NEXTOPCODE +Op97M0mod3: +lbl97mod3a: DirectIndirectIndexedLong0 +lbl97mod3b: STA16 + NEXTOPCODE +Op98M0mod3: +lbl98mod3: Op98M0X0 + NEXTOPCODE +Op99M0mod3: +lbl99mod3a: AbsoluteIndexedY0 +lbl99mod3b: STA16 + NEXTOPCODE +Op9Amod3: +lbl9Amod3: Op9AX0 + NEXTOPCODE +Op9BX0mod3: +lbl9Bmod3: Op9BX0 + NEXTOPCODE +Op9CM0mod3: +lbl9Cmod3a: Absolute +lbl9Cmod3b: STZ16 + NEXTOPCODE +Op9DM0mod3: +lbl9Dmod3a: AbsoluteIndexedX0 +lbl9Dmod3b: STA16 + NEXTOPCODE +Op9EM0mod3: +lbl9Emod3: AbsoluteIndexedX0 + STZ16 + NEXTOPCODE +Op9FM0mod3: +lbl9Fmod3a: AbsoluteLongIndexedX0 +lbl9Fmod3b: STA16 + NEXTOPCODE +OpA0X0mod3: +lblA0mod3: OpA0X0 + NEXTOPCODE +OpA1M0mod3: +lblA1mod3a: DirectIndexedIndirect0 +lblA1mod3b: LDA16 + NEXTOPCODE +OpA2X0mod3: +lblA2mod3: OpA2X0 + NEXTOPCODE +OpA3M0mod3: +lblA3mod3a: StackasmRelative +lblA3mod3b: LDA16 + NEXTOPCODE +OpA4X0mod3: +lblA4mod3a: Direct +lblA4mod3b: LDY16 + NEXTOPCODE +OpA5M0mod3: +lblA5mod3a: Direct +lblA5mod3b: LDA16 + NEXTOPCODE +OpA6X0mod3: +lblA6mod3a: Direct +lblA6mod3b: LDX16 + NEXTOPCODE +OpA7M0mod3: +lblA7mod3a: DirectIndirectLong +lblA7mod3b: LDA16 + NEXTOPCODE +OpA8X0mod3: +lblA8mod3: OpA8X0M0 + NEXTOPCODE +OpA9M0mod3: +lblA9mod3: OpA9M0 + NEXTOPCODE +OpAAX0mod3: +lblAAmod3: OpAAX0M0 + NEXTOPCODE +OpABmod3: +lblABmod3: OpAB + NEXTOPCODE +OpACX0mod3: +lblACmod3a: Absolute +lblACmod3b: LDY16 + NEXTOPCODE +OpADM0mod3: +lblADmod3a: Absolute +lblADmod3b: LDA16 + NEXTOPCODE +OpAEX0mod3: +lblAEmod3a: Absolute +lblAEmod3b: LDX16 + NEXTOPCODE +OpAFM0mod3: +lblAFmod3a: AbsoluteLong +lblAFmod3b: LDA16 + NEXTOPCODE +OpB0mod3: +lblB0mod3: OpB0 + NEXTOPCODE +OpB1M0mod3: +lblB1mod3a: DirectIndirectIndexed0 +lblB1mod3b: LDA16 + NEXTOPCODE +OpB2M0mod3: +lblB2mod3a: DirectIndirect +lblB2mod3b: LDA16 + NEXTOPCODE +OpB3M0mod3: +lblB3mod3a: StackasmRelativeIndirectIndexed0 +lblB3mod3b: LDA16 + NEXTOPCODE +OpB4X0mod3: +lblB4mod3a: DirectIndexedX0 +lblB4mod3b: LDY16 + NEXTOPCODE +OpB5M0mod3: +lblB5mod3a: DirectIndexedX0 +lblB5mod3b: LDA16 + NEXTOPCODE +OpB6X0mod3: +lblB6mod3a: DirectIndexedY0 +lblB6mod3b: LDX16 + NEXTOPCODE +OpB7M0mod3: +lblB7mod3a: DirectIndirectIndexedLong0 +lblB7mod3b: LDA16 + NEXTOPCODE +OpB8mod3: +lblB8mod3: OpB8 + NEXTOPCODE +OpB9M0mod3: +lblB9mod3a: AbsoluteIndexedY0 +lblB9mod3b: LDA16 + NEXTOPCODE +OpBAX0mod3: +lblBAmod3: OpBAX0 + NEXTOPCODE +OpBBX0mod3: +lblBBmod3: OpBBX0 + NEXTOPCODE +OpBCX0mod3: +lblBCmod3a: AbsoluteIndexedX0 +lblBCmod3b: LDY16 + NEXTOPCODE +OpBDM0mod3: +lblBDmod3a: AbsoluteIndexedX0 +lblBDmod3b: LDA16 + NEXTOPCODE +OpBEX0mod3: +lblBEmod3a: AbsoluteIndexedY0 +lblBEmod3b: LDX16 + NEXTOPCODE +OpBFM0mod3: +lblBFmod3a: AbsoluteLongIndexedX0 +lblBFmod3b: LDA16 + NEXTOPCODE +OpC0X0mod3: +lblC0mod3: OpC0X0 + NEXTOPCODE +OpC1M0mod3: +lblC1mod3a: DirectIndexedIndirect0 +lblC1mod3b: CMP16 + NEXTOPCODE +OpC2mod3: +lblC2mod3: OpC2 + NEXTOPCODE +.pool +OpC3M0mod3: +lblC3mod3a: StackasmRelative +lblC3mod3b: CMP16 + NEXTOPCODE +OpC4X0mod3: +lblC4mod3a: Direct +lblC4mod3b: CMY16 + NEXTOPCODE +OpC5M0mod3: +lblC5mod3a: Direct +lblC5mod3b: CMP16 + NEXTOPCODE +OpC6M0mod3: +lblC6mod3a: Direct +lblC6mod3b: DEC16 + NEXTOPCODE +OpC7M0mod3: +lblC7mod3a: DirectIndirectLong +lblC7mod3b: CMP16 + NEXTOPCODE +OpC8X0mod3: +lblC8mod3: OpC8X0 + NEXTOPCODE +OpC9M0mod3: +lblC9mod3: OpC9M0 + NEXTOPCODE +OpCAX0mod3: +lblCAmod3: OpCAX0 + NEXTOPCODE +OpCBmod3: +lblCBmod3: OpCB + NEXTOPCODE +OpCCX0mod3: +lblCCmod3a: Absolute +lblCCmod3b: CMY16 + NEXTOPCODE +OpCDM0mod3: +lblCDmod3a: Absolute +lblCDmod3b: CMP16 + NEXTOPCODE +OpCEM0mod3: +lblCEmod3a: Absolute +lblCEmod3b: DEC16 + NEXTOPCODE +OpCFM0mod3: +lblCFmod3a: AbsoluteLong +lblCFmod3b: CMP16 + NEXTOPCODE +OpD0mod3: + +lblD0mod3: OpD0 + NEXTOPCODE +OpD1M0mod3: +lblD1mod3a: DirectIndirectIndexed0 +lblD1mod3b: CMP16 + NEXTOPCODE +OpD2M0mod3: +lblD2mod3a: DirectIndirect +lblD2mod3b: CMP16 + NEXTOPCODE +OpD3M0mod3: +lblD3mod3a: StackasmRelativeIndirectIndexed0 +lblD3mod3b: CMP16 + NEXTOPCODE +OpD4mod3: +lblD4mod3: OpD4 + NEXTOPCODE +OpD5M0mod3: +lblD5mod3a: DirectIndexedX0 +lblD5mod3b: CMP16 + NEXTOPCODE +OpD6M0mod3: +lblD6mod3a: DirectIndexedX0 +lblD6mod3b: DEC16 + NEXTOPCODE +OpD7M0mod3: +lblD7mod3a: DirectIndirectIndexedLong0 +lblD7mod3b: CMP16 + NEXTOPCODE +OpD8mod3: +lblD8mod3: OpD8 + NEXTOPCODE +OpD9M0mod3: +lblD9mod3a: AbsoluteIndexedY0 +lblD9mod3b: CMP16 + NEXTOPCODE +OpDAX0mod3: +lblDAmod3: OpDAX0 + NEXTOPCODE +OpDBmod3: +lblDBmod3: OpDB + NEXTOPCODE +OpDCmod3: +lblDCmod3: OpDC + NEXTOPCODE +OpDDM0mod3: +lblDDmod3a: AbsoluteIndexedX0 +lblDDmod3b: CMP16 + NEXTOPCODE +OpDEM0mod3: +lblDEmod3a: AbsoluteIndexedX0 +lblDEmod3b: DEC16 + NEXTOPCODE +OpDFM0mod3: +lblDFmod3a: AbsoluteLongIndexedX0 +lblDFmod3b: CMP16 + NEXTOPCODE +OpE0X0mod3: +lblE0mod3: OpE0X0 + NEXTOPCODE +OpE1M0mod3: +lblE1mod3a: DirectIndexedIndirect0 +lblE1mod3b: SBC16 + NEXTOPCODE +OpE2mod3: +lblE2mod3: OpE2 + NEXTOPCODE +.pool +OpE3M0mod3: +lblE3mod3a: StackasmRelative +lblE3mod3b: SBC16 + NEXTOPCODE +OpE4X0mod3: +lblE4mod3a: Direct +lblE4mod3b: CMX16 + NEXTOPCODE +OpE5M0mod3: +lblE5mod3a: Direct +lblE5mod3b: SBC16 + NEXTOPCODE +OpE6M0mod3: +lblE6mod3a: Direct +lblE6mod3b: INC16 + NEXTOPCODE +OpE7M0mod3: +lblE7mod3a: DirectIndirectLong +lblE7mod3b: SBC16 + NEXTOPCODE +OpE8X0mod3: +lblE8mod3: OpE8X0 + NEXTOPCODE +OpE9M0mod3: +lblE9mod3a: Immediate16 +lblE9mod3b: SBC16 + NEXTOPCODE +OpEAmod3: +lblEAmod3: OpEA + NEXTOPCODE +OpEBmod3: +lblEBmod3: OpEBM0 + NEXTOPCODE +OpECX0mod3: +lblECmod3a: Absolute +lblECmod3b: CMX16 + NEXTOPCODE +OpEDM0mod3: +lblEDmod3a: Absolute +lblEDmod3b: SBC16 + NEXTOPCODE +OpEEM0mod3: +lblEEmod3a: Absolute +lblEEmod3b: INC16 + NEXTOPCODE +OpEFM0mod3: +lblEFmod3a: AbsoluteLong +lblEFmod3b: SBC16 + NEXTOPCODE +OpF0mod3: +lblF0mod3: OpF0 + NEXTOPCODE +OpF1M0mod3: +lblF1mod3a: DirectIndirectIndexed0 +lblF1mod3b: SBC16 + NEXTOPCODE +OpF2M0mod3: +lblF2mod3a: DirectIndirect +lblF2mod3b: SBC16 + NEXTOPCODE +OpF3M0mod3: +lblF3mod3a: StackasmRelativeIndirectIndexed0 +lblF3mod3b: SBC16 + NEXTOPCODE +OpF4mod3: +lblF4mod3: OpF4 + NEXTOPCODE +OpF5M0mod3: +lblF5mod3a: DirectIndexedX0 +lblF5mod3b: SBC16 + NEXTOPCODE +OpF6M0mod3: +lblF6mod3a: DirectIndexedX0 +lblF6mod3b: INC16 + NEXTOPCODE +OpF7M0mod3: +lblF7mod3a: DirectIndirectIndexedLong0 +lblF7mod3b: SBC16 + NEXTOPCODE +OpF8mod3: +lblF8mod3: OpF8 + NEXTOPCODE +OpF9M0mod3: +lblF9mod3a: AbsoluteIndexedY0 +lblF9mod3b: SBC16 + NEXTOPCODE +OpFAX0mod3: +lblFAmod3: OpFAX0 + NEXTOPCODE +OpFBmod3: +lblFBmod3: OpFB + NEXTOPCODE +OpFCmod3: +lblFCmod3: OpFCX0 + NEXTOPCODE +OpFDM0mod3: +lblFDmod3a: AbsoluteIndexedX0 +lblFDmod3b: SBC16 + NEXTOPCODE +OpFEM0mod3: +lblFEmod3a: AbsoluteIndexedX0 +lblFEmod3b: INC16 + NEXTOPCODE +OpFFM0mod3: +lblFFmod3a: AbsoluteLongIndexedX0 +lblFFmod3b: SBC16 + NEXTOPCODE +.pool + +jumptable4: .long Op00mod4 + .long Op01M0mod4 + .long Op02mod4 + .long Op03M0mod4 + .long Op04M0mod4 + .long Op05M0mod4 + .long Op06M0mod4 + .long Op07M0mod4 + .long Op08mod4 + .long Op09M0mod4 + .long Op0AM0mod4 + .long Op0Bmod4 + .long Op0CM0mod4 + .long Op0DM0mod4 + .long Op0EM0mod4 + .long Op0FM0mod4 + .long Op10mod4 + .long Op11M0mod4 + .long Op12M0mod4 + .long Op13M0mod4 + .long Op14M0mod4 + .long Op15M0mod4 + .long Op16M0mod4 + .long Op17M0mod4 + .long Op18mod4 + .long Op19M0mod4 + .long Op1AM0mod4 + .long Op1Bmod4 + .long Op1CM0mod4 + .long Op1DM0mod4 + .long Op1EM0mod4 + .long Op1FM0mod4 + .long Op20mod4 + .long Op21M0mod4 + .long Op22mod4 + .long Op23M0mod4 + .long Op24M0mod4 + .long Op25M0mod4 + .long Op26M0mod4 + .long Op27M0mod4 + .long Op28mod4 + .long Op29M0mod4 + .long Op2AM0mod4 + .long Op2Bmod4 + .long Op2CM0mod4 + .long Op2DM0mod4 + .long Op2EM0mod4 + .long Op2FM0mod4 + .long Op30mod4 + .long Op31M0mod4 + .long Op32M0mod4 + .long Op33M0mod4 + .long Op34M0mod4 + .long Op35M0mod4 + .long Op36M0mod4 + .long Op37M0mod4 + .long Op38mod4 + .long Op39M0mod4 + .long Op3AM0mod4 + .long Op3Bmod4 + .long Op3CM0mod4 + .long Op3DM0mod4 + .long Op3EM0mod4 + .long Op3FM0mod4 + .long Op40mod4 + .long Op41M0mod4 + .long Op42mod4 + .long Op43M0mod4 + .long Op44X1mod4 + .long Op45M0mod4 + .long Op46M0mod4 + .long Op47M0mod4 + .long Op48M0mod4 + .long Op49M0mod4 + .long Op4AM0mod4 + .long Op4Bmod4 + .long Op4Cmod4 + .long Op4DM0mod4 + .long Op4EM0mod4 + .long Op4FM0mod4 + .long Op50mod4 + .long Op51M0mod4 + .long Op52M0mod4 + .long Op53M0mod4 + .long Op54X1mod4 + .long Op55M0mod4 + .long Op56M0mod4 + .long Op57M0mod4 + .long Op58mod4 + .long Op59M0mod4 + .long Op5AX1mod4 + .long Op5Bmod4 + .long Op5Cmod4 + .long Op5DM0mod4 + .long Op5EM0mod4 + .long Op5FM0mod4 + .long Op60mod4 + .long Op61M0mod4 + .long Op62mod4 + .long Op63M0mod4 + .long Op64M0mod4 + .long Op65M0mod4 + .long Op66M0mod4 + .long Op67M0mod4 + .long Op68M0mod4 + .long Op69M0mod4 + .long Op6AM0mod4 + .long Op6Bmod4 + .long Op6Cmod4 + .long Op6DM0mod4 + .long Op6EM0mod4 + .long Op6FM0mod4 + .long Op70mod4 + .long Op71M0mod4 + .long Op72M0mod4 + .long Op73M0mod4 + .long Op74M0mod4 + .long Op75M0mod4 + .long Op76M0mod4 + .long Op77M0mod4 + .long Op78mod4 + .long Op79M0mod4 + .long Op7AX1mod4 + .long Op7Bmod4 + .long Op7Cmod4 + .long Op7DM0mod4 + .long Op7EM0mod4 + .long Op7FM0mod4 + .long Op80mod4 + .long Op81M0mod4 + .long Op82mod4 + .long Op83M0mod4 + .long Op84X1mod4 + .long Op85M0mod4 + .long Op86X1mod4 + .long Op87M0mod4 + .long Op88X1mod4 + .long Op89M0mod4 + .long Op8AM0mod4 + .long Op8Bmod4 + .long Op8CX1mod4 + .long Op8DM0mod4 + .long Op8EX1mod4 + .long Op8FM0mod4 + .long Op90mod4 + .long Op91M0mod4 + .long Op92M0mod4 + .long Op93M0mod4 + .long Op94X1mod4 + .long Op95M0mod4 + .long Op96X1mod4 + .long Op97M0mod4 + .long Op98M0mod4 + .long Op99M0mod4 + .long Op9Amod4 + .long Op9BX1mod4 + .long Op9CM0mod4 + .long Op9DM0mod4 + + .long Op9EM0mod4 + .long Op9FM0mod4 + .long OpA0X1mod4 + .long OpA1M0mod4 + .long OpA2X1mod4 + .long OpA3M0mod4 + .long OpA4X1mod4 + .long OpA5M0mod4 + .long OpA6X1mod4 + .long OpA7M0mod4 + .long OpA8X1mod4 + .long OpA9M0mod4 + .long OpAAX1mod4 + .long OpABmod4 + .long OpACX1mod4 + .long OpADM0mod4 + .long OpAEX1mod4 + .long OpAFM0mod4 + .long OpB0mod4 + .long OpB1M0mod4 + .long OpB2M0mod4 + .long OpB3M0mod4 + .long OpB4X1mod4 + .long OpB5M0mod4 + .long OpB6X1mod4 + .long OpB7M0mod4 + .long OpB8mod4 + .long OpB9M0mod4 + .long OpBAX1mod4 + .long OpBBX1mod4 + .long OpBCX1mod4 + .long OpBDM0mod4 + .long OpBEX1mod4 + .long OpBFM0mod4 + .long OpC0X1mod4 + .long OpC1M0mod4 + .long OpC2mod4 + .long OpC3M0mod4 + .long OpC4X1mod4 + .long OpC5M0mod4 + .long OpC6M0mod4 + .long OpC7M0mod4 + .long OpC8X1mod4 + .long OpC9M0mod4 + .long OpCAX1mod4 + .long OpCBmod4 + .long OpCCX1mod4 + .long OpCDM0mod4 + .long OpCEM0mod4 + .long OpCFM0mod4 + .long OpD0mod4 + .long OpD1M0mod4 + .long OpD2M0mod4 + .long OpD3M0mod4 + .long OpD4mod4 + .long OpD5M0mod4 + .long OpD6M0mod4 + .long OpD7M0mod4 + .long OpD8mod4 + .long OpD9M0mod4 + .long OpDAX1mod4 + .long OpDBmod4 + .long OpDCmod4 + .long OpDDM0mod4 + .long OpDEM0mod4 + .long OpDFM0mod4 + .long OpE0X1mod4 + .long OpE1M0mod4 + .long OpE2mod4 + .long OpE3M0mod4 + .long OpE4X1mod4 + .long OpE5M0mod4 + .long OpE6M0mod4 + .long OpE7M0mod4 + .long OpE8X1mod4 + .long OpE9M0mod4 + .long OpEAmod4 + .long OpEBmod4 + .long OpECX1mod4 + .long OpEDM0mod4 + .long OpEEM0mod4 + .long OpEFM0mod4 + .long OpF0mod4 + .long OpF1M0mod4 + .long OpF2M0mod4 + .long OpF3M0mod4 + .long OpF4mod4 + .long OpF5M0mod4 + .long OpF6M0mod4 + .long OpF7M0mod4 + .long OpF8mod4 + .long OpF9M0mod4 + .long OpFAX1mod4 + .long OpFBmod4 + .long OpFCmod4 + .long OpFDM0mod4 + .long OpFEM0mod4 + .long OpFFM0mod4 +Op00mod4: +lbl00mod4: Op00 + NEXTOPCODE +Op01M0mod4: +lbl01mod4a: DirectIndexedIndirect1 +lbl01mod4b: ORA16 + NEXTOPCODE +Op02mod4: +lbl02mod4: Op02 + NEXTOPCODE +Op03M0mod4: +lbl03mod4a: StackasmRelative +lbl03mod4b: ORA16 + NEXTOPCODE +Op04M0mod4: +lbl04mod4a: Direct +lbl04mod4b: TSB16 + NEXTOPCODE +Op05M0mod4: +lbl05mod4a: Direct +lbl05mod4b: ORA16 + NEXTOPCODE +Op06M0mod4: +lbl06mod4a: Direct +lbl06mod4b: ASL16 + NEXTOPCODE +Op07M0mod4: +lbl07mod4a: DirectIndirectLong +lbl07mod4b: ORA16 + NEXTOPCODE +Op08mod4: +lbl08mod4: Op08 + NEXTOPCODE +Op09M0mod4: +lbl09mod4: Op09M0 + NEXTOPCODE +Op0AM0mod4: +lbl0Amod4a: A_ASL16 + NEXTOPCODE +Op0Bmod4: +lbl0Bmod4: Op0B + NEXTOPCODE +Op0CM0mod4: +lbl0Cmod4a: Absolute +lbl0Cmod4b: TSB16 + NEXTOPCODE +Op0DM0mod4: +lbl0Dmod4a: Absolute +lbl0Dmod4b: ORA16 + NEXTOPCODE +Op0EM0mod4: +lbl0Emod4a: Absolute +lbl0Emod4b: ASL16 + NEXTOPCODE +Op0FM0mod4: +lbl0Fmod4a: AbsoluteLong +lbl0Fmod4b: ORA16 + NEXTOPCODE +Op10mod4: +lbl10mod4: Op10 + NEXTOPCODE +Op11M0mod4: +lbl11mod4a: DirectIndirectIndexed1 +lbl11mod4b: ORA16 + NEXTOPCODE +Op12M0mod4: +lbl12mod4a: DirectIndirect +lbl12mod4b: ORA16 + NEXTOPCODE +Op13M0mod4: +lbl13mod4a: StackasmRelativeIndirectIndexed1 +lbl13mod4b: ORA16 + NEXTOPCODE +Op14M0mod4: +lbl14mod4a: Direct +lbl14mod4b: TRB16 + NEXTOPCODE +Op15M0mod4: +lbl15mod4a: DirectIndexedX1 +lbl15mod4b: ORA16 + NEXTOPCODE +Op16M0mod4: +lbl16mod4a: DirectIndexedX1 +lbl16mod4b: ASL16 + NEXTOPCODE +Op17M0mod4: +lbl17mod4a: DirectIndirectIndexedLong1 +lbl17mod4b: ORA16 + NEXTOPCODE +Op18mod4: +lbl18mod4: Op18 + NEXTOPCODE +Op19M0mod4: +lbl19mod4a: AbsoluteIndexedY1 +lbl19mod4b: ORA16 + NEXTOPCODE +Op1AM0mod4: +lbl1Amod4a: A_INC16 + NEXTOPCODE +Op1Bmod4: +lbl1Bmod4: Op1BM0 + NEXTOPCODE +Op1CM0mod4: +lbl1Cmod4a: Absolute +lbl1Cmod4b: TRB16 + NEXTOPCODE +Op1DM0mod4: +lbl1Dmod4a: AbsoluteIndexedX1 +lbl1Dmod4b: ORA16 + NEXTOPCODE +Op1EM0mod4: +lbl1Emod4a: AbsoluteIndexedX1 +lbl1Emod4b: ASL16 + NEXTOPCODE +Op1FM0mod4: +lbl1Fmod4a: AbsoluteLongIndexedX1 +lbl1Fmod4b: ORA16 + NEXTOPCODE +Op20mod4: +lbl20mod4: Op20 + NEXTOPCODE +Op21M0mod4: +lbl21mod4a: DirectIndexedIndirect1 +lbl21mod4b: AND16 + NEXTOPCODE +Op22mod4: +lbl22mod4: Op22 + NEXTOPCODE +Op23M0mod4: +lbl23mod4a: StackasmRelative +lbl23mod4b: AND16 + NEXTOPCODE +Op24M0mod4: +lbl24mod4a: Direct +lbl24mod4b: BIT16 + NEXTOPCODE +Op25M0mod4: +lbl25mod4a: Direct +lbl25mod4b: AND16 + NEXTOPCODE +Op26M0mod4: +lbl26mod4a: Direct +lbl26mod4b: ROL16 + NEXTOPCODE +Op27M0mod4: +lbl27mod4a: DirectIndirectLong +lbl27mod4b: AND16 + NEXTOPCODE +Op28mod4: +lbl28mod4: Op28X1M0 + NEXTOPCODE +.pool +Op29M0mod4: +lbl29mod4: Op29M0 + NEXTOPCODE +Op2AM0mod4: +lbl2Amod4a: A_ROL16 + NEXTOPCODE +Op2Bmod4: +lbl2Bmod4: Op2B + NEXTOPCODE +Op2CM0mod4: +lbl2Cmod4a: Absolute +lbl2Cmod4b: BIT16 + NEXTOPCODE +Op2DM0mod4: +lbl2Dmod4a: Absolute +lbl2Dmod4b: AND16 + NEXTOPCODE +Op2EM0mod4: +lbl2Emod4a: Absolute +lbl2Emod4b: ROL16 + NEXTOPCODE +Op2FM0mod4: +lbl2Fmod4a: AbsoluteLong +lbl2Fmod4b: AND16 + NEXTOPCODE +Op30mod4: +lbl30mod4: Op30 + NEXTOPCODE +Op31M0mod4: +lbl31mod4a: DirectIndirectIndexed1 +lbl31mod4b: AND16 + NEXTOPCODE +Op32M0mod4: +lbl32mod4a: DirectIndirect +lbl32mod4b: AND16 + NEXTOPCODE +Op33M0mod4: +lbl33mod4a: StackasmRelativeIndirectIndexed1 +lbl33mod4b: AND16 + NEXTOPCODE +Op34M0mod4: +lbl34mod4a: DirectIndexedX1 +lbl34mod4b: BIT16 + NEXTOPCODE +Op35M0mod4: +lbl35mod4a: DirectIndexedX1 +lbl35mod4b: AND16 + NEXTOPCODE +Op36M0mod4: +lbl36mod4a: DirectIndexedX1 +lbl36mod4b: ROL16 + NEXTOPCODE +Op37M0mod4: +lbl37mod4a: DirectIndirectIndexedLong1 +lbl37mod4b: AND16 + NEXTOPCODE +Op38mod4: +lbl38mod4: Op38 + NEXTOPCODE +Op39M0mod4: +lbl39mod4a: AbsoluteIndexedY1 +lbl39mod4b: AND16 + NEXTOPCODE +Op3AM0mod4: +lbl3Amod4a: A_DEC16 + NEXTOPCODE +Op3Bmod4: +lbl3Bmod4: Op3BM0 + NEXTOPCODE +Op3CM0mod4: +lbl3Cmod4a: AbsoluteIndexedX1 +lbl3Cmod4b: BIT16 + NEXTOPCODE +Op3DM0mod4: +lbl3Dmod4a: AbsoluteIndexedX1 +lbl3Dmod4b: AND16 + NEXTOPCODE +Op3EM0mod4: +lbl3Emod4a: AbsoluteIndexedX1 +lbl3Emod4b: ROL16 + NEXTOPCODE +Op3FM0mod4: +lbl3Fmod4a: AbsoluteLongIndexedX1 +lbl3Fmod4b: AND16 + NEXTOPCODE +Op40mod4: +lbl40mod4: Op40X1M0 + NEXTOPCODE +.pool +Op41M0mod4: +lbl41mod4a: DirectIndexedIndirect1 +lbl41mod4b: EOR16 + NEXTOPCODE +Op42mod4: +lbl42mod4: Op42 + NEXTOPCODE +Op43M0mod4: +lbl43mod4a: StackasmRelative +lbl43mod4b: EOR16 + NEXTOPCODE +Op44X1mod4: +lbl44mod4: Op44X1M0 + NEXTOPCODE +Op45M0mod4: +lbl45mod4a: Direct +lbl45mod4b: EOR16 + NEXTOPCODE +Op46M0mod4: +lbl46mod4a: Direct +lbl46mod4b: LSR16 + NEXTOPCODE +Op47M0mod4: +lbl47mod4a: DirectIndirectLong +lbl47mod4b: EOR16 + NEXTOPCODE +Op48M0mod4: +lbl48mod4: Op48M0 + NEXTOPCODE +Op49M0mod4: +lbl49mod4: Op49M0 + NEXTOPCODE +Op4AM0mod4: +lbl4Amod4a: A_LSR16 + NEXTOPCODE +Op4Bmod4: +lbl4Bmod4: Op4B + NEXTOPCODE +Op4Cmod4: +lbl4Cmod4: Op4C + NEXTOPCODE +Op4DM0mod4: +lbl4Dmod4a: Absolute +lbl4Dmod4b: EOR16 + NEXTOPCODE +Op4EM0mod4: +lbl4Emod4a: Absolute +lbl4Emod4b: LSR16 + NEXTOPCODE +Op4FM0mod4: +lbl4Fmod4a: AbsoluteLong +lbl4Fmod4b: EOR16 + NEXTOPCODE +Op50mod4: +lbl50mod4: Op50 + NEXTOPCODE +Op51M0mod4: +lbl51mod4a: DirectIndirectIndexed1 +lbl51mod4b: EOR16 + NEXTOPCODE +Op52M0mod4: +lbl52mod4a: DirectIndirect +lbl52mod4b: EOR16 + NEXTOPCODE +Op53M0mod4: +lbl53mod4a: StackasmRelativeIndirectIndexed1 +lbl53mod4b: EOR16 + NEXTOPCODE + +Op54X1mod4: +lbl54mod4: Op54X1M0 + NEXTOPCODE +Op55M0mod4: +lbl55mod4a: DirectIndexedX1 +lbl55mod4b: EOR16 + NEXTOPCODE +Op56M0mod4: +lbl56mod4a: DirectIndexedX1 +lbl56mod4b: LSR16 + NEXTOPCODE +Op57M0mod4: +lbl57mod4a: DirectIndirectIndexedLong1 +lbl57mod4b: EOR16 + NEXTOPCODE +Op58mod4: +lbl58mod4: Op58 + NEXTOPCODE +Op59M0mod4: +lbl59mod4a: AbsoluteIndexedY1 +lbl59mod4b: EOR16 + NEXTOPCODE +Op5AX1mod4: +lbl5Amod4: Op5AX1 + NEXTOPCODE +Op5Bmod4: +lbl5Bmod4: Op5BM0 + NEXTOPCODE +Op5Cmod4: +lbl5Cmod4: Op5C + NEXTOPCODE +Op5DM0mod4: +lbl5Dmod4a: AbsoluteIndexedX1 +lbl5Dmod4b: EOR16 + NEXTOPCODE +Op5EM0mod4: +lbl5Emod4a: AbsoluteIndexedX1 +lbl5Emod4b: LSR16 + NEXTOPCODE +Op5FM0mod4: +lbl5Fmod4a: AbsoluteLongIndexedX1 +lbl5Fmod4b: EOR16 + NEXTOPCODE +Op60mod4: +lbl60mod4: Op60 + NEXTOPCODE +Op61M0mod4: +lbl61mod4a: DirectIndexedIndirect1 +lbl61mod4b: ADC16 + NEXTOPCODE +Op62mod4: +lbl62mod4: Op62 + NEXTOPCODE +Op63M0mod4: +lbl63mod4a: StackasmRelative +lbl63mod4b: ADC16 + NEXTOPCODE +.pool +Op64M0mod4: +lbl64mod4a: Direct +lbl64mod4b: STZ16 + NEXTOPCODE +Op65M0mod4: +lbl65mod4a: Direct +lbl65mod4b: ADC16 + NEXTOPCODE +.pool +Op66M0mod4: +lbl66mod4a: Direct +lbl66mod4b: ROR16 + NEXTOPCODE +Op67M0mod4: +lbl67mod4a: DirectIndirectLong +lbl67mod4b: ADC16 + NEXTOPCODE +.pool +Op68M0mod4: +lbl68mod4: Op68M0 + NEXTOPCODE +Op69M0mod4: +lbl69mod4a: Immediate16 +lbl69mod4b: ADC16 + NEXTOPCODE +.pool +Op6AM0mod4: +lbl6Amod4a: A_ROR16 + NEXTOPCODE +Op6Bmod4: +lbl6Bmod4: Op6B + NEXTOPCODE +Op6Cmod4: +lbl6Cmod4: Op6C + NEXTOPCODE +Op6DM0mod4: +lbl6Dmod4a: Absolute +lbl6Dmod4b: ADC16 + NEXTOPCODE +Op6EM0mod4: +lbl6Emod4a: Absolute +lbl6Emod4b: ROR16 + NEXTOPCODE +Op6FM0mod4: +lbl6Fmod4a: AbsoluteLong +lbl6Fmod4b: ADC16 + NEXTOPCODE +Op70mod4: +lbl70mod4: Op70 + NEXTOPCODE +Op71M0mod4: +lbl71mod4a: DirectIndirectIndexed1 +lbl71mod4b: ADC16 + NEXTOPCODE +Op72M0mod4: +lbl72mod4a: DirectIndirect +lbl72mod4b: ADC16 + NEXTOPCODE +Op73M0mod4: +lbl73mod4a: StackasmRelativeIndirectIndexed1 +lbl73mod4b: ADC16 + NEXTOPCODE +.pool +Op74M0mod4: +lbl74mod4a: DirectIndexedX1 +lbl74mod4b: STZ16 + NEXTOPCODE +Op75M0mod4: +lbl75mod4a: DirectIndexedX1 +lbl75mod4b: ADC16 + NEXTOPCODE +.pool +Op76M0mod4: +lbl76mod4a: DirectIndexedX1 +lbl76mod4b: ROR16 + NEXTOPCODE +Op77M0mod4: +lbl77mod4a: DirectIndirectIndexedLong1 +lbl77mod4b: ADC16 + NEXTOPCODE +Op78mod4: +lbl78mod4: Op78 + NEXTOPCODE +Op79M0mod4: +lbl79mod4a: AbsoluteIndexedY1 +lbl79mod4b: ADC16 + NEXTOPCODE +Op7AX1mod4: +lbl7Amod4: Op7AX1 + NEXTOPCODE +Op7Bmod4: +lbl7Bmod4: Op7BM0 + NEXTOPCODE +Op7Cmod4: +lbl7Cmod4: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE +Op7DM0mod4: +lbl7Dmod4a: AbsoluteIndexedX1 +lbl7Dmod4b: ADC16 + NEXTOPCODE +Op7EM0mod4: +lbl7Emod4a: AbsoluteIndexedX1 +lbl7Emod4b: ROR16 + NEXTOPCODE +Op7FM0mod4: +lbl7Fmod4a: AbsoluteLongIndexedX1 +lbl7Fmod4b: ADC16 + NEXTOPCODE +.pool +Op80mod4: +lbl80mod4: Op80 + NEXTOPCODE +Op81M0mod4: +lbl81mod4a: DirectIndexedIndirect1 +lbl81mod4b: Op81M0 + NEXTOPCODE +Op82mod4: +lbl82mod4: Op82 + NEXTOPCODE +Op83M0mod4: +lbl83mod4a: StackasmRelative +lbl83mod4b: STA16 + NEXTOPCODE +Op84X1mod4: +lbl84mod4a: Direct +lbl84mod4b: STY8 + NEXTOPCODE +Op85M0mod4: +lbl85mod4a: Direct +lbl85mod4b: STA16 + NEXTOPCODE +Op86X1mod4: +lbl86mod4a: Direct +lbl86mod4b: STX8 + NEXTOPCODE +Op87M0mod4: +lbl87mod4a: DirectIndirectLong +lbl87mod4b: STA16 + NEXTOPCODE +Op88X1mod4: +lbl88mod4: Op88X1 + NEXTOPCODE +Op89M0mod4: +lbl89mod4: Op89M0 + NEXTOPCODE +Op8AM0mod4: +lbl8Amod4: Op8AM0X1 + NEXTOPCODE +Op8Bmod4: +lbl8Bmod4: Op8B + NEXTOPCODE +Op8CX1mod4: +lbl8Cmod4a: Absolute +lbl8Cmod4b: STY8 + NEXTOPCODE +Op8DM0mod4: +lbl8Dmod4a: Absolute +lbl8Dmod4b: STA16 + NEXTOPCODE +Op8EX1mod4: +lbl8Emod4a: Absolute +lbl8Emod4b: STX8 + NEXTOPCODE +Op8FM0mod4: +lbl8Fmod4a: AbsoluteLong +lbl8Fmod4b: STA16 + NEXTOPCODE +Op90mod4: +lbl90mod4: Op90 + NEXTOPCODE +Op91M0mod4: +lbl91mod4a: DirectIndirectIndexed1 +lbl91mod4b: STA16 + NEXTOPCODE +Op92M0mod4: +lbl92mod4a: DirectIndirect +lbl92mod4b: STA16 + NEXTOPCODE +Op93M0mod4: +lbl93mod4a: StackasmRelativeIndirectIndexed1 +lbl93mod4b: STA16 + NEXTOPCODE +Op94X1mod4: +lbl94mod4a: DirectIndexedX1 +lbl94mod4b: STY8 + NEXTOPCODE +Op95M0mod4: +lbl95mod4a: DirectIndexedX1 +lbl95mod4b: STA16 + NEXTOPCODE +Op96X1mod4: +lbl96mod4a: DirectIndexedY1 +lbl96mod4b: STX8 + NEXTOPCODE +Op97M0mod4: +lbl97mod4a: DirectIndirectIndexedLong1 +lbl97mod4b: STA16 + NEXTOPCODE +Op98M0mod4: +lbl98mod4: Op98M0X1 + NEXTOPCODE +Op99M0mod4: +lbl99mod4a: AbsoluteIndexedY1 +lbl99mod4b: STA16 + NEXTOPCODE +Op9Amod4: +lbl9Amod4: Op9AX1 + NEXTOPCODE +Op9BX1mod4: +lbl9Bmod4: Op9BX1 + NEXTOPCODE +Op9CM0mod4: +lbl9Cmod4a: Absolute +lbl9Cmod4b: STZ16 + NEXTOPCODE +Op9DM0mod4: +lbl9Dmod4a: AbsoluteIndexedX1 +lbl9Dmod4b: STA16 + NEXTOPCODE +Op9EM0mod4: +lbl9Emod4: AbsoluteIndexedX1 + STZ16 + NEXTOPCODE +Op9FM0mod4: +lbl9Fmod4a: AbsoluteLongIndexedX1 +lbl9Fmod4b: STA16 + NEXTOPCODE +OpA0X1mod4: +lblA0mod4: OpA0X1 + NEXTOPCODE +OpA1M0mod4: +lblA1mod4a: DirectIndexedIndirect1 +lblA1mod4b: LDA16 + NEXTOPCODE +OpA2X1mod4: +lblA2mod4: OpA2X1 + NEXTOPCODE +OpA3M0mod4: +lblA3mod4a: StackasmRelative +lblA3mod4b: LDA16 + NEXTOPCODE +OpA4X1mod4: +lblA4mod4a: Direct +lblA4mod4b: LDY8 + NEXTOPCODE +OpA5M0mod4: +lblA5mod4a: Direct +lblA5mod4b: LDA16 + NEXTOPCODE +OpA6X1mod4: +lblA6mod4a: Direct +lblA6mod4b: LDX8 + NEXTOPCODE +OpA7M0mod4: +lblA7mod4a: DirectIndirectLong +lblA7mod4b: LDA16 + NEXTOPCODE +OpA8X1mod4: +lblA8mod4: OpA8X1M0 + NEXTOPCODE +OpA9M0mod4: +lblA9mod4: OpA9M0 + NEXTOPCODE +OpAAX1mod4: +lblAAmod4: OpAAX1M0 + NEXTOPCODE +OpABmod4: +lblABmod4: OpAB + NEXTOPCODE +OpACX1mod4: +lblACmod4a: Absolute +lblACmod4b: LDY8 + NEXTOPCODE +OpADM0mod4: +lblADmod4a: Absolute +lblADmod4b: LDA16 + NEXTOPCODE +OpAEX1mod4: +lblAEmod4a: Absolute +lblAEmod4b: LDX8 + NEXTOPCODE +OpAFM0mod4: +lblAFmod4a: AbsoluteLong +lblAFmod4b: LDA16 + NEXTOPCODE +OpB0mod4: +lblB0mod4: OpB0 + NEXTOPCODE +OpB1M0mod4: +lblB1mod4a: DirectIndirectIndexed1 +lblB1mod4b: LDA16 + NEXTOPCODE +OpB2M0mod4: +lblB2mod4a: DirectIndirect +lblB2mod4b: LDA16 + NEXTOPCODE +OpB3M0mod4: +lblB3mod4a: StackasmRelativeIndirectIndexed1 +lblB3mod4b: LDA16 + NEXTOPCODE +OpB4X1mod4: +lblB4mod4a: DirectIndexedX1 +lblB4mod4b: LDY8 + NEXTOPCODE +OpB5M0mod4: +lblB5mod4a: DirectIndexedX1 +lblB5mod4b: LDA16 + NEXTOPCODE +OpB6X1mod4: +lblB6mod4a: DirectIndexedY1 +lblB6mod4b: LDX8 + NEXTOPCODE +OpB7M0mod4: +lblB7mod4a: DirectIndirectIndexedLong1 +lblB7mod4b: LDA16 + NEXTOPCODE +OpB8mod4: +lblB8mod4: OpB8 + NEXTOPCODE +OpB9M0mod4: +lblB9mod4a: AbsoluteIndexedY1 +lblB9mod4b: LDA16 + NEXTOPCODE +OpBAX1mod4: +lblBAmod4: OpBAX1 + NEXTOPCODE +OpBBX1mod4: +lblBBmod4: OpBBX1 + NEXTOPCODE +OpBCX1mod4: +lblBCmod4a: AbsoluteIndexedX1 +lblBCmod4b: LDY8 + NEXTOPCODE +OpBDM0mod4: +lblBDmod4a: AbsoluteIndexedX1 +lblBDmod4b: LDA16 + NEXTOPCODE +OpBEX1mod4: +lblBEmod4a: AbsoluteIndexedY1 +lblBEmod4b: LDX8 + NEXTOPCODE +OpBFM0mod4: +lblBFmod4a: AbsoluteLongIndexedX1 +lblBFmod4b: LDA16 + NEXTOPCODE +OpC0X1mod4: +lblC0mod4: OpC0X1 + NEXTOPCODE +OpC1M0mod4: +lblC1mod4a: DirectIndexedIndirect1 +lblC1mod4b: CMP16 + NEXTOPCODE +OpC2mod4: +lblC2mod4: OpC2 + NEXTOPCODE +.pool +OpC3M0mod4: +lblC3mod4a: StackasmRelative +lblC3mod4b: CMP16 + NEXTOPCODE +OpC4X1mod4: +lblC4mod4a: Direct +lblC4mod4b: CMY8 + NEXTOPCODE +OpC5M0mod4: +lblC5mod4a: Direct +lblC5mod4b: CMP16 + NEXTOPCODE +OpC6M0mod4: +lblC6mod4a: Direct +lblC6mod4b: DEC16 + NEXTOPCODE +OpC7M0mod4: +lblC7mod4a: DirectIndirectLong +lblC7mod4b: CMP16 + NEXTOPCODE +OpC8X1mod4: +lblC8mod4: OpC8X1 + NEXTOPCODE +OpC9M0mod4: +lblC9mod4: OpC9M0 + NEXTOPCODE +OpCAX1mod4: +lblCAmod4: OpCAX1 + NEXTOPCODE +OpCBmod4: +lblCBmod4: OpCB + NEXTOPCODE +OpCCX1mod4: +lblCCmod4a: Absolute +lblCCmod4b: CMY8 + NEXTOPCODE +OpCDM0mod4: +lblCDmod4a: Absolute +lblCDmod4b: CMP16 + NEXTOPCODE +OpCEM0mod4: +lblCEmod4a: Absolute +lblCEmod4b: DEC16 + NEXTOPCODE +OpCFM0mod4: +lblCFmod4a: AbsoluteLong +lblCFmod4b: CMP16 + NEXTOPCODE +OpD0mod4: +lblD0mod4: OpD0 + NEXTOPCODE +OpD1M0mod4: +lblD1mod4a: DirectIndirectIndexed1 +lblD1mod4b: CMP16 + + NEXTOPCODE +OpD2M0mod4: +lblD2mod4a: DirectIndirect +lblD2mod4b: CMP16 + NEXTOPCODE +OpD3M0mod4: +lblD3mod4a: StackasmRelativeIndirectIndexed1 +lblD3mod4b: CMP16 + NEXTOPCODE +OpD4mod4: +lblD4mod4: OpD4 + NEXTOPCODE +OpD5M0mod4: +lblD5mod4a: DirectIndexedX1 +lblD5mod4b: CMP16 + NEXTOPCODE +OpD6M0mod4: +lblD6mod4a: DirectIndexedX1 +lblD6mod4b: DEC16 + NEXTOPCODE +OpD7M0mod4: +lblD7mod4a: DirectIndirectIndexedLong1 +lblD7mod4b: CMP16 + NEXTOPCODE +OpD8mod4: +lblD8mod4: OpD8 + NEXTOPCODE +OpD9M0mod4: +lblD9mod4a: AbsoluteIndexedY1 +lblD9mod4b: CMP16 + NEXTOPCODE +OpDAX1mod4: +lblDAmod4: OpDAX1 + NEXTOPCODE +OpDBmod4: +lblDBmod4: OpDB + NEXTOPCODE +OpDCmod4: +lblDCmod4: OpDC + NEXTOPCODE +OpDDM0mod4: +lblDDmod4a: AbsoluteIndexedX1 +lblDDmod4b: CMP16 + NEXTOPCODE +OpDEM0mod4: +lblDEmod4a: AbsoluteIndexedX1 +lblDEmod4b: DEC16 + NEXTOPCODE +OpDFM0mod4: +lblDFmod4a: AbsoluteLongIndexedX1 +lblDFmod4b: CMP16 + NEXTOPCODE +OpE0X1mod4: +lblE0mod4: OpE0X1 + NEXTOPCODE +OpE1M0mod4: +lblE1mod4a: DirectIndexedIndirect1 +lblE1mod4b: SBC16 + NEXTOPCODE +OpE2mod4: +lblE2mod4: OpE2 + NEXTOPCODE +.pool +OpE3M0mod4: +lblE3mod4a: StackasmRelative +lblE3mod4b: SBC16 + NEXTOPCODE +OpE4X1mod4: +lblE4mod4a: Direct +lblE4mod4b: CMX8 + NEXTOPCODE +OpE5M0mod4: +lblE5mod4a: Direct +lblE5mod4b: SBC16 + NEXTOPCODE +OpE6M0mod4: +lblE6mod4a: Direct +lblE6mod4b: INC16 + NEXTOPCODE +OpE7M0mod4: +lblE7mod4a: DirectIndirectLong +lblE7mod4b: SBC16 + NEXTOPCODE +OpE8X1mod4: +lblE8mod4: OpE8X1 + NEXTOPCODE +OpE9M0mod4: +lblE9mod4a: Immediate16 +lblE9mod4b: SBC16 + NEXTOPCODE +OpEAmod4: +lblEAmod4: OpEA + NEXTOPCODE +OpEBmod4: +lblEBmod4: OpEBM0 + NEXTOPCODE +OpECX1mod4: +lblECmod4a: Absolute +lblECmod4b: CMX8 + NEXTOPCODE +OpEDM0mod4: +lblEDmod4a: Absolute +lblEDmod4b: SBC16 + NEXTOPCODE +OpEEM0mod4: +lblEEmod4a: Absolute +lblEEmod4b: INC16 + NEXTOPCODE +OpEFM0mod4: +lblEFmod4a: AbsoluteLong +lblEFmod4b: SBC16 + NEXTOPCODE +OpF0mod4: +lblF0mod4: OpF0 + NEXTOPCODE +OpF1M0mod4: +lblF1mod4a: DirectIndirectIndexed1 +lblF1mod4b: SBC16 + NEXTOPCODE +OpF2M0mod4: +lblF2mod4a: DirectIndirect +lblF2mod4b: SBC16 + NEXTOPCODE +OpF3M0mod4: +lblF3mod4a: StackasmRelativeIndirectIndexed1 +lblF3mod4b: SBC16 + NEXTOPCODE +OpF4mod4: +lblF4mod4: OpF4 + NEXTOPCODE +OpF5M0mod4: +lblF5mod4a: DirectIndexedX1 +lblF5mod4b: SBC16 + NEXTOPCODE +OpF6M0mod4: +lblF6mod4a: DirectIndexedX1 +lblF6mod4b: INC16 + NEXTOPCODE +OpF7M0mod4: +lblF7mod4a: DirectIndirectIndexedLong1 +lblF7mod4b: SBC16 + NEXTOPCODE +OpF8mod4: +lblF8mod4: OpF8 + NEXTOPCODE +OpF9M0mod4: +lblF9mod4a: AbsoluteIndexedY1 +lblF9mod4b: SBC16 + NEXTOPCODE +OpFAX1mod4: +lblFAmod4: OpFAX1 + NEXTOPCODE +OpFBmod4: +lblFBmod4: OpFB + NEXTOPCODE +OpFCmod4: +lblFCmod4: OpFCX1 + NEXTOPCODE +OpFDM0mod4: +lblFDmod4a: AbsoluteIndexedX1 +lblFDmod4b: SBC16 + NEXTOPCODE +OpFEM0mod4: +lblFEmod4a: AbsoluteIndexedX1 +lblFEmod4b: INC16 + NEXTOPCODE +OpFFM0mod4: +lblFFmod4a: AbsoluteLongIndexedX1 +lblFFmod4b: SBC16 + NEXTOPCODE + + + .pool + diff --git a/src/os9x_asm_cpu.cpp b/src/os9x_asm_cpu.cpp new file mode 100644 index 0000000..bfd2ec5 --- /dev/null +++ b/src/os9x_asm_cpu.cpp @@ -0,0 +1,255 @@ +#include "snes9x.h" +#include "apu.h" +#include "ppu.h" +#include "cpuexec.h" +//#include "cpuops.h" + +#include "os9x_asm_cpu.h" + +//#define __debug_c_irq__ +//#define __debug_c_nmi__ +//#define __debug_c_hblank__ +//#define __debug_c_io__ + +START_EXTERN_C + +void asm_S9xSetPCBase(uint32 Address) +{ +#ifdef __debug_c_setpc__ + printf("spcb\n"); +#endif + S9xSetPCBase(Address); +} + + +#ifdef _C_GW_ +#define PushW(w) \ + S9xSetWord (w, Registers.S.W - 1);\ + Registers.S.W -= 2; +#define PushB(b)\ + S9xSetByte (b, Registers.S.W--); + + +void asm_S9xMainLoop(void) +{ + //S9xPackStatus(); + //printf("asmMainLoop Enter(0x%08x).\n", CPU.Flags); + asmMainLoop(&CPU); + //printf("asmMainLoop Exit(0x%08x, %d).\n", CPU.PC - CPU.PCBase, CPU.Cycles); + //S9xUnpackStatus(); +} + +void asm_S9xDoHBlankProcessing(void) +{ +#ifdef __debug_c_hblank__ + printf("hblank\n"); +#endif +// S9xUnpackStatus(); // not needed + S9xDoHBlankProcessing(); +// S9xPackStatus(); +} + + +uint8 asm_S9xGetByte(uint32 Address) +{ +#ifdef __debug_c_io__ + printf("gb\n"); +#endif + return S9xGetByte(Address); +} + +uint16 asm_S9xGetWord(uint32 Address) +{ +#ifdef __debug_c_io__ + printf("gw\n"); +#endif + return S9xGetWord(Address); +} + + +void asm_S9xSetByte(uint32 Address,uint8 value) +{ +#ifdef __debug_c_io__ + printf("sb\n"); +#endif + S9xSetByte(value,Address); +} + +void asm_S9xSetWord(uint32 Address,uint16 value) +{ +#ifdef __debug_c_io__ + printf("sw\n"); +#endif + S9xSetWord(value,Address); +} + + +void asm_S9xOpcode_NMI(void) +{ +#ifdef __debug_c_nmi__ + printf("nmi\n"); +#endif +// S9xUnpackStatus(); // not needed + + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); +// S9xPackStatus (); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; +// c = 0; // unused +#ifdef USE_SA1 + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20)) + S9xSetPCBase (Memory.FillRAM [0x220c] | + (Memory.FillRAM [0x220d] << 8)); + else +#endif + S9xSetPCBase (S9xGetWord (0xFFEA)); +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#else + CPU.Cycles += 8; +#endif + } + else + { + PushW (CPU.PC - CPU.PCBase); +// S9xPackStatus (); // not needed + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; +// ICPU.ShiftedPB = 0; // unused +#ifdef USE_SA1 + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x20)) + S9xSetPCBase (Memory.FillRAM [0x220c] | + (Memory.FillRAM [0x220d] << 8)); + else +#endif + S9xSetPCBase (S9xGetWord (0xFFFA)); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else + CPU.Cycles += 6; +#endif + } + +// S9xPackStatus(); // not needed +} + +void asm_S9xOpcode_IRQ(void) +{ +#ifdef __debug_c_irq__ + printf("irq\n"); +#endif +// S9xUnpackStatus(); // not needed + + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); +// S9xPackStatus (); // not needed + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; +// ICPU.ShiftedPB = 0; // unused + +#ifdef USE_SA1 + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40)) + S9xSetPCBase (Memory.FillRAM [0x220e] | + (Memory.FillRAM [0x220f] << 8)); + else +#endif + S9xSetPCBase (S9xGetWord (0xFFEE)); +#ifdef VAR_CYCLES + CPU.Cycles += TWO_CYCLES; +#else + CPU.Cycles += 8; +#endif + } + else + { + PushW (CPU.PC - CPU.PCBase); +// S9xPackStatus (); // not needed + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; +// ICPU.ShiftedPB = 0; // unused + +#ifdef USE_SA1 + if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40)) + S9xSetPCBase (Memory.FillRAM [0x220e] | + (Memory.FillRAM [0x220f] << 8)); + else +#endif + S9xSetPCBase (S9xGetWord (0xFFFE)); +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#else + CPU.Cycles += 6; +#endif + } + +// S9xPackStatus(); // not needed +} +#endif + +/* +void asm_APU_EXECUTE(int Mode) +{ +#ifdef __debug_c_apuex__ + printf("apuexec\n"); +#endif + if(CPU.APU_APUExecuting != Mode) return; + + if (Settings.asmspc700) + { + if(CPU.APU_Cycles < CPU.Cycles) { + int cycles = CPU.Cycles - CPU.APU_Cycles; + CPU.APU_Cycles += cycles - spc700_execute(cycles); + } + } + else + { + while (CPU.APU_Cycles <= CPU.Cycles) + { + CPU.APU_Cycles += S9xAPUCycles [*IAPU.PC]; + (*S9xApuOpcodes[*IAPU.PC]) (); + } + } +} + + +void asm_APU_EXECUTE2(void) +{ + if(CPU.APU_APUExecuting != 1) return; + + //ICPU.CPUExecuting = FALSE; + if (Settings.asmspc700) + { + if(CPU.APU_Cycles < CPU.NextEvent) { + int cycles = CPU.NextEvent - CPU.APU_Cycles; + CPU.APU_Cycles += cycles - spc700_execute(cycles); + } + } + else + { + do + { + CPU.APU_Cycles += S9xAPUCycles [*IAPU.PC]; + (*S9xApuOpcodes[*IAPU.PC]) (); + } while (CPU.APU_Cycles < CPU.NextEvent); + } + //ICPU.CPUExecuting = TRUE; +}*/ + +END_EXTERN_C diff --git a/src/os9x_asm_cpu.h b/src/os9x_asm_cpu.h new file mode 100644 index 0000000..250e55f --- /dev/null +++ b/src/os9x_asm_cpu.h @@ -0,0 +1,11 @@ +#ifndef __os9x_asm_cpu__ +#define __os9x_asm_cpu__ + +extern "C" void test_opcode(SCPUState *cpuptr); + +extern "C" void asmMainLoop_spcC(SCPUState *cpuptr); +extern "C" void asmMainLoop_spcAsm(SCPUState *cpuptr); + +extern "C" void asm_S9xMainLoop(void); + +#endif diff --git a/src/osd_disk.c b/src/osd_disk.c new file mode 100644 index 0000000..20ab220 --- /dev/null +++ b/src/osd_disk.c @@ -0,0 +1,45 @@ +/* GIMP RGB C-Source image dump (osd_disk.c) */ + +static const struct { + unsigned int width; + unsigned int height; + unsigned int bytes_per_pixel; /* 3:RGB, 4:RGBA */ + unsigned char pixel_data[16 * 16 * 3 + 1]; +} osd_img_disk = { + 16, 16, 3, + "\0\0\0Ir\263Ir\263\200\234\313\200\234\313\200\234\313\200\234\313\200\234" + "\313\200\234\313\200\234\313\200\234\313\200\234\313\200\234\313Ir\263Ir" + "\263\0\0\0Go\261m\245\341m\245\341\377\377\377\377\377\377\377\377\377\377" + "\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377" + "\377\377m\245\341m\245\341Go\261El\257m\245\341m\245\341\377\377\377\377" + "\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377" + "\377\377\377\377\377\377\377\377m\245\341m\245\341El\257Bh\254i\241\337i" + "\241\337\377\377\377\334\352\370\270\324\361\270\324\361\270\324\361\270" + "\324\361\270\324\361\270\324\361\334\352\370\377\377\377i\241\337i\241\337" + "Bh\254?e\250d\235\335d\235\335\377\377\377\377\377\377\377\377\377\377\377" + "\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377" + "\377d\235\335d\235\335?e\250<`\244^\230\332^\230\332\377\377\377\334\352" + "\370\270\324\361\270\324\361\270\324\361\270\324\361\270\324\361\270\324" + "\361\334\352\370\377\377\377^\230\332^\230\332<`\2448[\240X\223\327X\223" + "\327\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377" + "\377\377\377\377\377\377\377\377\377\377\377\377\377X\223\327X\223\3278[" + "\2404U\235R\215\324R\215\324\272\321\356\377\377\377\377\377\377\377\377" + "\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\377\272\321" + "\356R\215\324R\215\3244U\2350Q\230K\207\320K\207\320K\207\320K\207\320K\207" + "\320K\207\320K\207\320K\207\320K\207\320K\207\320K\207\320K\207\320K\207" + "\320K\207\3200Q\230-L\224D\201\315D\201\315D\201\315D\201\315D\201\315D\201" + "\315D\201\315D\201\315D\201\315D\201\315D\201\315D\201\315D\201\315D\201" + "\315-L\224)F\220>{\312>{\312>{\312\311\325\344\354\354\352\354\354\352\354" + "\354\352\354\354\352\354\354\352\354\354\352\311\325\344'?\214>{\312>{\312" + ")F\220%A\2148v\3078v\3078v\307\354\354\352.U\244.U\244\354\354\352\354\354" + "\352\354\354\352\354\354\352\354\354\352'?\2148v\3078v\307%A\214\"=\2112" + "q\3042q\3042q\304\354\354\352+S\242+S\242\354\354\352\354\354\352\354\354" + "\352\354\354\352\354\354\352'?\2142q\3042q\304\"=\211\0\0\0\36""9\205-m\302" + "-m\302\354\354\352)Q\242)Q\242\354\354\352\354\354\352\354\354\352\354\354" + "\352\354\354\352'?\214-m\302-m\302\36""9\205\0\0\0\0\0\0\34""5\202)i\300" + "\354\354\352\354\354\352\354\354\352\354\354\352\354\354\352\354\354\352" + "\354\354\352\354\354\352'?\214)i\300)i\300\34""5\202\0\0\0\0\0\0\0\0\0\32" + """2\177\203\220\265\203\220\265\203\220\265\203\220\265\203\220\265\203\220" + "\265\203\220\265\203\220\265\32""2\177\32""2\177\32""2\177\0\0\0", +}; + diff --git a/src/osnes9xgp_asmfunc.S b/src/osnes9xgp_asmfunc.S new file mode 100644 index 0000000..7cdc3ec --- /dev/null +++ b/src/osnes9xgp_asmfunc.S @@ -0,0 +1,101 @@ + .global asmClearScreenFast8 + .global asmClearScreenFast16 + +asmClearScreenFast16: +;@R0 = scr +;@R1 = starty +;@R2 = endy +;@R3 = col + stmfd R13!,{R4-R11} + + sub R12,R2,R1 + add R12,R12,#1 + ;@R12 = endy-starty+1 + + mov r2,#320 + mul r1,r2,r1 + ;@R1 = 320*starty + + add R0,R0,R1,lsl #1 + ;@R0 = screen + ((320*starty)<<1) + + mov R2,R3 + mov R4,R3 + mov R5,R3 + mov R6,R3 + mov R7,R3 + mov R8,R3 + mov R9,R3 +2: + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + + add r0,r0,#32*4 + + subs R12,R12,#1 + bne 2b + + ldmfd R13!,{R4-R11} + mov PC,LR + + +asmClearScreenFast8: +;R0 = scr +;R1 = starty +;R2 = endy +;R3 = col + stmfd R13!,{R4-R11} + + sub R12,R2,R1 + add R12,R12,#1 + ;@R12 = endy-starty+1 + + mov r2,#320 + mul r1,r2,r1 + ;@R1 = 320*starty + + add R0,R0,R1 + ;@R0 = screen + ((320*starty)) + + mov R2,R3 + mov R4,R3 + mov R5,R3 + mov R6,R3 + mov R7,R3 + mov R8,R3 + mov R9,R3 + +2: + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + stmia R0!,{R2,R3,R4,R5,R6,R7,R8,R9} + + subs R12,R12,#1 + bne 2b + + ldmfd R13!,{R4-R11} + mov PC,LR + + \ No newline at end of file diff --git a/src/out.s b/src/out.s new file mode 100644 index 0000000..2242e34 --- /dev/null +++ b/src/out.s @@ -0,0 +1,10697 @@ + .DATA +/**************************************************************** +****************************************************************/ + .align 4 + + @ notaz + .equiv ASM_SPC700, 1 ;@ 1 = use notaz's ASM_SPC700 core + +/**************************************************************** + DEFINES +****************************************************************/ + +.equ MAP_LAST, 12 + +rstatus .req R4 @ format : 0xff800000 +reg_d_bank .req R4 @ format : 0x000000ll +reg_a .req R5 @ format : 0xhhll0000 or 0xll000000 +reg_d .req R6 @ format : 0xhhll0000 +reg_p_bank .req R6 @ format : 0x000000ll +reg_x .req R7 @ format : 0xhhll0000 or 0xll000000 +reg_s .req R8 @ format : 0x0000hhll +reg_y .req R9 @ format : 0xhhll0000 or 0xll000000 + +rpc .req R10 @ 32bits address +reg_cycles .req R11 @ 32bits counter +regpcbase .req R12 @ 32bits address + +rscratch .req R0 @ format : 0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD +regopcode .req R0 @ format : 0x000000ll +rscratch2 .req R1 @ format : 0xhhll for calculation and value +rscratch3 .req R2 @ +rscratch4 .req R3 @ ?????? + +@ used for SBC opcode +rscratch9 .req R10 @ ?????? + +reg_cpu_var .req R14 + + + +@ not used +@ R13 @ Pointer 32 bit on a struct. + +@ R15 = pc (sic!) + + +/* +.equ Carry 1 +.equ Zero 2 +.equ IRQ 4 +.equ Decimal 8 +.equ IndexFlag 16 +.equ MemoryFlag 32 +.equ Overflow 64 +.equ Negative 128 +.equ Emulation 256*/ + +.equ STATUS_SHIFTER, 24 +.equ MASK_EMUL, (1<<(STATUS_SHIFTER-1)) +.equ MASK_SHIFTER_CARRY, (STATUS_SHIFTER+1) +.equ MASK_CARRY, (1<<(STATUS_SHIFTER)) @ 0 +.equ MASK_ZERO, (2<<(STATUS_SHIFTER)) @ 1 +.equ MASK_IRQ, (4<<(STATUS_SHIFTER)) @ 2 +.equ MASK_DECIMAL, (8<<(STATUS_SHIFTER)) @ 3 +.equ MASK_INDEX, (16<<(STATUS_SHIFTER)) @ 4 @ 1 +.equ MASK_MEM, (32<<(STATUS_SHIFTER)) @ 5 @ 2 +.equ MASK_OVERFLOW, (64<<(STATUS_SHIFTER)) @ 6 @ 4 +.equ MASK_NEG, (128<<(STATUS_SHIFTER))@ 7 @ 8 + +.equ ONE_CYCLE, 6 +.equ SLOW_ONE_CYCLE, 8 + +.equ NMI_FLAG, (1 << 7) +.equ IRQ_PENDING_FLAG, (1 << 11) +.equ SCAN_KEYS_FLAG, (1 << 4) + + +.equ MEMMAP_BLOCK_SIZE, (0x1000) +.equ MEMMAP_SHIFT, 12 +.equ MEMMAP_MASK, (0xFFF) + +/**************************************************************** + MACROS +****************************************************************/ + +@ #include "os9x_65c816_mac_gen.h" +/*****************************************************************/ +/* Offset in SCPUState structure */ +/*****************************************************************/ +.equ Flags_ofs, 0 +.equ BranchSkip_ofs, 4 +.equ NMIActive_ofs, 5 +.equ IRQActive_ofs, 6 +.equ WaitingForInterrupt_ofs, 7 + +.equ RPB_ofs, 8 +.equ RDB_ofs, 9 +.equ RP_ofs, 10 +.equ RA_ofs, 12 +.equ RAH_ofs, 13 +.equ RD_ofs, 14 +.equ RX_ofs, 16 +.equ RS_ofs, 18 +.equ RY_ofs, 20 +@.equ RPC_ofs, 22 + +.equ PC_ofs, 24 +.equ Cycles_ofs, 28 +.equ PCBase_ofs, 32 + +.equ PCAtOpcodeStart_ofs, 36 +.equ WaitAddress_ofs, 40 +.equ WaitCounter_ofs, 44 +.equ NextEvent_ofs, 48 +.equ V_Counter_ofs, 52 +.equ MemSpeed_ofs, 56 +.equ MemSpeedx2_ofs, 60 +.equ FastROMSpeed_ofs, 64 +.equ AutoSaveTimer_ofs, 68 +.equ NMITriggerPoint_ofs, 72 +.equ NMICycleCount_ofs, 76 +.equ IRQCycleCount_ofs, 80 + +.equ InDMA_ofs, 84 +.equ WhichEvent, 85 +.equ SRAMModified_ofs, 86 +.equ BRKTriggered_ofs, 87 +.equ asm_OPTABLE_ofs, 88 +.equ TriedInterleavedMode2_ofs, 92 + +.equ Map_ofs, 96 +.equ WriteMap_ofs, 100 +.equ MemorySpeed_ofs, 104 +.equ BlockIsRAM_ofs, 108 +.equ SRAM, 112 +.equ BWRAM, 116 +.equ SRAMMask, 120 + +.equ APUExecuting_ofs, 124 + +.equ PALMOS_R9_ofs, 132 +.equ PALMOS_R10_ofs, 136 + +@ notaz +.equ APU_Cycles, 140 + +/*****************************************************************/ +/* Offset in CMemory structure */ +/*****************************************************************/ +.equ _sram, 12 +.equ _bwram, 16 +.equ _fillram, 20 +.equ _c4ram, 24 + +/*****************************************************************/ + +/* prepare */ +.macro PREPARE_C_CALL + STMFD R13!,{R12,R14} +.endm +.macro PREPARE_C_CALL_R0 + STMFD R13!,{R0,R12,R14} +.endm +.macro PREPARE_C_CALL_R0R1 + STMFD R13!,{R0,R1,R12,R14} +.endm +.macro PREPARE_C_CALL_LIGHT + STMFD R13!,{R14} +.endm +.macro PREPARE_C_CALL_LIGHTR12 + STMFD R13!,{R12,R14} +.endm +/* restore */ +.macro RESTORE_C_CALL + LDMFD R13!,{R12,R14} +.endm +.macro RESTORE_C_CALL_R0 + LDMFD R13!,{R0,R12,R14} +.endm +.macro RESTORE_C_CALL_R1 + LDMFD R13!,{R1,R12,R14} +.endm +.macro RESTORE_C_CALL_LIGHT + LDMFD R13!,{R14} +.endm +.macro RESTORE_C_CALL_LIGHTR12 + LDMFD R13!,{R12,R14} +.endm + + +@ -------------- +.macro LOAD_REGS + @ notaz + add r0,reg_cpu_var,#8 + ldmia r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase} + @ rstatus (P) & reg_d_bank + mov reg_d_bank,r1,lsl #16 + mov reg_d_bank,reg_d_bank,lsr #24 + mov r0,r1,lsr #16 + orrs rstatus, rstatus, r0,lsl #STATUS_SHIFTER @ 24 + @ if Carry set, then EMULATION bit was set + orrcs rstatus,rstatus,#MASK_EMUL + @ reg_d & reg_p_bank + mov reg_d,reg_a,lsr #16 + mov reg_d,reg_d,lsl #8 + orr reg_d,reg_d,r1,lsl #24 + mov reg_d,reg_d,ror #24 @ 0xdddd00pb + @ reg_x, reg_s + mov reg_s,reg_x,lsr #16 + @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits) + tst rstatus,#MASK_INDEX + movne reg_x,reg_x,lsl #24 + movne reg_y,reg_y,lsl #24 + moveq reg_x,reg_x,lsl #16 + moveq reg_y,reg_y,lsl #16 + tst rstatus,#MASK_MEM + movne reg_a,reg_a,lsl #24 + moveq reg_a,reg_a,lsl #16 + +/* + @ reg_d & reg_p_bank share the same register + LDRB reg_p_bank,[reg_cpu_var,#RPB_ofs] + LDRH rscratch,[reg_cpu_var,#RD_ofs] + ORR reg_d,reg_d,rscratch, LSL #16 + @ rstatus & reg_d_bank share the same register + LDRB reg_d_bank,[reg_cpu_var,#RDB_ofs] + LDRH rscratch,[reg_cpu_var,#RP_ofs] + ORRS rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER @ 24 + @ if Carry set, then EMULATION bit was set + ORRCS rstatus,rstatus,#MASK_EMUL + @ + LDRH reg_a,[reg_cpu_var,#RA_ofs] + LDRH reg_x,[reg_cpu_var,#RX_ofs] + LDRH reg_y,[reg_cpu_var,#RY_ofs] + LDRH reg_s,[reg_cpu_var,#RS_ofs] + @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits) + TST rstatus,#MASK_INDEX + MOVNE reg_x,reg_x,LSL #24 + MOVNE reg_y,reg_y,LSL #24 + MOVEQ reg_x,reg_x,LSL #16 + MOVEQ reg_y,reg_y,LSL #16 + TST rstatus,#MASK_MEM + MOVNE reg_a,reg_a,LSL #24 + MOVEQ reg_a,reg_a,LSL #16 + + LDR regpcbase,[reg_cpu_var,#PCBase_ofs] + LDR rpc,[reg_cpu_var,#PC_ofs] + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] +*/ +.endm + + +.macro SAVE_REGS + @ notaz + @ reg_p_bank, reg_d_bank and rstatus + mov r1, rstatus, lsr #16 + orr r1, r1, reg_p_bank, lsl #24 + movs r1, r1, lsr #8 + orrcs r1, r1, #0x100 @ EMULATION bit + orr r1, r1, reg_d_bank, lsl #24 + mov r1, r1, ror #16 + @ reg_a, reg_d + tst rstatus,#MASK_MEM + ldrneh r0, [reg_cpu_var,#RA_ofs] + bicne r0, r0,#0xFF + orrne reg_a, r0, reg_a,lsr #24 + moveq reg_a, reg_a, lsr #16 + mov reg_d, reg_d, lsr #16 + orr reg_a, reg_a, reg_d, lsl #16 + @ Shift X&Y according to the current mode (INDEX, MEMORY bits) + tst rstatus,#MASK_INDEX + movne reg_x,reg_x,LSR #24 + movne reg_y,reg_y,LSR #24 + moveq reg_x,reg_x,LSR #16 + moveq reg_y,reg_y,LSR #16 + @ reg_x, reg_s + orr reg_x, reg_x, reg_s, lsl #16 + @ store + add r0,reg_cpu_var,#8 + stmia r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase} + +/* + @ reg_d & reg_p_bank is same register + STRB reg_p_bank,[reg_cpu_var,#RPB_ofs] + MOV rscratch,reg_d, LSR #16 + STRH rscratch,[reg_cpu_var,#RD_ofs] + @ rstatus & reg_d_bank is same register + STRB reg_d_bank,[reg_cpu_var,#RDB_ofs] + MOVS rscratch, rstatus, LSR #STATUS_SHIFTER + ORRCS rscratch,rscratch,#0x100 @ EMULATION bit + STRH rscratch,[reg_cpu_var,#RP_ofs] + @ + @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits) + TST rstatus,#MASK_INDEX + MOVNE rscratch,reg_x,LSR #24 + MOVNE rscratch2,reg_y,LSR #24 + MOVEQ rscratch,reg_x,LSR #16 + MOVEQ rscratch2,reg_y,LSR #16 + STRH rscratch,[reg_cpu_var,#RX_ofs] + STRH rscratch2,[reg_cpu_var,#RY_ofs] + TST rstatus,#MASK_MEM + LDRNEH rscratch,[reg_cpu_var,#RA_ofs] + BICNE rscratch,rscratch,#0xFF + ORRNE rscratch,rscratch,reg_a,LSR #24 + MOVEQ rscratch,reg_a,LSR #16 + STRH rscratch,[reg_cpu_var,#RA_ofs] + + STRH reg_s,[reg_cpu_var,#RS_ofs] + STR regpcbase,[reg_cpu_var,#PCBase_ofs] + STR rpc,[reg_cpu_var,#PC_ofs] + + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] +*/ +.endm + +/*****************************************************************/ +.macro ADD1CYCLE + @add reg_cycles,reg_cycles, #ONE_CYCLE +.endm +.macro ADD1CYCLENE + @addne reg_cycles,reg_cycles, #ONE_CYCLE +.endm +.macro ADD1CYCLEEQ + @addeq reg_cycles,reg_cycles, #ONE_CYCLE +.endm + +.macro ADD2CYCLE + @add reg_cycles,reg_cycles, #(ONE_CYCLE*2) +.endm +.macro ADD2CYCLENE + @addne reg_cycles,reg_cycles, #(ONE_CYCLE*2) +.endm +.macro ADD2CYCLE2MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + @add reg_cycles,reg_cycles, #(ONE_CYCLE*2) + @add reg_cycles, reg_cycles, rscratch, LSL #1 +.endm +.macro ADD2CYCLE1MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + @add reg_cycles,reg_cycles, #(ONE_CYCLE*2) + @add reg_cycles, reg_cycles, rscratch +.endm + +.macro ADD3CYCLE + @add reg_cycles,reg_cycles, #(ONE_CYCLE*3) +.endm + +.macro ADD1CYCLE1MEM + ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + add reg_cycles,reg_cycles, #ONE_CYCLE + add reg_cycles, reg_cycles, rscratch +.endm + +.macro ADD1CYCLE2MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + @add reg_cycles,reg_cycles, #ONE_CYCLE + @add reg_cycles, reg_cycles, rscratch, lsl #1 +.endm + +.macro ADD1MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + @add reg_cycles, reg_cycles, rscratch +.endm + +.macro ADD2MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + @add reg_cycles, reg_cycles, rscratch, lsl #1 +.endm + +.macro ADD3MEM + @ldr rscratch,[reg_cpu_var,#MemSpeed_ofs] + @add reg_cycles, rscratch, reg_cycles + @add reg_cycles, reg_cycles, rscratch, lsl #1 +.endm + +/**************/ +.macro ClearDecimal + BIC rstatus,rstatus,#MASK_DECIMAL +.endm +.macro SetDecimal + ORR rstatus,rstatus,#MASK_DECIMAL +.endm +.macro SetIRQ + ORR rstatus,rstatus,#MASK_IRQ +.endm +.macro ClearIRQ + BIC rstatus,rstatus,#MASK_IRQ +.endm + +.macro CPUShutdown +@ if (Settings.Shutdown && CPU.PC == CPU.WaitAddress) + LDR rscratch,[reg_cpu_var,#WaitAddress_ofs] + CMP rpc,rscratch + BNE 5431f +@ if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG))) + LDR rscratch,[reg_cpu_var,#Flags_ofs] + LDR rscratch2,[reg_cpu_var,#WaitCounter_ofs] + TST rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG) + BNE 5432f + MOVS rscratch2,rscratch2 + BNE 5432f +@ CPU.WaitAddress = NULL; + MOV rscratch,#0 + STR rscratch,[reg_cpu_var,#WaitAddress_ofs] +@ if (Settings.SA1) +@ S9xSA1ExecuteDuringSleep (); : TODO + +@ CPU.Cycles = CPU.NextEvent; + LDR reg_cycles,[reg_cpu_var,#NextEvent_ofs] + LDRB r0,[reg_cpu_var,#APUExecuting_ofs] + MOVS r0,r0 + BEQ 5431f +@ if (IAPU.APUExecuting) +/* { + ICPU.CPUExecuting = FALSE; + do + { + APU_EXECUTE1(); + } while (APU.Cycles < CPU.NextEvent); + ICPU.CPUExecuting = TRUE; + } + */ + asmAPU_EXECUTE2 + B 5431f +@.pool +5432: +/* else + if (CPU.WaitCounter >= 2) + CPU.WaitCounter = 1; + else + CPU.WaitCounter--; +*/ + CMP rscratch2,#1 + MOVHI rscratch2,#1 + @ SUBLS rscratch2,rscratch2,#1 + MOVLS rscratch2,#0 + STR rscratch2,[reg_cpu_var,#WaitCounter_ofs] +5431: + +.endm +.macro BranchCheck0 + /*in rsctach : OpAddress + /*destroy rscratch2*/ + LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + MOVS rscratch2,rscratch2 + BEQ 1110f + MOV rscratch2,#0 + STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + SUB rscratch2,rpc,regpcbase + @ if( CPU.PC - CPU.PCBase > OpAddress) return; + CMP rscratch2,rscratch + BHI 1111f +1110: +.endm +.macro BranchCheck1 + /*in rsctach : OpAddress + /*destroy rscratch2*/ + LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + MOVS rscratch2,rscratch2 + BEQ 1110f + MOV rscratch2,#0 + STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + SUB rscratch2,rpc,regpcbase + @ if( CPU.PC - CPU.PCBase > OpAddress) return; + CMP rscratch2,rscratch + BHI 1111f +1110: +.endm +.macro BranchCheck2 + /*in rsctach : OpAddress + /*destroy rscratch2*/ + LDRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + MOVS rscratch2,rscratch2 + BEQ 1110f + MOV rscratch2,#0 + STRB rscratch2,[reg_cpu_var,#BranchSkip_ofs] + SUB rscratch2,rpc,regpcbase + @ if( CPU.PC - CPU.PCBase > OpAddress) return; + CMP rscratch2,rscratch + BHI 1111f +1110: +.endm + +.macro S9xSetPCBase + @ in : rscratch (0x00hhmmll) + @PREPARE_C_CALL + @BL asm_S9xSetPCBase + @RESTORE_C_CALL + @LDR rpc,[reg_cpu_var,#PC_ofs] + @LDR regpcbase,[reg_cpu_var,#PCBase_ofs] + mov r3, pc @ r3 = return address + b asmS9xSetPCBase + @ return address +.endm + +.macro S9xFixCycles + TST rstatus,#MASK_EMUL + LDRNE rscratch, = jumptable1 @ Mode 0 : M=1,X=1 + BNE 991111f + @ EMULATION=0 + TST rstatus,#MASK_MEM + BEQ 991112f + @ MEMORY=1 + TST rstatus,#MASK_INDEX + @ INDEX=1 @ Mode 0 : M=1,X=1 + LDRNE rscratch, = jumptable1 + @ INDEX=0 @ Mode 1 : M=1,X=0 + LDREQ rscratch, = jumptable2 + B 991111f +991112: @ MEMORY=0 + TST rstatus,#MASK_INDEX + @ INDEX=1 @ Mode 3 : M=0,X=1 + LDRNE rscratch, = jumptable4 + @ INDEX=0 @ Mode 2 : M=0,X=0 + LDREQ rscratch, = jumptable3 +991111: + STR rscratch,[reg_cpu_var,#asm_OPTABLE_ofs] +.endm +/* +.macro S9xOpcode_NMI + SAVE_REGS + PREPARE_C_CALL_LIGHT + BL asm_S9xOpcode_NMI + RESTORE_C_CALL_LIGHT + LOAD_REGS +.endm +.macro S9xOpcode_IRQ + SAVE_REGS + PREPARE_C_CALL_LIGHT + BL asm_S9xOpcode_IRQ + RESTORE_C_CALL_LIGHT + LOAD_REGS +.endm +*/ +@--> +.macro S9xDoHBlankProcessing + SAVE_REGS + PREPARE_C_CALL_LIGHT +@ BL asm_S9xDoHBlankProcessing + BL S9xDoHBlankProcessing @ let's go straight to number one + RESTORE_C_CALL_LIGHT + LOAD_REGS +.endm + +/********************************/ +.macro EXEC_OP + @STR rpc,[reg_cpu_var,#PCAtOpcodeStart_ofs] + ADD1MEM + LDRB R0, [rpc], #1 + LDR R1,[reg_cpu_var,#asm_OPTABLE_ofs] + + LDR PC, [R1,R0, LSL #2] +.endm +.macro NEXTOPCODE cycles + add reg_cycles, reg_cycles, #(\cycles) + LDR rscratch,[reg_cpu_var,#NextEvent_ofs] + CMP reg_cycles,rscratch + BLT mainLoop + B mainLoop1 + @S9xDoHBlankProcessing + @B mainLoop +.endm + +.macro asmAPU_EXECUTE + LDRB R0,[reg_cpu_var,#APUExecuting_ofs] + CMP R0,#1 @ spc700 enabled, hack mode off + BNE 43210f + LDR R0,[reg_cpu_var,#APU_Cycles] + SUBS R0,reg_cycles,R0 + BMI 43210f +.if ASM_SPC700 + PREPARE_C_CALL_LIGHTR12 + BL spc700_execute + RESTORE_C_CALL_LIGHTR12 + SUB R0,reg_cycles,R0 @ sub cycles left + STR R0,[reg_cpu_var,#APU_Cycles] +.else + @ SAVE_REGS + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] + PREPARE_C_CALL_LIGHTR12 + BL asm_APU_EXECUTE + RESTORE_C_CALL_LIGHTR12 + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] +.endif + @ LOAD_REGS + @ S9xFixCycles +43210: +.endm + +.macro asmAPU_EXECUTE2 +.if ASM_SPC700 + LDRB R0,[reg_cpu_var,#APUExecuting_ofs] + CMP R0,#1 @ spc700 enabled, hack mode off + BNE 43211f + LDR R0,[reg_cpu_var,#APU_Cycles] + SUBS R0,reg_cycles,R0 @ reg_cycles == NextEvent + BLE 43211f + PREPARE_C_CALL_LIGHTR12 + BL spc700_execute + RESTORE_C_CALL_LIGHTR12 + SUB R0,reg_cycles,R0 @ sub cycles left + STR R0,[reg_cpu_var,#APU_Cycles] +43211: +.else + @ SAVE_REGS + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] + PREPARE_C_CALL_LIGHTR12 + BL asm_APU_EXECUTE2 + RESTORE_C_CALL_LIGHTR12 + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] + @ LOAD_REGS +.endif +.endm + +@ #include "os9x_65c816_mac_mem.h" +.macro S9xGetWord + @ in : rscratch (0x00hhmmll) + @ out : rscratch (0xhhll0000) + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 + MOV R0, R0, LSL #16 +.endm +.macro S9xGetWordLow + @ in : rscratch (0x00hhmmll) + @ out : rscratch (0x0000hhll) + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 +.endm +.macro S9xGetWordRegStatus reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xhhll0000) + @ flags have to be updated with read value + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 + MOVS \reg, R0, LSL #16 +.endm +.macro S9xGetWordRegNS reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xhhll0000) + @ DOES NOT DESTROY rscratch (R0) + STMFD R13!,{R0} + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 + MOV \reg, R0, LSL #16 + LDMFD R13!,{R0} +.endm +.macro S9xGetWordLowRegNS reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xhhll0000) + @ DOES NOT DESTROY rscratch (R0) + STMFD R13!,{R0} + STMFD R13!,{PC} @ Push return address + B asmS9xGetWord + MOV R0,R0 + MOV \reg, R0 + LDMFD R13!,{R0} +.endm + +.macro S9xGetByte + @ in : rscratch (0x00hhmmll) + @ out : rscratch (0xll000000) + @STMFD R13!,{PC} @ Push return address + mov r3, pc + B asmS9xGetByte + @MOV R0,R0 + MOV R0, R0, LSL #24 +.endm +.macro S9xGetByteLow + @ in : rscratch (0x00hhmmll) + @ out : rscratch (0x000000ll) + @STMFD R13!,{PC} @ Push return address + mov r3, pc + B asmS9xGetByte + @MOV R0,R0 +.endm +.macro S9xGetByteRegStatus reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xll000000) + @ flags have to be updated with read value + @STMFD R13!,{PC} @ Push return address + mov r3, pc + B asmS9xGetByte + @MOV R0,R0 + MOVS \reg, R0, LSL #24 +.endm +.macro S9xGetByteRegNS reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0xll000000) + @ DOES NOT DESTROY rscratch (R0) + STMFD R13!,{R0} + @STMFD R13!,{PC} @ Push return address + mov r3, pc + B asmS9xGetByte + @MOV R0,R0 + MOVS \reg, R0, LSL #24 + LDMFD R13!,{R0} +.endm +.macro S9xGetByteLowRegNS reg + @ in : rscratch (0x00hhmmll) + @ out : reg (0x000000ll) + @ DOES NOT DESTROY rscratch (R0) + STMFD R13!,{R0} + @STMFD R13!,{PC} @ Push return address + mov r3, pc + B asmS9xGetByte + @MOV R0,R0 + MOVS \reg, R0 + LDMFD R13!,{R0} +.endm + +.macro S9xSetWord regValue + @ in : regValue (0xhhll0000) + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,\regValue, LSR #16 + B asmS9xSetWord + MOV R0,R0 +.endm +.macro S9xSetWordZero + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,#0 + B asmS9xSetWord + MOV R0,R0 +.endm +.macro S9xSetWordLow regValue + @ in : regValue (0x0000hhll) + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,\regValue + B asmS9xSetWord + MOV R0,R0 +.endm +.macro S9xSetByte regValue + @ in : regValue (0xll000000) + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,\regValue, LSR #24 + B asmS9xSetByte + MOV R0,R0 +.endm +.macro S9xSetByteZero + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,#0 + B asmS9xSetByte + MOV R0,R0 +.endm +.macro S9xSetByteLow regValue + @ in : regValue (0x000000ll) + @ in : rscratch=address (0x00hhmmll) + STMFD R13!,{PC} @ Push return address + MOV R1,\regValue + B asmS9xSetByte + MOV R0,R0 +.endm + + +@ =========================================== +@ =========================================== +@ Adressing mode +@ =========================================== +@ =========================================== + + +.macro Absolute + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc],#2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 +.endm +.macro AbsoluteIndexedIndirectX0 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ADD rscratch , reg_x, rscratch, LSL #16 + MOV rscratch , rscratch, LSR #16 + ORR rscratch , rscratch, reg_p_bank, LSL #16 + S9xGetWordLow + +.endm +.macro AbsoluteIndexedIndirectX1 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ADD rscratch , rscratch, reg_x, LSR #24 + BIC rscratch , rscratch, #0x00FF0000 + ORR rscratch , rscratch, reg_p_bank, LSL #16 + S9xGetWordLow + +.endm +.macro AbsoluteIndirectLong + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch, #2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 +.endm +.macro AbsoluteIndirect + ADD2MEM + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + S9xGetWordLow + ORR rscratch , rscratch, reg_p_bank, LSL #16 +.endm +.macro AbsoluteIndexedX0 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_x, LSR #16 +.endm +.macro AbsoluteIndexedX1 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_x, LSR #24 +.endm + + +.macro AbsoluteIndexedY0 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_y, LSR #16 +.endm +.macro AbsoluteIndexedY1 + ADD2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_y, LSR #24 +.endm +.macro AbsoluteLong + ADD3MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + LDRB rscratch2 , [rpc], #1 + ORR rscratch , rscratch, rscratch2, LSL #16 +.endm + + +.macro AbsoluteLongIndexedX0 + ADD3MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + LDRB rscratch2 , [rpc], #1 + ORR rscratch , rscratch, rscratch2, LSL #16 + ADD rscratch , rscratch, reg_x, LSR #16 + BIC rscratch, rscratch, #0xFF000000 +.endm +.macro AbsoluteLongIndexedX1 + ADD3MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + LDRB rscratch2 , [rpc], #1 + ORR rscratch , rscratch, rscratch2, LSL #16 + ADD rscratch , rscratch, reg_x, LSR #24 + BIC rscratch, rscratch, #0xFF000000 +.endm +.macro Direct + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndirect + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch , rscratch, reg_d_bank, LSL #16 +.endm +.macro DirectIndirectLong + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch,#2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 +.endm +.macro DirectIndirectIndexed0 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch, rscratch,reg_d_bank, LSL #16 + ADD rscratch, rscratch,reg_y, LSR #16 +.endm +.macro DirectIndirectIndexed1 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch, rscratch,reg_d_bank, LSL #16 + ADD rscratch, rscratch,reg_y, LSR #24 +.endm +.macro DirectIndirectIndexedLong0 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch,#2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 + ADD rscratch, rscratch,reg_y, LSR #16 +.endm +.macro DirectIndirectIndexedLong1 + ADD1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , reg_d, rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLowRegNS rscratch2 + ADD rscratch , rscratch,#2 + STMFD r13!,{rscratch2} + S9xGetByteLow + LDMFD r13!,{rscratch2} + ORR rscratch , rscratch2, rscratch, LSL #16 + ADD rscratch, rscratch,reg_y, LSR #24 +.endm +.macro DirectIndexedIndirect0 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_x + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch , rscratch , reg_d_bank, LSL #16 +.endm +.macro DirectIndexedIndirect1 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_x, LSR #8 + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 + S9xGetWordLow + ORR rscratch , rscratch , reg_d_bank, LSL #16 +.endm +.macro DirectIndexedX0 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_x + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndexedX1 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_x, LSR #8 + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndexedY0 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_y + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro DirectIndexedY1 + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch2 , reg_d , reg_y, LSR #8 + ADD rscratch , rscratch2 , rscratch, LSL #16 + MOV rscratch, rscratch, LSR #16 +.endm +.macro Immediate8 + ADD rscratch, rpc, reg_p_bank, LSL #16 + SUB rscratch, rscratch, regpcbase + ADD rpc, rpc, #1 +.endm +.macro Immediate16 + ADD rscratch, rpc, reg_p_bank, LSL #16 + SUB rscratch, rscratch, regpcbase + ADD rpc, rpc, #2 +.endm +.macro asmRelative + ADD1MEM + LDRSB rscratch , [rpc],#1 + ADD rscratch , rscratch , rpc + SUB rscratch , rscratch, regpcbase + BIC rscratch,rscratch,#0x00FF0000 + BIC rscratch,rscratch,#0xFF000000 +.endm +.macro asmRelativeLong + ADD1CYCLE2MEM + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch , rscratch, rscratch2, LSL #8 + SUB rscratch2 , rpc, regpcbase + ADD rscratch , rscratch2, rscratch + BIC rscratch,rscratch,#0x00FF0000 +.endm + + +.macro StackasmRelative + ADD1CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , rscratch, reg_s + BIC rscratch,rscratch,#0x00FF0000 +.endm +.macro StackasmRelativeIndirectIndexed0 + ADD2CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , rscratch, reg_s + BIC rscratch,rscratch,#0x00FF0000 + S9xGetWordLow + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_y, LSR #16 + BIC rscratch, rscratch, #0xFF000000 +.endm +.macro StackasmRelativeIndirectIndexed1 + ADD2CYCLE1MEM + LDRB rscratch , [rpc], #1 + ADD rscratch , rscratch, reg_s + BIC rscratch,rscratch,#0x00FF0000 + S9xGetWordLow + ORR rscratch , rscratch, reg_d_bank, LSL #16 + ADD rscratch , rscratch, reg_y, LSR #24 + BIC rscratch, rscratch, #0xFF000000 +.endm + + +/****************************************/ +.macro PushB reg + MOV rscratch,reg_s + S9xSetByte \reg + SUB reg_s,reg_s,#1 +.endm +.macro PushBLow reg + MOV rscratch,reg_s + S9xSetByteLow \reg + SUB reg_s,reg_s,#1 +.endm +.macro PushWLow reg + SUB rscratch,reg_s,#1 + S9xSetWordLow \reg + SUB reg_s,reg_s,#2 +.endm +.macro PushWrLow + MOV rscratch2,rscratch + SUB rscratch,reg_s,#1 + S9xSetWordLow rscratch2 + SUB reg_s,reg_s,#2 +.endm +.macro PushW reg + SUB rscratch,reg_s,#1 + S9xSetWord \reg + SUB reg_s,reg_s,#2 +.endm + +/********/ + +.macro PullB reg + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOV \reg,rscratch,LSL #24 +.endm +.macro PullBr + ADD rscratch,reg_s,#1 + S9xGetByte + ADD reg_s,reg_s,#1 +.endm +.macro PullBLow reg + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOV \reg,rscratch +.endm +.macro PullBrLow + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 +.endm +.macro PullW reg + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOV \reg,rscratch,LSL #16 +.endm + +.macro PullWLow reg + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOV \reg,rscratch +.endm + + +/*****************/ +.macro PullBS reg + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOVS \reg,rscratch,LSL #24 +.endm +.macro PullBrS + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOVS rscratch,rscratch,LSL #24 +.endm +.macro PullBLowS reg + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOVS \reg,rscratch +.endm +.macro PullBrLowS + ADD rscratch,reg_s,#1 + S9xGetByteLow + ADD reg_s,reg_s,#1 + MOVS rscratch,rscratch +.endm +.macro PullWS reg + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOVS \reg,rscratch, LSL #16 +.endm +.macro PullWrS + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOVS rscratch,rscratch, LSL #16 +.endm +.macro PullWLowS reg + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOVS \reg,rscratch +.endm +.macro PullWrLowS + ADD rscratch,reg_s,#1 + S9xGetWordLow + ADD reg_s,reg_s,#2 + MOVS rscratch,rscratch +.endm + + +.globl asmS9xGetByte +.globl asmS9xGetWord +.globl asmS9xSetByte +.globl asmS9xSetWord +.globl asmS9xSetPCBase + +@ input: r0 : address +@ return: rpc, regpcbase +@ uint8 asmS9xSetPCBase(uint32 address); +asmS9xSetPCBase: + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + mov r1, r0, lsr #MEMMAP_SHIFT + + + @ R2 <= Map[block] (GetAddress) + ldr r2, [reg_cpu_var, #Map_ofs] + bic r1, r1, #0xFF000 + + ldr regpcbase, [r2, r1, lsl #2] + bic r0, r0, #0xff0000 @ Address & 0xffff + + cmp regpcbase, #MAP_LAST + @blo SPCBSpecial @ special + + addhs rpc, regpcbase, r0 + @str rpc, [reg_cpu_var, #PC_ofs] + @str regpcbase, [reg_cpu_var, #PCBase_ofs] + + bxhs r3 + + +SPCBSpecial: + + ldr pc, [pc, regpcbase, lsl #2] + mov r0, r0 @ nop, for align + .long SPCB_PPU + .long SPCB_CPU + .long SPCB_DSP + .long SPCB_LOROM_SRAM + .long SPCB_HIROM_SRAM + .long SPCB_LOROM_SRAM + .long SPCB_LOROM_SRAM + .long SPCB_C4 + .long SPCB_BWRAM + .long SPCB_LOROM_SRAM + .long SPCB_LOROM_SRAM + .long SPCB_LOROM_SRAM +/* + MAP_PPU 0 + MAP_CPU 1 + MAP_DSP 2 + MAP_LOROM_SRAM 3 + MAP_HIROM_SRAM 4 + MAP_NONE 5 + MAP_DEBUG 6 + MAP_C4 7 + MAP_BWRAM 8 + MAP_BWRAM_BITMAP 9 + MAP_BWRAM_BITMAP2 10 + MAP_SA1RAM 11 + MAP_LAST 12 +*/ + +vMemory: + .word Memory + +SPCB_PPU: + @CPU.PCBase = Memory.FillRAM - 0x2000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_fillram] + + sub regpcbase, regpcbase, #0x2000 + add rpc, regpcbase, r0 + + @str rpc, [reg_cpu_var, #PC_ofs] + @str regpcbase, [reg_cpu_var, #PCBase_ofs] + + @return; + bx r3 + @------------------- + +SPCB_CPU: + @CPU.PCBase = Memory.FillRAM - 0x4000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_fillram] + + sub regpcbase, regpcbase, #0x4000 + add rpc, regpcbase, r0 + + @str rpc, [reg_cpu_var, #PC_ofs] + @str regpcbase, [reg_cpu_var, #PCBase_ofs] + + @return; + bx r3 + @------------------- + +SPCB_DSP: + @CPU.PCBase = Memory.FillRAM - 0x6000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_fillram] + + sub regpcbase, regpcbase, #0x6000 + add rpc, regpcbase, r0 + + @str rpc, [reg_cpu_var, #PC_ofs] + @str regpcbase, [reg_cpu_var, #PCBase_ofs] + + @return; + bx r3 + @------------------- + +SPCB_LOROM_SRAM: + @CPU.PCBase = Memory.SRAM; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_sram] + + add rpc, regpcbase, r0 + + @str rpc, [reg_cpu_var, #PC_ofs] + @str regpcbase, [reg_cpu_var, #PCBase_ofs] + + @return; + bx r3 + @------------------- + +SPCB_HIROM_SRAM: + @CPU.PCBase = Memory.SRAM - 0x6000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr regpcbase, [r1, #_sram] + + sub regpcbase, regpcbase, #0x6000 + add rpc, regpcbase, r0 + + @str rpc, [reg_cpu_var, #PC_ofs] + @str regpcbase, [reg_cpu_var, #PCBase_ofs] + + @return; + bx r3 + @------------------- + +SPCB_C4: + @CPU.PCBase = Memory.C4RAM - 0x6000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + ldr r1, vMemory + ldr regpcbase, [r1, #_c4ram] + + sub regpcbase, regpcbase, #0x6000 + add rpc, regpcbase, r0 + + @str rpc, [reg_cpu_var, #PC_ofs] + @str regpcbase, [reg_cpu_var, #PCBase_ofs] + + @return; + bx r3 + @------------------- + +SPCB_BWRAM: + @CPU.PCBase = Memory.BWRAM - 0x6000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + ldr r1, vMemory + ldr regpcbase, [r1, #_bwram] + + sub regpcbase, regpcbase, #0x6000 + add rpc, regpcbase, r0 + + @str rpc, [reg_cpu_var, #PC_ofs] + @str regpcbase, [reg_cpu_var, #PCBase_ofs] + + @return; + bx r3 + @------------------- + +@ uint8 asmS9xGetByte(uint32 address); +asmS9xGetByte: + @ in : R0 = 0x00hhmmll + @ out : R0 = 0x000000ll + @ DESTROYED : R1,R2,R3 + @ UPDATE : reg_cycles + @ R1 <= block + MOV R1,R0,LSR #MEMMAP_SHIFT + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + BIC R1,R1,#0xFF000 + @ R2 <= Map[block] (GetAddress) + LDR R2,[reg_cpu_var,#Map_ofs] + LDR R2,[R2,R1,LSL #2] + CMP R2,#MAP_LAST + @BLO GBSpecial @ special + @ Direct ROM/RAM acess + @ R2 <= GetAddress + Address & 0xFFFF + @ R3 <= MemorySpeed[block] + @LDR R3,[reg_cpu_var,#MemorySpeed_ofs] + @MOV R0,R0,LSL #16 + @LDRB R3,[R3,R1] + @ADD R2,R2,R0,LSR #16 + @ Update CPU.Cycles + @ADD reg_cycles,reg_cycles,R3 + @ R3 = BlockIsRAM[block] + @LDR R3,[reg_cpu_var,#BlockIsRAM_ofs] + @ Get value to return + @LDRB R3,[R3,R1] + @LDRB R0,[R2] + @MOVS R3,R3 + @ if BlockIsRAM => update for CPUShutdown + @LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs] + @STRNE R1,[reg_cpu_var,#WaitAddress_ofs] + + bichs r0, #0xff0000 + ldrhsb r0, [r0, r2] + + bxhs r3 + @LDMFD R13!,{PC} @ Return +GBSpecial: + + stmfd r13!, {r3} @return address + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 @ nop, for align + .long GBPPU + .long GBCPU + @.long GBNONE + .long GBDSP + @.long GBNONE + .long GBLSRAM + .long GBHSRAM + @.long GBNONE + .long GBNONE + @.long GBDEBUG + .long GBNONE + @.long GBC4 + .long GBNONE + .long GBBWRAM + .long GBNONE @BWRAM_BITMAP + .long GBNONE @BWRAM_BITMAP2 + .long GBNONE @SA1_RAM + /*.long GB7ROM + .long GB7RAM + .long GB7SRM*/ +GBPPU: + @ InDMA ? + @LDRB R1,[reg_cpu_var,#InDMA_ofs] + @MOVS R1,R1 + @ADDEQ reg_cycles,reg_cycles,#ONE_CYCLE @ No -> update Cycles + @MOV R0,R0,LSL #16 @ S9xGetPPU(Address&0xFFFF); + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + BIC R0, #0Xff0000 + @MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetPPU + RESTORE_C_CALL + @LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GBCPU: + @ADD reg_cycles,reg_cycles,#ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF); + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + BIC R0, #0Xff0000 + @MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetCPU + + RESTORE_C_CALL + @LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GBDSP: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF); + @STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + BIC R0, #0Xff0000 + @MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetDSP + RESTORE_C_CALL + @LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GBLSRAM: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + LDR R2,[reg_cpu_var,#SRAMMask] + LDR R1,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + LDRB R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} +GB7SRM: +GBHSRAM: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + + MOV R1,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R1,R1,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R0,R2,R1 + LDRH R2,[reg_cpu_var,#SRAMMask] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDR R1,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + LDRB R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} @ return +GB7ROM: +GB7RAM: +GBNONE: + @MOV R0,R0,LSR #8 + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @AND R0,R0,#0xFF + EOR R0, R0 + LDMFD R13!,{PC} +@ GBDEBUG: + /*ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + MOV R0,#0 + LDMFD R13!,{PC}*/ +GBC4: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + MOV R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF); + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL + BL S9xGetC4 + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GBDEBUG: +GBBWRAM: + MOV R0,R0,LSL #17 + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + MOV R0,R0,LSR #17 @ Address&0x7FFF + LDR R1,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + LDRB R0,[R0,R1] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + LDMFD R13!,{PC} + +@ uint16 aaS9xGetWord(uint32 address); +asmS9xGetWord: + @ in : R0 = 0x00hhmmll + @ out : R0 = 0x000000ll + @ DESTROYED : R1,R2,R3 + @ UPDATE : reg_cycles + + + MOV R1,R0,LSL #19 + ADDS R1,R1,#0x80000 + @ if = 0x1FFF => 0 + BNE GW_NotBoundary + + STMFD R13!,{R0} + @STMFD R13!,{PC} @ Push return address + mov r3, pc + B asmS9xGetByte + @MOV R0,R0 + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + @STMFD R13!,{PC} @ Push return address + mov r3, pc + B asmS9xGetByte + @MOV R0,R0 + LDMFD R13!,{R1} + ORR R0,R1,R0,LSL #8 + LDMFD R13!,{PC} + +GW_NotBoundary: + + @ R1 <= block + MOV R1,R0,LSR #MEMMAP_SHIFT + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + BIC R1,R1,#0xFF000 + @ R2 <= Map[block] (GetAddress) + LDR R2,[reg_cpu_var,#Map_ofs] + LDR R2,[R2,R1,LSL #2] + CMP R2,#MAP_LAST + BLO GWSpecial @ special + @ Direct ROM/RAM acess + + TST R0,#1 + BNE GW_Not_Aligned1 + @ R2 <= GetAddress + Address & 0xFFFF + @ R3 <= MemorySpeed[block] + @LDR R3,[reg_cpu_var,#MemorySpeed_ofs] + @MOV R0,R0,LSL #16 + @LDRB R3,[R3,R1] + @MOV R0,R0,LSR #16 + bic r0, r0, #0xff0000 + @ Update CPU.Cycles + @ADD reg_cycles,reg_cycles,R3, LSL #1 + @ R3 = BlockIsRAM[block] + @LDR R3,[reg_cpu_var,#BlockIsRAM_ofs] + @ Get value to return + LDRH R0,[R2,R0] + @LDRB R3,[R3,R1] + @MOVS R3,R3 + @ if BlockIsRAM => update for CPUShutdown + @LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs] + @STRNE R1,[reg_cpu_var,#WaitAddress_ofs] + + LDMFD R13!,{PC} @ Return +GW_Not_Aligned1: + + MOV R0,R0,LSL #16 + ADD R3,R0,#0x10000 + LDRB R3,[R2,R3,LSR #16] @ GetAddress+ (Address+1)&0xFFFF + LDRB R0,[R2,R0,LSR #16] @ GetAddress+ Address&0xFFFF + ORR R0,R0,R3,LSL #8 + + @ if BlockIsRAM => update for CPUShutdown + @LDR R3,[reg_cpu_var,#BlockIsRAM_ofs] + @LDR R2,[reg_cpu_var,#MemorySpeed_ofs] + @LDRB R3,[R3,R1] @ R3 = BlockIsRAM[block] + @LDRB R2,[R2,R1] @ R2 <= MemorySpeed[block] + @MOVS R3,R3 @ IsRAM ? CPUShutdown stuff + @LDRNE R1,[reg_cpu_var,#PCAtOpcodeStart_ofs] + @STRNE R1,[reg_cpu_var,#WaitAddress_ofs] + @ADD reg_cycles,reg_cycles,R2, LSL #1 @ Update CPU.Cycles + LDMFD R13!,{PC} @ Return +GWSpecial: + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 @ nop, for align + .long GWPPU + .long GWCPU + .long GWDSP + .long GWLSRAM + .long GWHSRAM + .long GWNONE + .long GWDEBUG + .long GWC4 + .long GWBWRAM + .long GWNONE + .long GWNONE + .long GWNONE + /*.long GW7ROM + .long GW7RAM + .long GW7SRM*/ +/* MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM, + MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP, + MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/ + +GWPPU: + @ InDMA ? + @LDRB R1,[reg_cpu_var,#InDMA_ofs] + @MOVS R1,R1 + @ADDEQ reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ No -> update Cycles + @MOV R0,R0,LSL #16 @ S9xGetPPU(Address&0xFFFF); + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + + @MOV R0,R0,LSR #16 + bic r0, r0, #0xff0000 + PREPARE_C_CALL_R0 + BL S9xGetPPU + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + @ BIC R0,R0,#0x10000 + BL S9xGetPPU + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + @LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GWCPU: + @ADD reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF); + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + bic r0, r0, #0xff0000 + + PREPARE_C_CALL_R0 + BL S9xGetCPU + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + @ BIC R0,R0,#0x10000 + BL S9xGetCPU + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + @LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GWDSP: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + @MOV R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF); + @STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + bic r0, r0, #0xff0000 + + PREPARE_C_CALL_R0 + BL S9xGetDSP + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + @ BIC R0,R0,#0x10000 + BL S9xGetDSP + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + @LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GWLSRAM: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + + TST R0,#1 + BNE GW_Not_Aligned2 + LDRH R2,[reg_cpu_var,#SRAMMask] + LDR R1,[reg_cpu_var,#SRAM] + AND R3,R2,R0 @ Address&SRAMMask + LDRH R0,[R3,R1] @ *Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} @ return +GW_Not_Aligned2: + LDRH R2,[reg_cpu_var,#SRAMMask] + LDR R1,[reg_cpu_var,#SRAM] + AND R3,R2,R0 @ Address&SRAMMask + ADD R0,R0,#1 + AND R2,R0,R2 @ Address&SRAMMask + LDRB R3,[R1,R3] @ *Memory.SRAM + Address&SRAMMask + LDRB R2,[R1,R2] @ *Memory.SRAM + Address&SRAMMask + ORR R0,R3,R2,LSL #8 + LDMFD R13!,{PC} @ return +GW7SRM: +GWHSRAM: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + + TST R0,#1 + BNE GW_Not_Aligned3 + + MOV R1,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R1,R1,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R0,R2,R1 + LDRH R2,[reg_cpu_var,#SRAMMask] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDR R1,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + LDRH R0,[R1,R0] @ *Memory.SRAM + Address&SRAMMask + LDMFD R13!,{PC} @ return + +GW_Not_Aligned3: + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R2,R2,R3 + ADD R0,R0,#1 + SUB R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + MOV R3,R0,LSL #17 + AND R0,R0,#0xF0000 + MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF + MOV R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3) + ADD R0,R0,R3 + LDRH R3,[reg_cpu_var,#SRAMMask] @ reload mask + SUB R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3)) + AND R2,R3,R2 @ Address...&SRAMMask + AND R0,R3,R0 @ (Address+1...)&SRAMMask + + LDR R3,[reg_cpu_var,#SRAM] + LDRB R0,[R0,R3] @ *Memory.SRAM + (Address...)&SRAMMask + LDRB R2,[R2,R3] @ *Memory.SRAM + (Address+1...)&SRAMMask + ORR R0,R2,R0,LSL #8 + + LDMFD R13!,{PC} @ return +GW7ROM: +GW7RAM: +GWNONE: + MOV R0,R0,LSL #16 + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + MOV R0,R0,LSR #24 + ORR R0,R0,R0,LSL #8 + LDMFD R13!,{PC} +GWDEBUG: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + MOV R0,#0 + LDMFD R13!,{PC} +GWC4: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + MOV R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF); + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + MOV R0,R0,LSR #16 + PREPARE_C_CALL_R0 + BL S9xGetC4 + LDMFD R13!,{R1} + STMFD R13!,{R0} + ADD R0,R1,#1 + @ BIC R0,R0,#0x10000 + BL S9xGetC4 + RESTORE_C_CALL_R1 + ORR R0,R1,R0,LSL #8 + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +GWBWRAM: + TST R0,#1 + BNE GW_Not_Aligned4 + MOV R0,R0,LSL #17 + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + MOV R0,R0,LSR #17 @ Address&0x7FFF + LDR R1,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + LDRH R0,[R1,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + LDMFD R13!,{PC} @ return +GW_Not_Aligned4: + MOV R0,R0,LSL #17 + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + ADD R3,R0,#0x20000 + MOV R0,R0,LSR #17 @ Address&0x7FFF + MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF + LDR R1,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + SUB R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000) + LDRB R0,[R1,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + LDRB R3,[R1,R3] @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000) + ORR R0,R0,R3,LSL #8 + LDMFD R13!,{PC} @ return + + +@ void aaS9xSetByte(uint32 address,uint8 val); +asmS9xSetByte: + @ in : R0=0x00hhmmll R1=0x000000ll + @ DESTROYED : R0,R1,R2,R3 + @ UPDATE : reg_cycles + @ cpu shutdown + @MOV R2,#0 + @STR R2,[reg_cpu_var,#WaitAddress_ofs] + @ + + @ R3 <= block + MOV R3,R0,LSR #MEMMAP_SHIFT + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + BIC R3,R3,#0xFF000 + @ R2 <= Map[block] (SetAddress) + LDR R2,[reg_cpu_var,#WriteMap_ofs] + LDR R2,[R2,R3,LSL #2] + CMP R2,#MAP_LAST + @BLO SBSpecial @ special + @ Direct ROM/RAM acess + + @ R2 <= SetAddress + Address & 0xFFFF + @MOV R0,R0,LSL #16 + @ADD R2,R2,R0,LSR #16 + @LDR R0,[reg_cpu_var,#MemorySpeed_ofs] + @ Set byte + @STRB R1,[R2] + bichs r0, #0xff0000 + strhsb r1, [r2, r0] + @ R0 <= MemorySpeed[block] + @LDRB R0,[R0,R3] + @ Update CPU.Cycles + @ADD reg_cycles,reg_cycles,R0 + @ CPUShutdown + @ only SA1 here : TODO + @ Return + ldmhsfd r13!, {pc} + @LDMFD R13!,{PC} +SBSpecial: + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 @ nop, for align + .long SBPPU + .long SBCPU + .long SBDSP + .long SBLSRAM + .long SBHSRAM + .long SBNONE + .long SBDEBUG + .long SBC4 + .long SBBWRAM + .long SBNONE + .long SBNONE + .long SBNONE + /*.long SB7ROM + .long SB7RAM + .long SB7SRM*/ +SBPPU: + @ InDMA ? + @LDRB R2,[reg_cpu_var,#InDMA_ofs] + @MOVS R2,R2 + @ADDEQ reg_cycles,reg_cycles,#ONE_CYCLE @ No -> update Cycles + @MOV R0,R0,LSL #16 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + bic r0, r0, #0xff0000 + + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetPPU + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SBCPU: + @ADD reg_cycles,reg_cycles,#ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + bic r0, r0, #0xff0000 + + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetCPU + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SBDSP: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + bic r0, r0, #0xff0000 + + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetDSP + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SBLSRAM: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + LDRH R2,[reg_cpu_var,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} @ return if SRAMMask=0 + LDR R3,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SB7SRM: +SBHSRAM: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R0,R2,R3 + + LDRH R2,[reg_cpu_var,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} @ return if SRAMMask=0 + + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDR R3,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SB7ROM: +SB7RAM: +SBNONE: +SBDEBUG: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + LDMFD R13!,{PC} +SBC4: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + bic r0, r0, #0xff0000 + + PREPARE_C_CALL + MOV R12,R0 + MOV R0,R1 + MOV R1,R12 + BL S9xSetC4 + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SBBWRAM: + MOV R0,R0,LSL #17 + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + MOV R0,R0,LSR #17 @ Address&0x7FFF + LDR R2,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + STRB R1,[R0,R2] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + + LDMFD R13!,{PC} + + +@ void aaS9xSetWord(uint32 address,uint16 val); +asmS9xSetWord: + @ in : R0 = 0x00hhmmll R1=0x0000hhll + @ DESTROYED : R0,R1,R2,R3 + @ UPDATE : reg_cycles + @ R1 <= block + + MOV R2,R0,LSL #19 + ADDS R2,R2,#0x80000 + @ if = 0x1FFF => 0 + BNE SW_NotBoundary + + STMFD R13!,{R0,R1} + STMFD R13!,{PC} + B asmS9xSetByte + MOV R0,R0 + LDMFD R13!,{R0,R1} + ADD R0,R0,#1 + MOV R1,R1,LSR #8 + STMFD R13!,{PC} + B asmS9xSetByte + MOV R0,R0 + + LDMFD R13!,{PC} + +SW_NotBoundary: + + @MOV R2,#0 + @STR R2,[reg_cpu_var,#WaitAddress_ofs] + @ + @ R3 <= block + MOV R3,R0,LSR #MEMMAP_SHIFT + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + BIC R3,R3,#0xFF000 + @ R2 <= Map[block] (SetAddress) + LDR R2,[reg_cpu_var,#WriteMap_ofs] + LDR R2,[R2,R3,LSL #2] + CMP R2,#MAP_LAST + BLO SWSpecial @ special + @ Direct ROM/RAM acess + + + @ check if address is 16bits aligned or not + TST R0,#1 + BNE SW_not_aligned1 + @ aligned + @MOV R0,R0,LSL #16 + @ADD R2,R2,R0,LSR #16 @ address & 0xFFFF + SetAddress + @LDR R0,[reg_cpu_var,#MemorySpeed_ofs] + @ Set word + @STRH R1,[R2] + bic r0, #0xff0000 + strh r1, [r2, r0] + @ R1 <= MemorySpeed[block] + @LDRB R0,[R0,R3] + @ Update CPU.Cycles + @ADD reg_cycles,reg_cycles,R0, LSL #1 + @ CPUShutdown + @ only SA1 here : TODO + @ Return + LDMFD R13!,{PC} + +SW_not_aligned1: + @ R1 = (Address&0xFFFF)<<16 + MOV R0,R0,LSL #16 + @ First write @address + STRB R1,[R2,R0,LSR #16] + ADD R0,R0,#0x10000 + MOV R1,R1,LSR #8 + @ Second write @address+1 + + STRB R1,[R2,R0,LSR #16] + @ R1 <= MemorySpeed[block] + @LDR R0,[reg_cpu_var,#MemorySpeed_ofs] + @LDRB R0,[R0,R3] + @ Update CPU.Cycles + @ADD reg_cycles,reg_cycles,R0,LSL #1 + @ CPUShutdown + @ only SA1 here : TODO + @ Return + LDMFD R13!,{PC} +SWSpecial: + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 @ nop, for align + .long SWPPU + .long SWCPU + .long SWDSP + .long SWLSRAM + .long SWHSRAM + .long SWNONE + .long SWDEBUG + .long SWC4 + .long SWBWRAM + .long SWNONE + .long SWNONE + .long SWNONE + /*.long SW7ROM + .long SW7RAM + .long SW7SRM*/ +SWPPU: + @ InDMA ? + @LDRB R2,[reg_cpu_var,#InDMA_ofs] + @MOVS R2,R2 + @ADDEQ reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ No -> update Cycles + @MOV R0,R0,LSL #16 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 + bic r0, r0, #0xff0000 + + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetPPU + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetPPU + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SWCPU: + @ADD reg_cycles,reg_cycles,#(ONE_CYCLE*2) @ update Cycles + @MOV R0,R0,LSL #16 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + bic r0, r0, #0xff0000 + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetCPU + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetCPU + RESTORE_C_CALL + @LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SWDSP: + @ADD reg_cycles,reg_cycles,#SLOW_ONE_CYCLE @ update Cycles + @MOV R0,R0,LSL #16 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + bic r0, r0, #0xff0000 + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetDSP + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetDSP + RESTORE_C_CALL + @LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SWLSRAM: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + LDRH R2,[reg_cpu_var,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} @ return if SRAMMask=0 + + AND R3,R2,R0 @ Address&SRAMMask + TST R0,#1 + BNE SW_not_aligned2 + @ aligned + LDR R0,[reg_cpu_var,#SRAM] + STRH R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW_not_aligned2: + + ADD R0,R0,#1 + AND R2,R2,R0 @ (Address+1)&SRAMMask + LDR R0,[reg_cpu_var,#SRAM] + STRB R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + MOV R1,R1,LSR #8 + STRB R1,[R0,R2] @ *Memory.SRAM + (Address+1)&SRAMMask + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW7SRM: +SWHSRAM: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + + LDRH R2,[reg_cpu_var,#SRAMMask] + MOVS R2,R2 + LDMEQFD R13!,{PC} @ return if SRAMMask=0 + + TST R0,#1 + BNE SW_not_aligned3 + @ aligned + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R0,R2,R3 + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + LDRH R2,[reg_cpu_var,#SRAMMask] + LDR R3,[reg_cpu_var,#SRAM] + AND R0,R2,R0 @ Address&SRAMMask + STRH R1,[R0,R3] @ *Memory.SRAM + Address&SRAMMask + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW_not_aligned3: + MOV R3,R0,LSL #17 + AND R2,R0,#0xF0000 + MOV R3,R3,LSR #17 @ Address&0x7FFF + MOV R2,R2,LSR #3 @ (Address&0xF0000 >> 3) + ADD R2,R2,R3 + SUB R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3)) + + ADD R0,R0,#1 + MOV R3,R0,LSL #17 + AND R0,R0,#0xF0000 + MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF + MOV R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3) + ADD R0,R0,R3 + LDRH R3,[reg_cpu_var,#SRAMMask] @ reload mask + SUB R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3)) + AND R2,R3,R2 @ Address...&SRAMMask + AND R0,R3,R0 @ (Address+1...)&SRAMMask + + LDR R3,[reg_cpu_var,#SRAM] + STRB R1,[R2,R3] @ *Memory.SRAM + (Address...)&SRAMMask + MOV R1,R1,LSR #8 + STRB R1,[R0,R3] @ *Memory.SRAM + (Address+1...)&SRAMMask + + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW7ROM: +SW7RAM: +SWNONE: +SWDEBUG: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + LDMFD R13!,{PC} @ return +SWC4: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + @MOV R0,R0,LSL #16 + STR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles + @MOV R0,R0,LSR #16 @ Address&0xFFFF + bic r0, r0, #0xff0000 + + MOV R2,R1 + MOV R1,R0 + MOV R0,R2 + PREPARE_C_CALL_R0R1 + BL S9xSetC4 + LDMFD R13!,{R0,R1} + ADD R1,R1,#1 + MOV R0,R0,LSR #8 + BIC R1,R1,#0x10000 + BL S9xSetC4 + RESTORE_C_CALL + LDR reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles + LDMFD R13!,{PC} @ Return +SWBWRAM: + @ADD reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2) @ update Cycles + TST R0,#1 + BNE SW_not_aligned4 + @ aligned + MOV R0,R0,LSL #17 + LDR R2,[reg_cpu_var,#BWRAM] + MOV R0,R0,LSR #17 @ Address&0x7FFF + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + MOV R3,#1 + STRH R1,[R0,R2] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + STRB R3,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return +SW_not_aligned4: + MOV R0,R0,LSL #17 + ADD R3,R0,#0x20000 + MOV R0,R0,LSR #17 @ Address&0x7FFF + MOV R3,R3,LSR #17 @ (Address+1)&0x7FFF + LDR R2,[reg_cpu_var,#BWRAM] + SUB R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000) + SUB R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000) + STRB R1,[R2,R0] @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000) + MOV R1,R1,LSR #8 + STRB R1,[R2,R3] @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000) + MOV R0,#1 + STRB R0,[reg_cpu_var,#SRAMModified_ofs] + LDMFD R13!,{PC} @ return + + + + + +/***************************************************************** + FLAGS +*****************************************************************/ + +.macro UPDATE_C + @ CC : ARM Carry Clear + BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + @ CS : ARM Carry Set + ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one +.endm +.macro UPDATE_Z + @ NE : ARM Zero Clear + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + @ EQ : ARM Zero Set + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one +.endm +.macro UPDATE_ZN + @ NE : ARM Zero Clear + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + @ EQ : ARM Zero Set + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + @ PL : ARM Neg Clear + BICPL rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + @ MI : ARM Neg Set + ORRMI rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set N to one +.endm + +/***************************************************************** + OPCODES_MAC +*****************************************************************/ + + + + +.macro ADC8 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + S9xGetByte + + + STMFD R13!,{rscratch} + MOV rscratch4,#0x0F000000 + @ rscratch2=xxW1xxxxxxxxxxxx + AND rscratch2, rscratch, rscratch4 + @ rscratch=xxW2xxxxxxxxxxxx + AND rscratch, rscratch4, rscratch, LSR #4 + @ rscratch3=xxA2xxxxxxxxxxxx + AND rscratch3, rscratch4, reg_a, LSR #4 + @ rscratch4=xxA1xxxxxxxxxxxx + AND rscratch4,reg_a,rscratch4 + @ R1=A1+W1+CARRY + TST rstatus, #MASK_CARRY + ADDNE rscratch2, rscratch2, #0x01000000 + ADD rscratch2,rscratch2,rscratch4 + @ if R1 > 9 + CMP rscratch2, #0x09000000 + @ then R1 -= 10 + SUBGT rscratch2, rscratch2, #0x0A000000 + @ then A2++ + ADDGT rscratch3, rscratch3, #0x01000000 + @ R2 = A2+W2 + ADD rscratch3, rscratch3, rscratch + @ if R2 > 9 + CMP rscratch3, #0x09000000 + @ then R2 -= 10@ + SUBGT rscratch3, rscratch3, #0x0A000000 + @ then SetCarry() + ORRGT rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + @ else ClearCarry() + BICLE rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + @ gather rscratch3 and rscratch2 into ans8 + @ rscratch3 : 0R2000000 + @ rscratch2 : 0R1000000 + @ -> 0xR2R1000000 + ORR rscratch2, rscratch2, rscratch3, LSL #4 + LDMFD R13!,{rscratch} + @ only last bit + AND rscratch,rscratch,#0x80000000 + @ (register.AL ^ Work8) + EORS rscratch3, reg_a, rscratch + BICNE rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + BNE 1112f + @ (Work8 ^ Ans8) + EORS rscratch3, rscratch2, rscratch + @ & 0x80 + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one +1112: + MOVS reg_a, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetByteLow + MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY + SUBCS rscratch, rscratch, #0x100 + ADCS reg_a, reg_a, rscratch, ROR #8 + @ OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + @ Carry + UPDATE_C + @ clear lower part + ANDS reg_a, reg_a, #0xFF000000 + @ Update flag + UPDATE_ZN +1113: +.endm +/* TO TEST */ +.macro ADC16 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + S9xGetWord + + @ rscratch = W3W2W1W0........ + LDR rscratch4, = 0x0F0F0000 + @ rscratch2 = xxW2xxW0xxxxxx + @ rscratch3 = xxW3xxW1xxxxxx + AND rscratch2, rscratch4, rscratch + AND rscratch3, rscratch4, rscratch, LSR #4 + @ rscratch2 = xxW3xxW1xxW2xxW0 + ORR rscratch2, rscratch3, rscratch2, LSR #16 + @ rscratch3 = xxA2xxA0xxxxxx + @ rscratch4 = xxA3xxA1xxxxxx + @ rscratch2 = xxA3xxA1xxA2xxA0 + AND rscratch3, rscratch4, reg_a + AND rscratch4, rscratch4, reg_a, LSR #4 + ORR rscratch3, rscratch4, rscratch3, LSR #16 + ADD rscratch2, rscratch3, rscratch2 + LDR rscratch4, = 0x0F0F0000 + @ rscratch2 = A + W + TST rstatus, #MASK_CARRY + ADDNE rscratch2, rscratch2, #0x1 + @ rscratch2 = A + W + C + @ A0 + AND rscratch3, rscratch2, #0x0000001F + CMP rscratch3, #0x00000009 + ADDHI rscratch2, rscratch2, #0x00010000 + SUBHI rscratch2, rscratch2, #0x0000000A + @ A1 + AND rscratch3, rscratch2, #0x001F0000 + CMP rscratch3, #0x00090000 + ADDHI rscratch2, rscratch2, #0x00000100 + SUBHI rscratch2, rscratch2, #0x000A0000 + @ A2 + AND rscratch3, rscratch2, #0x00001F00 + CMP rscratch3, #0x00000900 + SUBHI rscratch2, rscratch2, #0x00000A00 + ADDHI rscratch2, rscratch2, #0x01000000 + @ A3 + AND rscratch3, rscratch2, #0x1F000000 + CMP rscratch3, #0x09000000 + SUBHI rscratch2, rscratch2, #0x0A000000 + @ SetCarry + ORRHI rstatus, rstatus, #MASK_CARRY + @ ClearCarry + BICLS rstatus, rstatus, #MASK_CARRY + @ rscratch2 = xxR3xxR1xxR2xxR0 + @ Pack result + @ rscratch3 = xxR3xxR1xxxxxxxx + AND rscratch3, rscratch4, rscratch2 + @ rscratch2 = xxR2xxR0xxxxxxxx + AND rscratch2, rscratch4, rscratch2,LSL #16 + @ rscratch2 = R3R2R1R0xxxxxxxx + ORR rscratch2, rscratch2,rscratch3,LSL #4 +@ only last bit + AND rscratch,rscratch,#0x80000000 + @ (register.AL ^ Work8) + EORS rscratch3, reg_a, rscratch + BICNE rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + BNE 1112f + @ (Work8 ^ Ans8) + EORS rscratch3, rscratch2, rscratch + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one +1112: + MOVS reg_a, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetWordLow + MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY + SUBCS rscratch, rscratch, #0x10000 + ADCS reg_a, reg_a,rscratch, ROR #16 + @ OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + MOV reg_a, reg_a, LSR #16 + @ Carry + UPDATE_C + @ clear lower parts + MOVS reg_a, reg_a, LSL #16 + @ Update flag + UPDATE_ZN +1113: +.endm + + +.macro AND16 + S9xGetWord + ANDS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro AND8 + S9xGetByte + ANDS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro A_ASL8 + @ 7 instr + MOVS reg_a, reg_a, LSL #1 + UPDATE_C + UPDATE_ZN + ADD1CYCLE +.endm +.macro A_ASL16 + @ 7 instr + MOVS reg_a, reg_a, LSL #1 + UPDATE_C + UPDATE_ZN + ADD1CYCLE +.endm +.macro ASL16 + S9xGetWordRegNS rscratch2 @ do not destroy Opadress in rscratch + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_C + UPDATE_ZN + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro ASL8 + S9xGetByteRegNS rscratch2 @ do not destroy Opadress in rscratch + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_C + UPDATE_ZN + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro BIT8 + S9xGetByte + MOVS rscratch2, rscratch, LSL #1 + @ Trick in ASM : shift one more bit : ARM C = Snes N + @ ARM N = Snes V + @ If Carry Set, then Set Neg in SNES + BICCC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set C to zero + ORRCS rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set C to one + @ If Neg Set, then Set Overflow in SNES + BICPL rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set N to zero + ORRMI rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set N to one + + @ Now do a real AND with A register + @ Set Zero Flag, bit test + ANDS rscratch2, reg_a, rscratch + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one +.endm + +.macro BIT16 + S9xGetWord + MOVS rscratch2, rscratch, LSL #1 + @ Trick in ASM : shift one more bit : ARM C = Snes N + @ ARM N = Snes V + @ If Carry Set, then Set Neg in SNES + BICCC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + ORRCS rstatus, rstatus, #MASK_NEG @ 1 : OR mask 00000100000 : set N to one + @ If Neg Set, then Set Overflow in SNES + BICPL rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRMI rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one + @ Now do a real AND with A register + @ Set Zero Flag, bit test + ANDS rscratch2, reg_a, rscratch + @ Bit set ->Z=0->xxxNE Clear flag + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + @ Bit clear->Z=1->xxxEQ Set flag + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one +.endm +.macro CMP8 + S9xGetByte + SUBS rscratch2,reg_a,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + +.endm +.macro CMP16 + S9xGetWord + SUBS rscratch2,reg_a,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + +.endm +.macro CMX16 + S9xGetWord + SUBS rscratch2,reg_x,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro CMX8 + S9xGetByte + SUBS rscratch2,reg_x,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro CMY16 + S9xGetWord + SUBS rscratch2,reg_y,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro CMY8 + S9xGetByte + SUBS rscratch2,reg_y,rscratch + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN +.endm +.macro A_DEC8 + MOV rscratch,#0 + SUBS reg_a, reg_a, #0x01000000 + STR rscratch,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro A_DEC16 + MOV rscratch,#0 + SUBS reg_a, reg_a, #0x00010000 + STR rscratch,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro DEC16 + S9xGetWordRegNS rscratch2 @ do not destroy Opadress in rscratch + MOV rscratch3,#0 + SUBS rscratch2, rscratch2, #0x00010000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro DEC8 + S9xGetByteRegNS rscratch2 @ do not destroy Opadress in rscratch + MOV rscratch3,#0 + SUBS rscratch2, rscratch2, #0x01000000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro EOR16 + S9xGetWord + EORS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro EOR8 + S9xGetByte + EORS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro A_INC8 + MOV rscratch3,#0 + ADDS reg_a, reg_a, #0x01000000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro A_INC16 + MOV rscratch3,#0 + ADDS reg_a, reg_a, #0x00010000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro INC16 + S9xGetWordRegNS rscratch2 + MOV rscratch3,#0 + ADDS rscratch2, rscratch2, #0x00010000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + + UPDATE_ZN + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro INC8 + S9xGetByteRegNS rscratch2 + MOV rscratch3,#0 + ADDS rscratch2, rscratch2, #0x01000000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro LDA16 + S9xGetWordRegStatus reg_a + UPDATE_ZN +.endm +.macro LDA8 + S9xGetByteRegStatus reg_a + UPDATE_ZN +.endm +.macro LDX16 + S9xGetWordRegStatus reg_x + UPDATE_ZN +.endm +.macro LDX8 + S9xGetByteRegStatus reg_x + UPDATE_ZN +.endm +.macro LDY16 + S9xGetWordRegStatus reg_y + UPDATE_ZN +.endm +.macro LDY8 + S9xGetByteRegStatus reg_y + UPDATE_ZN +.endm +.macro A_LSR16 + BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + MOVS reg_a, reg_a, LSR #17 @ hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll + @ Update Zero + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + MOV reg_a, reg_a, LSL #16 @ -> 0lllllll 00000000 00000000 00000000 + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + @ Note : the two MOV are included between instruction, to optimize + @ the pipeline. + UPDATE_C + ADD1CYCLE +.endm +.macro A_LSR8 + BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + MOVS reg_a, reg_a, LSR #25 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll + @ Update Zero + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + MOV reg_a, reg_a, LSL #24 @ -> 00000000 00000000 00000000 0lllllll + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + @ Note : the two MOV are included between instruction, to optimize + @ the pipeline. + UPDATE_C + ADD1CYCLE +.endm +.macro LSR16 + S9xGetWordRegNS rscratch2 + @ N set to zero by >> 1 LSR + BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + MOVS rscratch2, rscratch2, LSR #17 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll + @ Update Carry + BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + @ Update Zero + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + S9xSetWordLow rscratch2 + ADD1CYCLE +.endm +.macro LSR8 + S9xGetByteRegNS rscratch2 + @ N set to zero by >> 1 LSR + BIC rstatus, rstatus, #MASK_NEG @ 0 : AND mask 11111011111 : set N to zero + MOVS rscratch2, rscratch2, LSR #25 @ llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll + @ Update Carry + BICCC rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + ORRCS rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + @ Update Zero + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + S9xSetByteLow rscratch2 + ADD1CYCLE +.endm +.macro ORA8 + S9xGetByte + ORRS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro ORA16 + S9xGetWord + ORRS reg_a, reg_a, rscratch + UPDATE_ZN +.endm +.macro A_ROL16 + TST rstatus, #MASK_CARRY + ORRNE reg_a, reg_a, #0x00008000 + MOVS reg_a, reg_a, LSL #1 + UPDATE_ZN + UPDATE_C + ADD1CYCLE +.endm +.macro A_ROL8 + TST rstatus, #MASK_CARRY + ORRNE reg_a, reg_a, #0x00800000 + MOVS reg_a, reg_a, LSL #1 + UPDATE_ZN + UPDATE_C + ADD1CYCLE +.endm +.macro ROL16 + S9xGetWordRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00008000 + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_ZN + UPDATE_C + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro ROL8 + S9xGetByteRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00800000 + MOVS rscratch2, rscratch2, LSL #1 + UPDATE_ZN + UPDATE_C + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro A_ROR16 + MOV reg_a,reg_a, LSR #16 + TST rstatus, #MASK_CARRY + ORRNE reg_a, reg_a, #0x00010000 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS reg_a,reg_a,LSR #1 + UPDATE_C + UPDATE_Z + MOV reg_a,reg_a, LSL #16 + ADD1CYCLE +.endm +.macro A_ROR8 + MOV reg_a,reg_a, LSR #24 + TST rstatus, #MASK_CARRY + ORRNE reg_a, reg_a, #0x00000100 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS reg_a,reg_a,LSR #1 + UPDATE_C + UPDATE_Z + MOV reg_a,reg_a, LSL #24 + ADD1CYCLE +.endm +.macro ROR16 + S9xGetWordLowRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00010000 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS rscratch2,rscratch2,LSR #1 + UPDATE_C + UPDATE_Z + S9xSetWordLow rscratch2 + ADD1CYCLE + +.endm +.macro ROR8 + S9xGetByteLowRegNS rscratch2 + TST rstatus, #MASK_CARRY + ORRNE rscratch2, rscratch2, #0x00000100 + ORRNE rstatus,rstatus,#MASK_NEG + BICEQ rstatus,rstatus,#MASK_NEG + MOVS rscratch2,rscratch2,LSR #1 + UPDATE_C + UPDATE_Z + S9xSetByteLow rscratch2 + ADD1CYCLE +.endm + +.macro SBC16 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + @ TODO + S9xGetWord + + STMFD R13!,{rscratch9} + MOV rscratch9,#0x000F0000 + @ rscratch2 - result + @ rscratch3 - scratch + @ rscratch4 - scratch + @ rscratch9 - pattern + + AND rscratch2, rscratch, #0x000F0000 + TST rstatus, #MASK_CARRY + ADDEQ rscratch2, rscratch2, #0x00010000 @ W1=W1+!Carry + AND rscratch4, reg_a, #0x000F0000 + SUB rscratch2, rscratch4,rscratch2 @ R1=A1-W1-!Carry + CMP rscratch2, #0x00090000 @ if R1 > 9 + ADDHI rscratch2, rscratch2, #0x000A0000 @ then R1 += 10 + AND rscratch2, rscratch2, #0x000F0000 + + AND rscratch3, rscratch9, rscratch, LSR #4 + ADDHI rscratch3, rscratch3, #0x00010000 @ then (W2++) + + AND rscratch4, rscratch9, reg_a, LSR #4 + SUB rscratch3, rscratch4, rscratch3 @ R2=A2-W2 + CMP rscratch3, #0x00090000 @ if R2 > 9 + ADDHI rscratch3, rscratch3, #0x000A0000 @ then R2 += 10 + AND rscratch3, rscratch3, #0x000F0000 + ORR rscratch2, rscratch2, rscratch3,LSL #4 + + AND rscratch3, rscratch9, rscratch, LSR #8 + ADDHI rscratch3, rscratch3, #0x00010000 @ then (W3++) + + AND rscratch4, rscratch9, reg_a, LSR #8 + SUB rscratch3, rscratch4, rscratch3 @ R3=A3-W3 + CMP rscratch3, #0x00090000 @ if R3 > 9 + ADDHI rscratch3, rscratch3, #0x000A0000 @ then R3 += 10 + AND rscratch3, rscratch3, #0x000F0000 + ORR rscratch2, rscratch2, rscratch3,LSL #8 + + AND rscratch3, rscratch9, rscratch, LSR #12 + ADDHI rscratch3, rscratch3, #0x00010000 @ then (W3++) + + AND rscratch4, rscratch9, reg_a, LSR #12 + SUB rscratch3, rscratch4, rscratch3 @ R4=A4-W4 + CMP rscratch3, #0x00090000 @ if R4 > 9 + ADDHI rscratch3, rscratch3, #0x000A0000 @ then R4 += 10 + BICHI rstatus, rstatus, #MASK_CARRY @ then ClearCarry + ORRLS rstatus, rstatus, #MASK_CARRY @ else SetCarry + + AND rscratch3,rscratch3,#0x000F0000 + ORR rscratch2,rscratch2,rscratch3,LSL #12 + + LDMFD R13!,{rscratch9} + @ only last bit + AND reg_a,reg_a,#0x80000000 + @ (register.A.W ^ Work8) + EORS rscratch3, reg_a, rscratch + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + BEQ 1112f + @ (register.A.W ^ Ans8) + EORS rscratch3, reg_a, rscratch2 + @ & 0x80 + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one +1112: + MOVS reg_a, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetWordLow + MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY + SBCS reg_a, reg_a, rscratch, LSL #16 + @ OverFlow + + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + MOV reg_a, reg_a, LSR #16 + @ Carry + UPDATE_C + MOVS reg_a, reg_a, LSL #16 + @ Update flag + UPDATE_ZN +1113: +.endm + +.macro SBC8 + TST rstatus, #MASK_DECIMAL + BEQ 1111f + S9xGetByte + STMFD R13!,{rscratch} + MOV rscratch4,#0x0F000000 + @ rscratch2=xxW1xxxxxxxxxxxx + AND rscratch2, rscratch, rscratch4 + @ rscratch=xxW2xxxxxxxxxxxx + AND rscratch, rscratch4, rscratch, LSR #4 + @ rscratch3=xxA2xxxxxxxxxxxx + AND rscratch3, rscratch4, reg_a, LSR #4 + @ rscratch4=xxA1xxxxxxxxxxxx + AND rscratch4,reg_a,rscratch4 + @ R1=A1-W1-!CARRY + TST rstatus, #MASK_CARRY + ADDEQ rscratch2, rscratch2, #0x01000000 + SUB rscratch2,rscratch4,rscratch2 + @ if R1 > 9 + CMP rscratch2, #0x09000000 + @ then R1 += 10 + ADDHI rscratch2, rscratch2, #0x0A000000 + @ then A2-- (W2++) + ADDHI rscratch, rscratch, #0x01000000 + @ R2=A2-W2 + SUB rscratch3, rscratch3, rscratch + @ if R2 > 9 + CMP rscratch3, #0x09000000 + @ then R2 -= 10@ + ADDHI rscratch3, rscratch3, #0x0A000000 + @ then SetCarry() + BICHI rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + @ else ClearCarry() + ORRLS rstatus, rstatus, #MASK_CARRY @ 0 : AND mask 11111011111 : set C to zero + @ gather rscratch3 and rscratch2 into ans8 + AND rscratch3,rscratch3,#0x0F000000 + AND rscratch2,rscratch2,#0x0F000000 + @ rscratch3 : 0R2000000 + @ rscratch2 : 0R1000000 + @ -> 0xR2R1000000 + ORR rscratch2, rscratch2, rscratch3, LSL #4 + LDMFD R13!,{rscratch} + @ only last bit + AND reg_a,reg_a,#0x80000000 + @ (register.AL ^ Work8) + EORS rscratch3, reg_a, rscratch + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + BEQ 1112f + @ (register.AL ^ Ans8) + EORS rscratch3, reg_a, rscratch2 + @ & 0x80 + TSTNE rscratch3,#0x80000000 + BICEQ rstatus, rstatus, #MASK_OVERFLOW @ 0 : AND mask 11111011111 : set V to zero + ORRNE rstatus, rstatus, #MASK_OVERFLOW @ 1 : OR mask 00000100000 : set V to one +1112: + MOVS reg_a, rscratch2 + UPDATE_ZN + B 1113f +1111: + S9xGetByteLow + MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY + SBCS reg_a, reg_a, rscratch, LSL #24 + @ OverFlow + ORRVS rstatus, rstatus, #MASK_OVERFLOW + BICVC rstatus, rstatus, #MASK_OVERFLOW + @ Carry + UPDATE_C + @ Update flag + ANDS reg_a, reg_a, #0xFF000000 + UPDATE_ZN +1113: +.endm + +.macro STA16 + S9xSetWord reg_a +.endm +.macro STA8 + S9xSetByte reg_a +.endm +.macro STX16 + S9xSetWord reg_x +.endm +.macro STX8 + S9xSetByte reg_x +.endm +.macro STY16 + S9xSetWord reg_y +.endm +.macro STY8 + S9xSetByte reg_y +.endm +.macro STZ16 + S9xSetWordZero +.endm +.macro STZ8 + S9xSetByteZero +.endm +.macro TSB16 + S9xGetWordRegNS rscratch2 + TST reg_a, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + ORR rscratch2, reg_a, rscratch2 + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro TSB8 + S9xGetByteRegNS rscratch2 + TST reg_a, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + ORR rscratch2, reg_a, rscratch2 + S9xSetByte rscratch2 + ADD1CYCLE +.endm +.macro TRB16 + S9xGetWordRegNS rscratch2 + TST reg_a, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + MVN rscratch3, reg_a + AND rscratch2, rscratch3, rscratch2 + S9xSetWord rscratch2 + ADD1CYCLE +.endm +.macro TRB8 + S9xGetByteRegNS rscratch2 + TST reg_a, rscratch2 + BICNE rstatus, rstatus, #MASK_ZERO @ 0 : AND mask 11111011111 : set Z to zero + ORREQ rstatus, rstatus, #MASK_ZERO @ 1 : OR mask 00000100000 : set Z to one + MVN rscratch3, reg_a + AND rscratch2, rscratch3, rscratch2 + S9xSetByte rscratch2 + ADD1CYCLE +.endm +/**************************************************************************/ + + +/**************************************************************************/ + +.macro Op09M0 /*ORA*/ + LDRB rscratch2, [rpc,#1] + LDRB rscratch, [rpc], #2 + ORR rscratch2,rscratch,rscratch2,LSL #8 + ORRS reg_a,reg_a,rscratch2,LSL #16 + UPDATE_ZN + ADD2MEM +.endm +.macro Op09M1 /*ORA*/ + LDRB rscratch, [rpc], #1 + ORRS reg_a,reg_a,rscratch,LSL #24 + UPDATE_ZN + ADD1MEM +.endm +/***********************************************************************/ +.macro Op90 /*BCC*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_CARRY + BNE 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro OpB0 /*BCS*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_CARRY + BEQ 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro OpF0 /*BEQ*/ + asmRelative + BranchCheck2 + TST rstatus, #MASK_ZERO + BEQ 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro OpD0 /*BNE*/ + asmRelative + BranchCheck1 + TST rstatus, #MASK_ZERO + BNE 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op30 /*BMI*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_NEG + BEQ 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress +PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op10 /*BPL*/ + asmRelative + BranchCheck1 + TST rstatus, #MASK_NEG @ neg, z!=0, NE + BNE 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op50 /*BVC*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE + BNE 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op70 /*BVS*/ + asmRelative + BranchCheck0 + TST rstatus, #MASK_OVERFLOW @ neg, z!=0, NE + BEQ 1111f + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +.macro Op80 /*BRA*/ + asmRelative + ADD rpc, rscratch, regpcbase @ rpc = OpAddress + PCBase + ADD1CYCLE + CPUShutdown +1111: +.endm +/*******************************************************************************************/ +/************************************************************/ +/* SetFlag Instructions ********************************************************************** */ +.macro Op38 /*SEC*/ + ORR rstatus, rstatus, #MASK_CARRY @ 1 : OR mask 00000100000 : set C to one + ADD1CYCLE +.endm +.macro OpF8 /*SED*/ + SetDecimal + ADD1CYCLE +.endm +.macro Op78 /*SEI*/ + SetIRQ + ADD1CYCLE +.endm + + +/****************************************************************************************/ +/* ClearFlag Instructions ******************************************************************** */ +.macro Op18 /*CLC*/ + BIC rstatus, rstatus, #MASK_CARRY + ADD1CYCLE +.endm +.macro OpD8 /*CLD*/ + ClearDecimal + ADD1CYCLE +.endm +.macro Op58 /*CLI*/ + ClearIRQ + ADD1CYCLE + @ CHECK_FOR_IRQ +.endm +.macro OpB8 /*CLV*/ + BIC rstatus, rstatus, #MASK_OVERFLOW + ADD1CYCLE +.endm + +/******************************************************************************************/ +/* DEX/DEY *********************************************************************************** */ + +.macro OpCAX1 /*DEX*/ + MOV rscratch3,#0 + SUBS reg_x, reg_x, #0x01000000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpCAX0 /*DEX*/ + MOV rscratch3,#0 + SUBS reg_x, reg_x, #0x00010000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op88X1 /*DEY*/ + MOV rscratch3,#0 + SUBS reg_y, reg_y, #0x01000000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op88X0 /*DEY*/ + MOV rscratch3,#0 + SUBS reg_y, reg_y, #0x00010000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm + +/******************************************************************************************/ +/* INX/INY *********************************************************************************** */ +.macro OpE8X1 + MOV rscratch3,#0 + ADDS reg_x, reg_x, #0x01000000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpE8X0 + MOV rscratch3,#0 + ADDS reg_x, reg_x, #0x00010000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpC8X1 + MOV rscratch3,#0 + ADDS reg_y, reg_y, #0x01000000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpC8X0 + MOV rscratch3,#0 + ADDS reg_y, reg_y, #0x00010000 + STR rscratch3,[reg_cpu_var,#WaitAddress_ofs] + UPDATE_ZN + ADD1CYCLE +.endm + +/**********************************************************************************************/ + +/* NOP *************************************************************************************** */ +.macro OpEA + ADD1CYCLE +.endm + +/**************************************************************************/ +/* PUSH Instructions **************************************************** */ +.macro OpF4 + Absolute + PushWrLow +.endm +.macro OpD4 + DirectIndirect + PushWrLow +.endm +.macro Op62 + asmRelativeLong + PushWrLow +.endm +.macro Op48M0 + PushW reg_a + ADD1CYCLE +.endm +.macro Op48M1 + PushB reg_a + ADD1CYCLE +.endm +.macro Op8B + AND rscratch2, reg_d_bank, #0xFF + PushBLow rscratch2 + ADD1CYCLE +.endm +.macro Op0B + PushW reg_d + ADD1CYCLE +.endm +.macro Op4B + PushBlow reg_p_bank + ADD1CYCLE +.endm +.macro Op08 + PushB rstatus + ADD1CYCLE +.endm +.macro OpDAX1 + PushB reg_x + ADD1CYCLE +.endm +.macro OpDAX0 + PushW reg_x + ADD1CYCLE +.endm +.macro Op5AX1 + PushB reg_y + ADD1CYCLE +.endm +.macro Op5AX0 + PushW reg_y + ADD1CYCLE +.endm +/**************************************************************************/ +/* PULL Instructions **************************************************** */ +.macro Op68M1 + PullBS reg_a + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op68M0 + PullWS reg_a + UPDATE_ZN + ADD2CYCLE +.endm +.macro OpAB + BIC reg_d_bank,reg_d_bank, #0xFF + PullBrS + ORR reg_d_bank,reg_d_bank,rscratch, LSR #24 + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op2B + BIC reg_d,reg_d, #0xFF000000 + BIC reg_d,reg_d, #0x00FF0000 + PullWrS + ORR reg_d,rscratch,reg_d + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op28X1M1 /*PLP*/ + @ INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + @ INDEX clear & was set : 8->16 + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus, #MASK_MEM + @ MEMORY cleared & was set : 8->16 + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSR #8 + ORREQ reg_a,reg_a,rscratch, LSL #24 + S9xFixCycles + ADD2CYCLE +.endm +.macro Op28X0M1 /*PLP*/ + @ INDEX cleared, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + @ INDEX set & was cleared : 16->8 + MOVNE reg_x,reg_x,LSL #8 + MOVNE reg_y,reg_y,LSL #8 + TST rstatus, #MASK_MEM + @ MEMORY cleared & was set : 8->16 + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSR #8 + ORREQ reg_a,reg_a,rscratch, LSL #24 + S9xFixCycles + ADD2CYCLE +.endm +.macro Op28X1M0 /*PLP*/ + @ INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + @ INDEX clear & was set : 8->16 + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus, #MASK_MEM + @ MEMORY set & was cleared : 16->8 + MOVNE rscratch,reg_a,LSR #24 + MOVNE reg_a,reg_a,LSL #8 + STRNEB rscratch,[reg_cpu_var,#RAH_ofs] + S9xFixCycles + ADD2CYCLE +.endm +.macro Op28X0M0 /*PLP*/ + @ INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + TST rstatus, #MASK_INDEX + @ INDEX set & was cleared : 16->8 + MOVNE reg_x,reg_x,LSL #8 + MOVNE reg_y,reg_y,LSL #8 + TST rstatus, #MASK_MEM + @ MEMORY set & was cleared : 16->8 + MOVNE rscratch,reg_a,LSR #24 + MOVNE reg_a,reg_a,LSL #8 + STRNEB rscratch,[reg_cpu_var,#RAH_ofs] + S9xFixCycles + ADD2CYCLE +.endm +.macro OpFAX1 + PullBS reg_x + UPDATE_ZN + ADD2CYCLE +.endm +.macro OpFAX0 + PullWS reg_x + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op7AX1 + PullBS reg_y + UPDATE_ZN + ADD2CYCLE +.endm +.macro Op7AX0 + PullWS reg_y + UPDATE_ZN + ADD2CYCLE +.endm + +/**********************************************************************************************/ +/* Transfer Instructions ********************************************************************* */ +.macro OpAAX1M1 /*TAX8*/ + MOVS reg_x, reg_a + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpAAX0M1 /*TAX16*/ + LDRB reg_x, [reg_cpu_var,#RAH_ofs] + MOV reg_x, reg_x,LSL #24 + ORRS reg_x, reg_x,reg_a, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpAAX1M0 /*TAX8*/ + MOVS reg_x, reg_a, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpAAX0M0 /*TAX16*/ + MOVS reg_x, reg_a + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X1M1 /*TAY8*/ + MOVS reg_y, reg_a + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X0M1 /*TAY16*/ + LDRB reg_y, [reg_cpu_var,#RAH_ofs] + MOV reg_y, reg_y,LSL #24 + ORRS reg_y, reg_y,reg_a, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X1M0 /*TAY8*/ + MOVS reg_y, reg_a, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpA8X0M0 /*TAY16*/ + MOVS reg_y, reg_a + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op5BM1 + LDRB rscratch, [reg_cpu_var,#RAH_ofs] + MOV reg_d,reg_d,LSL #16 + MOV rscratch,rscratch,LSL #24 + ORRS rscratch,rscratch,reg_a, LSR #8 + UPDATE_ZN + ORR reg_d,rscratch,reg_d,LSR #16 + ADD1CYCLE +.endm +.macro Op5BM0 + MOV reg_d,reg_d,LSL #16 + MOVS reg_a,reg_a + UPDATE_ZN + ORR reg_d,reg_a,reg_d,LSR #16 + ADD1CYCLE +.endm +.macro Op1BM1 + TST rstatus, #MASK_EMUL + MOVNE reg_s, reg_a, LSR #24 + ORRNE reg_s, reg_s, #0x100 + LDREQB reg_s, [reg_cpu_var,#RAH_ofs] + ORREQ reg_s, reg_s, reg_a + MOVEQ reg_s, reg_s, ROR #24 + ADD1CYCLE +.endm +.macro Op1BM0 + MOV reg_s, reg_a, LSR #16 + ADD1CYCLE + +.endm +.macro Op7BM1 + MOVS reg_a, reg_d, ASR #16 + UPDATE_ZN + MOV rscratch,reg_a,LSR #8 + MOV reg_a,reg_a, LSL #24 + STRB rscratch, [reg_cpu_var,#RAH_ofs] + ADD1CYCLE +.endm +.macro Op7BM0 + MOVS reg_a, reg_d, ASR #16 + UPDATE_ZN + MOV reg_a,reg_a, LSL #16 + ADD1CYCLE +.endm +.macro Op3BM1 + MOV rscratch,reg_s, LSR #8 + MOVS reg_a, reg_s, LSL #16 + STRB rscratch, [reg_cpu_var,#RAH_ofs] + UPDATE_ZN + MOV reg_a,reg_a, LSL #8 + ADD1CYCLE +.endm +.macro Op3BM0 + MOVS reg_a, reg_s, LSL #16 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBAX1 + MOVS reg_x, reg_s, LSL #24 + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBAX0 + MOVS reg_x, reg_s, LSL #16 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM1X1 + MOVS reg_a, reg_x + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM1X0 + MOVS reg_a, reg_x, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM0X1 + MOVS reg_a, reg_x, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op8AM0X0 + MOVS reg_a, reg_x + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op9AX1 + MOV reg_s, reg_x, LSR #24 + + TST rstatus, #MASK_EMUL + ORRNE reg_s, reg_s, #0x100 + ADD1CYCLE +.endm +.macro Op9AX0 + MOV reg_s, reg_x, LSR #16 + ADD1CYCLE +.endm +.macro Op9BX1 + MOVS reg_y, reg_x + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op9BX0 + MOVS reg_y, reg_x + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M1X1 + MOVS reg_a, reg_y + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M1X0 + MOVS reg_a, reg_y, LSL #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M0X1 + MOVS reg_a, reg_y, LSR #8 + UPDATE_ZN + ADD1CYCLE +.endm +.macro Op98M0X0 + MOVS reg_a, reg_y + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBBX1 + MOVS reg_x, reg_y + UPDATE_ZN + ADD1CYCLE +.endm +.macro OpBBX0 + MOVS reg_x, reg_y + UPDATE_ZN + ADD1CYCLE +.endm + +/**********************************************************************************************/ +/* XCE *************************************************************************************** */ + +.macro OpFB + TST rstatus,#MASK_CARRY + BEQ 1111f + @ CARRY is set + TST rstatus,#MASK_EMUL + BNE 1112f + @ EMUL is cleared + BIC rstatus,rstatus,#(MASK_CARRY) + TST rstatus,#MASK_INDEX + @ X & Y were 16bits before + MOVEQ reg_x,reg_x,LSL #8 + MOVEQ reg_y,reg_y,LSL #8 + TST rstatus,#MASK_MEM + @ A was 16bits before + @ save AH + MOVEQ rscratch,reg_a,LSR #24 + STREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSL #8 + ORR rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX) + AND reg_s,reg_s,#0xFF + ORR reg_s,reg_s,#0x100 + B 1113f +1112: + @ EMUL is set + TST rstatus,#MASK_INDEX + @ X & Y were 16bits before + MOVEQ reg_x,reg_x,LSL #8 + MOVEQ reg_y,reg_y,LSL #8 + TST rstatus,#MASK_MEM + @ A was 16bits before + @ save AH + MOVEQ rscratch,reg_a,LSR #24 + STREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSL #8 + ORR rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX) + AND reg_s,reg_s,#0xFF + ORR reg_s,reg_s,#0x100 + B 1113f +1111: + @ CARRY is cleared + TST rstatus,#MASK_EMUL + BEQ 1115f + @ EMUL was set : X,Y & A were 8bits + @ Now have to check MEMORY & INDEX for potential conversions to 16bits + TST rstatus,#MASK_INDEX + @ X & Y are now 16bits + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus,#MASK_MEM + @ A is now 16bits + MOVEQ reg_a,reg_a,LSR #8 + @ restore AH + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + ORREQ reg_a,reg_a,rscratch,LSL #24 +1115: + BIC rstatus,rstatus,#(MASK_EMUL) + ORR rstatus,rstatus,#(MASK_CARRY) +1113: + ADD1CYCLE + S9xFixCycles +.endm + +/*******************************************************************************/ +/* BRK *************************************************************************/ +.macro Op00 /*BRK*/ + MOV rscratch,#1 + STRB rscratch,[reg_cpu_var,#BRKTriggered_ofs] + + TST rstatus, #MASK_EMUL + @ EQ is flag to zero (!CheckEmu) + BNE 2001f@ elseOp00 + PushBLow reg_p_bank + SUB rscratch, rpc, regpcbase + ADD rscratch2, rscratch, #1 + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank, reg_p_bank, #0xFF + MOV rscratch, #0xE6 + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD2CYCLE + B 2002f@ endOp00 +2001:@ elseOp00 + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank,reg_p_bank, #0xFF + MOV rscratch, #0xFE + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD1CYCLE +2002:@ endOp00 +.endm + + +/**********************************************************************************************/ +/* BRL ************************************************************************************** */ +.macro Op82 /*BRL*/ + asmRelativeLong + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase +.endm +/**********************************************************************************************/ +/* IRQ *************************************************************************************** */ +@ void S9xOpcode_IRQ (void) +.macro S9xOpcode_IRQ @ IRQ + TST rstatus, #MASK_EMUL + @ EQ is flag to zero (!CheckEmu) + BNE 2121f@ elseOp02 + PushBLow reg_p_bank + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank, reg_p_bank,#0xFF + MOV rscratch, #0xEE + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD2CYCLE + B 2122f +2121:@ else + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank,reg_p_bank, #0xFF + MOV rscratch, #0xFE + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD1CYCLE +2122: +.endm + +/* +void asm_S9xOpcode_IRQ(void) +{ + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + S9xSetPCBase (S9xGetWord (0xFFEE)); + CPU.Cycles += TWO_CYCLES; + } + else + { + PushW (CPU.PC - CPU.PCBase); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + S9xSetPCBase (S9xGetWord (0xFFFE)); + CPU.Cycles += ONE_CYCLE; + } +} +*/ + +/**********************************************************************************************/ +/* NMI *************************************************************************************** */ +@ void S9xOpcode_NMI (void) +.macro S9xOpcode_NMI @ NMI + TST rstatus, #MASK_EMUL + @ EQ is flag to zero (!CheckEmu) + BNE 2123f@ elseOp02 + PushBLow reg_p_bank + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank, reg_p_bank,#0xFF + MOV rscratch, #0xEA + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD2CYCLE + B 2124f +2123:@ else + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank,reg_p_bank, #0xFF + MOV rscratch, #0xFA + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD1CYCLE +2124: +.endm +/* +void asm_S9xOpcode_NMI(void) +{ + if (!CheckEmulation()) + { + PushB (Registers.PB); + PushW (CPU.PC - CPU.PCBase); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + S9xSetPCBase (S9xGetWord (0xFFEA)); + CPU.Cycles += TWO_CYCLES; + } + else + { + PushW (CPU.PC - CPU.PCBase); + PushB (Registers.PL); + ClearDecimal (); + SetIRQ (); + + Registers.PB = 0; + S9xSetPCBase (S9xGetWord (0xFFFA)); + CPU.Cycles += ONE_CYCLE; + } +} +*/ + +/**********************************************************************************************/ +/* COP *************************************************************************************** */ +.macro Op02 /*COP*/ + TST rstatus, #MASK_EMUL + @ EQ is flag to zero (!CheckEmu) + BNE 2021f@ elseOp02 + PushBLow reg_p_bank + SUB rscratch, rpc, regpcbase + ADD rscratch2, rscratch, #1 + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank, reg_p_bank,#0xFF + MOV rscratch, #0xE4 + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD2CYCLE + B 2022f@ endOp02 +2021:@ elseOp02 + SUB rscratch2, rpc, regpcbase + PushWLow rscratch2 + @ PackStatus + PushB rstatus + ClearDecimal + SetIRQ + BIC reg_p_bank,reg_p_bank, #0xFF + MOV rscratch, #0xF4 + ORR rscratch, rscratch, #0xFF00 + S9xGetWordLow + S9xSetPCBase + ADD1CYCLE +2022:@ endOp02 +.endm + +/**********************************************************************************************/ +/* JML *************************************************************************************** */ +.macro OpDC + AbsoluteIndirectLong + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank, rscratch, LSR #16 + S9xSetPCBase + ADD2CYCLE +.endm +.macro Op5C + AbsoluteLong + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank, rscratch, LSR #16 + S9xSetPCBase +.endm + +/**********************************************************************************************/ +/* JMP *************************************************************************************** */ +.macro Op4C + Absolute + BIC rscratch, rscratch, #0xFF0000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + CPUShutdown +.endm +.macro Op6C + AbsoluteIndirect + BIC rscratch, rscratch, #0xFF0000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase +.endm +.macro Op7C + ADD rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm + +/**********************************************************************************************/ +/* JSL/RTL *********************************************************************************** */ +.macro Op22 + PushBlow reg_p_bank + SUB rscratch, rpc, regpcbase + @ SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #2 + PushWlow rscratch2 + AbsoluteLong + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank, reg_p_bank, rscratch, LSR #16 + S9xSetPCBase +.endm +.macro Op6B + PullWLow rpc + BIC reg_p_bank,reg_p_bank,#0xFF + PullBrLow + ORR reg_p_bank, reg_p_bank, rscratch + ADD rscratch, rpc, #1 + BIC rscratch, rscratch,#0xFF0000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD2CYCLE +.endm +/**********************************************************************************************/ +/* JSR/RTS *********************************************************************************** */ +.macro Op20 + SUB rscratch, rpc, regpcbase + @ SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #1 + PushWlow rscratch2 + Absolute + BIC rscratch, rscratch, #0xFF0000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm +.macro OpFCX0 + SUB rscratch, rpc, regpcbase + @ SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #1 + PushWlow rscratch2 + AbsoluteIndexedIndirectX0 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm +.macro OpFCX1 + SUB rscratch, rpc, regpcbase + @ SUB rscratch2, rscratch2, #1 + ADD rscratch2, rscratch, #1 + PushWlow rscratch2 + AbsoluteIndexedIndirectX1 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD1CYCLE +.endm +.macro Op60 + PullWLow rpc + ADD rscratch, rpc, #1 + BIC rscratch, rscratch,#0x10000 + ORR rscratch, rscratch, reg_p_bank, LSL #16 + S9xSetPCBase + ADD3CYCLE +.endm + +/**********************************************************************************************/ +/* MVN/MVP *********************************************************************************** */ +.macro Op54X1M1 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #24 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + @ load 16bits A + LDRB rscratch,[reg_cpu_var,#RAH_ofs] + MOV reg_a,reg_a,LSR #8 + ORR reg_a,reg_a,rscratch, LSL #24 + ADD reg_x, reg_x, #0x01000000 + SUB reg_a, reg_a, #0x00010000 + ADD reg_y, reg_y, #0x01000000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + @ update AH + MOV rscratch, reg_a, LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op54X1M0 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #24 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + ADD reg_x, reg_x, #0x01000000 + SUB reg_a, reg_a, #0x00010000 + ADD reg_y, reg_y, #0x01000000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm +.macro Op54X0M1 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #16 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + @ load 16bits A + LDRB rscratch,[reg_cpu_var,#RAH_ofs] + MOV reg_a,reg_a,LSR #8 + ORR reg_a,reg_a,rscratch, LSL #24 + ADD reg_x, reg_x, #0x00010000 + SUB reg_a, reg_a, #0x00010000 + ADD reg_y, reg_y, #0x00010000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + @ update AH + MOV rscratch, reg_a, LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op54X0M0 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #16 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + ADD reg_x, reg_x, #0x00010000 + SUB reg_a, reg_a, #0x00010000 + ADD reg_y, reg_y, #0x00010000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm + +.macro Op44X1M1 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #24 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + @ load 16bits A + LDRB rscratch,[reg_cpu_var,#RAH_ofs] + MOV reg_a,reg_a,LSR #8 + ORR reg_a,reg_a,rscratch, LSL #24 + SUB reg_x, reg_x, #0x01000000 + SUB reg_a, reg_a, #0x00010000 + SUB reg_y, reg_y, #0x01000000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + @ update AH + MOV rscratch, reg_a, LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op44X1M0 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #24 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #24 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + SUB reg_x, reg_x, #0x01000000 + SUB reg_a, reg_a, #0x00010000 + SUB reg_y, reg_y, #0x01000000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm +.macro Op44X0M1 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #16 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + @ load 16bits A + LDRB rscratch,[reg_cpu_var,#RAH_ofs] + MOV reg_a,reg_a,LSR #8 + ORR reg_a,reg_a,rscratch, LSL #24 + SUB reg_x, reg_x, #0x00010000 + SUB reg_a, reg_a, #0x00010000 + SUB reg_y, reg_y, #0x00010000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + @ update AH + MOV rscratch, reg_a, LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE2MEM +.endm +.macro Op44X0M0 + @ Save RegStatus = reg_d_bank >> 24 + MOV rscratch, reg_d_bank, LSR #16 + LDRB reg_d_bank , [rpc], #1 + LDRB rscratch2 , [rpc], #1 + @ Restore RegStatus = reg_d_bank >> 24 + ORR reg_d_bank, reg_d_bank, rscratch, LSL #16 + MOV rscratch , reg_x, LSR #16 + ORR rscratch , rscratch, rscratch2, LSL #16 + S9xGetByteLow + MOV rscratch2, rscratch + MOV rscratch , reg_y, LSR #16 + ORR rscratch , rscratch, reg_d_bank, LSL #16 + S9xSetByteLow rscratch2 + SUB reg_x, reg_x, #0x00010000 + SUB reg_a, reg_a, #0x00010000 + SUB reg_y, reg_y, #0x00010000 + CMP reg_a, #0xFFFF0000 + SUBNE rpc, rpc, #3 + ADD2CYCLE2MEM +.endm + +/**********************************************************************************************/ +/* REP/SEP *********************************************************************************** */ +.macro OpC2 + @ status&=~(*rpc++); + @ so possible changes are : + @ INDEX = 1 -> 0 : X,Y 8bits -> 16bits + @ MEM = 1 -> 0 : A 8bits -> 16bits + @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison + MOV rscratch3, rstatus + LDRB rscratch, [rpc], #1 + MVN rscratch, rscratch + AND rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER) + TST rstatus,#MASK_EMUL + BEQ 1111f + @ emulation mode on : no changes since it was on before opcode + @ just be sure to reset MEM & INDEX accordingly + ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX) + B 1112f +1111: + @ NOT in Emulation mode, check INDEX & MEMORY bits + @ Now check INDEX + TST rscratch3,#MASK_INDEX + BEQ 1113f + @ X & Y were 8bit before + TST rstatus,#MASK_INDEX + BNE 1113f + @ X & Y are now 16bits + MOV reg_x,reg_x,LSR #8 + MOV reg_y,reg_y,LSR #8 +1113: @ X & Y still in 16bits + @ Now check MEMORY + TST rscratch3,#MASK_MEM + BEQ 1112f + @ A was 8bit before + TST rstatus,#MASK_MEM + BNE 1112f + @ A is now 16bits + MOV reg_a,reg_a,LSR #8 + @ restore AH + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + ORREQ reg_a,reg_a,rscratch,LSL #24 +1112: + S9xFixCycles + ADD1CYCLE1MEM +.endm +.macro OpE2 + @ status|=*rpc++; + @ so possible changes are : + @ INDEX = 0 -> 1 : X,Y 16bits -> 8bits + @ MEM = 0 -> 1 : A 16bits -> 8bits + @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison + MOV rscratch3, rstatus + LDRB rscratch, [rpc], #1 + ORR rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER + TST rstatus,#MASK_EMUL + BEQ 10111f + @ emulation mode on : no changes sinc eit was on before opcode + @ just be sure to have mem & index set accordingly + ORR rstatus,rstatus,#(MASK_MEM|MASK_INDEX) + B 10112f +10111: + @ NOT in Emulation mode, check INDEX & MEMORY bits + @ Now check INDEX + TST rscratch3,#MASK_INDEX + BNE 10113f + @ X & Y were 16bit before + TST rstatus,#MASK_INDEX + BEQ 10113f + @ X & Y are now 8bits + MOV reg_x,reg_x,LSL #8 + MOV reg_y,reg_y,LSL #8 +10113: @ X & Y still in 16bits + @ Now check MEMORY + TST rscratch3,#MASK_MEM + BNE 10112f + @ A was 16bit before + TST rstatus,#MASK_MEM + BEQ 10112f + @ A is now 8bits + @ save AH + MOV rscratch,reg_a,LSR #24 + MOV reg_a,reg_a,LSL #8 + STRB rscratch,[reg_cpu_var,#RAH_ofs] +10112: + S9xFixCycles + ADD1CYCLE1MEM +.endm + +/**********************************************************************************************/ +/* XBA *************************************************************************************** */ +.macro OpEBM1 + @ A is 8bits + ADD rscratch,reg_cpu_var,#RAH_ofs + MOV reg_a,reg_a, LSR #24 + SWPB reg_a,reg_a,[rscratch] + MOVS reg_a,reg_a, LSL #24 + UPDATE_ZN + ADD2CYCLE +.endm +.macro OpEBM0 + @ A is 16bits + MOV rscratch, reg_a, ROR #24 @ ll0000hh + ORR rscratch, rscratch, reg_a, LSR #8@ ll0000hh + 00hhll00 -> llhhllhh + MOV reg_a, rscratch, LSL #16@ llhhllhh -> llhh0000 + MOVS rscratch,rscratch,LSL #24 @ to set Z & N flags with AL + UPDATE_ZN + ADD2CYCLE +.endm + + +/**********************************************************************************************/ +/* RTI *************************************************************************************** */ +.macro Op40X1M1 + @ INDEX set, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank,rscratch +2401: + ADD rscratch, rpc, reg_p_bank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + @ INDEX cleared & was set : 8->16 + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus, #MASK_MEM + @ MEMORY cleared & was set : 8->16 + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSR #8 + ORREQ reg_a,reg_a,rscratch, LSL #24 + ADD2CYCLE + S9xFixCycles +.endm +.macro Op40X0M1 + @ INDEX cleared, MEMORY set + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank,rscratch +2401: + ADD rscratch, rpc, reg_p_bank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + @ INDEX set & was cleared : 16->8 + MOVNE reg_x,reg_x,LSL #8 + MOVNE reg_y,reg_y,LSL #8 + TST rstatus, #MASK_MEM + @ MEMORY cleared & was set : 8->16 + LDREQB rscratch,[reg_cpu_var,#RAH_ofs] + MOVEQ reg_a,reg_a,LSR #8 + ORREQ reg_a,reg_a,rscratch, LSL #24 + ADD2CYCLE + S9xFixCycles +.endm +.macro Op40X1M0 + @ INDEX set, MEMORY cleared + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank,rscratch +2401: + ADD rscratch, rpc, reg_p_bank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + @ INDEX cleared & was set : 8->16 + MOVEQ reg_x,reg_x,LSR #8 + MOVEQ reg_y,reg_y,LSR #8 + TST rstatus, #MASK_MEM + @ MEMORY set & was cleared : 16->8 + MOVNE rscratch,reg_a,LSR #24 + MOVNE reg_a,reg_a,LSL #8 + STRNEB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE + S9xFixCycles +.endm +.macro Op40X0M0 + @ INDEX cleared, MEMORY cleared + BIC rstatus,rstatus,#0xFF000000 + PullBr + ORR rstatus,rscratch,rstatus + PullWlow rpc + TST rstatus, #MASK_EMUL + ORRNE rstatus, rstatus, #(MASK_MEM|MASK_INDEX) + BNE 2401f + PullBrLow + BIC reg_p_bank,reg_p_bank,#0xFF + ORR reg_p_bank,reg_p_bank,rscratch +2401: + ADD rscratch, rpc, reg_p_bank, LSL #16 + S9xSetPCBase + TST rstatus, #MASK_INDEX + @ INDEX set & was cleared : 16->8 + MOVNE reg_x,reg_x,LSL #8 + MOVNE reg_y,reg_y,LSL #8 + TST rstatus, #MASK_MEM + @ MEMORY set & was cleared : 16->8 + @ MEMORY set & was cleared : 16->8 + MOVNE rscratch,reg_a,LSR #24 + MOVNE reg_a,reg_a,LSL #8 + STRNEB rscratch,[reg_cpu_var,#RAH_ofs] + ADD2CYCLE + S9xFixCycles +.endm + + +/**********************************************************************************************/ +/* STP/WAI/DB ******************************************************************************** */ +@ WAI +.macro OpCB /*WAI*/ + LDRB rscratch,[reg_cpu_var,#IRQActive_ofs] + MOVS rscratch,rscratch + @ (CPU.IRQActive) + ADD2CYCLENE + BNE 1234f +/* + CPU.WaitingForInterrupt = TRUE; + CPU.PC--;*/ + MOV rscratch,#1 + SUB rpc,rpc,#1 +/* + CPU.Cycles = CPU.NextEvent; +*/ + STRB rscratch,[reg_cpu_var,#WaitingForInterrupt_ofs] + LDR reg_cycles,[reg_cpu_var,#NextEvent_ofs] +/* + if (IAPU.APUExecuting) + { + ICPU.CPUExecuting = FALSE; + do + { + APU_EXECUTE1 (); + } while (APU.Cycles < CPU.NextEvent); + ICPU.CPUExecuting = TRUE; + } +*/ + LDRB rscratch,[reg_cpu_var,#APUExecuting_ofs] + MOVS rscratch,rscratch + BEQ 1234f + asmAPU_EXECUTE2 + +1234: +.endm +.macro OpDB /*STP*/ + SUB rpc,rpc,#1 + @ CPU.Flags |= DEBUG_MODE_FLAG; +.endm +.macro Op42 /*Reserved Snes9X*/ +.endm + +/**********************************************************************************************/ +/* AND ******************************************************************************** */ +.macro Op29M1 + LDRB rscratch , [rpc], #1 + ANDS reg_a , reg_a, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro Op29M0 + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + ANDS reg_a , reg_a, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + + + + + + + + + + + + + + + +/**********************************************************************************************/ +/* EOR ******************************************************************************** */ +.macro Op49M0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2,LSL #8 + EORS reg_a, reg_a, rscratch,LSL #16 + UPDATE_ZN + ADD2MEM +.endm + + +.macro Op49M1 + LDRB rscratch , [rpc], #1 + EORS reg_a, reg_a, rscratch,LSL #24 + UPDATE_ZN + ADD1MEM +.endm + + +/**********************************************************************************************/ +/* STA *************************************************************************************** */ +.macro Op81M1 + STA8 + @ TST rstatus, #MASK_INDEX + @ ADD1CYCLENE +.endm +.macro Op81M0 + STA16 + @ TST rstatus, #MASK_INDEX + @ ADD1CYCLENE +.endm + + +/**********************************************************************************************/ +/* BIT *************************************************************************************** */ +.macro Op89M1 + LDRB rscratch , [rpc], #1 + TST reg_a, rscratch, LSL #24 + UPDATE_Z + ADD1MEM +.endm +.macro Op89M0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + TST reg_a, rscratch, LSL #16 + UPDATE_Z + ADD2MEM +.endm + + + + + + +/**********************************************************************************************/ +/* LDY *************************************************************************************** */ +.macro OpA0X1 + LDRB rscratch , [rpc], #1 + MOVS reg_y, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro OpA0X0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + MOVS reg_y, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* LDX *************************************************************************************** */ +.macro OpA2X1 + LDRB rscratch , [rpc], #1 + MOVS reg_x, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro OpA2X0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + MOVS reg_x, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* LDA *************************************************************************************** */ +.macro OpA9M1 + LDRB rscratch , [rpc], #1 + MOVS reg_a, rscratch, LSL #24 + UPDATE_ZN + ADD1MEM +.endm +.macro OpA9M0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + MOVS reg_a, rscratch, LSL #16 + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* CMY *************************************************************************************** */ +.macro OpC0X1 + LDRB rscratch , [rpc], #1 + SUBS rscratch2 , reg_y , rscratch, LSL #24 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD1MEM +.endm +.macro OpC0X0 + LDRB rscratch2 , [rpc, #1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + SUBS rscratch2 , reg_y, rscratch, LSL #16 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD2MEM +.endm + + + + + +/**********************************************************************************************/ +/* CMP *************************************************************************************** */ +.macro OpC9M1 + LDRB rscratch , [rpc], #1 + SUBS rscratch2 , reg_a , rscratch, LSL #24 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD1MEM +.endm +.macro OpC9M0 + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + SUBS rscratch2 , reg_a, rscratch, LSL #16 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD2MEM +.endm + +/**********************************************************************************************/ +/* CMX *************************************************************************************** */ +.macro OpE0X1 + LDRB rscratch , [rpc], #1 + SUBS rscratch2 , reg_x , rscratch, LSL #24 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD1MEM +.endm +.macro OpE0X0 + LDRB rscratch2 , [rpc,#1] + LDRB rscratch , [rpc], #2 + ORR rscratch, rscratch, rscratch2, LSL #8 + SUBS rscratch2 , reg_x, rscratch, LSL #16 + BICCC rstatus, rstatus, #MASK_CARRY + ORRCS rstatus, rstatus, #MASK_CARRY + UPDATE_ZN + ADD2MEM +.endm + +/* + + +CLI_OPE_REC_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @treasuryDate, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @accountingDate, 103) + +CLI_OPE_Nos_Ope_Layer0 + n.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + n.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +CLI_OPE_Nos_Layer0 + nos.nos_ope_treasury_date = convert(DATETIME, @LARD, 103) + nos.nos_ope_accounting_date = convert(DATETIME, @LARD, 103) + +Ecrans: +------ + + +[GNV] : utilisation de la lard (laccdate) pour afficher les openings. + +nécessité d'avoir des valeurs dans l'opening pour date tréso=date compta=laccdate + +[Accounting rec] : si laccdate pas bonne (pas = BD-1) -> message warning et pas de donnée +sinon : + +données nécessaires : opening date tréso=date compta=laccdate=BD-1 + +données nécessaires : opening date tréso=date compta=laccdate-1 + +données nécessaires : opening date tréso=laccdate-1 et date compta=laccdate + */ + + + +/**************************************************************** + GLOBAL +****************************************************************/ + .globl test_opcode + .globl asmMainLoop + + +@ void asmMainLoop(asm_cpu_var_t *asmcpuPtr); +asmMainLoop: + @ save registers + STMFD R13!,{R4-R11,LR} + @ init pointer to CPUvar structure + MOV reg_cpu_var,R0 + @ init registers + LOAD_REGS + @ get cpu mode from flag and init jump table + S9xFixCycles + b mainLoop + +mainLoop1: + S9xDoHBlankProcessing +mainLoop: + @ APU Execute + asmAPU_EXECUTE + + @ Test Flags + LDR rscratch,[reg_cpu_var,#Flags_ofs] + MOVS rscratch,rscratch + BNE CPUFlags_set @ If flags => check for irq/nmi/scan_keys... + + EXEC_OP @ Execute next opcode + +CPUFlags_set: @ Check flags (!=0) + TST rscratch,#NMI_FLAG @ Check NMI + BEQ CPUFlagsNMI_FLAG_cleared + LDR rscratch2,[reg_cpu_var,#NMICycleCount_ofs] + SUBS rscratch2,rscratch2,#1 + STR rscratch2,[reg_cpu_var,#NMICycleCount_ofs] + BNE CPUFlagsNMI_FLAG_cleared + BIC rscratch,rscratch,#NMI_FLAG + STR rscratch,[reg_cpu_var,#Flags_ofs] + LDRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs] + MOVS rscratch2,rscratch2 + BEQ NotCPUaitingForInterruptNMI + MOV rscratch2,#0 + ADD rpc,rpc,#1 + STRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs] +NotCPUaitingForInterruptNMI: + S9xOpcode_NMI + LDR rscratch,[reg_cpu_var,#Flags_ofs] +CPUFlagsNMI_FLAG_cleared: + TST rscratch,#IRQ_PENDING_FLAG @ Check IRQ_PENDING_FLAG + BEQ CPUFlagsIRQ_PENDING_FLAG_cleared + LDR rscratch2,[reg_cpu_var,#IRQCycleCount_ofs] + MOVS rscratch2,rscratch2 + BNE CPUIRQCycleCount_NotZero + LDRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs] + MOVS rscratch2,rscratch2 + BEQ NotCPUaitingForInterruptIRQ + MOV rscratch2,#0 + ADD rpc,rpc,#1 + STRB rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs] +NotCPUaitingForInterruptIRQ: + LDRB rscratch2,[reg_cpu_var,#IRQActive_ofs] + MOVS rscratch2,rscratch2 + BEQ CPUIRQActive_cleared + TST rstatus,#MASK_IRQ + BNE CPUFlagsIRQ_PENDING_FLAG_cleared + S9xOpcode_IRQ + LDR rscratch,[reg_cpu_var,#Flags_ofs] + B CPUFlagsIRQ_PENDING_FLAG_cleared +CPUIRQActive_cleared: + BIC rscratch,rscratch,#IRQ_PENDING_FLAG + STR rscratch,[reg_cpu_var,#Flags_ofs] + B CPUFlagsIRQ_PENDING_FLAG_cleared +CPUIRQCycleCount_NotZero: + SUB rscratch2,rscratch2,#1 + STR rscratch2,[reg_cpu_var,#IRQCycleCount_ofs] +CPUFlagsIRQ_PENDING_FLAG_cleared: + + TST rscratch,#SCAN_KEYS_FLAG @ Check SCAN_KEYS_FLAG + BNE endmainLoop + + EXEC_OP @ Execute next opcode + +endmainLoop: + + /*Registers.PC = CPU.PC - CPU.PCBase; + S9xPackStatus (); + APURegisters.PC = IAPU.PC - IAPU.RAM; + S9xAPUPackStatus (); + + if (CPU.Flags & SCAN_KEYS_FLAG) + { + S9xSyncSpeed (); + CPU.Flags &= ~SCAN_KEYS_FLAG; + } */ +/********end*/ + SAVE_REGS + LDMFD R13!,{R4-R11,LR} + MOV PC,LR +.pool + +@ void test_opcode(struct asm_cpu_var *asm_var); +test_opcode: + @ save registers + STMFD R13!,{R4-R11,LR} + @ init pointer to CPUvar structure + MOV reg_cpu_var,R0 + @ init registers + LOAD_REGS + @ get cpu mode from flag and init jump table + S9xFixCycles + + EXEC_OP +.pool + +/***************************************************************** + ASM CODE +*****************************************************************/ + + +jumptable1: .long Op00mod1 + .long Op01M1mod1 + .long Op02mod1 + .long Op03M1mod1 + .long Op04M1mod1 + .long Op05M1mod1 + .long Op06M1mod1 + .long Op07M1mod1 + .long Op08mod1 + .long Op09M1mod1 + .long Op0AM1mod1 + .long Op0Bmod1 + .long Op0CM1mod1 + .long Op0DM1mod1 + .long Op0EM1mod1 + .long Op0FM1mod1 + .long Op10mod1 + .long Op11M1mod1 + .long Op12M1mod1 + .long Op13M1mod1 + .long Op14M1mod1 + .long Op15M1mod1 + .long Op16M1mod1 + .long Op17M1mod1 + .long Op18mod1 + .long Op19M1mod1 + .long Op1AM1mod1 + .long Op1Bmod1 + .long Op1CM1mod1 + .long Op1DM1mod1 + .long Op1EM1mod1 + .long Op1FM1mod1 + .long Op20mod1 + .long Op21M1mod1 + .long Op22mod1 + .long Op23M1mod1 + .long Op24M1mod1 + .long Op25M1mod1 + .long Op26M1mod1 + .long Op27M1mod1 + .long Op28mod1 + .long Op29M1mod1 + .long Op2AM1mod1 + .long Op2Bmod1 + .long Op2CM1mod1 + .long Op2DM1mod1 + .long Op2EM1mod1 + .long Op2FM1mod1 + .long Op30mod1 + .long Op31M1mod1 + .long Op32M1mod1 + .long Op33M1mod1 + .long Op34M1mod1 + .long Op35M1mod1 + .long Op36M1mod1 + .long Op37M1mod1 + .long Op38mod1 + .long Op39M1mod1 + .long Op3AM1mod1 + .long Op3Bmod1 + .long Op3CM1mod1 + .long Op3DM1mod1 + .long Op3EM1mod1 + .long Op3FM1mod1 + .long Op40mod1 + .long Op41M1mod1 + .long Op42mod1 + .long Op43M1mod1 + .long Op44X1mod1 + .long Op45M1mod1 + .long Op46M1mod1 + .long Op47M1mod1 + .long Op48M1mod1 + .long Op49M1mod1 + .long Op4AM1mod1 + .long Op4Bmod1 + .long Op4Cmod1 + .long Op4DM1mod1 + .long Op4EM1mod1 + .long Op4FM1mod1 + .long Op50mod1 + .long Op51M1mod1 + .long Op52M1mod1 + .long Op53M1mod1 + .long Op54X1mod1 + .long Op55M1mod1 + .long Op56M1mod1 + .long Op57M1mod1 + .long Op58mod1 + .long Op59M1mod1 + .long Op5AX1mod1 + .long Op5Bmod1 + .long Op5Cmod1 + .long Op5DM1mod1 + .long Op5EM1mod1 + .long Op5FM1mod1 + .long Op60mod1 + .long Op61M1mod1 + .long Op62mod1 + .long Op63M1mod1 + .long Op64M1mod1 + .long Op65M1mod1 + .long Op66M1mod1 + .long Op67M1mod1 + .long Op68M1mod1 + .long Op69M1mod1 + .long Op6AM1mod1 + .long Op6Bmod1 + .long Op6Cmod1 + .long Op6DM1mod1 + .long Op6EM1mod1 + .long Op6FM1mod1 + .long Op70mod1 + .long Op71M1mod1 + .long Op72M1mod1 + .long Op73M1mod1 + .long Op74M1mod1 + .long Op75M1mod1 + .long Op76M1mod1 + .long Op77M1mod1 + .long Op78mod1 + .long Op79M1mod1 + .long Op7AX1mod1 + .long Op7Bmod1 + .long Op7Cmod1 + .long Op7DM1mod1 + .long Op7EM1mod1 + .long Op7FM1mod1 + .long Op80mod1 + .long Op81M1mod1 + .long Op82mod1 + .long Op83M1mod1 + .long Op84X1mod1 + .long Op85M1mod1 + .long Op86X1mod1 + .long Op87M1mod1 + .long Op88X1mod1 + .long Op89M1mod1 + .long Op8AM1mod1 + .long Op8Bmod1 + .long Op8CX1mod1 + .long Op8DM1mod1 + .long Op8EX1mod1 + .long Op8FM1mod1 + .long Op90mod1 + .long Op91M1mod1 + .long Op92M1mod1 + .long Op93M1mod1 + .long Op94X1mod1 + .long Op95M1mod1 + .long Op96X1mod1 + .long Op97M1mod1 + .long Op98M1mod1 + .long Op99M1mod1 + + .long Op9Amod1 + .long Op9BX1mod1 + .long Op9CM1mod1 + .long Op9DM1mod1 + .long Op9EM1mod1 + .long Op9FM1mod1 + .long OpA0X1mod1 + .long OpA1M1mod1 + .long OpA2X1mod1 + .long OpA3M1mod1 + .long OpA4X1mod1 + .long OpA5M1mod1 + .long OpA6X1mod1 + .long OpA7M1mod1 + .long OpA8X1mod1 + .long OpA9M1mod1 + .long OpAAX1mod1 + .long OpABmod1 + .long OpACX1mod1 + .long OpADM1mod1 + .long OpAEX1mod1 + .long OpAFM1mod1 + .long OpB0mod1 + .long OpB1M1mod1 + .long OpB2M1mod1 + .long OpB3M1mod1 + .long OpB4X1mod1 + .long OpB5M1mod1 + .long OpB6X1mod1 + .long OpB7M1mod1 + .long OpB8mod1 + .long OpB9M1mod1 + .long OpBAX1mod1 + .long OpBBX1mod1 + .long OpBCX1mod1 + .long OpBDM1mod1 + .long OpBEX1mod1 + .long OpBFM1mod1 + .long OpC0X1mod1 + .long OpC1M1mod1 + .long OpC2mod1 + .long OpC3M1mod1 + .long OpC4X1mod1 + .long OpC5M1mod1 + .long OpC6M1mod1 + .long OpC7M1mod1 + .long OpC8X1mod1 + .long OpC9M1mod1 + .long OpCAX1mod1 + .long OpCBmod1 + .long OpCCX1mod1 + .long OpCDM1mod1 + .long OpCEM1mod1 + .long OpCFM1mod1 + .long OpD0mod1 + .long OpD1M1mod1 + .long OpD2M1mod1 + .long OpD3M1mod1 + .long OpD4mod1 + .long OpD5M1mod1 + .long OpD6M1mod1 + .long OpD7M1mod1 + .long OpD8mod1 + .long OpD9M1mod1 + .long OpDAX1mod1 + .long OpDBmod1 + .long OpDCmod1 + .long OpDDM1mod1 + .long OpDEM1mod1 + .long OpDFM1mod1 + .long OpE0X1mod1 + .long OpE1M1mod1 + .long OpE2mod1 + .long OpE3M1mod1 + .long OpE4X1mod1 + .long OpE5M1mod1 + .long OpE6M1mod1 + .long OpE7M1mod1 + .long OpE8X1mod1 + .long OpE9M1mod1 + .long OpEAmod1 + .long OpEBmod1 + .long OpECX1mod1 + .long OpEDM1mod1 + .long OpEEM1mod1 + .long OpEFM1mod1 + .long OpF0mod1 + .long OpF1M1mod1 + .long OpF2M1mod1 + .long OpF3M1mod1 + .long OpF4mod1 + .long OpF5M1mod1 + .long OpF6M1mod1 + .long OpF7M1mod1 + .long OpF8mod1 + .long OpF9M1mod1 + .long OpFAX1mod1 + .long OpFBmod1 + .long OpFCmod1 + .long OpFDM1mod1 + .long OpFEM1mod1 + .long OpFFM1mod1 + +Op00mod1: +lbl00mod1: Op00 + NEXTOPCODE 8 + @ 24 @ 8 +Op01M1mod1: +lbl01mod1a: DirectIndexedIndirect1 +lbl01mod1b: ORA8 + NEXTOPCODE 6 + @ 22 @ 6 +Op02mod1: +lbl02mod1: Op02 + NEXTOPCODE 8 + @ 24 @ 8 +Op03M1mod1: +lbl03mod1a: StackasmRelative +lbl03mod1b: ORA8 + NEXTOPCODE 4 + @ 20 @ 4 +Op04M1mod1: +lbl04mod1a: Direct +lbl04mod1b: TSB8 + NEXTOPCODE 5 + @ 21 @ 5 +Op05M1mod1: +lbl05mod1a: Direct +lbl05mod1b: ORA8 + NEXTOPCODE 3 + @ 19 @ 3 +Op06M1mod1: +lbl06mod1a: Direct +lbl06mod1b: ASL8 + NEXTOPCODE 5 + @ 21 @ 5 +Op07M1mod1: +lbl07mod1a: DirectIndirectLong +lbl07mod1b: ORA8 + NEXTOPCODE 6 + @ 22 @ 6 +Op08mod1: +lbl08mod1: Op08 + NEXTOPCODE 3 + @ 11 @ 3 +Op09M1mod1: +lbl09mod1: Op09M1 + NEXTOPCODE 2 + @ 18 @ 2 +Op0AM1mod1: +lbl0Amod1a: A_ASL8 + NEXTOPCODE 2 + @ 10 @ 2 +Op0Bmod1: +lbl0Bmod1: Op0B + NEXTOPCODE 4 + @ 12 @ 4 +Op0CM1mod1: +lbl0Cmod1a: Absolute +lbl0Cmod1b: TSB8 + NEXTOPCODE 6 + @ 30 @ 6 +Op0DM1mod1: +lbl0Dmod1a: Absolute +lbl0Dmod1b: ORA8 + NEXTOPCODE 4 + @ 28 @ 4 +Op0EM1mod1: +lbl0Emod1a: Absolute +lbl0Emod1b: ASL8 + NEXTOPCODE 6 + @ 30 @ 6 +Op0FM1mod1: +lbl0Fmod1a: AbsoluteLong +lbl0Fmod1b: ORA8 + NEXTOPCODE 5 + @ 37 @ 5 +Op10mod1: +lbl10mod1: Op10 + NEXTOPCODE 2 + @ 18 @ 2 +Op11M1mod1: +lbl11mod1a: DirectIndirectIndexed1 +lbl11mod1b: ORA8 + NEXTOPCODE 5 + @ 21 @ 5 +Op12M1mod1: +lbl12mod1a: DirectIndirect +lbl12mod1b: ORA8 + NEXTOPCODE 5 + @ 21 @ 5 +Op13M1mod1: +lbl13mod1a: StackasmRelativeIndirectIndexed1 +lbl13mod1b: ORA8 + NEXTOPCODE 7 + @ 23 @ 7 +Op14M1mod1: +lbl14mod1a: Direct +lbl14mod1b: TRB8 + NEXTOPCODE 5 + @ 21 @ 5 +Op15M1mod1: +lbl15mod1a: DirectIndexedX1 +lbl15mod1b: ORA8 + NEXTOPCODE 4 + @ 20 @ 4 +Op16M1mod1: +lbl16mod1a: DirectIndexedX1 +lbl16mod1b: ASL8 + NEXTOPCODE 6 + @ 22 @ 6 +Op17M1mod1: +lbl17mod1a: DirectIndirectIndexedLong1 +lbl17mod1b: ORA8 + NEXTOPCODE 6 + @ 22 @ 6 +Op18mod1: +lbl18mod1: Op18 + NEXTOPCODE 2 + @ 10 @ 2 +Op19M1mod1: +lbl19mod1a: AbsoluteIndexedY1 +lbl19mod1b: ORA8 + NEXTOPCODE 4 + @ 28 @ 4 +Op1AM1mod1: +lbl1Amod1a: A_INC8 + NEXTOPCODE 2 + @ 10 @ 2 +Op1Bmod1: +lbl1Bmod1: Op1BM1 + NEXTOPCODE 2 + @ 10 @ 2 +Op1CM1mod1: +lbl1Cmod1a: Absolute +lbl1Cmod1b: TRB8 + NEXTOPCODE 6 + @ 30 @ 6 +Op1DM1mod1: +lbl1Dmod1a: AbsoluteIndexedX1 +lbl1Dmod1b: ORA8 + NEXTOPCODE 4 + @ 28 @ 4 +Op1EM1mod1: +lbl1Emod1a: AbsoluteIndexedX1 +lbl1Emod1b: ASL8 + NEXTOPCODE 7 + @ 31 @ 7 +Op1FM1mod1: +lbl1Fmod1a: AbsoluteLongIndexedX1 +lbl1Fmod1b: ORA8 + NEXTOPCODE 5 + @ 37 @ 5 +Op20mod1: +lbl20mod1: Op20 + NEXTOPCODE 6 + @ 30 @ 6 +Op21M1mod1: +lbl21mod1a: DirectIndexedIndirect1 +lbl21mod1b: AND8 + NEXTOPCODE 6 + @ 22 @ 6 +Op22mod1: +lbl22mod1: Op22 + NEXTOPCODE 8 + @ 40 @ 8 +Op23M1mod1: +lbl23mod1a: StackasmRelative +lbl23mod1b: AND8 + NEXTOPCODE 4 + @ 20 @ 4 +Op24M1mod1: +lbl24mod1a: Direct +lbl24mod1b: BIT8 + NEXTOPCODE 3 + @ 19 @ 3 +Op25M1mod1: +lbl25mod1a: Direct +lbl25mod1b: AND8 + NEXTOPCODE 3 + @ 19 @ 3 +Op26M1mod1: +lbl26mod1a: Direct +lbl26mod1b: ROL8 + NEXTOPCODE 5 + @ 21 @ 5 +Op27M1mod1: +lbl27mod1a: DirectIndirectLong +lbl27mod1b: AND8 + NEXTOPCODE 6 + @ 22 @ 6 +Op28mod1: +lbl28mod1: Op28X1M1 + NEXTOPCODE 4 + @ 12 @ 4 +.pool +Op29M1mod1: +lbl29mod1: Op29M1 + NEXTOPCODE 2 + @ 18 @ 2 +Op2AM1mod1: +lbl2Amod1a: A_ROL8 + NEXTOPCODE 2 + @ 10 @ 2 +Op2Bmod1: +lbl2Bmod1: Op2B + NEXTOPCODE 5 + @ 13 @ 5 +Op2CM1mod1: +lbl2Cmod1a: Absolute +lbl2Cmod1b: BIT8 + NEXTOPCODE 4 + @ 28 @ 4 +Op2DM1mod1: +lbl2Dmod1a: Absolute +lbl2Dmod1b: AND8 + NEXTOPCODE 4 + @ 28 @ 4 +Op2EM1mod1: +lbl2Emod1a: Absolute +lbl2Emod1b: ROL8 + NEXTOPCODE 6 + @ 30 @ 6 +Op2FM1mod1: +lbl2Fmod1a: AbsoluteLong +lbl2Fmod1b: AND8 + NEXTOPCODE 5 + @ 37 @ 5 +Op30mod1: +lbl30mod1: Op30 + NEXTOPCODE 2 + @ 18 @ 2 +Op31M1mod1: +lbl31mod1a: DirectIndirectIndexed1 +lbl31mod1b: AND8 + NEXTOPCODE 5 + @ 21 @ 5 +Op32M1mod1: +lbl32mod1a: DirectIndirect +lbl32mod1b: AND8 + NEXTOPCODE 5 + @ 21 @ 5 +Op33M1mod1: +lbl33mod1a: StackasmRelativeIndirectIndexed1 +lbl33mod1b: AND8 + NEXTOPCODE 7 + @ 23 @ 7 +Op34M1mod1: +lbl34mod1a: DirectIndexedX1 +lbl34mod1b: BIT8 + NEXTOPCODE 4 + @ 20 @ 4 +Op35M1mod1: +lbl35mod1a: DirectIndexedX1 +lbl35mod1b: AND8 + NEXTOPCODE 4 + @ 20 @ 4 +Op36M1mod1: +lbl36mod1a: DirectIndexedX1 +lbl36mod1b: ROL8 + NEXTOPCODE 6 + @ 22 @ 6 +Op37M1mod1: +lbl37mod1a: DirectIndirectIndexedLong1 +lbl37mod1b: AND8 + NEXTOPCODE 6 + @ 22 @ 6 +Op38mod1: +lbl38mod1: Op38 + NEXTOPCODE 2 + @ 10 @ 2 +Op39M1mod1: +lbl39mod1a: AbsoluteIndexedY1 +lbl39mod1b: AND8 + NEXTOPCODE 4 + @ 28 @ 4 +Op3AM1mod1: +lbl3Amod1a: A_DEC8 + NEXTOPCODE 2 + @ 10 @ 2 +Op3Bmod1: +lbl3Bmod1: Op3BM1 + NEXTOPCODE 2 + @ 10 @ 2 +Op3CM1mod1: +lbl3Cmod1a: AbsoluteIndexedX1 +lbl3Cmod1b: BIT8 + NEXTOPCODE 4 + @ 28 @ 4 +Op3DM1mod1: +lbl3Dmod1a: AbsoluteIndexedX1 +lbl3Dmod1b: AND8 + NEXTOPCODE 4 + @ 28 @ 4 +Op3EM1mod1: +lbl3Emod1a: AbsoluteIndexedX1 +lbl3Emod1b: ROL8 + NEXTOPCODE 7 + @ 31 @ 7 +Op3FM1mod1: +lbl3Fmod1a: AbsoluteLongIndexedX1 +lbl3Fmod1b: AND8 + NEXTOPCODE 5 + @ 37 @ 5 +Op40mod1: +lbl40mod1: Op40X1M1 + NEXTOPCODE 7 + @ 15 @ 7 +.pool +Op41M1mod1: +lbl41mod1a: DirectIndexedIndirect1 +lbl41mod1b: EOR8 + NEXTOPCODE 6 + @ 22 @ 6 +Op42mod1: +lbl42mod1: Op42 + NEXTOPCODE 2 + @ 18 @ 2 +Op43M1mod1: +lbl43mod1a: StackasmRelative +lbl43mod1b: EOR8 + NEXTOPCODE 4 + @ 20 @ 4 +Op44X1mod1: +lbl44mod1: Op44X1M1 + NEXTOPCODE 0 + @ 24 @ 0 +Op45M1mod1: +lbl45mod1a: Direct +lbl45mod1b: EOR8 + NEXTOPCODE 3 + @ 19 @ 3 +Op46M1mod1: +lbl46mod1a: Direct +lbl46mod1b: LSR8 + NEXTOPCODE 5 + @ 21 @ 5 +Op47M1mod1: +lbl47mod1a: DirectIndirectLong +lbl47mod1b: EOR8 + NEXTOPCODE 6 + @ 22 @ 6 +Op48M1mod1: +lbl48mod1: Op48M1 + NEXTOPCODE 3 + @ 11 @ 3 +Op49M1mod1: +lbl49mod1: Op49M1 + NEXTOPCODE 2 + @ 18 @ 2 +Op4AM1mod1: +lbl4Amod1a: A_LSR8 + NEXTOPCODE 2 + @ 10 @ 2 +Op4Bmod1: +lbl4Bmod1: Op4B + NEXTOPCODE 3 + @ 11 @ 3 +Op4Cmod1: +lbl4Cmod1: Op4C + NEXTOPCODE 3 + @ 27 @ 3 +Op4DM1mod1: +lbl4Dmod1a: Absolute +lbl4Dmod1b: EOR8 + NEXTOPCODE 4 + @ 28 @ 4 +Op4EM1mod1: +lbl4Emod1a: Absolute +lbl4Emod1b: LSR8 + NEXTOPCODE 6 + @ 30 @ 6 +Op4FM1mod1: +lbl4Fmod1a: AbsoluteLong +lbl4Fmod1b: EOR8 + NEXTOPCODE 5 + @ 37 @ 5 +Op50mod1: +lbl50mod1: Op50 + NEXTOPCODE 2 + @ 18 @ 2 +Op51M1mod1: +lbl51mod1a: DirectIndirectIndexed1 +lbl51mod1b: EOR8 + NEXTOPCODE 5 + @ 21 @ 5 +Op52M1mod1: +lbl52mod1a: DirectIndirect +lbl52mod1b: EOR8 + NEXTOPCODE 5 + @ 21 @ 5 +Op53M1mod1: +lbl53mod1a: StackasmRelativeIndirectIndexed1 +lbl53mod1b: EOR8 + NEXTOPCODE 7 + @ 23 @ 7 +Op54X1mod1: +lbl54mod1: Op54X1M1 + NEXTOPCODE 0 + @ 24 @ 0 +Op55M1mod1: +lbl55mod1a: DirectIndexedX1 +lbl55mod1b: EOR8 + NEXTOPCODE 4 + @ 20 @ 4 +Op56M1mod1: +lbl56mod1a: DirectIndexedX1 +lbl56mod1b: LSR8 + NEXTOPCODE 6 + @ 22 @ 6 +Op57M1mod1: +lbl57mod1a: DirectIndirectIndexedLong1 +lbl57mod1b: EOR8 + NEXTOPCODE 6 + @ 22 @ 6 +Op58mod1: +lbl58mod1: Op58 + NEXTOPCODE 2 + @ 10 @ 2 +Op59M1mod1: +lbl59mod1a: AbsoluteIndexedY1 +lbl59mod1b: EOR8 + NEXTOPCODE 4 + @ 28 @ 4 +Op5AX1mod1: +lbl5Amod1: Op5AX1 + NEXTOPCODE 3 + @ 11 @ 3 +Op5Bmod1: +lbl5Bmod1: Op5BM1 + NEXTOPCODE 2 + @ 10 @ 2 +Op5Cmod1: +lbl5Cmod1: Op5C + NEXTOPCODE 4 + @ 36 @ 4 +Op5DM1mod1: +lbl5Dmod1a: AbsoluteIndexedX1 +lbl5Dmod1b: EOR8 + NEXTOPCODE 4 + @ 28 @ 4 +Op5EM1mod1: +lbl5Emod1a: AbsoluteIndexedX1 +lbl5Emod1b: LSR8 + NEXTOPCODE 7 + @ 31 @ 7 +Op5FM1mod1: +lbl5Fmod1a: AbsoluteLongIndexedX1 +lbl5Fmod1b: EOR8 + NEXTOPCODE 5 + @ 37 @ 5 +Op60mod1: +lbl60mod1: Op60 + NEXTOPCODE 6 + @ 14 @ 6 +Op61M1mod1: +lbl61mod1a: DirectIndexedIndirect1 +lbl61mod1b: ADC8 + NEXTOPCODE 6 + @ 22 @ 6 +Op62mod1: +lbl62mod1: Op62 + NEXTOPCODE 6 + @ 30 @ 6 +Op63M1mod1: +lbl63mod1a: StackasmRelative +lbl63mod1b: ADC8 + NEXTOPCODE 4 + @ 20 @ 4 +Op64M1mod1: +lbl64mod1a: Direct +lbl64mod1b: STZ8 + NEXTOPCODE 3 + @ 19 @ 3 +Op65M1mod1: +lbl65mod1a: Direct +lbl65mod1b: ADC8 + NEXTOPCODE 3 + @ 19 @ 3 +Op66M1mod1: +lbl66mod1a: Direct +lbl66mod1b: ROR8 + NEXTOPCODE 5 + @ 21 @ 5 +Op67M1mod1: +lbl67mod1a: DirectIndirectLong +lbl67mod1b: ADC8 + NEXTOPCODE 6 + @ 22 @ 6 +Op68M1mod1: +lbl68mod1: Op68M1 + NEXTOPCODE 4 + @ 12 @ 4 +Op69M1mod1: +lbl69mod1a: Immediate8 +lbl69mod1b: ADC8 + NEXTOPCODE 2 + @ 18 @ 2 +Op6AM1mod1: +lbl6Amod1a: A_ROR8 + NEXTOPCODE 2 + @ 10 @ 2 +Op6Bmod1: +lbl6Bmod1: Op6B + NEXTOPCODE 6 + @ 14 @ 6 +Op6Cmod1: +lbl6Cmod1: Op6C + NEXTOPCODE 5 + @ 29 @ 5 +Op6DM1mod1: +lbl6Dmod1a: Absolute +lbl6Dmod1b: ADC8 + NEXTOPCODE 4 + @ 28 @ 4 +Op6EM1mod1: + +lbl6Emod1a: Absolute +lbl6Emod1b: ROR8 + NEXTOPCODE 6 + @ 30 @ 6 +Op6FM1mod1: +lbl6Fmod1a: AbsoluteLong +lbl6Fmod1b: ADC8 + NEXTOPCODE 5 + @ 37 @ 5 +Op70mod1: +lbl70mod1: Op70 + NEXTOPCODE 2 + @ 18 @ 2 +Op71M1mod1: +lbl71mod1a: DirectIndirectIndexed1 +lbl71mod1b: ADC8 + NEXTOPCODE 5 + @ 21 @ 5 +Op72M1mod1: +lbl72mod1a: DirectIndirect +lbl72mod1b: ADC8 + NEXTOPCODE 5 + @ 21 @ 5 +Op73M1mod1: +lbl73mod1a: StackasmRelativeIndirectIndexed1 +lbl73mod1b: ADC8 + NEXTOPCODE 7 + @ 23 @ 7 + +Op74M1mod1: +lbl74mod1a: DirectIndexedX1 +lbl74mod1b: STZ8 + NEXTOPCODE 4 + @ 20 @ 4 +Op75M1mod1: +lbl75mod1a: DirectIndexedX1 +lbl75mod1b: ADC8 + NEXTOPCODE 4 + @ 20 @ 4 +Op76M1mod1: +lbl76mod1a: DirectIndexedX1 +lbl76mod1b: ROR8 + NEXTOPCODE 6 + @ 22 @ 6 +Op77M1mod1: +lbl77mod1a: DirectIndirectIndexedLong1 +lbl77mod1b: ADC8 + NEXTOPCODE 6 + @ 22 @ 6 +Op78mod1: +lbl78mod1: Op78 + NEXTOPCODE 2 + @ 10 @ 2 +Op79M1mod1: +lbl79mod1a: AbsoluteIndexedY1 +lbl79mod1b: ADC8 + NEXTOPCODE 4 + @ 28 @ 4 +Op7AX1mod1: +lbl7Amod1: Op7AX1 + NEXTOPCODE 4 + @ 12 @ 4 +Op7Bmod1: +lbl7Bmod1: Op7BM1 + NEXTOPCODE 2 + @ 10 @ 2 +Op7Cmod1: +lbl7Cmod1: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE 6 + @ 30 @ 6 +Op7DM1mod1: +lbl7Dmod1a: AbsoluteIndexedX1 +lbl7Dmod1b: ADC8 + NEXTOPCODE 4 + @ 28 @ 4 +Op7EM1mod1: +lbl7Emod1a: AbsoluteIndexedX1 +lbl7Emod1b: ROR8 + NEXTOPCODE 7 + @ 31 @ 7 +Op7FM1mod1: +lbl7Fmod1a: AbsoluteLongIndexedX1 +lbl7Fmod1b: ADC8 + NEXTOPCODE 5 + @ 37 @ 5 + + +Op80mod1: +lbl80mod1: Op80 + NEXTOPCODE 2 + @ 18 @ 2 +Op81M1mod1: +lbl81mod1a: DirectIndexedIndirect1 +lbl81mod1b: Op81M1 + NEXTOPCODE 6 + @ 22 @ 6 +Op82mod1: +lbl82mod1: Op82 + NEXTOPCODE 3 + @ 27 @ 3 +Op83M1mod1: +lbl83mod1a: StackasmRelative +lbl83mod1b: STA8 + NEXTOPCODE 4 + @ 20 @ 4 +Op84X1mod1: +lbl84mod1a: Direct +lbl84mod1b: STY8 + NEXTOPCODE 3 + @ 19 @ 3 +Op85M1mod1: +lbl85mod1a: Direct +lbl85mod1b: STA8 + NEXTOPCODE 3 + @ 19 @ 3 +Op86X1mod1: +lbl86mod1a: Direct +lbl86mod1b: STX8 + NEXTOPCODE 3 + @ 19 @ 3 +Op87M1mod1: +lbl87mod1a: DirectIndirectLong +lbl87mod1b: STA8 + NEXTOPCODE 6 + @ 22 @ 6 +Op88X1mod1: +lbl88mod1: Op88X1 + NEXTOPCODE 2 + @ 10 @ 2 +Op89M1mod1: +lbl89mod1: Op89M1 + NEXTOPCODE 2 + @ 18 @ 2 +Op8AM1mod1: +lbl8Amod1: Op8AM1X1 + NEXTOPCODE 2 + @ 10 @ 2 +Op8Bmod1: +lbl8Bmod1: Op8B + NEXTOPCODE 3 + @ 11 @ 3 +Op8CX1mod1: +lbl8Cmod1a: Absolute +lbl8Cmod1b: STY8 + NEXTOPCODE 4 + @ 28 @ 4 +Op8DM1mod1: +lbl8Dmod1a: Absolute +lbl8Dmod1b: STA8 + NEXTOPCODE 4 + @ 28 @ 4 +Op8EX1mod1: +lbl8Emod1a: Absolute +lbl8Emod1b: STX8 + NEXTOPCODE 4 + @ 28 @ 4 +Op8FM1mod1: +lbl8Fmod1a: AbsoluteLong +lbl8Fmod1b: STA8 + NEXTOPCODE 5 + @ 37 @ 5 +Op90mod1: +lbl90mod1: Op90 + NEXTOPCODE 2 + @ 18 @ 2 +Op91M1mod1: +lbl91mod1a: DirectIndirectIndexed1 +lbl91mod1b: STA8 + NEXTOPCODE 5 + @ 21 @ 5 +Op92M1mod1: +lbl92mod1a: DirectIndirect +lbl92mod1b: STA8 + NEXTOPCODE 5 + @ 21 @ 5 +Op93M1mod1: +lbl93mod1a: StackasmRelativeIndirectIndexed1 +lbl93mod1b: STA8 + NEXTOPCODE 7 + @ 23 @ 7 +Op94X1mod1: +lbl94mod1a: DirectIndexedX1 +lbl94mod1b: STY8 + NEXTOPCODE 4 + @ 20 @ 4 +Op95M1mod1: +lbl95mod1a: DirectIndexedX1 +lbl95mod1b: STA8 + NEXTOPCODE 4 + @ 20 @ 4 +Op96X1mod1: +lbl96mod1a: DirectIndexedY1 +lbl96mod1b: STX8 + NEXTOPCODE 4 + @ 20 @ 4 +Op97M1mod1: +lbl97mod1a: DirectIndirectIndexedLong1 +lbl97mod1b: STA8 + NEXTOPCODE 6 + @ 22 @ 6 +Op98M1mod1: +lbl98mod1: Op98M1X1 + NEXTOPCODE 2 + @ 10 @ 2 +Op99M1mod1: +lbl99mod1a: AbsoluteIndexedY1 +lbl99mod1b: STA8 + NEXTOPCODE 4 + @ 28 @ 4 +Op9Amod1: +lbl9Amod1: Op9AX1 + NEXTOPCODE 2 + @ 10 @ 2 +Op9BX1mod1: +lbl9Bmod1: Op9BX1 + NEXTOPCODE 2 + @ 10 @ 2 +Op9CM1mod1: +lbl9Cmod1a: Absolute +lbl9Cmod1b: STZ8 + NEXTOPCODE 4 + @ 28 @ 4 +Op9DM1mod1: +lbl9Dmod1a: AbsoluteIndexedX1 +lbl9Dmod1b: STA8 + NEXTOPCODE 4 + @ 28 @ 4 +Op9EM1mod1: +lbl9Emod1: AbsoluteIndexedX1 + STZ8 + NEXTOPCODE 4 + @ 28 @ 4 +Op9FM1mod1: +lbl9Fmod1a: AbsoluteLongIndexedX1 +lbl9Fmod1b: STA8 + NEXTOPCODE 5 + @ 37 @ 5 +OpA0X1mod1: +lblA0mod1: OpA0X1 + NEXTOPCODE 2 + @ 18 @ 2 +OpA1M1mod1: +lblA1mod1a: DirectIndexedIndirect1 +lblA1mod1b: LDA8 + NEXTOPCODE 6 + @ 22 @ 6 +OpA2X1mod1: +lblA2mod1: OpA2X1 + NEXTOPCODE 2 + @ 18 @ 2 +OpA3M1mod1: +lblA3mod1a: StackasmRelative +lblA3mod1b: LDA8 + NEXTOPCODE 4 + @ 20 @ 4 +OpA4X1mod1: +lblA4mod1a: Direct +lblA4mod1b: LDY8 + NEXTOPCODE 3 + @ 19 @ 3 +OpA5M1mod1: +lblA5mod1a: Direct +lblA5mod1b: LDA8 + NEXTOPCODE 3 + @ 19 @ 3 +OpA6X1mod1: +lblA6mod1a: Direct +lblA6mod1b: LDX8 + NEXTOPCODE 3 + @ 19 @ 3 +OpA7M1mod1: +lblA7mod1a: DirectIndirectLong +lblA7mod1b: LDA8 + NEXTOPCODE 6 + @ 22 @ 6 +OpA8X1mod1: +lblA8mod1: OpA8X1M1 + NEXTOPCODE 2 + @ 10 @ 2 +OpA9M1mod1: +lblA9mod1: OpA9M1 + NEXTOPCODE 2 + @ 18 @ 2 +OpAAX1mod1: +lblAAmod1: OpAAX1M1 + NEXTOPCODE 2 + @ 10 @ 2 +OpABmod1: +lblABmod1: OpAB + NEXTOPCODE 4 + @ 12 @ 4 +OpACX1mod1: +lblACmod1a: Absolute +lblACmod1b: LDY8 + NEXTOPCODE 4 + @ 28 @ 4 +OpADM1mod1: +lblADmod1a: Absolute +lblADmod1b: LDA8 + NEXTOPCODE 4 + @ 28 @ 4 +OpAEX1mod1: +lblAEmod1a: Absolute +lblAEmod1b: LDX8 + NEXTOPCODE 4 + @ 28 @ 4 +OpAFM1mod1: +lblAFmod1a: AbsoluteLong +lblAFmod1b: LDA8 + NEXTOPCODE 5 + @ 37 @ 5 +OpB0mod1: +lblB0mod1: OpB0 + NEXTOPCODE 2 + @ 18 @ 2 +OpB1M1mod1: +lblB1mod1a: DirectIndirectIndexed1 +lblB1mod1b: LDA8 + NEXTOPCODE 5 + @ 21 @ 5 +OpB2M1mod1: +lblB2mod1a: DirectIndirect +lblB2mod1b: LDA8 + NEXTOPCODE 5 + @ 21 @ 5 +OpB3M1mod1: +lblB3mod1a: StackasmRelativeIndirectIndexed1 +lblB3mod1b: LDA8 + NEXTOPCODE 7 + @ 23 @ 7 +OpB4X1mod1: +lblB4mod1a: DirectIndexedX1 +lblB4mod1b: LDY8 + NEXTOPCODE 4 + @ 20 @ 4 +OpB5M1mod1: +lblB5mod1a: DirectIndexedX1 +lblB5mod1b: LDA8 + NEXTOPCODE 4 + @ 20 @ 4 +OpB6X1mod1: +lblB6mod1a: DirectIndexedY1 +lblB6mod1b: LDX8 + NEXTOPCODE 4 + @ 20 @ 4 +OpB7M1mod1: +lblB7mod1a: DirectIndirectIndexedLong1 +lblB7mod1b: LDA8 + NEXTOPCODE 6 + @ 22 @ 6 +OpB8mod1: +lblB8mod1: OpB8 + NEXTOPCODE 2 + @ 10 @ 2 +OpB9M1mod1: +lblB9mod1a: AbsoluteIndexedY1 +lblB9mod1b: LDA8 + NEXTOPCODE 4 + @ 28 @ 4 +OpBAX1mod1: +lblBAmod1: OpBAX1 + NEXTOPCODE 2 + @ 10 @ 2 +OpBBX1mod1: +lblBBmod1: OpBBX1 + NEXTOPCODE 2 + @ 10 @ 2 +OpBCX1mod1: +lblBCmod1a: AbsoluteIndexedX1 +lblBCmod1b: LDY8 + NEXTOPCODE 4 + @ 28 @ 4 +OpBDM1mod1: +lblBDmod1a: AbsoluteIndexedX1 +lblBDmod1b: LDA8 + NEXTOPCODE 4 + @ 28 @ 4 +OpBEX1mod1: +lblBEmod1a: AbsoluteIndexedY1 +lblBEmod1b: LDX8 + NEXTOPCODE 4 + @ 28 @ 4 +OpBFM1mod1: +lblBFmod1a: AbsoluteLongIndexedX1 +lblBFmod1b: LDA8 + NEXTOPCODE 5 + @ 37 @ 5 +OpC0X1mod1: +lblC0mod1: OpC0X1 + NEXTOPCODE 2 + @ 18 @ 2 +OpC1M1mod1: +lblC1mod1a: DirectIndexedIndirect1 +lblC1mod1b: CMP8 + NEXTOPCODE 6 + @ 22 @ 6 +OpC2mod1: +lblC2mod1: OpC2 + NEXTOPCODE 3 + @ 19 @ 3 +.pool +OpC3M1mod1: +lblC3mod1a: StackasmRelative +lblC3mod1b: CMP8 + NEXTOPCODE 4 + @ 20 @ 4 +OpC4X1mod1: +lblC4mod1a: Direct +lblC4mod1b: CMY8 + NEXTOPCODE 3 + @ 19 @ 3 +OpC5M1mod1: +lblC5mod1a: Direct +lblC5mod1b: CMP8 + NEXTOPCODE 3 + @ 19 @ 3 +OpC6M1mod1: +lblC6mod1a: Direct +lblC6mod1b: DEC8 + NEXTOPCODE 5 + @ 21 @ 5 +OpC7M1mod1: +lblC7mod1a: DirectIndirectLong +lblC7mod1b: CMP8 + NEXTOPCODE 6 + @ 22 @ 6 +OpC8X1mod1: +lblC8mod1: OpC8X1 + NEXTOPCODE 2 + @ 10 @ 2 +OpC9M1mod1: +lblC9mod1: OpC9M1 + NEXTOPCODE 2 + @ 18 @ 2 +OpCAX1mod1: +lblCAmod1: OpCAX1 + NEXTOPCODE 2 + @ 10 @ 2 +OpCBmod1: +lblCBmod1: OpCB + NEXTOPCODE 3 + @ 11 @ 3 +OpCCX1mod1: +lblCCmod1a: Absolute +lblCCmod1b: CMY8 + NEXTOPCODE 4 + @ 28 @ 4 +OpCDM1mod1: +lblCDmod1a: Absolute +lblCDmod1b: CMP8 + NEXTOPCODE 4 + @ 28 @ 4 +OpCEM1mod1: +lblCEmod1a: Absolute +lblCEmod1b: DEC8 + NEXTOPCODE 6 + @ 30 @ 6 +OpCFM1mod1: +lblCFmod1a: AbsoluteLong +lblCFmod1b: CMP8 + NEXTOPCODE 5 + @ 37 @ 5 +OpD0mod1: +lblD0mod1: OpD0 + NEXTOPCODE 2 + @ 18 @ 2 +OpD1M1mod1: +lblD1mod1a: DirectIndirectIndexed1 +lblD1mod1b: CMP8 + NEXTOPCODE 5 + @ 21 @ 5 +OpD2M1mod1: +lblD2mod1a: DirectIndirect +lblD2mod1b: CMP8 + NEXTOPCODE 5 + @ 21 @ 5 +OpD3M1mod1: +lblD3mod1a: StackasmRelativeIndirectIndexed1 +lblD3mod1b: CMP8 + NEXTOPCODE 7 + @ 23 @ 7 +OpD4mod1: +lblD4mod1: OpD4 + NEXTOPCODE 6 + @ 22 @ 6 +OpD5M1mod1: +lblD5mod1a: DirectIndexedX1 +lblD5mod1b: CMP8 + NEXTOPCODE 4 + @ 20 @ 4 +OpD6M1mod1: +lblD6mod1a: DirectIndexedX1 +lblD6mod1b: DEC8 + NEXTOPCODE 6 + @ 22 @ 6 +OpD7M1mod1: +lblD7mod1a: DirectIndirectIndexedLong1 +lblD7mod1b: CMP8 + NEXTOPCODE 6 + @ 22 @ 6 +OpD8mod1: +lblD8mod1: OpD8 + NEXTOPCODE 2 + @ 10 @ 2 +OpD9M1mod1: +lblD9mod1a: AbsoluteIndexedY1 +lblD9mod1b: CMP8 + NEXTOPCODE 4 + @ 28 @ 4 +OpDAX1mod1: +lblDAmod1: OpDAX1 + NEXTOPCODE 3 + @ 11 @ 3 +OpDBmod1: +lblDBmod1: OpDB + NEXTOPCODE 3 + @ 11 @ 3 +OpDCmod1: +lblDCmod1: OpDC + NEXTOPCODE 6 + @ 30 @ 6 +OpDDM1mod1: +lblDDmod1a: AbsoluteIndexedX1 +lblDDmod1b: CMP8 + NEXTOPCODE 4 + @ 28 @ 4 +OpDEM1mod1: +lblDEmod1a: AbsoluteIndexedX1 +lblDEmod1b: DEC8 + NEXTOPCODE 7 + @ 31 @ 7 +OpDFM1mod1: +lblDFmod1a: AbsoluteLongIndexedX1 +lblDFmod1b: CMP8 + NEXTOPCODE 5 + @ 37 @ 5 +OpE0X1mod1: +lblE0mod1: OpE0X1 + NEXTOPCODE 2 + @ 18 @ 2 +OpE1M1mod1: +lblE1mod1a: DirectIndexedIndirect1 +lblE1mod1b: SBC8 + NEXTOPCODE 6 + @ 22 @ 6 +OpE2mod1: +lblE2mod1: OpE2 + NEXTOPCODE 3 + @ 19 @ 3 +.pool +OpE3M1mod1: +lblE3mod1a: StackasmRelative +lblE3mod1b: SBC8 + NEXTOPCODE 4 + @ 20 @ 4 +OpE4X1mod1: +lblE4mod1a: Direct +lblE4mod1b: CMX8 + NEXTOPCODE 3 + @ 19 @ 3 +OpE5M1mod1: +lblE5mod1a: Direct +lblE5mod1b: SBC8 + NEXTOPCODE 3 + @ 19 @ 3 +OpE6M1mod1: +lblE6mod1a: Direct +lblE6mod1b: INC8 + NEXTOPCODE 5 + @ 21 @ 5 +OpE7M1mod1: +lblE7mod1a: DirectIndirectLong +lblE7mod1b: SBC8 + NEXTOPCODE 6 + @ 22 @ 6 +OpE8X1mod1: +lblE8mod1: OpE8X1 + NEXTOPCODE 2 + @ 10 @ 2 +OpE9M1mod1: +lblE9mod1a: Immediate8 +lblE9mod1b: SBC8 + NEXTOPCODE 2 + @ 18 @ 2 +OpEAmod1: +lblEAmod1: OpEA + NEXTOPCODE 2 + @ 10 @ 2 +OpEBmod1: +lblEBmod1: OpEBM1 + NEXTOPCODE 3 + @ 11 @ 3 +OpECX1mod1: +lblECmod1a: Absolute +lblECmod1b: CMX8 + NEXTOPCODE 4 + @ 28 @ 4 +OpEDM1mod1: +lblEDmod1a: Absolute +lblEDmod1b: SBC8 + NEXTOPCODE 4 + @ 28 @ 4 +OpEEM1mod1: +lblEEmod1a: Absolute +lblEEmod1b: INC8 + NEXTOPCODE 6 + @ 30 @ 6 +OpEFM1mod1: +lblEFmod1a: AbsoluteLong +lblEFmod1b: SBC8 + NEXTOPCODE 5 + @ 37 @ 5 +OpF0mod1: +lblF0mod1: OpF0 + NEXTOPCODE 2 + @ 18 @ 2 +OpF1M1mod1: +lblF1mod1a: DirectIndirectIndexed1 +lblF1mod1b: SBC8 + NEXTOPCODE 5 + @ 21 @ 5 +OpF2M1mod1: +lblF2mod1a: DirectIndirect +lblF2mod1b: SBC8 + NEXTOPCODE 5 + @ 21 @ 5 +OpF3M1mod1: +lblF3mod1a: StackasmRelativeIndirectIndexed1 +lblF3mod1b: SBC8 + NEXTOPCODE 7 + @ 23 @ 7 +OpF4mod1: +lblF4mod1: OpF4 + NEXTOPCODE 5 + @ 29 @ 5 +OpF5M1mod1: +lblF5mod1a: DirectIndexedX1 +lblF5mod1b: SBC8 + NEXTOPCODE 4 + @ 20 @ 4 +OpF6M1mod1: +lblF6mod1a: DirectIndexedX1 +lblF6mod1b: INC8 + NEXTOPCODE 6 + @ 22 @ 6 +OpF7M1mod1: +lblF7mod1a: DirectIndirectIndexedLong1 +lblF7mod1b: SBC8 + NEXTOPCODE 6 + @ 22 @ 6 +OpF8mod1: +lblF8mod1: OpF8 + NEXTOPCODE 2 + @ 10 @ 2 +OpF9M1mod1: +lblF9mod1a: AbsoluteIndexedY1 +lblF9mod1b: SBC8 + NEXTOPCODE 4 + @ 28 @ 4 +OpFAX1mod1: +lblFAmod1: OpFAX1 + NEXTOPCODE 4 + @ 12 @ 4 +OpFBmod1: +lblFBmod1: OpFB + NEXTOPCODE 2 + @ 10 @ 2 +OpFCmod1: +lblFCmod1: OpFCX1 + NEXTOPCODE 6 + @ 30 @ 6 +OpFDM1mod1: +lblFDmod1a: AbsoluteIndexedX1 +lblFDmod1b: SBC8 + NEXTOPCODE 4 + @ 28 @ 4 +OpFEM1mod1: +lblFEmod1a: AbsoluteIndexedX1 +lblFEmod1b: INC8 + NEXTOPCODE 7 + @ 31 @ 7 +OpFFM1mod1: +lblFFmod1a: AbsoluteLongIndexedX1 +lblFFmod1b: SBC8 + NEXTOPCODE 5 + @ 37 @ 5 +.pool + + +jumptable2: .long Op00mod2 + .long Op01M1mod2 + .long Op02mod2 + .long Op03M1mod2 + .long Op04M1mod2 + .long Op05M1mod2 + .long Op06M1mod2 + .long Op07M1mod2 + .long Op08mod2 + .long Op09M1mod2 + .long Op0AM1mod2 + .long Op0Bmod2 + .long Op0CM1mod2 + .long Op0DM1mod2 + .long Op0EM1mod2 + .long Op0FM1mod2 + .long Op10mod2 + .long Op11M1mod2 + .long Op12M1mod2 + .long Op13M1mod2 + .long Op14M1mod2 + .long Op15M1mod2 + .long Op16M1mod2 + .long Op17M1mod2 + .long Op18mod2 + .long Op19M1mod2 + .long Op1AM1mod2 + .long Op1Bmod2 + .long Op1CM1mod2 + .long Op1DM1mod2 + .long Op1EM1mod2 + .long Op1FM1mod2 + .long Op20mod2 + .long Op21M1mod2 + .long Op22mod2 + .long Op23M1mod2 + .long Op24M1mod2 + .long Op25M1mod2 + .long Op26M1mod2 + .long Op27M1mod2 + .long Op28mod2 + .long Op29M1mod2 + .long Op2AM1mod2 + .long Op2Bmod2 + .long Op2CM1mod2 + .long Op2DM1mod2 + .long Op2EM1mod2 + .long Op2FM1mod2 + .long Op30mod2 + .long Op31M1mod2 + .long Op32M1mod2 + .long Op33M1mod2 + .long Op34M1mod2 + .long Op35M1mod2 + .long Op36M1mod2 + .long Op37M1mod2 + .long Op38mod2 + .long Op39M1mod2 + .long Op3AM1mod2 + .long Op3Bmod2 + .long Op3CM1mod2 + .long Op3DM1mod2 + .long Op3EM1mod2 + .long Op3FM1mod2 + .long Op40mod2 + .long Op41M1mod2 + .long Op42mod2 + .long Op43M1mod2 + .long Op44X0mod2 + .long Op45M1mod2 + .long Op46M1mod2 + .long Op47M1mod2 + .long Op48M1mod2 + .long Op49M1mod2 + .long Op4AM1mod2 + .long Op4Bmod2 + .long Op4Cmod2 + .long Op4DM1mod2 + .long Op4EM1mod2 + .long Op4FM1mod2 + .long Op50mod2 + .long Op51M1mod2 + .long Op52M1mod2 + .long Op53M1mod2 + .long Op54X0mod2 + .long Op55M1mod2 + .long Op56M1mod2 + .long Op57M1mod2 + .long Op58mod2 + .long Op59M1mod2 + .long Op5AX0mod2 + .long Op5Bmod2 + .long Op5Cmod2 + .long Op5DM1mod2 + .long Op5EM1mod2 + .long Op5FM1mod2 + .long Op60mod2 + .long Op61M1mod2 + .long Op62mod2 + .long Op63M1mod2 + .long Op64M1mod2 + .long Op65M1mod2 + .long Op66M1mod2 + .long Op67M1mod2 + .long Op68M1mod2 + .long Op69M1mod2 + .long Op6AM1mod2 + .long Op6Bmod2 + .long Op6Cmod2 + .long Op6DM1mod2 + .long Op6EM1mod2 + .long Op6FM1mod2 + .long Op70mod2 + .long Op71M1mod2 + .long Op72M1mod2 + .long Op73M1mod2 + .long Op74M1mod2 + .long Op75M1mod2 + .long Op76M1mod2 + .long Op77M1mod2 + .long Op78mod2 + .long Op79M1mod2 + .long Op7AX0mod2 + .long Op7Bmod2 + .long Op7Cmod2 + .long Op7DM1mod2 + .long Op7EM1mod2 + .long Op7FM1mod2 + .long Op80mod2 + .long Op81M1mod2 + .long Op82mod2 + .long Op83M1mod2 + .long Op84X0mod2 + .long Op85M1mod2 + .long Op86X0mod2 + .long Op87M1mod2 + .long Op88X0mod2 + .long Op89M1mod2 + .long Op8AM1mod2 + .long Op8Bmod2 + .long Op8CX0mod2 + .long Op8DM1mod2 + .long Op8EX0mod2 + .long Op8FM1mod2 + .long Op90mod2 + .long Op91M1mod2 + .long Op92M1mod2 + .long Op93M1mod2 + .long Op94X0mod2 + .long Op95M1mod2 + .long Op96X0mod2 + .long Op97M1mod2 + .long Op98M1mod2 + .long Op99M1mod2 + .long Op9Amod2 + .long Op9BX0mod2 + .long Op9CM1mod2 + .long Op9DM1mod2 + .long Op9EM1mod2 + .long Op9FM1mod2 + .long OpA0X0mod2 + .long OpA1M1mod2 + .long OpA2X0mod2 + .long OpA3M1mod2 + .long OpA4X0mod2 + .long OpA5M1mod2 + .long OpA6X0mod2 + .long OpA7M1mod2 + .long OpA8X0mod2 + .long OpA9M1mod2 + .long OpAAX0mod2 + .long OpABmod2 + .long OpACX0mod2 + .long OpADM1mod2 + .long OpAEX0mod2 + .long OpAFM1mod2 + .long OpB0mod2 + .long OpB1M1mod2 + .long OpB2M1mod2 + .long OpB3M1mod2 + .long OpB4X0mod2 + .long OpB5M1mod2 + .long OpB6X0mod2 + .long OpB7M1mod2 + .long OpB8mod2 + .long OpB9M1mod2 + .long OpBAX0mod2 + .long OpBBX0mod2 + .long OpBCX0mod2 + .long OpBDM1mod2 + .long OpBEX0mod2 + .long OpBFM1mod2 + .long OpC0X0mod2 + .long OpC1M1mod2 + .long OpC2mod2 + .long OpC3M1mod2 + .long OpC4X0mod2 + .long OpC5M1mod2 + .long OpC6M1mod2 + .long OpC7M1mod2 + .long OpC8X0mod2 + .long OpC9M1mod2 + .long OpCAX0mod2 + .long OpCBmod2 + .long OpCCX0mod2 + .long OpCDM1mod2 + .long OpCEM1mod2 + .long OpCFM1mod2 + .long OpD0mod2 + .long OpD1M1mod2 + .long OpD2M1mod2 + .long OpD3M1mod2 + .long OpD4mod2 + .long OpD5M1mod2 + .long OpD6M1mod2 + .long OpD7M1mod2 + .long OpD8mod2 + .long OpD9M1mod2 + .long OpDAX0mod2 + .long OpDBmod2 + .long OpDCmod2 + .long OpDDM1mod2 + .long OpDEM1mod2 + .long OpDFM1mod2 + .long OpE0X0mod2 + .long OpE1M1mod2 + .long OpE2mod2 + .long OpE3M1mod2 + .long OpE4X0mod2 + .long OpE5M1mod2 + .long OpE6M1mod2 + .long OpE7M1mod2 + .long OpE8X0mod2 + .long OpE9M1mod2 + .long OpEAmod2 + .long OpEBmod2 + .long OpECX0mod2 + .long OpEDM1mod2 + .long OpEEM1mod2 + .long OpEFM1mod2 + .long OpF0mod2 + .long OpF1M1mod2 + .long OpF2M1mod2 + .long OpF3M1mod2 + .long OpF4mod2 + .long OpF5M1mod2 + .long OpF6M1mod2 + .long OpF7M1mod2 + .long OpF8mod2 + .long OpF9M1mod2 + .long OpFAX0mod2 + .long OpFBmod2 + .long OpFCmod2 + .long OpFDM1mod2 + .long OpFEM1mod2 + .long OpFFM1mod2 +Op00mod2: +lbl00mod2: Op00 + NEXTOPCODE 8 + @ 24 @ 8 +Op01M1mod2: +lbl01mod2a: DirectIndexedIndirect0 +lbl01mod2b: ORA8 + NEXTOPCODE 6 + @ 22 @ 7 +Op02mod2: +lbl02mod2: Op02 + NEXTOPCODE 8 + @ 24 @ 8 +Op03M1mod2: +lbl03mod2a: StackasmRelative +lbl03mod2b: ORA8 + NEXTOPCODE 4 + @ 20 @ 5 +Op04M1mod2: +lbl04mod2a: Direct +lbl04mod2b: TSB8 + NEXTOPCODE 5 + @ 21 @ 7 +Op05M1mod2: +lbl05mod2a: Direct +lbl05mod2b: ORA8 + NEXTOPCODE 3 + @ 19 @ 4 +Op06M1mod2: +lbl06mod2a: Direct +lbl06mod2b: ASL8 + NEXTOPCODE 5 + @ 21 @ 7 +Op07M1mod2: +lbl07mod2a: DirectIndirectLong +lbl07mod2b: ORA8 + NEXTOPCODE 6 + @ 22 @ 7 +Op08mod2: +lbl08mod2: Op08 + NEXTOPCODE 3 + @ 11 @ 3 +Op09M1mod2: +lbl09mod2: Op09M1 + NEXTOPCODE 2 + @ 18 @ 3 +Op0AM1mod2: +lbl0Amod2a: A_ASL8 + NEXTOPCODE 2 + @ 10 @ 2 +Op0Bmod2: +lbl0Bmod2: Op0B + NEXTOPCODE 4 + @ 12 @ 4 +Op0CM1mod2: +lbl0Cmod2a: Absolute +lbl0Cmod2b: TSB8 + NEXTOPCODE 6 + @ 30 @ 8 +Op0DM1mod2: +lbl0Dmod2a: Absolute +lbl0Dmod2b: ORA8 + NEXTOPCODE 4 + @ 28 @ 5 +Op0EM1mod2: +lbl0Emod2a: Absolute +lbl0Emod2b: ASL8 + NEXTOPCODE 6 + @ 30 @ 8 +Op0FM1mod2: +lbl0Fmod2a: AbsoluteLong +lbl0Fmod2b: ORA8 + NEXTOPCODE 5 + @ 37 @ 6 +Op10mod2: +lbl10mod2: Op10 + NEXTOPCODE 2 + @ 18 @ 2 +Op11M1mod2: +lbl11mod2a: DirectIndirectIndexed0 +lbl11mod2b: ORA8 + NEXTOPCODE 6 + @ 22 @ 6 +Op12M1mod2: +lbl12mod2a: DirectIndirect +lbl12mod2b: ORA8 + NEXTOPCODE 5 + @ 21 @ 6 +Op13M1mod2: +lbl13mod2a: StackasmRelativeIndirectIndexed0 +lbl13mod2b: ORA8 + NEXTOPCODE 7 + @ 23 @ 8 +Op14M1mod2: +lbl14mod2a: Direct +lbl14mod2b: TRB8 + NEXTOPCODE 5 + @ 21 @ 7 +Op15M1mod2: +lbl15mod2a: DirectIndexedX0 +lbl15mod2b: ORA8 + NEXTOPCODE 4 + @ 20 @ 5 +Op16M1mod2: +lbl16mod2a: DirectIndexedX0 +lbl16mod2b: ASL8 + NEXTOPCODE 6 + @ 22 @ 8 +Op17M1mod2: +lbl17mod2a: DirectIndirectIndexedLong0 +lbl17mod2b: ORA8 + NEXTOPCODE 6 + @ 22 @ 7 +Op18mod2: +lbl18mod2: Op18 + NEXTOPCODE 2 + @ 10 @ 2 +Op19M1mod2: +lbl19mod2a: AbsoluteIndexedY0 +lbl19mod2b: ORA8 + NEXTOPCODE 5 + @ 29 @ 5 +Op1AM1mod2: +lbl1Amod2a: A_INC8 + NEXTOPCODE 2 + @ 10 @ 2 +Op1Bmod2: +lbl1Bmod2: Op1BM1 + NEXTOPCODE 2 + @ 10 @ 2 +Op1CM1mod2: +lbl1Cmod2a: Absolute +lbl1Cmod2b: TRB8 + NEXTOPCODE 6 + @ 30 @ 8 +Op1DM1mod2: +lbl1Dmod2a: AbsoluteIndexedX0 +lbl1Dmod2b: ORA8 + NEXTOPCODE 5 + @ 29 @ 5 +Op1EM1mod2: +lbl1Emod2a: AbsoluteIndexedX0 +lbl1Emod2b: ASL8 + NEXTOPCODE 7 + @ 31 @ 9 +Op1FM1mod2: +lbl1Fmod2a: AbsoluteLongIndexedX0 +lbl1Fmod2b: ORA8 + NEXTOPCODE 5 + @ 37 @ 6 +Op20mod2: +lbl20mod2: Op20 + NEXTOPCODE 6 + @ 30 @ 6 +Op21M1mod2: +lbl21mod2a: DirectIndexedIndirect0 +lbl21mod2b: AND8 + NEXTOPCODE 6 + @ 22 @ 7 +Op22mod2: +lbl22mod2: Op22 + NEXTOPCODE 8 + @ 40 @ 8 +Op23M1mod2: +lbl23mod2a: StackasmRelative +lbl23mod2b: AND8 + NEXTOPCODE 4 + @ 20 @ 5 +Op24M1mod2: +lbl24mod2a: Direct +lbl24mod2b: BIT8 + NEXTOPCODE 3 + @ 19 @ 4 +Op25M1mod2: +lbl25mod2a: Direct +lbl25mod2b: AND8 + NEXTOPCODE 3 + @ 19 @ 4 +Op26M1mod2: +lbl26mod2a: Direct +lbl26mod2b: ROL8 + NEXTOPCODE 5 + @ 21 @ 7 +Op27M1mod2: +lbl27mod2a: DirectIndirectLong +lbl27mod2b: AND8 + NEXTOPCODE 6 + @ 22 @ 7 +Op28mod2: +lbl28mod2: Op28X0M1 + NEXTOPCODE 4 + @ 12 @ 4 +.pool +Op29M1mod2: +lbl29mod2: Op29M1 + NEXTOPCODE 2 + @ 18 @ 3 +Op2AM1mod2: +lbl2Amod2a: A_ROL8 + NEXTOPCODE 2 + @ 10 @ 2 +Op2Bmod2: +lbl2Bmod2: Op2B + NEXTOPCODE 5 + @ 13 @ 5 +Op2CM1mod2: +lbl2Cmod2a: Absolute +lbl2Cmod2b: BIT8 + NEXTOPCODE 4 + @ 28 @ 5 +Op2DM1mod2: +lbl2Dmod2a: Absolute +lbl2Dmod2b: AND8 + NEXTOPCODE 4 + @ 28 @ 5 +Op2EM1mod2: +lbl2Emod2a: Absolute +lbl2Emod2b: ROL8 + NEXTOPCODE 6 + @ 30 @ 8 +Op2FM1mod2: +lbl2Fmod2a: AbsoluteLong +lbl2Fmod2b: AND8 + NEXTOPCODE 5 + @ 37 @ 6 +Op30mod2: +lbl30mod2: Op30 + NEXTOPCODE 2 + @ 18 @ 2 +Op31M1mod2: +lbl31mod2a: DirectIndirectIndexed0 +lbl31mod2b: AND8 + NEXTOPCODE 6 + @ 22 @ 6 +Op32M1mod2: +lbl32mod2a: DirectIndirect +lbl32mod2b: AND8 + NEXTOPCODE 5 + @ 21 @ 6 +Op33M1mod2: +lbl33mod2a: StackasmRelativeIndirectIndexed0 +lbl33mod2b: AND8 + NEXTOPCODE 7 + @ 23 @ 8 +Op34M1mod2: +lbl34mod2a: DirectIndexedX0 +lbl34mod2b: BIT8 + NEXTOPCODE 4 + @ 20 @ 5 +Op35M1mod2: +lbl35mod2a: DirectIndexedX0 +lbl35mod2b: AND8 + NEXTOPCODE 4 + @ 20 @ 5 +Op36M1mod2: +lbl36mod2a: DirectIndexedX0 +lbl36mod2b: ROL8 + NEXTOPCODE 6 + @ 22 @ 8 +Op37M1mod2: +lbl37mod2a: DirectIndirectIndexedLong0 +lbl37mod2b: AND8 + NEXTOPCODE 6 + @ 22 @ 7 +Op38mod2: +lbl38mod2: Op38 + NEXTOPCODE 2 + @ 10 @ 2 +Op39M1mod2: +lbl39mod2a: AbsoluteIndexedY0 +lbl39mod2b: AND8 + NEXTOPCODE 5 + @ 29 @ 5 +Op3AM1mod2: +lbl3Amod2a: A_DEC8 + NEXTOPCODE 2 + @ 10 @ 2 +Op3Bmod2: +lbl3Bmod2: Op3BM1 + NEXTOPCODE 2 + @ 10 @ 2 +Op3CM1mod2: +lbl3Cmod2a: AbsoluteIndexedX0 +lbl3Cmod2b: BIT8 + NEXTOPCODE 5 + @ 29 @ 5 +Op3DM1mod2: +lbl3Dmod2a: AbsoluteIndexedX0 +lbl3Dmod2b: AND8 + NEXTOPCODE 5 + @ 29 @ 5 +Op3EM1mod2: +lbl3Emod2a: AbsoluteIndexedX0 +lbl3Emod2b: ROL8 + NEXTOPCODE 7 + @ 31 @ 9 +Op3FM1mod2: +lbl3Fmod2a: AbsoluteLongIndexedX0 +lbl3Fmod2b: AND8 + NEXTOPCODE 5 + @ 37 @ 6 +Op40mod2: +lbl40mod2: Op40X0M1 + NEXTOPCODE 7 + @ 15 @ 7 +.pool +Op41M1mod2: +lbl41mod2a: DirectIndexedIndirect0 +lbl41mod2b: EOR8 + NEXTOPCODE 6 + @ 22 @ 7 +Op42mod2: +lbl42mod2: Op42 + NEXTOPCODE 2 + @ 18 @ 2 +Op43M1mod2: +lbl43mod2a: StackasmRelative +lbl43mod2b: EOR8 + NEXTOPCODE 4 + @ 20 @ 5 +Op44X0mod2: +lbl44mod2: Op44X0M1 + NEXTOPCODE 0 + @ 24 @ 0 +Op45M1mod2: +lbl45mod2a: Direct +lbl45mod2b: EOR8 + NEXTOPCODE 3 + @ 19 @ 4 +Op46M1mod2: +lbl46mod2a: Direct +lbl46mod2b: LSR8 + NEXTOPCODE 5 + @ 21 @ 7 +Op47M1mod2: +lbl47mod2a: DirectIndirectLong +lbl47mod2b: EOR8 + NEXTOPCODE 6 + @ 22 @ 7 +Op48M1mod2: +lbl48mod2: Op48M1 + NEXTOPCODE 4 + @ 12 @ 4 +Op49M1mod2: +lbl49mod2: Op49M1 + NEXTOPCODE 2 + @ 18 @ 3 +Op4AM1mod2: +lbl4Amod2a: A_LSR8 + NEXTOPCODE 2 + @ 10 @ 2 +Op4Bmod2: +lbl4Bmod2: Op4B + NEXTOPCODE 3 + @ 11 @ 3 +Op4Cmod2: + +lbl4Cmod2: Op4C + NEXTOPCODE 3 + @ 27 @ 3 +Op4DM1mod2: +lbl4Dmod2a: Absolute +lbl4Dmod2b: EOR8 + NEXTOPCODE 4 + @ 28 @ 5 +Op4EM1mod2: +lbl4Emod2a: Absolute +lbl4Emod2b: LSR8 + NEXTOPCODE 6 + @ 30 @ 8 +Op4FM1mod2: +lbl4Fmod2a: AbsoluteLong +lbl4Fmod2b: EOR8 + NEXTOPCODE 5 + @ 37 @ 6 +Op50mod2: +lbl50mod2: Op50 + NEXTOPCODE 2 + @ 18 @ 2 +Op51M1mod2: +lbl51mod2a: DirectIndirectIndexed0 +lbl51mod2b: EOR8 + NEXTOPCODE 6 + @ 22 @ 6 +Op52M1mod2: +lbl52mod2a: DirectIndirect +lbl52mod2b: EOR8 + NEXTOPCODE 5 + @ 21 @ 6 +Op53M1mod2: +lbl53mod2a: StackasmRelativeIndirectIndexed0 +lbl53mod2b: EOR8 + NEXTOPCODE 7 + @ 23 @ 8 +Op54X0mod2: +lbl54mod2: Op54X0M1 + NEXTOPCODE 0 + @ 24 @ 0 +Op55M1mod2: +lbl55mod2a: DirectIndexedX0 +lbl55mod2b: EOR8 + NEXTOPCODE 4 + @ 20 @ 5 +Op56M1mod2: +lbl56mod2a: DirectIndexedX0 +lbl56mod2b: LSR8 + NEXTOPCODE 6 + @ 22 @ 8 +Op57M1mod2: +lbl57mod2a: DirectIndirectIndexedLong0 +lbl57mod2b: EOR8 + NEXTOPCODE 6 + @ 22 @ 7 +Op58mod2: +lbl58mod2: Op58 + NEXTOPCODE 2 + @ 10 @ 2 +Op59M1mod2: +lbl59mod2a: AbsoluteIndexedY0 +lbl59mod2b: EOR8 + NEXTOPCODE 5 + @ 29 @ 5 +Op5AX0mod2: +lbl5Amod2: Op5AX0 + NEXTOPCODE 4 + @ 12 @ 3 +Op5Bmod2: +lbl5Bmod2: Op5BM1 + NEXTOPCODE 2 + @ 10 @ 2 +Op5Cmod2: +lbl5Cmod2: Op5C + NEXTOPCODE 4 + @ 36 @ 4 +Op5DM1mod2: +lbl5Dmod2a: AbsoluteIndexedX0 +lbl5Dmod2b: EOR8 + NEXTOPCODE 5 + @ 29 @ 5 +Op5EM1mod2: +lbl5Emod2a: AbsoluteIndexedX0 +lbl5Emod2b: LSR8 + NEXTOPCODE 7 + @ 31 @ 9 +Op5FM1mod2: +lbl5Fmod2a: AbsoluteLongIndexedX0 +lbl5Fmod2b: EOR8 + NEXTOPCODE 5 + @ 37 @ 6 +Op60mod2: +lbl60mod2: Op60 + NEXTOPCODE 6 + @ 14 @ 6 +Op61M1mod2: +lbl61mod2a: DirectIndexedIndirect0 +lbl61mod2b: ADC8 + NEXTOPCODE 6 + @ 22 @ 7 +Op62mod2: +lbl62mod2: Op62 + NEXTOPCODE 6 + @ 30 @ 6 +Op63M1mod2: +lbl63mod2a: StackasmRelative +lbl63mod2b: ADC8 + NEXTOPCODE 4 + @ 20 @ 5 +Op64M1mod2: +lbl64mod2a: Direct +lbl64mod2b: STZ8 + NEXTOPCODE 3 + @ 19 @ 4 +Op65M1mod2: +lbl65mod2a: Direct +lbl65mod2b: ADC8 + NEXTOPCODE 3 + @ 19 @ 4 +Op66M1mod2: +lbl66mod2a: Direct +lbl66mod2b: ROR8 + NEXTOPCODE 5 + @ 21 @ 7 +Op67M1mod2: +lbl67mod2a: DirectIndirectLong +lbl67mod2b: ADC8 + NEXTOPCODE 6 + @ 22 @ 7 +Op68M1mod2: +lbl68mod2: Op68M1 + NEXTOPCODE 5 + @ 13 @ 5 +Op69M1mod2: +lbl69mod2a: Immediate8 +lbl69mod2b: ADC8 + NEXTOPCODE 2 + @ 18 @ 3 +Op6AM1mod2: +lbl6Amod2a: A_ROR8 + NEXTOPCODE 2 + @ 10 @ 2 +Op6Bmod2: +lbl6Bmod2: Op6B + NEXTOPCODE 6 + @ 14 @ 6 +Op6Cmod2: +lbl6Cmod2: Op6C + NEXTOPCODE 5 + @ 29 @ 5 +Op6DM1mod2: +lbl6Dmod2a: Absolute +lbl6Dmod2b: ADC8 + NEXTOPCODE 4 + @ 28 @ 5 +Op6EM1mod2: +lbl6Emod2a: Absolute +lbl6Emod2b: ROR8 + NEXTOPCODE 6 + @ 30 @ 8 +Op6FM1mod2: +lbl6Fmod2a: AbsoluteLong +lbl6Fmod2b: ADC8 + NEXTOPCODE 5 + @ 37 @ 6 +Op70mod2: +lbl70mod2: Op70 + NEXTOPCODE 2 + @ 18 @ 2 +Op71M1mod2: +lbl71mod2a: DirectIndirectIndexed0 +lbl71mod2b: ADC8 + NEXTOPCODE 6 + @ 22 @ 6 +Op72M1mod2: +lbl72mod2a: DirectIndirect +lbl72mod2b: ADC8 + NEXTOPCODE 5 + @ 21 @ 6 +Op73M1mod2: +lbl73mod2a: StackasmRelativeIndirectIndexed0 +lbl73mod2b: ADC8 + NEXTOPCODE 7 + @ 23 @ 8 +Op74M1mod2: +lbl74mod2a: DirectIndexedX0 +lbl74mod2b: STZ8 + NEXTOPCODE 4 + @ 20 @ 5 +Op75M1mod2: +lbl75mod2a: DirectIndexedX0 +lbl75mod2b: ADC8 + NEXTOPCODE 4 + @ 20 @ 5 +Op76M1mod2: +lbl76mod2a: DirectIndexedX0 +lbl76mod2b: ROR8 + NEXTOPCODE 6 + @ 22 @ 8 +Op77M1mod2: +lbl77mod2a: DirectIndirectIndexedLong0 +lbl77mod2b: ADC8 + NEXTOPCODE 6 + @ 22 @ 7 +Op78mod2: +lbl78mod2: Op78 + NEXTOPCODE 2 + @ 10 @ 2 +Op79M1mod2: +lbl79mod2a: AbsoluteIndexedY0 +lbl79mod2b: ADC8 + NEXTOPCODE 5 + @ 29 @ 5 +Op7AX0mod2: +lbl7Amod2: Op7AX0 + NEXTOPCODE 5 + @ 13 @ 4 +Op7Bmod2: +lbl7Bmod2: Op7BM1 + NEXTOPCODE 2 + @ 10 @ 2 +Op7Cmod2: +lbl7Cmod2: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE 6 + @ 30 @ 6 +Op7DM1mod2: +lbl7Dmod2a: AbsoluteIndexedX0 +lbl7Dmod2b: ADC8 + NEXTOPCODE 5 + @ 29 @ 5 +Op7EM1mod2: +lbl7Emod2a: AbsoluteIndexedX0 +lbl7Emod2b: ROR8 + NEXTOPCODE 7 + @ 31 @ 9 +Op7FM1mod2: +lbl7Fmod2a: AbsoluteLongIndexedX0 +lbl7Fmod2b: ADC8 + NEXTOPCODE 5 + @ 37 @ 6 + + +Op80mod2: +lbl80mod2: Op80 + NEXTOPCODE 2 + @ 18 @ 2 +Op81M1mod2: +lbl81mod2a: DirectIndexedIndirect0 +lbl81mod2b: Op81M1 + NEXTOPCODE 6 + @ 22 @ 7 +Op82mod2: +lbl82mod2: Op82 + NEXTOPCODE 3 + @ 27 @ 3 +Op83M1mod2: +lbl83mod2a: StackasmRelative +lbl83mod2b: STA8 + NEXTOPCODE 4 + @ 20 @ 5 +Op84X0mod2: +lbl84mod2a: Direct +lbl84mod2b: STY16 + NEXTOPCODE 4 + @ 20 @ 3 +Op85M1mod2: +lbl85mod2a: Direct +lbl85mod2b: STA8 + + NEXTOPCODE 3 + @ 19 @ 4 +Op86X0mod2: +lbl86mod2a: Direct +lbl86mod2b: STX16 + NEXTOPCODE 4 + @ 20 @ 3 +Op87M1mod2: +lbl87mod2a: DirectIndirectLong +lbl87mod2b: STA8 + NEXTOPCODE 6 + @ 22 @ 7 +Op88X0mod2: +lbl88mod2: Op88X0 + NEXTOPCODE 2 + @ 10 @ 2 +Op89M1mod2: +lbl89mod2: Op89M1 + NEXTOPCODE 2 + @ 18 @ 3 +Op8AM1mod2: +lbl8Amod2: Op8AM1X0 + NEXTOPCODE 2 + @ 10 @ 2 +Op8Bmod2: +lbl8Bmod2: Op8B + NEXTOPCODE 3 + @ 11 @ 3 +Op8CX0mod2: +lbl8Cmod2a: Absolute +lbl8Cmod2b: STY16 + NEXTOPCODE 5 + @ 29 @ 4 +Op8DM1mod2: +lbl8Dmod2a: Absolute +lbl8Dmod2b: STA8 + NEXTOPCODE 4 + @ 28 @ 5 +Op8EX0mod2: +lbl8Emod2a: Absolute +lbl8Emod2b: STX16 + NEXTOPCODE 5 + @ 29 @ 4 +Op8FM1mod2: +lbl8Fmod2a: AbsoluteLong +lbl8Fmod2b: STA8 + NEXTOPCODE 5 + @ 37 @ 6 +Op90mod2: +lbl90mod2: Op90 + NEXTOPCODE 2 + @ 18 @ 2 +Op91M1mod2: +lbl91mod2a: DirectIndirectIndexed0 +lbl91mod2b: STA8 + NEXTOPCODE 6 + @ 22 @ 6 +Op92M1mod2: +lbl92mod2a: DirectIndirect +lbl92mod2b: STA8 + NEXTOPCODE 5 + @ 21 @ 6 +Op93M1mod2: +lbl93mod2a: StackasmRelativeIndirectIndexed0 +lbl93mod2b: STA8 + NEXTOPCODE 7 + @ 23 @ 8 +Op94X0mod2: +lbl94mod2a: DirectIndexedX0 +lbl94mod2b: STY16 + NEXTOPCODE 5 + @ 21 @ 4 +Op95M1mod2: + +lbl95mod2a: DirectIndexedX0 +lbl95mod2b: STA8 + NEXTOPCODE 4 + @ 20 @ 5 +Op96X0mod2: +lbl96mod2a: DirectIndexedY0 +lbl96mod2b: STX16 + NEXTOPCODE 5 + @ 21 @ 4 +Op97M1mod2: +lbl97mod2a: DirectIndirectIndexedLong0 +lbl97mod2b: STA8 + NEXTOPCODE 6 + @ 22 @ 7 +Op98M1mod2: +lbl98mod2: Op98M1X0 + NEXTOPCODE 2 + @ 10 @ 2 +Op99M1mod2: +lbl99mod2a: AbsoluteIndexedY0 +lbl99mod2b: STA8 + NEXTOPCODE 5 + @ 29 @ 5 +Op9Amod2: +lbl9Amod2: Op9AX0 + NEXTOPCODE 2 + @ 10 @ 2 +Op9BX0mod2: +lbl9Bmod2: Op9BX0 + NEXTOPCODE 2 + @ 10 @ 2 +Op9CM1mod2: +lbl9Cmod2a: Absolute +lbl9Cmod2b: STZ8 + NEXTOPCODE 4 + @ 28 @ 5 +Op9DM1mod2: +lbl9Dmod2a: AbsoluteIndexedX0 +lbl9Dmod2b: STA8 + NEXTOPCODE 5 + @ 29 @ 5 +Op9EM1mod2: +lbl9Emod2: AbsoluteIndexedX0 + STZ8 + NEXTOPCODE 5 + @ 29 @ 5 +Op9FM1mod2: +lbl9Fmod2a: AbsoluteLongIndexedX0 +lbl9Fmod2b: STA8 + NEXTOPCODE 5 + @ 37 @ 6 +OpA0X0mod2: +lblA0mod2: OpA0X0 + NEXTOPCODE 3 + @ 19 @ 2 +OpA1M1mod2: +lblA1mod2a: DirectIndexedIndirect0 +lblA1mod2b: LDA8 + NEXTOPCODE 6 + @ 22 @ 7 +OpA2X0mod2: +lblA2mod2: OpA2X0 + NEXTOPCODE 3 + @ 19 @ 2 +OpA3M1mod2: +lblA3mod2a: StackasmRelative +lblA3mod2b: LDA8 + NEXTOPCODE 4 + @ 20 @ 5 +OpA4X0mod2: +lblA4mod2a: Direct +lblA4mod2b: LDY16 + NEXTOPCODE 4 + @ 20 @ 3 +OpA5M1mod2: +lblA5mod2a: Direct +lblA5mod2b: LDA8 + NEXTOPCODE 3 + @ 19 @ 4 +OpA6X0mod2: +lblA6mod2a: Direct +lblA6mod2b: LDX16 + NEXTOPCODE 4 + @ 20 @ 3 +OpA7M1mod2: +lblA7mod2a: DirectIndirectLong +lblA7mod2b: LDA8 + NEXTOPCODE 6 + @ 22 @ 7 +OpA8X0mod2: +lblA8mod2: OpA8X0M1 + NEXTOPCODE 2 + @ 10 @ 2 +OpA9M1mod2: +lblA9mod2: OpA9M1 + NEXTOPCODE 2 + @ 18 @ 3 +OpAAX0mod2: +lblAAmod2: OpAAX0M1 + NEXTOPCODE 2 + @ 10 @ 2 +OpABmod2: +lblABmod2: OpAB + NEXTOPCODE 4 + @ 12 @ 4 +OpACX0mod2: +lblACmod2a: Absolute +lblACmod2b: LDY16 + NEXTOPCODE 5 + @ 29 @ 4 +OpADM1mod2: +lblADmod2a: Absolute +lblADmod2b: LDA8 + NEXTOPCODE 4 + @ 28 @ 5 +OpAEX0mod2: +lblAEmod2a: Absolute +lblAEmod2b: LDX16 + NEXTOPCODE 5 + @ 29 @ 4 +OpAFM1mod2: +lblAFmod2a: AbsoluteLong +lblAFmod2b: LDA8 + NEXTOPCODE 5 + @ 37 @ 6 +OpB0mod2: +lblB0mod2: OpB0 + NEXTOPCODE 2 + @ 18 @ 2 +OpB1M1mod2: +lblB1mod2a: DirectIndirectIndexed0 +lblB1mod2b: LDA8 + NEXTOPCODE 6 + @ 22 @ 6 +OpB2M1mod2: +lblB2mod2a: DirectIndirect +lblB2mod2b: LDA8 + NEXTOPCODE 5 + @ 21 @ 6 +OpB3M1mod2: +lblB3mod2a: StackasmRelativeIndirectIndexed0 +lblB3mod2b: LDA8 + NEXTOPCODE 7 + @ 23 @ 8 +OpB4X0mod2: +lblB4mod2a: DirectIndexedX0 +lblB4mod2b: LDY16 + NEXTOPCODE 5 + @ 21 @ 4 +OpB5M1mod2: +lblB5mod2a: DirectIndexedX0 +lblB5mod2b: LDA8 + NEXTOPCODE 4 + @ 20 @ 5 +OpB6X0mod2: +lblB6mod2a: DirectIndexedY0 +lblB6mod2b: LDX16 + NEXTOPCODE 5 + @ 21 @ 4 +OpB7M1mod2: +lblB7mod2a: DirectIndirectIndexedLong0 +lblB7mod2b: LDA8 + NEXTOPCODE 6 + @ 22 @ 7 +OpB8mod2: +lblB8mod2: OpB8 + NEXTOPCODE 2 + @ 10 @ 2 +OpB9M1mod2: +lblB9mod2a: AbsoluteIndexedY0 +lblB9mod2b: LDA8 + NEXTOPCODE 5 + @ 29 @ 5 +OpBAX0mod2: +lblBAmod2: OpBAX0 + NEXTOPCODE 2 + @ 10 @ 2 +OpBBX0mod2: +lblBBmod2: OpBBX0 + NEXTOPCODE 2 + @ 10 @ 2 +OpBCX0mod2: +lblBCmod2a: AbsoluteIndexedX0 +lblBCmod2b: LDY16 + NEXTOPCODE 5 + @ 29 @ 4 +OpBDM1mod2: +lblBDmod2a: AbsoluteIndexedX0 +lblBDmod2b: LDA8 + NEXTOPCODE 5 + @ 29 @ 5 +OpBEX0mod2: +lblBEmod2a: AbsoluteIndexedY0 +lblBEmod2b: LDX16 + NEXTOPCODE 5 + @ 29 @ 4 +OpBFM1mod2: +lblBFmod2a: AbsoluteLongIndexedX0 +lblBFmod2b: LDA8 + NEXTOPCODE 5 + @ 37 @ 6 +OpC0X0mod2: +lblC0mod2: OpC0X0 + NEXTOPCODE 3 + @ 19 @ 2 +OpC1M1mod2: +lblC1mod2a: DirectIndexedIndirect0 +lblC1mod2b: CMP8 + NEXTOPCODE 6 + @ 22 @ 7 +OpC2mod2: +lblC2mod2: OpC2 + NEXTOPCODE 3 + @ 19 @ 3 +.pool +OpC3M1mod2: +lblC3mod2a: StackasmRelative +lblC3mod2b: CMP8 + NEXTOPCODE 4 + @ 20 @ 5 +OpC4X0mod2: +lblC4mod2a: Direct +lblC4mod2b: CMY16 + NEXTOPCODE 4 + @ 20 @ 3 +OpC5M1mod2: +lblC5mod2a: Direct +lblC5mod2b: CMP8 + NEXTOPCODE 3 + @ 19 @ 4 +OpC6M1mod2: +lblC6mod2a: Direct +lblC6mod2b: DEC8 + NEXTOPCODE 6 + @ 22 @ 7 +OpC7M1mod2: +lblC7mod2a: DirectIndirectLong +lblC7mod2b: CMP8 + NEXTOPCODE 6 + @ 22 @ 7 +OpC8X0mod2: +lblC8mod2: OpC8X0 + NEXTOPCODE 2 + @ 10 @ 2 +OpC9M1mod2: +lblC9mod2: OpC9M1 + NEXTOPCODE 2 + @ 18 @ 3 +OpCAX0mod2: +lblCAmod2: OpCAX0 + NEXTOPCODE 2 + @ 10 @ 2 +OpCBmod2: +lblCBmod2: OpCB + NEXTOPCODE 3 + @ 11 @ 3 +OpCCX0mod2: +lblCCmod2a: Absolute +lblCCmod2b: CMY16 + NEXTOPCODE 5 + @ 29 @ 4 +OpCDM1mod2: +lblCDmod2a: Absolute +lblCDmod2b: CMP8 + NEXTOPCODE 4 + @ 28 @ 5 +OpCEM1mod2: +lblCEmod2a: Absolute +lblCEmod2b: DEC8 + NEXTOPCODE 6 + @ 30 @ 8 +OpCFM1mod2: +lblCFmod2a: AbsoluteLong +lblCFmod2b: CMP8 + NEXTOPCODE 5 + @ 37 @ 6 +OpD0mod2: +lblD0mod2: OpD0 + NEXTOPCODE 2 + @ 18 @ 2 +OpD1M1mod2: +lblD1mod2a: DirectIndirectIndexed0 +lblD1mod2b: CMP8 + NEXTOPCODE 6 + @ 22 @ 6 +OpD2M1mod2: +lblD2mod2a: DirectIndirect +lblD2mod2b: CMP8 + NEXTOPCODE 5 + @ 21 @ 6 +OpD3M1mod2: +lblD3mod2a: StackasmRelativeIndirectIndexed0 +lblD3mod2b: CMP8 + NEXTOPCODE 7 + @ 23 @ 8 +OpD4mod2: +lblD4mod2: OpD4 + NEXTOPCODE 6 + @ 22 @ 6 +OpD5M1mod2: +lblD5mod2a: DirectIndexedX0 +lblD5mod2b: CMP8 + NEXTOPCODE 4 + @ 20 @ 5 +OpD6M1mod2: +lblD6mod2a: DirectIndexedX0 +lblD6mod2b: DEC8 + NEXTOPCODE 8 + @ 24 @ 8 +OpD7M1mod2: +lblD7mod2a: DirectIndirectIndexedLong0 +lblD7mod2b: CMP8 + NEXTOPCODE 6 + @ 22 @ 7 +OpD8mod2: +lblD8mod2: OpD8 + NEXTOPCODE 2 + @ 10 @ 2 +OpD9M1mod2: +lblD9mod2a: AbsoluteIndexedY0 +lblD9mod2b: CMP8 + NEXTOPCODE 5 + @ 29 @ 5 +OpDAX0mod2: +lblDAmod2: OpDAX0 + NEXTOPCODE 4 + @ 12 @ 3 +OpDBmod2: +lblDBmod2: OpDB + NEXTOPCODE 3 + @ 11 @ 3 +OpDCmod2: +lblDCmod2: OpDC + NEXTOPCODE 6 + @ 30 @ 6 +OpDDM1mod2: +lblDDmod2a: AbsoluteIndexedX0 +lblDDmod2b: CMP8 + NEXTOPCODE 5 + @ 29 @ 5 +OpDEM1mod2: +lblDEmod2a: AbsoluteIndexedX0 +lblDEmod2b: DEC8 + NEXTOPCODE 7 + @ 31 @ 9 +OpDFM1mod2: +lblDFmod2a: AbsoluteLongIndexedX0 +lblDFmod2b: CMP8 + NEXTOPCODE 5 + @ 37 @ 6 +OpE0X0mod2: +lblE0mod2: OpE0X0 + NEXTOPCODE 3 + @ 19 @ 2 +OpE1M1mod2: +lblE1mod2a: DirectIndexedIndirect0 +lblE1mod2b: SBC8 + NEXTOPCODE 6 + @ 22 @ 7 +OpE2mod2: +lblE2mod2: OpE2 + NEXTOPCODE 3 + @ 19 @ 3 +.pool +OpE3M1mod2: +lblE3mod2a: StackasmRelative +lblE3mod2b: SBC8 + NEXTOPCODE 4 + @ 20 @ 5 +OpE4X0mod2: +lblE4mod2a: Direct +lblE4mod2b: CMX16 + NEXTOPCODE 4 + @ 20 @ 3 +OpE5M1mod2: +lblE5mod2a: Direct +lblE5mod2b: SBC8 + NEXTOPCODE 3 + @ 19 @ 4 +OpE6M1mod2: +lblE6mod2a: Direct +lblE6mod2b: INC8 + NEXTOPCODE 6 + @ 22 @ 7 +OpE7M1mod2: +lblE7mod2a: DirectIndirectLong +lblE7mod2b: SBC8 + NEXTOPCODE 6 + @ 22 @ 7 +OpE8X0mod2: +lblE8mod2: OpE8X0 + NEXTOPCODE 2 + @ 10 @ 2 +OpE9M1mod2: +lblE9mod2a: Immediate8 +lblE9mod2b: SBC8 + NEXTOPCODE 2 + @ 18 @ 3 +OpEAmod2: +lblEAmod2: OpEA + NEXTOPCODE 2 + @ 10 @ 2 +OpEBmod2: +lblEBmod2: OpEBM1 + NEXTOPCODE 3 + @ 11 @ 3 +OpECX0mod2: +lblECmod2a: Absolute +lblECmod2b: CMX16 + NEXTOPCODE 5 + @ 29 @ 4 +OpEDM1mod2: +lblEDmod2a: Absolute +lblEDmod2b: SBC8 + NEXTOPCODE 4 + @ 28 @ 5 +OpEEM1mod2: +lblEEmod2a: Absolute +lblEEmod2b: INC8 + NEXTOPCODE 6 + @ 30 @ 8 +OpEFM1mod2: +lblEFmod2a: AbsoluteLong +lblEFmod2b: SBC8 + NEXTOPCODE 5 + @ 37 @ 6 +OpF0mod2: +lblF0mod2: OpF0 + NEXTOPCODE 2 + @ 18 @ 2 +OpF1M1mod2: +lblF1mod2a: DirectIndirectIndexed0 +lblF1mod2b: SBC8 + NEXTOPCODE 6 + @ 22 @ 6 +OpF2M1mod2: +lblF2mod2a: DirectIndirect +lblF2mod2b: SBC8 + NEXTOPCODE 5 + @ 21 @ 6 +OpF3M1mod2: +lblF3mod2a: StackasmRelativeIndirectIndexed0 +lblF3mod2b: SBC8 + NEXTOPCODE 7 + @ 23 @ 8 +OpF4mod2: +lblF4mod2: OpF4 + NEXTOPCODE 5 + @ 29 @ 5 +OpF5M1mod2: +lblF5mod2a: DirectIndexedX0 +lblF5mod2b: SBC8 + NEXTOPCODE 4 + @ 20 @ 5 +OpF6M1mod2: +lblF6mod2a: DirectIndexedX0 +lblF6mod2b: INC8 + NEXTOPCODE 8 + @ 24 @ 8 +OpF7M1mod2: +lblF7mod2a: DirectIndirectIndexedLong0 +lblF7mod2b: SBC8 + NEXTOPCODE 6 + @ 22 @ 7 +OpF8mod2: +lblF8mod2: OpF8 + NEXTOPCODE 2 + @ 10 @ 2 +OpF9M1mod2: +lblF9mod2a: AbsoluteIndexedY0 +lblF9mod2b: SBC8 + NEXTOPCODE 5 + @ 29 @ 5 +OpFAX0mod2: +lblFAmod2: OpFAX0 + NEXTOPCODE 5 + @ 13 @ 4 +OpFBmod2: +lblFBmod2: OpFB + NEXTOPCODE 2 + @ 10 @ 2 +OpFCmod2: +lblFCmod2: OpFCX0 + NEXTOPCODE 6 + @ 30 @ 6 +OpFDM1mod2: +lblFDmod2a: AbsoluteIndexedX0 +lblFDmod2b: SBC8 + NEXTOPCODE 5 + @ 29 @ 5 +OpFEM1mod2: +lblFEmod2a: AbsoluteIndexedX0 +lblFEmod2b: INC8 + NEXTOPCODE 7 + @ 31 @ 9 +OpFFM1mod2: +lblFFmod2a: AbsoluteLongIndexedX0 +lblFFmod2b: SBC8 + NEXTOPCODE 5 + @ 37 @ 6 + +.pool + + +jumptable3: .long Op00mod3 + .long Op01M0mod3 + .long Op02mod3 + .long Op03M0mod3 + .long Op04M0mod3 + .long Op05M0mod3 + .long Op06M0mod3 + .long Op07M0mod3 + .long Op08mod3 + .long Op09M0mod3 + .long Op0AM0mod3 + .long Op0Bmod3 + .long Op0CM0mod3 + .long Op0DM0mod3 + .long Op0EM0mod3 + .long Op0FM0mod3 + .long Op10mod3 + .long Op11M0mod3 + .long Op12M0mod3 + .long Op13M0mod3 + .long Op14M0mod3 + .long Op15M0mod3 + .long Op16M0mod3 + .long Op17M0mod3 + .long Op18mod3 + .long Op19M0mod3 + .long Op1AM0mod3 + .long Op1Bmod3 + .long Op1CM0mod3 + .long Op1DM0mod3 + .long Op1EM0mod3 + .long Op1FM0mod3 + .long Op20mod3 + .long Op21M0mod3 + .long Op22mod3 + .long Op23M0mod3 + .long Op24M0mod3 + + .long Op25M0mod3 + .long Op26M0mod3 + .long Op27M0mod3 + .long Op28mod3 + .long Op29M0mod3 + .long Op2AM0mod3 + .long Op2Bmod3 + .long Op2CM0mod3 + .long Op2DM0mod3 + .long Op2EM0mod3 + .long Op2FM0mod3 + .long Op30mod3 + .long Op31M0mod3 + .long Op32M0mod3 + .long Op33M0mod3 + .long Op34M0mod3 + .long Op35M0mod3 + .long Op36M0mod3 + .long Op37M0mod3 + .long Op38mod3 + .long Op39M0mod3 + .long Op3AM0mod3 + .long Op3Bmod3 + .long Op3CM0mod3 + .long Op3DM0mod3 + .long Op3EM0mod3 + .long Op3FM0mod3 + .long Op40mod3 + .long Op41M0mod3 + .long Op42mod3 + .long Op43M0mod3 + .long Op44X0mod3 + .long Op45M0mod3 + .long Op46M0mod3 + .long Op47M0mod3 + .long Op48M0mod3 + .long Op49M0mod3 + .long Op4AM0mod3 + .long Op4Bmod3 + .long Op4Cmod3 + .long Op4DM0mod3 + .long Op4EM0mod3 + .long Op4FM0mod3 + .long Op50mod3 + .long Op51M0mod3 + .long Op52M0mod3 + .long Op53M0mod3 + .long Op54X0mod3 + .long Op55M0mod3 + .long Op56M0mod3 + .long Op57M0mod3 + .long Op58mod3 + .long Op59M0mod3 + .long Op5AX0mod3 + .long Op5Bmod3 + .long Op5Cmod3 + .long Op5DM0mod3 + .long Op5EM0mod3 + .long Op5FM0mod3 + .long Op60mod3 + .long Op61M0mod3 + .long Op62mod3 + .long Op63M0mod3 + .long Op64M0mod3 + .long Op65M0mod3 + .long Op66M0mod3 + .long Op67M0mod3 + .long Op68M0mod3 + .long Op69M0mod3 + .long Op6AM0mod3 + .long Op6Bmod3 + .long Op6Cmod3 + .long Op6DM0mod3 + .long Op6EM0mod3 + .long Op6FM0mod3 + .long Op70mod3 + .long Op71M0mod3 + .long Op72M0mod3 + .long Op73M0mod3 + .long Op74M0mod3 + .long Op75M0mod3 + .long Op76M0mod3 + .long Op77M0mod3 + .long Op78mod3 + .long Op79M0mod3 + .long Op7AX0mod3 + .long Op7Bmod3 + .long Op7Cmod3 + .long Op7DM0mod3 + .long Op7EM0mod3 + + .long Op7FM0mod3 + .long Op80mod3 + .long Op81M0mod3 + .long Op82mod3 + .long Op83M0mod3 + .long Op84X0mod3 + .long Op85M0mod3 + .long Op86X0mod3 + .long Op87M0mod3 + .long Op88X0mod3 + .long Op89M0mod3 + .long Op8AM0mod3 + .long Op8Bmod3 + .long Op8CX0mod3 + .long Op8DM0mod3 + .long Op8EX0mod3 + .long Op8FM0mod3 + .long Op90mod3 + .long Op91M0mod3 + .long Op92M0mod3 + .long Op93M0mod3 + .long Op94X0mod3 + .long Op95M0mod3 + .long Op96X0mod3 + .long Op97M0mod3 + .long Op98M0mod3 + .long Op99M0mod3 + .long Op9Amod3 + .long Op9BX0mod3 + .long Op9CM0mod3 + .long Op9DM0mod3 + .long Op9EM0mod3 + .long Op9FM0mod3 + .long OpA0X0mod3 + .long OpA1M0mod3 + .long OpA2X0mod3 + .long OpA3M0mod3 + .long OpA4X0mod3 + .long OpA5M0mod3 + .long OpA6X0mod3 + .long OpA7M0mod3 + .long OpA8X0mod3 + .long OpA9M0mod3 + .long OpAAX0mod3 + .long OpABmod3 + .long OpACX0mod3 + .long OpADM0mod3 + .long OpAEX0mod3 + .long OpAFM0mod3 + .long OpB0mod3 + .long OpB1M0mod3 + .long OpB2M0mod3 + .long OpB3M0mod3 + .long OpB4X0mod3 + .long OpB5M0mod3 + .long OpB6X0mod3 + .long OpB7M0mod3 + .long OpB8mod3 + .long OpB9M0mod3 + .long OpBAX0mod3 + .long OpBBX0mod3 + .long OpBCX0mod3 + .long OpBDM0mod3 + .long OpBEX0mod3 + .long OpBFM0mod3 + .long OpC0X0mod3 + .long OpC1M0mod3 + .long OpC2mod3 + .long OpC3M0mod3 + .long OpC4X0mod3 + .long OpC5M0mod3 + .long OpC6M0mod3 + .long OpC7M0mod3 + .long OpC8X0mod3 + .long OpC9M0mod3 + .long OpCAX0mod3 + .long OpCBmod3 + .long OpCCX0mod3 + .long OpCDM0mod3 + .long OpCEM0mod3 + .long OpCFM0mod3 + .long OpD0mod3 + .long OpD1M0mod3 + .long OpD2M0mod3 + .long OpD3M0mod3 + .long OpD4mod3 + .long OpD5M0mod3 + .long OpD6M0mod3 + .long OpD7M0mod3 + .long OpD8mod3 + .long OpD9M0mod3 + .long OpDAX0mod3 + .long OpDBmod3 + .long OpDCmod3 + .long OpDDM0mod3 + .long OpDEM0mod3 + .long OpDFM0mod3 + .long OpE0X0mod3 + .long OpE1M0mod3 + .long OpE2mod3 + .long OpE3M0mod3 + .long OpE4X0mod3 + .long OpE5M0mod3 + .long OpE6M0mod3 + .long OpE7M0mod3 + .long OpE8X0mod3 + .long OpE9M0mod3 + .long OpEAmod3 + .long OpEBmod3 + .long OpECX0mod3 + .long OpEDM0mod3 + .long OpEEM0mod3 + .long OpEFM0mod3 + .long OpF0mod3 + .long OpF1M0mod3 + .long OpF2M0mod3 + .long OpF3M0mod3 + .long OpF4mod3 + .long OpF5M0mod3 + .long OpF6M0mod3 + .long OpF7M0mod3 + .long OpF8mod3 + .long OpF9M0mod3 + .long OpFAX0mod3 + .long OpFBmod3 + .long OpFCmod3 + .long OpFDM0mod3 + .long OpFEM0mod3 + .long OpFFM0mod3 +Op00mod3: +lbl00mod3: Op00 + NEXTOPCODE 8 + @ 24 @ 8 +Op01M0mod3: +lbl01mod3a: DirectIndexedIndirect0 +lbl01mod3b: ORA16 + NEXTOPCODE 7 + @ 23 @ 6 +Op02mod3: +lbl02mod3: Op02 + NEXTOPCODE 8 + @ 24 @ 8 +Op03M0mod3: +lbl03mod3a: StackasmRelative +lbl03mod3b: ORA16 + NEXTOPCODE 5 + @ 21 @ 4 +Op04M0mod3: +lbl04mod3a: Direct +lbl04mod3b: TSB16 + NEXTOPCODE 7 + @ 23 @ 5 +Op05M0mod3: +lbl05mod3a: Direct +lbl05mod3b: ORA16 + NEXTOPCODE 4 + @ 20 @ 3 +Op06M0mod3: +lbl06mod3a: Direct +lbl06mod3b: ASL16 + NEXTOPCODE 7 + @ 23 @ 5 +Op07M0mod3: +lbl07mod3a: DirectIndirectLong +lbl07mod3b: ORA16 + NEXTOPCODE 7 + @ 23 @ 6 +Op08mod3: +lbl08mod3: Op08 + NEXTOPCODE 3 + @ 11 @ 3 +Op09M0mod3: +lbl09mod3: Op09M0 + NEXTOPCODE 3 + @ 19 @ 2 +Op0AM0mod3: +lbl0Amod3a: A_ASL16 + NEXTOPCODE 2 + @ 10 @ 2 +Op0Bmod3: +lbl0Bmod3: Op0B + NEXTOPCODE 4 + @ 12 @ 4 +Op0CM0mod3: +lbl0Cmod3a: Absolute +lbl0Cmod3b: TSB16 + NEXTOPCODE 8 + @ 32 @ 6 +Op0DM0mod3: +lbl0Dmod3a: Absolute +lbl0Dmod3b: ORA16 + NEXTOPCODE 5 + @ 29 @ 4 +Op0EM0mod3: +lbl0Emod3a: Absolute +lbl0Emod3b: ASL16 + NEXTOPCODE 8 + @ 32 @ 6 +Op0FM0mod3: +lbl0Fmod3a: AbsoluteLong +lbl0Fmod3b: ORA16 + NEXTOPCODE 6 + @ 38 @ 5 +Op10mod3: +lbl10mod3: Op10 + NEXTOPCODE 2 + @ 18 @ 2 +Op11M0mod3: +lbl11mod3a: DirectIndirectIndexed0 +lbl11mod3b: ORA16 + NEXTOPCODE 6 + @ 22 @ 6 +Op12M0mod3: +lbl12mod3a: DirectIndirect +lbl12mod3b: ORA16 + NEXTOPCODE 6 + @ 22 @ 5 +Op13M0mod3: +lbl13mod3a: StackasmRelativeIndirectIndexed0 +lbl13mod3b: ORA16 + NEXTOPCODE 8 + @ 24 @ 7 +Op14M0mod3: +lbl14mod3a: Direct +lbl14mod3b: TRB16 + NEXTOPCODE 7 + @ 23 @ 5 +Op15M0mod3: +lbl15mod3a: DirectIndexedX0 +lbl15mod3b: ORA16 + NEXTOPCODE 5 + @ 21 @ 4 +Op16M0mod3: +lbl16mod3a: DirectIndexedX0 +lbl16mod3b: ASL16 + NEXTOPCODE 8 + @ 24 @ 6 +Op17M0mod3: +lbl17mod3a: DirectIndirectIndexedLong0 +lbl17mod3b: ORA16 + NEXTOPCODE 7 + @ 23 @ 6 +Op18mod3: +lbl18mod3: Op18 + NEXTOPCODE 2 + @ 10 @ 2 +Op19M0mod3: +lbl19mod3a: AbsoluteIndexedY0 +lbl19mod3b: ORA16 + NEXTOPCODE 5 + @ 29 @ 5 +Op1AM0mod3: +lbl1Amod3a: A_INC16 + NEXTOPCODE 2 + @ 10 @ 2 +Op1Bmod3: +lbl1Bmod3: Op1BM0 + NEXTOPCODE 2 + @ 10 @ 2 +Op1CM0mod3: +lbl1Cmod3a: Absolute +lbl1Cmod3b: TRB16 + NEXTOPCODE 8 + @ 32 @ 6 +Op1DM0mod3: +lbl1Dmod3a: AbsoluteIndexedX0 +lbl1Dmod3b: ORA16 + NEXTOPCODE 5 + @ 29 @ 5 +Op1EM0mod3: +lbl1Emod3a: AbsoluteIndexedX0 +lbl1Emod3b: ASL16 + NEXTOPCODE 9 + @ 33 @ 7 +Op1FM0mod3: +lbl1Fmod3a: AbsoluteLongIndexedX0 +lbl1Fmod3b: ORA16 + NEXTOPCODE 6 + @ 38 @ 5 +Op20mod3: +lbl20mod3: Op20 + NEXTOPCODE 6 + @ 30 @ 6 +Op21M0mod3: +lbl21mod3a: DirectIndexedIndirect0 +lbl21mod3b: AND16 + NEXTOPCODE 7 + @ 23 @ 6 +Op22mod3: +lbl22mod3: Op22 + NEXTOPCODE 8 + @ 40 @ 8 +Op23M0mod3: +lbl23mod3a: StackasmRelative +lbl23mod3b: AND16 + NEXTOPCODE 5 + @ 21 @ 4 +Op24M0mod3: +lbl24mod3a: Direct +lbl24mod3b: BIT16 + NEXTOPCODE 4 + @ 20 @ 3 +Op25M0mod3: +lbl25mod3a: Direct +lbl25mod3b: AND16 + NEXTOPCODE 4 + @ 20 @ 3 +Op26M0mod3: +lbl26mod3a: Direct +lbl26mod3b: ROL16 + NEXTOPCODE 7 + @ 23 @ 5 +Op27M0mod3: +lbl27mod3a: DirectIndirectLong +lbl27mod3b: AND16 + NEXTOPCODE 7 + @ 23 @ 6 +Op28mod3: +lbl28mod3: Op28X0M0 + NEXTOPCODE 4 + @ 12 @ 4 +.pool +Op29M0mod3: +lbl29mod3: Op29M0 + NEXTOPCODE 3 + @ 19 @ 2 +Op2AM0mod3: +lbl2Amod3a: A_ROL16 + NEXTOPCODE 2 + @ 10 @ 2 +Op2Bmod3: +lbl2Bmod3: Op2B + NEXTOPCODE 5 + @ 13 @ 5 +Op2CM0mod3: +lbl2Cmod3a: Absolute +lbl2Cmod3b: BIT16 + NEXTOPCODE 5 + @ 29 @ 4 +Op2DM0mod3: +lbl2Dmod3a: Absolute +lbl2Dmod3b: AND16 + NEXTOPCODE 5 + @ 29 @ 4 +Op2EM0mod3: +lbl2Emod3a: Absolute +lbl2Emod3b: ROL16 + NEXTOPCODE 8 + @ 32 @ 6 +Op2FM0mod3: +lbl2Fmod3a: AbsoluteLong +lbl2Fmod3b: AND16 + NEXTOPCODE 6 + @ 38 @ 5 +Op30mod3: +lbl30mod3: Op30 + NEXTOPCODE 2 + @ 18 @ 2 +Op31M0mod3: +lbl31mod3a: DirectIndirectIndexed0 +lbl31mod3b: AND16 + NEXTOPCODE 6 + @ 22 @ 6 +Op32M0mod3: +lbl32mod3a: DirectIndirect +lbl32mod3b: AND16 + NEXTOPCODE 6 + @ 22 @ 5 +Op33M0mod3: +lbl33mod3a: StackasmRelativeIndirectIndexed0 +lbl33mod3b: AND16 + NEXTOPCODE 8 + @ 24 @ 7 +Op34M0mod3: +lbl34mod3a: DirectIndexedX0 +lbl34mod3b: BIT16 + NEXTOPCODE 5 + @ 21 @ 4 +Op35M0mod3: +lbl35mod3a: DirectIndexedX0 +lbl35mod3b: AND16 + NEXTOPCODE 5 + @ 21 @ 4 +Op36M0mod3: +lbl36mod3a: DirectIndexedX0 +lbl36mod3b: ROL16 + NEXTOPCODE 8 + @ 24 @ 6 +Op37M0mod3: +lbl37mod3a: DirectIndirectIndexedLong0 +lbl37mod3b: AND16 + NEXTOPCODE 7 + @ 23 @ 6 +Op38mod3: +lbl38mod3: Op38 + NEXTOPCODE 2 + @ 10 @ 2 +Op39M0mod3: +lbl39mod3a: AbsoluteIndexedY0 +lbl39mod3b: AND16 + NEXTOPCODE 5 + @ 29 @ 5 +Op3AM0mod3: +lbl3Amod3a: A_DEC16 + NEXTOPCODE 2 + @ 10 @ 2 +Op3Bmod3: +lbl3Bmod3: Op3BM0 + NEXTOPCODE 2 + @ 10 @ 2 +Op3CM0mod3: +lbl3Cmod3a: AbsoluteIndexedX0 +lbl3Cmod3b: BIT16 + NEXTOPCODE 5 + @ 29 @ 5 +Op3DM0mod3: +lbl3Dmod3a: AbsoluteIndexedX0 +lbl3Dmod3b: AND16 + NEXTOPCODE 5 + @ 29 @ 5 +Op3EM0mod3: +lbl3Emod3a: AbsoluteIndexedX0 +lbl3Emod3b: ROL16 + NEXTOPCODE 9 + @ 33 @ 7 +Op3FM0mod3: +lbl3Fmod3a: AbsoluteLongIndexedX0 +lbl3Fmod3b: AND16 + NEXTOPCODE 6 + @ 38 @ 5 +Op40mod3: +lbl40mod3: Op40X0M0 + NEXTOPCODE 7 + @ 15 @ 7 +.pool +Op41M0mod3: +lbl41mod3a: DirectIndexedIndirect0 +lbl41mod3b: EOR16 + NEXTOPCODE 7 + @ 23 @ 6 +Op42mod3: +lbl42mod3: Op42 + NEXTOPCODE 2 + @ 18 @ 2 +Op43M0mod3: +lbl43mod3a: StackasmRelative +lbl43mod3b: EOR16 + NEXTOPCODE 5 + @ 21 @ 4 +Op44X0mod3: +lbl44mod3: Op44X0M0 + NEXTOPCODE 0 + @ 24 @ 0 +Op45M0mod3: +lbl45mod3a: Direct +lbl45mod3b: EOR16 + NEXTOPCODE 4 + @ 20 @ 3 +Op46M0mod3: +lbl46mod3a: Direct +lbl46mod3b: LSR16 + NEXTOPCODE 7 + @ 23 @ 5 +Op47M0mod3: +lbl47mod3a: DirectIndirectLong +lbl47mod3b: EOR16 + NEXTOPCODE 7 + @ 23 @ 6 +Op48M0mod3: +lbl48mod3: Op48M0 + NEXTOPCODE 4 + @ 12 @ 4 +Op49M0mod3: +lbl49mod3: Op49M0 + NEXTOPCODE 3 + @ 19 @ 2 +Op4AM0mod3: +lbl4Amod3a: A_LSR16 + NEXTOPCODE 2 + @ 10 @ 2 +Op4Bmod3: +lbl4Bmod3: Op4B + NEXTOPCODE 3 + @ 11 @ 3 +Op4Cmod3: +lbl4Cmod3: Op4C + NEXTOPCODE 3 + @ 27 @ 3 +Op4DM0mod3: +lbl4Dmod3a: Absolute +lbl4Dmod3b: EOR16 + NEXTOPCODE 5 + @ 29 @ 4 +Op4EM0mod3: +lbl4Emod3a: Absolute +lbl4Emod3b: LSR16 + NEXTOPCODE 8 + @ 32 @ 6 +Op4FM0mod3: +lbl4Fmod3a: AbsoluteLong +lbl4Fmod3b: EOR16 + NEXTOPCODE 6 + @ 38 @ 5 +Op50mod3: +lbl50mod3: Op50 + NEXTOPCODE 2 + @ 18 @ 2 +Op51M0mod3: +lbl51mod3a: DirectIndirectIndexed0 +lbl51mod3b: EOR16 + NEXTOPCODE 6 + @ 22 @ 6 +Op52M0mod3: +lbl52mod3a: DirectIndirect +lbl52mod3b: EOR16 + NEXTOPCODE 6 + @ 22 @ 5 +Op53M0mod3: +lbl53mod3a: StackasmRelativeIndirectIndexed0 +lbl53mod3b: EOR16 + NEXTOPCODE 8 + @ 24 @ 7 +Op54X0mod3: +lbl54mod3: Op54X0M0 + NEXTOPCODE 0 + @ 24 @ 0 +Op55M0mod3: +lbl55mod3a: DirectIndexedX0 +lbl55mod3b: EOR16 + NEXTOPCODE 5 + @ 21 @ 4 +Op56M0mod3: +lbl56mod3a: DirectIndexedX0 +lbl56mod3b: LSR16 + NEXTOPCODE 8 + @ 24 @ 6 +Op57M0mod3: +lbl57mod3a: DirectIndirectIndexedLong0 +lbl57mod3b: EOR16 + NEXTOPCODE 7 + @ 23 @ 6 +Op58mod3: +lbl58mod3: Op58 + NEXTOPCODE 2 + @ 10 @ 2 +Op59M0mod3: +lbl59mod3a: AbsoluteIndexedY0 +lbl59mod3b: EOR16 + NEXTOPCODE 5 + @ 29 @ 5 +Op5AX0mod3: +lbl5Amod3: Op5AX0 + NEXTOPCODE 3 + @ 11 @ 4 +Op5Bmod3: +lbl5Bmod3: Op5BM0 + NEXTOPCODE 2 + @ 10 @ 2 +Op5Cmod3: +lbl5Cmod3: Op5C + NEXTOPCODE 4 + @ 36 @ 4 +Op5DM0mod3: +lbl5Dmod3a: AbsoluteIndexedX0 +lbl5Dmod3b: EOR16 + NEXTOPCODE 5 + @ 29 @ 5 +Op5EM0mod3: +lbl5Emod3a: AbsoluteIndexedX0 +lbl5Emod3b: LSR16 + NEXTOPCODE 9 + @ 33 @ 7 +Op5FM0mod3: +lbl5Fmod3a: AbsoluteLongIndexedX0 +lbl5Fmod3b: EOR16 + NEXTOPCODE 6 + @ 38 @ 5 +Op60mod3: +lbl60mod3: Op60 + NEXTOPCODE 6 + @ 14 @ 6 +Op61M0mod3: +lbl61mod3a: DirectIndexedIndirect0 +lbl61mod3b: ADC16 + NEXTOPCODE 7 + @ 23 @ 6 +Op62mod3: +lbl62mod3: Op62 + NEXTOPCODE 6 + @ 30 @ 6 +Op63M0mod3: +lbl63mod3a: StackasmRelative +lbl63mod3b: ADC16 + NEXTOPCODE 5 + @ 21 @ 4 +.pool +Op64M0mod3: +lbl64mod3a: Direct +lbl64mod3b: STZ16 + NEXTOPCODE 4 + @ 20 @ 3 +Op65M0mod3: +lbl65mod3a: Direct +lbl65mod3b: ADC16 + NEXTOPCODE 4 + @ 20 @ 3 +.pool +Op66M0mod3: +lbl66mod3a: Direct +lbl66mod3b: ROR16 + NEXTOPCODE 7 + @ 23 @ 5 +Op67M0mod3: +lbl67mod3a: DirectIndirectLong +lbl67mod3b: ADC16 + NEXTOPCODE 7 + @ 23 @ 6 +.pool +Op68M0mod3: +lbl68mod3: Op68M0 + NEXTOPCODE 5 + @ 13 @ 5 +Op69M0mod3: +lbl69mod3a: Immediate16 +lbl69mod3b: ADC16 + NEXTOPCODE 3 + @ 19 @ 2 +.pool +Op6AM0mod3: +lbl6Amod3a: A_ROR16 + NEXTOPCODE 2 + @ 10 @ 2 +Op6Bmod3: +lbl6Bmod3: Op6B + NEXTOPCODE 6 + @ 14 @ 6 +Op6Cmod3: +lbl6Cmod3: Op6C + NEXTOPCODE 5 + @ 29 @ 5 +Op6DM0mod3: +lbl6Dmod3a: Absolute +lbl6Dmod3b: ADC16 + NEXTOPCODE 5 + @ 29 @ 4 +Op6EM0mod3: +lbl6Emod3a: Absolute +lbl6Emod3b: ROR16 + NEXTOPCODE 8 + @ 32 @ 6 +Op6FM0mod3: +lbl6Fmod3a: AbsoluteLong +lbl6Fmod3b: ADC16 + NEXTOPCODE 6 + @ 38 @ 5 +Op70mod3: +lbl70mod3: Op70 + NEXTOPCODE 2 + @ 18 @ 2 +Op71M0mod3: +lbl71mod3a: DirectIndirectIndexed0 +lbl71mod3b: ADC16 + NEXTOPCODE 6 + @ 22 @ 6 +Op72M0mod3: +lbl72mod3a: DirectIndirect +lbl72mod3b: ADC16 + NEXTOPCODE 6 + @ 22 @ 5 +Op73M0mod3: +lbl73mod3a: StackasmRelativeIndirectIndexed0 +lbl73mod3b: ADC16 + NEXTOPCODE 8 + @ 24 @ 7 +.pool +Op74M0mod3: +lbl74mod3a: DirectIndexedX0 +lbl74mod3b: STZ16 + NEXTOPCODE 5 + @ 21 @ 4 +Op75M0mod3: +lbl75mod3a: DirectIndexedX0 +lbl75mod3b: ADC16 + NEXTOPCODE 5 + @ 21 @ 4 +.pool +Op76M0mod3: +lbl76mod3a: DirectIndexedX0 +lbl76mod3b: ROR16 + NEXTOPCODE 8 + @ 24 @ 6 +Op77M0mod3: +lbl77mod3a: DirectIndirectIndexedLong0 +lbl77mod3b: ADC16 + NEXTOPCODE 7 + @ 23 @ 6 +Op78mod3: +lbl78mod3: Op78 + NEXTOPCODE 2 + @ 10 @ 2 +Op79M0mod3: +lbl79mod3a: AbsoluteIndexedY0 +lbl79mod3b: ADC16 + NEXTOPCODE 5 + @ 29 @ 5 +Op7AX0mod3: +lbl7Amod3: Op7AX0 + NEXTOPCODE 4 + @ 12 @ 5 +Op7Bmod3: +lbl7Bmod3: Op7BM0 + NEXTOPCODE 2 + @ 10 @ 2 +Op7Cmod3: +lbl7Cmod3: AbsoluteIndexedIndirectX0 + Op7C + NEXTOPCODE 6 + @ 30 @ 6 +Op7DM0mod3: +lbl7Dmod3a: AbsoluteIndexedX0 +lbl7Dmod3b: ADC16 + NEXTOPCODE 5 + @ 29 @ 5 +Op7EM0mod3: +lbl7Emod3a: AbsoluteIndexedX0 +lbl7Emod3b: ROR16 + NEXTOPCODE 9 + @ 33 @ 7 +Op7FM0mod3: +lbl7Fmod3a: AbsoluteLongIndexedX0 +lbl7Fmod3b: ADC16 + NEXTOPCODE 6 + @ 38 @ 5 +.pool +Op80mod3: +lbl80mod3: Op80 + NEXTOPCODE 2 + @ 18 @ 2 +Op81M0mod3: +lbl81mod3a: DirectIndexedIndirect0 +lbl81mod3b: Op81M0 + NEXTOPCODE 7 + @ 23 @ 6 +Op82mod3: +lbl82mod3: Op82 + NEXTOPCODE 3 + @ 27 @ 3 +Op83M0mod3: +lbl83mod3a: StackasmRelative +lbl83mod3b: STA16 + NEXTOPCODE 5 + @ 21 @ 4 +Op84X0mod3: +lbl84mod3a: Direct +lbl84mod3b: STY16 + NEXTOPCODE 3 + @ 19 @ 4 +Op85M0mod3: +lbl85mod3a: Direct +lbl85mod3b: STA16 + NEXTOPCODE 4 + @ 20 @ 3 +Op86X0mod3: +lbl86mod3a: Direct +lbl86mod3b: STX16 + NEXTOPCODE 3 + @ 19 @ 4 +Op87M0mod3: +lbl87mod3a: DirectIndirectLong +lbl87mod3b: STA16 + NEXTOPCODE 7 + @ 23 @ 6 +Op88X0mod3: +lbl88mod3: Op88X0 + NEXTOPCODE 2 + @ 10 @ 2 +Op89M0mod3: +lbl89mod3: Op89M0 + NEXTOPCODE 3 + @ 19 @ 2 +Op8AM0mod3: +lbl8Amod3: Op8AM0X0 + NEXTOPCODE 2 + @ 10 @ 2 +Op8Bmod3: +lbl8Bmod3: Op8B + NEXTOPCODE 3 + @ 11 @ 3 +Op8CX0mod3: +lbl8Cmod3a: Absolute +lbl8Cmod3b: STY16 + NEXTOPCODE 4 + @ 28 @ 5 +Op8DM0mod3: +lbl8Dmod3a: Absolute +lbl8Dmod3b: STA16 + NEXTOPCODE 5 + @ 29 @ 4 +Op8EX0mod3: +lbl8Emod3a: Absolute +lbl8Emod3b: STX16 + NEXTOPCODE 4 + @ 28 @ 5 +Op8FM0mod3: +lbl8Fmod3a: AbsoluteLong +lbl8Fmod3b: STA16 + NEXTOPCODE 6 + @ 38 @ 5 +Op90mod3: +lbl90mod3: Op90 + NEXTOPCODE 2 + @ 18 @ 2 +Op91M0mod3: +lbl91mod3a: DirectIndirectIndexed0 +lbl91mod3b: STA16 + NEXTOPCODE 6 + @ 22 @ 6 +Op92M0mod3: +lbl92mod3a: DirectIndirect +lbl92mod3b: STA16 + NEXTOPCODE 6 + @ 22 @ 5 +Op93M0mod3: +lbl93mod3a: StackasmRelativeIndirectIndexed0 +lbl93mod3b: STA16 + NEXTOPCODE 8 + @ 24 @ 7 +Op94X0mod3: +lbl94mod3a: DirectIndexedX0 +lbl94mod3b: STY16 + NEXTOPCODE 4 + @ 20 @ 5 +Op95M0mod3: +lbl95mod3a: DirectIndexedX0 +lbl95mod3b: STA16 + NEXTOPCODE 5 + @ 21 @ 4 +Op96X0mod3: +lbl96mod3a: DirectIndexedY0 +lbl96mod3b: STX16 + NEXTOPCODE 4 + @ 20 @ 5 +Op97M0mod3: +lbl97mod3a: DirectIndirectIndexedLong0 +lbl97mod3b: STA16 + NEXTOPCODE 7 + @ 23 @ 6 +Op98M0mod3: +lbl98mod3: Op98M0X0 + NEXTOPCODE 2 + @ 10 @ 2 +Op99M0mod3: +lbl99mod3a: AbsoluteIndexedY0 +lbl99mod3b: STA16 + NEXTOPCODE 5 + @ 29 @ 5 +Op9Amod3: +lbl9Amod3: Op9AX0 + NEXTOPCODE 2 + @ 10 @ 2 +Op9BX0mod3: +lbl9Bmod3: Op9BX0 + NEXTOPCODE 2 + @ 10 @ 2 +Op9CM0mod3: +lbl9Cmod3a: Absolute +lbl9Cmod3b: STZ16 + NEXTOPCODE 5 + @ 29 @ 4 +Op9DM0mod3: +lbl9Dmod3a: AbsoluteIndexedX0 +lbl9Dmod3b: STA16 + NEXTOPCODE 5 + @ 29 @ 5 +Op9EM0mod3: +lbl9Emod3: AbsoluteIndexedX0 + STZ16 + NEXTOPCODE 5 + @ 29 @ 5 +Op9FM0mod3: +lbl9Fmod3a: AbsoluteLongIndexedX0 +lbl9Fmod3b: STA16 + NEXTOPCODE 6 + @ 38 @ 5 +OpA0X0mod3: +lblA0mod3: OpA0X0 + NEXTOPCODE 2 + @ 18 @ 3 +OpA1M0mod3: +lblA1mod3a: DirectIndexedIndirect0 +lblA1mod3b: LDA16 + NEXTOPCODE 7 + @ 23 @ 6 +OpA2X0mod3: +lblA2mod3: OpA2X0 + NEXTOPCODE 2 + @ 18 @ 3 +OpA3M0mod3: +lblA3mod3a: StackasmRelative +lblA3mod3b: LDA16 + NEXTOPCODE 5 + @ 21 @ 4 +OpA4X0mod3: +lblA4mod3a: Direct +lblA4mod3b: LDY16 + NEXTOPCODE 3 + @ 19 @ 4 +OpA5M0mod3: +lblA5mod3a: Direct +lblA5mod3b: LDA16 + NEXTOPCODE 4 + @ 20 @ 3 +OpA6X0mod3: +lblA6mod3a: Direct + +lblA6mod3b: LDX16 + NEXTOPCODE 3 + @ 19 @ 4 +OpA7M0mod3: +lblA7mod3a: DirectIndirectLong +lblA7mod3b: LDA16 + NEXTOPCODE 7 + @ 23 @ 6 +OpA8X0mod3: +lblA8mod3: OpA8X0M0 + NEXTOPCODE 2 + @ 10 @ 2 +OpA9M0mod3: +lblA9mod3: OpA9M0 + NEXTOPCODE 3 + @ 19 @ 2 +OpAAX0mod3: +lblAAmod3: OpAAX0M0 + NEXTOPCODE 2 + @ 10 @ 2 + +OpABmod3: +lblABmod3: OpAB + NEXTOPCODE 4 + @ 12 @ 4 +OpACX0mod3: +lblACmod3a: Absolute +lblACmod3b: LDY16 + NEXTOPCODE 4 + @ 28 @ 5 +OpADM0mod3: +lblADmod3a: Absolute +lblADmod3b: LDA16 + NEXTOPCODE 5 + @ 29 @ 4 +OpAEX0mod3: +lblAEmod3a: Absolute +lblAEmod3b: LDX16 + NEXTOPCODE 4 + @ 28 @ 5 +OpAFM0mod3: +lblAFmod3a: AbsoluteLong +lblAFmod3b: LDA16 + NEXTOPCODE 6 + @ 38 @ 5 +OpB0mod3: +lblB0mod3: OpB0 + NEXTOPCODE 2 + @ 18 @ 2 +OpB1M0mod3: +lblB1mod3a: DirectIndirectIndexed0 +lblB1mod3b: LDA16 + NEXTOPCODE 6 + @ 22 @ 6 +OpB2M0mod3: +lblB2mod3a: DirectIndirect +lblB2mod3b: LDA16 + NEXTOPCODE 6 + @ 22 @ 5 +OpB3M0mod3: +lblB3mod3a: StackasmRelativeIndirectIndexed0 +lblB3mod3b: LDA16 + NEXTOPCODE 8 + @ 24 @ 7 +OpB4X0mod3: +lblB4mod3a: DirectIndexedX0 +lblB4mod3b: LDY16 + NEXTOPCODE 4 + @ 20 @ 5 +OpB5M0mod3: +lblB5mod3a: DirectIndexedX0 +lblB5mod3b: LDA16 + NEXTOPCODE 5 + @ 21 @ 4 +OpB6X0mod3: +lblB6mod3a: DirectIndexedY0 +lblB6mod3b: LDX16 + NEXTOPCODE 4 + @ 20 @ 5 +OpB7M0mod3: +lblB7mod3a: DirectIndirectIndexedLong0 +lblB7mod3b: LDA16 + NEXTOPCODE 7 + @ 23 @ 6 +OpB8mod3: +lblB8mod3: OpB8 + NEXTOPCODE 2 + @ 10 @ 2 +OpB9M0mod3: +lblB9mod3a: AbsoluteIndexedY0 +lblB9mod3b: LDA16 + NEXTOPCODE 5 + @ 29 @ 5 +OpBAX0mod3: +lblBAmod3: OpBAX0 + NEXTOPCODE 2 + @ 10 @ 2 +OpBBX0mod3: +lblBBmod3: OpBBX0 + NEXTOPCODE 2 + @ 10 @ 2 +OpBCX0mod3: +lblBCmod3a: AbsoluteIndexedX0 +lblBCmod3b: LDY16 + NEXTOPCODE 4 + @ 28 @ 5 +OpBDM0mod3: +lblBDmod3a: AbsoluteIndexedX0 +lblBDmod3b: LDA16 + NEXTOPCODE 5 + @ 29 @ 5 +OpBEX0mod3: +lblBEmod3a: AbsoluteIndexedY0 +lblBEmod3b: LDX16 + NEXTOPCODE 4 + @ 28 @ 5 +OpBFM0mod3: +lblBFmod3a: AbsoluteLongIndexedX0 +lblBFmod3b: LDA16 + NEXTOPCODE 6 + @ 38 @ 5 +OpC0X0mod3: +lblC0mod3: OpC0X0 + NEXTOPCODE 2 + @ 18 @ 3 +OpC1M0mod3: +lblC1mod3a: DirectIndexedIndirect0 +lblC1mod3b: CMP16 + NEXTOPCODE 7 + @ 23 @ 6 +OpC2mod3: +lblC2mod3: OpC2 + NEXTOPCODE 3 + @ 19 @ 3 +.pool +OpC3M0mod3: +lblC3mod3a: StackasmRelative +lblC3mod3b: CMP16 + NEXTOPCODE 5 + @ 21 @ 4 +OpC4X0mod3: +lblC4mod3a: Direct +lblC4mod3b: CMY16 + NEXTOPCODE 3 + @ 19 @ 4 +OpC5M0mod3: +lblC5mod3a: Direct +lblC5mod3b: CMP16 + NEXTOPCODE 4 + @ 20 @ 3 +OpC6M0mod3: +lblC6mod3a: Direct +lblC6mod3b: DEC16 + NEXTOPCODE 7 + @ 23 @ 6 +OpC7M0mod3: +lblC7mod3a: DirectIndirectLong +lblC7mod3b: CMP16 + NEXTOPCODE 7 + @ 23 @ 6 +OpC8X0mod3: +lblC8mod3: OpC8X0 + NEXTOPCODE 2 + @ 10 @ 2 +OpC9M0mod3: +lblC9mod3: OpC9M0 + NEXTOPCODE 3 + @ 19 @ 2 +OpCAX0mod3: +lblCAmod3: OpCAX0 + NEXTOPCODE 2 + @ 10 @ 2 +OpCBmod3: +lblCBmod3: OpCB + NEXTOPCODE 3 + @ 11 @ 3 +OpCCX0mod3: +lblCCmod3a: Absolute +lblCCmod3b: CMY16 + NEXTOPCODE 4 + @ 28 @ 5 +OpCDM0mod3: +lblCDmod3a: Absolute +lblCDmod3b: CMP16 + NEXTOPCODE 5 + @ 29 @ 4 +OpCEM0mod3: +lblCEmod3a: Absolute +lblCEmod3b: DEC16 + NEXTOPCODE 8 + @ 32 @ 6 +OpCFM0mod3: +lblCFmod3a: AbsoluteLong +lblCFmod3b: CMP16 + NEXTOPCODE 6 + @ 38 @ 5 +OpD0mod3: +lblD0mod3: OpD0 + NEXTOPCODE 2 + @ 18 @ 2 +OpD1M0mod3: +lblD1mod3a: DirectIndirectIndexed0 +lblD1mod3b: CMP16 + NEXTOPCODE 6 + @ 22 @ 6 +OpD2M0mod3: +lblD2mod3a: DirectIndirect +lblD2mod3b: CMP16 + NEXTOPCODE 6 + @ 22 @ 5 +OpD3M0mod3: +lblD3mod3a: StackasmRelativeIndirectIndexed0 +lblD3mod3b: CMP16 + NEXTOPCODE 8 + @ 24 @ 7 +OpD4mod3: +lblD4mod3: OpD4 + NEXTOPCODE 6 + @ 22 @ 6 +OpD5M0mod3: +lblD5mod3a: DirectIndexedX0 +lblD5mod3b: CMP16 + NEXTOPCODE 5 + @ 21 @ 4 +OpD6M0mod3: +lblD6mod3a: DirectIndexedX0 +lblD6mod3b: DEC16 + NEXTOPCODE 8 + @ 24 @ 8 +OpD7M0mod3: +lblD7mod3a: DirectIndirectIndexedLong0 +lblD7mod3b: CMP16 + NEXTOPCODE 7 + @ 23 @ 6 +OpD8mod3: +lblD8mod3: OpD8 + NEXTOPCODE 2 + @ 10 @ 2 +OpD9M0mod3: +lblD9mod3a: AbsoluteIndexedY0 +lblD9mod3b: CMP16 + NEXTOPCODE 5 + @ 29 @ 5 +OpDAX0mod3: +lblDAmod3: OpDAX0 + NEXTOPCODE 3 + @ 11 @ 4 +OpDBmod3: +lblDBmod3: OpDB + NEXTOPCODE 3 + @ 11 @ 3 +OpDCmod3: +lblDCmod3: OpDC + NEXTOPCODE 6 + @ 30 @ 6 +OpDDM0mod3: +lblDDmod3a: AbsoluteIndexedX0 +lblDDmod3b: CMP16 + NEXTOPCODE 5 + @ 29 @ 5 +OpDEM0mod3: +lblDEmod3a: AbsoluteIndexedX0 +lblDEmod3b: DEC16 + NEXTOPCODE 9 + @ 33 @ 7 +OpDFM0mod3: +lblDFmod3a: AbsoluteLongIndexedX0 +lblDFmod3b: CMP16 + NEXTOPCODE 6 + @ 38 @ 5 +OpE0X0mod3: +lblE0mod3: OpE0X0 + NEXTOPCODE 2 + @ 18 @ 3 +OpE1M0mod3: +lblE1mod3a: DirectIndexedIndirect0 +lblE1mod3b: SBC16 + NEXTOPCODE 7 + @ 23 @ 6 +OpE2mod3: +lblE2mod3: OpE2 + NEXTOPCODE 3 + @ 19 @ 3 +.pool +OpE3M0mod3: +lblE3mod3a: StackasmRelative +lblE3mod3b: SBC16 + NEXTOPCODE 5 + @ 21 @ 4 +OpE4X0mod3: +lblE4mod3a: Direct +lblE4mod3b: CMX16 + NEXTOPCODE 3 + @ 19 @ 4 +OpE5M0mod3: +lblE5mod3a: Direct +lblE5mod3b: SBC16 + NEXTOPCODE 4 + @ 20 @ 3 +OpE6M0mod3: +lblE6mod3a: Direct +lblE6mod3b: INC16 + NEXTOPCODE 7 + @ 23 @ 6 +OpE7M0mod3: +lblE7mod3a: DirectIndirectLong +lblE7mod3b: SBC16 + NEXTOPCODE 7 + @ 23 @ 6 +OpE8X0mod3: +lblE8mod3: OpE8X0 + NEXTOPCODE 2 + @ 10 @ 2 +OpE9M0mod3: +lblE9mod3a: Immediate16 +lblE9mod3b: SBC16 + NEXTOPCODE 3 + @ 19 @ 2 +OpEAmod3: +lblEAmod3: OpEA + NEXTOPCODE 2 + @ 10 @ 2 +OpEBmod3: +lblEBmod3: OpEBM0 + NEXTOPCODE 3 + @ 11 @ 3 +OpECX0mod3: +lblECmod3a: Absolute +lblECmod3b: CMX16 + NEXTOPCODE 4 + @ 28 @ 5 +OpEDM0mod3: +lblEDmod3a: Absolute +lblEDmod3b: SBC16 + NEXTOPCODE 5 + @ 29 @ 4 +OpEEM0mod3: +lblEEmod3a: Absolute +lblEEmod3b: INC16 + NEXTOPCODE 8 + @ 32 @ 6 +OpEFM0mod3: +lblEFmod3a: AbsoluteLong +lblEFmod3b: SBC16 + NEXTOPCODE 6 + @ 38 @ 5 +OpF0mod3: +lblF0mod3: OpF0 + NEXTOPCODE 2 + @ 18 @ 2 +OpF1M0mod3: +lblF1mod3a: DirectIndirectIndexed0 +lblF1mod3b: SBC16 + NEXTOPCODE 6 + @ 22 @ 6 +OpF2M0mod3: +lblF2mod3a: DirectIndirect +lblF2mod3b: SBC16 + NEXTOPCODE 6 + @ 22 @ 5 +OpF3M0mod3: +lblF3mod3a: StackasmRelativeIndirectIndexed0 +lblF3mod3b: SBC16 + NEXTOPCODE 8 + @ 24 @ 7 +OpF4mod3: +lblF4mod3: OpF4 + NEXTOPCODE 5 + @ 29 @ 5 +OpF5M0mod3: +lblF5mod3a: DirectIndexedX0 +lblF5mod3b: SBC16 + NEXTOPCODE 5 + @ 21 @ 4 +OpF6M0mod3: +lblF6mod3a: DirectIndexedX0 +lblF6mod3b: INC16 + NEXTOPCODE 8 + @ 24 @ 8 +OpF7M0mod3: +lblF7mod3a: DirectIndirectIndexedLong0 +lblF7mod3b: SBC16 + NEXTOPCODE 7 + @ 23 @ 6 +OpF8mod3: +lblF8mod3: OpF8 + NEXTOPCODE 2 + @ 10 @ 2 +OpF9M0mod3: +lblF9mod3a: AbsoluteIndexedY0 +lblF9mod3b: SBC16 + NEXTOPCODE 5 + @ 29 @ 5 +OpFAX0mod3: +lblFAmod3: OpFAX0 + NEXTOPCODE 4 + @ 12 @ 5 +OpFBmod3: +lblFBmod3: OpFB + NEXTOPCODE 2 + @ 10 @ 2 +OpFCmod3: +lblFCmod3: OpFCX0 + NEXTOPCODE 6 + @ 30 @ 6 +OpFDM0mod3: +lblFDmod3a: AbsoluteIndexedX0 +lblFDmod3b: SBC16 + NEXTOPCODE 5 + @ 29 @ 5 +OpFEM0mod3: +lblFEmod3a: AbsoluteIndexedX0 +lblFEmod3b: INC16 + NEXTOPCODE 9 + @ 33 @ 7 +OpFFM0mod3: +lblFFmod3a: AbsoluteLongIndexedX0 +lblFFmod3b: SBC16 + NEXTOPCODE 6 + @ 38 @ 5 +.pool + +jumptable4: .long Op00mod4 + .long Op01M0mod4 + .long Op02mod4 + .long Op03M0mod4 + .long Op04M0mod4 + .long Op05M0mod4 + .long Op06M0mod4 + .long Op07M0mod4 + .long Op08mod4 + .long Op09M0mod4 + .long Op0AM0mod4 + .long Op0Bmod4 + .long Op0CM0mod4 + .long Op0DM0mod4 + .long Op0EM0mod4 + .long Op0FM0mod4 + .long Op10mod4 + .long Op11M0mod4 + .long Op12M0mod4 + .long Op13M0mod4 + .long Op14M0mod4 + .long Op15M0mod4 + .long Op16M0mod4 + .long Op17M0mod4 + .long Op18mod4 + .long Op19M0mod4 + .long Op1AM0mod4 + .long Op1Bmod4 + .long Op1CM0mod4 + .long Op1DM0mod4 + .long Op1EM0mod4 + .long Op1FM0mod4 + .long Op20mod4 + .long Op21M0mod4 + .long Op22mod4 + .long Op23M0mod4 + .long Op24M0mod4 + .long Op25M0mod4 + .long Op26M0mod4 + .long Op27M0mod4 + .long Op28mod4 + .long Op29M0mod4 + .long Op2AM0mod4 + .long Op2Bmod4 + .long Op2CM0mod4 + .long Op2DM0mod4 + .long Op2EM0mod4 + .long Op2FM0mod4 + .long Op30mod4 + .long Op31M0mod4 + .long Op32M0mod4 + .long Op33M0mod4 + .long Op34M0mod4 + .long Op35M0mod4 + .long Op36M0mod4 + .long Op37M0mod4 + .long Op38mod4 + .long Op39M0mod4 + .long Op3AM0mod4 + .long Op3Bmod4 + .long Op3CM0mod4 + .long Op3DM0mod4 + .long Op3EM0mod4 + .long Op3FM0mod4 + .long Op40mod4 + .long Op41M0mod4 + .long Op42mod4 + .long Op43M0mod4 + .long Op44X1mod4 + .long Op45M0mod4 + .long Op46M0mod4 + .long Op47M0mod4 + .long Op48M0mod4 + .long Op49M0mod4 + .long Op4AM0mod4 + .long Op4Bmod4 + .long Op4Cmod4 + .long Op4DM0mod4 + .long Op4EM0mod4 + .long Op4FM0mod4 + .long Op50mod4 + .long Op51M0mod4 + .long Op52M0mod4 + .long Op53M0mod4 + .long Op54X1mod4 + .long Op55M0mod4 + .long Op56M0mod4 + .long Op57M0mod4 + .long Op58mod4 + .long Op59M0mod4 + .long Op5AX1mod4 + .long Op5Bmod4 + .long Op5Cmod4 + .long Op5DM0mod4 + .long Op5EM0mod4 + .long Op5FM0mod4 + .long Op60mod4 + .long Op61M0mod4 + .long Op62mod4 + .long Op63M0mod4 + .long Op64M0mod4 + .long Op65M0mod4 + .long Op66M0mod4 + .long Op67M0mod4 + + .long Op68M0mod4 + .long Op69M0mod4 + .long Op6AM0mod4 + .long Op6Bmod4 + .long Op6Cmod4 + .long Op6DM0mod4 + .long Op6EM0mod4 + .long Op6FM0mod4 + .long Op70mod4 + .long Op71M0mod4 + .long Op72M0mod4 + .long Op73M0mod4 + .long Op74M0mod4 + .long Op75M0mod4 + .long Op76M0mod4 + .long Op77M0mod4 + .long Op78mod4 + .long Op79M0mod4 + .long Op7AX1mod4 + .long Op7Bmod4 + .long Op7Cmod4 + .long Op7DM0mod4 + .long Op7EM0mod4 + .long Op7FM0mod4 + .long Op80mod4 + .long Op81M0mod4 + .long Op82mod4 + .long Op83M0mod4 + .long Op84X1mod4 + .long Op85M0mod4 + .long Op86X1mod4 + .long Op87M0mod4 + .long Op88X1mod4 + .long Op89M0mod4 + .long Op8AM0mod4 + .long Op8Bmod4 + .long Op8CX1mod4 + .long Op8DM0mod4 + .long Op8EX1mod4 + .long Op8FM0mod4 + .long Op90mod4 + .long Op91M0mod4 + .long Op92M0mod4 + .long Op93M0mod4 + .long Op94X1mod4 + .long Op95M0mod4 + .long Op96X1mod4 + .long Op97M0mod4 + .long Op98M0mod4 + .long Op99M0mod4 + .long Op9Amod4 + .long Op9BX1mod4 + .long Op9CM0mod4 + .long Op9DM0mod4 + .long Op9EM0mod4 + .long Op9FM0mod4 + .long OpA0X1mod4 + .long OpA1M0mod4 + + .long OpA2X1mod4 + .long OpA3M0mod4 + .long OpA4X1mod4 + .long OpA5M0mod4 + .long OpA6X1mod4 + .long OpA7M0mod4 + .long OpA8X1mod4 + .long OpA9M0mod4 + .long OpAAX1mod4 + .long OpABmod4 + .long OpACX1mod4 + .long OpADM0mod4 + .long OpAEX1mod4 + .long OpAFM0mod4 + .long OpB0mod4 + .long OpB1M0mod4 + .long OpB2M0mod4 + .long OpB3M0mod4 + .long OpB4X1mod4 + .long OpB5M0mod4 + .long OpB6X1mod4 + .long OpB7M0mod4 + .long OpB8mod4 + .long OpB9M0mod4 + .long OpBAX1mod4 + .long OpBBX1mod4 + .long OpBCX1mod4 + .long OpBDM0mod4 + .long OpBEX1mod4 + .long OpBFM0mod4 + .long OpC0X1mod4 + .long OpC1M0mod4 + .long OpC2mod4 + .long OpC3M0mod4 + .long OpC4X1mod4 + .long OpC5M0mod4 + .long OpC6M0mod4 + .long OpC7M0mod4 + .long OpC8X1mod4 + .long OpC9M0mod4 + .long OpCAX1mod4 + .long OpCBmod4 + .long OpCCX1mod4 + .long OpCDM0mod4 + .long OpCEM0mod4 + .long OpCFM0mod4 + .long OpD0mod4 + .long OpD1M0mod4 + .long OpD2M0mod4 + .long OpD3M0mod4 + .long OpD4mod4 + .long OpD5M0mod4 + .long OpD6M0mod4 + .long OpD7M0mod4 + .long OpD8mod4 + .long OpD9M0mod4 + .long OpDAX1mod4 + .long OpDBmod4 + .long OpDCmod4 + .long OpDDM0mod4 + .long OpDEM0mod4 + .long OpDFM0mod4 + .long OpE0X1mod4 + .long OpE1M0mod4 + .long OpE2mod4 + .long OpE3M0mod4 + .long OpE4X1mod4 + .long OpE5M0mod4 + .long OpE6M0mod4 + .long OpE7M0mod4 + .long OpE8X1mod4 + .long OpE9M0mod4 + .long OpEAmod4 + .long OpEBmod4 + .long OpECX1mod4 + .long OpEDM0mod4 + .long OpEEM0mod4 + .long OpEFM0mod4 + .long OpF0mod4 + .long OpF1M0mod4 + .long OpF2M0mod4 + .long OpF3M0mod4 + .long OpF4mod4 + .long OpF5M0mod4 + .long OpF6M0mod4 + .long OpF7M0mod4 + .long OpF8mod4 + .long OpF9M0mod4 + .long OpFAX1mod4 + .long OpFBmod4 + .long OpFCmod4 + .long OpFDM0mod4 + .long OpFEM0mod4 + .long OpFFM0mod4 +Op00mod4: +lbl00mod4: Op00 + NEXTOPCODE 8 + @ 24 @ 8 +Op01M0mod4: +lbl01mod4a: DirectIndexedIndirect1 +lbl01mod4b: ORA16 + NEXTOPCODE 7 + @ 23 @ 7 +Op02mod4: +lbl02mod4: Op02 + NEXTOPCODE 8 + @ 24 @ 8 +Op03M0mod4: +lbl03mod4a: StackasmRelative +lbl03mod4b: ORA16 + NEXTOPCODE 5 + @ 21 @ 5 +Op04M0mod4: +lbl04mod4a: Direct +lbl04mod4b: TSB16 + NEXTOPCODE 7 + @ 23 @ 7 +Op05M0mod4: +lbl05mod4a: Direct +lbl05mod4b: ORA16 + NEXTOPCODE 4 + @ 20 @ 4 +Op06M0mod4: +lbl06mod4a: Direct +lbl06mod4b: ASL16 + NEXTOPCODE 7 + @ 23 @ 7 +Op07M0mod4: +lbl07mod4a: DirectIndirectLong +lbl07mod4b: ORA16 + NEXTOPCODE 7 + @ 23 @ 7 +Op08mod4: +lbl08mod4: Op08 + NEXTOPCODE 3 + @ 11 @ 3 +Op09M0mod4: +lbl09mod4: Op09M0 + NEXTOPCODE 3 + @ 19 @ 3 +Op0AM0mod4: +lbl0Amod4a: A_ASL16 + NEXTOPCODE 2 + @ 10 @ 2 +Op0Bmod4: +lbl0Bmod4: Op0B + NEXTOPCODE 4 + @ 12 @ 4 +Op0CM0mod4: +lbl0Cmod4a: Absolute +lbl0Cmod4b: TSB16 + NEXTOPCODE 8 + @ 32 @ 8 +Op0DM0mod4: +lbl0Dmod4a: Absolute +lbl0Dmod4b: ORA16 + NEXTOPCODE 5 + @ 29 @ 5 +Op0EM0mod4: +lbl0Emod4a: Absolute +lbl0Emod4b: ASL16 + NEXTOPCODE 8 + @ 32 @ 8 +Op0FM0mod4: +lbl0Fmod4a: AbsoluteLong +lbl0Fmod4b: ORA16 + NEXTOPCODE 6 + @ 38 @ 6 +Op10mod4: +lbl10mod4: Op10 + NEXTOPCODE 2 + @ 18 @ 2 +Op11M0mod4: +lbl11mod4a: DirectIndirectIndexed1 +lbl11mod4b: ORA16 + NEXTOPCODE 7 + @ 23 @ 7 +Op12M0mod4: +lbl12mod4a: DirectIndirect +lbl12mod4b: ORA16 + NEXTOPCODE 6 + @ 22 @ 6 +Op13M0mod4: +lbl13mod4a: StackasmRelativeIndirectIndexed1 +lbl13mod4b: ORA16 + NEXTOPCODE 8 + @ 24 @ 8 +Op14M0mod4: +lbl14mod4a: Direct +lbl14mod4b: TRB16 + NEXTOPCODE 7 + @ 23 @ 7 +Op15M0mod4: +lbl15mod4a: DirectIndexedX1 +lbl15mod4b: ORA16 + NEXTOPCODE 5 + @ 21 @ 5 +Op16M0mod4: +lbl16mod4a: DirectIndexedX1 +lbl16mod4b: ASL16 + NEXTOPCODE 8 + @ 24 @ 8 +Op17M0mod4: +lbl17mod4a: DirectIndirectIndexedLong1 +lbl17mod4b: ORA16 + NEXTOPCODE 7 + @ 23 @ 7 +Op18mod4: +lbl18mod4: Op18 + NEXTOPCODE 2 + @ 10 @ 2 +Op19M0mod4: +lbl19mod4a: AbsoluteIndexedY1 +lbl19mod4b: ORA16 + NEXTOPCODE 6 + @ 30 @ 6 +Op1AM0mod4: +lbl1Amod4a: A_INC16 + NEXTOPCODE 2 + @ 10 @ 2 +Op1Bmod4: +lbl1Bmod4: Op1BM0 + NEXTOPCODE 2 + @ 10 @ 2 +Op1CM0mod4: +lbl1Cmod4a: Absolute +lbl1Cmod4b: TRB16 + NEXTOPCODE 8 + @ 32 @ 8 +Op1DM0mod4: +lbl1Dmod4a: AbsoluteIndexedX1 +lbl1Dmod4b: ORA16 + NEXTOPCODE 6 + @ 30 @ 6 +Op1EM0mod4: +lbl1Emod4a: AbsoluteIndexedX1 +lbl1Emod4b: ASL16 + NEXTOPCODE 9 + @ 33 @ 9 +Op1FM0mod4: +lbl1Fmod4a: AbsoluteLongIndexedX1 +lbl1Fmod4b: ORA16 + NEXTOPCODE 6 + @ 38 @ 6 +Op20mod4: +lbl20mod4: Op20 + NEXTOPCODE 6 + @ 30 @ 6 +Op21M0mod4: +lbl21mod4a: DirectIndexedIndirect1 +lbl21mod4b: AND16 + NEXTOPCODE 7 + @ 23 @ 7 +Op22mod4: +lbl22mod4: Op22 + NEXTOPCODE 8 + @ 40 @ 8 +Op23M0mod4: +lbl23mod4a: StackasmRelative +lbl23mod4b: AND16 + NEXTOPCODE 5 + @ 21 @ 5 +Op24M0mod4: +lbl24mod4a: Direct +lbl24mod4b: BIT16 + NEXTOPCODE 4 + @ 20 @ 4 +Op25M0mod4: +lbl25mod4a: Direct +lbl25mod4b: AND16 + NEXTOPCODE 4 + @ 20 @ 4 +Op26M0mod4: +lbl26mod4a: Direct +lbl26mod4b: ROL16 + NEXTOPCODE 7 + @ 23 @ 7 +Op27M0mod4: +lbl27mod4a: DirectIndirectLong +lbl27mod4b: AND16 + NEXTOPCODE 7 + @ 23 @ 7 +Op28mod4: +lbl28mod4: Op28X1M0 + NEXTOPCODE 4 + @ 12 @ 4 +.pool +Op29M0mod4: +lbl29mod4: Op29M0 + NEXTOPCODE 3 + @ 19 @ 3 +Op2AM0mod4: +lbl2Amod4a: A_ROL16 + NEXTOPCODE 2 + @ 10 @ 2 +Op2Bmod4: +lbl2Bmod4: Op2B + NEXTOPCODE 5 + @ 13 @ 5 +Op2CM0mod4: +lbl2Cmod4a: Absolute +lbl2Cmod4b: BIT16 + NEXTOPCODE 5 + @ 29 @ 5 +Op2DM0mod4: +lbl2Dmod4a: Absolute +lbl2Dmod4b: AND16 + NEXTOPCODE 5 + @ 29 @ 5 +Op2EM0mod4: +lbl2Emod4a: Absolute +lbl2Emod4b: ROL16 + NEXTOPCODE 8 + @ 32 @ 8 +Op2FM0mod4: +lbl2Fmod4a: AbsoluteLong +lbl2Fmod4b: AND16 + NEXTOPCODE 6 + @ 38 @ 6 +Op30mod4: +lbl30mod4: Op30 + NEXTOPCODE 2 + @ 18 @ 2 +Op31M0mod4: +lbl31mod4a: DirectIndirectIndexed1 +lbl31mod4b: AND16 + NEXTOPCODE 7 + @ 23 @ 7 +Op32M0mod4: +lbl32mod4a: DirectIndirect +lbl32mod4b: AND16 + NEXTOPCODE 6 + @ 22 @ 6 +Op33M0mod4: +lbl33mod4a: StackasmRelativeIndirectIndexed1 +lbl33mod4b: AND16 + NEXTOPCODE 8 + @ 24 @ 8 +Op34M0mod4: +lbl34mod4a: DirectIndexedX1 +lbl34mod4b: BIT16 + NEXTOPCODE 5 + @ 21 @ 5 +Op35M0mod4: +lbl35mod4a: DirectIndexedX1 +lbl35mod4b: AND16 + NEXTOPCODE 5 + @ 21 @ 5 +Op36M0mod4: +lbl36mod4a: DirectIndexedX1 +lbl36mod4b: ROL16 + NEXTOPCODE 8 + @ 24 @ 8 +Op37M0mod4: +lbl37mod4a: DirectIndirectIndexedLong1 +lbl37mod4b: AND16 + NEXTOPCODE 7 + @ 23 @ 7 +Op38mod4: +lbl38mod4: Op38 + NEXTOPCODE 2 + @ 10 @ 2 +Op39M0mod4: +lbl39mod4a: AbsoluteIndexedY1 +lbl39mod4b: AND16 + NEXTOPCODE 6 + @ 30 @ 6 +Op3AM0mod4: +lbl3Amod4a: A_DEC16 + NEXTOPCODE 2 + @ 10 @ 2 +Op3Bmod4: +lbl3Bmod4: Op3BM0 + NEXTOPCODE 2 + @ 10 @ 2 +Op3CM0mod4: +lbl3Cmod4a: AbsoluteIndexedX1 +lbl3Cmod4b: BIT16 + NEXTOPCODE 6 + @ 30 @ 6 +Op3DM0mod4: +lbl3Dmod4a: AbsoluteIndexedX1 +lbl3Dmod4b: AND16 + NEXTOPCODE 6 + @ 30 @ 6 +Op3EM0mod4: +lbl3Emod4a: AbsoluteIndexedX1 +lbl3Emod4b: ROL16 + NEXTOPCODE 9 + @ 33 @ 9 +Op3FM0mod4: +lbl3Fmod4a: AbsoluteLongIndexedX1 +lbl3Fmod4b: AND16 + NEXTOPCODE 6 + @ 38 @ 6 +Op40mod4: +lbl40mod4: Op40X1M0 + NEXTOPCODE 7 + @ 15 @ 7 +.pool +Op41M0mod4: +lbl41mod4a: DirectIndexedIndirect1 +lbl41mod4b: EOR16 + + NEXTOPCODE 7 + @ 23 @ 7 +Op42mod4: +lbl42mod4: Op42 + NEXTOPCODE 2 + @ 18 @ 2 +Op43M0mod4: +lbl43mod4a: StackasmRelative +lbl43mod4b: EOR16 + NEXTOPCODE 5 + @ 21 @ 5 +Op44X1mod4: +lbl44mod4: Op44X1M0 + NEXTOPCODE 0 + @ 24 @ 0 +Op45M0mod4: +lbl45mod4a: Direct +lbl45mod4b: EOR16 + NEXTOPCODE 4 + @ 20 @ 4 +Op46M0mod4: +lbl46mod4a: Direct +lbl46mod4b: LSR16 + NEXTOPCODE 7 + @ 23 @ 7 +Op47M0mod4: +lbl47mod4a: DirectIndirectLong +lbl47mod4b: EOR16 + NEXTOPCODE 7 + @ 23 @ 7 +Op48M0mod4: +lbl48mod4: Op48M0 + NEXTOPCODE 3 + @ 11 @ 3 +Op49M0mod4: +lbl49mod4: Op49M0 + NEXTOPCODE 3 + @ 19 @ 3 +Op4AM0mod4: +lbl4Amod4a: A_LSR16 + NEXTOPCODE 2 + @ 10 @ 2 +Op4Bmod4: +lbl4Bmod4: Op4B + NEXTOPCODE 3 + @ 11 @ 3 +Op4Cmod4: +lbl4Cmod4: Op4C + NEXTOPCODE 3 + @ 27 @ 3 +Op4DM0mod4: +lbl4Dmod4a: Absolute +lbl4Dmod4b: EOR16 + NEXTOPCODE 5 + @ 29 @ 5 +Op4EM0mod4: +lbl4Emod4a: Absolute +lbl4Emod4b: LSR16 + NEXTOPCODE 8 + @ 32 @ 8 +Op4FM0mod4: +lbl4Fmod4a: AbsoluteLong +lbl4Fmod4b: EOR16 + NEXTOPCODE 6 + @ 38 @ 6 +Op50mod4: +lbl50mod4: Op50 + NEXTOPCODE 2 + @ 18 @ 2 +Op51M0mod4: +lbl51mod4a: DirectIndirectIndexed1 +lbl51mod4b: EOR16 + NEXTOPCODE 7 + @ 23 @ 7 +Op52M0mod4: +lbl52mod4a: DirectIndirect +lbl52mod4b: EOR16 + NEXTOPCODE 6 + @ 22 @ 6 +Op53M0mod4: +lbl53mod4a: StackasmRelativeIndirectIndexed1 +lbl53mod4b: EOR16 + NEXTOPCODE 8 + @ 24 @ 8 +Op54X1mod4: +lbl54mod4: Op54X1M0 + NEXTOPCODE 0 + @ 24 @ 0 +Op55M0mod4: +lbl55mod4a: DirectIndexedX1 +lbl55mod4b: EOR16 + NEXTOPCODE 5 + @ 21 @ 5 +Op56M0mod4: +lbl56mod4a: DirectIndexedX1 +lbl56mod4b: LSR16 + NEXTOPCODE 8 + @ 24 @ 8 +Op57M0mod4: +lbl57mod4a: DirectIndirectIndexedLong1 +lbl57mod4b: EOR16 + NEXTOPCODE 7 + @ 23 @ 7 +Op58mod4: +lbl58mod4: Op58 + NEXTOPCODE 2 + @ 10 @ 2 +Op59M0mod4: +lbl59mod4a: AbsoluteIndexedY1 +lbl59mod4b: EOR16 + NEXTOPCODE 6 + @ 30 @ 6 +Op5AX1mod4: +lbl5Amod4: Op5AX1 + NEXTOPCODE 4 + @ 12 @ 4 +Op5Bmod4: +lbl5Bmod4: Op5BM0 + NEXTOPCODE 2 + @ 10 @ 2 +Op5Cmod4: +lbl5Cmod4: Op5C + NEXTOPCODE 4 + @ 36 @ 4 +Op5DM0mod4: +lbl5Dmod4a: AbsoluteIndexedX1 +lbl5Dmod4b: EOR16 + NEXTOPCODE 6 + @ 30 @ 6 +Op5EM0mod4: +lbl5Emod4a: AbsoluteIndexedX1 +lbl5Emod4b: LSR16 + NEXTOPCODE 9 + @ 33 @ 9 +Op5FM0mod4: +lbl5Fmod4a: AbsoluteLongIndexedX1 +lbl5Fmod4b: EOR16 + NEXTOPCODE 6 + @ 38 @ 6 +Op60mod4: +lbl60mod4: Op60 + NEXTOPCODE 6 + @ 14 @ 6 +Op61M0mod4: +lbl61mod4a: DirectIndexedIndirect1 +lbl61mod4b: ADC16 + NEXTOPCODE 7 + @ 23 @ 7 +Op62mod4: +lbl62mod4: Op62 + NEXTOPCODE 6 + @ 30 @ 6 +Op63M0mod4: +lbl63mod4a: StackasmRelative +lbl63mod4b: ADC16 + NEXTOPCODE 5 + @ 21 @ 5 +.pool +Op64M0mod4: +lbl64mod4a: Direct +lbl64mod4b: STZ16 + NEXTOPCODE 4 + @ 20 @ 4 +Op65M0mod4: +lbl65mod4a: Direct +lbl65mod4b: ADC16 + NEXTOPCODE 4 + @ 20 @ 4 +.pool +Op66M0mod4: +lbl66mod4a: Direct +lbl66mod4b: ROR16 + NEXTOPCODE 7 + @ 23 @ 7 +Op67M0mod4: +lbl67mod4a: DirectIndirectLong +lbl67mod4b: ADC16 + NEXTOPCODE 7 + @ 23 @ 7 +.pool +Op68M0mod4: +lbl68mod4: Op68M0 + NEXTOPCODE 4 + @ 12 @ 4 +Op69M0mod4: +lbl69mod4a: Immediate16 +lbl69mod4b: ADC16 + NEXTOPCODE 3 + @ 19 @ 3 +.pool +Op6AM0mod4: +lbl6Amod4a: A_ROR16 + NEXTOPCODE 2 + @ 10 @ 2 +Op6Bmod4: +lbl6Bmod4: Op6B + NEXTOPCODE 6 + @ 14 @ 6 +Op6Cmod4: +lbl6Cmod4: Op6C + NEXTOPCODE 5 + @ 29 @ 5 +Op6DM0mod4: +lbl6Dmod4a: Absolute +lbl6Dmod4b: ADC16 + NEXTOPCODE 5 + @ 29 @ 5 +Op6EM0mod4: +lbl6Emod4a: Absolute +lbl6Emod4b: ROR16 + NEXTOPCODE 8 + @ 32 @ 8 +Op6FM0mod4: +lbl6Fmod4a: AbsoluteLong +lbl6Fmod4b: ADC16 + NEXTOPCODE 6 + @ 38 @ 6 +Op70mod4: +lbl70mod4: Op70 + NEXTOPCODE 2 + @ 18 @ 2 +Op71M0mod4: +lbl71mod4a: DirectIndirectIndexed1 +lbl71mod4b: ADC16 + NEXTOPCODE 7 + @ 23 @ 7 +Op72M0mod4: +lbl72mod4a: DirectIndirect +lbl72mod4b: ADC16 + NEXTOPCODE 6 + @ 22 @ 6 +Op73M0mod4: +lbl73mod4a: StackasmRelativeIndirectIndexed1 +lbl73mod4b: ADC16 + NEXTOPCODE 8 + @ 24 @ 8 +.pool +Op74M0mod4: +lbl74mod4a: DirectIndexedX1 +lbl74mod4b: STZ16 + NEXTOPCODE 5 + @ 21 @ 5 +Op75M0mod4: +lbl75mod4a: DirectIndexedX1 +lbl75mod4b: ADC16 + NEXTOPCODE 5 + @ 21 @ 5 +.pool +Op76M0mod4: +lbl76mod4a: DirectIndexedX1 +lbl76mod4b: ROR16 + NEXTOPCODE 8 + @ 24 @ 8 +Op77M0mod4: +lbl77mod4a: DirectIndirectIndexedLong1 +lbl77mod4b: ADC16 + NEXTOPCODE 7 + @ 23 @ 7 +Op78mod4: +lbl78mod4: Op78 + NEXTOPCODE 2 + @ 10 @ 2 +Op79M0mod4: +lbl79mod4a: AbsoluteIndexedY1 +lbl79mod4b: ADC16 + NEXTOPCODE 6 + @ 30 @ 6 +Op7AX1mod4: +lbl7Amod4: Op7AX1 + NEXTOPCODE 5 + @ 13 @ 5 +Op7Bmod4: +lbl7Bmod4: Op7BM0 + NEXTOPCODE 2 + @ 10 @ 2 +Op7Cmod4: +lbl7Cmod4: AbsoluteIndexedIndirectX1 + Op7C + NEXTOPCODE 6 + @ 30 @ 6 +Op7DM0mod4: +lbl7Dmod4a: AbsoluteIndexedX1 +lbl7Dmod4b: ADC16 + NEXTOPCODE 6 + @ 30 @ 6 +Op7EM0mod4: +lbl7Emod4a: AbsoluteIndexedX1 +lbl7Emod4b: ROR16 + NEXTOPCODE 9 + @ 33 @ 9 +Op7FM0mod4: +lbl7Fmod4a: AbsoluteLongIndexedX1 +lbl7Fmod4b: ADC16 + NEXTOPCODE 6 + @ 38 @ 6 +.pool +Op80mod4: +lbl80mod4: Op80 + NEXTOPCODE 2 + @ 18 @ 2 +Op81M0mod4: +lbl81mod4a: DirectIndexedIndirect1 +lbl81mod4b: Op81M0 + NEXTOPCODE 7 + @ 23 @ 7 +Op82mod4: +lbl82mod4: Op82 + NEXTOPCODE 3 + @ 27 @ 3 +Op83M0mod4: +lbl83mod4a: StackasmRelative +lbl83mod4b: STA16 + NEXTOPCODE 5 + @ 21 @ 5 +Op84X1mod4: +lbl84mod4a: Direct +lbl84mod4b: STY8 + NEXTOPCODE 4 + @ 20 @ 4 +Op85M0mod4: +lbl85mod4a: Direct +lbl85mod4b: STA16 + NEXTOPCODE 4 + @ 20 @ 4 +Op86X1mod4: +lbl86mod4a: Direct +lbl86mod4b: STX8 + NEXTOPCODE 4 + @ 20 @ 4 +Op87M0mod4: +lbl87mod4a: DirectIndirectLong +lbl87mod4b: STA16 + NEXTOPCODE 7 + @ 23 @ 7 +Op88X1mod4: +lbl88mod4: Op88X1 + NEXTOPCODE 2 + @ 10 @ 2 +Op89M0mod4: +lbl89mod4: Op89M0 + NEXTOPCODE 3 + @ 19 @ 3 +Op8AM0mod4: +lbl8Amod4: Op8AM0X1 + NEXTOPCODE 2 + @ 10 @ 2 +Op8Bmod4: +lbl8Bmod4: Op8B + NEXTOPCODE 3 + @ 11 @ 3 +Op8CX1mod4: +lbl8Cmod4a: Absolute +lbl8Cmod4b: STY8 + NEXTOPCODE 5 + @ 29 @ 5 +Op8DM0mod4: +lbl8Dmod4a: Absolute +lbl8Dmod4b: STA16 + NEXTOPCODE 5 + @ 29 @ 5 +Op8EX1mod4: +lbl8Emod4a: Absolute +lbl8Emod4b: STX8 + NEXTOPCODE 5 + @ 29 @ 5 +Op8FM0mod4: +lbl8Fmod4a: AbsoluteLong +lbl8Fmod4b: STA16 + NEXTOPCODE 6 + @ 38 @ 6 +Op90mod4: +lbl90mod4: Op90 + NEXTOPCODE 2 + @ 18 @ 2 +Op91M0mod4: +lbl91mod4a: DirectIndirectIndexed1 +lbl91mod4b: STA16 + NEXTOPCODE 7 + @ 23 @ 7 +Op92M0mod4: +lbl92mod4a: DirectIndirect +lbl92mod4b: STA16 + NEXTOPCODE 6 + @ 22 @ 6 +Op93M0mod4: +lbl93mod4a: StackasmRelativeIndirectIndexed1 +lbl93mod4b: STA16 + NEXTOPCODE 8 + @ 24 @ 8 +Op94X1mod4: +lbl94mod4a: DirectIndexedX1 +lbl94mod4b: STY8 + NEXTOPCODE 5 + @ 21 @ 5 +Op95M0mod4: +lbl95mod4a: DirectIndexedX1 +lbl95mod4b: STA16 + NEXTOPCODE 5 + @ 21 @ 5 +Op96X1mod4: +lbl96mod4a: DirectIndexedY1 +lbl96mod4b: STX8 + NEXTOPCODE 5 + @ 21 @ 5 +Op97M0mod4: +lbl97mod4a: DirectIndirectIndexedLong1 +lbl97mod4b: STA16 + NEXTOPCODE 7 + @ 23 @ 7 +Op98M0mod4: +lbl98mod4: Op98M0X1 + NEXTOPCODE 2 + @ 10 @ 2 +Op99M0mod4: +lbl99mod4a: AbsoluteIndexedY1 +lbl99mod4b: STA16 + NEXTOPCODE 6 + @ 30 @ 6 +Op9Amod4: +lbl9Amod4: Op9AX1 + NEXTOPCODE 2 + @ 10 @ 2 +Op9BX1mod4: +lbl9Bmod4: Op9BX1 + NEXTOPCODE 2 + @ 10 @ 2 +Op9CM0mod4: +lbl9Cmod4a: Absolute +lbl9Cmod4b: STZ16 + NEXTOPCODE 5 + @ 29 @ 5 +Op9DM0mod4: +lbl9Dmod4a: AbsoluteIndexedX1 +lbl9Dmod4b: STA16 + NEXTOPCODE 6 + @ 30 @ 6 +Op9EM0mod4: +lbl9Emod4: AbsoluteIndexedX1 + STZ16 + NEXTOPCODE 6 + @ 30 @ 6 +Op9FM0mod4: +lbl9Fmod4a: AbsoluteLongIndexedX1 +lbl9Fmod4b: STA16 + NEXTOPCODE 6 + @ 38 @ 6 +OpA0X1mod4: +lblA0mod4: OpA0X1 + NEXTOPCODE 3 + @ 19 @ 3 +OpA1M0mod4: +lblA1mod4a: DirectIndexedIndirect1 +lblA1mod4b: LDA16 + NEXTOPCODE 7 + @ 23 @ 7 +OpA2X1mod4: +lblA2mod4: OpA2X1 + NEXTOPCODE 3 + @ 19 @ 3 +OpA3M0mod4: +lblA3mod4a: StackasmRelative +lblA3mod4b: LDA16 + NEXTOPCODE 5 + @ 21 @ 5 +OpA4X1mod4: +lblA4mod4a: Direct +lblA4mod4b: LDY8 + NEXTOPCODE 4 + @ 20 @ 4 +OpA5M0mod4: +lblA5mod4a: Direct +lblA5mod4b: LDA16 + NEXTOPCODE 4 + @ 20 @ 4 +OpA6X1mod4: +lblA6mod4a: Direct +lblA6mod4b: LDX8 + NEXTOPCODE 4 + @ 20 @ 4 +OpA7M0mod4: +lblA7mod4a: DirectIndirectLong +lblA7mod4b: LDA16 + NEXTOPCODE 7 + @ 23 @ 7 +OpA8X1mod4: +lblA8mod4: OpA8X1M0 + NEXTOPCODE 2 + @ 10 @ 2 +OpA9M0mod4: +lblA9mod4: OpA9M0 + NEXTOPCODE 3 + @ 19 @ 3 +OpAAX1mod4: +lblAAmod4: OpAAX1M0 + NEXTOPCODE 2 + @ 10 @ 2 +OpABmod4: +lblABmod4: OpAB + NEXTOPCODE 4 + @ 12 @ 4 +OpACX1mod4: +lblACmod4a: Absolute +lblACmod4b: LDY8 + NEXTOPCODE 5 + @ 29 @ 5 +OpADM0mod4: +lblADmod4a: Absolute +lblADmod4b: LDA16 + NEXTOPCODE 5 + @ 29 @ 5 +OpAEX1mod4: +lblAEmod4a: Absolute +lblAEmod4b: LDX8 + NEXTOPCODE 5 + @ 29 @ 5 +OpAFM0mod4: +lblAFmod4a: AbsoluteLong +lblAFmod4b: LDA16 + NEXTOPCODE 6 + @ 38 @ 6 +OpB0mod4: +lblB0mod4: OpB0 + NEXTOPCODE 2 + @ 18 @ 2 +OpB1M0mod4: +lblB1mod4a: DirectIndirectIndexed1 +lblB1mod4b: LDA16 + NEXTOPCODE 7 + @ 23 @ 7 +OpB2M0mod4: +lblB2mod4a: DirectIndirect +lblB2mod4b: LDA16 + NEXTOPCODE 6 + @ 22 @ 6 +OpB3M0mod4: +lblB3mod4a: StackasmRelativeIndirectIndexed1 +lblB3mod4b: LDA16 + NEXTOPCODE 8 + @ 24 @ 8 +OpB4X1mod4: +lblB4mod4a: DirectIndexedX1 +lblB4mod4b: LDY8 + NEXTOPCODE 5 + @ 21 @ 5 +OpB5M0mod4: +lblB5mod4a: DirectIndexedX1 +lblB5mod4b: LDA16 + NEXTOPCODE 5 + @ 21 @ 5 +OpB6X1mod4: +lblB6mod4a: DirectIndexedY1 +lblB6mod4b: LDX8 + NEXTOPCODE 5 + @ 21 @ 5 +OpB7M0mod4: +lblB7mod4a: DirectIndirectIndexedLong1 +lblB7mod4b: LDA16 + NEXTOPCODE 7 + @ 23 @ 7 +OpB8mod4: +lblB8mod4: OpB8 + NEXTOPCODE 2 + @ 10 @ 2 +OpB9M0mod4: +lblB9mod4a: AbsoluteIndexedY1 +lblB9mod4b: LDA16 + NEXTOPCODE 6 + @ 30 @ 6 +OpBAX1mod4: +lblBAmod4: OpBAX1 + NEXTOPCODE 2 + @ 10 @ 2 +OpBBX1mod4: +lblBBmod4: OpBBX1 + NEXTOPCODE 2 + @ 10 @ 2 +OpBCX1mod4: +lblBCmod4a: AbsoluteIndexedX1 +lblBCmod4b: LDY8 + NEXTOPCODE 5 + @ 29 @ 5 +OpBDM0mod4: +lblBDmod4a: AbsoluteIndexedX1 +lblBDmod4b: LDA16 + NEXTOPCODE 6 + @ 30 @ 6 +OpBEX1mod4: +lblBEmod4a: AbsoluteIndexedY1 +lblBEmod4b: LDX8 + NEXTOPCODE 5 + @ 29 @ 5 +OpBFM0mod4: +lblBFmod4a: AbsoluteLongIndexedX1 +lblBFmod4b: LDA16 + NEXTOPCODE 6 + @ 38 @ 6 +OpC0X1mod4: +lblC0mod4: OpC0X1 + NEXTOPCODE 3 + @ 19 @ 3 +OpC1M0mod4: +lblC1mod4a: DirectIndexedIndirect1 +lblC1mod4b: CMP16 + NEXTOPCODE 7 + @ 23 @ 7 +OpC2mod4: +lblC2mod4: OpC2 + NEXTOPCODE 3 + @ 19 @ 3 +.pool +OpC3M0mod4: +lblC3mod4a: StackasmRelative +lblC3mod4b: CMP16 + NEXTOPCODE 5 + @ 21 @ 5 +OpC4X1mod4: +lblC4mod4a: Direct +lblC4mod4b: CMY8 + NEXTOPCODE 4 + @ 20 @ 4 +OpC5M0mod4: +lblC5mod4a: Direct +lblC5mod4b: CMP16 + NEXTOPCODE 4 + @ 20 @ 4 +OpC6M0mod4: +lblC6mod4a: Direct +lblC6mod4b: DEC16 + NEXTOPCODE 7 + @ 23 @ 7 +OpC7M0mod4: +lblC7mod4a: DirectIndirectLong +lblC7mod4b: CMP16 + NEXTOPCODE 7 + @ 23 @ 7 +OpC8X1mod4: +lblC8mod4: OpC8X1 + NEXTOPCODE 2 + @ 10 @ 2 +OpC9M0mod4: +lblC9mod4: OpC9M0 + NEXTOPCODE 3 + @ 19 @ 3 +OpCAX1mod4: +lblCAmod4: OpCAX1 + NEXTOPCODE 2 + @ 10 @ 2 +OpCBmod4: +lblCBmod4: OpCB + NEXTOPCODE 3 + @ 11 @ 3 +OpCCX1mod4: +lblCCmod4a: Absolute +lblCCmod4b: CMY8 + NEXTOPCODE 5 + @ 29 @ 5 +OpCDM0mod4: +lblCDmod4a: Absolute +lblCDmod4b: CMP16 + NEXTOPCODE 5 + @ 29 @ 5 +OpCEM0mod4: +lblCEmod4a: Absolute +lblCEmod4b: DEC16 + NEXTOPCODE 8 + @ 32 @ 8 +OpCFM0mod4: +lblCFmod4a: AbsoluteLong +lblCFmod4b: CMP16 + NEXTOPCODE 6 + @ 38 @ 6 +OpD0mod4: +lblD0mod4: OpD0 + NEXTOPCODE 2 + @ 18 @ 2 +OpD1M0mod4: +lblD1mod4a: DirectIndirectIndexed1 +lblD1mod4b: CMP16 + NEXTOPCODE 7 + @ 23 @ 7 +OpD2M0mod4: +lblD2mod4a: DirectIndirect +lblD2mod4b: CMP16 + NEXTOPCODE 6 + @ 22 @ 6 +OpD3M0mod4: +lblD3mod4a: StackasmRelativeIndirectIndexed1 +lblD3mod4b: CMP16 + NEXTOPCODE 8 + @ 24 @ 8 +OpD4mod4: +lblD4mod4: OpD4 + NEXTOPCODE 6 + @ 22 @ 6 +OpD5M0mod4: +lblD5mod4a: DirectIndexedX1 +lblD5mod4b: CMP16 + NEXTOPCODE 5 + @ 21 @ 5 +OpD6M0mod4: +lblD6mod4a: DirectIndexedX1 +lblD6mod4b: DEC16 + NEXTOPCODE 8 + @ 24 @ 8 +OpD7M0mod4: +lblD7mod4a: DirectIndirectIndexedLong1 +lblD7mod4b: CMP16 + NEXTOPCODE 7 + @ 23 @ 7 +OpD8mod4: +lblD8mod4: OpD8 + NEXTOPCODE 2 + @ 10 @ 2 +OpD9M0mod4: +lblD9mod4a: AbsoluteIndexedY1 +lblD9mod4b: CMP16 + NEXTOPCODE 6 + @ 30 @ 6 +OpDAX1mod4: +lblDAmod4: OpDAX1 + NEXTOPCODE 4 + @ 12 @ 4 +OpDBmod4: +lblDBmod4: OpDB + NEXTOPCODE 3 + @ 11 @ 3 +OpDCmod4: +lblDCmod4: OpDC + NEXTOPCODE 6 + @ 30 @ 6 +OpDDM0mod4: +lblDDmod4a: AbsoluteIndexedX1 +lblDDmod4b: CMP16 + NEXTOPCODE 6 + @ 30 @ 6 +OpDEM0mod4: +lblDEmod4a: AbsoluteIndexedX1 +lblDEmod4b: DEC16 + NEXTOPCODE 9 + @ 33 @ 9 +OpDFM0mod4: +lblDFmod4a: AbsoluteLongIndexedX1 +lblDFmod4b: CMP16 + NEXTOPCODE 6 + @ 38 @ 6 +OpE0X1mod4: +lblE0mod4: OpE0X1 + NEXTOPCODE 3 + @ 19 @ 3 +OpE1M0mod4: +lblE1mod4a: DirectIndexedIndirect1 +lblE1mod4b: SBC16 + NEXTOPCODE 7 + @ 23 @ 7 +OpE2mod4: +lblE2mod4: OpE2 + NEXTOPCODE 3 + @ 19 @ 3 +.pool +OpE3M0mod4: +lblE3mod4a: StackasmRelative +lblE3mod4b: SBC16 + NEXTOPCODE 5 + @ 21 @ 5 +OpE4X1mod4: +lblE4mod4a: Direct +lblE4mod4b: CMX8 + NEXTOPCODE 4 + @ 20 @ 4 +OpE5M0mod4: +lblE5mod4a: Direct +lblE5mod4b: SBC16 + NEXTOPCODE 4 + @ 20 @ 4 +OpE6M0mod4: +lblE6mod4a: Direct +lblE6mod4b: INC16 + NEXTOPCODE 7 + @ 23 @ 7 +OpE7M0mod4: +lblE7mod4a: DirectIndirectLong +lblE7mod4b: SBC16 + NEXTOPCODE 7 + @ 23 @ 7 +OpE8X1mod4: +lblE8mod4: OpE8X1 + NEXTOPCODE 2 + @ 10 @ 2 +OpE9M0mod4: +lblE9mod4a: Immediate16 +lblE9mod4b: SBC16 + NEXTOPCODE 3 + @ 19 @ 3 +OpEAmod4: +lblEAmod4: OpEA + NEXTOPCODE 2 + @ 10 @ 2 +OpEBmod4: +lblEBmod4: OpEBM0 + NEXTOPCODE 3 + @ 11 @ 3 +OpECX1mod4: +lblECmod4a: Absolute +lblECmod4b: CMX8 + NEXTOPCODE 5 + @ 29 @ 5 +OpEDM0mod4: +lblEDmod4a: Absolute +lblEDmod4b: SBC16 + NEXTOPCODE 5 + @ 29 @ 5 +OpEEM0mod4: +lblEEmod4a: Absolute +lblEEmod4b: INC16 + NEXTOPCODE 8 + @ 32 @ 8 +OpEFM0mod4: +lblEFmod4a: AbsoluteLong +lblEFmod4b: SBC16 + NEXTOPCODE 6 + @ 38 @ 6 +OpF0mod4: +lblF0mod4: OpF0 + NEXTOPCODE 2 + @ 18 @ 2 +OpF1M0mod4: +lblF1mod4a: DirectIndirectIndexed1 +lblF1mod4b: SBC16 + NEXTOPCODE 7 + @ 23 @ 7 +OpF2M0mod4: +lblF2mod4a: DirectIndirect +lblF2mod4b: SBC16 + NEXTOPCODE 6 + @ 22 @ 6 +OpF3M0mod4: +lblF3mod4a: StackasmRelativeIndirectIndexed1 +lblF3mod4b: SBC16 + NEXTOPCODE 8 + @ 24 @ 8 +OpF4mod4: +lblF4mod4: OpF4 + NEXTOPCODE 5 + @ 29 @ 5 +OpF5M0mod4: +lblF5mod4a: DirectIndexedX1 +lblF5mod4b: SBC16 + NEXTOPCODE 5 + @ 21 @ 5 +OpF6M0mod4: +lblF6mod4a: DirectIndexedX1 +lblF6mod4b: INC16 + NEXTOPCODE 8 + @ 24 @ 8 +OpF7M0mod4: +lblF7mod4a: DirectIndirectIndexedLong1 +lblF7mod4b: SBC16 + NEXTOPCODE 7 + @ 23 @ 7 +OpF8mod4: +lblF8mod4: OpF8 + NEXTOPCODE 2 + @ 10 @ 2 +OpF9M0mod4: +lblF9mod4a: AbsoluteIndexedY1 +lblF9mod4b: SBC16 + NEXTOPCODE 6 + @ 30 @ 6 +OpFAX1mod4: +lblFAmod4: OpFAX1 + NEXTOPCODE 5 + @ 13 @ 5 +OpFBmod4: +lblFBmod4: OpFB + NEXTOPCODE 2 + @ 10 @ 2 +OpFCmod4: +lblFCmod4: OpFCX1 + NEXTOPCODE 6 + @ 30 @ 6 +OpFDM0mod4: +lblFDmod4a: AbsoluteIndexedX1 +lblFDmod4b: SBC16 + NEXTOPCODE 6 + @ 30 @ 6 +OpFEM0mod4: +lblFEmod4a: AbsoluteIndexedX1 +lblFEmod4b: INC16 + NEXTOPCODE 9 + @ 33 @ 9 +OpFFM0mod4: +lblFFmod4a: AbsoluteLongIndexedX1 +lblFFmod4b: SBC16 + NEXTOPCODE 6 + @ 38 @ 6 + + + .pool + diff --git a/src/pixform.h b/src/pixform.h new file mode 100644 index 0000000..c0a49c5 --- /dev/null +++ b/src/pixform.h @@ -0,0 +1,272 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _PIXFORM_H_ +#define _PIXFORM_H_ + +#ifdef GFX_MULTI_FORMAT + +enum { RGB565, RGB555, BGR565, BGR555, GBR565, GBR555, RGB5551 }; + +#define BUILD_PIXEL(R,G,B) ((*GFX.BuildPixel) (R, G, B)) +#define BUILD_PIXEL2(R,G,B) ((*GFX.BuildPixel2) (R, G, B)) +#define DECOMPOSE_PIXEL(Pixel,R,G,B) ((*GFX.DecomposePixel) (Pixel, R,G,B)) + +extern uint32 RED_LOW_BIT_MASK; +extern uint32 GREEN_LOW_BIT_MASK; +extern uint32 BLUE_LOW_BIT_MASK; +extern uint32 RED_HI_BIT_MASK; +extern uint32 GREEN_HI_BIT_MASK; +extern uint32 BLUE_HI_BIT_MASK; +extern uint32 MAX_RED; +extern uint32 MAX_GREEN; +extern uint32 MAX_BLUE; +extern uint32 SPARE_RGB_BIT_MASK; +extern uint32 GREEN_HI_BIT; +extern uint32 RGB_LOW_BITS_MASK; +extern uint32 RGB_HI_BITS_MASK; +extern uint32 RGB_HI_BITS_MASKx2; +extern uint32 RGB_REMOVE_LOW_BITS_MASK; +extern uint32 FIRST_COLOR_MASK; +extern uint32 SECOND_COLOR_MASK; +extern uint32 THIRD_COLOR_MASK; +extern uint32 ALPHA_BITS_MASK; +extern uint32 FIRST_THIRD_COLOR_MASK; +extern uint32 TWO_LOW_BITS_MASK; +extern uint32 HIGH_BITS_SHIFTED_TWO_MASK; + +#endif + +// RGB565 format +#define BUILD_PIXEL_RGB565(R,G,B) (((int) (R) << 11) | ((int) (G) << 6) | (int) (B)) +#define BUILD_PIXEL2_RGB565(R,G,B) (((int) (R) << 11) | ((int) (G) << 5) | (int) (B)) +#define DECOMPOSE_PIXEL_RGB565(PIX,R,G,B) {(R) = (PIX) >> 11; (G) = ((PIX) >> 6) & 0x1f; (B) = (PIX) & 0x1f; } +#define SPARE_RGB_BIT_MASK_RGB565 (1 << 5) + +#define MAX_RED_RGB565 31 +#define MAX_GREEN_RGB565 63 +#define MAX_BLUE_RGB565 31 +#define RED_LOW_BIT_MASK_RGB565 0x0800 +#define GREEN_LOW_BIT_MASK_RGB565 0x0020 +#define BLUE_LOW_BIT_MASK_RGB565 0x0001 +#define RED_HI_BIT_MASK_RGB565 0x8000 +#define GREEN_HI_BIT_MASK_RGB565 0x0400 +#define BLUE_HI_BIT_MASK_RGB565 0x0010 +#define FIRST_COLOR_MASK_RGB565 0xF800 +#define SECOND_COLOR_MASK_RGB565 0x07E0 +#define THIRD_COLOR_MASK_RGB565 0x001F +#define ALPHA_BITS_MASK_RGB565 0x0000 + +// RGB555 format +#define BUILD_PIXEL_RGB555(R,G,B) (((int) (R) << 10) | ((int) (G) << 5) | (int) (B)) +#define BUILD_PIXEL2_RGB555(R,G,B) (((int) (R) << 10) | ((int) (G) << 5) | (int) (B)) +#define DECOMPOSE_PIXEL_RGB555(PIX,R,G,B) {(R) = (PIX) >> 10; (G) = ((PIX) >> 5) & 0x1f; (B) = (PIX) & 0x1f; } +#define SPARE_RGB_BIT_MASK_RGB555 (1 << 15) + +#define MAX_RED_RGB555 31 +#define MAX_GREEN_RGB555 31 +#define MAX_BLUE_RGB555 31 +#define RED_LOW_BIT_MASK_RGB555 0x0400 +#define GREEN_LOW_BIT_MASK_RGB555 0x0020 +#define BLUE_LOW_BIT_MASK_RGB555 0x0001 +#define RED_HI_BIT_MASK_RGB555 0x4000 +#define GREEN_HI_BIT_MASK_RGB555 0x0200 +#define BLUE_HI_BIT_MASK_RGB555 0x0010 +#define FIRST_COLOR_MASK_RGB555 0x7C00 +#define SECOND_COLOR_MASK_RGB555 0x03E0 +#define THIRD_COLOR_MASK_RGB555 0x001F +#define ALPHA_BITS_MASK_RGB555 0x0000 + +// BGR565 format +#define BUILD_PIXEL_BGR565(R,G,B) (((int) (B) << 11) | ((int) (G) << 6) | (int) (R)) +#define BUILD_PIXEL2_BGR565(R,G,B) (((int) (B) << 11) | ((int) (G) << 5) | (int) (R)) +#define DECOMPOSE_PIXEL_BGR565(PIX,R,G,B) {(B) = (PIX) >> 11; (G) = ((PIX) >> 6) & 0x1f; (R) = (PIX) & 0x1f; } +#define SPARE_RGB_BIT_MASK_BGR565 (1 << 5) + +#define MAX_RED_BGR565 31 +#define MAX_GREEN_BGR565 63 +#define MAX_BLUE_BGR565 31 +#define RED_LOW_BIT_MASK_BGR565 0x0001 +#define GREEN_LOW_BIT_MASK_BGR565 0x0040 +#define BLUE_LOW_BIT_MASK_BGR565 0x0800 +#define RED_HI_BIT_MASK_BGR565 0x0010 +#define GREEN_HI_BIT_MASK_BGR565 0x0400 +#define BLUE_HI_BIT_MASK_BGR565 0x8000 +#define FIRST_COLOR_MASK_BGR565 0xF800 +#define SECOND_COLOR_MASK_BGR565 0x07E0 +#define THIRD_COLOR_MASK_BGR565 0x001F +#define ALPHA_BITS_MASK_BGR565 0x0000 + +// BGR555 format +#define BUILD_PIXEL_BGR555(R,G,B) (((int) (B) << 10) | ((int) (G) << 5) | (int) (R)) +#define BUILD_PIXEL2_BGR555(R,G,B) (((int) (B) << 10) | ((int) (G) << 5) | (int) (R)) +#define DECOMPOSE_PIXEL_BGR555(PIX,R,G,B) {(B) = (PIX) >> 10; (G) = ((PIX) >> 5) & 0x1f; (R) = (PIX) & 0x1f; } +#define SPARE_RGB_BIT_MASK_BGR555 (1 << 15) + +#define MAX_RED_BGR555 31 +#define MAX_GREEN_BGR555 31 +#define MAX_BLUE_BGR555 31 +#define RED_LOW_BIT_MASK_BGR555 0x0001 +#define GREEN_LOW_BIT_MASK_BGR555 0x0020 +#define BLUE_LOW_BIT_MASK_BGR555 0x0400 +#define RED_HI_BIT_MASK_BGR555 0x0010 +#define GREEN_HI_BIT_MASK_BGR555 0x0200 +#define BLUE_HI_BIT_MASK_BGR555 0x4000 +#define FIRST_COLOR_MASK_BGR555 0x7C00 +#define SECOND_COLOR_MASK_BGR555 0x03E0 +#define THIRD_COLOR_MASK_BGR555 0x001F +#define ALPHA_BITS_MASK_BGR555 0x0000 + +// GBR565 format +#define BUILD_PIXEL_GBR565(R,G,B) (((int) (G) << 11) | ((int) (B) << 6) | (int) (R)) +#define BUILD_PIXEL2_GBR565(R,G,B) (((int) (G) << 11) | ((int) (B) << 5) | (int) (R)) +#define DECOMPOSE_PIXEL_GBR565(PIX,R,G,B) {(G) = (PIX) >> 11; (B) = ((PIX) >> 6) & 0x1f; (R) = (PIX) & 0x1f; } +#define SPARE_RGB_BIT_MASK_GBR565 (1 << 5) + +#define MAX_RED_GBR565 31 +#define MAX_BLUE_GBR565 63 +#define MAX_GREEN_GBR565 31 +#define RED_LOW_BIT_MASK_GBR565 0x0001 +#define BLUE_LOW_BIT_MASK_GBR565 0x0040 +#define GREEN_LOW_BIT_MASK_GBR565 0x0800 +#define RED_HI_BIT_MASK_GBR565 0x0010 +#define BLUE_HI_BIT_MASK_GBR565 0x0400 +#define GREEN_HI_BIT_MASK_GBR565 0x8000 +#define FIRST_COLOR_MASK_GBR565 0xF800 +#define SECOND_COLOR_MASK_GBR565 0x07E0 +#define THIRD_COLOR_MASK_GBR565 0x001F +#define ALPHA_BITS_MASK_GBR565 0x0000 + +// GBR555 format +#define BUILD_PIXEL_GBR555(R,G,B) (((int) (G) << 10) | ((int) (B) << 5) | (int) (R)) +#define BUILD_PIXEL2_GBR555(R,G,B) (((int) (G) << 10) | ((int) (B) << 5) | (int) (R)) +#define DECOMPOSE_PIXEL_GBR555(PIX,R,G,B) {(G) = (PIX) >> 10; (B) = ((PIX) >> 5) & 0x1f; (R) = (PIX) & 0x1f; } +#define SPARE_RGB_BIT_MASK_GBR555 (1 << 15) + +#define MAX_RED_GBR555 31 +#define MAX_BLUE_GBR555 31 +#define MAX_GREEN_GBR555 31 +#define RED_LOW_BIT_MASK_GBR555 0x0001 +#define BLUE_LOW_BIT_MASK_GBR555 0x0020 +#define GREEN_LOW_BIT_MASK_GBR555 0x0400 +#define RED_HI_BIT_MASK_GBR555 0x0010 +#define BLUE_HI_BIT_MASK_GBR555 0x0200 +#define GREEN_HI_BIT_MASK_GBR555 0x4000 +#define FIRST_COLOR_MASK_GBR555 0x7C00 +#define SECOND_COLOR_MASK_GBR555 0x03E0 +#define THIRD_COLOR_MASK_GBR555 0x001F +#define ALPHA_BITS_MASK_GBR555 0x0000 + +// RGB5551 format +#define BUILD_PIXEL_RGB5551(R,G,B) (((int) (R) << 11) | ((int) (G) << 6) | (int) ((B) << 1) | 1) +#define BUILD_PIXEL2_RGB5551(R,G,B) (((int) (R) << 11) | ((int) (G) << 6) | (int) ((B) << 1) | 1) +#define DECOMPOSE_PIXEL_RGB5551(PIX,R,G,B) {(R) = (PIX) >> 11; (G) = ((PIX) >> 6) & 0x1f; (B) = ((PIX) >> 1) & 0x1f; } +#define SPARE_RGB_BIT_MASK_RGB5551 (1) + +#define MAX_RED_RGB5551 31 +#define MAX_GREEN_RGB5551 31 +#define MAX_BLUE_RGB5551 31 +#define RED_LOW_BIT_MASK_RGB5551 0x0800 +#define GREEN_LOW_BIT_MASK_RGB5551 0x0040 +#define BLUE_LOW_BIT_MASK_RGB5551 0x0002 +#define RED_HI_BIT_MASK_RGB5551 0x8000 +#define GREEN_HI_BIT_MASK_RGB5551 0x0400 +#define BLUE_HI_BIT_MASK_RGB5551 0x0020 +#define FIRST_COLOR_MASK_RGB5551 0xf800 +#define SECOND_COLOR_MASK_RGB5551 0x07c0 +#define THIRD_COLOR_MASK_RGB5551 0x003e +#define ALPHA_BITS_MASK_RGB5551 0x0001 + +#ifndef GFX_MULTI_FORMAT +#define CONCAT(X,Y) X##Y + +// C pre-processor needs a two stage macro define to enable it to concat +// to macro names together to form the name of another macro. +#define BUILD_PIXEL_D(F,R,G,B) CONCAT(BUILD_PIXEL_,F) (R,G,B) +#define BUILD_PIXEL2_D(F,R,G,B) CONCAT(BUILD_PIXEL2_,F) (R,G,B) +#define DECOMPOSE_PIXEL_D(F,PIX,R,G,B) CONCAT(DECOMPOSE_PIXEL_,F) (PIX,R,G,B) + +#define BUILD_PIXEL(R,G,B) BUILD_PIXEL_D(PIXEL_FORMAT,R,G,B) +#define BUILD_PIXEL2(R,G,B) BUILD_PIXEL2_D(PIXEL_FORMAT,R,G,B) +#define DECOMPOSE_PIXEL(PIX,R,G,B) DECOMPOSE_PIXEL_D(PIXEL_FORMAT,PIX,R,G,B) + +#define MAX_RED_D(F) CONCAT(MAX_RED_,F) +#define MAX_BLUE_D(F) CONCAT(MAX_BLUE_,F) +#define MAX_GREEN_D(F) CONCAT(MAX_GREEN_,F) +#define RED_LOW_BIT_MASK_D(F) CONCAT(RED_LOW_BIT_MASK_,F) +#define BLUE_LOW_BIT_MASK_D(F) CONCAT(BLUE_LOW_BIT_MASK_,F) +#define GREEN_LOW_BIT_MASK_D(F) CONCAT(GREEN_LOW_BIT_MASK_,F) +#define RED_HI_BIT_MASK_D(F) CONCAT(RED_HI_BIT_MASK_,F) +#define BLUE_HI_BIT_MASK_D(F) CONCAT(BLUE_HI_BIT_MASK_,F) +#define GREEN_HI_BIT_MASK_D(F) CONCAT(GREEN_HI_BIT_MASK_,F) +#define FIRST_COLOR_MASK_D(F) CONCAT(FIRST_COLOR_MASK_,F) +#define SECOND_COLOR_MASK_D(F) CONCAT(SECOND_COLOR_MASK_,F) +#define THIRD_COLOR_MASK_D(F) CONCAT(THIRD_COLOR_MASK_,F) +#define ALPHA_BITS_MASK_D(F) CONCAT(ALPHA_BITS_MASK_,F) + +#define MAX_RED MAX_RED_D(PIXEL_FORMAT) +#define MAX_BLUE MAX_BLUE_D(PIXEL_FORMAT) +#define MAX_GREEN MAX_GREEN_D(PIXEL_FORMAT) +#define RED_LOW_BIT_MASK RED_LOW_BIT_MASK_D(PIXEL_FORMAT) +#define BLUE_LOW_BIT_MASK BLUE_LOW_BIT_MASK_D(PIXEL_FORMAT) +#define GREEN_LOW_BIT_MASK GREEN_LOW_BIT_MASK_D(PIXEL_FORMAT) +#define RED_HI_BIT_MASK RED_HI_BIT_MASK_D(PIXEL_FORMAT) +#define BLUE_HI_BIT_MASK BLUE_HI_BIT_MASK_D(PIXEL_FORMAT) +#define GREEN_HI_BIT_MASK GREEN_HI_BIT_MASK_D(PIXEL_FORMAT) +#define FIRST_COLOR_MASK FIRST_COLOR_MASK_D(PIXEL_FORMAT) +#define SECOND_COLOR_MASK SECOND_COLOR_MASK_D(PIXEL_FORMAT) +#define THIRD_COLOR_MASK THIRD_COLOR_MASK_D(PIXEL_FORMAT) +#define ALPHA_BITS_MASK ALPHA_BITS_MASK_D(PIXEL_FORMAT) + +#define GREEN_HI_BIT ((MAX_GREEN + 1) >> 1) +#define RGB_LOW_BITS_MASK (RED_LOW_BIT_MASK | GREEN_LOW_BIT_MASK | \ + BLUE_LOW_BIT_MASK) +#define RGB_HI_BITS_MASK (RED_HI_BIT_MASK | GREEN_HI_BIT_MASK | \ + BLUE_HI_BIT_MASK) +#define RGB_HI_BITS_MASKx2 ((RED_HI_BIT_MASK | GREEN_HI_BIT_MASK | \ + BLUE_HI_BIT_MASK) << 1) +#define RGB_REMOVE_LOW_BITS_MASK (~RGB_LOW_BITS_MASK) +#define FIRST_THIRD_COLOR_MASK (FIRST_COLOR_MASK | THIRD_COLOR_MASK) +#define TWO_LOW_BITS_MASK (RGB_LOW_BITS_MASK | (RGB_LOW_BITS_MASK << 1)) +#define HIGH_BITS_SHIFTED_TWO_MASK (( (FIRST_COLOR_MASK | SECOND_COLOR_MASK | THIRD_COLOR_MASK) & \ + ~TWO_LOW_BITS_MASK ) >> 2) +#endif + +#endif diff --git a/src/png.c b/src/png.c new file mode 100644 index 0000000..2d24c47 --- /dev/null +++ b/src/png.c @@ -0,0 +1,38 @@ +/* + Simple PNG handling library + Under GPL v2 License + 2011 by bitrider +*/ + +#include +#include "lodepng.h" +#include "png.h" + +#define ERROR(err) {if (error) (*error) = PNG_ERROR_OPENING; return NULL;} +gBITMAP *load_png(char *filename, int *error) /* We need to open the file */ +{ + gBITMAP *img = NULL; + unsigned int e; + + // allocate memory + img = malloc(sizeof(gBITMAP)); + if (!img) ERROR(PNG_ERROR_MEMORY); + + img->data = NULL; + + e = LodePNG_decode32_file(&img->data, &img->w, &img->h, filename); + if (e) { + gDestroyBitmap(img); + ERROR(e); + } + + img->bpp = 32; + if (error) (*error) = PNG_OK; + return img; +} + +int save_png(gBITMAP *img, char *filename) { + if ((!img) || (!img->data) || (img->bpp != 32)) return PNG_ERROR_INVALID_INPUT; + + return LodePNG_encode32_file(filename, img->data, img->w, img->h); +} diff --git a/src/png.h b/src/png.h new file mode 100644 index 0000000..c6b85d5 --- /dev/null +++ b/src/png.h @@ -0,0 +1,26 @@ +#ifndef __PNG_H__ +#define __PNG_H__ + +#include "graphics.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PNG_OK 0 +#define PNG_ERROR_OPENING 1 +#define PNG_ERROR_READING 2 +#define PNG_ERROR_NOT_PNG 3 +#define PNG_ERROR_PNG_STRUCTS 4 +#define PNG_ERROR_MEMORY 5 +#define PNG_ERROR 6 +#define PNG_ERROR_INVALID_INPUT 7 + +gBITMAP *load_png(char *filename, int *error); +int save_png(gBITMAP *img, char *filename); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/pollux_set.cpp b/src/pollux_set.cpp new file mode 100644 index 0000000..fcbd129 --- /dev/null +++ b/src/pollux_set.cpp @@ -0,0 +1,380 @@ +/* + * quick tool to set various timings for Wiz + * + * Copyright (c) Gražvydas "notaz" Ignotas, 2009 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the organization nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * HTOTAL: X VTOTAL: 341 + * HSWIDTH: 1 VSWIDTH: 0 + * HASTART: 37 VASTART: 17 + * HAEND: 277 VAEND: 337 + * + * 120Hz + * pcd 8, 447: + 594us + * pcd 9, 397: + 36us + * pcd 10, 357: - 523us + * pcd 11, 325: +1153us + * + * 'lcd_timings=397,1,37,277,341,0,17,337;dpc_clkdiv0=9' + * 'ram_timings=2,9,4,1,1,1,1' + */ + +#include +#include +#include +#include "pollux_set.h" + +/* parse stuff */ +static int parse_lcd_timings(const char *str, void *data) +{ + int *lcd_timings = (int *)data; + const char *p = str; + int ret, c; + ret = sscanf(str, "%d,%d,%d,%d,%d,%d,%d,%d", + &lcd_timings[0], &lcd_timings[1], &lcd_timings[2], &lcd_timings[3], + &lcd_timings[4], &lcd_timings[5], &lcd_timings[6], &lcd_timings[7]); + if (ret != 8) + return -1; + /* skip seven commas */ + for (c = 0; c < 7 && *p != 0; p++) + if (*p == ',') + c++; + if (c != 7) + return -1; + /* skip last number */ + while ('0' <= *p && *p <= '9') + p++; + + return p - str; +} + +static int parse_ram_timings(const char *str, void *data) +{ + int *ram_timings = (int *)data; + const char *p = str; + int ret, c; + float cas; + + ret = sscanf(p, "%f,%d,%d,%d,%d,%d,%d", + &cas, &ram_timings[1], &ram_timings[2], &ram_timings[3], + &ram_timings[4], &ram_timings[5], &ram_timings[6]); + if (ret != 7) + return -1; + if (cas == 2) + ram_timings[0] = 1; + else if (cas == 2.5) + ram_timings[0] = 2; + else if (cas == 3) + ram_timings[0] = 3; + else + return -1; + for (c = 0; c < 6 && *p != 0; p++) + if (*p == ',') + c++; + if (c != 6) + return -1; + while ('0' <= *p && *p <= '9') + p++; + + return p - str; +} + +static int parse_decimal(const char *str, void *data) +{ + char *ep; + + *(int *)data = strtoul(str, &ep, 10); + if (ep == str) + return -1; + + return ep - str; +} + +/* validate and apply stuff */ +static int apply_lcd_timings(volatile unsigned short *memregs, void *data) +{ + int *lcd_timings = (int *)data; + int i; + + for (i = 0; i < 8; i++) { + if (lcd_timings[i] & ~0xffff) { + fprintf(stderr, "pollux_set: invalid lcd timing %d: %d\n", i, lcd_timings[i]); + return -1; + } + } + + for (i = 0; i < 8; i++) + memregs[(0x307c>>1) + i] = lcd_timings[i]; + + return 0; +} + +static const struct { + signed char adj; /* how to adjust value passed by user */ + signed short min; /* range of */ + signed short max; /* allowed values (inclusive) */ +} +ram_ranges[] = { + { 0, 1, 3 }, /* cas (cl) */ + { -2, 0, 15 }, /* trc */ + { -2, 0, 15 }, /* tras */ + { 0, 0, 15 }, /* twr */ + { 0, 0, 15 }, /* tmrd */ + { 0, 0, 15 }, /* trp */ + { 0, 0, 15 }, /* trcd */ +}; + +static int apply_ram_timings(volatile unsigned short *memregs, void *data) +{ + int *ram_timings = (int *)data; + int i, val; + + for (i = 0; i < 7; i++) + { + ram_timings[i] += ram_ranges[i].adj; + if (ram_timings[i] < ram_ranges[i].min || ram_timings[i] > ram_ranges[i].max) { + fprintf(stderr, "pollux_set: invalid RAM timing %d\n", i); + return -1; + } + } + + val = memregs[0x14802>>1] & 0x0f00; + val |= (ram_timings[4] << 12) | (ram_timings[5] << 4) | ram_timings[6]; + memregs[0x14802>>1] = val; + + val = memregs[0x14804>>1] & 0x4000; + val |= (ram_timings[0] << 12) | (ram_timings[1] << 8) | + (ram_timings[2] << 4) | ram_timings[3]; + val |= 0x8000; + memregs[0x14804>>1] = val; + + for (i = 0; i < 0x100000 && (memregs[0x14804>>1] & 0x8000); i++) + ; + + return 0; +} + +static int apply_dpc_clkdiv0(volatile unsigned short *memregs, void *data) +{ + int pcd = *(int *)data; + int tmp; + + if ((pcd - 1) & ~0x3f) { + fprintf(stderr, "pollux_set: invalid lcd clkdiv0: %d\n", pcd); + return -1; + } + + pcd = (pcd - 1) & 0x3f; + tmp = memregs[0x31c4>>1]; + memregs[0x31c4>>1] = (tmp & ~0x3f0) | (pcd << 4); + + return 0; +} + +static int apply_cpuclk(volatile unsigned short *memregs, void *data) +{ + volatile unsigned int *memregl = (volatile unsigned int *)memregs; + int mhz = *(int *)data; + int mdiv, pdiv, sdiv = 0; + int i, v; + + // m = MDIV, p = PDIV, s = SDIV + #define SYS_CLK_FREQ 27 + pdiv = 9; + mdiv = (mhz * pdiv) / SYS_CLK_FREQ; + if (mdiv & ~0x3ff) + return -1; + v = (pdiv<<18) | (mdiv<<8) | sdiv; + + memregl[0xf004>>2] = v; + memregl[0xf07c>>2] |= 0x8000; + for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++) + ; + + return 0; +} + +static int lcd_timings[8]; +static int ram_timings[7]; +static int dpc_clkdiv0; +static int cpuclk; + +static const char lcd_t_help[] = "htotal,hswidth,hastart,haend,vtotal,vswidth,vastart,vaend"; +static const char ram_t_help[] = "CAS,tRC,tRAS,tWR,tMRD,tRP,tRCD"; + +static const struct { + const char *name; + const char *help; + int (*parse)(const char *str, void *data); + int (*apply)(volatile unsigned short *memregs, void *data); + void *data; +} +all_params[] = { + { "lcd_timings", lcd_t_help, parse_lcd_timings, apply_lcd_timings, lcd_timings }, + { "ram_timings", ram_t_help, parse_ram_timings, apply_ram_timings, ram_timings }, + { "dpc_clkdiv0", "divider", parse_decimal, apply_dpc_clkdiv0, &dpc_clkdiv0 }, + { "clkdiv0", "divider", parse_decimal, apply_dpc_clkdiv0, &dpc_clkdiv0 }, /* alias */ + { "cpuclk", "MHZ", parse_decimal, apply_cpuclk, &cpuclk }, +}; +#define ALL_PARAM_COUNT (sizeof(all_params) / sizeof(all_params[0])) + +/* + * set timings based on preformated string (see usage() below for params). + * returns 0 on success. + */ +int pollux_set(volatile unsigned short *memregs, const char *str) +{ + int parsed_params[ALL_PARAM_COUNT]; + int applied_params[ALL_PARAM_COUNT]; + int applied_something = 0; + const char *p, *po; + int i, ret; + + if (str == NULL) + return -1; + + memset(parsed_params, 0, sizeof(parsed_params)); + memset(applied_params, 0, sizeof(applied_params)); + + p = str; + while (1) + { +again: + while (*p == ';' || *p == ' ') + p++; + if (*p == 0) + break; + + for (i = 0; i < ALL_PARAM_COUNT; i++) + { + int param_len = strlen(all_params[i].name); + if (strncmp(p, all_params[i].name, param_len) == 0 && p[param_len] == '=') + { + p += param_len + 1; + ret = all_params[i].parse(p, all_params[i].data); + if (ret < 0) { + fprintf(stderr, "pollux_set parser: error at %-10s\n", p); + fprintf(stderr, " valid format is: <%s>\n", all_params[i].help); + return -1; + } + parsed_params[i] = 1; + p += ret; + goto again; + } + } + + /* Unknown param. Attempt to be forward compatible and ignore it. */ + for (po = p; *p != 0 && *p != ';'; p++) + ; + + fprintf(stderr, "unhandled param: "); + fwrite(po, 1, p - po, stderr); + fprintf(stderr, "\n"); + } + + /* validate and apply */ + for (i = 0; i < ALL_PARAM_COUNT; i++) + { + if (!parsed_params[i]) + continue; + + ret = all_params[i].apply(memregs, all_params[i].data); + if (ret < 0) { + fprintf(stderr, "pollux_set: failed to apply %s (bad value?)\n", + all_params[i].name); + continue; + } + + applied_something = 1; + applied_params[i] = 1; + } + + if (applied_something) + { + int c; + printf("applied: "); + for (i = c = 0; i < ALL_PARAM_COUNT; i++) + { + if (!applied_params[i]) + continue; + if (c != 0) + printf(", "); + printf("%s", all_params[i].name); + c++; + } + printf("\n"); + } + + return 0; +} + +#ifdef BINARY +#include +#include +#include +#include +#include + +static void usage(const char *binary) +{ + int i; + printf("usage:\n%s \n" + "set_str:\n", binary); + for (i = 0; i < ALL_PARAM_COUNT; i++) + printf(" %s=<%s>\n", all_params[i].name, all_params[i].help); +} + +int main(int argc, char *argv[]) +{ + volatile unsigned short *memregs; + int ret, memdev; + + if (argc != 2) { + usage(argv[0]); + return 1; + } + + memdev = open("/dev/mem", O_RDWR); + if (memdev == -1) + { + perror("open(/dev/mem) failed"); + return 1; + } + + memregs = mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000); + if (memregs == MAP_FAILED) + { + perror("mmap(memregs) failed"); + close(memdev); + return 1; + } + + ret = pollux_set(memregs, argv[1]); + + munmap((void *)memregs, 0x20000); + close(memdev); + + return ret; +} +#endif diff --git a/src/pollux_set.h b/src/pollux_set.h new file mode 100644 index 0000000..64bb220 --- /dev/null +++ b/src/pollux_set.h @@ -0,0 +1,10 @@ +#ifdef __cplusplus +extern "C" +{ +#endif + +int pollux_set(volatile unsigned short *memregs, const char *str); + +#ifdef __cplusplus +} +#endif diff --git a/src/polluxregs.h b/src/polluxregs.h new file mode 100644 index 0000000..c9e96aa --- /dev/null +++ b/src/polluxregs.h @@ -0,0 +1,96 @@ +#ifndef __POLLUXREGS_H__ +#define __POLLUXREGS_H__ + +extern volatile uint32_t *memregs32; +extern volatile uint16_t *memregs16; +extern volatile uint8_t *memregs8; +//extern volatile uint16_t *uppermem; +#define BIT(number) (1<<(number)) + +/* CPU control */ + +#define PLLSETREG0 (memregs32[0xF004>>2]) +#define PWRMODE (memregs32[0xF07C>>2]) + +/* MLC */ +#define MLCCONTROLT (memregs32[0x4000>>2]) +#define MLCSCREENSIZE (memregs32[0x4004>>2]) +#define MLCBGCOLOR (memregs32[0x4008>>2]) + +#define MLCLEFTRIGHT0 (memregs32[0x400C>>2]) +#define MLCTOPBOTTOM0 (memregs32[0x4010>>2]) +#define MLCLEFTRIGHT0_0 (memregs32[0x4014>>2]) +#define MLCTOPBOTTOM0_0 (memregs32[0x4018>>2]) +#define MLCLEFTRIGHT0_1 (memregs32[0x401C>>2]) +#define MLCTOPBOTTOM0_1 (memregs32[0x4020>>2]) +#define MLCCONTROL0 (memregs32[0x4024>>2]) +#define MLCHSTRIDE0 (memregs32[0x4028>>2]) +#define MLCVSTRIDE0 (memregs32[0x402C>>2]) +#define MLCTPCOLOR0 (memregs32[0x4030>>2]) +#define MLCINVCOLOR0 (memregs32[0x4034>>2]) +#define MLCADDRESS0 (memregs32[0x4038>>2]) +#define MLCPALETTE0 (memregs32[0x403C>>2]) + +#define MLCLEFTRIGHT1 (memregs32[0x4040>>2]) +#define MLCTOPBOTTOM1 (memregs32[0x4044>>2]) +#define MLCLEFTRIGHT1_0 (memregs32[0x4048>>2]) +#define MLCTOPBOTTOM1_0 (memregs32[0x404C>>2]) +#define MLCLEFTRIGHT1_1 (memregs32[0x4050>>2]) +#define MLCTOPBOTTOM1_1 (memregs32[0x4054>>2]) +#define MLCCONTROL1 (memregs32[0x4058>>2]) +#define MLCHSTRIDE1 (memregs32[0x405C>>2]) +#define MLCVSTRIDE1 (memregs32[0x4060>>2]) +#define MLCTPCOLOR1 (memregs32[0x4064>>2]) +#define MLCINVCOLOR1 (memregs32[0x4068>>2]) +#define MLCADDRESS1 (memregs32[0x406C>>2]) +#define MLCPALETTE1 (memregs32[0x4070>>2]) + +/* Graphics modes */ +enum { + RGB565 = 0x4432, + BGR565 = 0xC432, + XRGB1555 = 0x4342, + XBGR1555 = 0xC342, + XRGB4444 = 0x4211, + XBGR4444 = 0xC211, + XRGB8332 = 0x4120, + XBGR8332 = 0xC120, + ARGB1555 = 0x3342, + ABGR1555 = 0xB342, + ARGB4444 = 0x2211, + ABGR4444 = 0xA211, + ARGB8332 = 0x1120, + ABGR8332 = 0x9120, + RGB888 = 0x4653, + BGR888 = 0xC653, + XRGB8888 = 0x4653, + XBGR8888 = 0xC653, + ARGB8888 = 0x0653, + ABGR8888 = 0x8653, + PTRGB565 = 0x443A +}; + +/* Display controller */ +#define DPCHTOTAL (memregs16[0x307C>>1]) +#define DPCHAEND (memregs16[0x3082>>1]) +#define DPCVTOTAL (memregs16[0x3084>>1]) +#define DPCVASTART (memregs16[0x3088>>1]) +#define DPCVAEND (memregs16[0x308A>>1]) +#define DPCCTRL0 (memregs16[0x308C>>1]) +#define DPCCTRL1 (memregs16[0x308E>>1]) +#define DITHER_NONE 0 +#define DITHER_4BIT 1 +#define DITHER_5BIT 2 +#define DITHER_6BIT 3 + +/* GPIO */ +#define GPIOAPAD (memregs16[0xA018>>1]) +#define GPIOBPAD (memregs16[0xA058>>1]) +#define GPIOCPAD (memregs16[0xA098>>1]) + +/* RTC */ +#define RTCCNTWRITE (memregs32[0xF080>>2]) +#define RTCCNTREAD (memregs32[0xF084>>2]) +#define RTCCTRL (memregs32[0xF08C>>2]) + +#endif diff --git a/src/port.h b/src/port.h new file mode 100644 index 0000000..96a3ac1 --- /dev/null +++ b/src/port.h @@ -0,0 +1,503 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _PORT_H_ +#define _PORT_H_ + +/* +This port.h is really a right-of-passage for anyone trying to port the emulator + to another platform. It must have started out as a set of defines for a + single platform, and instead of using define blocks as new platforms were + added, individual coders simply added exceptions and sprinkled #ifdef and #ifndef + statements throughout the original list. + +I can't take it anymore, it's too convoluted. So I've commented out the entire + section, and preemptively rewritten the first #define segment the way god intended, + with a single define-block for each target platform. +*/ + +/* +** _SNESPPC DEFINES +*/ + +#ifdef __GIZ__ + +//Title +#define TITLE "Snes9x" + +//Required Includes +#include "pixform.h" +#include //RC +//#include +#include +#include +//Types Defined +typedef unsigned char bool8; +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; +typedef signed char int8; +typedef short int16; +typedef int int32; +typedef long long int64; + +//CSNES Types for conversion to 32 bit +/*typedef unsigned long bool8_32; +typedef unsigned long uint8_32; +typedef unsigned long uint16_32; +typedef long int8_32; +typedef long int16_32;*/ + +//For Debugging Purposes: + +typedef unsigned char bool8_32; +typedef unsigned char uint8_32; +typedef unsigned short uint16_32; +typedef signed char int8_32; +typedef short int16_32; + + +//Defines for Extern C +#define EXTERN_C extern +#define START_EXTERN_C extern "C" { +#define END_EXTERN_C } + +//Path Defines +#undef _MAX_PATH +#define _MAX_DIR PATH_MAX +#define _MAX_DRIVE 1 +#define _MAX_FNAME PATH_MAX +#define _MAX_EXT PATH_MAX +#define PATH_MAX 1024 +#define _MAX_PATH (1024) + +//True/False Defines +#define TRUE 1 +#define FALSE 0 + +//Slash Char Definitions +#define SLASH_STR "/" +#define SLASH_CHAR '/' + +//Misc Items +#define VAR_CYCLES +//#define SPC700_SHUTDOWN +#define LSB_FIRST +#define STATIC static +#define FASTCALL +#define PIXEL_FORMAT RGB565 +#define CHECK_SOUND() +#define VOID void +#define CPU_SHUTDOWN +#define UNZIP_SUPPORT +#define ZeroMemory(a,b) memset((a),0,(b)) +#define PACKING __attribute__ ((packed)) +#define ALIGN_BY_ONE __attribute__ ((aligned (1), packed)) +#define LSB_FIRST +#undef FAST_LSB_WORD_ACCESS +#ifdef ASMCPU + #define ASM_SPC700 +#endif + +EXTERN_C void S9xGenerateSound (); + +//Additional Items for _SNESPPC port +void _makepath (char *path, const char *drive, const char *dir, + const char *fname, const char *ext); +void _splitpath (const char *path, char *drive, char *dir, char *fname, + char *ext); +#define strcasecmp strcmp +#define strncasecmp strncmp +#define time(a) (0) + +#ifdef INLINE +#undef INLINE +#define INLINE __inline +#endif + +#ifdef inline +#undef inline +#define inline __inline +#endif + +#endif // _SNESPPC + +#if defined(__GP2X__) || defined(__WIZ__) + +#define ZDELTA 0x13000 + +//Title +#define TITLE "Snes9x" + +//Required Includes +#include "pixform.h" +#include //RC +//#include +#include +#include +//Types Defined +typedef unsigned char bool8; +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int bool32; +typedef unsigned int uint32; +typedef signed char int8; +typedef short int16; +typedef int int32; +typedef long long int64; + +//CSNES Types for conversion to 32 bit +/*typedef unsigned long bool8_32; +typedef unsigned long uint8_32; +typedef unsigned long uint16_32; +typedef long int8_32; +typedef long int16_32;*/ + +//For Debugging Purposes: + +typedef unsigned char bool8_32; +typedef unsigned char uint8_32; +typedef unsigned short uint16_32; +typedef signed char int8_32; +typedef short int16_32; + +//Defines for Extern C +#define EXTERN_C extern +#define START_EXTERN_C extern "C" { +#define END_EXTERN_C } + +//Path Defines +#undef _MAX_PATH +#define _MAX_DIR PATH_MAX +#define _MAX_DRIVE 1 +#define _MAX_FNAME PATH_MAX +#define _MAX_EXT PATH_MAX +#define _MAX_PATH (1024) + +//True/False Defines +#define TRUE 1 +#define FALSE 0 + +//Slash Char Definitions +#define SLASH_STR "/" +#define SLASH_CHAR '/' + +//Misc Items +#define VAR_CYCLES +//#define SPC700_SHUTDOWN +#define LSB_FIRST +#define STATIC static +#define FASTCALL +#define PIXEL_FORMAT RGB565 +#define CHECK_SOUND() +#define VOID void +#define CPU_SHUTDOWN +#define UNZIP_SUPPORT +#define ZeroMemory(a,b) memset((a),0,(b)) +#define PACKING __attribute__ ((packed)) +#define ALIGN_BY_ONE __attribute__ ((aligned (1), packed)) +#define LSB_FIRST +#undef FAST_LSB_WORD_ACCESS +#define ASM_SPC700 +#define SUPER_FX + +EXTERN_C void S9xGenerateSound (); + +//Additional Items for _SNESPPC port +void _makepath (char *path, const char *drive, const char *dir, + const char *fname, const char *ext); +void _splitpath (const char *path, char *drive, char *dir, char *fname, + char *ext); +#define strcasecmp strcmp +#define strncasecmp strncmp +#define time(a) (0) + +#ifdef INLINE +#undef INLINE +#define INLINE inline +#endif + +#endif // _SNESPPC +#endif // _PORT_H_ + +/* +#ifndef _SNESPPC +#define _SNESPPC +#endif + +#ifndef RC_OPTIMIZED +#define RC_OPTIMIZED +#endif + +#ifdef inline +#undef inline +#endif + +#ifdef INLINE +#undef INLINE +#endif + +#define inline __inline +#define INLINE __inline + +#ifdef DEBUG +#ifndef _PROFILE_ +#define _PROFILE_ +#endif +#endif + +#ifndef _SNESPPC +#ifndef STORM +#include +#include +#else +//#include +//#include +#endif + +#include +#else +#include +#endif + +#define PIXEL_FORMAT RGB565 +//#define GFX_MULTI_FORMAT + +#if defined(TARGET_OS_MAC) && TARGET_OS_MAC + +#ifdef _SNESPPC +#include "zlib/zlib.h" //RC +#else +#include "zlib.h" +#endif + +#define ZLIB +#define EXECUTE_SUPERFX_PER_LINE +#define SOUND +#define VAR_CYCLES +#define CPU_SHUTDOWN +#define SPC700_SHUTDOWN +#define PIXEL_FORMAT RGB555 +#define CHECK_SOUND() +#define M_PI 3.14159265359 +#undef _MAX_PATH + +#undef DEBUGGER // Apple Universal Headers sometimes #define DEBUGGER +#undef GFX_MULTI_FORMAT + +int strncasecmp(const char *s1, const char *s2, unsigned n); +int strcasecmp(const char *s1, const char *s2 ); + +#endif + +#ifndef snes9x_types_defined +#define snes9x_types_defined + +//CSNES +#ifdef _SNESPPC +typedef unsigned long bool8; +#else +typedef unsigned char bool8; +#endif + +#ifndef __WIN32__ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef signed char int8; +typedef short int16; +//typedef long int32; +//typedef unsigned long uint32; +typedef int int32; +typedef unsigned int uint32; +#ifdef _SNESPPC +typedef __int64 int64; +//CSNES +typedef unsigned long uint8_32; +typedef unsigned long uint16_32; +typedef long int8_32; +typedef long int16_32; + +#else +typedef long long int64; +#endif +#else // __WIN32__ + +#ifdef __BORLANDC__ +//#include +#else + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef signed char int8; +typedef short int16; + +#ifndef WSAAPI +// winsock2.h typedefs int32 as well. +typedef long int32; +#endif + +typedef unsigned int uint32; + +#endif // __BORLANDC__ + +typedef __int64 int64; + +#endif // __WIN32__ +#endif // snes9x_types_defined +#include "pixform.h" + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifdef STORM +#define EXTERN_C +#define START_EXTERN_C +#define END_EXTERN_C +#else +#if defined(__cplusplus) || defined(c_plusplus) +#define EXTERN_C extern "C" +#define START_EXTERN_C extern "C" { +#define END_EXTERN_C } +#else +#define EXTERN_C extern +#define START_EXTERN_C +#define END_EXTERN_C +#endif +#endif + +#ifndef __WIN32__ + +#ifndef PATH_MAX +#define PATH_MAX 1024 +#endif + +#define _MAX_DIR PATH_MAX +#define _MAX_DRIVE 1 +#define _MAX_FNAME PATH_MAX +#define _MAX_EXT PATH_MAX +#ifndef _MAX_PATH +#define _MAX_PATH PATH_MAX +#endif + +#ifdef _SNESPPC +#define strcasecmp strcmp +#define strncasecmp strncmp +#define time(a) (0) +#ifdef _MAX_PATH +#undef _MAX_PATH +#define _MAX_PATH (1024) +#endif +#endif + +#define ZeroMemory(a,b) memset((a),0,(b)) + +void _makepath (char *path, const char *drive, const char *dir, + const char *fname, const char *ext); +void _splitpath (const char *path, char *drive, char *dir, char *fname, + char *ext); +#else // __WIN32__ +#define strcasecmp stricmp +#define strncasecmp strnicmp +#endif + +EXTERN_C void S9xGenerateSound (); + +#ifdef STORM +EXTERN_C int soundsignal; +EXTERN_C void MixSound(void); +//Yes, CHECK_SOUND is getting defined correctly! +#define CHECK_SOUND if (Settings.APUEnabled) if(SetSignalPPC(0L, soundsignal) & soundsignal) MixSound +#else +#define CHECK_SOUND() +#endif + +#ifdef __DJGPP +#define SLASH_STR "\\" +#define SLASH_CHAR '\\' +#else +#define SLASH_STR "/" +#define SLASH_CHAR '/' +#endif + +#ifdef __linux +typedef void (*SignalHandler)(int); +#define SIG_PF SignalHandler +#endif + +#if defined(__i386__) || defined(__i486__) || defined(__i586__) || \ + defined(__WIN32__) || defined(__alpha__) +#define LSB_FIRST +#define FAST_LSB_WORD_ACCESS +#else +#ifdef _SNESPPC +#define LSB_FIRST +//NOPE! #define FAST_LSB_WORD_ACCESS //RC +#else +#define MSB_FIRST +#endif +#endif + +#ifdef __sun +#define TITLE "Snes9X: Solaris" +#endif + +#ifdef __linux +#define TITLE "Snes9X: Linux" +#endif + +#ifndef TITLE +#define TITLE "Snes9x" +#endif + +#ifdef STORM +#define STATIC +#define strncasecmp strnicmp +#else +#define STATIC static +#endif + +#endif +*/ + diff --git a/src/ppu.cpp b/src/ppu.cpp new file mode 100644 index 0000000..19340fb --- /dev/null +++ b/src/ppu.cpp @@ -0,0 +1,1418 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "missing.h" +#include "apu.h" +#include "dma.h" +#include "gfx.h" +#include "display.h" +#include "sa1.h" +#ifndef _SNESPPC +//#include "netplay.h" +#endif +#include "sdd1.h" +#include "srtc.h" + +#include "port.h" + +#ifndef ZSNES_FX +#include "fxemu.h" +#include "fxinst.h" +extern struct FxInit_s SuperFX; +extern struct FxRegs_s GSU; +#else +EXTERN_C void S9xSuperFXWriteReg (uint8, uint32); +EXTERN_C uint8 S9xSuperFXReadReg (uint32); +#endif +extern uint8 *HDMAMemPointers [8]; + +void S9xUpdateHTimer () +{ + if (PPU.HTimerEnabled) + { +#ifdef DEBUGGER + missing.hirq_pos = PPU.IRQHBeamPos; +#endif + PPU.HTimerPosition = PPU.IRQHBeamPos * Settings.H_Max / SNES_HCOUNTER_MAX; + if (PPU.HTimerPosition == Settings.H_Max || + PPU.HTimerPosition == Settings.HBlankStart) + { + PPU.HTimerPosition--; + } + + if (!PPU.VTimerEnabled || CPU.V_Counter == PPU.IRQVBeamPos) + { + if (PPU.HTimerPosition < CPU.Cycles) + { + // Missed the IRQ on this line already + if (CPU.WhichEvent == HBLANK_END_EVENT || + CPU.WhichEvent == HTIMER_AFTER_EVENT) + { + CPU.WhichEvent = HBLANK_END_EVENT; + CPU.NextEvent = Settings.H_Max; + } + else + { + CPU.WhichEvent = HBLANK_START_EVENT; + CPU.NextEvent = Settings.HBlankStart; + } + } + else + { + if (CPU.WhichEvent == HTIMER_BEFORE_EVENT || + CPU.WhichEvent == HBLANK_START_EVENT) + { + if (PPU.HTimerPosition > Settings.HBlankStart) + { + // HTimer was to trigger before h-blank start, + // now triggers after start of h-blank + CPU.NextEvent = Settings.HBlankStart; + CPU.WhichEvent = HBLANK_START_EVENT; + } + else + { + CPU.NextEvent = PPU.HTimerPosition; + CPU.WhichEvent = HTIMER_BEFORE_EVENT; + } + } + else + { + CPU.WhichEvent = HTIMER_AFTER_EVENT; + CPU.NextEvent = PPU.HTimerPosition; + } + } + } + } +} + +void S9xFixColourBrightness () +{ + IPPU.XB = mul_brightness [PPU.Brightness]; +#ifndef _SNESPPC + if (Settings.SixteenBit) +#endif + { + for (unsigned int i = 0; i < 256; i++) + { + //IPPU.Red [i] = IPPU.XB [PPU.CGDATA [i] & 0x1f]; + //IPPU.Green [i] = IPPU.XB [(PPU.CGDATA [i] >> 5) & 0x1f]; + //IPPU.Blue [i] = IPPU.XB [(PPU.CGDATA [i] >> 10) & 0x1f]; + IPPU.ScreenColors [i] = BUILD_PIXEL (IPPU.XB[IPPU.Red [i]], IPPU.XB[IPPU.Green [i]], IPPU.XB[IPPU.Blue [i]]); + } + } +} + +/**********************************************************************************************/ +/* S9xSetPPU() */ +/* This function sets a PPU Register to a specific byte */ +/**********************************************************************************************/ +#include "ppu_setppu.h" + +/**********************************************************************************************/ +/* S9xGetPPU() */ +/* This function retrieves a PPU Register */ +/**********************************************************************************************/ +#include "ppu_getppu.h" + +/**********************************************************************************************/ +/* S9xSetCPU() */ +/* This function sets a CPU/DMA Register to a specific byte */ +/**********************************************************************************************/ +void S9xSetCPU(uint8 byte, uint16 Address) +{ + int d; + + if (Address < 0x4200) + { +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + switch (Address) + { + case 0x4016 : + // S9xReset reading of old-style joypads + if ((byte & 1) && !(Memory.FillRAM[Address] & 1)) + { + PPU.Joypad1ButtonReadPos = 0; + PPU.Joypad2ButtonReadPos = 0; + PPU.Joypad3ButtonReadPos = 0; + } + break; + case 0x4017 : + break; + default : +#ifdef DEBUGGER + missing.unknowncpu_write = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf(String, "Unknown register register write: $%02X->$%04X\n", byte, Address); + S9xMessage(S9X_TRACE, S9X_PPU_TRACE, String); + } +#endif + break; + } + } + else + switch (Address) + { + case 0x4200 : + // NMI, V & H IRQ and joypad reading enable flags + if (byte & 0x20) + { + if (!PPU.VTimerEnabled) + { +#ifdef DEBUGGER + missing.virq = 1; + missing.virq_pos = PPU.IRQVBeamPos; +#endif + PPU.VTimerEnabled = TRUE; + if (PPU.HTimerEnabled) + S9xUpdateHTimer(); + else if (PPU.IRQVBeamPos == CPU.V_Counter) + S9xSetIRQ(PPU_V_BEAM_IRQ_SOURCE); + } + } + else + { + PPU.VTimerEnabled = FALSE; + } + + if (byte & 0x10) + { + if (!PPU.HTimerEnabled) + { +#ifdef DEBUGGER + missing.hirq = 1; + missing.hirq_pos = PPU.IRQHBeamPos; +#endif + PPU.HTimerEnabled = TRUE; + S9xUpdateHTimer(); + } + } + else + { + // No need to check for HTimer being disabled as the scanline + // event trigger code won't trigger an H-IRQ unless its enabled. + PPU.HTimerEnabled = FALSE; + PPU.HTimerPosition = Settings.H_Max + 1; + } + +#ifndef RC_OPTIMIZED + if (!Settings.DaffyDuck) + CLEAR_IRQ_SOURCE(PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE); + + if ((byte & 0x80) + && !(Memory.FillRAM[0x4200] & 0x80) + && CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE + && CPU.V_Counter <= PPU.ScreenHeight + (SNESGameFixes.alienVSpredetorFix ? 25 : 15) + && //jyam 15->25 alien vs predetor + // Panic Bomberman clears the NMI pending flag @ scanline 230 before enabling + // NMIs again. The NMI routine crashes the CPU if it is called without the NMI + // pending flag being set... + (Memory.FillRAM[0x4210] & 0x80) && !CPU.NMIActive) + { + CPU.Flags |= NMI_FLAG; + CPU.NMIActive = TRUE; + CPU.NMICycleCount = CPU.NMITriggerPoint; + } +#endif + break; + case 0x4201 : + // I/O port output + case 0x4202 : + // Multiplier (for multply) + break; + case 0x4203 : + { + // Multiplicand + uint32 res = Memory.FillRAM[0x4202] * byte; + + Memory.FillRAM[0x4216] = (uint8) res; + Memory.FillRAM[0x4217] = (uint8) (res >> 8); + break; + } + case 0x4204 : + case 0x4205 : + // Low and high muliplier (for divide) + break; + case 0x4206 : + { + // Divisor + uint16 a = + Memory.FillRAM[0x4204] + (Memory.FillRAM[0x4205] << 8); + uint16 div = byte ? a / byte : 0xffff; + uint16 rem = byte ? a % byte : a; + + Memory.FillRAM[0x4214] = (uint8) div; + Memory.FillRAM[0x4215] = div >> 8; + Memory.FillRAM[0x4216] = (uint8) rem; + Memory.FillRAM[0x4217] = rem >> 8; + break; + } + case 0x4207 : + d = PPU.IRQHBeamPos; + PPU.IRQHBeamPos = (PPU.IRQHBeamPos & 0xFF00) | byte; + + if (PPU.HTimerEnabled && PPU.IRQHBeamPos != d) + S9xUpdateHTimer(); + break; + + case 0x4208 : + d = PPU.IRQHBeamPos; + PPU.IRQHBeamPos = (PPU.IRQHBeamPos & 0xFF) | ((byte & 1) << 8); + + if (PPU.HTimerEnabled && PPU.IRQHBeamPos != d) + S9xUpdateHTimer(); + + break; + + case 0x4209 : + d = PPU.IRQVBeamPos; + PPU.IRQVBeamPos = (PPU.IRQVBeamPos & 0xFF00) | byte; +#ifdef DEBUGGER + missing.virq_pos = PPU.IRQVBeamPos; +#endif + if (PPU.VTimerEnabled && PPU.IRQVBeamPos != d) + { + if (PPU.HTimerEnabled) + S9xUpdateHTimer(); + else + { + if (PPU.IRQVBeamPos == CPU.V_Counter) + S9xSetIRQ(PPU_V_BEAM_IRQ_SOURCE); + } + } + break; + + case 0x420A : + d = PPU.IRQVBeamPos; + PPU.IRQVBeamPos = (PPU.IRQVBeamPos & 0xFF) | ((byte & 1) << 8); +#ifdef DEBUGGER + missing.virq_pos = PPU.IRQVBeamPos; +#endif + if (PPU.VTimerEnabled && PPU.IRQVBeamPos != d) + { + if (PPU.HTimerEnabled) + S9xUpdateHTimer(); + else + { + if (PPU.IRQVBeamPos == CPU.V_Counter) + S9xSetIRQ(PPU_V_BEAM_IRQ_SOURCE); + } + } + break; + + case 0x420B : +#ifdef DEBUGGER + missing.dma_this_frame = byte; + missing.dma_channels = byte; +#endif + if ((byte & 0x01) != 0) + S9xDoDMA(0); + if ((byte & 0x02) != 0) + S9xDoDMA(1); + if ((byte & 0x04) != 0) + S9xDoDMA(2); + if ((byte & 0x08) != 0) + S9xDoDMA(3); + if ((byte & 0x10) != 0) + S9xDoDMA(4); + if ((byte & 0x20) != 0) + S9xDoDMA(5); + if ((byte & 0x40) != 0) + S9xDoDMA(6); + if ((byte & 0x80) != 0) + S9xDoDMA(7); + break; + case 0x420C : +#ifdef DEBUGGER + missing.hdma_this_frame |= byte; + missing.hdma_channels |= byte; +#endif + //if (Settings.DisableHDMA) + // byte = 0; + Memory.FillRAM[0x420c] = byte; + IPPU.HDMA = byte; + break; + + case 0x420d : + // Cycle speed 0 - 2.68Mhz, 1 - 3.58Mhz (banks 0x80 +) + if ((byte & 1) != (Memory.FillRAM[0x420d] & 1)) + { + if (byte & 1) + { + CPU.FastROMSpeed = ONE_CYCLE; +#ifdef DEBUGGER + missing.fast_rom = 1; +#endif + } + else + CPU.FastROMSpeed = SLOW_ONE_CYCLE; + + Memory.FixROMSpeed(); + } + /* FALL */ + case 0x420e : + case 0x420f : + // --->>> Unknown + break; + case 0x4210 : + // NMI ocurred flag (reset on read or write) + Memory.FillRAM[0x4210] = 0; + return; + case 0x4211 : + // IRQ ocurred flag (reset on read or write) + CLEAR_IRQ_SOURCE(PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE); + break; + case 0x4212 : + // v-blank, h-blank and joypad being scanned flags (read-only) + case 0x4213 : + // I/O Port (read-only) + case 0x4214 : + case 0x4215 : + // Quotent of divide (read-only) + case 0x4216 : + case 0x4217 : + // Multiply product (read-only) + return; + case 0x4218 : + case 0x4219 : + case 0x421a : + case 0x421b : + case 0x421c : + case 0x421d : + case 0x421e : + case 0x421f : + // Joypad values (read-only) + return; + + case 0x4300 : + case 0x4310 : + case 0x4320 : + case 0x4330 : + case 0x4340 : + case 0x4350 : + case 0x4360 : + case 0x4370 : + d = (Address >> 4) & 0x7; + DMA[d].TransferDirection = (byte & 128) != 0 ? 1 : 0; + DMA[d].HDMAIndirectAddressing = (byte & 64) != 0 ? 1 : 0; + DMA[d].AAddressDecrement = (byte & 16) != 0 ? 1 : 0; + DMA[d].AAddressFixed = (byte & 8) != 0 ? 1 : 0; + DMA[d].TransferMode = (byte & 7); + break; + + case 0x4301 : + case 0x4311 : + case 0x4321 : + case 0x4331 : + case 0x4341 : + case 0x4351 : + case 0x4361 : + case 0x4371 : + DMA[((Address >> 4) & 0x7)].BAddress = byte; + break; + + case 0x4302 : + case 0x4312 : + case 0x4322 : + case 0x4332 : + case 0x4342 : + case 0x4352 : + case 0x4362 : + case 0x4372 : + d = (Address >> 4) & 0x7; + DMA[d].AAddress &= 0xFF00; + DMA[d].AAddress |= byte; + break; + + case 0x4303 : + case 0x4313 : + case 0x4323 : + case 0x4333 : + case 0x4343 : + case 0x4353 : + case 0x4363 : + case 0x4373 : + d = (Address >> 4) & 0x7; + DMA[d].AAddress &= 0xFF; + DMA[d].AAddress |= byte << 8; + break; + + case 0x4304 : + case 0x4314 : + case 0x4324 : + case 0x4334 : + case 0x4344 : + case 0x4354 : + case 0x4364 : + case 0x4374 : + DMA[((Address >> 4) & 0x7)].ABank = byte; + HDMAMemPointers[((Address >> 4) & 0x7)]=NULL; + break; + + case 0x4305 : + case 0x4315 : + case 0x4325 : + case 0x4335 : + case 0x4345 : + case 0x4355 : + case 0x4365 : + case 0x4375 : + d = (Address >> 4) & 0x7; + DMA[d].TransferBytes &= 0xFF00; + DMA[d].TransferBytes |= byte; + DMA[d].IndirectAddress &= 0xff00; + DMA[d].IndirectAddress |= byte; + HDMAMemPointers[d]=NULL; + break; + + case 0x4306 : + case 0x4316 : + case 0x4326 : + case 0x4336 : + case 0x4346 : + case 0x4356 : + case 0x4366 : + case 0x4376 : + d = (Address >> 4) & 0x7; + DMA[d].TransferBytes &= 0xFF; + DMA[d].TransferBytes |= byte << 8; + DMA[d].IndirectAddress &= 0xff; + DMA[d].IndirectAddress |= byte << 8; + HDMAMemPointers[d]=NULL; + break; + + case 0x4307 : + case 0x4317 : + case 0x4327 : + case 0x4337 : + case 0x4347 : + case 0x4357 : + case 0x4367 : + case 0x4377 : + DMA[d = ((Address >> 4) & 0x7)].IndirectBank = byte; + HDMAMemPointers[d]=NULL; + break; + + case 0x4308 : + case 0x4318 : + case 0x4328 : + case 0x4338 : + case 0x4348 : + case 0x4358 : + case 0x4368 : + case 0x4378 : + d = (Address >> 4) & 7; + DMA[d].Address &= 0xff00; + DMA[d].Address |= byte; + HDMAMemPointers[d] = NULL; + break; + + case 0x4309 : + case 0x4319 : + case 0x4329 : + case 0x4339 : + case 0x4349 : + case 0x4359 : + case 0x4369 : + case 0x4379 : + d = (Address >> 4) & 0x7; + DMA[d].Address &= 0xff; + DMA[d].Address |= byte << 8; + HDMAMemPointers[d] = NULL; + break; + + case 0x430A : + case 0x431A : + case 0x432A : + case 0x433A : + case 0x434A : + case 0x435A : + case 0x436A : + case 0x437A : + d = (Address >> 4) & 0x7; + DMA[d].LineCount = byte & 0x7f; + DMA[d].Repeat = !(byte & 0x80); + break; + + case 0x430F: + case 0x431F: + case 0x432F: + case 0x433F: + case 0x434F: + case 0x435F: + case 0x436F: + case 0x437F: + Address &= ~4; // Convert 43xF to 43xB + /* fall through */ + case 0x430B: + case 0x431B: + case 0x432B: + case 0x433B: + case 0x434B: + case 0x435B: + case 0x436B: + case 0x437B: + + // Unknown, but they seem to be RAM-ish + break; + case 0x4800 : + case 0x4801 : + case 0x4802 : + case 0x4803 : + //printf ("%02x->%04x\n", byte, Address); + break; + + case 0x4804 : + case 0x4805 : + case 0x4806 : + case 0x4807 : + //printf ("%02x->%04x\n", byte, Address); + + S9xSetSDD1MemoryMap(Address - 0x4804, byte & 7); + break; + default : +#ifdef DEBUGGER + missing.unknowncpu_write = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf( + String, + "Unknown register write: $%02X->$%04X\n", + byte, + Address); + S9xMessage(S9X_TRACE, S9X_PPU_TRACE, String); + } +#endif + break; + } + Memory.FillRAM[Address] = byte; +} + +/**********************************************************************************************/ +/* S9xGetCPU() */ +/* This function retrieves a CPU/DMA Register */ +/**********************************************************************************************/ +uint8 S9xGetCPU(uint16 Address) +{ + uint8 byte; + if(Address>=0x4800&&Address<=0x4807&&Settings.SDD1) + { + return Memory.FillRAM[Address]; + } + + if (Address < 0x4200) + { +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + switch (Address) + { + // Secret of the Evermore + case 0x4000 : + case 0x4001 : + return (0x40); + + case 0x4016 : + { + if (Memory.FillRAM[0x4016] & 1) + { + return (0); + } + + byte = IPPU.Joypads[0] >> (PPU.Joypad1ButtonReadPos ^ 15); + PPU.Joypad1ButtonReadPos++; + return (byte & 1); + } + case 0x4017 : + { + if (Memory.FillRAM[0x4016] & 1) + { + // MultiPlayer5 adaptor is only allowed to be plugged into port 2 + switch (IPPU.Controller) + { + case SNES_MULTIPLAYER5 : + return (2); + + case SNES_MOUSE : + if (++PPU.MouseSpeed[0] > 2) + PPU.MouseSpeed[0] = 0; + break; + } + return (0x00); + } + + if (IPPU.Controller == SNES_MULTIPLAYER5) + { + if (Memory.FillRAM[0x4201] & 0x80) + { + byte = + ((IPPU.Joypads[0] + >> (PPU.Joypad2ButtonReadPos ^ 15)) + & 1) + | (((IPPU.Joypads[2] + >> (PPU.Joypad2ButtonReadPos ^ 15)) + & 1) + << 1); + PPU.Joypad2ButtonReadPos++; + return (byte); + } + else + { + byte = + ((IPPU.Joypads[3] + >> (PPU.Joypad3ButtonReadPos ^ 15)) + & 1) + | (((IPPU.Joypads[4] + >> (PPU.Joypad3ButtonReadPos ^ 15)) + & 1) + << 1); + PPU.Joypad3ButtonReadPos++; + return (byte); + } + } + return ( + (IPPU.Joypads[0] + >> (PPU.Joypad2ButtonReadPos++ ^ 15)) + & 1); + } + default : +#ifdef DEBUGGER + missing.unknowncpu_read = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf(String, "Unknown register read: $%04X\n", Address); + S9xMessage(S9X_TRACE, S9X_PPU_TRACE, String); + } +#endif + break; + } + return (Memory.FillRAM[Address]); + } + else + switch (Address) + { + // BS Dynami Tracer! needs to be able to check if NMIs are enabled + // already, otherwise the game locks up. + case 0x4200 : + // NMI, h & v timers and joypad reading enable + if (SNESGameFixes.Old_Read0x4200) + { +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + return (REGISTER_4212()); + } + case 0x4201 : + // I/O port (output - write only?) + case 0x4202 : + case 0x4203 : + // Multiplier and multiplicand (write) + case 0x4204 : + case 0x4205 : + case 0x4206 : + // Divisor and dividend (write) + return (Memory.FillRAM[Address]); + case 0x4207 : + return (uint8) (PPU.IRQHBeamPos); + case 0x4208 : + return (PPU.IRQHBeamPos >> 8); + case 0x4209 : + return (uint8) (PPU.IRQVBeamPos); + case 0x420a : + return (PPU.IRQVBeamPos >> 8); + case 0x420b : + // General purpose DMA enable + // Super Formation Soccer 95 della Serie A UCC Xaqua requires this + // register should not always return zero. + // .. But Aero 2 waits until this register goes zero.. + // Just keep toggling the value for now in the hope that it breaks + // the game out of its wait loop... + Memory.FillRAM[0x420b] = !Memory.FillRAM[0x420b]; + return (Memory.FillRAM[0x420b]); + case 0x420c : + // H-DMA enable + return (IPPU.HDMA); + case 0x420d : + // Cycle speed 0 - 2.68Mhz, 1 - 3.58Mhz (banks 0x80 +) + return (Memory.FillRAM[Address]); + case 0x420e : + case 0x420f : + // --->>> Unknown + return (Memory.FillRAM[Address]); + case 0x4210 : +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + byte = Memory.FillRAM[0x4210]; + Memory.FillRAM[0x4210] = 0; + return (byte); + case 0x4211 : + byte = + (CPU.IRQActive + & (PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE)) + ? 0x80 + : 0; + // Super Robot Wars Ex ROM bug requires this. + byte |= CPU.Cycles >= Settings.HBlankStart ? 0x40 : 0; + CLEAR_IRQ_SOURCE(PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE); + return (byte); + case 0x4212 : + // V-blank, h-blank and joypads being read flags (read-only) +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + return (REGISTER_4212()); + case 0x4213 : + // I/O port input + case 0x4214 : + case 0x4215 : + // Quotient of divide result + case 0x4216 : + case 0x4217 : + // Multiplcation result (for multiply) or remainder of + // divison. + return (Memory.FillRAM[Address]); + case 0x4218 : + case 0x4219 : + case 0x421a : + case 0x421b : + case 0x421c : + case 0x421d : + case 0x421e : + case 0x421f : + // Joypads 1-4 button and direction state. + return (Memory.FillRAM[Address]); + + case 0x4300 : + case 0x4310 : + case 0x4320 : + case 0x4330 : + case 0x4340 : + case 0x4350 : + case 0x4360 : + case 0x4370 : + // DMA direction, address type, fixed flag, + return (Memory.FillRAM[Address]); + + case 0x4301 : + case 0x4311 : + case 0x4321 : + case 0x4331 : + case 0x4341 : + case 0x4351 : + case 0x4361 : + case 0x4371 : + return (Memory.FillRAM[Address]); + + case 0x4302 : + case 0x4312 : + case 0x4322 : + case 0x4332 : + case 0x4342 : + case 0x4352 : + case 0x4362 : + case 0x4372 : + return (Memory.FillRAM[Address]); + + case 0x4303 : + case 0x4313 : + case 0x4323 : + case 0x4333 : + case 0x4343 : + case 0x4353 : + case 0x4363 : + case 0x4373 : + return (Memory.FillRAM[Address]); + + case 0x4304 : + case 0x4314 : + case 0x4324 : + case 0x4334 : + case 0x4344 : + case 0x4354 : + case 0x4364 : + case 0x4374 : + return (Memory.FillRAM[Address]); + + case 0x4305 : + case 0x4315 : + case 0x4325 : + case 0x4335 : + case 0x4345 : + case 0x4355 : + case 0x4365 : + case 0x4375 : + return (Memory.FillRAM[Address]); + + case 0x4306 : + case 0x4316 : + case 0x4326 : + case 0x4336 : + case 0x4346 : + case 0x4356 : + case 0x4366 : + case 0x4376 : + return (Memory.FillRAM[Address]); + + case 0x4307 : + case 0x4317 : + case 0x4327 : + case 0x4337 : + case 0x4347 : + case 0x4357 : + case 0x4367 : + case 0x4377 : + return (DMA[(Address >> 4) & 7].IndirectBank); + + case 0x4308 : + case 0x4318 : + case 0x4328 : + case 0x4338 : + case 0x4348 : + case 0x4358 : + case 0x4368 : + case 0x4378 : + return (Memory.FillRAM[Address]); + + case 0x4309 : + case 0x4319 : + case 0x4329 : + case 0x4339 : + case 0x4349 : + case 0x4359 : + case 0x4369 : + case 0x4379 : + return (Memory.FillRAM[Address]); + + case 0x430A : + case 0x431A : + case 0x432A : + case 0x433A : + case 0x434A : + case 0x435A : + case 0x436A : + case 0x437A : + { + int d = (Address & 0x70) >> 4; + if (IPPU.HDMA & (1 << d)) + { + return (DMA[d].LineCount); + } + return (Memory.FillRAM[Address]); + } + case 0x430F: + case 0x431F: + case 0x432F: + case 0x433F: + case 0x434F: + case 0x435F: + case 0x436F: + case 0x437F: + Address &= ~4; // Convert 43xF to 43xB + /* fall through */ + case 0x430B: + case 0x431B: + case 0x432B: + case 0x433B: + case 0x434B: + case 0x435B: + case 0x436B: + case 0x437B: + + // Unknown, but they seem to be RAM-ish + return (Memory.FillRAM[Address]); + default : +#ifdef DEBUGGER + missing.unknowncpu_read = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf(String, "Unknown register read: $%04X\n", Address); + S9xMessage(S9X_TRACE, S9X_PPU_TRACE, String); + } + +#endif + break; + } + return (Memory.FillRAM[Address]); +} + +void S9xResetPPU() +{ + PPU.BGMode = 0; + PPU.BG3Priority = 0; + PPU.Brightness = 0; + PPU.VMA.High = 0; + PPU.VMA.Increment = 1; + PPU.VMA.Address = 0; + PPU.VMA.FullGraphicCount = 0; + PPU.VMA.Shift = 0; + + for (uint8 B = 0; B != 4; B++) + { + PPU.BG[B].SCBase = 0; + PPU.BG[B].VOffset = 0; + PPU.BG[B].HOffset = 0; + PPU.BG[B].BGSize = 0; + PPU.BG[B].NameBase = 0; + PPU.BG[B].SCSize = 0; + + PPU.ClipCounts[B] = 0; + PPU.ClipWindowOverlapLogic[B] = CLIP_OR; + PPU.ClipWindow1Enable[B] = FALSE; + PPU.ClipWindow2Enable[B] = FALSE; + PPU.ClipWindow1Inside[B] = TRUE; + PPU.ClipWindow2Inside[B] = TRUE; + } + + PPU.ClipCounts[4] = 0; + PPU.ClipCounts[5] = 0; + PPU.ClipWindowOverlapLogic[4] = PPU.ClipWindowOverlapLogic[5] = CLIP_OR; + PPU.ClipWindow1Enable[4] = PPU.ClipWindow1Enable[5] = FALSE; + PPU.ClipWindow2Enable[4] = PPU.ClipWindow2Enable[5] = FALSE; + PPU.ClipWindow1Inside[4] = PPU.ClipWindow1Inside[5] = TRUE; + PPU.ClipWindow2Inside[4] = PPU.ClipWindow2Inside[5] = TRUE; + + PPU.CGFLIP = 0; + unsigned int c; + for (c = 0; c < 256; c++) + { + IPPU.Red[c] = (c & 7) << 2; + IPPU.Green[c] = ((c >> 3) & 7) << 2; + IPPU.Blue[c] = ((c >> 6) & 2) << 3; + PPU.CGDATA[c] = + IPPU.Red[c] | (IPPU.Green[c] << 5) | (IPPU.Blue[c] << 10); + } + + PPU.FirstSprite = 0; + PPU.LastSprite = 127; + for (int Sprite = 0; Sprite < 128; Sprite++) + { + PPU.OBJ[Sprite].HPos = 0; + PPU.OBJ[Sprite].VPos = 0; + PPU.OBJ[Sprite].VFlip = 0; + PPU.OBJ[Sprite].HFlip = 0; + PPU.OBJ[Sprite].Priority = 0; + PPU.OBJ[Sprite].Palette = 0; + PPU.OBJ[Sprite].Name = 0; + PPU.OBJ[Sprite].Size = 0; + } + PPU.OAMPriorityRotation = 0; + PPU.OAMWriteRegister = 0; + + PPU.OAMFlip = 0; + PPU.OAMTileAddress = 0; + PPU.OAMAddr = 0; + PPU.IRQVBeamPos = 0; + PPU.IRQHBeamPos = 0; + PPU.VBeamPosLatched = 0; + PPU.HBeamPosLatched = 0; + + PPU.HBeamFlip = 0; + PPU.VBeamFlip = 0; + PPU.HVBeamCounterLatched = 0; + + PPU.MatrixA = PPU.MatrixB = PPU.MatrixC = PPU.MatrixD = 0; + PPU.CentreX = PPU.CentreY = 0; + PPU.Joypad1ButtonReadPos = 0; + PPU.Joypad2ButtonReadPos = 0; + PPU.Joypad3ButtonReadPos = 0; + + PPU.CGADD = 0; + PPU.FixedColourRed = PPU.FixedColourGreen = PPU.FixedColourBlue = 0; + PPU.SavedOAMAddr = 0; + PPU.SavedOAMAddr2 = 0; + PPU.ScreenHeight = SNES_HEIGHT; + PPU.WRAM = 0; + PPU.BG_Forced = 0; + PPU.ForcedBlanking = TRUE; + PPU.OBJThroughMain = FALSE; + PPU.OBJThroughSub = FALSE; + PPU.OBJSizeSelect = 0; + PPU.OBJNameSelect = 0; + PPU.OBJNameBase = 0; + PPU.OBJAddition = FALSE; + PPU.OAMReadFlip = 0; + PPU.BGnxOFSbyte = 0; + ZeroMemory(PPU.OAMData, 512 + 32); + + PPU.VTimerEnabled = FALSE; + PPU.HTimerEnabled = FALSE; + PPU.HTimerPosition = Settings.H_Max + 1; + PPU.Mosaic = 0; + PPU.BGMosaic[0] = PPU.BGMosaic[1] = FALSE; + PPU.BGMosaic[2] = PPU.BGMosaic[3] = FALSE; + PPU.Mode7HFlip = FALSE; + PPU.Mode7VFlip = FALSE; + PPU.Mode7Repeat = 0; + PPU.Window1Left = 1; + PPU.Window1Right = 0; + PPU.Window2Left = 1; + PPU.Window2Right = 0; + PPU.RecomputeClipWindows = TRUE; + PPU.CGFLIPRead = 0; + PPU.Need16x8Mulitply = FALSE; + PPU.MouseSpeed[0] = PPU.MouseSpeed[1] = 0; + + IPPU.ColorsChanged = TRUE; + IPPU.HDMA = 0; + IPPU.HDMAStarted = FALSE; + IPPU.MaxBrightness = 0; + IPPU.LatchedBlanking = 0; + IPPU.OBJChanged = TRUE; + IPPU.RenderThisFrame = TRUE; + IPPU.DirectColourMapsNeedRebuild = TRUE; + IPPU.FrameCount = 0; + IPPU.RenderedFramesCount = 0; + IPPU.DisplayedRenderedFrameCount = 0; + IPPU.SkippedFrames = 0; + IPPU.FrameSkip = 0; + ZeroMemory(IPPU.TileCached[TILE_2BIT], MAX_2BIT_TILES); + ZeroMemory(IPPU.TileCached[TILE_4BIT], MAX_4BIT_TILES); + ZeroMemory(IPPU.TileCached[TILE_8BIT], MAX_8BIT_TILES); + IPPU.FirstVRAMRead = FALSE; + IPPU.LatchedInterlace = FALSE; + IPPU.DoubleWidthPixels = FALSE; + IPPU.RenderedScreenWidth = SNES_WIDTH; + IPPU.RenderedScreenHeight = SNES_HEIGHT; + IPPU.XB = NULL; + for (c = 0; c < 256; c++) + IPPU.ScreenColors[c] = c; + S9xFixColourBrightness(); + IPPU.PreviousLine = IPPU.CurrentLine = 0; + IPPU.Joypads[0] = IPPU.Joypads[1] = IPPU.Joypads[2] = 0; + IPPU.Joypads[3] = IPPU.Joypads[4] = 0; + IPPU.SuperScope = 0; + IPPU.Mouse[0] = IPPU.Mouse[1] = 0; + IPPU.PrevMouseX[0] = IPPU.PrevMouseX[1] = 256 / 2; + IPPU.PrevMouseY[0] = IPPU.PrevMouseY[1] = 224 / 2; + + if (Settings.ControllerOption == 0) + IPPU.Controller = SNES_MAX_CONTROLLER_OPTIONS - 1; + else + IPPU.Controller = Settings.ControllerOption - 1; + S9xNextController(); + + for (c = 0; c < 2; c++) + memset(& IPPU.Clip[c], 0, sizeof(struct ClipData)); + + if (Settings.MouseMaster) + { + S9xProcessMouse(0); + S9xProcessMouse(1); + } + for (c = 0; c < 0x8000; c += 0x100) + memset(& Memory.FillRAM[c], c >> 8, 0x100); + + ZeroMemory(& Memory.FillRAM[0x2100], 0x100); + ZeroMemory(& Memory.FillRAM[0x4200], 0x100); + ZeroMemory(& Memory.FillRAM[0x4000], 0x100); + // For BS Suttehakkun 2... + ZeroMemory(& Memory.FillRAM[0x1000], 0x1000); + Memory.FillRAM[0x4201]=Memory.FillRAM[0x4213]=0xFF; + + PPU.BG[0].OffsetsChanged = 0; + PPU.BG[1].OffsetsChanged = 0; + PPU.BG[2].OffsetsChanged = 0; + PPU.BG[3].OffsetsChanged = 0; + ROpCount = 0; + ZeroMemory(&rops, MAX_ROPS); + GFX.r212c_s = 0; + GFX.r212d_s = 0; + GFX.r212e_s = 0; + GFX.r212f_s = 0; + GFX.r2130_s = 0; + GFX.r2131_s = 0; +} + +void S9xProcessMouse(int which1) +{ + int x, y; + uint32 buttons; + + if ((IPPU.Controller == SNES_MOUSE + || IPPU.Controller == SNES_MOUSE_SWAPPED) + && S9xReadMousePosition(which1, x, y, buttons)) + { + int delta_x, delta_y; +#define MOUSE_SIGNATURE 0x1 + IPPU.Mouse[which1] = + MOUSE_SIGNATURE + | (PPU.MouseSpeed[which1] << 4) + | ((buttons & 1) << 6) + | ((buttons & 2) << 6); + + delta_x = x - IPPU.PrevMouseX[which1]; + delta_y = y - IPPU.PrevMouseY[which1]; + + if (delta_x > 63) + { + delta_x = 63; + IPPU.PrevMouseX[which1] += 63; + } + else if (delta_x < -63) + { + delta_x = -63; + IPPU.PrevMouseX[which1] -= 63; + } + else + IPPU.PrevMouseX[which1] = x; + + if (delta_y > 63) + { + delta_y = 63; + IPPU.PrevMouseY[which1] += 63; + } + else if (delta_y < -63) + { + delta_y = -63; + IPPU.PrevMouseY[which1] -= 63; + } + else + IPPU.PrevMouseY[which1] = y; + + if (delta_x < 0) + { + delta_x = -delta_x; + IPPU.Mouse[which1] |= (delta_x | 0x80) << 16; + } + else + IPPU.Mouse[which1] |= delta_x << 16; + + if (delta_y < 0) + { + delta_y = -delta_y; + IPPU.Mouse[which1] |= (delta_y | 0x80) << 24; + } + else + IPPU.Mouse[which1] |= delta_y << 24; + + if (IPPU.Controller == SNES_MOUSE_SWAPPED) + IPPU.Joypads[0] = IPPU.Mouse[which1]; + else + IPPU.Joypads[1] = IPPU.Mouse[which1]; + } +} + +void ProcessSuperScope() +{ + int x, y; + uint32 buttons; + + if (IPPU.Controller == SNES_SUPERSCOPE + && S9xReadSuperScopePosition(x, y, buttons)) + { +#define SUPERSCOPE_SIGNATURE 0x00ff + uint32 scope; + + scope = + SUPERSCOPE_SIGNATURE + | ((buttons & 1) << (7 + 8)) + | ((buttons & 2) << (5 + 8)) + | ((buttons & 4) << (3 + 8)) + | ((buttons & 8) << (1 + 8)); + if (x > 255) + x = 255; + if (x < 0) + x = 0; + if (y > PPU.ScreenHeight - 1) + y = PPU.ScreenHeight - 1; + if (y < 0) + y = 0; + + PPU.VBeamPosLatched = (uint16) (y + 1); + PPU.HBeamPosLatched = (uint16) x; + PPU.HVBeamCounterLatched = TRUE; + Memory.FillRAM[0x213F] |= 0x40; + IPPU.Joypads[1] = scope; + } +} + +void S9xNextController() +{ + switch (IPPU.Controller) + { + case SNES_MULTIPLAYER5 : + IPPU.Controller = SNES_JOYPAD; + break; + case SNES_JOYPAD : + if (Settings.MouseMaster) + { + IPPU.Controller = SNES_MOUSE_SWAPPED; + break; + } + case SNES_MOUSE_SWAPPED : + if (Settings.MouseMaster) + { + IPPU.Controller = SNES_MOUSE; + break; + } + case SNES_MOUSE : + if (Settings.SuperScopeMaster) + { + IPPU.Controller = SNES_SUPERSCOPE; + break; + } + case SNES_SUPERSCOPE : + if (Settings.MultiPlayer5Master) + { + IPPU.Controller = SNES_MULTIPLAYER5; + break; + } + default : + IPPU.Controller = SNES_JOYPAD; + break; + } +} + +void S9xUpdateJoypads() +{ +#if defined (__WIZ__) + IPPU.Joypads[0] = S9xReadJoypad (0); + + if (IPPU.Joypads[0] & SNES_LEFT_MASK) + IPPU.Joypads[0] &= ~SNES_RIGHT_MASK; + if (IPPU.Joypads[0] & SNES_UP_MASK) + IPPU.Joypads[0] &= ~SNES_DOWN_MASK; + + if (Memory.FillRAM [0x4200] & 1) + { + PPU.Joypad1ButtonReadPos = 16; + + Memory.FillRAM [0x4218] = (uint8) IPPU.Joypads[0]; + Memory.FillRAM [0x4219] = (uint8) (IPPU.Joypads[0] >> 8); + if (Memory.FillRAM [0x4201] & 0x80) + { + Memory.FillRAM [0x421c] = (uint8) IPPU.Joypads[0]; + Memory.FillRAM [0x421d] = (uint8) (IPPU.Joypads[0] >> 8); + } + } +#else + int i; + + for (i = 0; i < 5; i++) + { + IPPU.Joypads[i] = S9xReadJoypad(i); + if (IPPU.Joypads[i] & SNES_LEFT_MASK) + IPPU.Joypads[i] &= ~SNES_RIGHT_MASK; + if (IPPU.Joypads[i] & SNES_UP_MASK) + IPPU.Joypads[i] &= ~SNES_DOWN_MASK; + } + + if (IPPU.Controller == SNES_JOYPAD + || IPPU.Controller == SNES_MULTIPLAYER5) + { + for (i = 0; i < 5; i++) + { + if (IPPU.Joypads[i]) + IPPU.Joypads[i] |= 0xffff0000; + } + } + + // Read mouse position if enabled + if (Settings.MouseMaster) + { + for (i = 0; i < 2; i++) + S9xProcessMouse(i); + } + + // Read SuperScope if enabled + if (Settings.SuperScopeMaster) + ProcessSuperScope(); + + if (Memory.FillRAM[0x4200] & 1) + { + PPU.Joypad1ButtonReadPos = 16; + if (Memory.FillRAM[0x4201] & 0x80) + { + PPU.Joypad2ButtonReadPos = 16; + PPU.Joypad3ButtonReadPos = 0; + } + else + { + PPU.Joypad2ButtonReadPos = 0; + PPU.Joypad3ButtonReadPos = 16; + } + + Memory.FillRAM[0x4218] = (uint8) IPPU.Joypads[0]; + Memory.FillRAM[0x4219] = (uint8) (IPPU.Joypads[0] >> 8); + Memory.FillRAM[0x421a] = (uint8) IPPU.Joypads[1]; + Memory.FillRAM[0x421b] = (uint8) (IPPU.Joypads[1] >> 8); + if (Memory.FillRAM[0x4201] & 0x80) + { + Memory.FillRAM[0x421c] = (uint8) IPPU.Joypads[0]; + Memory.FillRAM[0x421d] = (uint8) (IPPU.Joypads[0] >> 8); + Memory.FillRAM[0x421e] = (uint8) IPPU.Joypads[2]; + Memory.FillRAM[0x421f] = (uint8) (IPPU.Joypads[2] >> 8); + } + else + { + Memory.FillRAM[0x421c] = (uint8) IPPU.Joypads[3]; + Memory.FillRAM[0x421d] = (uint8) (IPPU.Joypads[3] >> 8); + Memory.FillRAM[0x421e] = (uint8) IPPU.Joypads[4]; + Memory.FillRAM[0x421f] = (uint8) (IPPU.Joypads[4] >> 8); + } + } +#endif +} + +void S9xSuperFXExec() +{ + if ((Memory.FillRAM[0x3000 + GSU_SFR] & FLG_G) + && (Memory.FillRAM[0x3000 + GSU_SCMR] & 0x18) == 0x18) + { + if (!Settings.WinterGold||Settings.StarfoxHack) + FxEmulate(~0); + else FxEmulate((Memory.FillRAM[0x3000 + GSU_CLSR] & 1) ? 700 : 350); + int GSUStatus = Memory.FillRAM[0x3000 + + GSU_SFR] | (Memory.FillRAM[0x3000 + GSU_SFR + 1] << 8); + if ((GSUStatus & (FLG_G | FLG_IRQ)) == FLG_IRQ) + { + // Trigger a GSU IRQ. + S9xSetIRQ(GSU_IRQ_SOURCE); + } + } +} + diff --git a/src/ppu.h b/src/ppu.h new file mode 100644 index 0000000..17da27e --- /dev/null +++ b/src/ppu.h @@ -0,0 +1,606 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _PPU_H_ +#define _PPU_H_ + +#include "rops.h" +#include "menu.h" + +#define FIRST_VISIBLE_LINE 1 + +extern uint8 GetBank; +extern uint16 SignExtend [2]; + +#define TILE_2BIT 0 +#define TILE_4BIT 1 +#define TILE_8BIT 2 + +#define MAX_2BIT_TILES 4096 +#define MAX_4BIT_TILES 2048 +#define MAX_8BIT_TILES 1024 + +#define PPU_H_BEAM_IRQ_SOURCE (1 << 0) +#define PPU_V_BEAM_IRQ_SOURCE (1 << 1) +#define GSU_IRQ_SOURCE (1 << 2) +#define SA1_IRQ_SOURCE (1 << 7) +#define SA1_DMA_IRQ_SOURCE (1 << 5) + +struct ClipData { + uint32 Count [6]; + uint32 Left [6][6]; + uint32 Right [6][6]; +}; + +struct InternalPPU { + bool8 ColorsChanged; + uint8 HDMA; + bool8 HDMAStarted; + uint8 MaxBrightness; + bool8 LatchedBlanking; + bool8 OBJChanged; + bool8 RenderThisFrame; + bool8 DirectColourMapsNeedRebuild; + uint32 FrameCount; + uint32 RenderedFramesCount; + uint32 DisplayedRenderedFrameCount; + uint32 SkippedFrames; + uint32 FrameSkip; + uint8 *TileCache [3]; + uint8 *TileCached [3]; + bool8 FirstVRAMRead; + bool8 LatchedInterlace; + bool8 DoubleWidthPixels; + int RenderedScreenHeight; + int RenderedScreenWidth; + uint32 Red [256]; + uint32 Green [256]; + uint32 Blue [256]; + uint8 *XB; + uint32 ScreenColors [256]; + int PreviousLine; + int CurrentLine; + int Controller; + uint32 Joypads[5]; + uint32 SuperScope; + uint32 Mouse[2]; + int PrevMouseX[2]; + int PrevMouseY[2]; + struct ClipData Clip [2]; +}; + +struct SOBJ +{ + short HPos; + uint16 VPos; + uint16 Name; + uint8 VFlip; + uint8 HFlip; + uint8 Priority; + uint8 Palette; + uint8 Size; +}; + +struct SPPU { + uint8 BGMode; + uint8 BG3Priority; + uint8 Brightness; + + struct { + bool8 High; + uint8 Increment; + uint16 Address; + uint16 Mask1; + uint16 FullGraphicCount; + uint16 Shift; + } VMA; + + struct { + uint16 SCBase; + uint16 VOffset; + uint16 HOffset; + uint8 BGSize; + uint16 NameBase; + uint16 SCSize; + bool8 OffsetsChanged; //-chg + } BG [4]; + + bool8 CGFLIP; + uint16 CGDATA [256]; + uint8 FirstSprite; + uint8 LastSprite; + struct SOBJ OBJ [128]; + uint8 OAMPriorityRotation; + uint16 OAMAddr; + + uint8 OAMFlip; + uint16 OAMTileAddress; + uint16 IRQVBeamPos; + uint16 IRQHBeamPos; + uint16 VBeamPosLatched; + uint16 HBeamPosLatched; + + uint8 HBeamFlip; + uint8 VBeamFlip; + uint8 HVBeamCounterLatched; + + short MatrixA; + short MatrixB; + short MatrixC; + short MatrixD; + short CentreX; + short CentreY; + uint8 Joypad1ButtonReadPos; + uint8 Joypad2ButtonReadPos; + + uint8 CGADD; + uint8 FixedColourRed; + uint8 FixedColourGreen; + uint8 FixedColourBlue; + uint16 SavedOAMAddr; + uint16 ScreenHeight; + uint32 WRAM; + uint8 BG_Forced; + bool8 ForcedBlanking; + bool8 OBJThroughMain; + bool8 OBJThroughSub; + uint8 OBJSizeSelect; + uint16 OBJNameBase; + bool8 OBJAddition; + uint8 OAMReadFlip; + uint8 OAMData [512 + 32]; + bool8 VTimerEnabled; + bool8 HTimerEnabled; + short HTimerPosition; + uint8 Mosaic; + bool8 BGMosaic [4]; + bool8 Mode7HFlip; + bool8 Mode7VFlip; + uint8 Mode7Repeat; + uint8 Window1Left; + uint8 Window1Right; + uint8 Window2Left; + uint8 Window2Right; + uint8 ClipCounts [6]; + uint8 ClipWindowOverlapLogic [6]; + uint8 ClipWindow1Enable [6]; + uint8 ClipWindow2Enable [6]; + bool8 ClipWindow1Inside [6]; + bool8 ClipWindow2Inside [6]; + bool8 RecomputeClipWindows; + uint8 CGFLIPRead; + uint16 OBJNameSelect; + bool8 Need16x8Mulitply; + uint8 Joypad3ButtonReadPos; + uint8 MouseSpeed[2]; + uint16 SavedOAMAddr2; + uint16 OAMWriteRegister; + uint8 BGnxOFSbyte; +}; + +#define CLIP_OR 0 +#define CLIP_AND 1 +#define CLIP_XOR 2 +#define CLIP_XNOR 3 + +struct SDMA { + bool8 TransferDirection; + bool8 AAddressFixed; + bool8 AAddressDecrement; + uint8 TransferMode; + + uint8 ABank; + uint16 AAddress; + uint16 Address; + uint8 BAddress; + + // General DMA only: + uint16 TransferBytes; + + // H-DMA only: + bool8 HDMAIndirectAddressing; + uint16 IndirectAddress; + uint8 IndirectBank; + uint8 Repeat; + uint8 LineCount; + uint8 FirstLine; +}; + +START_EXTERN_C +//void S9xUpdateScreen (); +void S9xResetPPU (); +void S9xFixColourBrightness (); +void S9xUpdateJoypads (); +void S9xProcessMouse(int which1); +void S9xSuperFXExec (); + +void S9xSetPPU (uint8 Byte, uint16 Address); +uint8 S9xGetPPU (uint16 Address); +void S9xSetCPU (uint8 Byte, uint16 Address); +uint8 S9xGetCPU (uint16 Address); + +void S9xInitC4 (); +void S9xSetC4 (uint8 Byte, uint16 Address); +uint8 S9xGetC4 (uint16 Address); +void S9xSetC4RAM (uint8 Byte, uint16 Address); +uint8 S9xGetC4RAM (uint16 Address); + +extern struct SPPU PPU; +extern struct SDMA DMA [8]; +extern struct InternalPPU IPPU; +END_EXTERN_C + +#include "gfx.h" +#include "memmap.h" + +STATIC INLINE uint8 REGISTER_4212() +{ + GetBank = 0; + if (CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE && + CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE + 3) + GetBank = 1; + + GetBank |= CPU.Cycles >= Settings.HBlankStart ? 0x40 : 0; + if (CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE) + GetBank |= 0x80; /* XXX: 0x80 or 0xc0 ? */ + + return (GetBank); +} + +/* +STATIC INLINE void FLUSH_REDRAW () +{ + if (IPPU.PreviousLine != IPPU.CurrentLine) + S9xUpdateScreen (); +} +*/ + +#define FLUSH_REDRAW() if (IPPU.PreviousLine != IPPU.CurrentLine) S9xUpdateScreen () + + +STATIC INLINE void REGISTER_2104 (uint8 byte) +{ + if (PPU.OAMAddr & 0x100) + { + int addr = ((PPU.OAMAddr & 0x10f) << 1) + (PPU.OAMFlip & 1); + if (byte != PPU.OAMData [addr]){ +#ifdef __DEBUG__ + printf("SetPPU_2104, PPU.OAMData. Byte : %x\n", byte); +#endif + + FLUSH_REDRAW (); + PPU.OAMData [addr] = byte; + IPPU.OBJChanged = TRUE; + + // X position high bit, and sprite size (x4) + struct SOBJ *pObj = &PPU.OBJ [(addr & 0x1f) * 4]; + + pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(byte >> 0) & 1]; + pObj++->Size = byte & 2; + pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(byte >> 2) & 1]; + pObj++->Size = byte & 8; + pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(byte >> 4) & 1]; + pObj++->Size = byte & 32; + pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(byte >> 6) & 1]; + pObj->Size = byte & 128; + } + PPU.OAMFlip ^= 1; + if(!(PPU.OAMFlip & 1)){ + ++PPU.OAMAddr; + PPU.OAMAddr &= 0x1ff; + } + } else if(!(PPU.OAMFlip & 1)){ + PPU.OAMWriteRegister &= 0xff00; + PPU.OAMWriteRegister |= byte; + PPU.OAMFlip |= 1; + } else { + PPU.OAMWriteRegister &= 0x00ff; + uint8 lowbyte = (uint8)(PPU.OAMWriteRegister); + uint8 highbyte = byte; + PPU.OAMWriteRegister |= byte << 8; + + int addr = (PPU.OAMAddr << 1); + + if (lowbyte != PPU.OAMData [addr] || + highbyte != PPU.OAMData [addr+1]) + { + FLUSH_REDRAW (); +#ifdef __DEBUG__ + printf("SetPPU_2104, PPU.OAMData. Byte : %x\n", byte); +#endif + + PPU.OAMData [addr] = lowbyte; + PPU.OAMData [addr+1] = highbyte; + IPPU.OBJChanged = TRUE; + if (addr & 2) + { + // Tile + PPU.OBJ[addr = PPU.OAMAddr >> 1].Name = PPU.OAMWriteRegister & 0x1ff; + + // priority, h and v flip. + PPU.OBJ[addr].Palette = (highbyte >> 1) & 7; + PPU.OBJ[addr].Priority = (highbyte >> 4) & 3; + PPU.OBJ[addr].HFlip = (highbyte >> 6) & 1; + PPU.OBJ[addr].VFlip = (highbyte >> 7) & 1; + } + else + { + // X position (low) + PPU.OBJ[addr = PPU.OAMAddr >> 1].HPos &= 0xFF00; + PPU.OBJ[addr].HPos |= lowbyte; + + // Sprite Y position + PPU.OBJ[addr].VPos = highbyte; + } + } + PPU.OAMFlip &= ~1; + ++PPU.OAMAddr; + } + + Memory.FillRAM [0x2104] = byte; +} + +STATIC INLINE void REGISTER_2118 (uint8 Byte) +{ + uint32 address; + if (PPU.VMA.FullGraphicCount) + { + uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1; + address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + + (rem >> PPU.VMA.Shift) + + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff; + Memory.VRAM [address] = Byte; + } + else + { + Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xFFFF] = Byte; + } + IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE; + IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE; + IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE; + if (!PPU.VMA.High) + { +#ifdef DEBUGGER + if (Settings.TraceVRAM && !CPU.InDMA) + { + printf ("VRAM write byte: $%04X (%d,%d)\n", PPU.VMA.Address, + Memory.FillRAM[0x2115] & 3, + (Memory.FillRAM [0x2115] & 0x0c) >> 2); + } +#endif + PPU.VMA.Address += PPU.VMA.Increment; + } +// Memory.FillRAM [0x2118] = Byte; +} + +STATIC INLINE void REGISTER_2118_tile (uint8 Byte) +{ + uint32 address; + uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1; + address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + + (rem >> PPU.VMA.Shift) + + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff; + Memory.VRAM [address] = Byte; + IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE; + IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE; + IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE; + if (!PPU.VMA.High) + PPU.VMA.Address += PPU.VMA.Increment; +// Memory.FillRAM [0x2118] = Byte; +} + +STATIC INLINE void REGISTER_2118_linear (uint8 Byte) +{ + uint32 address; + Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xFFFF] = Byte; + IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE; + IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE; + IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE; + if (!PPU.VMA.High) + PPU.VMA.Address += PPU.VMA.Increment; +// Memory.FillRAM [0x2118] = Byte; +} + +STATIC INLINE void REGISTER_2119 (uint8 Byte) +{ + uint32 address; + if (PPU.VMA.FullGraphicCount) + { + uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1; + address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) + + (rem >> PPU.VMA.Shift) + + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xFFFF; + Memory.VRAM [address] = Byte; + } + else + { + Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xFFFF] = Byte; + } + IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE; + IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE; + IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE; + if (PPU.VMA.High) + { +#ifdef DEBUGGER + if (Settings.TraceVRAM && !CPU.InDMA) + { + printf ("VRAM write word: $%04X (%d,%d)\n", PPU.VMA.Address, + Memory.FillRAM[0x2115] & 3, + (Memory.FillRAM [0x2115] & 0x0c) >> 2); + } +#endif + PPU.VMA.Address += PPU.VMA.Increment; + } +// Memory.FillRAM [0x2119] = Byte; +} + +STATIC INLINE void REGISTER_2119_tile (uint8 Byte) +{ + uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1; + uint32 address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) + + (rem >> PPU.VMA.Shift) + + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xFFFF; + Memory.VRAM [address] = Byte; + IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE; + IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE; + IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE; + if (PPU.VMA.High) + PPU.VMA.Address += PPU.VMA.Increment; +// Memory.FillRAM [0x2119] = Byte; +} + +STATIC INLINE void REGISTER_2119_linear (uint8 Byte) +{ + uint32 address; + Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xFFFF] = Byte; + IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE; + IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE; + IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE; + if (PPU.VMA.High) + PPU.VMA.Address += PPU.VMA.Increment; +// Memory.FillRAM [0x2119] = Byte; +} + +#ifdef __OLD_RASTER_FX__ +STATIC INLINE void REGISTER_2122_delayedRasterFx(uint8 Byte) +#else +STATIC INLINE void REGISTER_2122(uint8 Byte) +#endif +{ + // CG-RAM (palette) write + + if (PPU.CGFLIP) + { + if ((Byte & 0x7f) != (PPU.CGDATA[PPU.CGADD] >> 8)) + { + PPU.CGDATA[PPU.CGADD] &= 0x00FF; + PPU.CGDATA[PPU.CGADD] |= (Byte & 0x7f) << 8; + if (!(Settings.os9x_hack&PPU_IGNORE_PALWRITE)){ +#ifdef __DEBUG__ + printf("SetPPU_2122, CG-RAM (palette) write. PPU.CFGFLIP. Byte : %x\n", Byte); +#endif + ADD_ROP(ROP_PALETTE, PPU.CGADD | (PPU.CGDATA[PPU.CGADD] << 16)); + } + } + PPU.CGADD++; + } + else + { + if (Byte != (uint8) (PPU.CGDATA[PPU.CGADD] & 0xff)) + { + PPU.CGDATA[PPU.CGADD] &= 0x7F00; + PPU.CGDATA[PPU.CGADD] |= Byte; + if (!(Settings.os9x_hack&PPU_IGNORE_PALWRITE)){ +#ifdef __DEBUG__ + printf("SetPPU_2122, CG-RAM (palette) write. !PPU.CFGFLIP. Byte : %x\n", Byte); +#endif + ADD_ROP(ROP_PALETTE, PPU.CGADD | (PPU.CGDATA[PPU.CGADD] << 16)); + } + } + } + PPU.CGFLIP ^= 1; +// Memory.FillRAM [0x2122] = Byte; +} + +#ifdef __OLD_RASTER_FX__ +STATIC INLINE void REGISTER_2122_normalRasterFx(uint8 Byte) +{ + // CG-RAM (palette) write + + if (PPU.CGFLIP) + { + if ((Byte & 0x7f) != (PPU.CGDATA[PPU.CGADD] >> 8)) + { + if (!(Settings.os9x_hack&PPU_IGNORE_PALWRITE)){ +#ifdef __DEBUG__ + printf("SetPPU_2122, CG-RAM (palette) write. PPU.CFGFLIP. Byte : %x\n", Byte); +#endif + FLUSH_REDRAW (); + } + PPU.CGDATA[PPU.CGADD] &= 0x00FF; + PPU.CGDATA[PPU.CGADD] |= (Byte & 0x7f) << 8; + IPPU.ColorsChanged = TRUE; + IPPU.Blue [PPU.CGADD] = (Byte >> 2) & 0x1f; + IPPU.Green [PPU.CGADD] = (PPU.CGDATA[PPU.CGADD] >> 5) & 0x1f; + IPPU.ScreenColors [PPU.CGADD] = (uint16) BUILD_PIXEL (IPPU.XB[IPPU.Red[PPU.CGADD]], + IPPU.XB[IPPU.Green[PPU.CGADD]], + IPPU.XB[IPPU.Blue [PPU.CGADD]]); + } + PPU.CGADD++; + } + else + { + if (Byte != (uint8) (PPU.CGDATA[PPU.CGADD] & 0xff)) + { + if (!(Settings.os9x_hack&PPU_IGNORE_PALWRITE)){ +#ifdef __DEBUG__ + printf("SetPPU_2122, CG-RAM (palette) write. !PPU.CFGFLIP. Byte : %x\n", Byte); +#endif + FLUSH_REDRAW (); + } + + PPU.CGDATA[PPU.CGADD] &= 0x7F00; + PPU.CGDATA[PPU.CGADD] |= Byte; + IPPU.ColorsChanged = TRUE; + IPPU.Red [PPU.CGADD] = Byte & 0x1f; + IPPU.Green [PPU.CGADD] = (PPU.CGDATA[PPU.CGADD] >> 5) & 0x1f; + IPPU.ScreenColors [PPU.CGADD] = (uint16) BUILD_PIXEL (IPPU.XB[IPPU.Red[PPU.CGADD]], + IPPU.XB[IPPU.Green[PPU.CGADD]], + IPPU.XB[IPPU.Blue [PPU.CGADD]]); + } + } + PPU.CGFLIP ^= 1; +// Memory.FillRAM [0x2122] = Byte; +} + + +STATIC INLINE void REGISTER_2122(uint8 Byte) { + if (snesMenuOptions.delayedRasterFX) REGISTER_2122_delayedRasterFx(Byte); + else REGISTER_2122_normalRasterFx(Byte); +} +#endif + +STATIC INLINE void REGISTER_2180(uint8 Byte) +{ + Memory.RAM[PPU.WRAM++] = Byte; + PPU.WRAM &= 0x1FFFF; + Memory.FillRAM [0x2180] = Byte; +} +#endif diff --git a/src/ppu_.cpp b/src/ppu_.cpp new file mode 100644 index 0000000..1cdfa0b --- /dev/null +++ b/src/ppu_.cpp @@ -0,0 +1,2644 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" +#include "missing.h" +#include "apu.h" +#include "dma.h" +#include "gfx.h" +#include "display.h" +#include "sa1.h" +#ifndef _SNESPPC +//#include "netplay.h" +#endif +#include "sdd1.h" +#include "srtc.h" + + +#ifndef ZSNES_FX +#include "fxemu.h" +#include "fxinst.h" +extern struct FxInit_s SuperFX; +extern struct FxRegs_s GSU; +#else +EXTERN_C void S9xSuperFXWriteReg (uint8, uint32); +EXTERN_C uint8 S9xSuperFXReadReg (uint32); +#endif + +void S9xUpdateHTimer () +{ + if (PPU.HTimerEnabled) + { +#ifdef DEBUGGER + missing.hirq_pos = PPU.IRQHBeamPos; +#endif + PPU.HTimerPosition = PPU.IRQHBeamPos * Settings.H_Max / SNES_HCOUNTER_MAX; + if (PPU.HTimerPosition == Settings.H_Max || + PPU.HTimerPosition == Settings.HBlankStart) + { + PPU.HTimerPosition--; + } + + if (!PPU.VTimerEnabled || CPU.V_Counter == PPU.IRQVBeamPos) + { + if (PPU.HTimerPosition < CPU.Cycles) + { + // Missed the IRQ on this line already + if (CPU.WhichEvent == HBLANK_END_EVENT || + CPU.WhichEvent == HTIMER_AFTER_EVENT) + { + CPU.WhichEvent = HBLANK_END_EVENT; + CPU.NextEvent = Settings.H_Max; + } + else + { + CPU.WhichEvent = HBLANK_START_EVENT; + CPU.NextEvent = Settings.HBlankStart; + } + } + else + { + if (CPU.WhichEvent == HTIMER_BEFORE_EVENT || + CPU.WhichEvent == HBLANK_START_EVENT) + { + if (PPU.HTimerPosition > Settings.HBlankStart) + { + // HTimer was to trigger before h-blank start, + // now triggers after start of h-blank + CPU.NextEvent = Settings.HBlankStart; + CPU.WhichEvent = HBLANK_START_EVENT; + } + else + { + CPU.NextEvent = PPU.HTimerPosition; + CPU.WhichEvent = HTIMER_BEFORE_EVENT; + } + } + else + { + CPU.WhichEvent = HTIMER_AFTER_EVENT; + CPU.NextEvent = PPU.HTimerPosition; + } + } + } + } +} + +void S9xFixColourBrightness () +{ + IPPU.XB = mul_brightness [PPU.Brightness]; +#ifndef _SNESPPC + if (Settings.SixteenBit) +#endif + { + for (int i = 0; i < 256; i++) + { + IPPU.Red [i] = IPPU.XB [PPU.CGDATA [i] & 0x1f]; + IPPU.Green [i] = IPPU.XB [(PPU.CGDATA [i] >> 5) & 0x1f]; + IPPU.Blue [i] = IPPU.XB [(PPU.CGDATA [i] >> 10) & 0x1f]; + IPPU.ScreenColors [i] = BUILD_PIXEL (IPPU.Red [i], IPPU.Green [i], + IPPU.Blue [i]); + } + } +} + +/**********************************************************************************************/ +/* S9xSetPPU() */ +/* This function sets a PPU Register to a specific byte */ +/**********************************************************************************************/ +void S9xSetPPU (uint8 Byte, uint16 Address) +{ + if (Address <= 0x2183) + { + switch (Address) + { + case 0x2100: + // Brightness and screen blank bit + if (Byte != Memory.FillRAM [0x2100]) + { + FLUSH_REDRAW (); + if (PPU.Brightness != (Byte & 0xF)) + { + IPPU.ColorsChanged = TRUE; + IPPU.DirectColourMapsNeedRebuild = TRUE; + PPU.Brightness = Byte & 0xF; + S9xFixColourBrightness (); + if (PPU.Brightness > IPPU.MaxBrightness) + IPPU.MaxBrightness = PPU.Brightness; + } + if ((Memory.FillRAM[0x2100] & 0x80) != (Byte & 0x80)) + { + IPPU.ColorsChanged = TRUE; + PPU.ForcedBlanking = (Byte >> 7) & 1; + } + } + break; + + case 0x2101: + // Sprite (OBJ) tile address + if (Byte != Memory.FillRAM [0x2101]) + { + FLUSH_REDRAW (); + PPU.OBJNameBase = (Byte & 3) << 14; + PPU.OBJNameSelect = ((Byte >> 3) & 3) << 13; + PPU.OBJSizeSelect = (Byte >> 5) & 7; + IPPU.OBJChanged = TRUE; + } + break; + + case 0x2102: + // Sprite write address (low) + PPU.OAMAddr = Byte; + PPU.OAMFlip = 2; + PPU.OAMReadFlip = 0; + PPU.SavedOAMAddr = PPU.OAMAddr; + if (PPU.OAMPriorityRotation) + { + PPU.FirstSprite = PPU.OAMAddr & 0x7f; +#ifdef DEBUGGER + missing.sprite_priority_rotation = 1; +#endif + } + break; + + case 0x2103: + // Sprite register write address (high), sprite priority rotation + // bit. + if ((PPU.OAMPriorityRotation = (Byte & 0x80) == 0 ? 0 : 1)) + { + PPU.FirstSprite = PPU.OAMAddr & 0x7f; +#ifdef DEBUGGER + missing.sprite_priority_rotation = 1; +#endif + } + // Only update the sprite write address top bit if the low byte has + // been written to first. + if (PPU.OAMFlip & 2) + { + PPU.OAMAddr &= 0x00FF; + PPU.OAMAddr |= (Byte & 1) << 8; + } + PPU.OAMFlip = 0; + PPU.OAMReadFlip = 0; + PPU.SavedOAMAddr = PPU.OAMAddr; + break; + + case 0x2104: + // Sprite register write + REGISTER_2104(Byte, &Memory, &IPPU, &PPU); + + break; + + case 0x2105: + // Screen mode (0 - 7), background tile sizes and background 3 + // priority + if (Byte != Memory.FillRAM [0x2105]) + { + FLUSH_REDRAW (); + PPU.BG3Priority = (Byte >> 3) & 1; + PPU.BG[0].BGSize = (Byte >> 4) & 1; + PPU.BG[1].BGSize = (Byte >> 5) & 1; + PPU.BG[2].BGSize = (Byte >> 6) & 1; + PPU.BG[3].BGSize = (Byte >> 7) & 1; + PPU.BGMode = Byte & 7; +#ifdef DEBUGGER + missing.modes[PPU.BGMode] = 1; +#endif + } + break; + + case 0x2106: + // Mosaic pixel size and enable + if (Byte != Memory.FillRAM [0x2106]) + { + FLUSH_REDRAW (); +#ifdef DEBUGGER + if ((Byte & 0xf0) && (Byte & 0x0f)) + missing.mosaic = 1; +#endif + PPU.Mosaic = (Byte >> 4) + 1; + PPU.BGMosaic [0] = (Byte & 1) && PPU.Mosaic > 1; + PPU.BGMosaic [1] = (Byte & 2) && PPU.Mosaic > 1; + PPU.BGMosaic [2] = (Byte & 4) && PPU.Mosaic > 1; + PPU.BGMosaic [3] = (Byte & 8) && PPU.Mosaic > 1; + } + break; + case 0x2107: // [BG0SC] + if (Byte != Memory.FillRAM [0x2107]) + { + FLUSH_REDRAW (); + PPU.BG[0].SCSize = Byte & 3; + PPU.BG[0].SCBase = (Byte & 0x7c) << 8; + } + break; + + case 0x2108: // [BG1SC] + if (Byte != Memory.FillRAM [0x2108]) + { + FLUSH_REDRAW (); + PPU.BG[1].SCSize = Byte & 3; + PPU.BG[1].SCBase = (Byte & 0x7c) << 8; + } + break; + + case 0x2109: // [BG2SC] + if (Byte != Memory.FillRAM [0x2109]) + { + FLUSH_REDRAW (); + PPU.BG[2].SCSize = Byte & 3; + PPU.BG[2].SCBase = (Byte & 0x7c) << 8; + } + break; + + case 0x210A: // [BG3SC] + if (Byte != Memory.FillRAM [0x210a]) + { + FLUSH_REDRAW (); + PPU.BG[3].SCSize = Byte & 3; + PPU.BG[3].SCBase = (Byte & 0x7c) << 8; + } + break; + + case 0x210B: // [BG01NBA] + if (Byte != Memory.FillRAM [0x210b]) + { + FLUSH_REDRAW (); + PPU.BG[0].NameBase = (Byte & 7) << 12; + PPU.BG[1].NameBase = ((Byte >> 4) & 7) << 12; + } + break; + + case 0x210C: // [BG23NBA] + if (Byte != Memory.FillRAM [0x210c]) + { + FLUSH_REDRAW (); + PPU.BG[2].NameBase = (Byte & 7) << 12; + PPU.BG[3].NameBase = ((Byte >> 4) & 7) << 12; + } + break; + + case 0x210D: + PPU.BG[0].HOffset = ((PPU.BG[0].HOffset >> 8) & 0xff) | + ((uint16) Byte << 8); + break; + + case 0x210E: + PPU.BG[0].VOffset = ((PPU.BG[0].VOffset >> 8) & 0xff) | + ((uint16) Byte << 8); + break; + case 0x210F: + PPU.BG[1].HOffset = ((PPU.BG[1].HOffset >> 8) & 0xff) | + ((uint16) Byte << 8); + break; + + case 0x2110: + PPU.BG[1].VOffset = ((PPU.BG[1].VOffset >> 8) & 0xff) | + ((uint16) Byte << 8); + break; + + case 0x2111: + PPU.BG[2].HOffset = ((PPU.BG[2].HOffset >> 8) & 0xff) | + ((uint16) Byte << 8); + break; + + case 0x2112: + PPU.BG[2].VOffset = ((PPU.BG[2].VOffset >> 8) & 0xff) | + ((uint16) Byte << 8); + break; + + case 0x2113: + PPU.BG[3].HOffset = ((PPU.BG[3].HOffset >> 8) & 0xff) | + ((uint16) Byte << 8); + break; + + case 0x2114: + PPU.BG[3].VOffset = ((PPU.BG[3].VOffset >> 8) & 0xff) | + ((uint16) Byte << 8); + break; + + case 0x2115: + // VRAM byte/word access flag and increment + PPU.VMA.High = (Byte & 0x80) == 0 ? FALSE : TRUE; + switch (Byte & 3) + { + case 0: + PPU.VMA.Increment = 1; + break; + case 1: + PPU.VMA.Increment = 32; + break; + case 2: + PPU.VMA.Increment = 128; + break; + case 3: + PPU.VMA.Increment = 128; + break; + } +#ifdef DEBUGGER + if ((Byte & 3) != 0) + missing.vram_inc = Byte & 3; +#endif + if (Byte & 0x0c) + { + static uint16 IncCount [4] = { 0, 32, 64, 128 }; + static uint16 Shift [4] = { 0, 5, 6, 7 }; +#ifdef DEBUGGER + missing.vram_full_graphic_inc = (Byte & 0x0c) >> 2; +#endif + PPU.VMA.Increment = 1; + uint8 i = (Byte & 0x0c) >> 2; + PPU.VMA.FullGraphicCount = IncCount [i]; + PPU.VMA.Mask1 = IncCount [i] * 8 - 1; + PPU.VMA.Shift = Shift [i]; + } + else + PPU.VMA.FullGraphicCount = 0; + break; + + case 0x2116: + // VRAM read/write address (low) + PPU.VMA.Address &= 0xFF00; + PPU.VMA.Address |= Byte; + IPPU.FirstVRAMRead = TRUE; + break; + + case 0x2117: + // VRAM read/write address (high) + PPU.VMA.Address &= 0x00FF; + PPU.VMA.Address |= Byte << 8; + IPPU.FirstVRAMRead = TRUE; + break; + + case 0x2118: + // VRAM write data (low) + IPPU.FirstVRAMRead = TRUE; + REGISTER_2118(Byte, &Memory, &IPPU, &PPU); + break; + + case 0x2119: + // VRAM write data (high) + IPPU.FirstVRAMRead = TRUE; + REGISTER_2119(Byte, &Memory, &IPPU, &PPU); + break; + + case 0x211a: + // Mode 7 outside rotation area display mode and flipping + if (Byte != Memory.FillRAM [0x211a]) + { + FLUSH_REDRAW (); + PPU.Mode7Repeat = Byte >> 6; + PPU.Mode7VFlip = (Byte & 2) >> 1; + PPU.Mode7HFlip = Byte & 1; + } + break; + case 0x211b: + // Mode 7 matrix A (low & high) + PPU.MatrixA = ((PPU.MatrixA >> 8) & 0xff) | (Byte << 8); + PPU.Need16x8Mulitply = TRUE; + break; + case 0x211c: + // Mode 7 matrix B (low & high) + PPU.MatrixB = ((PPU.MatrixB >> 8) & 0xff) | (Byte << 8); + PPU.Need16x8Mulitply = TRUE; + break; + case 0x211d: + // Mode 7 matrix C (low & high) + PPU.MatrixC = ((PPU.MatrixC >> 8) & 0xff) | (Byte << 8); + break; + case 0x211e: + // Mode 7 matrix D (low & high) + PPU.MatrixD = ((PPU.MatrixD >> 8) & 0xff) | (Byte << 8); + break; + case 0x211f: + // Mode 7 centre of rotation X (low & high) + PPU.CentreX = ((PPU.CentreX >> 8) & 0xff) | (Byte << 8); + break; + case 0x2120: + // Mode 7 centre of rotation Y (low & high) + PPU.CentreY = ((PPU.CentreY >> 8) & 0xff) | (Byte << 8); + break; + + case 0x2121: + // CG-RAM address + PPU.CGFLIP = 0; + PPU.CGFLIPRead = 0; + PPU.CGADD = Byte; + break; + + case 0x2122: + REGISTER_2122(Byte, &Memory, &IPPU, &PPU); + break; + + case 0x2123: + // Window 1 and 2 enable for backgrounds 1 and 2 + if (Byte != Memory.FillRAM [0x2123]) + { + FLUSH_REDRAW (); + + PPU.ClipWindow1Enable [0] = !!(Byte & 0x02); + PPU.ClipWindow1Enable [1] = !!(Byte & 0x20); + PPU.ClipWindow2Enable [0] = !!(Byte & 0x08); + PPU.ClipWindow2Enable [1] = !!(Byte & 0x80); + PPU.ClipWindow1Inside [0] = !(Byte & 0x01); + PPU.ClipWindow1Inside [1] = !(Byte & 0x10); + PPU.ClipWindow2Inside [0] = !(Byte & 0x04); + PPU.ClipWindow2Inside [1] = !(Byte & 0x40); + PPU.RecomputeClipWindows = TRUE; +#ifdef DEBUGGER + if (Byte & 0x80) + missing.window2[1] = 1; + if (Byte & 0x20) + missing.window1[1] = 1; + if (Byte & 0x08) + missing.window2[0] = 1; + if (Byte & 0x02) + missing.window1[0] = 1; +#endif + } + break; + case 0x2124: + // Window 1 and 2 enable for backgrounds 3 and 4 + if (Byte != Memory.FillRAM [0x2124]) + { + FLUSH_REDRAW (); + + PPU.ClipWindow1Enable [2] = !!(Byte & 0x02); + PPU.ClipWindow1Enable [3] = !!(Byte & 0x20); + PPU.ClipWindow2Enable [2] = !!(Byte & 0x08); + PPU.ClipWindow2Enable [3] = !!(Byte & 0x80); + PPU.ClipWindow1Inside [2] = !(Byte & 0x01); + PPU.ClipWindow1Inside [3] = !(Byte & 0x10); + PPU.ClipWindow2Inside [2] = !(Byte & 0x04); + PPU.ClipWindow2Inside [3] = !(Byte & 0x40); + PPU.RecomputeClipWindows = TRUE; +#ifdef DEBUGGER + if (Byte & 0x80) + missing.window2[3] = 1; + if (Byte & 0x20) + missing.window1[3] = 1; + if (Byte & 0x08) + missing.window2[2] = 1; + if (Byte & 0x02) + missing.window1[2] = 1; +#endif + } + break; + case 0x2125: + // Window 1 and 2 enable for objects and colour window + if (Byte != Memory.FillRAM [0x2125]) + { + FLUSH_REDRAW (); + + PPU.ClipWindow1Enable [4] = !!(Byte & 0x02); + PPU.ClipWindow1Enable [5] = !!(Byte & 0x20); + PPU.ClipWindow2Enable [4] = !!(Byte & 0x08); + PPU.ClipWindow2Enable [5] = !!(Byte & 0x80); + PPU.ClipWindow1Inside [4] = !(Byte & 0x01); + PPU.ClipWindow1Inside [5] = !(Byte & 0x10); + PPU.ClipWindow2Inside [4] = !(Byte & 0x04); + PPU.ClipWindow2Inside [5] = !(Byte & 0x40); + PPU.RecomputeClipWindows = TRUE; +#ifdef DEBUGGER + if (Byte & 0x80) + missing.window2[5] = 1; + if (Byte & 0x20) + missing.window1[5] = 1; + if (Byte & 0x08) + missing.window2[4] = 1; + if (Byte & 0x02) + missing.window1[4] = 1; +#endif + } + break; + case 0x2126: + // Window 1 left position + if (Byte != Memory.FillRAM [0x2126]) + { + FLUSH_REDRAW (); + + PPU.Window1Left = Byte; + PPU.RecomputeClipWindows = TRUE; + } + break; + case 0x2127: + // Window 1 right position + if (Byte != Memory.FillRAM [0x2127]) + { + FLUSH_REDRAW (); + + PPU.Window1Right = Byte; + PPU.RecomputeClipWindows = TRUE; + } + break; + case 0x2128: + // Window 2 left position + if (Byte != Memory.FillRAM [0x2128]) + { + FLUSH_REDRAW (); + + PPU.Window2Left = Byte; + PPU.RecomputeClipWindows = TRUE; + } + break; + case 0x2129: + // Window 2 right position + if (Byte != Memory.FillRAM [0x2129]) + { + FLUSH_REDRAW (); + + PPU.Window2Right = Byte; + PPU.RecomputeClipWindows = TRUE; + } + break; + case 0x212a: + // Windows 1 & 2 overlap logic for backgrounds 1 - 4 + if (Byte != Memory.FillRAM [0x212a]) + { + FLUSH_REDRAW (); + + PPU.ClipWindowOverlapLogic [0] = (Byte & 0x03); + PPU.ClipWindowOverlapLogic [1] = (Byte & 0x0c) >> 2; + PPU.ClipWindowOverlapLogic [2] = (Byte & 0x30) >> 4; + PPU.ClipWindowOverlapLogic [3] = (Byte & 0xc0) >> 6; + PPU.RecomputeClipWindows = TRUE; + } + break; + case 0x212b: + // Windows 1 & 2 overlap logic for objects and colour window + if (Byte != Memory.FillRAM [0x212b]) + { + FLUSH_REDRAW (); + + PPU.ClipWindowOverlapLogic [4] = Byte & 0x03; + PPU.ClipWindowOverlapLogic [5] = (Byte & 0x0c) >> 2; + PPU.RecomputeClipWindows = TRUE; + } + break; + case 0x212c: + // Main screen designation (backgrounds 1 - 4 and objects) + if (Byte != Memory.FillRAM [0x212c]) + { + FLUSH_REDRAW (); + + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM [Address] = Byte; + return; + } + break; + case 0x212d: + // Sub-screen designation (backgrounds 1 - 4 and objects) + if (Byte != Memory.FillRAM [0x212d]) + { + FLUSH_REDRAW (); + +#ifdef DEBUGGER + if (Byte & 0x1f) + missing.subscreen = 1; +#endif + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM [Address] = Byte; + return; + } + break; + case 0x212e: + // Window mask designation for main screen ? + if (Byte != Memory.FillRAM [0x212e]) + { + FLUSH_REDRAW (); + + PPU.RecomputeClipWindows = TRUE; + } + break; + case 0x212f: + // Window mask designation for sub-screen ? + if (Byte != Memory.FillRAM [0x212f]) + { + FLUSH_REDRAW (); + + PPU.RecomputeClipWindows = TRUE; + } + break; + case 0x2130: + // Fixed colour addition or screen addition + if (Byte != Memory.FillRAM [0x2130]) + { + FLUSH_REDRAW (); + + PPU.RecomputeClipWindows = TRUE; +#ifdef DEBUGGER + if ((Byte & 1) && (PPU.BGMode == 3 || PPU.BGMode == 4 || PPU.BGMode == 7)) + missing.direct = 1; +#endif + } + break; + case 0x2131: + // Colour addition or subtraction select + if (Byte != Memory.FillRAM[0x2131]) + { + FLUSH_REDRAW (); + + // Backgrounds 1 - 4, objects and backdrop colour add/sub enable +#ifdef DEBUGGER + if (Byte & 0x80) + { + // Subtract + if (Memory.FillRAM[0x2130] & 0x02) + missing.subscreen_sub = 1; + else + missing.fixed_colour_sub = 1; + } + else + { + // Addition + if (Memory.FillRAM[0x2130] & 0x02) + missing.subscreen_add = 1; + else + missing.fixed_colour_add = 1; + } +#endif + Memory.FillRAM[0x2131] = Byte; + } + break; + case 0x2132: + if (Byte != Memory.FillRAM [0x2132]) + { + FLUSH_REDRAW (); + + // Colour data for fixed colour addition/subtraction + if (Byte & 0x80) + PPU.FixedColourBlue = Byte & 0x1f; + if (Byte & 0x40) + PPU.FixedColourGreen = Byte & 0x1f; + if (Byte & 0x20) + PPU.FixedColourRed = Byte & 0x1f; + } + break; + case 0x2133: + // Screen settings + if (Byte != Memory.FillRAM [0x2133]) + { +#ifdef DEBUGGER + if (Byte & 0x40) + missing.mode7_bgmode = 1; + if (Byte & 0x08) + missing.pseudo_512 = 1; +#endif + if (Byte & 0x04) + { + PPU.ScreenHeight = SNES_HEIGHT_EXTENDED; +#ifdef DEBUGGER + missing.lines_239 = 1; +#endif + } + else + PPU.ScreenHeight = SNES_HEIGHT; +#ifdef DEBUGGER + if (Byte & 0x02) + missing.sprite_double_height = 1; + + if (Byte & 1) + missing.interlace = 1; +#endif + } + break; + case 0x2134: + case 0x2135: + case 0x2136: + // Matrix 16bit x 8bit multiply result (read-only) + return; + + case 0x2137: + // Software latch for horizontal and vertical timers (read-only) + return; + case 0x2138: + // OAM read data (read-only) + return; + case 0x2139: + case 0x213a: + // VRAM read data (read-only) + return; + case 0x213b: + // CG-RAM read data (read-only) + return; + case 0x213c: + case 0x213d: + // Horizontal and vertical (low/high) read counter (read-only) + return; + case 0x213e: + // PPU status (time over and range over) + return; + case 0x213f: + // NTSC/PAL select and field (read-only) + return; + case 0x2140: case 0x2141: case 0x2142: case 0x2143: + case 0x2144: case 0x2145: case 0x2146: case 0x2147: + case 0x2148: case 0x2149: case 0x214a: case 0x214b: + case 0x214c: case 0x214d: case 0x214e: case 0x214f: + case 0x2150: case 0x2151: case 0x2152: case 0x2153: + case 0x2154: case 0x2155: case 0x2156: case 0x2157: + case 0x2158: case 0x2159: case 0x215a: case 0x215b: + case 0x215c: case 0x215d: case 0x215e: case 0x215f: + case 0x2160: case 0x2161: case 0x2162: case 0x2163: + case 0x2164: case 0x2165: case 0x2166: case 0x2167: + case 0x2168: case 0x2169: case 0x216a: case 0x216b: + case 0x216c: case 0x216d: case 0x216e: case 0x216f: + case 0x2170: case 0x2171: case 0x2172: case 0x2173: + case 0x2174: case 0x2175: case 0x2176: case 0x2177: + case 0x2178: case 0x2179: case 0x217a: case 0x217b: + case 0x217c: case 0x217d: case 0x217e: case 0x217f: +#ifdef SPCTOOL + _SPCInPB (Address & 3, Byte); +#else +// CPU.Flags |= DEBUG_MODE_FLAG; + Memory.FillRAM [Address] = Byte; + IAPU.RAM [(Address & 3) + 0xf4] = Byte; +#ifdef SPC700_SHUTDOWN + IAPU.APUExecuting = Settings.APUEnabled; + IAPU.WaitCounter++; +#endif +#endif // SPCTOOL + break; + case 0x2180: + REGISTER_2180(Byte, &Memory, &IPPU, &PPU); + break; + case 0x2181: + PPU.WRAM &= 0x1FF00; + PPU.WRAM |= Byte; + break; + case 0x2182: + PPU.WRAM &= 0x100FF; + PPU.WRAM |= Byte << 8; + break; + case 0x2183: + PPU.WRAM &= 0x0FFFF; + PPU.WRAM |= Byte << 16; + PPU.WRAM &= 0x1FFFF; + break; + } + } + else + { + if (Settings.SA1) + { + if (Address >= 0x2200 && Address <0x23ff) + S9xSetSA1 (Byte, Address); + else + Memory.FillRAM [Address] = Byte; + return; + } + else + // Dai Kaijyu Monogatari II + if (Address == 0x2801 && Settings.SRTC) + S9xSetSRTC (Byte, Address); + else + if (Address < 0x3000 || Address >= 0x3000 + 768) + { +#ifdef DEBUGGER + missing.unknownppu_write = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf (String, "Unknown register write: $%02X->$%04X\n", + Byte, Address); + S9xMessage (S9X_TRACE, S9X_PPU_TRACE, String); + } +#endif + } + else + { + if (!Settings.SuperFX) + return; + + #ifdef ZSNES_FX + Memory.FillRAM [Address] = Byte; + if (Address < 0x3040) + S9xSuperFXWriteReg (Byte, Address); + #else + switch (Address) + { + case 0x3030: + if ((Memory.FillRAM [0x3030] ^ Byte) & FLG_G) + { + Memory.FillRAM [Address] = Byte; + // Go flag has been changed + if (Byte & FLG_G) + S9xSuperFXExec (); + else + FxFlushCache (&GSU); + } + else + Memory.FillRAM [Address] = Byte; + break; + + case 0x3031: + Memory.FillRAM [Address] = Byte; + break; + case 0x3033: + Memory.FillRAM [Address] = Byte; + break; + case 0x3034: + Memory.FillRAM [Address] = Byte & 0x7f; + break; + case 0x3036: + Memory.FillRAM [Address] = Byte & 0x7f; + break; + case 0x3037: + Memory.FillRAM [Address] = Byte; + break; + case 0x3038: + Memory.FillRAM [Address] = Byte; + break; + case 0x3039: + Memory.FillRAM [Address] = Byte; + break; + case 0x303a: + Memory.FillRAM [Address] = Byte; + break; + case 0x303b: + break; + case 0x303f: + Memory.FillRAM [Address] = Byte; + break; + case 0x301f: + Memory.FillRAM [Address] = Byte; + Memory.FillRAM [0x3000 + GSU_SFR] |= FLG_G; + S9xSuperFXExec (); + return; + + default: + Memory.FillRAM[Address] = Byte; + if (Address >= 0x3100) + { + FxCacheWriteAccess (Address, &GSU); + } + break; + } + #endif + return; + } + } + Memory.FillRAM[Address] = Byte; +} + +/**********************************************************************************************/ +/* S9xGetPPU() */ +/* This function retrieves a PPU Register */ +/**********************************************************************************************/ +uint8 S9xGetPPU (uint16 Address) +{ + uint8 byte = 0; + + if (Address <= 0x2190) + { + switch (Address) + { + case 0x2100: + case 0x2101: + return (Memory.FillRAM[Address]); + case 0x2102: +#ifdef DEBUGGER + missing.oam_address_read = 1; +#endif + return (uint8)(PPU.OAMAddr); + case 0x2103: + return (((PPU.OAMAddr >> 8) & 1) | (PPU.OAMPriorityRotation << 7)); + case 0x2104: + case 0x2105: + case 0x2106: + case 0x2107: + case 0x2108: + case 0x2109: + case 0x210a: + case 0x210b: + case 0x210c: + return (Memory.FillRAM[Address]); + case 0x210d: + case 0x210e: + case 0x210f: + case 0x2110: + case 0x2111: + case 0x2112: + case 0x2113: + case 0x2114: +#ifdef DEBUGGER + missing.bg_offset_read = 1; +#endif + return (Memory.FillRAM[Address]); + case 0x2115: + return (Memory.FillRAM[Address]); + case 0x2116: + return (uint8)(PPU.VMA.Address); + case 0x2117: + return (PPU.VMA.Address >> 8); + case 0x2118: + case 0x2119: + case 0x211a: + return (Memory.FillRAM[Address]); + case 0x211b: + case 0x211c: + case 0x211d: + case 0x211e: + case 0x211f: + case 0x2120: +#ifdef DEBUGGER + missing.matrix_read = 1; +#endif + return (Memory.FillRAM[Address]); + case 0x2121: + return (PPU.CGADD); + case 0x2122: + case 0x2123: + case 0x2124: + case 0x2125: + case 0x2126: + case 0x2127: + case 0x2128: + case 0x2129: + case 0x212a: + case 0x212b: + case 0x212c: + case 0x212d: + case 0x212e: + case 0x212f: + case 0x2130: + case 0x2131: + case 0x2132: + case 0x2133: + return (Memory.FillRAM[Address]); + + case 0x2134: + case 0x2135: + case 0x2136: + // 16bit x 8bit multiply read result. + if (PPU.Need16x8Mulitply) + { + int32 r = (int32) PPU.MatrixA * (int32) (PPU.MatrixB >> 8); + + Memory.FillRAM[0x2134] = (uint8) r; + Memory.FillRAM[0x2135] = (uint8)(r >> 8); + Memory.FillRAM[0x2136] = (uint8)(r >> 16); + PPU.Need16x8Mulitply = FALSE; + } +#ifdef DEBUGGER + missing.matrix_multiply = 1; +#endif + return (Memory.FillRAM[Address]); + case 0x2137: + // Latch h and v counters +#ifdef DEBUGGER + missing.h_v_latch = 1; +#endif +#if 0 +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif +#endif + PPU.HVBeamCounterLatched = 1; + PPU.VBeamPosLatched = (uint16) CPU.V_Counter; + PPU.HBeamPosLatched = (uint16) ((CPU.Cycles * SNES_HCOUNTER_MAX) / Settings.H_Max); + + // Causes screen flicker for Yoshi's Island if uncommented + //CLEAR_IRQ_SOURCE (PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE); + + if (SNESGameFixes.NeedInit0x2137) + PPU.VBeamFlip = 0; //jyam sword world sfc2 & godzill + return (0); + case 0x2138: + // Read OAM (sprite) control data + if (!PPU.OAMReadFlip) + { + byte = PPU.OAMData [PPU.OAMAddr << 1]; + } + else + { + byte = PPU.OAMData [(PPU.OAMAddr << 1) + 1]; + if (++PPU.OAMAddr >= 0x110) + PPU.OAMAddr = 0; + + } + PPU.OAMReadFlip ^= 1; +#ifdef DEBUGGER + missing.oam_read = 1; +#endif + return (byte); + + case 0x2139: + // Read vram low byte +#ifdef DEBUGGER + missing.vram_read = 1; +#endif + if (IPPU.FirstVRAMRead) + byte = Memory.VRAM[PPU.VMA.Address << 1]; + else + if (PPU.VMA.FullGraphicCount) + { + uint32 addr = PPU.VMA.Address - 1; + uint32 rem = addr & PPU.VMA.Mask1; + uint32 address = (addr & ~PPU.VMA.Mask1) + + (rem >> PPU.VMA.Shift) + + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3); + byte = Memory.VRAM [((address << 1) - 2) & 0xFFFF]; + } + else + byte = Memory.VRAM[((PPU.VMA.Address << 1) - 2) & 0xffff]; + + if (!PPU.VMA.High) + { + PPU.VMA.Address += PPU.VMA.Increment; + IPPU.FirstVRAMRead = FALSE; + } + break; + case 0x213A: + // Read vram high byte +#ifdef DEBUGGER + missing.vram_read = 1; +#endif + if (IPPU.FirstVRAMRead) + byte = Memory.VRAM[((PPU.VMA.Address << 1) + 1) & 0xffff]; + else + if (PPU.VMA.FullGraphicCount) + { + uint32 addr = PPU.VMA.Address - 1; + uint32 rem = addr & PPU.VMA.Mask1; + uint32 address = (addr & ~PPU.VMA.Mask1) + + (rem >> PPU.VMA.Shift) + + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3); + byte = Memory.VRAM [((address << 1) - 1) & 0xFFFF]; + } + else + byte = Memory.VRAM[((PPU.VMA.Address << 1) - 1) & 0xFFFF]; + if (PPU.VMA.High) + { + PPU.VMA.Address += PPU.VMA.Increment; + IPPU.FirstVRAMRead = FALSE; + } + break; + + case 0x213B: + // Read palette data +#ifdef DEBUGGER + missing.cgram_read = 1; +#endif + if (PPU.CGFLIPRead) + byte = PPU.CGDATA [PPU.CGADD++] >> 8; + else + byte = PPU.CGDATA [PPU.CGADD] & 0xff; + + PPU.CGFLIPRead ^= 1; + return (byte); + + case 0x213C: + // Horizontal counter value 0-339 +#ifdef DEBUGGER + missing.h_counter_read = 1; +#endif + if (PPU.HBeamFlip) + byte = PPU.HBeamPosLatched >> 8; + else + byte = (uint8)PPU.HBeamPosLatched; + PPU.HBeamFlip ^= 1; + break; + case 0x213D: + // Vertical counter value 0-262 +#ifdef DEBUGGER + missing.v_counter_read = 1; +#endif + if (PPU.VBeamFlip) + byte = PPU.VBeamPosLatched >> 8; + else + byte = (uint8)PPU.VBeamPosLatched; + PPU.VBeamFlip ^= 1; + break; + case 0x213E: + // PPU time and range over flags + return (SNESGameFixes._0x213E_ReturnValue); + + case 0x213F: + // NTSC/PAL and which field flags + PPU.VBeamFlip = PPU.HBeamFlip = 0; + return ((Settings.PAL ? 0x10 : 0) | (Memory.FillRAM[0x213f] & 0xc0)); + + case 0x2140: case 0x2141: case 0x2142: case 0x2143: + case 0x2144: case 0x2145: case 0x2146: case 0x2147: + case 0x2148: case 0x2149: case 0x214a: case 0x214b: + case 0x214c: case 0x214d: case 0x214e: case 0x214f: + case 0x2150: case 0x2151: case 0x2152: case 0x2153: + case 0x2154: case 0x2155: case 0x2156: case 0x2157: + case 0x2158: case 0x2159: case 0x215a: case 0x215b: + case 0x215c: case 0x215d: case 0x215e: case 0x215f: + case 0x2160: case 0x2161: case 0x2162: case 0x2163: + case 0x2164: case 0x2165: case 0x2166: case 0x2167: + case 0x2168: case 0x2169: case 0x216a: case 0x216b: + case 0x216c: case 0x216d: case 0x216e: case 0x216f: + case 0x2170: case 0x2171: case 0x2172: case 0x2173: + case 0x2174: case 0x2175: case 0x2176: case 0x2177: + case 0x2178: case 0x2179: case 0x217a: case 0x217b: + case 0x217c: case 0x217d: case 0x217e: case 0x217f: +#ifdef SPCTOOL + return ((uint8) _SPCOutP [Address & 3]); +#else + // CPU.Flags |= DEBUG_MODE_FLAG; +#ifdef SPC700_SHUTDOWN + IAPU.APUExecuting = Settings.APUEnabled; + IAPU.WaitCounter++; +#endif + if (Settings.APUEnabled) + { +#ifdef CPU_SHUTDOWN +// CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + if (SNESGameFixes.APU_OutPorts_ReturnValueFix && + Address >= 0x2140 && Address <= 0x2143 && !CPU.V_Counter) + { + return (uint8)((Address & 1) ? ((rand() & 0xff00) >> 8) : + (rand() & 0xff)); + } + + return (APU.OutPorts [Address & 3]); + } + + switch (Settings.SoundSkipMethod) + { + case 0: + case 1: + CPU.BranchSkip = TRUE; + break; + case 2: + break; + case 3: + CPU.BranchSkip = TRUE; + break; + } + if (Address & 3 < 2) + { + int r = rand (); + if (r & 2) + { + if (r & 4) + return (Address & 3 == 1 ? 0xaa : 0xbb); + else + return ((r >> 3) & 0xff); + } + } + else + { + int r = rand (); + if (r & 2) + return ((r >> 3) & 0xff); + } + return (Memory.FillRAM[Address]); +#endif // SPCTOOL + + case 0x2180: + // Read WRAM +#ifdef DEBUGGER + missing.wram_read = 1; +#endif + byte = Memory.RAM [PPU.WRAM++]; + PPU.WRAM &= 0x1FFFF; + break; + case 0x2181: + case 0x2182: + case 0x2183: + return (Memory.FillRAM [Address]); + case 0x2190: + return (1); + } + } + else + { + if (Settings.SA1) + return (S9xGetSA1 (Address)); + + if (Address <= 0x2fff || Address >= 0x3000 + 768) + { + switch (Address) + { + case 0x21c2: + return (0x20); + case 0x21c3: + return (0); + case 0x2800: + // For Dai Kaijyu Monogatari II + if (Settings.SRTC) + return (S9xGetSRTC (Address)); + /*FALL*/ + + default: +#ifdef DEBUGGER + missing.unknownppu_read = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf (String, "Unknown register read: $%04X\n", Address); + S9xMessage (S9X_TRACE, S9X_PPU_TRACE, String); + } +#endif + // XXX: + return (0); //Memory.FillRAM[Address]); + } + } + + if (!Settings.SuperFX) + return (0x30); +#ifdef ZSNES_FX + if (Address < 0x3040) + byte = S9xSuperFXReadReg (Address); + else + byte = Memory.FillRAM [Address]; + +#ifdef CPU_SHUTDOWN + if (Address == 0x3030) + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + if (Address == 0x3031) + CLEAR_IRQ_SOURCE (GSU_IRQ_SOURCE); +#else + byte = Memory.FillRAM [Address]; + +//if (Address != 0x3030 && Address != 0x3031) +//printf ("%04x\n", Address); +#ifdef CPU_SHUTDOWN + if (Address == 0x3030) + { + CPU.WaitAddress = CPU.PCAtOpcodeStart; + } + else +#endif + if (Address == 0x3031) + { + CLEAR_IRQ_SOURCE (GSU_IRQ_SOURCE); + Memory.FillRAM [0x3031] = byte & 0x7f; + } + return (byte); +#endif + } + + return (byte); +} + +/**********************************************************************************************/ +/* S9xSetCPU() */ +/* This function sets a CPU/DMA Register to a specific byte */ +/**********************************************************************************************/ +void S9xSetCPU (uint8 byte, uint16 Address) +{ + int d; + + if (Address < 0x4200) + { +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + switch (Address) + { + case 0x4016: + // S9xReset reading of old-style joypads + if ((byte & 1) && !(Memory.FillRAM [Address] & 1)) + { + PPU.Joypad1ButtonReadPos = 0; + PPU.Joypad2ButtonReadPos = 0; + PPU.Joypad3ButtonReadPos = 0; + } + break; + case 0x4017: + break; + default: +#ifdef DEBUGGER + missing.unknowncpu_write = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf (String, "Unknown register register write: $%02X->$%04X\n", + byte, Address); + S9xMessage (S9X_TRACE, S9X_PPU_TRACE, String); + } +#endif + break; + } + } + else + switch (Address) + { + case 0x4200: + // NMI, V & H IRQ and joypad reading enable flags + if ((byte & 0x20) && + (!SNESGameFixes.umiharakawaseFix || PPU.IRQVBeamPos < 209)) + { + if (!PPU.VTimerEnabled) + { +#ifdef DEBUGGER + missing.virq = 1; + missing.virq_pos = PPU.IRQVBeamPos; +#endif + PPU.VTimerEnabled = TRUE; + if (PPU.HTimerEnabled) + S9xUpdateHTimer (); + else + if (PPU.IRQVBeamPos == CPU.V_Counter) + S9xSetIRQ (PPU_V_BEAM_IRQ_SOURCE); + } + } + else + { + PPU.VTimerEnabled = FALSE; +#ifndef RC_OPTIMIZED + if (SNESGameFixes.umiharakawaseFix) + byte &= ~0x20; +#endif + } + + if (byte & 0x10) + { + if (!PPU.HTimerEnabled) + { +#ifdef DEBUGGER + missing.hirq = 1; + missing.hirq_pos = PPU.IRQHBeamPos; +#endif + PPU.HTimerEnabled = TRUE; + S9xUpdateHTimer (); + } + } + else + { + // No need to check for HTimer being disabled as the scanline + // event trigger code won't trigger an H-IRQ unless its enabled. + PPU.HTimerEnabled = FALSE; + PPU.HTimerPosition = Settings.H_Max + 1; + } + +#ifndef RC_OPTIMIZED + if (!Settings.DaffyDuck) + CLEAR_IRQ_SOURCE (PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE); + + if ((byte & 0x80) && + !(Memory.FillRAM [0x4200] & 0x80) && + CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE && + CPU.V_Counter <= PPU.ScreenHeight + + (SNESGameFixes.alienVSpredetorFix ? 25 : 15) && //jyam 15->25 alien vs predetor +// Panic Bomberman clears the NMI pending flag @ scanline 230 before enabling +// NMIs again. The NMI routine crashes the CPU if it is called without the NMI +// pending flag being set... + (Memory.FillRAM [0x4210] & 0x80) && + !CPU.NMIActive) + { + CPU.Flags |= NMI_FLAG; + CPU.NMIActive = TRUE; + CPU.NMICycleCount = CPU.NMITriggerPoint; + } +#endif + break; + case 0x4201: + // I/O port output + case 0x4202: + // Multiplier (for multply) + break; + case 0x4203: + { + // Multiplicand + uint32 res = Memory.FillRAM[0x4202] * byte; + + Memory.FillRAM[0x4216] = (uint8) res; + Memory.FillRAM[0x4217] = (uint8) (res >> 8); + break; + } + case 0x4204: + case 0x4205: + // Low and high muliplier (for divide) + break; + case 0x4206: + { + // Divisor + uint16 a = Memory.FillRAM[0x4204] + (Memory.FillRAM[0x4205] << 8); + uint16 div = byte ? a / byte : 0xffff; + uint16 rem = byte ? a % byte : a; + + Memory.FillRAM[0x4214] = (uint8)div; + Memory.FillRAM[0x4215] = div >> 8; + Memory.FillRAM[0x4216] = (uint8)rem; + Memory.FillRAM[0x4217] = rem >> 8; + break; + } + case 0x4207: + d = PPU.IRQHBeamPos; + PPU.IRQHBeamPos = (PPU.IRQHBeamPos & 0xFF00) | byte; + + if (PPU.HTimerEnabled && PPU.IRQHBeamPos != d) + S9xUpdateHTimer (); + break; + + case 0x4208: + d = PPU.IRQHBeamPos; + PPU.IRQHBeamPos = (PPU.IRQHBeamPos & 0xFF) | ((byte & 1) << 8); + + if (PPU.HTimerEnabled && PPU.IRQHBeamPos != d) + S9xUpdateHTimer (); + + break; + + case 0x4209: + d = PPU.IRQVBeamPos; + PPU.IRQVBeamPos = (PPU.IRQVBeamPos & 0xFF00) | byte; +#ifdef DEBUGGER + missing.virq_pos = PPU.IRQVBeamPos; +#endif + if (PPU.VTimerEnabled && PPU.IRQVBeamPos != d) + { + if (PPU.HTimerEnabled) + S9xUpdateHTimer (); + else + { + if (PPU.IRQVBeamPos == CPU.V_Counter) + S9xSetIRQ (PPU_V_BEAM_IRQ_SOURCE); + } + } + break; + + case 0x420A: + d = PPU.IRQVBeamPos; + PPU.IRQVBeamPos = (PPU.IRQVBeamPos & 0xFF) | ((byte & 1) << 8); +#ifdef DEBUGGER + missing.virq_pos = PPU.IRQVBeamPos; +#endif + if (PPU.VTimerEnabled && PPU.IRQVBeamPos != d) + { + if (PPU.HTimerEnabled) + S9xUpdateHTimer (); + else + { + if (PPU.IRQVBeamPos == CPU.V_Counter) + S9xSetIRQ (PPU_V_BEAM_IRQ_SOURCE); + } + } + break; + + case 0x420B: +#ifdef DEBUGGER + missing.dma_this_frame = byte; + missing.dma_channels = byte; +#endif + if ((byte & 0x01) != 0) + S9xDoDMA (0); + if ((byte & 0x02) != 0) + S9xDoDMA (1); + if ((byte & 0x04) != 0) + S9xDoDMA (2); + if ((byte & 0x08) != 0) + S9xDoDMA (3); + if ((byte & 0x10) != 0) + S9xDoDMA (4); + if ((byte & 0x20) != 0) + S9xDoDMA (5); + if ((byte & 0x40) != 0) + S9xDoDMA (6); + if ((byte & 0x80) != 0) + S9xDoDMA (7); + break; + case 0x420C: +#ifdef DEBUGGER + missing.hdma_this_frame |= byte; + missing.hdma_channels |= byte; +#endif + if (Settings.DisableHDMA) + byte = 0; + Memory.FillRAM[0x420c] = byte; + IPPU.HDMA = byte; + break; + + case 0x420d: + // Cycle speed 0 - 2.68Mhz, 1 - 3.58Mhz (banks 0x80 +) + if ((byte & 1) != (Memory.FillRAM [0x420d] & 1)) + { + if (byte & 1) + { + CPU.FastROMSpeed = ONE_CYCLE; +#ifdef DEBUGGER + missing.fast_rom = 1; +#endif + } + else + CPU.FastROMSpeed = SLOW_ONE_CYCLE; + + Memory.FixROMSpeed (); + } + /* FALL */ + case 0x420e: + case 0x420f: + // --->>> Unknown + break; + case 0x4210: + // NMI ocurred flag (reset on read or write) + Memory.FillRAM[0x4210] = 0; + return; + case 0x4211: + // IRQ ocurred flag (reset on read or write) + CLEAR_IRQ_SOURCE (PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE); + break; + case 0x4212: + // v-blank, h-blank and joypad being scanned flags (read-only) + case 0x4213: + // I/O Port (read-only) + case 0x4214: + case 0x4215: + // Quotent of divide (read-only) + case 0x4216: + case 0x4217: + // Multiply product (read-only) + return; + case 0x4218: + case 0x4219: + case 0x421a: + case 0x421b: + case 0x421c: + case 0x421d: + case 0x421e: + case 0x421f: + // Joypad values (read-only) + return; + + case 0x4300: + case 0x4310: + case 0x4320: + case 0x4330: + case 0x4340: + case 0x4350: + case 0x4360: + case 0x4370: + d = (Address >> 4) & 0x7; + DMA[d].TransferDirection = (byte & 128) != 0 ? 1 : 0; + DMA[d].HDMAIndirectAddressing = (byte & 64) != 0 ? 1 : 0; + DMA[d].AAddressDecrement = (byte & 16) != 0 ? 1 : 0; + DMA[d].AAddressFixed = (byte & 8) != 0 ? 1 : 0; + DMA[d].TransferMode = (byte & 7); + break; + + case 0x4301: + case 0x4311: + case 0x4321: + case 0x4331: + case 0x4341: + case 0x4351: + case 0x4361: + case 0x4371: + DMA[((Address >> 4) & 0x7)].BAddress = byte; + break; + + case 0x4302: + case 0x4312: + case 0x4322: + case 0x4332: + case 0x4342: + case 0x4352: + case 0x4362: + case 0x4372: + d = (Address >> 4) & 0x7; + DMA[d].AAddress &= 0xFF00; + DMA[d].AAddress |= byte; + break; + + case 0x4303: + case 0x4313: + case 0x4323: + case 0x4333: + case 0x4343: + case 0x4353: + case 0x4363: + case 0x4373: + d = (Address >> 4) & 0x7; + DMA[d].AAddress &= 0xFF; + DMA[d].AAddress |= byte << 8; + break; + + case 0x4304: + case 0x4314: + case 0x4324: + case 0x4334: + case 0x4344: + case 0x4354: + case 0x4364: + case 0x4374: + DMA[((Address >> 4) & 0x7)].ABank = byte; + break; + + case 0x4305: + case 0x4315: + case 0x4325: + case 0x4335: + case 0x4345: + case 0x4355: + case 0x4365: + case 0x4375: + d = (Address >> 4) & 0x7; + DMA[d].TransferBytes &= 0xFF00; + DMA[d].TransferBytes |= byte; + DMA[d].IndirectAddress &= 0xff00; + DMA[d].IndirectAddress |= byte; + break; + + case 0x4306: + case 0x4316: + case 0x4326: + case 0x4336: + case 0x4346: + case 0x4356: + case 0x4366: + case 0x4376: + d = (Address >> 4) & 0x7; + DMA[d].TransferBytes &= 0xFF; + DMA[d].TransferBytes |= byte << 8; + DMA[d].IndirectAddress &= 0xff; + DMA[d].IndirectAddress |= byte << 8; + break; + + case 0x4307: + case 0x4317: + case 0x4327: + case 0x4337: + case 0x4347: + case 0x4357: + case 0x4367: + case 0x4377: + DMA[d = ((Address >> 4) & 0x7)].IndirectBank = byte; + break; + + case 0x4308: + case 0x4318: + case 0x4328: + case 0x4338: + case 0x4348: + case 0x4358: + case 0x4368: + case 0x4378: + d = (Address >> 4) & 7; + DMA[d].Address &= 0xff00; + DMA[d].Address |= byte; + break; + + case 0x4309: + case 0x4319: + case 0x4329: + case 0x4339: + case 0x4349: + case 0x4359: + case 0x4369: + case 0x4379: + d = (Address >> 4) & 0x7; + DMA[d].Address &= 0xff; + DMA[d].Address |= byte << 8; + break; + + case 0x430A: + case 0x431A: + case 0x432A: + case 0x433A: + case 0x434A: + case 0x435A: + case 0x436A: + case 0x437A: + d = (Address >> 4) & 0x7; + DMA[d].LineCount = byte & 0x7f; + DMA[d].Repeat = !(byte & 0x80); + break; + + case 0x4800: + case 0x4801: + case 0x4802: + case 0x4803: +//printf ("%02x->%04x\n", byte, Address); + break; + + case 0x4804: + case 0x4805: + case 0x4806: + case 0x4807: +//printf ("%02x->%04x\n", byte, Address); + + S9xSetSDD1MemoryMap (Address - 0x4804, byte & 7); + break; + default: +#ifdef DEBUGGER + missing.unknowncpu_write = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf (String, "Unknown register write: $%02X->$%04X\n", + byte, Address); + S9xMessage (S9X_TRACE, S9X_PPU_TRACE, String); + } +#endif + break; + } + Memory.FillRAM [Address] = byte; +} + +/**********************************************************************************************/ +/* S9xGetCPU() */ +/* This function retrieves a CPU/DMA Register */ +/**********************************************************************************************/ +uint8 S9xGetCPU (uint16 Address) +{ + uint8 byte; + + if (Address < 0x4200) + { +#ifdef VAR_CYCLES + CPU.Cycles += ONE_CYCLE; +#endif + switch (Address) + { + // Secret of the Evermore + case 0x4000: + case 0x4001: + return (0x40); + + case 0x4016: + { + if (Memory.FillRAM [0x4016] & 1) + { + if ((!Settings.SwapJoypads && + IPPU.Controller == SNES_MOUSE_SWAPPED) || + (Settings.SwapJoypads && + IPPU.Controller == SNES_MOUSE)) + { + if (++PPU.MouseSpeed [0] > 2) + PPU.MouseSpeed [0] = 0; + } + return (0); + } + + int ind = Settings.SwapJoypads ? 1 : 0; + byte = IPPU.Joypads[ind] >> (PPU.Joypad1ButtonReadPos ^ 15); + PPU.Joypad1ButtonReadPos++; + return (byte & 1); + } + case 0x4017: + { + if (Memory.FillRAM [0x4016] & 1) + { + // MultiPlayer5 adaptor is only allowed to be plugged into port 2 + switch (IPPU.Controller) + { + case SNES_MULTIPLAYER5: + return (2); + case SNES_MOUSE_SWAPPED: + if (Settings.SwapJoypads && ++PPU.MouseSpeed [0] > 2) + PPU.MouseSpeed [0] = 0; + break; + + case SNES_MOUSE: + if (!Settings.SwapJoypads && ++PPU.MouseSpeed [0] > 2) + PPU.MouseSpeed [0] = 0; + break; + } + return (0x00); + } + + int ind = Settings.SwapJoypads ? 0 : 1; + + if (IPPU.Controller == SNES_MULTIPLAYER5) + { + if (Memory.FillRAM [0x4201] & 0x80) + { + byte = ((IPPU.Joypads[ind] >> (PPU.Joypad2ButtonReadPos ^ 15)) & 1) | + (((IPPU.Joypads[2] >> (PPU.Joypad2ButtonReadPos ^ 15)) & 1) << 1); + PPU.Joypad2ButtonReadPos++; + return (byte); + } + else + { + byte = ((IPPU.Joypads[3] >> (PPU.Joypad3ButtonReadPos ^ 15)) & 1) | + (((IPPU.Joypads[4] >> (PPU.Joypad3ButtonReadPos ^ 15)) & 1) << 1); + PPU.Joypad3ButtonReadPos++; + return (byte); + } + } + return ((IPPU.Joypads[ind] >> (PPU.Joypad2ButtonReadPos++ ^ 15)) & 1); + } + default: +#ifdef DEBUGGER + missing.unknowncpu_read = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf (String, "Unknown register read: $%04X\n", Address); + S9xMessage (S9X_TRACE, S9X_PPU_TRACE, String); + } +#endif + break; + } + return (Memory.FillRAM [Address]); + } + else + switch (Address) + { + // BS Dynami Tracer! needs to be able to check if NMIs are enabled + // already, otherwise the game locks up. + case 0x4200: + // NMI, h & v timers and joypad reading enable + if (SNESGameFixes.Old_Read0x4200) + { +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + return (REGISTER_4212()); + } + case 0x4201: + // I/O port (output - write only?) + case 0x4202: + case 0x4203: + // Multiplier and multiplicand (write) + case 0x4204: + case 0x4205: + case 0x4206: + // Divisor and dividend (write) + return (Memory.FillRAM[Address]); + case 0x4207: + return (uint8)(PPU.IRQHBeamPos); + case 0x4208: + return (PPU.IRQHBeamPos >> 8); + case 0x4209: + return (uint8)(PPU.IRQVBeamPos); + case 0x420a: + return (PPU.IRQVBeamPos >> 8); + case 0x420b: + // General purpose DMA enable + // Super Formation Soccer 95 della Serie A UCC Xaqua requires this + // register should not always return zero. + // .. But Aero 2 waits until this register goes zero.. + // Just keep toggling the value for now in the hope that it breaks + // the game out of its wait loop... + Memory.FillRAM [0x420b] = !Memory.FillRAM [0x420b]; + return (Memory.FillRAM [0x420b]); + case 0x420c: + // H-DMA enable + return (IPPU.HDMA); + case 0x420d: + // Cycle speed 0 - 2.68Mhz, 1 - 3.58Mhz (banks 0x80 +) + return (Memory.FillRAM[Address]); + case 0x420e: + case 0x420f: + // --->>> Unknown + return (Memory.FillRAM[Address]); + case 0x4210: +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + byte = Memory.FillRAM[0x4210]; + Memory.FillRAM[0x4210] = 0; + return (byte); + case 0x4211: + byte = (CPU.IRQActive & (PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE)) ? 0x80 : 0; + // Super Robot Wars Ex ROM bug requires this. + byte |= CPU.Cycles >= Settings.HBlankStart ? 0x40 : 0; + CLEAR_IRQ_SOURCE (PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE); + return (byte); + case 0x4212: + // V-blank, h-blank and joypads being read flags (read-only) +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + return (REGISTER_4212()); + case 0x4213: + // I/O port input + case 0x4214: + case 0x4215: + // Quotient of divide result + case 0x4216: + case 0x4217: + // Multiplcation result (for multiply) or remainder of + // divison. + return (Memory.FillRAM[Address]); + case 0x4218: + case 0x4219: + case 0x421a: + case 0x421b: + case 0x421c: + case 0x421d: + case 0x421e: + case 0x421f: + // Joypads 1-4 button and direction state. + return (Memory.FillRAM [Address]); + + case 0x4300: + case 0x4310: + case 0x4320: + case 0x4330: + case 0x4340: + case 0x4350: + case 0x4360: + case 0x4370: + // DMA direction, address type, fixed flag, + return (Memory.FillRAM[Address]); + + case 0x4301: + case 0x4311: + case 0x4321: + case 0x4331: + case 0x4341: + case 0x4351: + case 0x4361: + case 0x4371: + return (Memory.FillRAM[Address]); + + case 0x4302: + case 0x4312: + case 0x4322: + case 0x4332: + case 0x4342: + case 0x4352: + case 0x4362: + case 0x4372: + return (Memory.FillRAM[Address]); + + case 0x4303: + case 0x4313: + case 0x4323: + case 0x4333: + case 0x4343: + case 0x4353: + case 0x4363: + case 0x4373: + return (Memory.FillRAM[Address]); + + case 0x4304: + case 0x4314: + case 0x4324: + case 0x4334: + case 0x4344: + case 0x4354: + case 0x4364: + case 0x4374: + return (Memory.FillRAM[Address]); + + case 0x4305: + case 0x4315: + case 0x4325: + case 0x4335: + case 0x4345: + case 0x4355: + case 0x4365: + case 0x4375: + return (Memory.FillRAM[Address]); + + case 0x4306: + case 0x4316: + case 0x4326: + case 0x4336: + case 0x4346: + case 0x4356: + case 0x4366: + case 0x4376: + return (Memory.FillRAM[Address]); + + case 0x4307: + case 0x4317: + case 0x4327: + case 0x4337: + case 0x4347: + case 0x4357: + case 0x4367: + case 0x4377: + return (DMA[(Address >> 4) & 7].IndirectBank); + + case 0x4308: + case 0x4318: + case 0x4328: + case 0x4338: + case 0x4348: + case 0x4358: + case 0x4368: + case 0x4378: + return (Memory.FillRAM[Address]); + + case 0x4309: + case 0x4319: + case 0x4329: + case 0x4339: + case 0x4349: + case 0x4359: + case 0x4369: + case 0x4379: + return (Memory.FillRAM[Address]); + + case 0x430A: + case 0x431A: + case 0x432A: + case 0x433A: + case 0x434A: + case 0x435A: + case 0x436A: + case 0x437A: + { + int d = (Address & 0x70) >> 4; + if (IPPU.HDMA & (1 << d)) + { + return (DMA[d].LineCount); + } + return (Memory.FillRAM[Address]); + } + default: +#ifdef DEBUGGER + missing.unknowncpu_read = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf (String, "Unknown register read: $%04X\n", Address); + S9xMessage (S9X_TRACE, S9X_PPU_TRACE, String); + } + +#endif + break; + } + return (Memory.FillRAM[Address]); +} + +void S9xResetPPU () +{ + PPU.BGMode = 0; + PPU.BG3Priority = 0; + PPU.Brightness = 0; + PPU.VMA.High = 0; + PPU.VMA.Increment = 1; + PPU.VMA.Address = 0; + PPU.VMA.FullGraphicCount = 0; + PPU.VMA.Shift = 0; + + for (uint8 B = 0; B != 4; B++) + { + PPU.BG[B].SCBase = 0; + PPU.BG[B].VOffset = 0; + PPU.BG[B].HOffset = 0; + PPU.BG[B].BGSize = 0; + PPU.BG[B].NameBase = 0; + PPU.BG[B].SCSize = 0; + + PPU.ClipCounts[B] = 0; + PPU.ClipWindowOverlapLogic [B] = CLIP_OR; + PPU.ClipWindow1Enable[B] = FALSE; + PPU.ClipWindow2Enable[B] = FALSE; + PPU.ClipWindow1Inside[B] = TRUE; + PPU.ClipWindow2Inside[B] = TRUE; + } + + PPU.ClipCounts[4] = 0; + PPU.ClipCounts[5] = 0; + PPU.ClipWindowOverlapLogic[4] = PPU.ClipWindowOverlapLogic[5] = CLIP_OR; + PPU.ClipWindow1Enable[4] = PPU.ClipWindow1Enable[5] = FALSE; + PPU.ClipWindow2Enable[4] = PPU.ClipWindow2Enable[5] = FALSE; + PPU.ClipWindow1Inside[4] = PPU.ClipWindow1Inside[5] = TRUE; + PPU.ClipWindow2Inside[4] = PPU.ClipWindow2Inside[5] = TRUE; + + PPU.CGFLIP = 0; + int c; + for (c = 0; c < 256; c++) + { + IPPU.Red [c] = (c & 7) << 2; + IPPU.Green [c] = ((c >> 3) & 7) << 2; + IPPU.Blue [c] = ((c >> 6) & 2) << 3; + PPU.CGDATA [c] = IPPU.Red [c] | (IPPU.Green [c] << 5) | + (IPPU.Blue [c] << 10); + } + + PPU.FirstSprite = 0; + PPU.LastSprite = 127; + for (int Sprite = 0; Sprite < 128; Sprite++) + { + PPU.OBJ[Sprite].HPos = 0; + PPU.OBJ[Sprite].VPos = 0; + PPU.OBJ[Sprite].VFlip = 0; + PPU.OBJ[Sprite].HFlip = 0; + PPU.OBJ[Sprite].Priority = 0; + PPU.OBJ[Sprite].Palette = 0; + PPU.OBJ[Sprite].Name = 0; + PPU.OBJ[Sprite].Size = 0; + } + PPU.OAMPriorityRotation = 0; + + PPU.OAMFlip = 0; + PPU.OAMTileAddress = 0; + PPU.OAMAddr = 0; + PPU.IRQVBeamPos = 0; + PPU.IRQHBeamPos = 0; + PPU.VBeamPosLatched = 0; + PPU.HBeamPosLatched = 0; + + PPU.HBeamFlip = 0; + PPU.VBeamFlip = 0; + PPU.HVBeamCounterLatched = 0; + + PPU.MatrixA = PPU.MatrixB = PPU.MatrixC = PPU.MatrixD = 0; + PPU.CentreX = PPU.CentreY = 0; + PPU.Joypad1ButtonReadPos = 0; + PPU.Joypad2ButtonReadPos = 0; + PPU.Joypad3ButtonReadPos = 0; + + PPU.CGADD = 0; + PPU.FixedColourRed = PPU.FixedColourGreen = PPU.FixedColourBlue = 0; + PPU.SavedOAMAddr = 0; + PPU.ScreenHeight = SNES_HEIGHT; + PPU.WRAM = 0; + PPU.BG_Forced = 0; + PPU.ForcedBlanking = TRUE; + PPU.OBJThroughMain = FALSE; + PPU.OBJThroughSub = FALSE; + PPU.OBJSizeSelect = 0; + PPU.OBJNameSelect = 0; + PPU.OBJNameBase = 0; + PPU.OBJAddition = FALSE; + PPU.OAMReadFlip = 0; + ZeroMemory (PPU.OAMData, 512 + 32); + + PPU.VTimerEnabled = FALSE; + PPU.HTimerEnabled = FALSE; + PPU.HTimerPosition = Settings.H_Max + 1; + PPU.Mosaic = 0; + PPU.BGMosaic [0] = PPU.BGMosaic [1] = FALSE; + PPU.BGMosaic [2] = PPU.BGMosaic [3] = FALSE; + PPU.Mode7HFlip = FALSE; + PPU.Mode7VFlip = FALSE; + PPU.Mode7Repeat = 0; + PPU.Window1Left = 1; + PPU.Window1Right = 0; + PPU.Window2Left = 1; + PPU.Window2Right = 0; + PPU.RecomputeClipWindows = TRUE; + PPU.CGFLIPRead = 0; + PPU.Need16x8Mulitply = FALSE; + PPU.MouseSpeed[0] = PPU.MouseSpeed[1] = 0; + + IPPU.ColorsChanged = TRUE; + IPPU.HDMA = 0; + IPPU.HDMAStarted = FALSE; + IPPU.MaxBrightness = 0; + IPPU.LatchedBlanking = 0; + IPPU.OBJChanged = TRUE; + IPPU.RenderThisFrame = TRUE; + IPPU.DirectColourMapsNeedRebuild = TRUE; + IPPU.FrameCount = 0; + IPPU.RenderedFramesCount = 0; + IPPU.DisplayedRenderedFrameCount = 0; + IPPU.SkippedFrames = 0; + IPPU.FrameSkip = 0; + ZeroMemory (IPPU.TileCached [TILE_2BIT], MAX_2BIT_TILES); + ZeroMemory (IPPU.TileCached [TILE_4BIT], MAX_4BIT_TILES); + ZeroMemory (IPPU.TileCached [TILE_8BIT], MAX_8BIT_TILES); + IPPU.FirstVRAMRead = FALSE; + IPPU.LatchedInterlace = FALSE; + IPPU.DoubleWidthPixels = FALSE; + IPPU.RenderedScreenWidth = SNES_WIDTH; + IPPU.RenderedScreenHeight = SNES_HEIGHT; + IPPU.XB = NULL; + for (c = 0; c < 256; c++) + IPPU.ScreenColors [c] = c; + S9xFixColourBrightness (); + IPPU.PreviousLine = IPPU.CurrentLine = 0; + IPPU.Joypads[0] = IPPU.Joypads[1] = IPPU.Joypads[2] = 0; + IPPU.Joypads[3] = IPPU.Joypads[4] = 0; + IPPU.SuperScope = 0; + IPPU.Mouse[0] = IPPU.Mouse[1] = 0; + IPPU.PrevMouseX[0] = IPPU.PrevMouseX[1] = 256 / 2; + IPPU.PrevMouseY[0] = IPPU.PrevMouseY[1] = 224 / 2; + + if (Settings.ControllerOption == 0) + IPPU.Controller = SNES_MAX_CONTROLLER_OPTIONS - 1; + else + IPPU.Controller = Settings.ControllerOption - 1; + S9xNextController (); + + for (c = 0; c < 2; c++) + memset (&IPPU.Clip [c], 0, sizeof (struct ClipData)); + + if (Settings.MouseMaster) + { + S9xProcessMouse (0); + S9xProcessMouse (1); + } + for (c = 0; c < 0x8000; c += 0x100) + memset (&Memory.FillRAM [c], c >> 8, 0x100); + + ZeroMemory (&Memory.FillRAM [0x2100], 0x100); + ZeroMemory (&Memory.FillRAM [0x4200], 0x100); + ZeroMemory (&Memory.FillRAM [0x4000], 0x100); + // For BS Suttehakkun 2... + ZeroMemory (&Memory.FillRAM [0x1000], 0x1000); +} + +void S9xProcessMouse (int which1) +{ + int x, y; + uint32 buttons; + + if ((IPPU.Controller == SNES_MOUSE || IPPU.Controller == SNES_MOUSE_SWAPPED) && + S9xReadMousePosition (which1, x, y, buttons)) + { + int delta_x, delta_y; +#define MOUSE_SIGNATURE 0x1 + IPPU.Mouse [which1] = MOUSE_SIGNATURE | + (PPU.MouseSpeed [which1] << 4) | + ((buttons & 1) << 6) | ((buttons & 2) << 6); + + delta_x = x - IPPU.PrevMouseX[which1]; + delta_y = y - IPPU.PrevMouseY[which1]; + + if (delta_x > 63) + { + delta_x = 63; + IPPU.PrevMouseX[which1] += 63; + } + else + if (delta_x < -63) + { + delta_x = -63; + IPPU.PrevMouseX[which1] -= 63; + } + else + IPPU.PrevMouseX[which1] = x; + + if (delta_y > 63) + { + delta_y = 63; + IPPU.PrevMouseY[which1] += 63; + } + else + if (delta_y < -63) + { + delta_y = -63; + IPPU.PrevMouseY[which1] -= 63; + } + else + IPPU.PrevMouseY[which1] = y; + + if (delta_x < 0) + { + delta_x = -delta_x; + IPPU.Mouse [which1] |= (delta_x | 0x80) << 16; + } + else + IPPU.Mouse [which1] |= delta_x << 16; + + if (delta_y < 0) + { + delta_y = -delta_y; + IPPU.Mouse [which1] |= (delta_y | 0x80) << 24; + } + else + IPPU.Mouse [which1] |= delta_y << 24; + + if (IPPU.Controller == SNES_MOUSE_SWAPPED) + IPPU.Joypads [0] = IPPU.Mouse [which1]; + else + IPPU.Joypads [1] = IPPU.Mouse [which1]; + } +} + +void ProcessSuperScope () +{ + int x, y; + uint32 buttons; + + if (IPPU.Controller == SNES_SUPERSCOPE && + S9xReadSuperScopePosition (x, y, buttons)) + { +#define SUPERSCOPE_SIGNATURE 0x00ff + uint32 scope; + + scope = SUPERSCOPE_SIGNATURE | ((buttons & 1) << (7 + 8)) | + ((buttons & 2) << (5 + 8)) | ((buttons & 4) << (3 + 8)) | + ((buttons & 8) << (1 + 8)); + if (x > 255) + x = 255; + if (x < 0) + x = 0; + if (y > PPU.ScreenHeight - 1) + y = PPU.ScreenHeight - 1; + if (y < 0) + y = 0; + + PPU.VBeamPosLatched = (uint16) (y + 1); + PPU.HBeamPosLatched = (uint16) x; + PPU.HVBeamCounterLatched = TRUE; + Memory.FillRAM [0x213F] |= 0x40; + IPPU.Joypads [1] = scope; + } +} + +void S9xNextController () +{ + switch (IPPU.Controller) + { + case SNES_MULTIPLAYER5: + IPPU.Controller = SNES_JOYPAD; + break; + case SNES_JOYPAD: + if (Settings.MouseMaster) + { + IPPU.Controller = SNES_MOUSE_SWAPPED; + break; + } + case SNES_MOUSE_SWAPPED: + if (Settings.MouseMaster) + { + IPPU.Controller = SNES_MOUSE; + break; + } + case SNES_MOUSE: + if (Settings.SuperScopeMaster) + { + IPPU.Controller = SNES_SUPERSCOPE; + break; + } + case SNES_SUPERSCOPE: + if (Settings.MultiPlayer5Master) + { + IPPU.Controller = SNES_MULTIPLAYER5; + break; + } + default: + IPPU.Controller = SNES_JOYPAD; + break; + } +} + +void S9xUpdateJoypads () +{ +#ifdef _SNESPPC + int i = 0; +#else + int i; + + for (i = 0; i < 5; i++) +#endif + { + IPPU.Joypads [i] = S9xReadJoypad (i); + if (IPPU.Joypads [i] & SNES_LEFT_MASK) + IPPU.Joypads [i] &= ~SNES_RIGHT_MASK; + if (IPPU.Joypads [i] & SNES_UP_MASK) + IPPU.Joypads [i] &= ~SNES_DOWN_MASK; + } + + //touhaiden controller Fix + if (SNESGameFixes.TouhaidenControllerFix && + (IPPU.Controller == SNES_JOYPAD || IPPU.Controller == SNES_MULTIPLAYER5)) + { + for (i = 0; i < 5; i++) + { + if (IPPU.Joypads [i]) + IPPU.Joypads [i] |= 0xffff0000; + } + } + + // Read mouse position if enabled + if (Settings.MouseMaster) + { + for (i = 0; i < 2; i++) + S9xProcessMouse (i); + } + + // Read SuperScope if enabled + if (Settings.SuperScopeMaster) + ProcessSuperScope (); + + if (Memory.FillRAM [0x4200] & 1) + { + PPU.Joypad1ButtonReadPos = 16; + if (Memory.FillRAM [0x4201] & 0x80) + { + PPU.Joypad2ButtonReadPos = 16; + PPU.Joypad3ButtonReadPos = 0; + } + else + { + PPU.Joypad2ButtonReadPos = 0; + PPU.Joypad3ButtonReadPos = 16; + } + int ind = Settings.SwapJoypads ? 1 : 0; + + Memory.FillRAM [0x4218] = (uint8) IPPU.Joypads [ind]; + Memory.FillRAM [0x4219] = (uint8) (IPPU.Joypads [ind] >> 8); + Memory.FillRAM [0x421a] = (uint8) IPPU.Joypads [ind ^ 1]; + Memory.FillRAM [0x421b] = (uint8) (IPPU.Joypads [ind ^ 1] >> 8); + if (Memory.FillRAM [0x4201] & 0x80) + { + Memory.FillRAM [0x421c] = (uint8) IPPU.Joypads [ind]; + Memory.FillRAM [0x421d] = (uint8) (IPPU.Joypads [ind] >> 8); + Memory.FillRAM [0x421e] = (uint8) IPPU.Joypads [2]; + Memory.FillRAM [0x421f] = (uint8) (IPPU.Joypads [2] >> 8); + } + else + { + Memory.FillRAM [0x421c] = (uint8) IPPU.Joypads [3]; + Memory.FillRAM [0x421d] = (uint8) (IPPU.Joypads [3] >> 8); + Memory.FillRAM [0x421e] = (uint8) IPPU.Joypads [4]; + Memory.FillRAM [0x421f] = (uint8) (IPPU.Joypads [4] >> 8); + } + } +} + +#ifndef ZSNES_FX +void S9xSuperFXExec () +{ +#if 1 + if (Settings.SuperFX) + { + if ((Memory.FillRAM [0x3000 + GSU_SFR] & FLG_G) && + (Memory.FillRAM [0x3000 + GSU_SCMR] & 0x18) == 0x18) + { + if (!Settings.WinterGold) + FxEmulate (~0); + else + FxEmulate ((Memory.FillRAM [0x3000 + GSU_CLSR] & 1) ? 700 : 350); + int GSUStatus = Memory.FillRAM [0x3000 + GSU_SFR] | + (Memory.FillRAM [0x3000 + GSU_SFR + 1] << 8); + if ((GSUStatus & (FLG_G | FLG_IRQ)) == FLG_IRQ) + { + // Trigger a GSU IRQ. + S9xSetIRQ (GSU_IRQ_SOURCE); + } + } + } +#else + uint32 tmp = (Memory.FillRAM[0x3034] << 16) + *(uint16 *) &Memory.FillRAM [0x301e]; + +#if 0 + if (tmp == 0x018428) + { + *(uint16 *) &SRAM [0x0064] = 0xbc00; + *(uint16 *) &SRAM [0x002c] = 0x8000; + } +#endif + if (tmp == -1)//0x018428) //0x01bfc3) //0x09edaf) //-1) //0x57edaf) + { + while (Memory.FillRAM [0x3030] & 0x20) + { + int i; + int32 vError; + uint8 avReg[0x40]; + char tmp[128]; + uint8 vPipe; + uint8 vColr; + uint8 vPor; + + FxPipeString (tmp); + /* Make the string 32 chars long */ + if(strlen(tmp) < 32) { memset(&tmp[strlen(tmp)],' ',32-strlen(tmp)); tmp[32] = 0; } + + /* Copy registers (so we can see if any changed) */ + vColr = FxGetColorRegister(); + vPor = FxGetPlotOptionRegister(); + memcpy(avReg,SuperFX.pvRegisters,0x40); + + /* Print the pipe string */ + printf(tmp); + + /* Execute the instruction in the pipe */ + vPipe = FxPipe(); + vError = FxEmulate(1); + + /* Check if any registers changed (and print them if they did) */ + for(i=0; i<16; i++) + { + uint32 a = 0; + uint32 r1 = ((uint32)avReg[i*2]) | (((uint32)avReg[(i*2)+1])<<8); + uint32 r2 = (uint32)(SuperFX.pvRegisters[i*2]) | (((uint32)SuperFX.pvRegisters[(i*2)+1])<<8); + if(i==15) + a = OPCODE_BYTES(vPipe); + if(((r1+a)&0xffff) != r2) + printf(" r%d=$%04x",i,r2); + } + { + /* Check SFR */ + uint32 r1 = ((uint32)avReg[0x30]) | (((uint32)avReg[0x31])<<8); + uint32 r2 = (uint32)(SuperFX.pvRegisters[0x30]) | (((uint32)SuperFX.pvRegisters[0x31])<<8); + if((r1&(1<<1)) != (r2&(1<<1))) + printf(" Z=%d",(uint32)(!!(r2&(1<<1)))); + if((r1&(1<<2)) != (r2&(1<<2))) + printf(" CY=%d",(uint32)(!!(r2&(1<<2)))); + if((r1&(1<<3)) != (r2&(1<<3))) + printf(" S=%d",(uint32)(!!(r2&(1<<3)))); + if((r1&(1<<4)) != (r2&(1<<4))) + printf(" OV=%d",(uint32)(!!(r2&(1<<4)))); + if((r1&(1<<5)) != (r2&(1<<5))) + printf(" G=%d",(uint32)(!!(r2&(1<<5)))); + if((r1&(1<<6)) != (r2&(1<<6))) + printf(" R=%d",(uint32)(!!(r2&(1<<6)))); + if((r1&(1<<8)) != (r2&(1<<8))) + printf(" ALT1=%d",(uint32)(!!(r2&(1<<8)))); + if((r1&(1<<9)) != (r2&(1<<9))) + printf(" ALT2=%d",(uint32)(!!(r2&(1<<9)))); + if((r1&(1<<10)) != (r2&(1<<10))) + printf(" IL=%d",(uint32)(!!(r2&(1<<10)))); + if((r1&(1<<11)) != (r2&(1<<11))) + printf(" IH=%d",(uint32)(!!(r2&(1<<11)))); + if((r1&(1<<12)) != (r2&(1<<12))) + printf(" B=%d",(uint32)(!!(r2&(1<<12)))); + if((r1&(1<<15)) != (r2&(1<<15))) + printf(" IRQ=%d",(uint32)(!!(r2&(1<<15)))); + } + { + /* Check PBR */ + uint32 r1 = ((uint32)avReg[0x34]); + uint32 r2 = (uint32)(SuperFX.pvRegisters[0x34]); + if(r1 != r2) + printf(" PBR=$%02x",r2); + } + { + /* Check ROMBR */ + uint32 r1 = ((uint32)avReg[0x36]); + uint32 r2 = (uint32)(SuperFX.pvRegisters[0x36]); + if(r1 != r2) + printf(" ROMBR=$%02x",r2); + } + { + /* Check RAMBR */ + uint32 r1 = ((uint32)avReg[0x3c]); + uint32 r2 = (uint32)(SuperFX.pvRegisters[0x3c]); + if(r1 != r2) + printf(" RAMBR=$%02x",r2); + } + { + /* Check CBR */ + uint32 r1 = ((uint32)avReg[0x3e]) | (((uint32)avReg[0x3f])<<8); + uint32 r2 = (uint32)(SuperFX.pvRegisters[0x3e]) | (((uint32)SuperFX.pvRegisters[0x3f])<<8); + if(r1 != r2) + printf(" CBR=$%04x",r2); + } + { + /* Check COLR */ + if(vColr != FxGetColorRegister()) + printf(" COLR=$%02x",FxGetColorRegister()); + } + { + /* Check POR */ + if(vPor != FxGetPlotOptionRegister()) + printf(" POR=$%02x",FxGetPlotOptionRegister()); + } + printf ("\n"); + } + S9xExit (); + } + else + { + uint32 t = (Memory.FillRAM [0x3034] << 16) + + (Memory.FillRAM [0x301f] << 8) + + (Memory.FillRAM [0x301e] << 0); + +printf ("%06x: %d\n", t, FxEmulate (2000000)); +// FxEmulate (2000000); + } +#if 0 + if (!(CPU.Flags & TRACE_FLAG)) + { + static int z = 1; + if (z == 0) + { + extern FILE *trace; + CPU.Flags |= TRACE_FLAG; + trace = fopen ("trace.log", "wb"); + } + else + z--; + } +#endif + Memory.FillRAM [0x3030] &= ~0x20; + if (Memory.FillRAM [0x3031] & 0x80) + { + S9xSetIRQ (GSU_IRQ_SOURCE); + } +#endif +} +#endif diff --git a/src/ppu_getppu.h b/src/ppu_getppu.h new file mode 100644 index 0000000..eb4eb62 --- /dev/null +++ b/src/ppu_getppu.h @@ -0,0 +1,407 @@ +static uint8 GetPPU_2102 (uint16 Address) +{ + return (uint8) (PPU.OAMAddr); +} + +static uint8 GetPPU_2103 (uint16 Address) +{ + return (((PPU.OAMAddr >> 8) & 1) | (PPU.OAMPriorityRotation << 7)); +} + +static uint8 GetPPU_RAM (uint16 Address) +{ + return (Memory.FillRAM[Address]); +} + +static uint8 GetPPU_2116 (uint16 Address) +{ + return (uint8) (PPU.VMA.Address); +} + +static uint8 GetPPU_2117 (uint16 Address) +{ + return (PPU.VMA.Address >> 8); +} + +static uint8 GetPPU_2121 (uint16 Address) +{ + return (PPU.CGADD); +} + +static uint8 GetPPU_213x (uint16 Address) +{ + if (PPU.Need16x8Mulitply) + { + int32 r = (int32) PPU.MatrixA * (int32) (PPU.MatrixB >> 8); + + Memory.FillRAM[0x2134] = (uint8) r; + Memory.FillRAM[0x2135] = (uint8) (r >> 8); + Memory.FillRAM[0x2136] = (uint8) (r >> 16); + PPU.Need16x8Mulitply = FALSE; + } + return (Memory.FillRAM[Address]); +} + +static uint8 GetPPU_2137 (uint16 Address) +{ +#ifdef DEBUGGER + missing.h_v_latch = 1; +#endif +#if 0 +#ifdef CPU_SHUTDOWN + CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif +#endif + PPU.HVBeamCounterLatched = 1; + PPU.VBeamPosLatched = (uint16) + CPU.V_Counter; + PPU.HBeamPosLatched = (uint16) ((CPU.Cycles * SNES_HCOUNTER_MAX) / Settings.H_Max); + + // Causes screen flicker for Yoshi's Island if uncommented + //CLEAR_IRQ_SOURCE (PPU_V_BEAM_IRQ_SOURCE | PPU_H_BEAM_IRQ_SOURCE); + + if (SNESGameFixes.NeedInit0x2137) + PPU.VBeamFlip = 0; //jyam sword world sfc2 & godzill + return (0); +} + +static uint8 GetPPU_2138 (uint16 Address) +{ + uint8 byte = 0; + + // Read OAM (sprite) control data + if(PPU.OAMAddr&0x100){ + if (!(PPU.OAMFlip&1)) + { + byte = PPU.OAMData [(PPU.OAMAddr&0x10f) << 1]; + } + else + { + byte = PPU.OAMData [((PPU.OAMAddr&0x10f) << 1) + 1]; + PPU.OAMAddr=(PPU.OAMAddr+1)&0x1ff; + } + } else { + if (!(PPU.OAMFlip&1)) + { + byte = PPU.OAMData [PPU.OAMAddr << 1]; + } + else + { + byte = PPU.OAMData [(PPU.OAMAddr << 1) + 1]; + ++PPU.OAMAddr; + } + } + PPU.OAMFlip ^= 1; + + return (byte); + +} + +static uint8 GetPPU_2139 (uint16 Address) +{ + uint8 byte = 0; + // Read vram low byte +#ifdef DEBUGGER + missing.vram_read = 1; +#endif + if (IPPU.FirstVRAMRead) + byte = Memory.VRAM[(PPU.VMA.Address << 1)&0xFFFF]; + else if (PPU.VMA.FullGraphicCount) + { + uint32 addr = PPU.VMA.Address - 1; + uint32 rem = addr & PPU.VMA.Mask1; + uint32 address = + (addr & ~PPU.VMA.Mask1) + + (rem >> PPU.VMA.Shift) + + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3); + byte = Memory.VRAM[((address << 1) - 2) & 0xFFFF]; + } + else + byte = Memory.VRAM[((PPU.VMA.Address << 1) - 2) & 0xffff]; + + if (!PPU.VMA.High) + { + PPU.VMA.Address += PPU.VMA.Increment; + IPPU.FirstVRAMRead = FALSE; + } + return byte; +} + +static uint8 GetPPU_213A (uint16 Address) +{ + uint8 byte = 0; + // Read vram high byte +#ifdef DEBUGGER + missing.vram_read = 1; +#endif + if (IPPU.FirstVRAMRead) + byte = Memory.VRAM[((PPU.VMA.Address << 1) + 1) & 0xffff]; + else if (PPU.VMA.FullGraphicCount) + { + uint32 addr = PPU.VMA.Address - 1; + uint32 rem = addr & PPU.VMA.Mask1; + uint32 address = + (addr & ~PPU.VMA.Mask1) + + (rem >> PPU.VMA.Shift) + + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3); + byte = Memory.VRAM[((address << 1) - 1) & 0xFFFF]; + } + else + byte = Memory.VRAM[((PPU.VMA.Address << 1) - 1) & 0xFFFF]; + if (PPU.VMA.High) + { + PPU.VMA.Address += PPU.VMA.Increment; + IPPU.FirstVRAMRead = FALSE; + } + return byte; +} + +static uint8 GetPPU_213B (uint16 Address) +{ + uint8 byte = 0; + // Read palette data +#ifdef DEBUGGER + missing.cgram_read = 1; +#endif + if (PPU.CGFLIPRead) + byte = PPU.CGDATA[PPU.CGADD++] >> 8; + else + byte = PPU.CGDATA[PPU.CGADD] & 0xff; + + PPU.CGFLIPRead ^= 1; + return (byte); +} + +static uint8 GetPPU_213C (uint16 Address) +{ + uint8 byte = 0; + // Horizontal counter value 0-339 +#ifdef DEBUGGER + missing.h_counter_read = 1; +#endif + if (PPU.HBeamFlip) + byte = PPU.HBeamPosLatched >> 8; + else + byte = (uint8) PPU.HBeamPosLatched; + PPU.HBeamFlip ^= 1; + return byte; +} + +static uint8 GetPPU_213D (uint16 Address) +{ + uint8 byte = 0; + // Vertical counter value 0-262 +#ifdef DEBUGGER + missing.v_counter_read = 1; +#endif + if (PPU.VBeamFlip) + byte = PPU.VBeamPosLatched >> 8; + else + byte = (uint8) PPU.VBeamPosLatched; + PPU.VBeamFlip ^= 1; + return byte; +} + +static uint8 GetPPU_213E (uint16 Address) +{ + // PPU time and range over flags + return (SNESGameFixes._0x213E_ReturnValue); +} + +static uint8 GetPPU_213F (uint16 Address) +{ + // NTSC/PAL and which field flags + PPU.VBeamFlip = PPU.HBeamFlip = 0; + return ((Settings.PAL ? 0x10 : 0) | (Memory.FillRAM[0x213f] & 0xc0)); +} + +static uint8 GetPPU_APUR (uint16 Address) +{ +/* + case 0x2140: case 0x2141: case 0x2142: case 0x2143: + case 0x2144: case 0x2145: case 0x2146: case 0x2147: + case 0x2148: case 0x2149: case 0x214a: case 0x214b: + case 0x214c: case 0x214d: case 0x214e: case 0x214f: + case 0x2150: case 0x2151: case 0x2152: case 0x2153: + case 0x2154: case 0x2155: case 0x2156: case 0x2157: + case 0x2158: case 0x2159: case 0x215a: case 0x215b: + case 0x215c: case 0x215d: case 0x215e: case 0x215f: + case 0x2160: case 0x2161: case 0x2162: case 0x2163: + case 0x2164: case 0x2165: case 0x2166: case 0x2167: + case 0x2168: case 0x2169: case 0x216a: case 0x216b: + case 0x216c: case 0x216d: case 0x216e: case 0x216f: + case 0x2170: case 0x2171: case 0x2172: case 0x2173: + case 0x2174: case 0x2175: case 0x2176: case 0x2177: + case 0x2178: case 0x2179: case 0x217a: case 0x217b: + case 0x217c: case 0x217d: case 0x217e: case 0x217f: +*/ +#ifdef SPCTOOL + return ((uint8) _SPCOutP[Address & 3]); +#else + // CPU.Flags |= DEBUG_MODE_FLAG; +#ifdef SPC700_SHUTDOWN + CPU.APU_APUExecuting = Settings.APUEnabled; + IAPU.WaitCounter++; +#endif + if(Settings.APUEnabled) + { +#ifdef CPU_SHUTDOWN + //CPU.WaitAddress = CPU.PCAtOpcodeStart; +#endif + if (!SNESGameFixes.APU_OutPorts_ReturnValueFix) return (APU.OutPorts[Address & 3]); // early exit + if(Address >= 0x2140 + && Address <= 0x2143 + && !CPU.V_Counter) + { + return (uint8) ((Address & 1) ? + ((rand() & 0xff00) >> 8) : (rand() & 0xff)); + } + return (APU.OutPorts[Address & 3]); + } +/* + switch (Settings.SoundSkipMethod) + { + case 3 : + case 0 : + case 1 : +*/ + #ifdef ASMCPU + CPU.rstatus |= (1<<(24-2)); + #endif + CPU.BranchSkip = TRUE; +/* + break; + case 2 : + break; + } +*/ + if ((Address & 3) < 2) + { + int r = rand(); + if (r & 2) + { + if (r & 4) + return ((Address & 3) == 1 ? 0xaa : 0xbb); + else + return ((r >> 3) & 0xff); + } + } + else + { + int r = rand(); + if (r & 2) + return ((r >> 3) & 0xff); + } + return (Memory.FillRAM[Address]); +#endif // SPCTOOL +} + +static uint8 GetPPU_2180 (uint16 Address) +{ + uint8 byte = 0; + // Read WRAM +#ifdef DEBUGGER + missing.wram_read = 1; +#endif + byte = Memory.RAM[PPU.WRAM++]; + PPU.WRAM &= 0x1FFFF; + return byte; +} + +static uint8 GetPPU_ZERO (uint16 Address) +{ + return 0; +} + +static uint8 GetPPU_ONE (uint16 Address) +{ + return 1; +} + +uint8 (*GetPPU[])(uint16 Address) = { + GetPPU_RAM, GetPPU_RAM, GetPPU_2102, GetPPU_2103, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, + GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, + GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_2116, GetPPU_2117, + GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, + GetPPU_RAM, GetPPU_2121, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, + GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, + GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_213x, GetPPU_213x, GetPPU_213x, GetPPU_2137, + GetPPU_2138, GetPPU_2139, GetPPU_213A, GetPPU_213B, GetPPU_213C, GetPPU_213D, GetPPU_213E, GetPPU_213F, + GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, + GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, + GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, + GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, + GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, + GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, + GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, + GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, GetPPU_APUR, + GetPPU_2180, GetPPU_RAM, GetPPU_RAM, GetPPU_RAM, GetPPU_ZERO, GetPPU_ZERO, GetPPU_ZERO, GetPPU_ZERO, + GetPPU_ZERO, GetPPU_ZERO, GetPPU_ZERO, GetPPU_ZERO, GetPPU_ZERO, GetPPU_ZERO, GetPPU_ZERO, GetPPU_ZERO, + GetPPU_ONE +}; + +uint8 S9xGetPPU (uint16 Address) +{ + uint8 byte = 0; + if(Address<0x2100)//not a real PPU reg + return 0; //treat as unmapped memory returning last byte on the bus + if (Address <= 0x2190){ + return GetPPU[Address - 0x2100](Address); + } else + { + #ifdef USE_SA1 + if (Settings.SA1) + return (S9xGetSA1(Address)); + #endif + if (Address <= 0x2fff || Address >= 0x3000 + 768) + { + switch (Address) + { + case 0x21c2 : + return (0x20); + case 0x21c3 : + return (0); + case 0x2800 : + // For Dai Kaijyu Monogatari II + if (Settings.SRTC) + return (S9xGetSRTC(Address)); + /*FALL*/ + + default : + #ifdef DEBUGGER + missing.unknownppu_read = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf(String, "Unknown register read: $%04X\n", Address); + S9xMessage(S9X_TRACE, S9X_PPU_TRACE, String); + } + #endif + // XXX: + return (0); //Memory.FillRAM[Address]); + } + } + + if (!Settings.SuperFX) + return (0x30); + byte = Memory.FillRAM[Address]; + + //if (Address != 0x3030 && Address != 0x3031) + //printf ("%04x\n", Address); + #ifdef CPU_SHUTDOWN + if (Address == 0x3030) + { + CPU.WaitAddress = CPU.PCAtOpcodeStart; + #ifdef ASMCPU + CPU.rstatus |= (1<<(24-3)); + #endif + } + else + #endif + if (Address == 0x3031) + { + CLEAR_IRQ_SOURCE(GSU_IRQ_SOURCE); + Memory.FillRAM[0x3031] = byte & 0x7f; + } + return (byte); + } +} diff --git a/src/ppu_setppu.h b/src/ppu_setppu.h new file mode 100644 index 0000000..160f209 --- /dev/null +++ b/src/ppu_setppu.h @@ -0,0 +1,1546 @@ +#include "rops.h" + +static void SetPPU_2100_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Brightness and screen blank bit + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2100, Brightness and screen blank bit Byte: %x\n", Byte); +#endif + if ((Memory.FillRAM[Address] & 0x0f) != (Byte & 0x0f)) ADD_ROP(ROP_BRIGHTNESS, Byte & 0xf); + if ((Memory.FillRAM[Address] & 0x80) != (Byte & 0x80)) ADD_ROP(ROP_FORCE_BLANKING, (Byte >> 7) & 1); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2100 (uint8 Byte, uint16 Address) +{ + // Brightness and screen blank bit + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2100, Brightness and screen blank bit Byte: %x\n", Byte); +#endif + + // Wiz & Gp2x, no Brightness handling + FLUSH_REDRAW(); + + if (PPU.Brightness != (Byte & 0xF)) + { + + IPPU.ColorsChanged = TRUE; + IPPU.DirectColourMapsNeedRebuild = TRUE; + PPU.Brightness = Byte & 0xF; + S9xFixColourBrightness(); + if (PPU.Brightness > IPPU.MaxBrightness) + IPPU.MaxBrightness = PPU.Brightness; + } + if ((Memory.FillRAM[Address] & 0x80) != (Byte & 0x80)) + { + + IPPU.ColorsChanged = TRUE; + PPU.ForcedBlanking = (Byte >> 7) & 1; + } + Memory.FillRAM[Address] = Byte; + } +} +#endif + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2101 (uint8 Byte, uint16 Address) +{ + // Sprite (OBJ) tile address + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2101, tile address. Byte: %x\n", Byte); +#endif + FLUSH_REDRAW(); + PPU.OBJNameBase = (Byte & 3) << 14; + PPU.OBJNameSelect = ((Byte >> 3) & 3) << 13; + PPU.OBJSizeSelect = (Byte >> 5) & 7; + IPPU.OBJChanged = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2101_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Sprite (OBJ) tile address + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2101, tile address. Byte: %x\n", Byte); +#endif + ADD_ROP(ROP_TILE_ADDRESS, Byte); + Memory.FillRAM[Address] = Byte; + } +} + + +static void SetPPU_2102 (uint8 Byte, uint16 Address) +{ + // Sprite write address (low) + PPU.OAMAddr = ((Memory.FillRAM[0x2103]&1)<<8) | Byte; + PPU.OAMFlip = 2; + PPU.OAMReadFlip = 0; + PPU.SavedOAMAddr2 = PPU.SavedOAMAddr; + PPU.SavedOAMAddr = PPU.OAMAddr; + if (PPU.OAMPriorityRotation && PPU.FirstSprite != (PPU.OAMAddr >> 1)) + { + PPU.FirstSprite = (PPU.OAMAddr&0xFE) >> 1; + IPPU.OBJChanged = TRUE; +#ifdef DEBUGGER + missing.sprite_priority_rotation = 1; +#endif + } + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2103 (uint8 Byte, uint16 Address) +{ + // Sprite register write address (high), sprite priority rotation + // bit. + PPU.OAMAddr &= 0x00FF; + PPU.OAMAddr |= (Byte & 1) << 8; + + if(SNESGameFixes.Flintstones) + { + PPU.OAMPriorityRotation=(Byte & 0x80)? 0 : 1; + } + else + { + PPU.OAMPriorityRotation=(Byte & 0x80)? 1 : 0; + } + if (PPU.OAMPriorityRotation && PPU.FirstSprite != (PPU.OAMAddr >> 1)) + { + PPU.FirstSprite = (PPU.OAMAddr&0xFE) >> 1; + IPPU.OBJChanged = TRUE; + } + PPU.OAMFlip = 0; + PPU.OAMReadFlip = 0; + PPU.SavedOAMAddr = PPU.OAMAddr; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2104 (uint8 Byte, uint16 Address) +{ + // Sprite register write + REGISTER_2104(Byte); + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2105_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Screen mode (0 - 7), background tile sizes and background 3 + // priority + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2105, Screen mode (0 - 7), background tile sizes and background 3 priority. Byte: %x\n", Byte); +#endif + ADD_ROP(ROP_SCREEN_MODE, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2105 (uint8 Byte, uint16 Address) +{ + // Screen mode (0 - 7), background tile sizes and background 3 + // priority + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2105, Screen mode (0 - 7), background tile sizes and background 3 priority. Byte: %x\n", Byte); +#endif + FLUSH_REDRAW(); + PPU.BG[0].BGSize = (Byte >> 4) & 1; + PPU.BG[1].BGSize = (Byte >> 5) & 1; + PPU.BG[2].BGSize = (Byte >> 6) & 1; + PPU.BG[3].BGSize = (Byte >> 7) & 1; + PPU.BGMode = Byte & 7; + // BJ: BG3Priority only takes effect if BGMode==1 and the bit is set + PPU.BG3Priority = ((Byte & 0x0f) == 0x09); + Memory.FillRAM[Address] = Byte; + } +} +#endif + + +static void SetPPU_2106_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Mosaic pixel size and enable + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2106, Mosaic pixel size and enable. Byte: %x\n", Byte); +#endif + ADD_ROP(ROP_MOSAIC, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2106 (uint8 Byte, uint16 Address) +{ + // Mosaic pixel size and enable + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2106, Mosaic pixel size and enable. Byte: %x\n", Byte); +#endif + FLUSH_REDRAW(); +#ifdef DEBUGGER + if ((Byte & 0xf0) && (Byte & 0x0f)) + missing.mosaic = 1; +#endif + PPU.Mosaic = (Byte >> 4) + 1; + PPU.BGMosaic[0] = (Byte & 1) && PPU.Mosaic > 1; + PPU.BGMosaic[1] = (Byte & 2) && PPU.Mosaic > 1; + PPU.BGMosaic[2] = (Byte & 4) && PPU.Mosaic > 1; + PPU.BGMosaic[3] = (Byte & 8) && PPU.Mosaic > 1; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2107_delayedRasterFx (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2107, BG 0, SCSize & SCBase . Byte : %x\n", Byte); +#endif + ADD_ROP(ROP_BG_SCSIZE_SCBASE, (0 << 16) | Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ + +static void SetPPU_2107 (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2107, BG 0, SCSize & SCBase . Byte : %x\n", Byte); +#endif + FLUSH_REDRAW(); + PPU.BG[0].SCSize = Byte & 3; + PPU.BG[0].SCBase = (Byte & 0x7c) << 8; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2108_delayedRasterFx (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2108, BG 1, SCSize & SCBase . Byte : %x\n", Byte); +#endif + ADD_ROP(ROP_BG_SCSIZE_SCBASE, (1 << 16) | Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2108 (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2108, BG 1, SCSize & SCBase . Byte : %x\n", Byte); +#endif + FLUSH_REDRAW(); + PPU.BG[1].SCSize = Byte & 3; + PPU.BG[1].SCBase = (Byte & 0x7c) << 8; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2109_delayedRasterFx (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2109, BG 2, SCSize & SCBase . Byte : %x\n", Byte); +#endif + ADD_ROP(ROP_BG_SCSIZE_SCBASE, (2 << 16) | Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2109 (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2109, BG 2, SCSize & SCBase . Byte : %x\n", Byte); +#endif + FLUSH_REDRAW(); + PPU.BG[2].SCSize = Byte & 3; + PPU.BG[2].SCBase = (Byte & 0x7c) << 8; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_210A_delayedRasterFx (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_210A, BG 3, SCSize & SCBase . Byte : %x\n", Byte); +#endif + ADD_ROP(ROP_BG_SCSIZE_SCBASE, (3 << 16) | Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_210A (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_210A, BG 3, SCSize & SCBase . Byte : %x\n", Byte); +#endif + FLUSH_REDRAW(); + PPU.BG[3].SCSize = Byte & 3; + PPU.BG[3].SCBase = (Byte & 0x7c) << 8; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_210B_delayedRasterFx (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_210B, BG 0 & 1, NameBase. Byte : %x\n", Byte); +#endif + ADD_ROP(ROP_BG_NAMEBASE, (0 << 16) | Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_210B (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_210B, BG 0 & 1, NameBase. Byte : %x\n", Byte); +#endif + FLUSH_REDRAW(); + PPU.BG[0].NameBase = (Byte & 7) << 12; + PPU.BG[1].NameBase = ((Byte >> 4) & 7) << 12; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_210C_delayedRasterFx (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_210C, BG 2 & 3, NameBase. Byte : %x\n", Byte); +#endif + ADD_ROP(ROP_BG_NAMEBASE, (2 << 16) | Byte); + Memory.FillRAM[Address] = Byte; + } +} + +static void SetPPU_210C (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_210C, BG 2 & 3, NameBase. Byte : %x\n", Byte); +#endif + FLUSH_REDRAW(); + PPU.BG[2].NameBase = (Byte & 7) << 12; + PPU.BG[3].NameBase = ((Byte >> 4) & 7) << 12; + Memory.FillRAM[Address] = Byte; + } +} + + +//This is the Theme Park fix - it appears all these registers +//share a previous byte value for setting them. + +static void SetPPU_210D (uint8 Byte, uint16 Address) +{ + PPU.BG[0].HOffset = (Byte<<8) | PPU.BGnxOFSbyte; + PPU.BG[0].OffsetsChanged = 1; + PPU.BGnxOFSbyte = Byte; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_210E (uint8 Byte, uint16 Address) +{ + PPU.BG[0].VOffset = (Byte<<8) | PPU.BGnxOFSbyte; + PPU.BG[0].OffsetsChanged = 1; + PPU.BGnxOFSbyte = Byte; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_210F (uint8 Byte, uint16 Address) +{ + PPU.BG[1].HOffset = (Byte<<8) | PPU.BGnxOFSbyte; + PPU.BG[1].OffsetsChanged = 1; + PPU.BGnxOFSbyte = Byte; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2110 (uint8 Byte, uint16 Address) +{ + PPU.BG[1].VOffset = (Byte<<8) | PPU.BGnxOFSbyte; + PPU.BG[1].OffsetsChanged = 1; + PPU.BGnxOFSbyte = Byte; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2111 (uint8 Byte, uint16 Address) +{ + PPU.BG[2].HOffset = (Byte<<8) | PPU.BGnxOFSbyte; + PPU.BG[2].OffsetsChanged = 1; + PPU.BGnxOFSbyte = Byte; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2112 (uint8 Byte, uint16 Address) +{ + PPU.BG[2].VOffset = (Byte<<8) | PPU.BGnxOFSbyte; + PPU.BG[2].OffsetsChanged = 1; + PPU.BGnxOFSbyte = Byte; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2113 (uint8 Byte, uint16 Address) +{ + PPU.BG[3].HOffset = (Byte<<8) | PPU.BGnxOFSbyte; + PPU.BG[3].OffsetsChanged = 1; + PPU.BGnxOFSbyte = Byte; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2114 (uint8 Byte, uint16 Address) +{ + PPU.BG[3].VOffset = (Byte<<8) | PPU.BGnxOFSbyte; + PPU.BG[3].OffsetsChanged = 1; + PPU.BGnxOFSbyte = Byte; + Memory.FillRAM[Address] = Byte; +} + +//end Theme Park + + +static void SetPPU_2115 (uint8 Byte, uint16 Address) +{ + // VRAM byte/word access flag and increment + PPU.VMA.High = (Byte & 0x80) == 0 ? FALSE : TRUE; + switch (Byte & 3) + { + case 0 : + PPU.VMA.Increment = 1; + break; + case 1 : + PPU.VMA.Increment = 32; + break; + case 2 : + PPU.VMA.Increment = 128; + break; + case 3 : + PPU.VMA.Increment = 128; + break; + } +#ifdef DEBUGGER + if ((Byte & 3) != 0) + missing.vram_inc = Byte & 3; +#endif + if (Byte & 0x0c) + { + static uint16 IncCount[4] = { 0, 32, 64, 128 }; + static uint16 Shift[4] = { 0, 5, 6, 7 }; +#ifdef DEBUGGER + missing.vram_full_graphic_inc = + (Byte & 0x0c) >> 2; +#endif + PPU.VMA.Increment = 1; + uint8 i = (Byte & 0x0c) >> 2; + PPU.VMA.FullGraphicCount = IncCount[i]; + PPU.VMA.Mask1 = IncCount[i] * 8 - 1; + PPU.VMA.Shift = Shift[i]; + } + else + PPU.VMA.FullGraphicCount = 0; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2116 (uint8 Byte, uint16 Address) +{ + // VRAM read/write address (low) + PPU.VMA.Address &= 0xFF00; + PPU.VMA.Address |= Byte; + IPPU.FirstVRAMRead = TRUE; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2117 (uint8 Byte, uint16 Address) +{ + // VRAM read/write address (high) + PPU.VMA.Address &= 0x00FF; + PPU.VMA.Address |= Byte << 8; + IPPU.FirstVRAMRead = TRUE; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2118 (uint8 Byte, uint16 Address) +{ + // VRAM write data (low) + IPPU.FirstVRAMRead = TRUE; + REGISTER_2118(Byte); + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2119 (uint8 Byte, uint16 Address) +{ + // VRAM write data (high) + IPPU.FirstVRAMRead = TRUE; + REGISTER_2119(Byte); + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_211A_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Mode 7 outside rotation area display mode and flipping + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_211A, Mode 7 outside rotation area display mode and flipping. Byte : %x\n", Byte); +#endif + ADD_ROP(ROP_MODE7_ROTATION, Byte); + + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_211A (uint8 Byte, uint16 Address) +{ + // Mode 7 outside rotation area display mode and flipping + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_211A, Mode 7 outside rotation area display mode and flipping. Byte : %x\n", Byte); +#endif + FLUSH_REDRAW(); + PPU.Mode7Repeat = Byte >> 6; + if (PPU.Mode7Repeat == 1) PPU.Mode7Repeat = 0; + PPU.Mode7VFlip = (Byte & 2) >> 1; + PPU.Mode7HFlip = Byte & 1; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_211B (uint8 Byte, uint16 Address) +{ + // Mode 7 matrix A (low & high) + PPU.MatrixA = ((PPU.MatrixA >> 8) & 0xff) | (Byte << 8); + PPU.Need16x8Mulitply = TRUE; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_211C (uint8 Byte, uint16 Address) +{ + // Mode 7 matrix B (low & high) + PPU.MatrixB = ((PPU.MatrixB >> 8) & 0xff) | (Byte << 8); + PPU.Need16x8Mulitply = TRUE; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_211D (uint8 Byte, uint16 Address) +{ + // Mode 7 matrix C (low & high) + PPU.MatrixC = ((PPU.MatrixC >> 8) & 0xff) | (Byte << 8); + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_211E (uint8 Byte, uint16 Address) +{ + // Mode 7 matrix D (low & high) + PPU.MatrixD = ((PPU.MatrixD >> 8) & 0xff) | (Byte << 8); + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_211F (uint8 Byte, uint16 Address) +{ + // Mode 7 centre of rotation X (low & high) + PPU.CentreX = ((PPU.CentreX >> 8) & 0xff) | (Byte << 8); + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2120 (uint8 Byte, uint16 Address) +{ + // Mode 7 centre of rotation Y (low & high) + PPU.CentreY = ((PPU.CentreY >> 8) & 0xff) | (Byte << 8); + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2121 (uint8 Byte, uint16 Address) +{ + // CG-RAM address + PPU.CGFLIP = 0; + PPU.CGFLIPRead = 0; + PPU.CGADD = Byte; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2122 (uint8 Byte, uint16 Address) +{ + REGISTER_2122(Byte); + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2123_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Window 1 and 2 enable for backgrounds 1 and 2 + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2123, Window 1 and 2 enable for backgrounds 1 and 2. Byte: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + ADD_ROP(ROP_BG_WINDOW_ENABLE, (0 << 16) | Byte); +#ifdef DEBUGGER + if (Byte & 0x80) + missing.window2[1] = 1; + if (Byte & 0x20) + missing.window1[1] = 1; + if (Byte & 0x08) + missing.window2[0] = 1; + if (Byte & 0x02) + missing.window1[0] = 1; +#endif + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2123 (uint8 Byte, uint16 Address) +{ + // Window 1 and 2 enable for backgrounds 1 and 2 + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2123, Window 1 and 2 enable for backgrounds 1 and 2. Byte: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + FLUSH_REDRAW(); + + PPU.ClipWindow1Enable[0] = !!(Byte & 0x02); + PPU.ClipWindow1Enable[1] = !!(Byte & 0x20); + PPU.ClipWindow2Enable[0] = !!(Byte & 0x08); + PPU.ClipWindow2Enable[1] = !!(Byte & 0x80); + PPU.ClipWindow1Inside[0] = !(Byte & 0x01); + PPU.ClipWindow1Inside[1] = !(Byte & 0x10); + PPU.ClipWindow2Inside[0] = !(Byte & 0x04); + PPU.ClipWindow2Inside[1] = !(Byte & 0x40); + PPU.RecomputeClipWindows = TRUE; +#ifdef DEBUGGER + if (Byte & 0x80) + missing.window2[1] = 1; + if (Byte & 0x20) + missing.window1[1] = 1; + if (Byte & 0x08) + missing.window2[0] = 1; + if (Byte & 0x02) + missing.window1[0] = 1; +#endif + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2124_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Window 1 and 2 enable for backgrounds 3 and 4 + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2124, Window 1 and 2 enable for backgrounds 3 and 4. Byte: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + ADD_ROP(ROP_BG_WINDOW_ENABLE, (2 << 16) | Byte); +#ifdef DEBUGGER + if (Byte & 0x80) + missing.window2[3] = 1; + if (Byte & 0x20) + missing.window1[3] = 1; + if (Byte & 0x08) + missing.window2[2] = 1; + if (Byte & 0x02) + missing.window1[2] = 1; +#endif + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2124 (uint8 Byte, uint16 Address) +{ + // Window 1 and 2 enable for backgrounds 3 and 4 + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2124, Window 1 and 2 enable for backgrounds 3 and 4. Byte: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + FLUSH_REDRAW(); + + PPU.ClipWindow1Enable[2] = !!(Byte & 0x02); + PPU.ClipWindow1Enable[3] = !!(Byte & 0x20); + PPU.ClipWindow2Enable[2] = !!(Byte & 0x08); + PPU.ClipWindow2Enable[3] = !!(Byte & 0x80); + PPU.ClipWindow1Inside[2] = !(Byte & 0x01); + PPU.ClipWindow1Inside[3] = !(Byte & 0x10); + PPU.ClipWindow2Inside[2] = !(Byte & 0x04); + PPU.ClipWindow2Inside[3] = !(Byte & 0x40); + PPU.RecomputeClipWindows = TRUE; +#ifdef DEBUGGER + if (Byte & 0x80) + missing.window2[3] = 1; + if (Byte & 0x20) + missing.window1[3] = 1; + if (Byte & 0x08) + missing.window2[2] = 1; + if (Byte & 0x02) + missing.window1[2] = 1; +#endif + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2125_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Window 1 and 2 enable for objects and colour window + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2125, Window 1 and 2 enable for objects and colour window. Byte: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + ADD_ROP(ROP_BG_WINDOW_ENABLE, (4 << 16) | Byte); +#ifdef DEBUGGER + if (Byte & 0x80) + missing.window2[5] = 1; + if (Byte & 0x20) + missing.window1[5] = 1; + if (Byte & 0x08) + missing.window2[4] = 1; + if (Byte & 0x02) + missing.window1[4] = 1; +#endif + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2125 (uint8 Byte, uint16 Address) +{ + // Window 1 and 2 enable for objects and colour window + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2125, Window 1 and 2 enable for objects and colour window. Byte: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + FLUSH_REDRAW(); + + PPU.ClipWindow1Enable[4] = !!(Byte & 0x02); + PPU.ClipWindow1Enable[5] = !!(Byte & 0x20); + PPU.ClipWindow2Enable[4] = !!(Byte & 0x08); + PPU.ClipWindow2Enable[5] = !!(Byte & 0x80); + PPU.ClipWindow1Inside[4] = !(Byte & 0x01); + PPU.ClipWindow1Inside[5] = !(Byte & 0x10); + PPU.ClipWindow2Inside[4] = !(Byte & 0x04); + PPU.ClipWindow2Inside[5] = !(Byte & 0x40); + PPU.RecomputeClipWindows = TRUE; +#ifdef DEBUGGER + if (Byte & 0x80) + missing.window2[5] = 1; + if (Byte & 0x20) + missing.window1[5] = 1; + if (Byte & 0x08) + missing.window2[4] = 1; + if (Byte & 0x02) + missing.window1[4] = 1; +#endif + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2126_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Window 1 left position + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2126, Window 1 left position. Byte: %x\n", Byte); +#endif + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + ADD_ROP(ROP_WINDOW1_LEFT, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2126 (uint8 Byte, uint16 Address) +{ + // Window 1 left position + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2126, Window 1 left position. Byte: %x\n", Byte); +#endif + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + FLUSH_REDRAW(); + + PPU.Window1Left = Byte; + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2127_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Window 1 right position + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2127, Window 1 right position. Byte: %x\n", Byte); +#endif + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + ADD_ROP(ROP_WINDOW1_RIGHT, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2127 (uint8 Byte, uint16 Address) +{ + // Window 1 right position + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2127, Window 1 right position. Byte: %x\n", Byte); +#endif + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + FLUSH_REDRAW(); + + PPU.Window1Right = Byte; + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2128_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Window 2 left position + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2128, Window 2 left position. Byte: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + ADD_ROP(ROP_WINDOW2_LEFT, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2128 (uint8 Byte, uint16 Address) +{ + // Window 2 left position + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2128, Window 2 left position. Byte: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + FLUSH_REDRAW(); + + PPU.Window2Left = Byte; + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2129_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Window 2 right position + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2129, Window 2 right position. Byte: %x\n", Byte); +#endif + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + ADD_ROP(ROP_WINDOW2_RIGHT, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2129 (uint8 Byte, uint16 Address) +{ + // Window 2 right position + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2129, Window 2 right position. Byte: %x\n", Byte); +#endif + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + FLUSH_REDRAW(); + + PPU.Window2Right = Byte; + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_212A_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Windows 1 & 2 overlap logic for backgrounds 1 - 4 + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212A, Window 1 and 2 overlap logic for backgrounds 1 - 4: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + ADD_ROP(ROP_BG_WINDOW_LOGIC, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_212A (uint8 Byte, uint16 Address) +{ + // Windows 1 & 2 overlap logic for backgrounds 1 - 4 + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212A, Window 1 and 2 overlap logic for backgrounds 1 - 4: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + FLUSH_REDRAW(); + + PPU.ClipWindowOverlapLogic[0] = (Byte & 0x03); + PPU.ClipWindowOverlapLogic[1] = (Byte & 0x0c) >> 2; + PPU.ClipWindowOverlapLogic[2] = (Byte & 0x30) >> 4; + PPU.ClipWindowOverlapLogic[3] = (Byte & 0xc0) >> 6; + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_212B_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Windows 1 & 2 overlap logic for objects and colour window + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212B, Window 1 and 2 overlap logic objects and colour window: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + ADD_ROP(ROP_OBJS_WINDOW_LOGIC, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_212B (uint8 Byte, uint16 Address) +{ + // Windows 1 & 2 overlap logic for objects and colour window + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212B, Window 1 and 2 overlap logic objects and colour window: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_WINDOW) return; + FLUSH_REDRAW(); + + PPU.ClipWindowOverlapLogic[4] = Byte & 0x03; + PPU.ClipWindowOverlapLogic[5] = (Byte & 0x0c) >> 2; + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_212C_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Main screen designation (backgrounds 1 - 4 and objects) + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212C, Main screen designation bg 1-4 and objs: %x\n", Byte); +#endif + ADD_ROP(ROP_MAIN_SCREEN_DESIG, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_212C (uint8 Byte, uint16 Address) +{ + // Main screen designation (backgrounds 1 - 4 and objects) + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212C, Main screen designation bg 1-4 and objs: %x\n", Byte); +#endif + + FLUSH_REDRAW(); + + PPU.RecomputeClipWindows = TRUE; + GFX.r212c_s = Byte; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_212D_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Sub-screen designation (backgrounds 1 - 4 and objects) + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212D, Sub-screen designation bg 1-4 and objs: %x\n", Byte); +#endif + + +#ifdef DEBUGGER + if (Byte & 0x1f) + missing.subscreen = 1; +#endif + ADD_ROP(ROP_SUB_SCREEN_DESIG, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_212D (uint8 Byte, uint16 Address) +{ + // Sub-screen designation (backgrounds 1 - 4 and objects) + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212D, Sub-screen designation bg 1-4 and objs: %x\n", Byte); +#endif + + +#ifdef DEBUGGER + if (Byte & 0x1f) + missing.subscreen = 1; +#endif + FLUSH_REDRAW(); + + PPU.RecomputeClipWindows = TRUE; + GFX.r212d_s = Byte; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_212E_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Window mask designation for main screen ? + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212E, Window mask designation for main screen ?: %x\n", Byte); +#endif + ADD_ROP(ROP_MAIN_SCREEN_WMASK, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_212E (uint8 Byte, uint16 Address) +{ + // Window mask designation for main screen ? + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212E, Window mask designation for main screen ?: %x\n", Byte); +#endif + FLUSH_REDRAW(); + + GFX.r212e_s = Byte; + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_212F_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Window mask designation for sub-screen ? + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212F, Window mask designation for sub-screen: %x\n", Byte); +#endif + ADD_ROP(ROP_SUB_SCREEN_WMASK, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_212F (uint8 Byte, uint16 Address) +{ + // Window mask designation for sub-screen ? + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_212F, Window mask designation for sub-screen: %x\n", Byte); +#endif + FLUSH_REDRAW(); + + GFX.r212f_s = Byte; + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2130_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Fixed colour addition or screen addition + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2130, Fixed colour addition or screen addition: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_ADDSUB) return; + +#ifdef DEBUGGER + if ((Byte & 1) && (PPU.BGMode == 3 || PPU.BGMode == 4 + || PPU.BGMode == 7)) + missing.direct = 1; +#endif + ADD_ROP(ROP_FIXEDCOL_OR_SCREEN, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2130 (uint8 Byte, uint16 Address) +{ + // Fixed colour addition or screen addition + if (Byte != Memory.FillRAM[Address]) + { +#ifdef __DEBUG__ + printf("SetPPU_2130, Fixed colour addition or screen addition: %x\n", Byte); +#endif + + if (Settings.os9x_hack&PPU_IGNORE_ADDSUB) return; + +#ifdef DEBUGGER + if ((Byte & 1) && (PPU.BGMode == 3 || PPU.BGMode == 4 + || PPU.BGMode == 7)) + missing.direct = 1; +#endif + FLUSH_REDRAW(); + + GFX.r2130_s = Byte; + PPU.RecomputeClipWindows = TRUE; + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2131_delayedRasterFx (uint8 Byte, uint16 Address) +{ + // Colour addition or subtraction select + if (Byte != Memory.FillRAM[Address]) + { + if (Settings.os9x_hack&PPU_IGNORE_ADDSUB) return; +#ifdef __DEBUG__ + printf("SetPPU_2131, Colour addition or subtraction select %x\n", Byte); +#endif + + + // Backgrounds 1 - 4, objects and backdrop colour add/sub enable +#ifdef DEBUGGER + if (Byte & 0x80) + { + // Subtract + if (Memory.FillRAM[0x2130] & 0x02) + missing.subscreen_sub = 1; + else + missing.fixed_colour_sub = 1; + } + else + { + // Addition + if (Memory.FillRAM[0x2130] & 0x02) + missing.subscreen_add = 1; + else + missing.fixed_colour_add = 1; + } +#endif + ADD_ROP(ROP_ADD_OR_SUB_COLOR, Byte); + Memory.FillRAM[0x2131] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2131 (uint8 Byte, uint16 Address) +{ + // Colour addition or subtraction select + if (Byte != Memory.FillRAM[Address]) + { + if (Settings.os9x_hack&PPU_IGNORE_ADDSUB) return; +#ifdef __DEBUG__ + printf("SetPPU_2131, Colour addition or subtraction select %x\n", Byte); +#endif + + + // Backgrounds 1 - 4, objects and backdrop colour add/sub enable +#ifdef DEBUGGER + if (Byte & 0x80) + { + // Subtract + if (Memory.FillRAM[0x2130] & 0x02) + missing.subscreen_sub = 1; + else + missing.fixed_colour_sub = 1; + } + else + { + // Addition + if (Memory.FillRAM[0x2130] & 0x02) + missing.subscreen_add = 1; + else + missing.fixed_colour_add = 1; + } +#endif + FLUSH_REDRAW(); + GFX.r2131_s = Byte; + Memory.FillRAM[0x2131] = Byte; + } +} +#endif + +static void SetPPU_2132_delayedRasterFx (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { + + if (!(Settings.os9x_hack & PPU_IGNORE_FIXEDCOLCHANGES)) ADD_ROP(ROP_FIXEDCOLOUR, Byte); + Memory.FillRAM[Address] = Byte; + } +} + +#ifdef __OLD_RASTER_FX__ +static void SetPPU_2132 (uint8 Byte, uint16 Address) +{ + if (Byte != Memory.FillRAM[Address]) + { + + int redraw_needed=0; + int new_fixedcol; + //FLUSH_REDRAW (); + + new_fixedcol=(Byte & 0x1f); + // Colour data for fixed colour addition/subtraction + if (Byte & 0x80) { + //PPU.FixedColourBlue = Byte & 0x1f; + if (new_fixedcol!=PPU.FixedColourBlue) {if (!(Settings.os9x_hack&PPU_IGNORE_FIXEDCOLCHANGES)) FLUSH_REDRAW();PPU.FixedColourBlue=new_fixedcol;} + } + if (Byte & 0x40) { + //PPU.FixedColourGreen = Byte & 0x1f; + if (new_fixedcol!=PPU.FixedColourGreen) {if (!(Settings.os9x_hack&PPU_IGNORE_FIXEDCOLCHANGES)) FLUSH_REDRAW();PPU.FixedColourGreen=new_fixedcol;} + } + if (Byte & 0x20) { + //PPU.FixedColourRed = Byte & 0x1f; + if (new_fixedcol!=PPU.FixedColourRed) {if (!(Settings.os9x_hack&PPU_IGNORE_FIXEDCOLCHANGES)) FLUSH_REDRAW();PPU.FixedColourRed=new_fixedcol;} + } + Memory.FillRAM[Address] = Byte; + } +} +#endif + +static void SetPPU_2133 (uint8 Byte, uint16 Address) +{ + // Screen settings + if (Byte != Memory.FillRAM[Address]) + { +#ifdef DEBUGGER + if (Byte & 0x40) + missing.mode7_bgmode = 1; + if (Byte & 0x08) + missing.pseudo_512 = 1; +#endif + if (Byte & 0x04) + { + PPU.ScreenHeight = SNES_HEIGHT_EXTENDED; +#ifdef DEBUGGER + missing.lines_239 = 1; +#endif + } + else + PPU.ScreenHeight = SNES_HEIGHT; +#ifdef DEBUGGER + if (Byte & 0x02) + missing.sprite_double_height = 1; + + if (Byte & 1) + missing.interlace = 1; +#endif + Memory.FillRAM[Address] = Byte; + } +} + +static void SetPPU_NOP (uint8 Byte, uint16 Address) +{ +} + +static void SetPPU_APU (uint8 Byte, uint16 Address) +{ +#ifdef SPCTOOL + _SPCInPB(Address & 3, Byte); +#else + // CPU.Flags |= DEBUG_MODE_FLAG; + Memory.FillRAM[Address] = Byte; + IAPU.RAM[(Address & 3) + 0xf4] = Byte; +#ifdef SPC700_SHUTDOWN + CPU.APU_APUExecuting = Settings.APUEnabled; + IAPU.WaitCounter++; +#endif +#endif // SPCTOOL +} + +static void SetPPU_2180 (uint8 Byte, uint16 Address) +{ + REGISTER_2180(Byte); + Memory.FillRAM[Address] = Byte; +} + + +static void SetPPU_2181 (uint8 Byte, uint16 Address) +{ + PPU.WRAM &= 0x1FF00; + PPU.WRAM |= Byte; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2182 (uint8 Byte, uint16 Address) +{ + PPU.WRAM &= 0x100FF; + PPU.WRAM |= Byte << 8; + Memory.FillRAM[Address] = Byte; +} + +static void SetPPU_2183 (uint8 Byte, uint16 Address) +{ + PPU.WRAM &= 0x0FFFF; + PPU.WRAM |= Byte << 16; + PPU.WRAM &= 0x1FFFF; + Memory.FillRAM[Address] = Byte; +} + +#ifdef __OLD_RASTER_FX__ +static void (*SetPPU[])(uint8 Byte, uint16 Address) = { + SetPPU_2100, SetPPU_2101, SetPPU_2102, SetPPU_2103, SetPPU_2104, SetPPU_2105, SetPPU_2106, SetPPU_2107, + SetPPU_2108, SetPPU_2109, SetPPU_210A, SetPPU_210B, SetPPU_210C, SetPPU_210D, SetPPU_210E, SetPPU_210F, + SetPPU_2110, SetPPU_2111, SetPPU_2112, SetPPU_2113, SetPPU_2114, SetPPU_2115, SetPPU_2116, SetPPU_2117, + SetPPU_2118, SetPPU_2119, SetPPU_211A, SetPPU_211B, SetPPU_211C, SetPPU_211D, SetPPU_211E, SetPPU_211F, + SetPPU_2120, SetPPU_2121, SetPPU_2122, SetPPU_2123, SetPPU_2124, SetPPU_2125, SetPPU_2126, SetPPU_2127, + SetPPU_2128, SetPPU_2129, SetPPU_212A, SetPPU_212B, SetPPU_212C, SetPPU_212D, SetPPU_212E, SetPPU_212F, + SetPPU_2130, SetPPU_2131, SetPPU_2132, SetPPU_2133, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, + SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_2180, SetPPU_2181, SetPPU_2182, SetPPU_2183 +}; +#endif + +static void (*SetPPU_delayedRasterFx[])(uint8 Byte, uint16 Address) = { + SetPPU_2100_delayedRasterFx, SetPPU_2101_delayedRasterFx, SetPPU_2102, SetPPU_2103, SetPPU_2104, SetPPU_2105_delayedRasterFx, SetPPU_2106_delayedRasterFx, SetPPU_2107_delayedRasterFx, + SetPPU_2108_delayedRasterFx, SetPPU_2109_delayedRasterFx, SetPPU_210A_delayedRasterFx, SetPPU_210B_delayedRasterFx, SetPPU_210C_delayedRasterFx, SetPPU_210D, SetPPU_210E, SetPPU_210F, + SetPPU_2110, SetPPU_2111, SetPPU_2112, SetPPU_2113, SetPPU_2114, SetPPU_2115, SetPPU_2116, SetPPU_2117, + SetPPU_2118, SetPPU_2119, SetPPU_211A_delayedRasterFx, SetPPU_211B, SetPPU_211C, SetPPU_211D, SetPPU_211E, SetPPU_211F, + SetPPU_2120, SetPPU_2121, SetPPU_2122, SetPPU_2123_delayedRasterFx, SetPPU_2124_delayedRasterFx, SetPPU_2125_delayedRasterFx, SetPPU_2126_delayedRasterFx, SetPPU_2127_delayedRasterFx, + SetPPU_2128_delayedRasterFx, SetPPU_2129_delayedRasterFx, SetPPU_212A_delayedRasterFx, SetPPU_212B_delayedRasterFx, SetPPU_212C_delayedRasterFx, SetPPU_212D_delayedRasterFx, SetPPU_212E_delayedRasterFx, SetPPU_212F_delayedRasterFx, + SetPPU_2130_delayedRasterFx, SetPPU_2131_delayedRasterFx, SetPPU_2132_delayedRasterFx, SetPPU_2133, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, + SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, SetPPU_NOP, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, SetPPU_APU, + SetPPU_2180, SetPPU_2181, SetPPU_2182, SetPPU_2183 +}; + +void S9xSetPPU (uint8 Byte, uint16 Address) +{ +// fprintf(stderr, "%03d: %02x to %04x\n", CPU.V_Counter, Byte, Address); + if ( Address < 0x2100 ) + { + Memory.FillRAM[Address] = Byte; + return; + } + + if (Address <= 0x2183) + { +#ifdef __OLD_RASTER_FX__ + + if (!snesMenuOptions.delayedRasterFX) SetPPU[Address - 0x2100]( Byte, Address ); + else +#endif + SetPPU_delayedRasterFx[Address - 0x2100]( Byte, Address ); + return; + } + else + { +#ifdef USE_SA1 + if (Settings.SA1) + { + if (Address >= 0x2200 && Address < 0x23ff) + S9xSetSA1(Byte, Address); + else + Memory.FillRAM[Address] = Byte; + return; + } + else +#endif + // Dai Kaijyu Monogatari II + if (Address == 0x2801 && Settings.SRTC) + S9xSetSRTC(Byte, Address); + else if (Address < 0x3000 || Address >= 0x3000 + 768) + { +#ifdef DEBUGGER + missing.unknownppu_write = Address; + if (Settings.TraceUnknownRegisters) + { + sprintf( + String, + "Unknown register write: $%02X->$%04X\n", + Byte, + Address); + S9xMessage(S9X_TRACE, S9X_PPU_TRACE, String); + } +#endif + } + else + { + if (!Settings.SuperFX) + return; + + switch (Address) + { + case 0x3030 : + if ((Memory.FillRAM[0x3030] ^ Byte) & FLG_G) + { + Memory.FillRAM[Address] = Byte; + // Go flag has been changed + if (Byte & FLG_G) + S9xSuperFXExec(); + else + FxFlushCache(); + } + else + Memory.FillRAM[Address] = Byte; + break; + + case 0x3031 : + Memory.FillRAM[Address] = Byte; + break; + case 0x3033 : + Memory.FillRAM[Address] = Byte; + break; + case 0x3034 : + Memory.FillRAM[Address] = Byte & 0x7f; + break; + case 0x3036 : + Memory.FillRAM[Address] = Byte & 0x7f; + break; + case 0x3037 : + Memory.FillRAM[Address] = Byte; + break; + case 0x3038 : + Memory.FillRAM[Address] = Byte; + break; + case 0x3039 : + Memory.FillRAM[Address] = Byte; + break; + case 0x303a : + Memory.FillRAM[Address] = Byte; + break; + case 0x303b : + break; + case 0x303f : + Memory.FillRAM[Address] = Byte; + break; + case 0x301f : + Memory.FillRAM[Address] = Byte; + Memory.FillRAM[0x3000 + GSU_SFR] |= FLG_G; + S9xSuperFXExec(); + return; + + default : + Memory.FillRAM[Address] = Byte; + if (Address >= 0x3100) + { + FxCacheWriteAccess(Address); + } + break; + } + return; + } + } + Memory.FillRAM[Address] = Byte; +} diff --git a/src/r.txt b/src/r.txt new file mode 100644 index 0000000..49eac71 --- /dev/null +++ b/src/r.txt @@ -0,0 +1,876 @@ +os9x_65c816_common.s: Assembler messages: +os9x_65c816_common.s:7: Error: no such instruction: `rstatus .req R4@format:0xff800000' +os9x_65c816_common.s:8: Error: no such instruction: `reg_d_bank .req R4@format:0x000000ll' +os9x_65c816_common.s:9: Error: no such instruction: `reg_a .req R5@format:0xhhll0000 or 0xll000000' +os9x_65c816_common.s:10: Error: no such instruction: `reg_d .req R6@format:0xhhll0000' +os9x_65c816_common.s:11: Error: no such instruction: `reg_p_bank .req R6@format:0x000000ll' +os9x_65c816_common.s:12: Error: no such instruction: `reg_x .req R7@format:0xhhll0000 or 0xll000000' +os9x_65c816_common.s:13: Error: no such instruction: `reg_s .req R8@format:0x0000hhll' +os9x_65c816_common.s:14: Error: no such instruction: `reg_y .req R9@format:0xhhll0000 or 0xll000000' +os9x_65c816_common.s:16: Error: no such instruction: `rpc .req R10@32bits address' +os9x_65c816_common.s:17: Error: no such instruction: `reg_cycles .req R11@32bits counter' +os9x_65c816_common.s:18: Error: no such instruction: `regpcbase .req R12@32bits address' +os9x_65c816_common.s:20: Error: no such instruction: `rscratch .req R0@format:0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD' +os9x_65c816_common.s:21: Error: no such instruction: `regopcode .req R0@format:0x000000ll' +os9x_65c816_common.s:22: Error: no such instruction: `rscratch2 .req R1@format:0xhhll for calculation and value' +os9x_65c816_common.s:23: Error: no such instruction: `rscratch3 .req R2@' +os9x_65c816_common.s:24: Error: no such instruction: `rscratch4 .req R3@??????' +os9x_65c816_common.s:26: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:27: Error: no such instruction: `rscratch9 .req R10@??????' +os9x_65c816_common.s:29: Error: no such instruction: `reg_cpu_var .req R14' +os9x_65c816_common.s:33: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:34: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:36: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:56: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:57: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:58: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:59: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:60: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:61: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:62: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:63: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:85: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:104: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:143: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:194: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:667: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:841: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:842: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:843: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:844: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_common.s:845: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:8: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:9: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:10: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:12: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:13: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:14: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:15: Error: too many memory references for `mov' +os9x_65c816_global.s:18: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:19: Error: no such instruction: `ldr r2,[reg_cpu_var,' +os9x_65c816_global.s:20: Error: no such instruction: `bic r1,r1,' +os9x_65c816_global.s:22: Error: no such instruction: `ldr regpcbase,[r2,r1,lsl' +os9x_65c816_global.s:23: Error: no such instruction: `bic r0,r0,' +os9x_65c816_global.s:25: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:26: Error: no such instruction: `blo SPCBSpecial' +os9x_65c816_global.s:30: Error: no such instruction: `ldr r2,[reg_cpu_var,' +os9x_65c816_global.s:31: Error: no such instruction: `ldr r1,[r2,r1,lsl' +os9x_65c816_global.s:32: Error: too many memory references for `add' +os9x_65c816_global.s:33: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:34: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:35: Error: no such instruction: `orr rstatus,rstatus,r1,lsl' +os9x_65c816_global.s:37: Error: no such instruction: `bx r3' +os9x_65c816_global.s:42: Error: no such instruction: `ldr pc,[pc,regpcbase,lsl' +os9x_65c816_global.s:43: Error: too many memory references for `mov' +os9x_65c816_global.s:76: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:77: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:79: Error: no such instruction: `ldr r1,vMemory' +os9x_65c816_global.s:80: Error: no such instruction: `ldr regpcbase,[r1,' +os9x_65c816_global.s:82: Error: too many memory references for `sub' +os9x_65c816_global.s:83: Error: too many memory references for `add' +os9x_65c816_global.s:85: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:86: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:87: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:88: Error: no such instruction: `orr rstatus,rstatus,r0,lsl' +os9x_65c816_global.s:90: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:91: Error: no such instruction: `bx r3' +os9x_65c816_global.s:92: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:95: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:96: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:98: Error: no such instruction: `ldr r1,vMemory' +os9x_65c816_global.s:99: Error: no such instruction: `ldr regpcbase,[r1,' +os9x_65c816_global.s:101: Error: too many memory references for `sub' +os9x_65c816_global.s:102: Error: too many memory references for `add' +os9x_65c816_global.s:104: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:105: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:106: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:107: Error: no such instruction: `orr rstatus,rstatus,r0,lsl' +os9x_65c816_global.s:109: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:110: Error: no such instruction: `bx r3' +os9x_65c816_global.s:111: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:114: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:115: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:117: Error: no such instruction: `ldr r1,vMemory' +os9x_65c816_global.s:118: Error: no such instruction: `ldr regpcbase,[r1,' +os9x_65c816_global.s:120: Error: too many memory references for `sub' +os9x_65c816_global.s:121: Error: too many memory references for `add' +os9x_65c816_global.s:123: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:124: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:125: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:126: Error: no such instruction: `orr rstatus,rstatus,r0,lsl' +os9x_65c816_global.s:128: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:129: Error: no such instruction: `bx r3' +os9x_65c816_global.s:130: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:133: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:134: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:136: Error: no such instruction: `ldr r1,vMemory' +os9x_65c816_global.s:137: Error: no such instruction: `ldr regpcbase,[r1,' +os9x_65c816_global.s:139: Error: too many memory references for `add' +os9x_65c816_global.s:141: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:142: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:143: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:144: Error: no such instruction: `orr rstatus,rstatus,r0,lsl' +os9x_65c816_global.s:146: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:147: Error: no such instruction: `bx r3' +os9x_65c816_global.s:148: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:151: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:152: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:154: Error: no such instruction: `ldr r1,vMemory' +os9x_65c816_global.s:155: Error: no such instruction: `ldr regpcbase,[r1,' +os9x_65c816_global.s:157: Error: too many memory references for `sub' +os9x_65c816_global.s:158: Error: too many memory references for `add' +os9x_65c816_global.s:160: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:161: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:162: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:163: Error: no such instruction: `orr rstatus,rstatus,r0,lsl' +os9x_65c816_global.s:165: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:166: Error: no such instruction: `bx r3' +os9x_65c816_global.s:167: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:170: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:171: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:172: Error: no such instruction: `ldr r1,vMemory' +os9x_65c816_global.s:173: Error: no such instruction: `ldr regpcbase,[r1,' +os9x_65c816_global.s:175: Error: too many memory references for `sub' +os9x_65c816_global.s:176: Error: too many memory references for `add' +os9x_65c816_global.s:178: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:179: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:180: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:181: Error: no such instruction: `orr rstatus,rstatus,r0,lsl' +os9x_65c816_global.s:183: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:184: Error: no such instruction: `bx r3' +os9x_65c816_global.s:185: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:188: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:189: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:190: Error: no such instruction: `ldr r1,vMemory' +os9x_65c816_global.s:191: Error: no such instruction: `ldr regpcbase,[r1,' +os9x_65c816_global.s:193: Error: too many memory references for `sub' +os9x_65c816_global.s:194: Error: too many memory references for `add' +os9x_65c816_global.s:196: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:197: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:198: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:199: Error: no such instruction: `orr rstatus,rstatus,r0,lsl' +os9x_65c816_global.s:201: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:202: Error: no such instruction: `bx r3' +os9x_65c816_global.s:203: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:206: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:208: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:209: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:210: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:211: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:212: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:213: Error: too many memory references for `mov' +os9x_65c816_global.s:214: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:215: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:216: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:217: Error: no such instruction: `bic R1,R1,' +os9x_65c816_global.s:218: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:219: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:220: Error: no such instruction: `ldr R2,[R2,R1,LSL' +os9x_65c816_global.s:221: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:222: Error: no such instruction: `blo GBSpecial@special' +os9x_65c816_global.s:223: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:224: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:225: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:226: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:227: Error: too many memory references for `mov' +os9x_65c816_global.s:228: Error: no such instruction: `ldr R3,[R3,R1,lsl' +os9x_65c816_global.s:229: Error: too many memory references for `add' +os9x_65c816_global.s:230: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:231: Error: too many memory references for `add' +os9x_65c816_global.s:232: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:233: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:234: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:235: Error: no such instruction: `ldrb R3,[R3,R1]' +os9x_65c816_global.s:236: Error: no such instruction: `ldrb R0,[R2]' +os9x_65c816_global.s:237: Warning: `R3' is not valid here (expected `(%esi)') +os9x_65c816_global.s:237: Warning: `R3' is not valid here (expected `(%edi)') +os9x_65c816_global.s:237: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:238: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:239: Error: no such instruction: `ldrne R1,[reg_cpu_var,' +os9x_65c816_global.s:240: Error: no such instruction: `orrne rstatus,rstatus,' +os9x_65c816_global.s:241: Error: no such instruction: `strne R1,[reg_cpu_var,' +os9x_65c816_global.s:244: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:247: Error: no such instruction: `ldr PC,[PC,R2,LSL' +os9x_65c816_global.s:248: Error: too many memory references for `mov' +os9x_65c816_global.s:265: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:266: Error: no such instruction: `ldrb R1,[reg_cpu_var,' +os9x_65c816_global.s:267: Warning: `R1' is not valid here (expected `(%esi)') +os9x_65c816_global.s:267: Warning: `R1' is not valid here (expected `(%edi)') +os9x_65c816_global.s:267: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:268: Error: no such instruction: `addeq reg_cycles,reg_cycles,' +os9x_65c816_global.s:269: Error: too many memory references for `mov' +os9x_65c816_global.s:270: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:271: Error: too many memory references for `mov' +os9x_65c816_global.s:273: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:274: Error: no such instruction: `stmfd R13!,{R12,R14}' +os9x_65c816_global.s:275: Error: no such instruction: `bl S9xGetPPU' +os9x_65c816_global.s:276: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:277: Error: no such instruction: `ldr rstatus,[reg_cpu_var,' +os9x_65c816_global.s:279: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:280: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:282: Error: too many memory references for `add' +os9x_65c816_global.s:283: Error: too many memory references for `mov' +os9x_65c816_global.s:284: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:285: Error: too many memory references for `mov' +os9x_65c816_global.s:286: Error: no such instruction: `stmfd R13!,{R12,R14}' +os9x_65c816_global.s:287: Error: no such instruction: `bl S9xGetCPU' +os9x_65c816_global.s:288: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:289: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:290: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:293: Error: too many memory references for `add' +os9x_65c816_global.s:294: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:295: Error: no such instruction: `bic r0,r0,' +os9x_65c816_global.s:296: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:297: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:299: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:300: Error: no such instruction: `stmfd R13!,{R12,R14}' +os9x_65c816_global.s:301: Error: no such instruction: `blx reg_cycles' +os9x_65c816_global.s:302: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:303: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:304: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:305: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:307: Error: too many memory references for `add' +os9x_65c816_global.s:308: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:309: Error: no such instruction: `ldr R1,[reg_cpu_var,' +os9x_65c816_global.s:310: Error: too many memory references for `and' +os9x_65c816_global.s:311: Error: no such instruction: `ldrb R0,[R1,R0]@*Memory.SRAM+Address&SRAMMask' +os9x_65c816_global.s:312: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:315: Error: too many memory references for `add' +os9x_65c816_global.s:317: Error: too many memory references for `mov' +os9x_65c816_global.s:318: Error: too many memory references for `and' +os9x_65c816_global.s:319: Error: too many memory references for `mov' +os9x_65c816_global.s:320: Error: too many memory references for `mov' +os9x_65c816_global.s:321: Error: too many memory references for `add' +os9x_65c816_global.s:322: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:323: Error: too many memory references for `sub' +os9x_65c816_global.s:324: Error: no such instruction: `ldr R1,[reg_cpu_var,' +os9x_65c816_global.s:325: Error: too many memory references for `and' +os9x_65c816_global.s:326: Error: no such instruction: `ldrb R0,[R1,R0]@*Memory.SRAM+Address&SRAMMask' +os9x_65c816_global.s:327: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:331: Error: too many memory references for `mov' +os9x_65c816_global.s:332: Error: too many memory references for `add' +os9x_65c816_global.s:333: Error: too many memory references for `and' +os9x_65c816_global.s:334: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:335: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:340: Error: too many memory references for `add' +os9x_65c816_global.s:341: Error: too many memory references for `mov' +os9x_65c816_global.s:342: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:343: Error: too many memory references for `mov' +os9x_65c816_global.s:344: Error: no such instruction: `stmfd R13!,{R12,R14}' +os9x_65c816_global.s:345: Error: no such instruction: `bl S9xGetC4' +os9x_65c816_global.s:346: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:347: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:348: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:351: Error: too many memory references for `mov' +os9x_65c816_global.s:352: Error: too many memory references for `add' +os9x_65c816_global.s:353: Error: too many memory references for `mov' +os9x_65c816_global.s:354: Error: no such instruction: `ldr R1,[reg_cpu_var,' +os9x_65c816_global.s:355: Error: too many memory references for `sub' +os9x_65c816_global.s:356: Error: no such instruction: `ldrb R0,[R0,R1]@*Memory.BWRAM+((Address&0x7fff)- 0x6000)' +os9x_65c816_global.s:357: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:360: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:362: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:363: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:364: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:365: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:368: Error: too many memory references for `mov' +os9x_65c816_global.s:369: Error: too many memory references for `add' +os9x_65c816_global.s:370: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:371: Error: no such instruction: `bne GW_NotBoundary' +os9x_65c816_global.s:373: Error: no such instruction: `stmfd R13!,{R0}' +os9x_65c816_global.s:374: Error: no such instruction: `stmfd R13!,{PC}' +os9x_65c816_global.s:375: Error: no such instruction: `b asmS9xGetByte' +os9x_65c816_global.s:376: Error: too many memory references for `mov' +os9x_65c816_global.s:377: Error: no such instruction: `ldmfd R13!,{R1}' +os9x_65c816_global.s:378: Error: no such instruction: `stmfd R13!,{R0}' +os9x_65c816_global.s:379: Error: too many memory references for `add' +os9x_65c816_global.s:380: Error: no such instruction: `stmfd R13!,{PC}' +os9x_65c816_global.s:381: Error: no such instruction: `b asmS9xGetByte' +os9x_65c816_global.s:382: Error: too many memory references for `mov' +os9x_65c816_global.s:383: Error: no such instruction: `ldmfd R13!,{R1}' +os9x_65c816_global.s:384: Error: no such instruction: `orr R0,R1,R0,LSL' +os9x_65c816_global.s:385: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:389: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:390: Error: too many memory references for `mov' +os9x_65c816_global.s:391: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:392: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:393: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:394: Error: no such instruction: `bic R1,R1,' +os9x_65c816_global.s:395: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:396: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:397: Error: no such instruction: `ldr R2,[R2,R1,LSL' +os9x_65c816_global.s:398: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:399: Error: no such instruction: `blo GWSpecial@special' +os9x_65c816_global.s:400: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:402: Error: no such instruction: `tst R0,' +os9x_65c816_global.s:403: Error: no such instruction: `bne GW_Not_Aligned1' +os9x_65c816_global.s:404: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:405: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:406: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:407: Error: too many memory references for `mov' +os9x_65c816_global.s:408: Error: no such instruction: `ldr R3,[R3,R1,lsl' +os9x_65c816_global.s:409: Error: too many memory references for `mov' +os9x_65c816_global.s:410: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:411: Error: too many memory references for `add' +os9x_65c816_global.s:412: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:413: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:414: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:415: Error: no such instruction: `ldrh R0,[R2,R0]' +os9x_65c816_global.s:416: Error: no such instruction: `ldrb R3,[R3,R1]' +os9x_65c816_global.s:417: Warning: `R3' is not valid here (expected `(%esi)') +os9x_65c816_global.s:417: Warning: `R3' is not valid here (expected `(%edi)') +os9x_65c816_global.s:417: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:418: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:419: Error: no such instruction: `ldrne R1,[reg_cpu_var,' +os9x_65c816_global.s:420: Error: no such instruction: `orrne rstatus,rstatus,' +os9x_65c816_global.s:421: Error: no such instruction: `strne R1,[reg_cpu_var,' +os9x_65c816_global.s:423: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:426: Error: too many memory references for `mov' +os9x_65c816_global.s:427: Error: too many memory references for `add' +os9x_65c816_global.s:428: Error: no such instruction: `ldrb R3,[R2,R3,LSR' +os9x_65c816_global.s:429: Error: no such instruction: `ldrb R0,[R2,R0,LSR' +os9x_65c816_global.s:430: Error: no such instruction: `orr R0,R0,R3,LSL' +os9x_65c816_global.s:432: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:433: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:434: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:435: Error: no such instruction: `ldrb R3,[R3,R1]@R3=BlockIsRAM[block]' +os9x_65c816_global.s:436: Error: no such instruction: `ldr R2,[R2,R1,lsl' +os9x_65c816_global.s:437: Warning: `R3' is not valid here (expected `(%esi)') +os9x_65c816_global.s:437: Error: invalid character '?' in operand 2 +os9x_65c816_global.s:438: Error: no such instruction: `ldrne R1,[reg_cpu_var,' +os9x_65c816_global.s:439: Error: no such instruction: `orrne rstatus,rstatus,' +os9x_65c816_global.s:440: Error: no such instruction: `strne R1,[reg_cpu_var,' +os9x_65c816_global.s:441: Error: too many memory references for `add' +os9x_65c816_global.s:442: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:444: Error: no such instruction: `ldr PC,[PC,R2,LSL' +os9x_65c816_global.s:445: Error: too many memory references for `mov' +os9x_65c816_global.s:466: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:467: Error: no such instruction: `ldrb R1,[reg_cpu_var,' +os9x_65c816_global.s:468: Warning: `R1' is not valid here (expected `(%esi)') +os9x_65c816_global.s:468: Warning: `R1' is not valid here (expected `(%edi)') +os9x_65c816_global.s:468: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:469: Error: no such instruction: `addeq reg_cycles,reg_cycles,' +os9x_65c816_global.s:470: Error: too many memory references for `mov' +os9x_65c816_global.s:471: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:472: Error: too many memory references for `mov' +os9x_65c816_global.s:474: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:475: Error: no such instruction: `stmfd R13!,{R0,R12,R14}' +os9x_65c816_global.s:476: Error: no such instruction: `bl S9xGetPPU' +os9x_65c816_global.s:477: Error: no such instruction: `ldmfd R13!,{R1}' +os9x_65c816_global.s:478: Error: no such instruction: `stmfd R13!,{R0}' +os9x_65c816_global.s:479: Error: too many memory references for `add' +os9x_65c816_global.s:480: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:481: Error: no such instruction: `bl S9xGetPPU' +os9x_65c816_global.s:482: Error: no such instruction: `ldmfd R13!,{R1,R12,R14}' +os9x_65c816_global.s:483: Error: no such instruction: `ldr rstatus,[reg_cpu_var,' +os9x_65c816_global.s:485: Error: no such instruction: `orr R0,R1,R0,LSL' +os9x_65c816_global.s:486: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:487: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:489: Error: too many memory references for `add' +os9x_65c816_global.s:490: Error: too many memory references for `mov' +os9x_65c816_global.s:491: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:492: Error: too many memory references for `mov' +os9x_65c816_global.s:493: Error: no such instruction: `stmfd R13!,{R0,R12,R14}' +os9x_65c816_global.s:494: Error: no such instruction: `bl S9xGetCPU' +os9x_65c816_global.s:495: Error: no such instruction: `ldmfd R13!,{R1}' +os9x_65c816_global.s:496: Error: no such instruction: `stmfd R13!,{R0}' +os9x_65c816_global.s:497: Error: too many memory references for `add' +os9x_65c816_global.s:498: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:499: Error: no such instruction: `bl S9xGetCPU' +os9x_65c816_global.s:500: Error: no such instruction: `ldmfd R13!,{R1,R12,R14}' +os9x_65c816_global.s:501: Error: no such instruction: `orr R0,R1,R0,LSL' +os9x_65c816_global.s:502: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:503: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:505: Error: too many memory references for `add' +os9x_65c816_global.s:507: Error: no such instruction: `bic r0,r0,' +os9x_65c816_global.s:508: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:511: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:512: Error: no such instruction: `stmfd R13!,{R0,R12,R14}' +os9x_65c816_global.s:513: Error: no such instruction: `blx reg_cycles' +os9x_65c816_global.s:514: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:515: Error: no such instruction: `ldmfd R13!,{R1}' +os9x_65c816_global.s:516: Error: no such instruction: `stmfd R13!,{R0}' +os9x_65c816_global.s:517: Error: too many memory references for `add' +os9x_65c816_global.s:518: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:519: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:520: Error: no such instruction: `blx reg_cycles' +os9x_65c816_global.s:521: Error: no such instruction: `ldmfd R13!,{R1,R12,R14}' +os9x_65c816_global.s:522: Error: no such instruction: `orr R0,R1,R0,LSL' +os9x_65c816_global.s:523: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:524: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:526: Error: too many memory references for `add' +os9x_65c816_global.s:528: Error: no such instruction: `tst R0,' +os9x_65c816_global.s:529: Error: no such instruction: `bne GW_Not_Aligned2' +os9x_65c816_global.s:530: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:531: Error: no such instruction: `ldr R1,[reg_cpu_var,' +os9x_65c816_global.s:532: Error: too many memory references for `and' +os9x_65c816_global.s:533: Error: no such instruction: `ldrh R0,[R3,R1]@*Memory.SRAM+Address&SRAMMask' +os9x_65c816_global.s:534: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:536: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:537: Error: no such instruction: `ldr R1,[reg_cpu_var,' +os9x_65c816_global.s:538: Error: too many memory references for `and' +os9x_65c816_global.s:539: Error: too many memory references for `add' +os9x_65c816_global.s:540: Error: too many memory references for `and' +os9x_65c816_global.s:541: Error: no such instruction: `ldrb R3,[R1,R3]@*Memory.SRAM+Address&SRAMMask' +os9x_65c816_global.s:542: Error: no such instruction: `ldrb R2,[R1,R2]@*Memory.SRAM+Address&SRAMMask' +os9x_65c816_global.s:543: Error: no such instruction: `orr R0,R3,R2,LSL' +os9x_65c816_global.s:544: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:547: Error: too many memory references for `add' +os9x_65c816_global.s:549: Error: no such instruction: `tst R0,' +os9x_65c816_global.s:550: Error: no such instruction: `bne GW_Not_Aligned3' +os9x_65c816_global.s:552: Error: too many memory references for `mov' +os9x_65c816_global.s:553: Error: too many memory references for `and' +os9x_65c816_global.s:554: Error: too many memory references for `mov' +os9x_65c816_global.s:555: Error: too many memory references for `mov' +os9x_65c816_global.s:556: Error: too many memory references for `add' +os9x_65c816_global.s:557: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:558: Error: too many memory references for `sub' +os9x_65c816_global.s:560: Error: no such instruction: `ldr R1,[reg_cpu_var,' +os9x_65c816_global.s:561: Error: too many memory references for `and' +os9x_65c816_global.s:562: Error: no such instruction: `ldrh R0,[R1,R0]@*Memory.SRAM+Address&SRAMMask' +os9x_65c816_global.s:563: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:566: Error: too many memory references for `mov' +os9x_65c816_global.s:567: Error: too many memory references for `and' +os9x_65c816_global.s:568: Error: too many memory references for `mov' +os9x_65c816_global.s:569: Error: too many memory references for `mov' +os9x_65c816_global.s:570: Error: too many memory references for `add' +os9x_65c816_global.s:571: Error: too many memory references for `add' +os9x_65c816_global.s:572: Error: too many memory references for `sub' +os9x_65c816_global.s:573: Error: too many memory references for `mov' +os9x_65c816_global.s:574: Error: too many memory references for `and' +os9x_65c816_global.s:575: Error: too many memory references for `mov' +os9x_65c816_global.s:576: Error: too many memory references for `mov' +os9x_65c816_global.s:577: Error: too many memory references for `add' +os9x_65c816_global.s:578: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:579: Error: too many memory references for `sub' +os9x_65c816_global.s:580: Error: too many memory references for `and' +os9x_65c816_global.s:581: Error: too many memory references for `and' +os9x_65c816_global.s:583: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:584: Error: no such instruction: `ldrb R0,[R0,R3]@*Memory.SRAM+(Address...)&SRAMMask' +os9x_65c816_global.s:585: Error: no such instruction: `ldrb R2,[R2,R3]@*Memory.SRAM+(Address+1...)&SRAMMask' +os9x_65c816_global.s:586: Error: no such instruction: `orr R0,R2,R0,LSL' +os9x_65c816_global.s:588: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:592: Error: too many memory references for `mov' +os9x_65c816_global.s:593: Error: too many memory references for `add' +os9x_65c816_global.s:594: Error: too many memory references for `mov' +os9x_65c816_global.s:595: Error: no such instruction: `orr R0,R0,R0,LSL' +os9x_65c816_global.s:596: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:598: Error: too many memory references for `add' +os9x_65c816_global.s:599: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:600: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:602: Error: too many memory references for `add' +os9x_65c816_global.s:603: Error: too many memory references for `mov' +os9x_65c816_global.s:604: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:605: Error: too many memory references for `mov' +os9x_65c816_global.s:606: Error: no such instruction: `stmfd R13!,{R0,R12,R14}' +os9x_65c816_global.s:607: Error: no such instruction: `bl S9xGetC4' +os9x_65c816_global.s:608: Error: no such instruction: `ldmfd R13!,{R1}' +os9x_65c816_global.s:609: Error: no such instruction: `stmfd R13!,{R0}' +os9x_65c816_global.s:610: Error: too many memory references for `add' +os9x_65c816_global.s:611: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:612: Error: no such instruction: `bl S9xGetC4' +os9x_65c816_global.s:613: Error: no such instruction: `ldmfd R13!,{R1,R12,R14}' +os9x_65c816_global.s:614: Error: no such instruction: `orr R0,R1,R0,LSL' +os9x_65c816_global.s:615: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:616: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:618: Error: no such instruction: `tst R0,' +os9x_65c816_global.s:619: Error: no such instruction: `bne GW_Not_Aligned4' +os9x_65c816_global.s:620: Error: too many memory references for `mov' +os9x_65c816_global.s:621: Error: too many memory references for `add' +os9x_65c816_global.s:622: Error: too many memory references for `mov' +os9x_65c816_global.s:623: Error: no such instruction: `ldr R1,[reg_cpu_var,' +os9x_65c816_global.s:624: Error: too many memory references for `sub' +os9x_65c816_global.s:625: Error: no such instruction: `ldrh R0,[R1,R0]@*Memory.BWRAM+((Address&0x7fff)- 0x6000)' +os9x_65c816_global.s:626: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:628: Error: too many memory references for `mov' +os9x_65c816_global.s:629: Error: too many memory references for `add' +os9x_65c816_global.s:630: Error: too many memory references for `add' +os9x_65c816_global.s:631: Error: too many memory references for `mov' +os9x_65c816_global.s:632: Error: too many memory references for `mov' +os9x_65c816_global.s:633: Error: no such instruction: `ldr R1,[reg_cpu_var,' +os9x_65c816_global.s:634: Error: too many memory references for `sub' +os9x_65c816_global.s:635: Error: too many memory references for `sub' +os9x_65c816_global.s:636: Error: no such instruction: `ldrb R0,[R1,R0]@*Memory.BWRAM+((Address&0x7fff)- 0x6000)' +os9x_65c816_global.s:637: Error: no such instruction: `ldrb R3,[R1,R3]@*Memory.BWRAM+(((Address+1)&0x7fff)- 0x6000)' +os9x_65c816_global.s:638: Error: no such instruction: `orr R0,R0,R3,LSL' +os9x_65c816_global.s:639: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:644: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:646: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:647: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:648: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:649: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:650: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:651: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:652: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:654: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:656: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:657: Error: too many memory references for `mov' +os9x_65c816_global.s:658: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:659: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:660: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:661: Error: no such instruction: `bic R3,R3,' +os9x_65c816_global.s:662: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:663: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:664: Error: no such instruction: `ldr R2,[R2,R3,LSL' +os9x_65c816_global.s:665: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:666: Error: no such instruction: `blo SBSpecial@special' +os9x_65c816_global.s:667: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:669: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:670: Error: too many memory references for `mov' +os9x_65c816_global.s:671: Error: too many memory references for `add' +os9x_65c816_global.s:672: Error: no such instruction: `ldr R0,[reg_cpu_var,' +os9x_65c816_global.s:673: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:674: Error: invalid char '[' beginning operand 2 `[R2]' +os9x_65c816_global.s:675: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:676: Error: no such instruction: `ldr R0,[R0,R3,lsl' +os9x_65c816_global.s:677: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:678: Error: too many memory references for `add' +os9x_65c816_global.s:679: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:680: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:681: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:682: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:684: Error: no such instruction: `ldr PC,[PC,R2,LSL' +os9x_65c816_global.s:685: Error: too many memory references for `mov' +os9x_65c816_global.s:702: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:703: Error: no such instruction: `ldrb R2,[reg_cpu_var,' +os9x_65c816_global.s:704: Warning: `R2' is not valid here (expected `(%esi)') +os9x_65c816_global.s:704: Warning: `R2' is not valid here (expected `(%edi)') +os9x_65c816_global.s:704: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:705: Error: no such instruction: `addeq reg_cycles,reg_cycles,' +os9x_65c816_global.s:706: Error: too many memory references for `mov' +os9x_65c816_global.s:707: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:708: Error: too many memory references for `mov' +os9x_65c816_global.s:709: Error: no such instruction: `stmfd R13!,{R12,R14}' +os9x_65c816_global.s:710: Error: too many memory references for `mov' +os9x_65c816_global.s:711: Error: too many memory references for `mov' +os9x_65c816_global.s:712: Error: too many memory references for `mov' +os9x_65c816_global.s:713: Error: no such instruction: `bl S9xSetPPU' +os9x_65c816_global.s:714: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:715: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:716: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:718: Error: too many memory references for `add' +os9x_65c816_global.s:719: Error: too many memory references for `mov' +os9x_65c816_global.s:720: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:721: Error: too many memory references for `mov' +os9x_65c816_global.s:722: Error: no such instruction: `stmfd R13!,{R12,R14}' +os9x_65c816_global.s:723: Error: too many memory references for `mov' +os9x_65c816_global.s:724: Error: too many memory references for `mov' +os9x_65c816_global.s:725: Error: too many memory references for `mov' +os9x_65c816_global.s:726: Error: no such instruction: `bl S9xSetCPU' +os9x_65c816_global.s:727: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:728: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:729: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:731: Error: too many memory references for `add' +os9x_65c816_global.s:732: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:733: Error: no such instruction: `bic r0,r0,' +os9x_65c816_global.s:734: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:735: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:736: Error: no such instruction: `stmfd R13!,{R12,R14}' +os9x_65c816_global.s:737: Error: too many memory references for `mov' +os9x_65c816_global.s:738: Error: too many memory references for `mov' +os9x_65c816_global.s:739: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:740: Error: too many memory references for `mov' +os9x_65c816_global.s:741: Error: no such instruction: `blx reg_cycles' +os9x_65c816_global.s:742: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:743: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:744: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:745: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:747: Error: too many memory references for `add' +os9x_65c816_global.s:748: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:749: Warning: `R2' is not valid here (expected `(%esi)') +os9x_65c816_global.s:749: Warning: `R2' is not valid here (expected `(%edi)') +os9x_65c816_global.s:749: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:750: Error: no such instruction: `ldmeqfd R13!,{PC}@return if SRAMMask=0' +os9x_65c816_global.s:751: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:752: Error: too many memory references for `and' +os9x_65c816_global.s:753: Error: invalid char '[' beginning operand 2 `[R0' +os9x_65c816_global.s:755: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:756: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:757: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:760: Error: too many memory references for `add' +os9x_65c816_global.s:762: Error: too many memory references for `mov' +os9x_65c816_global.s:763: Error: too many memory references for `and' +os9x_65c816_global.s:764: Error: too many memory references for `mov' +os9x_65c816_global.s:765: Error: too many memory references for `mov' +os9x_65c816_global.s:766: Error: too many memory references for `add' +os9x_65c816_global.s:768: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:769: Warning: `R2' is not valid here (expected `(%esi)') +os9x_65c816_global.s:769: Warning: `R2' is not valid here (expected `(%edi)') +os9x_65c816_global.s:769: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:770: Error: no such instruction: `ldmeqfd R13!,{PC}@return if SRAMMask=0' +os9x_65c816_global.s:772: Error: too many memory references for `sub' +os9x_65c816_global.s:773: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:774: Error: too many memory references for `and' +os9x_65c816_global.s:775: Error: invalid char '[' beginning operand 2 `[R0' +os9x_65c816_global.s:777: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:778: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:779: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:784: Error: too many memory references for `add' +os9x_65c816_global.s:785: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:787: Error: too many memory references for `add' +os9x_65c816_global.s:788: Error: too many memory references for `mov' +os9x_65c816_global.s:789: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:790: Error: too many memory references for `mov' +os9x_65c816_global.s:791: Error: no such instruction: `stmfd R13!,{R12,R14}' +os9x_65c816_global.s:792: Error: too many memory references for `mov' +os9x_65c816_global.s:793: Error: too many memory references for `mov' +os9x_65c816_global.s:794: Error: too many memory references for `mov' +os9x_65c816_global.s:795: Error: no such instruction: `bl S9xSetC4' +os9x_65c816_global.s:796: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:797: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:798: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:800: Error: too many memory references for `mov' +os9x_65c816_global.s:801: Error: too many memory references for `add' +os9x_65c816_global.s:802: Error: too many memory references for `mov' +os9x_65c816_global.s:803: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:804: Error: too many memory references for `sub' +os9x_65c816_global.s:805: Error: invalid char '[' beginning operand 2 `[R0' +os9x_65c816_global.s:807: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:808: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:810: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:814: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:816: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:817: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:818: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:819: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:821: Error: too many memory references for `mov' +os9x_65c816_global.s:822: Error: too many memory references for `add' +os9x_65c816_global.s:823: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:824: Error: no such instruction: `bne SW_NotBoundary' +os9x_65c816_global.s:826: Error: no such instruction: `stmfd R13!,{R0,R1}' +os9x_65c816_global.s:827: Error: no such instruction: `stmfd R13!,{PC}' +os9x_65c816_global.s:828: Error: no such instruction: `b asmS9xSetByte' +os9x_65c816_global.s:829: Error: too many memory references for `mov' +os9x_65c816_global.s:830: Error: no such instruction: `ldmfd R13!,{R0,R1}' +os9x_65c816_global.s:831: Error: too many memory references for `add' +os9x_65c816_global.s:832: Error: too many memory references for `mov' +os9x_65c816_global.s:833: Error: no such instruction: `stmfd R13!,{PC}' +os9x_65c816_global.s:834: Error: no such instruction: `b asmS9xSetByte' +os9x_65c816_global.s:835: Error: too many memory references for `mov' +os9x_65c816_global.s:837: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:841: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:842: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:843: Error: no such instruction: `bic rstatus,rstatus,' +os9x_65c816_global.s:845: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:846: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:847: Error: too many memory references for `mov' +os9x_65c816_global.s:848: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:849: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:850: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:851: Error: no such instruction: `bic R3,R3,' +os9x_65c816_global.s:852: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:853: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:854: Error: no such instruction: `ldr R2,[R2,R3,LSL' +os9x_65c816_global.s:855: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:856: Error: no such instruction: `blo SWSpecial@special' +os9x_65c816_global.s:857: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:860: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:861: Error: no such instruction: `tst R0,' +os9x_65c816_global.s:862: Error: no such instruction: `bne SW_not_aligned1' +os9x_65c816_global.s:863: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:864: Error: too many memory references for `mov' +os9x_65c816_global.s:865: Error: too many memory references for `add' +os9x_65c816_global.s:866: Error: no such instruction: `ldr R0,[reg_cpu_var,' +os9x_65c816_global.s:867: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:868: Error: no such instruction: `strh R1,[R2]' +os9x_65c816_global.s:869: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:870: Error: no such instruction: `ldr R0,[R0,R3,lsl' +os9x_65c816_global.s:871: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:872: Error: too many memory references for `add' +os9x_65c816_global.s:873: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:874: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:875: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:876: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:879: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:880: Error: too many memory references for `mov' +os9x_65c816_global.s:881: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:882: Error: invalid char '[' beginning operand 2 `[R2' +os9x_65c816_global.s:883: Error: too many memory references for `add' +os9x_65c816_global.s:884: Error: too many memory references for `mov' +os9x_65c816_global.s:885: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:886: Error: invalid char '[' beginning operand 2 `[R2' +os9x_65c816_global.s:887: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:888: Error: no such instruction: `ldr R0,[reg_cpu_var,' +os9x_65c816_global.s:889: Error: no such instruction: `ldr R0,[R0,R3,lsl' +os9x_65c816_global.s:890: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:891: Error: too many memory references for `add' +os9x_65c816_global.s:892: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:893: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:894: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:895: Error: no such instruction: `ldmfd R13!,{PC}' +os9x_65c816_global.s:897: Error: no such instruction: `ldr PC,[PC,R2,LSL' +os9x_65c816_global.s:898: Error: too many memory references for `mov' +os9x_65c816_global.s:915: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:916: Error: no such instruction: `ldrb R2,[reg_cpu_var,' +os9x_65c816_global.s:917: Warning: `R2' is not valid here (expected `(%esi)') +os9x_65c816_global.s:917: Warning: `R2' is not valid here (expected `(%edi)') +os9x_65c816_global.s:917: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:918: Error: no such instruction: `addeq reg_cycles,reg_cycles,' +os9x_65c816_global.s:919: Error: too many memory references for `mov' +os9x_65c816_global.s:920: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:921: Error: too many memory references for `mov' +os9x_65c816_global.s:922: Error: too many memory references for `mov' +os9x_65c816_global.s:923: Error: too many memory references for `mov' +os9x_65c816_global.s:924: Error: too many memory references for `mov' +os9x_65c816_global.s:925: Error: no such instruction: `stmfd R13!,{R0,R1,R12,R14}' +os9x_65c816_global.s:926: Error: no such instruction: `bl S9xSetPPU' +os9x_65c816_global.s:927: Error: no such instruction: `ldmfd R13!,{R0,R1}' +os9x_65c816_global.s:928: Error: too many memory references for `add' +os9x_65c816_global.s:929: Error: too many memory references for `mov' +os9x_65c816_global.s:930: Error: no such instruction: `bic R1,R1,' +os9x_65c816_global.s:931: Error: no such instruction: `bl S9xSetPPU' +os9x_65c816_global.s:932: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:933: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:934: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:936: Error: too many memory references for `add' +os9x_65c816_global.s:937: Error: too many memory references for `mov' +os9x_65c816_global.s:938: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:939: Error: too many memory references for `mov' +os9x_65c816_global.s:940: Error: too many memory references for `mov' +os9x_65c816_global.s:941: Error: too many memory references for `mov' +os9x_65c816_global.s:942: Error: too many memory references for `mov' +os9x_65c816_global.s:943: Error: no such instruction: `stmfd R13!,{R0,R1,R12,R14}' +os9x_65c816_global.s:944: Error: no such instruction: `bl S9xSetCPU' +os9x_65c816_global.s:945: Error: no such instruction: `ldmfd R13!,{R0,R1}' +os9x_65c816_global.s:946: Error: too many memory references for `add' +os9x_65c816_global.s:947: Error: too many memory references for `mov' +os9x_65c816_global.s:948: Error: no such instruction: `bic R1,R1,' +os9x_65c816_global.s:949: Error: no such instruction: `bl S9xSetCPU' +os9x_65c816_global.s:950: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:951: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:952: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:954: Error: too many memory references for `add' +os9x_65c816_global.s:955: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:956: Error: no such instruction: `bic r0,r0,' +os9x_65c816_global.s:957: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:958: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:959: Error: too many memory references for `mov' +os9x_65c816_global.s:960: Error: too many memory references for `mov' +os9x_65c816_global.s:961: Error: too many memory references for `mov' +os9x_65c816_global.s:962: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:963: Error: no such instruction: `stmfd R13!,{R0,R1,R12,R14}' +os9x_65c816_global.s:964: Error: no such instruction: `blx reg_cycles' +os9x_65c816_global.s:965: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:966: Error: no such instruction: `ldmfd R13!,{R0,R1}' +os9x_65c816_global.s:967: Error: too many memory references for `add' +os9x_65c816_global.s:968: Error: too many memory references for `mov' +os9x_65c816_global.s:969: Error: no such instruction: `bic R1,R1,' +os9x_65c816_global.s:970: Error: no such instruction: `blx reg_cycles' +os9x_65c816_global.s:971: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:972: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:973: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:974: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:976: Error: too many memory references for `add' +os9x_65c816_global.s:977: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:978: Warning: `R2' is not valid here (expected `(%esi)') +os9x_65c816_global.s:978: Warning: `R2' is not valid here (expected `(%edi)') +os9x_65c816_global.s:978: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:979: Error: no such instruction: `ldmeqfd R13!,{PC}@return if SRAMMask=0' +os9x_65c816_global.s:981: Error: too many memory references for `and' +os9x_65c816_global.s:982: Error: no such instruction: `tst R0,' +os9x_65c816_global.s:983: Error: no such instruction: `bne SW_not_aligned2' +os9x_65c816_global.s:984: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:985: Error: no such instruction: `ldr R0,[reg_cpu_var,' +os9x_65c816_global.s:986: Error: no such instruction: `strh R1,[R0,R3]@*Memory.SRAM+Address&SRAMMask' +os9x_65c816_global.s:987: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:988: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:989: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:992: Error: too many memory references for `add' +os9x_65c816_global.s:993: Error: too many memory references for `and' +os9x_65c816_global.s:994: Error: no such instruction: `ldr R0,[reg_cpu_var,' +os9x_65c816_global.s:995: Error: invalid char '[' beginning operand 2 `[R0' +os9x_65c816_global.s:996: Error: too many memory references for `mov' +os9x_65c816_global.s:997: Error: invalid char '[' beginning operand 2 `[R0' +os9x_65c816_global.s:998: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:999: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:1000: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:1003: Error: too many memory references for `add' +os9x_65c816_global.s:1005: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:1006: Warning: `R2' is not valid here (expected `(%esi)') +os9x_65c816_global.s:1006: Warning: `R2' is not valid here (expected `(%edi)') +os9x_65c816_global.s:1006: Error: no instruction mnemonic suffix given and no register operands; can't size instruction +os9x_65c816_global.s:1007: Error: no such instruction: `ldmeqfd R13!,{PC}@return if SRAMMask=0' +os9x_65c816_global.s:1009: Error: no such instruction: `tst R0,' +os9x_65c816_global.s:1010: Error: no such instruction: `bne SW_not_aligned3' +os9x_65c816_global.s:1011: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:1012: Error: too many memory references for `mov' +os9x_65c816_global.s:1013: Error: too many memory references for `and' +os9x_65c816_global.s:1014: Error: too many memory references for `mov' +os9x_65c816_global.s:1015: Error: too many memory references for `mov' +os9x_65c816_global.s:1016: Error: too many memory references for `add' +os9x_65c816_global.s:1017: Error: too many memory references for `sub' +os9x_65c816_global.s:1018: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:1019: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:1020: Error: too many memory references for `and' +os9x_65c816_global.s:1021: Error: no such instruction: `strh R1,[R0,R3]@*Memory.SRAM+Address&SRAMMask' +os9x_65c816_global.s:1022: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:1023: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:1024: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:1026: Error: too many memory references for `mov' +os9x_65c816_global.s:1027: Error: too many memory references for `and' +os9x_65c816_global.s:1028: Error: too many memory references for `mov' +os9x_65c816_global.s:1029: Error: too many memory references for `mov' +os9x_65c816_global.s:1030: Error: too many memory references for `add' +os9x_65c816_global.s:1031: Error: too many memory references for `sub' +os9x_65c816_global.s:1033: Error: too many memory references for `add' +os9x_65c816_global.s:1034: Error: too many memory references for `mov' +os9x_65c816_global.s:1035: Error: too many memory references for `and' +os9x_65c816_global.s:1036: Error: too many memory references for `mov' +os9x_65c816_global.s:1037: Error: too many memory references for `mov' +os9x_65c816_global.s:1038: Error: too many memory references for `add' +os9x_65c816_global.s:1039: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:1040: Error: too many memory references for `sub' +os9x_65c816_global.s:1041: Error: too many memory references for `and' +os9x_65c816_global.s:1042: Error: too many memory references for `and' +os9x_65c816_global.s:1044: Error: no such instruction: `ldr R3,[reg_cpu_var,' +os9x_65c816_global.s:1045: Error: invalid char '[' beginning operand 2 `[R2' +os9x_65c816_global.s:1046: Error: too many memory references for `mov' +os9x_65c816_global.s:1047: Error: invalid char '[' beginning operand 2 `[R0' +os9x_65c816_global.s:1049: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:1050: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:1051: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:1056: Error: too many memory references for `add' +os9x_65c816_global.s:1057: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:1059: Error: too many memory references for `add' +os9x_65c816_global.s:1060: Error: too many memory references for `mov' +os9x_65c816_global.s:1061: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:1062: Error: too many memory references for `mov' +os9x_65c816_global.s:1063: Error: too many memory references for `mov' +os9x_65c816_global.s:1064: Error: too many memory references for `mov' +os9x_65c816_global.s:1065: Error: too many memory references for `mov' +os9x_65c816_global.s:1066: Error: no such instruction: `stmfd R13!,{R0,R1,R12,R14}' +os9x_65c816_global.s:1067: Error: no such instruction: `bl S9xSetC4' +os9x_65c816_global.s:1068: Error: no such instruction: `ldmfd R13!,{R0,R1}' +os9x_65c816_global.s:1069: Error: too many memory references for `add' +os9x_65c816_global.s:1070: Error: too many memory references for `mov' +os9x_65c816_global.s:1071: Error: no such instruction: `bic R1,R1,' +os9x_65c816_global.s:1072: Error: no such instruction: `bl S9xSetC4' +os9x_65c816_global.s:1073: Error: no such instruction: `ldmfd R13!,{R12,R14}' +os9x_65c816_global.s:1074: Error: no such instruction: `ldr reg_cycles,[reg_cpu_var,' +os9x_65c816_global.s:1075: Error: no such instruction: `ldmfd R13!,{PC}@Return' +os9x_65c816_global.s:1077: Error: too many memory references for `add' +os9x_65c816_global.s:1078: Error: no such instruction: `tst R0,' +os9x_65c816_global.s:1079: Error: no such instruction: `bne SW_not_aligned4' +os9x_65c816_global.s:1080: Error: junk at end of line, first unrecognized character is `@' +os9x_65c816_global.s:1081: Error: too many memory references for `mov' +os9x_65c816_global.s:1082: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:1083: Error: too many memory references for `mov' +os9x_65c816_global.s:1084: Error: too many memory references for `sub' +os9x_65c816_global.s:1085: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:1086: Error: no such instruction: `strh R1,[R0,R2]@*Memory.BWRAM+((Address&0x7fff)- 0x6000)' +os9x_65c816_global.s:1087: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:1088: Error: no such instruction: `ldmfd R13!,{PC}@return' +os9x_65c816_global.s:1090: Error: too many memory references for `mov' +os9x_65c816_global.s:1091: Error: too many memory references for `add' +os9x_65c816_global.s:1092: Error: too many memory references for `mov' +os9x_65c816_global.s:1093: Error: too many memory references for `mov' +os9x_65c816_global.s:1094: Error: no such instruction: `ldr R2,[reg_cpu_var,' +os9x_65c816_global.s:1095: Error: too many memory references for `sub' +os9x_65c816_global.s:1096: Error: too many memory references for `sub' +os9x_65c816_global.s:1097: Error: invalid char '[' beginning operand 2 `[R2' +os9x_65c816_global.s:1098: Error: too many memory references for `mov' +os9x_65c816_global.s:1099: Error: invalid char '[' beginning operand 2 `[R2' +os9x_65c816_global.s:1100: Error: expecting operand after ','; got nothing +os9x_65c816_global.s:1101: Error: invalid char '[' beginning operand 2 `[reg_cpu_var' +os9x_65c816_global.s:1102: Error: no such instruction: `ldmfd R13!,{PC}@return' +make: *** [os9x_65c816_global.o] Error 1 diff --git a/src/readme.txt b/src/readme.txt new file mode 100644 index 0000000..8fe6f95 --- /dev/null +++ b/src/readme.txt @@ -0,0 +1,10 @@ +3.71 +--files were errorenously getting _logXX.log names instead of _logXX.txt. Fixed +3.7 +what's new: +--new feature: per thread indent in the log files +--new options: STLOG_MULTITHREADING (turns on/off multithreading features), STLOG_USE_PERFORMANCE_CONTER (you can turn off usage of GetPerformanceCounter() function) +--fixed bug with stack overflow in GetLogFileName() function (thanks to Alexander Shargin) +--fixed bug with unclosed handle when used from DLL (thanks to Rene Heijndijk). +--fixed bug with ___DoNothing() function for the cases when the STLOG_DEBUG macro is undefined +--new functions: STLOG_WRITE_IID, STLOG_WRITE_GUID, STLOG_WRITE_CLSID diff --git a/src/rel/menu_header.bmp b/src/rel/menu_header.bmp new file mode 100644 index 0000000..6066978 Binary files /dev/null and b/src/rel/menu_header.bmp differ diff --git a/src/rel/readme.txt b/src/rel/readme.txt new file mode 100644 index 0000000..43e4104 --- /dev/null +++ b/src/rel/readme.txt @@ -0,0 +1,347 @@ +DrPocketSnes +Super Nintendo (SNES) Emulator +by Reesy + +DrPocketSnes is a Super Nintendo (SNES) emulator for the GP2X and Gizmondo. I've taken bits from PocketSnes and SquidgeSnes and merged them into another new emulator. I then stuck my menu system on it and called it my own :) you've got to love porting stuff. + +So credits for this emulator should really go to. + +Snes9x Team for creating the original Snes9x emulator +http://www.snes9x.com/ + +Scott Ramsby for PocketSnes port based on Snes9x sources +http://paqpark.nuclearfallout.net/projects/pocketsnes.php + +Yoyofr for OpenSnes9x port based on Snes9x sources +http://yoyofr.fr.st/ + +Squidge for the SquidgeSnes port based on OpenSnes9x +http://squidge2x.com/ + +Notaz for his fixes and improvements to SquidgeSnes. +http://notaz.atspace.com/ + +Rlyeh for his work on the gp2x (not so)minimal sdk +http://www.retrodev.info/ + +Reesy for merging everything and sticking a menu on it...the really complicated stuff ;). +http://reesy.gp32x.de/ + +==================== +IMPORTANT +When upgrading from v4 to v5 you will need to manually move the savestate files (*.sv*) from the options directory into the savestate directory and the SRAM files (*.srm) from the root installation directory into the sram directory. See change history for more details. +==================== + +============== +Change History +============== + +___________________________________ +Version 7.1.0 Release Date 28/10/2010 +___________________________________ +Changes by Bitrider + +- Added: Tv-Out compatiblity. + Thanks to XiM for the Ext connector used to make my Tv-Out cable, which made this feature possible. +- Internal changes: + Lots of code refactoring, make my life easier. + A new saner Makefile. + +___________________________________ +Version 7.0.1 Release Date ??/09/2010 +___________________________________ +Changes by Bitrider + +- Bug-fix release (Mode-7, priorities, sprites, etc) + +___________________________________ +Version 7.0.0 Release Date 30/07/2010 +___________________________________ +Changes by Bitrider + + Thanks goes to: + Buba-ho-tep, Rivroner (beta testers) + Anarchy (GP32Spain webmaster & conding contest promoter) + Head-On-Heels (v 6.5.0 developer) + Notaz, Squidge, Little Johnz & all those who contributed to this wonderful emulator. + +- Added: deep changes to SPC 700 assembly core, now it is faster. + - moved a few registers + - less reads/writes to memory + - implemented GetByteZ, GetByte, SetByteZ & SetByte in ARM assembly +- Added: modifications to 65c816 assembly core, a little bit faster. + - moved several flags from memory to status register. + - implemented SetPCBase in ARM assembly. + - SetDSP & GetDSP called directly (S9x_SetDSP & S9x_GetDSP where just wrapper functions with no added value). + - Assembly CPU code splitted in several files (modularity purposes) +- Added: 4 different assembly APU (SPC 700) cycle sizes: 13, 14, 15 & 21. + Now more games are compatible with fast executable & fast mode on compatible executable : + Human's ones (Firemen, ...), Secret of evermore, Clock Tower (yeah, I know it's also by Human but a special case) that one is for you Buba. +- Added: 16 bit fast assembly renderers for: + tile: opaque, add, add 1/2, add fix 1/2, sub, sub 1/2, sub fix 1/2 + tile clipped: opaque, add, add 1/2, add fix 1/2, sub, sub 1/2, sub fix 1/2 + mode 7 just one layer: solid, solid with priority, add, add 1/2, sub, sub 1/2 + mode 7 with priorities (two layers): solid, add, add 1/2, sub, sub 1/2. + subscreen filling: solid, add, add 1/2, sub, sub 1/2 +- Added: SpeedHacks (rom patching with snesadvance.dat) to fast executable +- Added: a switch to enable/disable speed hacks, "Apply snesadvance.dat on ROM load". +- Added: Super FX emulation to fast executable version. +- Added: last played ROM loading at PocketSNES startup +- Added: a switch to enable/disable last played ROM loading at startup +- Added: persistent selector in ROM list selector + Last selected ROM will continue being focused when you launch a ROM + and go back to the menu to select another ROM. (idea by Buba-ho-tep, thanks man.) + It does work only when you are in default PocketSNES ROM directory +- Added: display ROM file name while loading. +- Added: on ROM load error display error, pause & show "Push a button to continue". +- Added: fast version (65c816 assembly emulation) will show as "v 7.0.0 fast" + compatible version (65c816 C emulation) will show as "v 7.0.0 compatible" +- Added: the ability to use Fast (assembly SPC-700) or Compatible (C SPC-700), more games playable on fast executable. + - So "Emulation (Reset Required): Compatible/Fast" switch is now available on fast executable. +- Fixed: Auto save SRAM should only save when a change occurred +- Added: "Manual + indicator" to SRAM saving options + A disk will be displayed on the lower right corner of the screen when SRAM data is awaiting + Note: disk won't be visible if screen is resized +- Added: a little bit optimized sound block decode routine. + + +___________________________________ +Version 6.5.0 Release Date 24/10/2009 +___________________________________ +Changes by HeadOverHeels + 1. Optimizations in mode 7 and other code optimizations + 2. Horizontal scaler + + FAST VERSION + ------------ + 3. Increased compatibility: star ocean, rendering ranger, etc. + 4. More games are compatible with audio performance hack + + NORMAL VERSION + -------------- + 5. Full SuperFX and SA-1 emulation + 6. Snesadvance.dat speedhacks support + 7. 2 sound emulation modes: compatible and fast + +___________________________________ +Version 6.4.5 Release Date 06/06/2009 +___________________________________ +Changes by HeadOverHeels + 1. Ported to GP2X WIZ + 2. Optimizations in C4 emulation + +___________________________________ +Version 6.4.4 Release Date 16/11/2008 +___________________________________ +Changes by Reesy + 1. Zipped save states + 2. Rom Browser code tidied, you can now set the default directory + from inside the rom browser. The rom browser now also tells + you the current directory. +Changes by HeadOverHeels + 1. Fixed some bugs in layer priority (super ghouls'n ghosts level 4 for example) + 2. Optimizations in tile rendering code, ppu emulation, ... + 3. Changes in volume control to be more usable with headphones in firmware 4.0.0 and louder with firmware 4.1.1 + 4. Fixed: some games do not work if you don't restart the emulator + 5. Menu now sets cpu clock to 66 mhz to save battery + +___________________________________ +Version 6.4.3 Release Date 23/02/2008 +___________________________________ +Changes by HeadOverHeels + 1. USB pads support + 2. Fixed sky colour for Super Mario World when transparencies are not active. + 3. Fixed framerate for PAL games (50 fps) and added an option to configure region (AUTO, NTSC, PAL) + 4. Fixed sound problems with some games (Ilussion of Gaia for exmaple) + 5. Sound frequencies have been changed (8250,16500) to make GP2X F200 compatible + 6. 256x240 games resolution problem have been fixed + 7. C4 chip support (Megaman X2, X3) + 8. High resolution text support (Seiken Densetsu 3 - Secret of Mana2) + 9. Added DSP optimizations from snes9xTYL of Yoyofr. + 10. F200 sound level now is lower + 11. SDD1 support (Star Ocean & Street Fighter Alpha 2) + SDD1 decompressed packs are supported. SDD1GFX.DAT & SDD1GFX.IDX must be copied to a subdirectory named socnsdd1 (for Star Ocean) and sfa2sdd1 (for Street Fighter 2 alpha). Create these subdirectories in the roms directory. + If no packs are found, the emulator uses realtime decompression (slower) + 12. Other minor fixes and optimizations. + 13. Added stereo sound. + 14. New advanced hacks options: + Audio performance hack + Ignore palette writes + Ignore Fixed Colour + Ignore Windows clipping + Ignore Add/Sub modes + Layer desactivation + +Changes by Reesy +___________________________________ +Version 6 Release Date 04/02/2007 +___________________________________ + 1. Fixed a bug on the rom browsing code. Strings were not being terminated correctly. +___________________________________ +Version 5 Release Date 03/02/2007 +___________________________________ + 1. Changed the way SRAM works. The old versions of PocketSnes used a timer to check if SRAM had changed while the SNES emulator was running. If a change was detected the SRAM was saved straight away. This used to cause glitches in the framerate. SRAM is now saved when you enter the menu as long as you have SRAM saving set to automatic in the options menu. + 2. Added options to allow you to switch MMU hack on or off + 3. Added options to allow you to switch Craigx's RAM settings on or off. + 4. Fixed problems where data was not being saved to SD card correctly, I was missing a few calls to sync() + 5. I've tidied up the installation directory abit. Most things used to be stored in the options sub directory and somethings were saved to the root installation directory, which was a bit of a mess. So I've now created the following 3 directories in order to make things more logical. + + options (*.opt) - used to hold global and individual game settings + savestate (*.sv*) - used to hold save states for all games + sram (*.srm) - used to hold SRAM saves for all games + + This means that we you upgrade from Version 4 to Version 5 you will need to manually copy the savestates out of the options directory and into the savestate directory in order for PocketSnes to recognise them. You will also have to move the SRAM files out of the root +installation directory and into the sram directory. +___________________________________ +Version 4 Release Date 30/01/2007 +___________________________________ + 1. Fixed timer code which was causing the emulator to crash +___________________________________ +Version 3 Release Date 24/01/2007 +___________________________________ + 1. Scaled display mode added. + 2. 44K sound mode added. + 3. Super FX support added - very very buggy and slow +___________________________________ +Version 2 Release Date 24/01/2007 +___________________________________ + 1. Fixed Diagnals. + 2. Fixed Volume controls. + 3. Fixed Reset game function. + 4. Snes Select button now working. +___________________________________ +Version 1 Release Date 24/01/2007 +___________________________________ + Initial release + +========================= +Installation Instructions +========================= + +Along with this document you are reading you should have also received the following files + +PocketSnes.gpe - PocketSnes emulator +mmuhack.o - Additional module used to hack MMU and improve performance. + +Simply copy these files onto your SD card, the files can go anywhere but both files need to be in the same directory. I recommend putting the in a directory of their own because when the emulator first starts up it will create several subdirectories which are used to store options, savestates and SRAM saves. + +So for example create a directory called DrPocketSnes and then copy the PocketSnes.gpe and mmuhack.o files into the DrPocketSnes directory. + +Now you need to copy some SNES roms to you SD card. Again you can put your roms anywhere you like on your SD card, you just need to configure DrPocketSnes to point at your rom directory. To do this follow the instructions below + +1. Start PocketSnes +2. Select "Select Rom" from the menu. +3. This will take you by default to the current working directory (e.g the directory where you installed DrPocketSnes /mnt/sd/DrPocketSnes. +4. You now need to browse through the file system to find your rom directory. +5. To do this select ".." to move up and directory or select any entries that start with "+". Entries that start with "+" are directories, so selecting takes you into that directory. +6. Once you have located your rom directory, you need to save the current directory as your default rom directory. +7. To do this select the "Back To Main Menu" menu option. +8. Then select "SNES Options" +9. Then select "Save Current Rom Directory" +10. This will store the current rom directory in a text file held in the options directory. So the next time you start PocketSnes and select "Select Rom" you will be taken straight to your rom directory. + +============ +Menu Options +============ +_______________________________________________ +Return To Game + If you have a rom loaded this will allow to exit the menu and return to the game. +_______________________________________________ +Select Rom + Takes you to the Rom Selection screen which allows you load a new game. +_______________________________________________ +Manage Save States + Takes you to the save state management screen. Save states allow you to save your current position in the currently loaded game. This means that you can reload a particular position in the game as many times as you want. +_______________________________________________ +Save Sram + Allows you save the current contents of SRAM to a file. SRAM is the battery backup ram which used to be on the Snes cartridges. This allowed high scores or game progress, so that the next time you loaded the snes game you could continue where you left off. If you plan to use save states then you don't need to worry about SRAM saves as the save state holds all of this information as well. +_______________________________________________ +SNES Options + Takes you into the options screen which allows you to customise how the emulator runs. See "SNES Options - In Detail" for more information on each of the settings. +_______________________________________________ +Reset Game + Allows you to reset the current rom, its the same as reloading the rom apart from you don't have to read the rom file from the SD card again. +_______________________________________________ +Exit Application + Exits PocketSnes and reloaded the GP2X menu. +_______________________________________________ + +======================== +SNES Options - In Detail +======================== +_______________________________________________ +Sound + Allows you to turn the sound on or off +_______________________________________________ +Sound Rate + Allows you to configure the sample rate of the sound emulation. The high the rate the clearer and more accurate the sound. +_______________________________________________ +Volumne + Allows you setup default volume levels. Volume can also be controlled using the volume controls on the GP2X. +_______________________________________________ +Cpu Speed + Allows you select the GP2X cpu speed to be used when emulating the Snes. The higher the cpu speed the smoother the emulation is ( plus it drains you battery more) +_______________________________________________ +FrameSkip + Allows you to control how many frames are not rendered, this can allow you to keep full speed emulation when at low cpu speeds. AUTO will skip as many frames as needed in order to maintain full speed emulation. +_______________________________________________ +Action Buttons + The GP2X has the same button as the snes but the buttons are in the wrong order. This option allows you to have the same button names as the snes, or to have the same button positions as snes. + NORMAL = same button names as Snes + SWAPPED = same button positions as Snes +_______________________________________________ +Show FPS + This allows you to see how man frames are being rendered per second. This can allow you to see how the emulator is performing. +_______________________________________________ +Brightness + This allows you to control the current brightness of the screen. You can make it darker or brighter. +_______________________________________________ +Transparencies + The SNES has very complicated graphics hardware which can be quite slow to emulate. Switching off transparencies can improve performce but makes some games unplayable because you can not see all of the information that you need. +_______________________________________________ +Render Mode + Allows you to scale the emulated SNES graphics. The normal SNES screen resolution is less than the GP2X's, so when in unscaled mode the graphics appear in a window. If you select the scaled mode then the graphics are stretched to fill the screen. +_______________________________________________ +RAM Timing + This allows you select faster ram timings. This can improve performance. If you change this option you need to restart PocketSnes because these settings are only applied as the emulator is first started. +_______________________________________________ +MMU Hack + This option allows you to enable the MMU hack developed by Squidge. This option massively improves performance and is recommended. Again if you change this option you need to restart PocketSnes because these settings are only applied as the emulator is first started. +_______________________________________________ +Saving SRAM + This option allows you to control how the SRAM is saved to you SD card. If you select automatic then SRAM will be saved automatically everytime you return to the menu if it has been modified during the last run of emulation. If you select the manual option then SRAM will only be saved when you select the Save SRAM menu option from the main menu. +_______________________________________________ +Load Global Settings + This option will reload the global settings. Global Settings affect all games as long as the games does not have a setting file of its own ( See Load Settings for current game). +_______________________________________________ +Save Global Settings + This option allows you to save the current settings to the SD card. Everytime you load a new rom these settings will be reloaded, so basically they become you default settings. This can be overwritten using the "Save Settings For Current Game" option which allows you to save a config file for a particular rom. So each time you load the rom these settings will automatically be loaded. +_______________________________________________ +Delete Global Settings + Deletes any global setting file that has been created. If you have no global setting file then PocketSnes will use its own internal default settings when loading a new rom. +_______________________________________________ +Load Settings For Current Game + This option will load any setting file associated with the currently loaded rom. +_______________________________________________ +Save Settings For Current Game + This option allows you to save a config file for the currently loaded rom. So each time you load this rom these settings will automatically be loaded instead of the global settings. +_______________________________________________ +Delete Settings For Current Game + Deletes any config file for the currently loaded rom. +_______________________________________________ +Save Current Rom Directory + This option allows you to save the current rom directory as you default rom directory. +_______________________________________________ + + + + + + + + + + + + + diff --git a/src/rel/snesadvance.dat b/src/rel/snesadvance.dat new file mode 100644 index 0000000..a75bfe6 --- /dev/null +++ b/src/rel/snesadvance.dat @@ -0,0 +1,641 @@ +10000004|0|7E0147|0|1E|2A|18EC3|0|18EC3=EAEA,18E52=EAEA,18E70=EAEA,18E79=EAEA,185CC=EAEA,18612=EAEA,1865E=EAEA,186A5=EAEA,1871D=EAEA,18762=EAEA,184F1=EAEA,18531=EAEA,18560=EAEA,1858D=EAEA,656=42FC,18ED5=42D2,18EDC=EAEA,189F1=EAEA,18A0A=EAEA,18A44=EAEA,18A81=EAEA,18AC7=EAEA,18AF4=EAEA,18803=EAEA,1884A=EAEA,18896=EAEA,188DB=EAEA,188DD=EAEA,18955=EAEA,1899A=EAEA,18B20=EAEA,18B7E=EAEA,18BCA=EAEA,18C11=EAEA,18C89=EAEA,18CD0=EAEA,18D3C=EAEA,18D5A=EAEA,18D85=EAEA,15943=42FA,18EF7=42DB,18E00=42DB,18E2C=EAEA,15811=42FA,18DAE=EAEA,18DD7=80,189D3=EAEA,87=42FA,1534F=42F6 +FBF3C0FF|3x3 Eyes - Seima Korin Den (J)|4|40044804|0|0|0|0|214=42D8 +B3ABDDE6|7th Saga (U)|1320005|40800|0|0|0|0|3F2EB=42DA,FAC0=42F7 +68D7819A|7thsaga|5|C00|0|0|0|C +27FF5BA1|AAAHH! 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Mahou Se|4|0|0|0|0|0 +D1AE87BE|Andre Agassi Tennis (U)|0|0|0|0|0|0 +EA6AE8A9|Angelic Voice Fantasy (J)|10000005|4040|0|0|0|0 +CF0F14D2|Animaniacs|0|0|0|0|0|0|364C=EAEA,34EE=EAEA,139=4284,570=EAEA +83B40AF2|Another World (E)|10000002|0|0|0|0|0|658D=EAEA,65A0=EAEA,65B7=EAEA,65CC=EAEA,65D4=EAEA,65E1=EAEA,65E6=EAEA,65FB=EAEA,6605=EAEA,6617=EAEA,662A=EAEA,66B5=EAEA,66C5=EAEA,1D997=4251,234C9=DB6D +4CA1696F|Aqutallion (J)|4|0|0|0|0|0 +B6DBF57B|Arabian Nights - Sabaku no Seir|5|44000|0|0|0|0|114C=EAEA,1177=EAEA,1156=EAEA,573A=EAEA,58B3=EAEA,4FBA=EAEA,4F90=EAEA,5387=EAEA,538C=EAEA,4C45=42FB +02394F36|Arcade's Greatest Hits - The At|0|0|0|0|0|0|155=421B,D5F=421B +C891B297|Arcana (U)|4|0|0|0|0|0|1C1A=EAEA,1C3D=EAEA,5128=EAEA,516C=EAEA,51FB=EAEA,5208=EAEA,52BA=EAEA,52D0=EAEA,52DD=EAEA,5303=EAEA,5330=EAEA,533B=EAEA,5340=EAEA,5372=EAEA,E8160=EAEA,3A6=42,8FA=423A,900=421A,300EC=423F,30564=423F,EA2B9=4219 +E1CCCE49|Archer MacLean's Dropzone (E) [|2|0|0|0|0|0|F840C=EAEA +C9067671|Arcus Spirits (J)|0|0|0|0|0|0 +51A5F489|Ardy Lightfoot (U)|0|44C00|0|0|0|0|D008F=EAEA,D04A7=EAEA,7D6A=EAEA +06388F71|Area 88 (J)|8000000|44400|0|0|0|0|61=EAEA,129=42FC,65C4=42D5 +395BADE3|Aretha (J)|10000004|40840840|0|0|0|0|2367D=42D9,103D=423B +FF63EC26|Aretha II - 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Search for Eden (U)|4|0|0|0|0|0|130406=EAEA,13031A=EAEA,130429=EAEA +DC9BB451|Earthbound (U)|5|0|0|0|0|FFFFFFF6|AB93=EAEA,281D=EAEA,83A2=800E1A8FF07F32CFF07F3080,A12D=80,1FFE7=EAA90000,3FDD6=EAA9000080,8762=42FB +3A4A47EB|Earthworm Jim|4000001|0|5114|0|32|0|30169=DB +393DE197|Earthworm Jim 2 (U)|1|0|0|0|0|0|EB99=EAEA,EBC5=EAEA,ED96=EAEA,EDC4=EAEA,EABB=EAEA,E2B4=EAEA,582A=42FC +F0AEAD80|Edo No Kiba (J)|14000001|44800|0|0|0|0|E00A8=EAEA,759=42FC +EEC5A5B1|Edono Kiba (J)|14000001|44800|0|0|0|0|E00A8=EAEA,759=42FC +41E9CD70|Eien no Filena (J)|4|0|0|0|0|0|14DB62=EAEA,14DB96=EAEA,14DBB1=EAEA,14DBB9=EAEA,14DCC4=EAEA,14DFFC=EAEA,14E00E=EAEA,14E02B=EAEA,14E036=EAEA,14E058=EAEA,14E067=EAEA,14E078=EAEA,14E084=EAEA,14E0C4=EAEA,14E0DB=EAEA,14E0E6=EAEA,11A=423B,11F=421B,137=42D7,2296=42D9,2408=42D7,681F=42D9,1276B=42BA,12D63=42BA,1577D4=4251 +F70F2A95|Energy Breaker (J)|4000004|0|0|0|0|0 +BDBF64B3|Energy Breaker (J) [T-Eng]|4|0|0|0|0|0|17F2E8=428A,1813F3=42,1B64E0=4270,1BA050=42D0,1BA3AE=42BA,1BEE5F=42,1C17A0=DB,30D24D=DBF6,30E115=4210,766E=EAEA,7930=EAEA,7985=EAEA,7A94=EAEA,7C2E=EAEA,7C46=EAEA,7C51=EAEA,7C56=EAEA,20C291=EAEA,20F33F=EAEA +634344A0|Esparks - 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Emblem of Justice (J)|5|0|0|0|0|0|5057B=EAEA,503B0=EAEA,503EC=EAEA,50423=EAEA,50453=EAEA,5047C=EAEA,504B0=EAEA,E9E=42DC,23A8=42D4,1017C=42D8,218C7=42D1,10401=42D1,503B4=42D2,F62=42D4,90385=42D4,19DE=42D4,11E67=42D4 +7D36ECD7|Feda - The Emblem of Justice (J|5|0|0|0|0|0|5057B=EAEA,503B0=EAEA,503EC=EAEA,50423=EAEA,50453=EAEA,5047C=EAEA,504B0=EAEA,E9E=42DC,23A8=42D4,1017C=42D8,218C7=42D1,10401=42D1,503B4=42D2,F62=42D4,90385=42D4,19DE=42D4,11E67=42D4 +65D0A825|ff2|10000004|0|0|0|0|0|F24=42DC,F15=42DC,BED=42,10524=42,20033=EAEA,20063=EAEA,20077=EAEA,200AA=EAEA,20235=EAEA,202D6=EAEA,202FA=EAEA,20311=EAEA,20374=EAEA,20385=EAEA,203A1=EAEA,204AB=EAEA,20547=EAEA,2056F=EAEA,205C7=EAEA,205D8=EAEA,205FA=EAEA,20610=EAEA +CAA15E97|FF4 (J)|4|0|0|0|0|0|F24=42DC,F15=42DC,BED=42,10524=42,20033=EAEA,20063=EAEA,20077=EAEA,200AA=EAEA,20235=EAEA,202D6=EAEA,202FA=EAEA,20311=EAEA,20374=EAEA,20385=EAEA,203A1=EAEA,204AB=EAEA,20547=EAEA,2056F=EAEA,205C7=EAEA,205D8=EAEA,205FA=EAEA,20610=EAEA +D5CC300E|ff4e|4|0|0|0|0|0|F24=42DC,F15=42DC,BED=42,10524=42,20033=EAEA,20063=EAEA,20077=EAEA,200AA=EAEA,20235=EAEA,202D6=EAEA,202FA=EAEA,20311=EAEA,20374=EAEA,20385=EAEA,203A1=EAEA,204AB=EAEA,20547=EAEA,2056F=EAEA,205C7=EAEA,205D8=EAEA,205FA=EAEA,20610=EAEA +C1BC267D|FF5 (J)|10000005|0|0|0|0|0 +170778FA|ff6e|5|0|0|0|0|0 +250B44BA|FFMISTIC|10000004|40C00|0|0|0|0|68047=EAEA,68068=EAEA,6807A=EAEA,680CD=EAEA,680FD=EAEA,68114=EAEA,68121=EAEA,6819B=EAEA,681A3=EAEA,681B9=EAEA,681C1=EAEA,681CB=EAEA,681DC=EAEA,681E4=EAEA,68214=EAEA,6821C=EAEA,6822F=EAEA,6828C=EAEA,6839E=EAEA,683C7=EAEA,683DD=EAEA,68437=EAEA,684CA=EAEA,6855F=EAEA,685D0=EAEA,685D6=EAEA,685F0=EAEA +A27F1C7A|Final Fantasy 3 (V1.0) (U)|10000005|44C00|0|0|0|0|28236=42DC,B7A3=EAEA,568=42FC,B80A=EAEA,109B9=EAEA,50055=EAEA,500A6=EAEA,500D6=EAEA,500ED=EAEA,500FA=EAEA,501B8=EAEA,5027C=EAEA,50391=EAEA,503E1=EAEA,5044C=EAEA,50489=EAEA,504B0=EAEA,504CB=EAEA,504F2=EAEA,50521=EAEA,5059B=EAEA,505C5=EAEA,5064A=EAEA,50662=EAEA,506A4=EAEA,506B2=EAEA,71796=EAEA,83440=EAEA,25F824=EAEA,25F855=EAEA,25F8D0=EAEA,295AF6=EAEA,2E1889=EAEA,11A28=42DC +C0FA0464|Final Fantasy III (U) (V1|10000005|44C00|0|0|0|0|28236=42DC,B7A3=EAEA,568=42FC,B80A=EAEA,11A28=42DC +892E44BE|Final Fantasy 5|5|0|0|0|0|0 +17444605|Final Fantasy 5 (Translated)|10000005|0|0|0|0|0|387BB=42DC,4E45=42FC,422=EAEAEA +8D66F796|Final Fantasy 5 (Translated)|10000005|40C00|0|0|0|0|422=EAEAEA,10397=421A,11A88=42D5,1EA6C=421A,1F77A=421A,2A10D=423A,2A113=421A,4CE48=42,4F07A=DBFE,1BF7CC=DB,387BB=42DC,4E45=42FC +45EF5AC8|Final Fantasy 6 (J)|10000005|44C00|0|0|0|0|B6D8=421B,B6D8=EAEA,B73F=421B,B73F=EAEA,568=42FC +23084FCD|Final Fantasy II|0|0|0|0|0|FFFFFFE7|F24=42DC,F15=42DC,BED=42,10524=42,20033=EAEA,20063=EAEA,20077=EAEA,200AA=EAEA,20235=EAEA,202D6=EAEA,202FA=EAEA,20311=EAEA,20374=EAEA,20385=EAEA,203A1=EAEA,204AB=EAEA,20547=EAEA,2056F=EAEA,205C7=EAEA,205D8=EAEA,205FA=EAEA,20610=EAEA +D19F6CB5|Final Fantasy V (J) [T+Eng1|10000005|0|0|0|0|0|B7D8=EAEA,B7E0=EAEA,3FE4A=EAEA,3FE6E=EAEA,3FE81=EAEA,3FED2=EAEA,3FF02=EAEA,3FF19=EAEA,3FF26=EAEA,3FFA0=EAEA,3FFA8=EAEA,3FFB2=EAEA,3FFC3=EAEA,3FFCB=EAEA,3FFF3=EAEA,3FFFB=EAEA +87C13675|Final Fantasy V (J) [T+Eng1|10000006|0|0|0|0|0|387BB=42DC,4E45=42FC,422=EAEAEA +4CAB21DB|Final Fight|0|0|7E0D0A|0|1E|0|81F5=EAEA,8231=EAEA,FA=421C +8C37FF55|Final Fight 2 (U)|0|0|7E1019|0|1E|0|966=42DB +A916E708|Final Fight 3 (U)|1|0|0|0|0|0|66F3=42F4 +BC1AE3C2|Final Fight Guy (US)|0|0|0|0|0|0|8456=EAEA,8312=EAEA,836C=EAEA +25D214F4|Fire Emblem - Monsyo no Nazo (V|4|0|0|0|0|0|3969=EAEA,3977=EAEA,39CC=EAEA,39DD=EAEA,39F0=EAEA,3A24=EAEA,3A56=EAEA,3A5B=EAEA,3A8A=EAEA,3AA2=EAEA,3AAD=EAEA,3AB2=EAEA,3CA5=EAEA,3CBE=EAEA,1C9A35=EAEA +DC0D8CF9|Fire Emblem 4 - Seisen no Keifu|5|0|0|0|0|0 +BC6162AE|Fire Emblem 5 Trachia 776 (J) (|4|0|0|0|0|0 +FC519952|Fire Emblem 5 Trachia 776 (Rom|4|0|0|0|0|0 +E500C7BA|Fire Striker (U)|0|0|0|0|0|0|96=42D9 +1E6ACEBA|Flashback - The Quest for Ident|1|0|0|0|0|0|190098=EAEA,1900B0=EAEA,1900BB=EAEA,1900C0=EAEA,1900EE=EAEA,1900FD=EAEA,190497=EAEA,1904C6=EAEA,1904F5=EAEA,19052C=EAEA,190560=EAEA,190588=EAEA,80A2=42D9,8183=42,15974=42,15991=42,159CF=42,159EC=42,15B60=42,16220=42,1628E4=4259 +3E7B51E0|Flintstones, The (U)|0|0|0|0|0|0 +5FA4D051|Foreman For Real (U)|0|0|0|0|0|0|11791=42F2 +21239DDA|Frank Thomas' Big Hurt Basebal|4|0|0|0|0|0|44F4=42FC,44D9=42FC,39104=42FC,39159=42FC,1E445=42FC,1E4AC=42FC,1F4F7=42FC,1F6CC=42FC,12126=42FC +FFA8D1FF|Frantic Flea (U)|0|0|0|0|0|0|1A424=EAEA,1A547=EAEA,1A4EF=EAEA,1A3FB=EAEA,1A4C4=EAEA,1A399=EAEA,1A45E=EAEA,1A49B=EAEA,8138=42FB +2488B8F2|Frogger (U)|0|0|0|0|0|0|7F353=EAEA,7F378=EAEA,7ED2F=42FC +2B4CD5A3|Front Mission (J) (V1.0)|5|40800|0|0|0|0|2A0A1B=EAEA,258A=42FB +5847D80F|Front Mission - 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Aah Sekai yo Ha|4|0|0|0|0|0 +D191AD46|Hanjuku Eiyuu - Aah Sekai yo Ha|4|0|0|0|0|0 +D54E1452|Harvest Moon (E) [!]|6|0|7E0147|0|1E|2A|18EC3=EAEA,18E52=EAEA,18E70=EAEA,18E79=EAEA,185CC=EAEA,18612=EAEA,1865E=EAEA,186A5=EAEA,1871D=EAEA,18762=EAEA,184F1=EAEA,18531=EAEA,18560=EAEA,1858D=EAEA,656=42FC,18ED5=42D2,18EDC=EAEA,189F1=EAEA,18A0A=EAEA,18A44=EAEA,18A81=EAEA,18AC7=EAEA,18AF4=EAEA,18803=EAEA,1884A=EAEA,18896=EAEA,188DB=EAEA,188DD=EAEA,18955=EAEA,1899A=EAEA,18B20=EAEA,18B7E=EAEA,18BCA=EAEA,18C11=EAEA,18C89=EAEA,18CD0=EAEA,18D3C=EAEA,18D5A=EAEA,18D85=EAEA,15943=42FA,18EF7=42DB,18E00=42DB,18E2C=EAEA,15811=42FA,18DAE=EAEA,18DD7=80,189D3=EAEA,87=42FA,1534F=42F6 +F829129E|Harvest Moon (U)|4|0|7E0147|0|1E|2A|18EC3=EAEA,18E52=EAEA,18E70=EAEA,18E79=EAEA,185CC=EAEA,18612=EAEA,1865E=EAEA,186A5=EAEA,1871D=EAEA,18762=EAEA,184F1=EAEA,18531=EAEA,18560=EAEA,1858D=EAEA,656=42FC,18ED5=42D2,18EDC=EAEA,189F1=EAEA,18A0A=EAEA,18A44=EAEA,18A81=EAEA,18AC7=EAEA,18AF4=EAEA,18803=EAEA,1884A=EAEA,18896=EAEA,188DB=EAEA,188DD=EAEA,18955=EAEA,1899A=EAEA,18B20=EAEA,18B7E=EAEA,18BCA=EAEA,18C11=EAEA,18C89=EAEA,18CD0=EAEA,18D3C=EAEA,18D5A=EAEA,18D85=EAEA,15943=42FA,18EF7=42DB,18E00=42DB,18E2C=EAEA,15811=42FA,18DAE=EAEA,18DD7=80,189D3=EAEA,87=42FA,1534F=42F6 +DD792499|Hashire Hebereke (J)|4|0|0|0|0|0|902=421A,938=421A,946=421A,9C3=421A,BCB=42BA +46ACFC84|Holy Striker (J)|0|0|0|0|0|0 +07C494B1|Home Alone|0|0|0|0|0|0|1C1=EAEA,3D9=EAEA,3FB=EAEA,40D=EAEA,429=EAEA,443=EAEA,44E=EAEA,453=EAEA,48E=EAEA,499=EAEA,4AE=EAEA,4C5=EAEA,4DC=EAEA,4E9=EAEA,4F9=EAEA +D19165D9|Home Alone 2 - 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The Enforce Fighter |0|4040|0|0|0|0|11D=EAEA,FEBD9=42FB,348=42DB +DEF45776|Pilotwings (E)|2|0|0|0|0|0|31F5=EAEA,38D8=EAEA,52B6=EAEA,579D=EAEA,57D2=EAEA,58A0=EAEA,6176=EAEA,6576=EAEA,65B2=EAEA,65CA=EAEA,72A7=EAEA,72BD=EAEA,72C8=EAEA,72CD=EAEA,A76A=EAEA,BD06=EAEA,CE61=EAEA,CFEF=EAEA,716F=4217,728D=42D4 +81107CE2|Pinball Dreams (U)|10000000|0|0|0|0|0|56EB=EAEA,575B=EAEA,578A=EAEA,57AE=EAEA,5685=42DB,1320=42FB,13A5=42FB,3237=42FB,D34=42,953=42B9,1C74=42FA,1E94=42D8 +822AD378|Pinball Fantasies (U)|0|0|0|0|0|0|B0339=EAEA,B0486=EAEA,B0492=EAEA,B0384=EAEA,B0390=EAEA,B03A9=EAEA,B03B5=EAEA,1458=42FB,14DD=42FB,3D8D=42FB +AF2A3DFE|Pipe Dream (J)|0|40800|0|0|0|F|103B8=42FB,164=42F9,F74=42 +7CA0CA4D|Pirates of Dark Water (U)|0|0|0|0|0|0|297D=42FC +2B0E7EA3|Pocky & Rocky (U) [!]|0|0|0|0|0|0|5252=EAEA,2299=EAEA,2421=EAEA,1CA=42DB +892C6765|Pokemon (PD)|4000000|900000|0|0|0|0|4326=EAEA,4353=EAEA,436B=EAEA,4376=EAEA,437B=EAEA,43A9=EAEA,43BA=EAEA,FA3=42,22BA=42D8,1BE60F=DB +D16810CD|Poko Nyan! - Henpokorin Adventu|0|44000|0|0|0|0|69A4=428E +EE13E32D|Pop 'N' Twinbee (J)|10000000|840000|0|0|0|0|118=4280 +2DF4AA0F|Populous (U)|0|40C00|0|0|0|0|390D=4280,14F0E=429C,181A8=DB,1F450=DB +0A0235C0|Populous 2 (J)|0|4040|0|0|0|0 +CB4F87BB|Prehistorik Man (U)|10000000|4F0000|0|0|0|0|1FA18=EAEA,1FA61=EAEA,48314=EAEA,7F68=42FC,4D4=EAEA,181E3=EAEA,1F9CA=EAEA,1F9E2=EAEA,1F9F3=EAEA,1FA0E=EAEA,1FA35=EAEA,1FC6C=EAEA,1FC71=EAEA,1FCA8=EAEA,333E8=EAEA,496E7=EAEA +320562C3|Prince of Persia (E)|2|0|0|0|0|0 +891BB2BB|Prince of Persia (U)|0|0|0|0|0|0|118C2=EAEA,118D3=EAEA,118DF=EAEA,1190B=EAEA,11999=EAEA,11921=EAEA,1A2C1=42DB,1A2CD=4299 +96BD588B|Puzzle Bobble (J)|0|40C00|0|0|0|0 +694CBFE4|Q-bert 3 (U)|0|0|0|0|0|0|7E56=EAEA,6822=42FC +642B656B|R-Type 3|0|0|0|0|0|0|7F37=428E,1DE49E=421B +583FDBFF|Radical Dreamers (SNES) (J) [T+|5|0|0|0|0|0|20F21=EAEA,CFE58=EAEA,CFE5F=EAEA,CFE7D=EAEA,CFEB0=EAEA,CFEE0=EAEA,CFEFB=EAEA,CFF08=EAEA,D0054=EAEA,D0084=EAEA,D00C9=EAEA,D023F=EAEA,D028D=EAEA,D03DB=EAEA,D03FA=EAEA,D040C=EAEA,D0416=EAEA,D0445=EAEA,D0467=EAEA,D050C=EAEA,D0563=EAEA,D05AF=EAEA,D05CB=EAEA,D05D2=EAEA,D05E2=EAEA,D0664=EAEA,D067B=EAEA,D09C2=EAEA,9E41=421A,A1AB=421A,A1BE=421A,A1EA=421A,A1FF=421A,B85B=42BA,F8050=42 +C352D27F|Raiden Densetsu (J) [!]|18000000|0|0|0|0|0|E29=42,E34=42FC,E3A=429A +02CE6C96|Raiden Trad|18000000|0|0|0|0|0|E29=42,E3A=429A +9C79C3B8|Ranma RPG - Anime [T+Eng1.00]|4|0|0|0|0|0|456B=42DB +053B2615|Ranma ½ Bun no 1 - Bakuretsu Ra|1|0|0|0|0|0|FFA0=EAEA,4B1=42FB +0C552B1F|Ranma ½ Bun no 1 - Chogi Ranbu|1|0|0|0|0|0|32F=42DB,40640=42FB,48AF2=DB03,45E5B=DB91 +9BE46820|Realm (E) [!]|2|0|0|0|0|0|85EF=EAEA,F8263=EAEA,F82AF=EAEA,F82D5=EAEA,85E1=42FC,958=42FC,228=42FC +C2413BDD|Rejoice - Aretha Oukoku no Kana|4|44800|0|0|0|0|A5831=EAEA,A55F3=EAEA,A55FB=EAEA,A5838=EAEA,A583C=EAEA,A5845=EAEA,A5849=EAEA,A582D=42DA,2D516=42DB,2DAE1=42DB,2D687=42DB,95F6=42DB,226=42DB,4F7=42DB,7C86=42DB,6E74=42DB,72A5=42DB,1425B=42DB,16DF=42DB,9252=42DB,CEFE=42DB,CEB5=42DB,6D06=42DB,AFB6=42DB,92BC=42DB +CA988F59|Rival Turf (U)|0|0|0|0|0|0|272=EAEA,A6E=EAEA,1A3B=EAEA,1A9F=EAEA,1BB3=EAEA,1BB9=EAEA,632F=EAEA,6343=EAEA,635B=EAEA,6368=EAEA,643A=EAEA,6432=EAEA,6441=EAEA,6456=EAEA,C435=EAEA,11B16=EAEA,F1444=EAEA +BB2B8E2E|Road Runner (E)|2|0|0|0|0|0|7DD3=EAEA,7DEB=EAEA,7DF6=EAEA,7DFB=EAEA,7E88=EAEA,7E8E=EAEA,28902=EAEA,2A605=EAEA,381FD=EAEA,9FE7E=EAEA,9FE84=EAEA,163B=DB +F5AB5D91|Robocop Versus The Terminator |14000000|4040|0|0|0|0|94E=42DB,6D=42DB,AE=42DB,141E=EAEA,5FF5=42D9 +7AD4AADC|Robotrek (U)|5|0|0|0|0|0|4800D=421A +7D06F473|Rock N' Roll Racing (U)|0|0|0|0|0|0|7994=EAEA,AD8F=EAEA,F617=EAEA,3D10=4284 +0ECDC493|Rockman & Forte (J) [T+Eng1.00-|4000001|40000|7|0|0|0|D=42FB +2DCD95B9|Rockman 7 - Syukumei no Taikets|0|0|0|0|0|0 +F0ECDD92|Roger Clemens' MVP Baseball (U)|0|44808|0|0|0|0|A2E5D=42,A2E68=42,A5F0C=42DA,9=42,A39CB=42DB,683E=42 +8033574A|Romance of the Three Kingdoms I|4|0|0|0|0|0|12C1=EAEA,3115=EAEA,19F3=42DB +9684526D|Romancing Saga (V1.1) (J)|8000004|84848484|0|0|0|0|20068=EAEA,20098=EAEA,200AC=EAEA,200DF=EAEA,201C3=EAEA,201CB=EAEA,201E1=EAEA,20248=EAEA,202F0=EAEA,20319=EAEA,20330=EAEA,20385=EAEA,2039D=EAEA,2043C=EAEA,204EA=EAEA,2055C=EAEA,20564=EAEA,20589=EAEA,2058F=EAEA,205A9=EAEA,2D4=42D9,962=DB,13D34=4280,CEFBF=4258 +54A585BC|Romancing Saga 2 (J)|5|0|0|0|0|0|370B=EAEA,556F=EAEA,5581=EAEA,321E5=EAEA,4004A=EAEA,4006A=EAEA,40081=EAEA,4008C=EAEA,40095=EAEA,400E6=EAEA,40116=EAEA,4012D=EAEA,4013A=EAEA,40232=EAEA,4023A=EAEA,40257=EAEA,403DA=EAEA,40403=EAEA,40419=EAEA,40501=EAEA,40593=EAEA,405E1=EAEA,40613=EAEA,40619=EAEA,40666=EAEA,4067F=EAEA,406EB=EAEA,40719=EAEA,4072E=EAEA,40779=EAEA,407A7=EAEA,407BC=EAEA,407EA=EAEA,407FF=EAEA,4082D=EAEA,40840=EAEA,4084C=EAEA,14315C=EAEA,32F=4296,572=4210,69A=42D9,3981=42B0,E76B=42D9,204AF=42D9,30176=4280,3AEA7=42DD,3B0CB=42DD,3B3D2=42DD,3DF0A=DB,3E2E3=DB,3E91F=4280,568B5=DB +5399BDDB|Romancing SaGa 3 (J) (V1.0)|5|4800|0|0|0|0|6063D=EAEA,60643=EAEA,609B0=EAEA,670=42DC,3EC170=42FA,1C42A=42D9,5F957=42FC +42C664C2|Romancing Saga 3 (V1|5|40444444|0|0|0|0|6063D=EAEA,60643=EAEA,609B0=EAEA,670=42DC,3EC170=42FA,1C42A=42D9,5F957=42FC +E0BD6C71|RPG Tukool - Super Dante|4|0|0|0|0|0|00C1=EAEA,B74C=EAEA,B757=EAEA,B762=EAEA,B761=EAEA,B74B=EAEA +E20870EE|RPG Tukool - Super Dante (J)|4|0|0|0|0|0 +5D8CB7AC|Rudra no Hihou (J)|5|0|0|0|0|0|23A5=EAEA,4AA=42FC +244280AE|Rudra no Hihou (J) [T+Eng|2|0|0|0|0|0|130906=EAEA,26187A=EAEA,2B0022=EAEA,2B00A5=EAEA,2B00C9=EAEA,2B031C=EAEA,2B033E=EAEA,2B0357=EAEA,2B0457=EAEA,2B094B=EAEA,2B0954=EAEA,2B095F=EAEA,2DC5B6=EAEA,4AA=42FC +8708E5BB|Run Saber (U)|0|0|0|0|0|0|525=421B,9AB=4290 +454D7DCD|Ryuuki Heidan Danzalv (J)|5|44800|0|0|0|0|F8335=42FB,F8345=421B,F73FE=421B,F8340=423B,F8DDA=42DB,88D3A=4215,8C04F=42FC +CD89020D|Sailor Moon (F)|3|0|0|0|0|0|1B7F8=42FC,1BE5A=42CF,936E=42FC +2E614A53|Samurai Shodown (U)|1|4040|0|0|0|0|10B4=42 +4C78D5EE|Sangokushi - Eiketsu Den (J)|5|4000|0|0|0|0|2C0BB0=EAEA,898D=42DC,1E29=42DB,850E=42DC,1E8F=42DB,87A4=42DC,8544=42DC,1D8C=42DC +98D7611E|Scooby Doo (U)|0|C00|0|0|0|0|DDF0D=EAEA,1017D6=EAEA,114DD0=EAEA,114DF2=EAEA,114DFD=EAEA,114E02=EAEA,114FE5=EAEA,114FF4=EAEA,115007=EAEA,115041=EAEA,11506F=EAEA,115077=EAEA,115097=EAEA,1150A2=EAEA,1B5B14=EAEA,1C988F=EAEA,C39=42DB,1A6874=4211 +8BFCB5A3|SD Gundam X (J)|4|44000|0|0|0|0|454F=EAEA,16E91=EAEA,16ECC=EAEA,16EDD=EAEA,16EEB=EAEA,16EF0=EAEA,16F1E=EAEA,2C5F1=EAEA,4D024=EAEA,975E1=EAEA,AE344=4219 +AAE842D2|SD The Great Battle (J)|1230000|0|0|0|0|0|181=EAEA,6A9C=DB6A +A5C0045E|Secret of Evermore (U)|14000005|0|0|0|0|0 +D0176B24|Secret of Mana (U)|5|4000|7E0604|0|64|A|79773=EAEA,B07B=42DC,694D=421B +EF968ED1|Secret of the Stars (U)|1320004|0|0|0|0|0|417=421B +A638BEF1|Seifuku Densetsu Pretty Fighter|1|0|0|0|0|0 +15320173|Seijuu Maden - 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Baseball Jitsumei Ban 2 |4|0|0|0|0|0|7AF=421C +393CCCA2|Umi Hara Kawa Se (J)|40C0004|0|0|0|0|0|F0=42 +3C3C63E6|Uncharted Waters - New Horizons|5|0|0|0|0|0|9E98=42D9,9F5F=42DB +B574C939|Undercover Cops (J)|1|0|0|0|0|0|1C0520=EAEA,1C011D=EAEA,1C04C6=EAEA,1C04E3=EAEA,1C02E2=EAEA,1C02FF=EAEA,1C00D0=EAEA,1C00ED=EAEA,8128=42 +59180F1C|Universal Soldier (U) (Beta)|0|44C00|0|0|0|0|4A68=EAEA,4423=42FB,43F1=42F7,43A4=42D9,6033=42D8 +B9BF7990|Urban Strike (U) [!]|0|0|0|0|0|0 +2D1004F1|Wario's Woods (U)|4|0|0|0|0|0|58195=EAEA,5824E=EAEA,32F=42DC +A47884D0|Warlock (U)|4000000|0|0|0|0|0|676E=EAEA,6786=EAEA,6791=EAEA,6796=EAEA,67DB=EAEA,67E2=EAEA,6804=EAEA,683D=EAEA,6854=EAEA,6867=EAEA,68E0=EAEA,68F7=EAEA,690A=EAEA,694C=EAEA,69ED=429B,E905=42D9,1680FA=DB6E +8B477300|WCW Super Brawl (U)|0|0|0|0|0|0|13FFD=42FC,BBD9=42DB +7379E3B3|Whirlo (E)|2|0|0|0|0|0|CD3=42DC +1637D1A5|Wings 2 (U)|0|0|0|0|0|0|78103=EAEA,78116=EAEA,78119=EAEA +D5CE2DB5|Wizard of Oz, The (U)|0|44800|0|0|0|0|150=42FC,5224=42 +B8A72553|Wizardry 1 2 3 (J) (NP)|4|0|0|0|0|0|1C008E=EAEA,1C00CB=EAEA,1C00E0=EAEA,1C0108=EAEA,1C05AC=EAEA,1C05E3=EAEA,1C05ED=EAEA,BD=DB,1BF=42BA,159750=4210 +D8FDDD76|Wizardry 5 (U)|4|0|0|0|0|0|18A=42BA,213=428C,66830=42,14C5=EAEA,15D4=EAEA,695E=EAEA,69D8=EAEA,6C5F=EAEA,4003C=EAEA,40046=EAEA,40056=EAEA,40070=EAEA,4009A=EAEA,400A8=EAEA,400B3=EAEA,400C4=EAEA,400DE=EAEA,400FC=EAEA,40117=EAEA,40144=EAEA,40164=EAEA,4016B=EAEA,4017F=EAEA,401B8=EAEA,401C5=EAEA,401CF=EAEA,401DF=EAEA,401F1=EAEA,4020D=EAEA,49C8F=EAEA,5004B=EAEA,50055=EAEA,50065=EAEA,5007F=EAEA,500B7=EAEA,500D1=EAEA,500E6=EAEA,50105=EAEA,5011B=EAEA,5017D=EAEA,50187=EAEA,50197=EAEA,501B1=EAEA,501BA=EAEA,501CB=EAEA,501DD=EAEA,501EA=EAEA,5023B=EAEA,50245=EAEA,50255=EAEA,5026F=EAEA,50289=EAEA,50298=EAEA,95CD3=EAEA,A8655=EAEA,B7A03=EAEA,BBE13=EAEA,DCCB1=EAEA +1703D522|Wizardry Gaiden IV - Taima no K|4|40040800|0|0|0|0|B0726=EAEA,B05C8=EAEA,523=42DC,B071F=42,60=4283 +13BFB3A0|Wolfchild (U)|4000000|804|0|0|0|0|F8099=EAEA,F8146=EAEA,F811B=EAEA,F815E=EAEA,F809E=EAEA,5F8=42FC,614=42FC +36079184|Wonder Project J [T+Eng1.04]|5|0|0|0|0|0|AB80=EAEA,2E4A2=EAEA,2E4A8=EAEA,2E4BB=EAEA,2E4BF=EAEA,8420=42DB +90D0FAC0|Worms (E)|10000002|0|0|0|0|0|150085=EAEA,150178=EAEA,19C3B7=EAEA,1B5A=423A,1B60=421A,7627=DB,794E=423A,7BD1=42D8,1B1013=DB +4F02A304|X-Men Mutant Apocalypse (J)|4000001|44000|0|0|0|0|AB=42FB +5E34822A|X-Men Mutant Apocalypse (U)|4000001|44800|0|0|0|0|AB=42FB +C7C12A57|Xardion|4|0|D02|0|1E|5|5E90=421B,5E9E=421B,5E82=421B +7448D45C|Yogi Bear (U)|0|0|0|0|0|0|1ED=EAEA,74C=EAEA,856=EAEA,1137=EAEA,1DB6=EAEA,1EFC=EAEA,1FAD=EAEA,279E=EAEA,57FA=EAEA,5849=EAEA,5861=EAEA,586C=EAEA,5871=EAEA,601BD=EAEA,E84A7=EAEA +EF15F4C3|Yoshi's Cookie (U)|0|0|0|0|0|0|2824F=421B +D138F224|Yoshi's Island (V1.0) (U)|0|0|0|0|0|0|F4=423B +CF98DDAA|Yoshi's Island (U) (M3) (V1.1)|F4=423B +59490CE8|Yoshi's Safari|0|0|0|0|0|0 +7EA1AFE8|Young Merlin|0|0|0|0|0|0 +64A91E64|Ys 3 - Wanderers from Ys|0|0|0|0|0|0|D8=42 +1ADD47F0|Ys 4 - Mask of the Sun (J) [T-E|4|0|0|0|0|0|14060C=EAEA,140631=EAEA,9CA=42DC,A3B=42DC +7B4CEBAF|Ys 4 - Mask of the Sun (J) [T-E|4|0|0|0|0|14060C|14060C=EAEA,140631=EAEA,9CA=42DC,A3B=42DC +CFE632B9|Ys V - Expert (J)|4|44800|0|0|0|0|886=EAEA,79D=EAEA,3B81=EAEA,86C=EAEA,5E06=42FB,A9C=42FB,5DCC=42DB +EC96D517|YUUYUU Hakusho (J)|0|0|0|0|0|0|E15=42FC +EEF45A93|YUUYUU Hakusho 2 - Kakutou no S|0|0|0|0|0|0|10F=42DC +5617A42E|YUUYUU Hakusho Final (J)|1|0|0|0|0|0|A71D=EAEA,A683=EAEA,AB=42DC +535CCCAC|YUUYUU Hakusho Tokubehuten (J)|0|0|0|0|0|0|7957=EAEA,781A=EAEA +5409D4F4|Zen Nihon GT Sensyuken (J)|1320000|0|0|0|0|0|8003B=EAEA,8012B=EAEA,80137=EAEA,15E=42FB +5397D5BC|Zero the Kamikaze Squirrel (U)|0|0|0|0|0|0|41B44=EAEA,41B69=EAEA,1F3=42DB,12EA=4214,2884A=42DB,496=421B,41F=421B +7CFC0C7C|Zombies Ate My Neighbors (U)|10000000|4040|0|0|0|0|4CCF=EAEA,9DC=42 diff --git a/src/rel/warm_2.6.24.ko b/src/rel/warm_2.6.24.ko new file mode 100644 index 0000000..d2b8dc4 Binary files /dev/null and b/src/rel/warm_2.6.24.ko differ diff --git a/src/render8 orr.S b/src/render8 orr.S new file mode 100644 index 0000000..aaff045 --- /dev/null +++ b/src/render8 orr.S @@ -0,0 +1,218 @@ + .global asmDrawTile8_noflip + .global asmDrawTile8_hflip + .global asmDrawTile8_hvflip + .global asmDrawTile8_vflip + .global asmDrawTile8T_noflip + .global asmDrawTile8T_hflip + .global asmDrawTile8T_hvflip + .global asmDrawTile8T_vflip + + ;@ ############################### + .macro DRAWTILE_NOFLIP + ;@ ############################### + ldr r3,[r0],#4 + + ands r12,r3,#0x0000000F + orrne r12,r1,r12 + strneb r12,[r2,#0] + + ands r12,r3,#0x000000F0 + orrne r12,r1,r12,lsr#4 + strneb r12,[r2,#1] + + ands r12,r3,#0x00000F00 + orrne r12,r1,r12,lsr#8 + strneb r12,[r2,#2] + + ands r12,r3,#0x0000F000 + orrne r12,r1,r12,lsr#12 + strneb r12,[r2,#3] + + ands r12,r3,#0x000F0000 + orrne r12,r1,r12,lsr#16 + strneb r12,[r2,#4] + + ands r12,r3,#0x00F00000 + orrne r12,r1,r12,lsr#20 + strneb r12,[r2,#5] + + ands r12,r3,#0x0F000000 + orrne r12,r1,r12,lsr#24 + strneb r12,[r2,#6] + + ands r12,r3,#0xF0000000 + orrne r12,r1,r12,lsr#28 + strneb r12,[r2,#7] + + add r2,r2,#320 + .endm + + ;@ ############################### + .macro DRAWTILE_HFLIP + ;@ ############################### + ldr r3,[r0],#4 + + ands r12,r3,#0x0000000F + orrne r12,r1,r12 + strneb r12,[r2,#7] + + ands r12,r3,#0x000000F0 + orrne r12,r1,r12,lsr#4 + strneb r12,[r2,#6] + + ands r12,r3,#0x00000F00 + orrne r12,r1,r12,lsr#8 + strneb r12,[r2,#5] + + ands r12,r3,#0x0000F000 + orrne r12,r1,r12,lsr#12 + strneb r12,[r2,#4] + + ands r12,r3,#0x000F0000 + orrne r12,r1,r12,lsr#16 + strneb r12,[r2,#3] + + ands r12,r3,#0x00F00000 + orrne r12,r1,r12,lsr#20 + strneb r12,[r2,#2] + + ands r12,r3,#0x0F000000 + orrne r12,r1,r12,lsr#24 + strneb r12,[r2,#1] + + ands r12,r3,#0xF0000000 + orrne r12,r1,r12,lsr#28 + strneb r12,[r2,#0] + + add r2,r2,#320 + .endm + + ;@ ############################### + .macro DRAWTILE_HVFLIP + ;@ ############################### + ldr r3,[r0],#4 + + ands r12,r3,#0x0000000F + orrne r12,r1,r12 + strneb r12,[r2,#7] + + ands r12,r3,#0x000000F0 + orrne r12,r1,r12,lsr#4 + strneb r12,[r2,#6] + + ands r12,r3,#0x00000F00 + orrne r12,r1,r12,lsr#8 + strneb r12,[r2,#5] + + ands r12,r3,#0x0000F000 + orrne r12,r1,r12,lsr#12 + strneb r12,[r2,#4] + + ands r12,r3,#0x000F0000 + orrne r12,r1,r12,lsr#16 + strneb r12,[r2,#3] + + ands r12,r3,#0x00F00000 + orrne r12,r1,r12,lsr#20 + strneb r12,[r2,#2] + + ands r12,r3,#0x0F000000 + orrne r12,r1,r12,lsr#24 + strneb r12,[r2,#1] + + ands r12,r3,#0xF0000000 + orrne r12,r1,r12,lsr#28 + strneb r12,[r2,#0] + + sub r2,r2,#320 + .endm + + ;@ ############################### + .macro DRAWTILE_VFLIP + ;@ ############################### + ldr r3,[r0],#4 + + ands r12,r3,#0x0000000F + orrne r12,r1,r12 + strneb r12,[r2,#0] + + ands r12,r3,#0x000000F0 + orrne r12,r1,r12,lsr#4 + strneb r12,[r2,#1] + + ands r12,r3,#0x00000F00 + orrne r12,r1,r12,lsr#8 + strneb r12,[r2,#2] + + ands r12,r3,#0x0000F000 + orrne r12,r1,r12,lsr#12 + strneb r12,[r2,#3] + + ands r12,r3,#0x000F0000 + orrne r12,r1,r12,lsr#16 + strneb r12,[r2,#4] + + ands r12,r3,#0x00F00000 + orrne r12,r1,r12,lsr#20 + strneb r12,[r2,#5] + + ands r12,r3,#0x0F000000 + orrne r12,r1,r12,lsr#24 + strneb r12,[r2,#6] + + ands r12,r3,#0xF0000000 + orrne r12,r1,r12,lsr#28 + strneb r12,[r2,#7] + + sub r2,r2,#320 + .endm + + +asmDrawTile8_noflip: + DRAWTILE_NOFLIP + DRAWTILE_NOFLIP + DRAWTILE_NOFLIP + DRAWTILE_NOFLIP + DRAWTILE_NOFLIP + DRAWTILE_NOFLIP + DRAWTILE_NOFLIP + DRAWTILE_NOFLIP + mov pc,lr + +asmDrawTile8_hflip: + DRAWTILE_HFLIP + DRAWTILE_HFLIP + DRAWTILE_HFLIP + DRAWTILE_HFLIP + DRAWTILE_HFLIP + DRAWTILE_HFLIP + DRAWTILE_HFLIP + DRAWTILE_HFLIP + mov pc,lr + +asmDrawTile8_hvflip: + DRAWTILE_HVFLIP + DRAWTILE_HVFLIP + DRAWTILE_HVFLIP + DRAWTILE_HVFLIP + DRAWTILE_HVFLIP + DRAWTILE_HVFLIP + DRAWTILE_HVFLIP + DRAWTILE_HVFLIP + mov pc,lr + +asmDrawTile8_vflip: + DRAWTILE_VFLIP + DRAWTILE_VFLIP + DRAWTILE_VFLIP + DRAWTILE_VFLIP + DRAWTILE_VFLIP + DRAWTILE_VFLIP + DRAWTILE_VFLIP + DRAWTILE_VFLIP + mov pc,lr + + + + + diff --git a/src/resource.h b/src/resource.h new file mode 100644 index 0000000..34fc53a --- /dev/null +++ b/src/resource.h @@ -0,0 +1,181 @@ +//{{NO_DEPENDENCIES}} +// Microsoft Developer Studio generated include file. +// Used by PocketSNES.rc +// +#define IDS_APP_TITLE 1 +#define IDS_HELLO 2 +#define IDC_POCKETSNES 3 +#define IDS_HELLO2 4 +#define IDS_PAUSED 5 +#define IDS_LINK 6 +#define IDS_CREDITS1 7 +#define IDS_CREDITS2 8 +#define IDS_CREDITS0 9 +#define IDI_POCKETSNES 101 +#define IDM_MENU 102 +#define IDS_HELP 104 +#define IDD_OPTIONS 104 +#define IDB_KEYPAD 105 +#define IDD_SKINS 106 +#define IDD_KEYS 107 +#define IDD_KEYS1 108 +#define IDD_CREDITS 108 +#define IDD_KEYS_NEW 109 +#define IDD_DISPLAY 109 +#define IDD_SOUND 110 +#define IDD_SETTINGS 111 +#define IDD_SYSTEM 111 +#define IDB_POCKETSNES 114 +#define IDB_6BUTTON 115 +#define IDB_4BUTTON 118 +#define IDI_LEFT_ARROW 119 +#define IDI_RIGHT_ARROW 120 +#define IDS_COMMAND1 301 +#define IDC_STATIC_TITLE 444 +#define IDC_STATIC_TITLE2 445 +#define IDC_TRANSPARENCY 1001 +#define IDC_SOUND 1002 +#define IDC_ECHO 1003 +#define IDC_SYNC 1004 +#define IDC_SYNCSOUND 1004 +#define IDC_CUSTOM1 1005 +#define IDC_REVERSE 1005 +#define IDC_REVERSESTEREO 1005 +#define IDC_STEREO 1006 +#define IDC_BUTTON_PREVIOUS 1007 +#define IDC_INTERPOLATE 1007 +#define IDC_INTERPOLATESOUND 1007 +#define IDC_BUTTON_SET 1008 +#define IDC_ALTDECODE 1008 +#define IDC_BUTTON_NEXT 1009 +#define IDC_ENVELOPEHEIGHT 1009 +#define IDC_SMOOTHSTRETCH 1010 +#define IDC_FIXFREQUENCY 1010 +#define IDC_LANDSCAPE 1011 +#define IDC_BUTTON_UP 1028 +#define IDC_BUTTON_DOWN 1029 +#define IDC_BUTTON_LEFT 1030 +#define IDC_BUTTON_RIGHT 1031 +#define IDC_BUTTON_B 1032 +#define IDC_BUTTON_A 1033 +#define IDC_BUTTON_Y 1034 +#define IDC_BUTTON_X 1035 +#define IDC_BUTTON_START 1036 +#define IDC_BUTTON_SELECT 1037 +#define IDC_BUTTON_L 1038 +#define IDC_BUTTON_R 1039 +#define IDC_STATIC_UP 1040 +#define IDC_STATIC_LEFT 1041 +#define IDC_STATIC_B 1042 +#define IDC_STATIC_Y 1043 +#define IDC_STATIC_START 1044 +#define IDC_STATIC_L 1045 +#define IDC_STATIC_DOWN 1046 +#define IDC_STATIC_RIGHT 1047 +#define IDC_STATIC_A 1048 +#define IDC_STATIC_X 1049 +#define IDC_STATIC_SELECT 1050 +#define IDC_STATIC_R 1051 +#define IDC_STATIC_INFO 1052 +#define IDC_FRAMESKIP 1053 +#define IDC_SPIN_FRAMESKIP 1055 +#define IDC_CREDITS 1056 +#define IDC_SIXTEENBIT 1059 +#define IDC_EIGHTBIT 1060 +#define IDC_SOUNDQUALITY 1061 +#define IDC_LEFT 1063 +#define IDC_AUTO 1065 +#define IDC_COMPAT 1066 +#define IDC_CYCLES 1067 +#define IDC_CYCLES_SPIN 1068 +#define IDC_PORTRAIT 1069 +#define IDC_LANDLEFT 1070 +#define IDC_LANDLEFTSTRETCH 1071 +#define IDC_LANDRIGHTSTRETCH 1072 +#define IDC_LANDRIGHT 1073 +#define IDC_SLIDER1 1074 +#define IDC_FRAMESKIP_SLIDER 1074 +#define IDC_SKIP 1075 +#define IDC_EDIT1 1076 +#define IDC_BROWSE 1077 +#define IDC_STARTLOADSTATE 1078 +#define IDC_RESUMEAFTERLOADSTATE 1078 +#define IDC_STARTSAVESTATE 1079 +#define IDC_RESUMEAFTERSAVESTATE 1079 +#define IDC_DISPLAYFRAMERATE 1080 +#define IDC_SOUNDQUALITYTEXTBOX 1081 +#define IDC_USEFOLDER 1081 +#define IDM_MAIN_COMMAND1 40001 +#define IDM_HELP_ABOUT 40003 +#define IDM_FILE_LOAD 40004 +#define IDM_TOOLS_LOAD 40004 +#define ID_HELP 40005 +#define IDS_CAP_HELP 40007 +#define IDM_TOOLS_EXIT 40008 +#define IDS_CAP_OPTIONS 40008 +#define IDM_TOOLS_OPTIONS 40009 +#define IDM_OPTIONS_SETTINGS 40009 +#define IDM_TOOLS_SKINS 40010 +#define ID_OPTIONS 40011 +#define IDM_OPTIONS_KEYS 40013 +#define IDM_TOOLS_CREDITS 40014 +#define IDM_TOOLS_LOADSTATE 40015 +#define IDM_TOOLS_SAVESTATE 40016 +#define IDM_OPTIONS_DISPLAY 40017 +#define IDM_OPTIONS_SOUND 40018 +#define IDM_BLANK 40020 +#define IDM_OPTIONS_RESET 40022 +#define IDM_TOOLS_RESET 40022 +#define IDM_LOAD1 40023 +#define IDM_TOOLS_LOAD1 40023 +#define IDM_LOAD2 40024 +#define IDM_TOOLS_LOAD2 40024 +#define IDM_LOAD3 40025 +#define IDM_TOOLS_LOAD3 40025 +#define IDM_LOAD4 40026 +#define IDM_TOOLS_LOAD4 40026 +#define IDM_LOAD5 40027 +#define IDM_TOOLS_LOAD5 40027 +#define IDM_HELP 40029 +#define IDM_SAVE1 40031 +#define IDM_TOOLS_SAVE1 40031 +#define IDM_SAVE2 40032 +#define IDM_TOOLS_SAVE2 40032 +#define IDM_SAVE3 40033 +#define IDM_TOOLS_SAVE3 40033 +#define IDM_SAVE4 40034 +#define IDM_LOAD6 40035 +#define IDM_TOOLS_LOAD6 40035 +#define IDM_LOAD7 40036 +#define IDM_TOOLS_LOAD7 40036 +#define IDM_LOAD8 40037 +#define IDM_SAVE6 40038 +#define IDM_TOOLS_SAVE6 40038 +#define IDM_SAVE7 40039 +#define IDM_TOOLS_SAVE7 40039 +#define IDM_SAVE8 40040 +#define IDM_TOOLS_SAVE8 40040 +#define IDM_SAVE9 40041 +#define IDM_TOOLS_SAVE9 40041 +#define IDM_TOOLS_SAVE4 40042 +#define IDM_TOOLS_SAVE5 40043 +#define IDM_TOOLS_RECENT1 40044 +#define IDM_TOOLS_LOAD8 40045 +#define IDM_TOOLS_LOAD9 40046 +#define ID_OPTIONS_SYSTEM 40049 +#define IDM_OPTIONS_SYSTEM 40049 +#define IDM_CHEAT 40050 +#define IDS_CAP_CHEAT 40052 +#define IDM_NETPLAY 40053 +#define IDS_CAP_NETPLAY 40055 + +// Next default values for new objects +// +#ifdef APSTUDIO_INVOKED +#ifndef APSTUDIO_READONLY_SYMBOLS +#define _APS_NEXT_RESOURCE_VALUE 143 +#define _APS_NEXT_COMMAND_VALUE 40056 +#define _APS_NEXT_CONTROL_VALUE 1082 +#define _APS_NEXT_SYMED_VALUE 101 +#endif +#endif diff --git a/src/rops.cpp b/src/rops.cpp new file mode 100644 index 0000000..8628ccd --- /dev/null +++ b/src/rops.cpp @@ -0,0 +1,275 @@ +#include "snes9x.h" +#include "ppu.h" +#include "rops.h" + +ROPSTRUCT rops[MAX_ROPS]; +unsigned int ROpCount; + +//#define __DEBUG__ + +#ifdef __DEBUG__ +static char *rasterNames[] = { + "ROP_NOP", + "ROP_FIXEDCOLOUR", + "ROP_PALETTE", + "ROP_SCREEN_MODE", + "ROP_BRIGHTNESS", + "ROP_FORCE_BLANKING", + "ROP_TILE_ADDRESS", + "ROP_MOSAIC", + "ROP_BG_SCSIZE_SCBASE", + "ROP_BG_NAMEBASE", + "ROP_MODE7_ROTATION", + "ROP_BG_WINDOW_ENABLE", + "ROP_WINDOW1_LEFT", + "ROP_WINDOW1_RIGHT", + "ROP_WINDOW2_LEFT", + "ROP_WINDOW2_RIGHT", + "ROP_BG_WINDOW_LOGIC", + "ROP_OBJS_WINDOW_LOGIC", + "ROP_MAIN_SCREEN_DESIG", + "ROP_SUB_SCREEN_DESIG", + "ROP_MAIN_SCREEN_WMASK", + "ROP_SUB_SCREEN_WMASK", + "ROP_FIXEDCOL_OR_SCREEN", + "ROP_ADD_OR_SUB_COLOR" + }; +#endif + +void doRaster(ROPSTRUCT *rop) { + if (!rop) return; +#ifdef __DEBUG__ + printf("%s, line: %d, value: %x\n", rasterNames[rop->rop], rop->line, rop->value); +#endif + switch (rop->rop) { + case ROP_NOP: + // NOP + break; + case ROP_FIXEDCOLOUR: + { + unsigned char col = rop->value & 0x1f; + // Colour data for fixed colour addition/subtraction + if (rop->value & 0x80) PPU.FixedColourBlue = col; + if (rop->value & 0x40) PPU.FixedColourGreen = col; + if (rop->value & 0x20) PPU.FixedColourRed = col; + } + break; + case ROP_PALETTE: + { + // Pallette, colors + unsigned char col = rop->value & 255; + IPPU.Blue[col] = (rop->value >> (16 + 10)) & 0x1f; + IPPU.Green[col] = (rop->value >> (16 + 5)) & 0x1f; + IPPU.Red[col] = (rop->value >> (16 + 0)) & 0x1f; + IPPU.ScreenColors[col] = (uint16) BUILD_PIXEL (IPPU.XB[IPPU.Red[col]], IPPU.XB[IPPU.Green[col]], IPPU.XB[IPPU.Blue[col]]); + IPPU.ColorsChanged = TRUE; + } + break; + case ROP_SCREEN_MODE: + // Screen mode (0 - 7), background tile sizes and background 3 priority + PPU.BG[0].BGSize = (rop->value >> 4) & 1; + PPU.BG[1].BGSize = (rop->value >> 5) & 1; + PPU.BG[2].BGSize = (rop->value >> 6) & 1; + PPU.BG[3].BGSize = (rop->value >> 7) & 1; + PPU.BGMode = rop->value & 7; + // BJ: BG3Priority only takes effect if BGMode==1 and the bit is set + PPU.BG3Priority = ((rop->value & 0x0f) == 0x09); + break; + case ROP_BRIGHTNESS: + PPU.Brightness = rop->value; + S9xFixColourBrightness(); + if (PPU.Brightness > IPPU.MaxBrightness) IPPU.MaxBrightness = PPU.Brightness; + IPPU.ColorsChanged = TRUE; + IPPU.DirectColourMapsNeedRebuild = TRUE; + break; + case ROP_FORCE_BLANKING: + PPU.ForcedBlanking = rop->value; + IPPU.ColorsChanged = TRUE; + break; + case ROP_TILE_ADDRESS: + PPU.OBJNameBase = (rop->value & 3) << 14; + PPU.OBJNameSelect = ((rop->value >> 3) & 3) << 13; + PPU.OBJSizeSelect = (rop->value >> 5) & 7; + IPPU.OBJChanged = TRUE; + break; + case ROP_MOSAIC: + PPU.Mosaic = (rop->value >> 4) + 1; + PPU.BGMosaic[0] = (rop->value & 1) && PPU.Mosaic > 1; + PPU.BGMosaic[1] = (rop->value & 2) && PPU.Mosaic > 1; + PPU.BGMosaic[2] = (rop->value & 4) && PPU.Mosaic > 1; + PPU.BGMosaic[3] = (rop->value & 8) && PPU.Mosaic > 1; + break; + case ROP_BG_SCSIZE_SCBASE: + PPU.BG[rop->value >> 16].SCSize = rop->value & 3; + PPU.BG[rop->value >> 16].SCBase = (rop->value & 0x7c) << 8; + break; + case ROP_BG_NAMEBASE: + PPU.BG[(rop->value >> 16) + 0].NameBase = (rop->value & 7) << 12; + PPU.BG[(rop->value >> 16) + 1].NameBase = ((rop->value >> 4) & 7) << 12; + break; + case ROP_MODE7_ROTATION: + PPU.Mode7Repeat = rop->value >> 6; + if (PPU.Mode7Repeat == 1) PPU.Mode7Repeat = 0; + PPU.Mode7VFlip = (rop->value & 2) >> 1; + PPU.Mode7HFlip = rop->value & 1; + break; + case ROP_BG_WINDOW_ENABLE: + PPU.ClipWindow1Enable[(rop->value >> 16) + 0] = !!(rop->value & 0x02); + PPU.ClipWindow1Enable[(rop->value >> 16) + 1] = !!(rop->value & 0x20); + PPU.ClipWindow2Enable[(rop->value >> 16) + 0] = !!(rop->value & 0x08); + PPU.ClipWindow2Enable[(rop->value >> 16) + 1] = !!(rop->value & 0x80); + PPU.ClipWindow1Inside[(rop->value >> 16) + 0] = !(rop->value & 0x01); + PPU.ClipWindow1Inside[(rop->value >> 16) + 1] = !(rop->value & 0x10); + PPU.ClipWindow2Inside[(rop->value >> 16) + 0] = !(rop->value & 0x04); + PPU.ClipWindow2Inside[(rop->value >> 16) + 1] = !(rop->value & 0x40); + PPU.RecomputeClipWindows = TRUE; + break; + case ROP_WINDOW1_LEFT: + PPU.Window1Left = rop->value; + PPU.RecomputeClipWindows = TRUE; + break; + case ROP_WINDOW1_RIGHT: + PPU.Window1Right = rop->value; + PPU.RecomputeClipWindows = TRUE; + break; + case ROP_WINDOW2_LEFT: + PPU.Window2Left = rop->value; + PPU.RecomputeClipWindows = TRUE; + break; + case ROP_WINDOW2_RIGHT: + PPU.Window2Right = rop->value; + PPU.RecomputeClipWindows = TRUE; + break; + case ROP_BG_WINDOW_LOGIC: + PPU.ClipWindowOverlapLogic[0] = (rop->value & 0x03); + PPU.ClipWindowOverlapLogic[1] = (rop->value & 0x0c) >> 2; + PPU.ClipWindowOverlapLogic[2] = (rop->value & 0x30) >> 4; + PPU.ClipWindowOverlapLogic[3] = (rop->value & 0xc0) >> 6; + PPU.RecomputeClipWindows = TRUE; + break; + case ROP_OBJS_WINDOW_LOGIC: + PPU.ClipWindowOverlapLogic[4] = (rop->value & 0x03); + PPU.ClipWindowOverlapLogic[5] = (rop->value & 0x0c) >> 2; + PPU.RecomputeClipWindows = TRUE; + break; + case ROP_MAIN_SCREEN_DESIG: + // Main screen designation (backgrounds 1 - 4 and objects) + if ((GFX.r212c_s & GFX.r212e_s & 0x1f) != (GFX.r212e_s & rop->value & 0x1f)) PPU.RecomputeClipWindows = TRUE; + GFX.r212c_s = rop->value; + break; + case ROP_SUB_SCREEN_DESIG: + // Sub-screen designation (backgrounds 1 - 4 and objects) + if ((GFX.r212d_s & GFX.r212f_s & 0x1f) != (GFX.r212f_s & rop->value & 0x1f)) PPU.RecomputeClipWindows = TRUE; + GFX.r212d_s = rop->value; + break; + case ROP_MAIN_SCREEN_WMASK: + // Window mask designation for main screen ? + if ((GFX.r212c_s & GFX.r212e_s & 0x1f) != (GFX.r212c_s & rop->value & 0x1f)) PPU.RecomputeClipWindows = TRUE; + GFX.r212e_s = rop->value; + break; + case ROP_SUB_SCREEN_WMASK: + // Window mask designation for sub-sreen ? + if ((GFX.r212d_s & GFX.r212f_s & 0x1f) != (GFX.r212d_s & rop->value & 0x1f)) PPU.RecomputeClipWindows = TRUE; + GFX.r212f_s = rop->value; + break; + case ROP_FIXEDCOL_OR_SCREEN: + // Fixed colour addition or screen addition + if ((GFX.r2130_s & 0xf0) != (rop->value & 0xf0)) PPU.RecomputeClipWindows = TRUE; + GFX.r2130_s = rop->value; + break; + case ROP_ADD_OR_SUB_COLOR: + // Backgrounds 1 - 4, objects and backdrop colour add/sub enable + GFX.r2131_s = rop->value; + break; + } +#ifdef __DEBUG__ + printf("ROP OK\n"); +#endif + rop->rop = 0; // Raster Operation already done, invalidate it +} + +bool wouldRasterAlterStatus(ROPSTRUCT *rop) { + if (!rop) return false; + switch (rop->rop) { + case ROP_NOP: + return false; + break; + case ROP_FIXEDCOLOUR: + { + unsigned char col = rop->value & 0x1f; + // Colour data for fixed colour addition/subtraction + if ((rop->value & 0x80) && (PPU.FixedColourBlue != col)) return true; + if ((rop->value & 0x40) && (PPU.FixedColourGreen != col)) return true; + if ((rop->value & 0x20) && (PPU.FixedColourRed != col)) return true; + return false; + } + break; + case ROP_PALETTE: + return true; + break; + case ROP_SCREEN_MODE: + return true; + break; + case ROP_BRIGHTNESS: + return true; + break; + case ROP_FORCE_BLANKING: + return true; + break; + case ROP_TILE_ADDRESS: + return true; + break; + case ROP_MOSAIC: + return true; + break; + case ROP_BG_SCSIZE_SCBASE: + return true; + break; + case ROP_BG_NAMEBASE: + return true; + break; + case ROP_MODE7_ROTATION: + return true; + break; + case ROP_BG_WINDOW_ENABLE: + return true; + break; + case ROP_WINDOW1_LEFT: + return true; + break; + case ROP_WINDOW1_RIGHT: + return true; + break; + case ROP_WINDOW2_LEFT: + return true; + break; + case ROP_WINDOW2_RIGHT: + return true; + break; + case ROP_BG_WINDOW_LOGIC: + return true; + break; + case ROP_OBJS_WINDOW_LOGIC: + return true; + break; + case ROP_MAIN_SCREEN_DESIG: + return true; + break; + case ROP_SUB_SCREEN_DESIG: + return true; + break; + case ROP_MAIN_SCREEN_WMASK: + return true; + break; + case ROP_SUB_SCREEN_WMASK: + return true; + break; + case ROP_FIXEDCOL_OR_SCREEN: + return true; + break; + case ROP_ADD_OR_SUB_COLOR: + return true; + break; + } + return true; +} diff --git a/src/rops.h b/src/rops.h new file mode 100644 index 0000000..e751a58 --- /dev/null +++ b/src/rops.h @@ -0,0 +1,168 @@ +#ifndef __ROPS_H__ +#define __ROPS_H__ + +/* + Raster Operations macros +*/ + +// ------------- +// RGB_565 +// a.red = a.red - b.red +// a.blue = a.blue - b.blue +// a.green = a.green - b.green +/* +#define ROP_SUB(a, b) \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b10000000000000000 \n"\ + " sub " #a ", " #a ", " #b " \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " biceq " #a ", " #a ", #0b01111100000000000 \n" +*/ +#define ROP_SUB(a, b) \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " beq 999f \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #(1 << 31) \n"\ + " subs " #a ", " #a ", " #b " \n"\ + " bicpl " #a ", " #a ", #0b01111100000000000 \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + "999:\n" + + +// ------------- +// RGB_565 +// if ZF set do ROP_SUB, else: +// a.red = (a.red - b.red) / 2 +// a.blue = (a.blue - b.blue) / 2 +// a.green = (a.green - b.green) / 2 +/* +#define ROP_SUB1_2(a, b) \ + " movne " #a ", " #a ", lsr #1 \n"\ + " bicne " #a ", " #a ", #0b00000010000010000 \n"\ + " movne " #b ", " #b ", lsr #1 \n"\ + " bicne " #b ", " #b ", #0b00000010000010000 \n"\ + \ + " bic " #b ", " #b ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b10000000000000000 \n"\ + " sub " #a ", " #a ", " #b " \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " biceq " #a ", " #a ", #0b01111100000000000 \n" +*/ + +#define ROP_SUB1_2(a, b) \ + " movne " #a ", " #a ", lsr #1 \n"\ + " bicne " #a ", " #a ", #0b00000010000010000 \n"\ + " movne " #b ", " #b ", lsr #1 \n"\ + " bicne " #b ", " #b ", #0b00000010000010000 \n"\ + \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " beq 999f \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #(1 << 31) \n"\ + " subs " #a ", " #a ", " #b " \n"\ + " bicpl " #a ", " #a ", #0b01111100000000000 \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + "999:\n" + + +// ------------- +// RGB_565 +// a.red = a.red + b.red +// a.blue = a.blue + b.blue +// a.green = a.green + b.green +#define ROP_ADD(a, b) \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " beq 999f \n"\ + " bic " #a ", " #a ", #0b00000100000100000 \n"\ + " add " #a ", " #a ", " #b " \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " orrne " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " orrne " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " orrne " #a ", " #a ", #0b01111100000000000 \n"\ + "999:\n" + +// ------------- +// RGB_565 +// if ZF set do ROP_ADD, else: +// a.red = (a.red + b.red) / 2 +// a.blue = (a.blue + b.blue) / 2 +// a.green = (a.green + b.green) / 2 +#define ROP_ADD1_2(a, b) \ + " bic " #a ", " #a ", #0b00000100000100000 \n"\ + " bicne " #a ", " #a ", #0b00001000001000000 \n"\ + " bic " #b ", " #b ", #0b00000100000100000 \n"\ + " bicne " #b ", " #b ", #0b00001000001000000 \n"\ + " add " #a ", " #a ", " #b " \n"\ + " movne " #a ", " #a ", lsr #1 \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " orrne " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " orrne " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " orrne " #a ", " #a ", #0b01111100000000000 \n" + + +typedef struct { + unsigned char line; + unsigned char rop; + unsigned int value; +} ROPSTRUCT; + +#define MAX_ROPS 0x10000 +extern ROPSTRUCT rops[MAX_ROPS]; +extern unsigned int ROpCount; + +#define ROP_NOP 0 +#define ROP_FIXEDCOLOUR 1 +#define ROP_PALETTE 2 +#define ROP_SCREEN_MODE 3 +#define ROP_BRIGHTNESS 4 +#define ROP_FORCE_BLANKING 5 +#define ROP_TILE_ADDRESS 6 +#define ROP_MOSAIC 7 +#define ROP_BG_SCSIZE_SCBASE 8 +#define ROP_BG_NAMEBASE 9 +#define ROP_MODE7_ROTATION 10 +#define ROP_BG_WINDOW_ENABLE 11 +#define ROP_WINDOW1_LEFT 12 +#define ROP_WINDOW1_RIGHT 13 +#define ROP_WINDOW2_LEFT 14 +#define ROP_WINDOW2_RIGHT 15 +#define ROP_BG_WINDOW_LOGIC 16 +#define ROP_OBJS_WINDOW_LOGIC 17 +#define ROP_MAIN_SCREEN_DESIG 18 +#define ROP_SUB_SCREEN_DESIG 19 +#define ROP_MAIN_SCREEN_WMASK 20 +#define ROP_SUB_SCREEN_WMASK 21 +#define ROP_FIXEDCOL_OR_SCREEN 22 +#define ROP_ADD_OR_SUB_COLOR 23 + +#define ADD_ROP(drop, dval) {rops[ROpCount].line = IPPU.CurrentLine; rops[ROpCount].rop = drop; rops[ROpCount].value = dval; ROpCount++;} +#define RESET_ROPS(from) \ + { \ + for (unsigned int c = from; c < ROpCount; c++) doRaster(&rops[c]);\ + ROpCount = 0;\ + } + +void doRaster(ROPSTRUCT *rop); +bool wouldRasterAlterStatus(ROPSTRUCT *rop); + +#endif diff --git a/src/rops.h.last b/src/rops.h.last new file mode 100644 index 0000000..5ec3e24 --- /dev/null +++ b/src/rops.h.last @@ -0,0 +1,118 @@ +/* + Raster Operations macros +*/ + +// ------------- +// RGB_565 +// a.red = a.red - b.red +// a.blue = a.blue - b.blue +// a.green = a.green - b.green +/* +#define ROP_SUB(a, b) \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b10000000000000000 \n"\ + " sub " #a ", " #a ", " #b " \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " biceq " #a ", " #a ", #0b01111100000000000 \n" +*/ +#define ROP_SUB(a, b) \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " beq 999f \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #(1 << 31) \n"\ + " subs " #a ", " #a ", " #b " \n"\ + " bicpl " #a ", " #a ", #0b01111100000000000 \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + "999:\n" + + +// ------------- +// RGB_565 +// if ZF set do ROP_SUB, else: +// a.red = (a.red - b.red) / 2 +// a.blue = (a.blue - b.blue) / 2 +// a.green = (a.green - b.green) / 2 +/* +#define ROP_SUB1_2(a, b) \ + " movne " #a ", " #a ", lsr #1 \n"\ + " bicne " #a ", " #a ", #0b00000010000010000 \n"\ + " movne " #b ", " #b ", lsr #1 \n"\ + " bicne " #b ", " #b ", #0b00000010000010000 \n"\ + \ + " bic " #b ", " #b ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b10000000000000000 \n"\ + " sub " #a ", " #a ", " #b " \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " biceq " #a ", " #a ", #0b01111100000000000 \n" +*/ + +#define ROP_SUB1_2(a, b) \ + " movne " #a ", " #a ", lsr #1 \n"\ + " bicne " #a ", " #a ", #0b00000010000010000 \n"\ + " movne " #b ", " #b ", lsr #1 \n"\ + " bicne " #b ", " #b ", #0b00000010000010000 \n"\ + \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " beq 999f \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #(1 << 31) \n"\ + " subs " #a ", " #a ", " #b " \n"\ + " bicpl " #a ", " #a ", #0b01111100000000000 \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + "999:\n" + + +// ------------- +// RGB_565 +// a.red = a.red + b.red +// a.blue = a.blue + b.blue +// a.green = a.green + b.green +#define ROP_ADD(a, b) \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " beq 999f \n"\ + " bics " #a ", " #a ", #0b00000100000100000 \n"\ + " add " #a ", " #a ", " #b " \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " orrne " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " orrne " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " orrne " #a ", " #a ", #0b01111100000000000 \n"\ + "999:\n" + +// ------------- +// RGB_565 +// if ZF set do ROP_ADD, else: +// a.red = (a.red + b.red) / 2 +// a.blue = (a.blue + b.blue) / 2 +// a.green = (a.green + b.green) / 2 +#define ROP_ADD1_2(a, b) \ + " bic " #a ", " #a ", #0b00000100000100000 \n"\ + " bicne " #a ", " #a ", #0b00001000001000000 \n"\ + " bic " #b ", " #b ", #0b00000100000100000 \n"\ + " bicne " #b ", " #b ", #0b00001000001000000 \n"\ + " add " #a ", " #a ", " #b " \n"\ + " movne " #a ", " #a ", lsr #1 \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " orrne " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " orrne " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " orrne " #a ", " #a ", #0b01111100000000000 \n" + diff --git a/src/rops.h.old b/src/rops.h.old new file mode 100644 index 0000000..899b007 --- /dev/null +++ b/src/rops.h.old @@ -0,0 +1,118 @@ +/* + Raster Operations macros +*/ + +// ------------- +// RGB_565 +// a.red = a.red - b.red +// a.blue = a.blue - b.blue +// a.green = a.green - b.green +/* +#define ROP_SUB(a, b) \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b10000000000000000 \n"\ + " sub " #a ", " #a ", " #b " \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " biceq " #a ", " #a ", #0b01111100000000000 \n" +*/ +#define ROP_SUB(a, b) \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " beq 999f \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #(1 << 31) \n"\ + " subs " #a ", " #a ", " #b " \n"\ + " bicpl " #a ", " #a ", #0b01111100000000000 \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + "999:\n" + + +// ------------- +// RGB_565 +// if ZF set do ROP_SUB, else: +// a.red = (a.red - b.red) / 2 +// a.blue = (a.blue - b.blue) / 2 +// a.green = (a.green - b.green) / 2 +/* +#define ROP_SUB1_2(a, b) \ + " movne " #a ", " #a ", lsr #1 \n"\ + " bicne " #a ", " #a ", #0b00000010000010000 \n"\ + " movne " #b ", " #b ", lsr #1 \n"\ + " bicne " #b ", " #b ", #0b00000010000010000 \n"\ + \ + " bic " #b ", " #b ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #0b10000000000000000 \n"\ + " sub " #a ", " #a ", " #b " \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " biceq " #a ", " #a ", #0b01111100000000000 \n" +*/ + +#define ROP_SUB1_2(a, b) \ + " movne " #a ", " #a ", lsr #1 \n"\ + " bicne " #a ", " #a ", #0b00000010000010000 \n"\ + " movne " #b ", " #b ", lsr #1 \n"\ + " bicne " #b ", " #b ", #0b00000010000010000 \n"\ + \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " beq 999f \n"\ + " orr " #a ", " #a ", #0b00000100000100000 \n"\ + " orr " #a ", " #a ", #(1 << 31) \n"\ + " subs " #a ", " #a ", " #b " \n"\ + " bicpl " #a ", " #a ", #0b01111100000000000 \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " biceq " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " biceq " #a ", " #a ", #0b00000011111100000 \n"\ + "999:\n" + + +// ------------- +// RGB_565 +// a.red = a.red + b.red +// a.blue = a.blue + b.blue +// a.green = a.green + b.green +#define ROP_ADD(a, b) \ + " bics " #b ", " #b ", #0b00000100000100000 \n"\ + " beq 999f \n"\ + " bic " #a ", " #a ", #0b00000100000100000 \n"\ + " add " #a ", " #a ", " #b " \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " orrne " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " orrne " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " orrne " #a ", " #a ", #0b01111100000000000 \n"\ + "999:\n" + +// ------------- +// RGB_565 +// if ZF set do ROP_ADD, else: +// a.red = (a.red + b.red) / 2 +// a.blue = (a.blue + b.blue) / 2 +// a.green = (a.green + b.green) / 2 +#define ROP_ADD1_2(a, b) \ + " bic " #a ", " #a ", #0b00000100000100000 \n"\ + " bicne " #a ", " #a ", #0b00001000001000000 \n"\ + " bic " #b ", " #b ", #0b00000100000100000 \n"\ + " bicne " #b ", " #b ", #0b00001000001000000 \n"\ + " add " #a ", " #a ", " #b " \n"\ + " movne " #a ", " #a ", lsr #1 \n"\ + " tst " #a ", #0b00000000000100000 \n"\ + " orrne " #a ", " #a ", #0b00000000000011111 \n"\ + " tst " #a ", #0b00000100000000000 \n"\ + " orrne " #a ", " #a ", #0b00000011111100000 \n"\ + " tst " #a ", #0b10000000000000000 \n"\ + " orrne " #a ", " #a ", #0b01111100000000000 \n" + diff --git a/src/sa1.cpp b/src/sa1.cpp new file mode 100644 index 0000000..9bd0f8f --- /dev/null +++ b/src/sa1.cpp @@ -0,0 +1,775 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#ifdef USE_SA1 + +#include "snes9x.h" +#include "ppu.h" +#include "cpuexec.h" + +#include "sa1.h" + +static void S9xSA1CharConv2 (); +static void S9xSA1DMA (); +static void S9xSA1ReadVariableLengthData (bool8 inc, bool8 no_shift); + +void S9xSA1Init () +{ + SA1.NMIActive = FALSE; + SA1.IRQActive = FALSE; + SA1.WaitingForInterrupt = FALSE; + SA1.Waiting = FALSE; + SA1.Flags = 0; + SA1.Executing = FALSE; + memset (&Memory.FillRAM [0x2200], 0, 0x200); + Memory.FillRAM [0x2200] = 0x20; + Memory.FillRAM [0x2220] = 0x00; + Memory.FillRAM [0x2221] = 0x01; + Memory.FillRAM [0x2222] = 0x02; + Memory.FillRAM [0x2223] = 0x03; + Memory.FillRAM [0x2228] = 0xff; + SA1.op1 = 0; + SA1.op2 = 0; + SA1.arithmetic_op = 0; + SA1.sum = 0; + SA1.overflow = FALSE; +} + +void S9xSA1Reset () +{ + SA1Registers.PB = 0; + SA1Registers.PC = Memory.FillRAM [0x2203] | + (Memory.FillRAM [0x2204] << 8); + SA1Registers.D.W = 0; + SA1Registers.DB = 0; + SA1Registers.SH = 1; + SA1Registers.SL = 0xFF; + SA1Registers.XH = 0; + SA1Registers.YH = 0; + SA1Registers.P.W = 0; + + SA1.ShiftedPB = 0; + SA1.ShiftedDB = 0; + SA1SetFlags (MemoryFlag | IndexFlag | IRQ | Emulation); + SA1ClearFlags (Decimal); + + SA1.WaitingForInterrupt = FALSE; + SA1.PC = NULL; + SA1.PCBase = NULL; + S9xSA1SetPCBase (SA1Registers.PC); + SA1.S9xOpcodes = S9xSA1OpcodesM1X1; + + S9xSA1UnpackStatus(); + S9xSA1FixCycles (); + SA1.Executing = TRUE; + SA1.BWRAM = Memory.SRAM; + Memory.FillRAM [0x2225] = 0; +} + +void S9xSA1SetBWRAMMemMap (uint8 val) +{ + int c; + + if (val & 0x80) + { + for (c = 0; c < 0x400; c += 16) + { + SA1_Map [c + 6] = SA1_Map [c + 0x806] = (uint8 *) CMemory::MAP_BWRAM_BITMAP2; + SA1_Map [c + 7] = SA1_Map [c + 0x807] = (uint8 *) CMemory::MAP_BWRAM_BITMAP2; + SA1_WriteMap [c + 6] = SA1_WriteMap [c + 0x806] = (uint8 *) CMemory::MAP_BWRAM_BITMAP2; + SA1_WriteMap [c + 7] = SA1_WriteMap [c + 0x807] = (uint8 *) CMemory::MAP_BWRAM_BITMAP2; + } + SA1.BWRAM = Memory.SRAM + (val & 0x7f) * 0x2000 / 4; + } + else + { + for (c = 0; c < 0x400; c += 16) + { + SA1_Map [c + 6] = SA1_Map [c + 0x806] = (uint8 *) CMemory::MAP_BWRAM; + SA1_Map [c + 7] = SA1_Map [c + 0x807] = (uint8 *) CMemory::MAP_BWRAM; + SA1_WriteMap [c + 6] = SA1_WriteMap [c + 0x806] = (uint8 *) CMemory::MAP_BWRAM; + SA1_WriteMap [c + 7] = SA1_WriteMap [c + 0x807] = (uint8 *) CMemory::MAP_BWRAM; + } + SA1.BWRAM = Memory.SRAM + (val & 7) * 0x2000; + } +} + +void S9xFixSA1AfterSnapshotLoad () +{ + SA1.ShiftedPB = (uint32) SA1Registers.PB << 16; + SA1.ShiftedDB = (uint32) SA1Registers.DB << 16; + + S9xSA1SetPCBase (SA1.ShiftedPB + SA1Registers.PC); + S9xSA1UnpackStatus (); + S9xSA1FixCycles (); + SA1.VirtualBitmapFormat = (Memory.FillRAM [0x223f] & 0x80) ? 2 : 4; + Memory.BWRAM = Memory.SRAM + (Memory.FillRAM [0x2224] & 7) * 0x2000; + S9xSA1SetBWRAMMemMap (Memory.FillRAM [0x2225]); + + SA1.Waiting = (Memory.FillRAM [0x2200] & 0x60) != 0; + SA1.Executing = !SA1.Waiting; +} + +// SA9xSA1GetByte --- begin +static uint8 S9xSA1GetByte_default (uint32 address) { +#ifdef DEBUGGER +// printf ("R(B) %06x\n", address); +#endif + return (0); +} +static uint8 S9xSA1GetByte_PPU (uint32 address) { + return (S9xGetSA1 (address & 0xffff)); +} +static uint8 S9xSA1GetByte_SA1RAM (uint32 address) { + return (*(Memory.SRAM + (address & 0xffff))); +} +static uint8 S9xSA1GetByte_BWRAM (uint32 address) { + return (*(SA1.BWRAM + ((address & 0x7fff) - 0x6000))); +} +static uint8 S9xSA1GetByte_BWRAM_BITMAP (uint32 address) { + address -= 0x600000; + if (SA1.VirtualBitmapFormat == 2) + return ((Memory.SRAM [(address >> 2) & 0xffff] >> ((address & 3) << 1)) & 3); + else + return ((Memory.SRAM [(address >> 1) & 0xffff] >> ((address & 1) << 2)) & 15); +} +static uint8 S9xSA1GetByte_BWRAM_BITMAP2 (uint32 address) { + address = (address & 0xffff) - 0x6000; + if (SA1.VirtualBitmapFormat == 2) + return ((SA1.BWRAM [(address >> 2) & 0xffff] >> ((address & 3) << 1)) & 3); + else + return ((SA1.BWRAM [(address >> 1) & 0xffff] >> ((address & 1) << 2)) & 15); +} + +// GetByte JumpTable for Memmory map modes +uint8 (*S9xSA1GetByte_JumpTable[(1 << (16 - 12))]) (uint32 address) = { + S9xSA1GetByte_PPU, // MAP_PPU + S9xSA1GetByte_default, // MAP_CPU + S9xSA1GetByte_default, // MAP_DSP + S9xSA1GetByte_SA1RAM, // MAP_LOROM_SRAM + S9xSA1GetByte_default, // MAP_HIROM_SRAM + S9xSA1GetByte_default, // MAP_NONE + S9xSA1GetByte_default, // MAP_DEBUG + S9xSA1GetByte_default, // MAP_C4 + S9xSA1GetByte_BWRAM, // MAP_BWRAM + S9xSA1GetByte_BWRAM_BITMAP, // MAP_BWRAM_BITMAP + S9xSA1GetByte_BWRAM_BITMAP2, // MAP_BWRAM_BITMAP2 + S9xSA1GetByte_SA1RAM, // MAP_SA1RAM + S9xSA1GetByte_default, // MAP_LAST + S9xSA1GetByte_default, // MAP_LAST+1 + S9xSA1GetByte_default, // MAP_LAST+2 + S9xSA1GetByte_default // MAP_LAST+3 +}; + +uint8 S9xSA1GetByte (uint32 address) +{ + uint8 *GetAddress = SA1_Map [(address >> MEMMAP_SHIFT) & MEMMAP_MASK]; + if (GetAddress >= (uint8 *) CMemory::MAP_LAST) return (*(GetAddress + (address & 0xffff))); + return S9xSA1GetByte_JumpTable[(int) GetAddress](address); +// return (SA1_Map [(address >> MEMMAP_SHIFT) & MEMMAP_MASK] >= (uint8 *)CMemory::MAP_LAST) ? +// (*((uint8 *)(SA1_Map [(address >> MEMMAP_SHIFT) & MEMMAP_MASK]) + (address & 0xffff))) : +// S9xSA1GetByte_JumpTable[(int) SA1_Map [(address >> MEMMAP_SHIFT) & MEMMAP_MASK]](address); +} + +/* +uint16 S9xSA1GetWord (uint32 address) +{ + uint8 *GetAddress = SA1_Map [(address >> MEMMAP_SHIFT) & MEMMAP_MASK]; + if (GetAddress >= (uint8 *) CMemory::MAP_LAST) + return (*(GetAddress + (address & 0xffff))) | ((*(GetAddress + ((address+1) & 0xffff))) << 8); + return (S9xSA1GetByte_JumpTable[(int) GetAddress](address)) | ((S9xSA1GetByte_JumpTable[(int) GetAddress](address+1)) << 8); +} +*/ +// SA9xSA1SetByte --- begin +static void S9xSA1SetByte_default (uint8 byte, uint32 address) { +} +static void S9xSA1SetByte_PPU (uint8 byte, uint32 address) { + S9xSetSA1 (byte, address & 0xffff); +} +static void S9xSA1SetByte_SA1RAM (uint8 byte, uint32 address) { + *(Memory.SRAM + (address & 0xffff)) = byte; +} +static void S9xSA1SetByte_BWRAM (uint8 byte, uint32 address) { + *(SA1.BWRAM + ((address & 0x7fff) - 0x6000)) = byte; +} +static void S9xSA1SetByte_BWRAM_BITMAP (uint8 byte, uint32 address) { + uint8 *ptr; + address -= 0x600000; + if (SA1.VirtualBitmapFormat == 2) { + ptr = &Memory.SRAM [(address >> 2) & 0xffff]; + *ptr &= ~(3 << ((address & 3) << 1)); + *ptr |= (byte & 3) << ((address & 3) << 1); + } else { + ptr = &Memory.SRAM [(address >> 1) & 0xffff]; + *ptr &= ~(15 << ((address & 1) << 2)); + *ptr |= (byte & 15) << ((address & 1) << 2); + } + address -= 0x600000; +} +static void S9xSA1SetByte_BWRAM_BITMAP2 (uint8 byte, uint32 address) { + uint8 *ptr; + address = (address & 0xffff) - 0x6000; + if (SA1.VirtualBitmapFormat == 2) + { + ptr = &SA1.BWRAM [(address >> 2) & 0xffff]; + *ptr &= ~(3 << ((address & 3) << 1)); + *ptr |= (byte & 3) << ((address & 3) << 1); + } + else + { + ptr = &SA1.BWRAM [(address >> 1) & 0xffff]; + *ptr &= ~(15 << ((address & 1) << 2)); + *ptr |= (byte & 15) << ((address & 1) << 2); + } +} + +// SetByte JumpTable for Memmory map modes +void (*S9xSA1SetByte_JumpTable[(1 << (16 - 12))]) (uint8 byte, uint32 address) = { + S9xSA1SetByte_PPU, // MAP_PPU + S9xSA1SetByte_default, // MAP_CPU + S9xSA1SetByte_default, // MAP_DSP + S9xSA1SetByte_SA1RAM, // MAP_LOROM_SRAM + S9xSA1SetByte_default, // MAP_HIROM_SRAM + S9xSA1SetByte_default, // MAP_NONE + S9xSA1SetByte_default, // MAP_DEBUG + S9xSA1SetByte_default, // MAP_C4 + S9xSA1SetByte_BWRAM, // MAP_BWRAM + S9xSA1SetByte_BWRAM_BITMAP, // MAP_BWRAM_BITMAP + S9xSA1SetByte_BWRAM_BITMAP2, // MAP_BWRAM_BITMAP2 + S9xSA1SetByte_SA1RAM, // MAP_SA1RAM + S9xSA1SetByte_default, // MAP_LAST + S9xSA1SetByte_default, // MAP_LAST+1 + S9xSA1SetByte_default, // MAP_LAST+2 + S9xSA1SetByte_default // MAP_LAST+3 +}; + +void S9xSA1SetByte (uint8 byte, uint32 address) +{ + // MEMMAP_SHIFT 12 + // MEMMAP_MASK 0xFFF + + uint8 *Setaddress = SA1_WriteMap [(address >> MEMMAP_SHIFT) & MEMMAP_MASK]; + if (Setaddress >= (uint8 *) CMemory::MAP_LAST) + { + *(Setaddress + (address & 0xffff)) = byte; + return; + } + S9xSA1SetByte_JumpTable[(int)Setaddress](byte, address); +} + +void S9xSA1SetPCBase (uint32 address) +{ + uint8 *GetAddress = SA1_Map [(address >> MEMMAP_SHIFT) & MEMMAP_MASK]; + if (GetAddress >= (uint8 *) CMemory::MAP_LAST) + { + SA1.PCBase = GetAddress; + SA1.PC = GetAddress + (address & 0xffff); + return; + } + + switch ((int) GetAddress) + { + case CMemory::MAP_PPU: + SA1.PCBase = Memory.FillRAM - 0x2000; + SA1.PC = SA1.PCBase + (address & 0xffff); + return; + + case CMemory::MAP_CPU: + SA1.PCBase = Memory.FillRAM - 0x4000; + SA1.PC = SA1.PCBase + (address & 0xffff); + return; + + case CMemory::MAP_DSP: + SA1.PCBase = Memory.FillRAM - 0x6000; + SA1.PC = SA1.PCBase + (address & 0xffff); + return; + + case CMemory::MAP_SA1RAM: + case CMemory::MAP_LOROM_SRAM: + SA1.PCBase = Memory.SRAM; + SA1.PC = SA1.PCBase + (address & 0xffff); + return; + + case CMemory::MAP_BWRAM: + SA1.PCBase = SA1.BWRAM - 0x6000; + SA1.PC = SA1.PCBase + (address & 0xffff); + return; + case CMemory::MAP_HIROM_SRAM: + SA1.PCBase = Memory.SRAM - 0x6000; + SA1.PC = SA1.PCBase + (address & 0xffff); + return; + + case CMemory::MAP_DEBUG: +#ifdef DEBUGGER + printf ("SBP %06x\n", address); +#endif + + default: + case CMemory::MAP_NONE: + SA1.PCBase = Memory.RAM; + SA1.PC = Memory.RAM + (address & 0xffff); + return; + } +} + +void S9xSA1ExecuteDuringSleep () +{ +} + +void S9xSetSA1MemMap (uint32 which1, uint8 map) +{ + int c; + int start = which1 * 0x100 + 0xc00; + int start2 = which1 * 0x200; + uint8 *block; + int i; + + if (which1 >= 2) + start2 += 0x400; + + for (c = 0; c < 0x100; c += 16) + { + block = &Memory.ROM [(map & 7) * 0x100000 + (c << 12)]; + for (i = c; i < c + 16; i++) + Memory.Map [start + i] = SA1_Map [start + i] = block; + } + + for (c = 0; c < 0x200; c += 16) + { + block = &Memory.ROM [(map & 7) * 0x100000 + (c << 11) - 0x8000]; + for (i = c + 8; i < c + 16; i++) + Memory.Map [start2 + i] = SA1_Map [start2 + i] = block; + } +} + +uint8 S9xGetSA1 (uint32 address) +{ + if ((address < 0x2300) && (address > 0x230d)) return (Memory.FillRAM [address]); + switch (address) + { + case 0x2300: + return ((uint8) ((Memory.FillRAM [0x2209] & 0x5f) | + (CPU.IRQActive & (SA1_IRQ_SOURCE | SA1_DMA_IRQ_SOURCE)))); + case 0x2301: + return ((Memory.FillRAM [0x2200] & 0xf) | + (Memory.FillRAM [0x2301] & 0xf0)); + case 0x2306: + return ((uint8) SA1.sum); + case 0x2307: + return ((uint8) (SA1.sum >> 8)); + case 0x2308: + return ((uint8) (SA1.sum >> 16)); + case 0x2309: + return ((uint8) (SA1.sum >> 24)); + case 0x230a: + return ((uint8) (SA1.sum >> 32)); + case 0x230b: + return (Memory.FillRAM [address]); + case 0x230c: + return (Memory.FillRAM [0x230c]); + case 0x230d: + { + uint8 byte = Memory.FillRAM [0x230d]; + + if (Memory.FillRAM [0x2258] & 0x80) + { + S9xSA1ReadVariableLengthData (TRUE, FALSE); + } + return (byte); + } + } + +} + +void S9xSetSA1 (uint8 byte, uint32 address) +{ + + if (address < 0x2200 || address > 0x22ff) return; + + switch (address) + { + case 0x2200: + SA1.Waiting = (byte & 0x60) != 0; + + if (!(byte & 0x20) && (Memory.FillRAM [0x2200] & 0x20)) + { + S9xSA1Reset (); + } + if (byte & 0x80) + { + Memory.FillRAM [0x2301] |= 0x80; + if (Memory.FillRAM [0x220a] & 0x80) + { + SA1.Flags |= IRQ_PENDING_FLAG; + SA1.IRQActive |= SNES_IRQ_SOURCE; + SA1.Executing = !SA1.Waiting && SA1.S9xOpcodes; + } + } + if (byte & 0x10) + { + Memory.FillRAM [0x2301] |= 0x10; + } + break; + + case 0x2201: + if (((byte ^ Memory.FillRAM [0x2201]) & 0x80) && + (Memory.FillRAM [0x2300] & byte & 0x80)) + { + S9xSetIRQ (SA1_IRQ_SOURCE); + } + if (((byte ^ Memory.FillRAM [0x2201]) & 0x20) && + (Memory.FillRAM [0x2300] & byte & 0x20)) + { + S9xSetIRQ (SA1_DMA_IRQ_SOURCE); + } + break; + case 0x2202: + if (byte & 0x80) + { + Memory.FillRAM [0x2300] &= ~0x80; + S9xClearIRQ (SA1_IRQ_SOURCE); + } + if (byte & 0x20) + { + Memory.FillRAM [0x2300] &= ~0x20; + S9xClearIRQ (SA1_DMA_IRQ_SOURCE); + } + break; + + case 0x2209: + Memory.FillRAM [0x2209] = byte; + if (byte & 0x80) + Memory.FillRAM [0x2300] |= 0x80; + + if (byte & Memory.FillRAM [0x2201] & 0x80) + { + S9xSetIRQ (SA1_IRQ_SOURCE); + } + return; + case 0x220a: + if (((byte ^ Memory.FillRAM [0x220a]) & 0x80) && + (Memory.FillRAM [0x2301] & byte & 0x80)) + { + SA1.Flags |= IRQ_PENDING_FLAG; + SA1.IRQActive |= SNES_IRQ_SOURCE; + } + if (((byte ^ Memory.FillRAM [0x220a]) & 0x40) && + (Memory.FillRAM [0x2301] & byte & 0x40)) + { + SA1.Flags |= IRQ_PENDING_FLAG; + SA1.IRQActive |= TIMER_IRQ_SOURCE; + } + if (((byte ^ Memory.FillRAM [0x220a]) & 0x20) && + (Memory.FillRAM [0x2301] & byte & 0x20)) + { + SA1.Flags |= IRQ_PENDING_FLAG; + SA1.IRQActive |= DMA_IRQ_SOURCE; + } + if (((byte ^ Memory.FillRAM [0x220a]) & 0x10) && + (Memory.FillRAM [0x2301] & byte & 0x10)) + { + } + break; + case 0x220b: + if (byte & 0x80) + { + SA1.IRQActive &= ~SNES_IRQ_SOURCE; + Memory.FillRAM [0x2301] &= ~0x80; + } + if (byte & 0x40) + { + SA1.IRQActive &= ~TIMER_IRQ_SOURCE; + Memory.FillRAM [0x2301] &= ~0x40; + } + if (byte & 0x20) + { + SA1.IRQActive &= ~DMA_IRQ_SOURCE; + Memory.FillRAM [0x2301] &= ~0x20; + } + if (byte & 0x10) + { + // Clear NMI + Memory.FillRAM [0x2301] &= ~0x10; + } + if (!SA1.IRQActive) + SA1.Flags &= ~IRQ_PENDING_FLAG; + break; + case 0x2220: + case 0x2221: + case 0x2222: + case 0x2223: + S9xSetSA1MemMap (address - 0x2220, byte); + break; + case 0x2224: + Memory.BWRAM = Memory.SRAM + (byte & 7) * 0x2000; + break; + case 0x2225: + if (byte != Memory.FillRAM [address]) + S9xSA1SetBWRAMMemMap (byte); + break; + case 0x2231: + if (byte & 0x80) + SA1.in_char_dma = FALSE; + break; + case 0x2236: + Memory.FillRAM [address] = byte; + if ((Memory.FillRAM [0x2230] & 0xa4) == 0x80) + { + // Normal DMA to I-RAM + S9xSA1DMA (); + } + else + if ((Memory.FillRAM [0x2230] & 0xb0) == 0xb0) + { + Memory.FillRAM [0x2300] |= 0x20; + if (Memory.FillRAM [0x2201] & 0x20) + S9xSetIRQ (SA1_DMA_IRQ_SOURCE); + SA1.in_char_dma = TRUE; + } + return; + case 0x2237: + Memory.FillRAM [address] = byte; + if ((Memory.FillRAM [0x2230] & 0xa4) == 0x84) + { + // Normal DMA to BW-RAM + S9xSA1DMA (); + } + return; + case 0x223f: + SA1.VirtualBitmapFormat = (byte & 0x80) ? 2 : 4; + break; + + case 0x224f: + Memory.FillRAM [address] = byte; + if ((Memory.FillRAM [0x2230] & 0xb0) == 0xa0) + { + // Char conversion 2 DMA enabled + memmove (&Memory.ROM [CMemory::MAX_ROM_SIZE - 0x10000] + (SA1.in_char_dma << 4), + &Memory.FillRAM [0x2240], 16); + SA1.in_char_dma = (SA1.in_char_dma + 1) & 7; + if ((SA1.in_char_dma & 3) == 0) + { + S9xSA1CharConv2 (); + } + } + return; + case 0x2250: + if (byte & 2) + SA1.sum = 0; + SA1.arithmetic_op = byte & 3; + break; + + case 0x2251: + SA1.op1 = (SA1.op1 & 0xff00) | byte; + break; + case 0x2252: + SA1.op1 = (SA1.op1 & 0xff) | (byte << 8); + break; + case 0x2253: + SA1.op2 = (SA1.op2 & 0xff00) | byte; + break; + case 0x2254: + SA1.op2 = (SA1.op2 & 0xff) | (byte << 8); + switch (SA1.arithmetic_op) + { + case 0: // multiply + SA1.sum = SA1.op1 * SA1.op2; + break; + case 1: // divide + if (SA1.op2 == 0) + SA1.sum = SA1.op1 << 16; + else + { + unsigned int x = (SA1.op1 / (int) ((uint16) SA1.op2)); + SA1.sum = x | ((SA1.op1 - (x * (uint16) SA1.op2)) << 16); + // SA1.sum = (SA1.op1 / (int) ((uint16) SA1.op2)) | + //((SA1.op1 % (int) ((uint16) SA1.op2)) << 16); + } + break; + default: // cumulative sum + SA1.sum += SA1.op1 * SA1.op2; + if (SA1.sum & ((int64) 0xffffff << 32)) + SA1.overflow = TRUE; + break; + } + break; + case 0x2258: // Variable bit-field length/auto inc/start. + Memory.FillRAM [0x2258] = byte; + S9xSA1ReadVariableLengthData (TRUE, FALSE); + return; + case 0x2259: + case 0x225a: + case 0x225b: // Variable bit-field start address + Memory.FillRAM [address] = byte; + // XXX: ??? + SA1.variable_bit_pos = 0; + S9xSA1ReadVariableLengthData (FALSE, TRUE); + return; + } + if (address >= 0x2200 && address <= 0x22ff) + Memory.FillRAM [address] = byte; +} + +static void S9xSA1CharConv2 () +{ + uint32 dest = Memory.FillRAM [0x2235] | (Memory.FillRAM [0x2236] << 8); + uint32 offset = (SA1.in_char_dma & 7) ? 0 : 1; + int depth = (Memory.FillRAM [0x2231] & 3) == 0 ? 8 : + (Memory.FillRAM [0x2231] & 3) == 1 ? 4 : 2; + int bytes_per_char = 8 * depth; + uint8 *p = &Memory.FillRAM [0x3000] + dest + offset * bytes_per_char; + uint8 *q = &Memory.ROM [CMemory::MAX_ROM_SIZE - 0x10000] + offset * 64; + + if (depth == 8) + { + for (int l = 0; l < 8; l++, q += 8) + { + for (int b = 0; b < 8; b++) + { + uint8 r = *(q + b); + *(p + 0) = (*(p + 0) << 1) | ((r >> 0) & 1); + *(p + 1) = (*(p + 1) << 1) | ((r >> 1) & 1); + *(p + 16) = (*(p + 16) << 1) | ((r >> 2) & 1); + *(p + 17) = (*(p + 17) << 1) | ((r >> 3) & 1); + *(p + 32) = (*(p + 32) << 1) | ((r >> 4) & 1); + *(p + 33) = (*(p + 33) << 1) | ((r >> 5) & 1); + *(p + 48) = (*(p + 48) << 1) | ((r >> 6) & 1); + *(p + 49) = (*(p + 49) << 1) | ((r >> 7) & 1); + } + p += 2; + } + } +} + +static void S9xSA1DMA () +{ + uint32 src = Memory.FillRAM [0x2232] | + (Memory.FillRAM [0x2233] << 8) | + (Memory.FillRAM [0x2234] << 16); + uint32 dst = Memory.FillRAM [0x2235] | + (Memory.FillRAM [0x2236] << 8) | + (Memory.FillRAM [0x2237] << 16); + uint32 len = Memory.FillRAM [0x2238] | + (Memory.FillRAM [0x2239] << 8); + + uint8 *s; + uint8 *d; + + switch (Memory.FillRAM [0x2230] & 3) + { + case 0: // ROM + s = SA1_Map [(src >> MEMMAP_SHIFT) & MEMMAP_MASK]; + if (s >= (uint8 *) CMemory::MAP_LAST) + s += (src & 0xffff); + else + s = Memory.ROM + (src & 0xffff); + break; + case 1: // BW-RAM + src &= CPU.Memory_SRAMMask; + len &= CPU.Memory_SRAMMask; + s = Memory.SRAM + src; + break; + default: + case 2: + src &= 0x3ff; + len &= 0x3ff; + s = &Memory.FillRAM [0x3000] + src; + break; + } + + if (Memory.FillRAM [0x2230] & 4) + { + dst &= CPU.Memory_SRAMMask; + len &= CPU.Memory_SRAMMask; + d = Memory.SRAM + dst; + } + else + { + dst &= 0x3ff; + len &= 0x3ff; + d = &Memory.FillRAM [0x3000] + dst; + } + memmove (d, s, len); + Memory.FillRAM [0x2301] |= 0x20; + + if (Memory.FillRAM [0x220a] & 0x20) + { + SA1.Flags |= IRQ_PENDING_FLAG; + SA1.IRQActive |= DMA_IRQ_SOURCE; + } +} + +void S9xSA1ReadVariableLengthData (bool8 inc, bool8 no_shift) +{ + uint32 addr = Memory.FillRAM [0x2259] | + (Memory.FillRAM [0x225a] << 8) | + (Memory.FillRAM [0x225b] << 16); + uint8 shift = Memory.FillRAM [0x2258] & 15; + + if (no_shift) + shift = 0; + else + if (shift == 0) + shift = 16; + + uint8 s = shift + SA1.variable_bit_pos; + + if (s >= 16) + { + addr += (s >> 4) << 1; + s &= 15; + } + uint32 data = S9xSA1GetWord (addr) | + (S9xSA1GetWord (addr + 2) << 16); + + data >>= s; + Memory.FillRAM [0x230c] = (uint8) data; + Memory.FillRAM [0x230d] = (uint8) (data >> 8); + if (inc) + { + SA1.variable_bit_pos = (SA1.variable_bit_pos + shift) & 15; + Memory.FillRAM [0x2259] = (uint8) addr; + Memory.FillRAM [0x225a] = (uint8) (addr >> 8); + Memory.FillRAM [0x225b] = (uint8) (addr >> 16); + } +} + +#endif // USE_SA1 diff --git a/src/sa1.h b/src/sa1.h new file mode 100644 index 0000000..3a297f5 --- /dev/null +++ b/src/sa1.h @@ -0,0 +1,189 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holder:s request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef USE_SA1 +#define _sa1_h_ +#endif + +#ifndef _sa1_h_ +#define _sa1_h_ + +#include "memmap.h" + +struct SSA1Registers { + uint8 PB; + uint8 DB; + pair P; + pair A; + pair D; + pair S; + pair X; + pair Y; + uint16 PC; +}; + +struct SSA1 { + struct SOpcodes *S9xOpcodes; + uint8 _Carry; + uint8 _Zero; + uint8 _Negative; + uint8 _Overflow; + bool8 CPUExecuting; + uint32 ShiftedPB; + uint32 ShiftedDB; + uint32 Flags; + bool8 Executing; + bool8 NMIActive; + bool8 IRQActive; + bool8 WaitingForInterrupt; + bool8 Waiting; +// uint8 WhichEvent; + uint8 *PC; + uint8 *PCBase; + uint8 *BWRAM; + uint8 *PCAtOpcodeStart; + uint8 *WaitAddress; + uint32 WaitCounter; + uint8 *WaitByteAddress1; + uint8 *WaitByteAddress2; +// long Cycles; +// long NextEvent; +// long V_Counter; + int16 op1; + int16 op2; + int arithmetic_op; + int64 sum; + bool8 overflow; + + uint8 VirtualBitmapFormat; + bool8 in_char_dma; + uint8 variable_bit_pos; +}; + +extern struct SSA1Registers SA1Registers; +extern struct SSA1 SA1; + +extern uint8 *SA1_Map [MEMMAP_NUM_BLOCKS]; +extern uint8 *SA1_WriteMap [MEMMAP_NUM_BLOCKS]; + + +#ifdef USE_SA1 + +#define SA1CheckZero() (SA1._Zero == 0) +#define SA1CheckCarry() (SA1._Carry) +#define SA1CheckIRQ() (SA1Registers.PL & IRQ) +#define SA1CheckDecimal() (SA1Registers.PL & Decimal) +#define SA1CheckIndex() (SA1Registers.PL & IndexFlag) +#define SA1CheckMemory() (SA1Registers.PL & MemoryFlag) +#define SA1CheckOverflow() (SA1._Overflow) +#define SA1CheckNegative() (SA1._Negative & 0x80) +#define SA1CheckEmulation() (SA1Registers.P.W & Emulation) + +#define SA1ClearFlags(f) (SA1Registers.P.W &= ~(f)) +#define SA1SetFlags(f) (SA1Registers.P.W |= (f)) +#define SA1CheckFlag(f) (SA1Registers.PL & (f)) + + +START_EXTERN_C +uint8 S9xSA1GetByte (uint32); +//uint16 S9xSA1GetWord (uint32); +#define S9xSA1GetWord(address) (S9xSA1GetByte(address) | (S9xSA1GetByte(address+1) << 8)) +void S9xSA1SetByte (uint8, uint32); +//void S9xSA1SetWord (uint16, uint32); +#define S9xSA1SetWord(word, address) S9xSA1SetByte(word, address); S9xSA1SetByte(word >> 8, address+1); +void S9xSA1SetPCBase (uint32); +uint8 S9xGetSA1 (uint32); +void S9xSetSA1 (uint8, uint32); + +extern struct SOpcodes S9xSA1OpcodesM1X1 [256]; +extern struct SOpcodes S9xSA1OpcodesM1X0 [256]; +extern struct SOpcodes S9xSA1OpcodesM0X1 [256]; +extern struct SOpcodes S9xSA1OpcodesM0X0 [256]; + +void S9xSA1MainLoop (); +void S9xSA1Init (); +void S9xFixSA1AfterSnapshotLoad (); +void S9xSA1ExecuteDuringSleep (); +END_EXTERN_C + +#define SNES_IRQ_SOURCE (1 << 7) +#define TIMER_IRQ_SOURCE (1 << 6) +#define DMA_IRQ_SOURCE (1 << 5) + +STATIC inline void S9xSA1UnpackStatus() +{ + SA1._Zero = (SA1Registers.PL & Zero) == 0; + SA1._Negative = (SA1Registers.PL & Negative); + SA1._Carry = (SA1Registers.PL & Carry); + SA1._Overflow = (SA1Registers.PL & Overflow) >> 6; +} + +STATIC inline void S9xSA1PackStatus() +{ + SA1Registers.PL &= ~(Zero | Negative | Carry | Overflow); + SA1Registers.PL |= SA1._Carry | ((SA1._Zero == 0) << 1) | + (SA1._Negative & 0x80) | (SA1._Overflow << 6); +} + +STATIC inline void S9xSA1FixCycles () +{ + if (SA1CheckEmulation ()) + SA1.S9xOpcodes = S9xSA1OpcodesM1X1; + else + if (SA1CheckMemory ()) + { + if (SA1CheckIndex ()) + SA1.S9xOpcodes = S9xSA1OpcodesM1X1; + else + SA1.S9xOpcodes = S9xSA1OpcodesM1X0; + } + else + { + if (SA1CheckIndex ()) + SA1.S9xOpcodes = S9xSA1OpcodesM0X1; + else + SA1.S9xOpcodes = S9xSA1OpcodesM0X0; + } +} + + +#endif // USE_SA1 + +#endif diff --git a/src/sa1.s b/src/sa1.s new file mode 100644 index 0000000..aaeea37 --- /dev/null +++ b/src/sa1.s @@ -0,0 +1 @@ + .file "sa1.cpp" diff --git a/src/sa1_asm.s b/src/sa1_asm.s new file mode 100644 index 0000000..a79d185 --- /dev/null +++ b/src/sa1_asm.s @@ -0,0 +1,9 @@ + .text + .global S9xGetSA1; + .type S9xGetSA1,%function + .align 2; + +S9xGetSA1: + mov pc, lr + +.size S9xGetSA1,.-S9xGetSA1; diff --git a/src/sa1cpu.cpp b/src/sa1cpu.cpp new file mode 100644 index 0000000..0e571cb --- /dev/null +++ b/src/sa1cpu.cpp @@ -0,0 +1,125 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#ifdef USE_SA1 + +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "cpuexec.h" + +#include "sa1.h" +#define CPU SA1 +#define ICPU SA1 + +#undef Registers + +#define Registers SA1Registers +#define S9xGetByte S9xSA1GetByte +#define S9xGetWord S9xSA1GetWord +#define S9xSetByte S9xSA1SetByte +#define S9xSetWord S9xSA1SetWord +#define S9xSetPCBase S9xSA1SetPCBase +#define S9xOpcodesM1X1 S9xSA1OpcodesM1X1 +#define S9xOpcodesM1X0 S9xSA1OpcodesM1X0 +#define S9xOpcodesM0X1 S9xSA1OpcodesM0X1 +#define S9xOpcodesM0X0 S9xSA1OpcodesM0X0 +#define S9xOpcode_IRQ S9xSA1Opcode_IRQ +#define S9xOpcode_NMI S9xSA1Opcode_NMI +#define S9xUnpackStatus S9xSA1UnpackStatus +#define S9xPackStatus S9xSA1PackStatus +#define S9xFixCycles S9xSA1FixCycles +#define Immediate8 SA1Immediate8 +#define Immediate16 SA1Immediate16 +#define Relative SA1Relative +#define RelativeLong SA1RelativeLong +#define AbsoluteIndexedIndirect SA1AbsoluteIndexedIndirect +#define AbsoluteIndirectLong SA1AbsoluteIndirectLong +#define AbsoluteIndirect SA1AbsoluteIndirect +#define Absolute SA1Absolute +#define AbsoluteLong SA1AbsoluteLong +#define Direct SA1Direct +#define DirectIndirectIndexed SA1DirectIndirectIndexed +#define DirectIndirectIndexedLong SA1DirectIndirectIndexedLong +#define DirectIndexedIndirect SA1DirectIndexedIndirect +#define DirectIndexedX SA1DirectIndexedX +#define DirectIndexedY SA1DirectIndexedY +#define AbsoluteIndexedX SA1AbsoluteIndexedX +#define AbsoluteIndexedY SA1AbsoluteIndexedY +#define AbsoluteLongIndexedX SA1AbsoluteLongIndexedX +#define DirectIndirect SA1DirectIndirect +#define DirectIndirectLong SA1DirectIndirectLong +#define StackRelative SA1StackRelative +#define StackRelativeIndirectIndexed SA1StackRelativeIndirectIndexed + +//#undef CPU_SHUTDOWN +#undef VAR_CYCLES +#define SA1_OPCODES + +#include "cpuops.cpp" + +void S9xSA1MainLoop () +{ + int i; + + if (SA1.Flags & IRQ_PENDING_FLAG) + { + if (SA1.IRQActive) + { + if (SA1.WaitingForInterrupt) + { + SA1.WaitingForInterrupt = FALSE; + SA1.PC++; + } + if (!SA1CheckFlag (IRQ)) + S9xSA1Opcode_IRQ (); + } + else + SA1.Flags &= ~IRQ_PENDING_FLAG; + } + + for (i = 0; i < 3 && SA1.Executing; i++) + { + (*SA1.S9xOpcodes [*SA1.PC++].S9xOpcode) (); + } +} + +#endif // USE_SA1 diff --git a/src/sar.h b/src/sar.h new file mode 100644 index 0000000..1c62aa0 --- /dev/null +++ b/src/sar.h @@ -0,0 +1,132 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2003 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2002 - 2003 Matthew Kendora and + Brad Jorsch (anomie@users.sourceforge.net) + + + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and + Nach (n-a-c-h@users.sourceforge.net) + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2003 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman (jweidman@slip.net), + neviksti (neviksti@hotmail.com), and + Kris Bleakley (stinkfish@bigpond.com) + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2003 zsKnight, pagefault (pagefault@zsnes.com) + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar and Gary Henderson. + + + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ + +#ifndef _SAR_H_ +#define _SAR_H_ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include "port.h" + +#ifndef snes9x_types_defined +#define snes9x_types_defined + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; +typedef unsigned char bool8; +typedef unsigned int bool32; +typedef signed char int8; +typedef short int16; +typedef int int32; +#endif + +#ifdef RIGHTSHIFT_IS_SAR +#define SAR(b, n) ((b)>>(n)) +#else + +static inline int8 SAR(const int8 b, const int n){ +#ifndef RIGHTSHIFT_INT8_IS_SAR + if(b<0) return (b>>n)|(-1<<(8-n)); +#endif + return b>>n; +} + +static inline int16 SAR(const int16 b, const int n){ +#ifndef RIGHTSHIFT_INT16_IS_SAR + if(b<0) return (b>>n)|(-1<<(16-n)); +#endif + return b>>n; +} + +static inline int32 SAR(const int32 b, const int n){ +#ifndef RIGHTSHIFT_INT32_IS_SAR + if(b<0) return (b>>n)|(-1<<(32-n)); +#endif + return b>>n; +} + +static inline int64 SAR(const int64 b, const int n){ +#ifndef RIGHTSHIFT_INT64_IS_SAR + if(b<0) return (b>>n)|(-1<<(64-n)); +#endif + return b>>n; +} + +#endif + +#endif diff --git a/src/screenshot.c b/src/screenshot.c new file mode 100644 index 0000000..ab169cf --- /dev/null +++ b/src/screenshot.c @@ -0,0 +1,71 @@ +#include +#include +#include +#include "screenshot.h" +#include "png.h" +#include "menu.h" +#include "config.h" + +static gBITMAP *screenShot = NULL; + +#define SS_WIDTH 256 +#define SS_HEIGHT 240 + +// Copy screen into screenshot buffer +void getScreenShot(unsigned short *screen) { + unsigned int x, y; + screen += 32; + + if (!screenShot) { + screenShot = gCreateBitmap(SS_WIDTH, SS_HEIGHT, 32); + if (!screenShot) return; + } + + for (y = 0; y < SS_HEIGHT; y++) + for(x = 0; x < SS_WIDTH; x++) { + unsigned short pixel = screen[y * SCREEN_WIDTH + x]; + screenShot->data[(y * SS_WIDTH + x) * 4 + 0] = PIXEL16_R(pixel); + screenShot->data[(y * SS_WIDTH + x) * 4 + 1] = PIXEL16_G(pixel); + screenShot->data[(y * SS_WIDTH + x) * 4 + 2] = PIXEL16_B(pixel); + screenShot->data[(y * SS_WIDTH + x) * 4 + 3] = 0xff; + } +} + +int saveScreenShot() { + char fn[1024]; + char png_fn[1024]; + char *ext; + int ret; + + if (!screenShot) return -1; + + // get filename of last loaded ROM (the running one) + getConfigValue(CONFIG_LASTLOADED, fn, sizeof(fn)); + // set file ext to .png + ext = strrchr(fn, '.'); + if (!ext) ext = &fn[strlen(fn)]; + strcpy(ext, ".png"); + // compose screenshot file's full path + sprintf(png_fn, "%s%s", getScreenShotsDir(), strrchr(fn, '/')); + + ret = save_png(screenShot, png_fn); + sync(); + + return ret; +} + +static char screenShotsDir[1024] = "\0"; +static int getScreenShotsDirFirstTime = 1; +const char *getScreenShotsDir() { + if (screenShotsDir[0] == '\0') sprintf(screenShotsDir, "%s/%s", currentWorkingDir, "screenshots"); + if (getScreenShotsDirFirstTime) { + mkdir(screenShotsDir, 0777); + getScreenShotsDirFirstTime = 0; + } + return screenShotsDir; +} + +void destroyScreenShot() { + gDestroyBitmap(screenShot); + screenShot = NULL; +} diff --git a/src/screenshot.h b/src/screenshot.h new file mode 100644 index 0000000..64df2ba --- /dev/null +++ b/src/screenshot.h @@ -0,0 +1,19 @@ +#ifndef __SCREENSHOT_H__ +#define __SCREENSHOT_H__ + +#include "graphics.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int saveScreenShot(); +void destroyScreenShot(); +void getScreenShot(unsigned short *screen); +const char *getScreenShotsDir(); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/sdd1.cpp b/src/sdd1.cpp new file mode 100644 index 0000000..8c79750 --- /dev/null +++ b/src/sdd1.cpp @@ -0,0 +1,135 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "sdd1.h" +#include "display.h" + +#ifdef __linux +//#include +#endif + +void S9xSetSDD1MemoryMap (uint32 bank, uint32 value) +{ + bank = 0xc00 + bank * 0x100; + value = value * 1024 * 1024; + + int c; + + for (c = 0; c < 0x100; c += 16) + { + uint8 *block = &Memory.ROM [value + (c << 12)]; + int i; + + for (i = c; i < c + 16; i++) + Memory.Map [i + bank] = block; + } +} + +void S9xResetSDD1 () +{ + memset (&Memory.FillRAM [0x4800], 0, 4); + for (int i = 0; i < 4; i++) + { + Memory.FillRAM [0x4804 + i] = i; + S9xSetSDD1MemoryMap (i, i); + } +} + +void S9xSDD1PostLoadState () +{ + for (int i = 0; i < 4; i++) + S9xSetSDD1MemoryMap (i, Memory.FillRAM [0x4804 + i]); +} + +#ifndef _SNESPPC +static int S9xCompareSDD1LoggedDataEntries (const void *p1, const void *p2) +#else +static int _cdecl S9xCompareSDD1LoggedDataEntries (const void *p1, const void *p2) +#endif +{ + uint8 *b1 = (uint8 *) p1; + uint8 *b2 = (uint8 *) p2; + uint32 a1 = (*b1 << 16) + (*(b1 + 1) << 8) + *(b1 + 2); + uint32 a2 = (*b2 << 16) + (*(b2 + 1) << 8) + *(b2 + 2); + + return (a1 - a2); +} + +void S9xSDD1SaveLoggedData () +{ + if (Memory.SDD1LoggedDataCount != Memory.SDD1LoggedDataCountPrev) + { + qsort (Memory.SDD1LoggedData, Memory.SDD1LoggedDataCount, 8, + S9xCompareSDD1LoggedDataEntries); + + FILE *fs = fopen (S9xGetFilename (".dat"), "wb"); + + if (fs) + { + fwrite (Memory.SDD1LoggedData, 8, + Memory.SDD1LoggedDataCount, fs); + fclose (fs); +#if defined(__linux) + chown (S9xGetFilename (".dat"), getuid (), getgid ()); +#endif + } + Memory.SDD1LoggedDataCountPrev = Memory.SDD1LoggedDataCount; + } +} + +void S9xSDD1LoadLoggedData () +{ + FILE *fs = fopen (S9xGetFilename (".dat"), "rb"); + + Memory.SDD1LoggedDataCount = Memory.SDD1LoggedDataCountPrev = 0; + + if (fs) + { + int c = fread (Memory.SDD1LoggedData, 8, + MEMMAP_MAX_SDD1_LOGGED_ENTRIES, fs); + + if (c != EOF) + Memory.SDD1LoggedDataCount = Memory.SDD1LoggedDataCountPrev = c; + fclose (fs); + } +} diff --git a/src/sdd1.h b/src/sdd1.h new file mode 100644 index 0000000..1320889 --- /dev/null +++ b/src/sdd1.h @@ -0,0 +1,48 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _SDD1_H_ +#define _SDD1_H_ +void S9xSetSDD1MemoryMap (uint32 bank, uint32 value); +void S9xResetSDD1 (); +void S9xSDD1PostLoadState (); +void S9xSDD1SaveLoggedData (); +void S9xSDD1LoadLoggedData (); +#endif diff --git a/src/sdd1emu.cpp b/src/sdd1emu.cpp new file mode 100644 index 0000000..3f97ee2 --- /dev/null +++ b/src/sdd1emu.cpp @@ -0,0 +1,414 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +/* S-DD1 decompressor + * + * Based on code and documentation by Andreas Naive, who deserves a great deal + * of thanks and credit for figuring this out. + * + * Andreas says: + * The author is greatly indebted with The Dumper, without whose help and + * patience providing him with real S-DD1 data the research had never been + * possible. He also wish to note that in the very beggining of his research, + * Neviksti had done some steps in the right direction. By last, the author is + * indirectly indebted to all the people that worked and contributed in the + * S-DD1 issue in the past. + */ + +#include +#include "port.h" +#include "sdd1emu.h" + +static int valid_bits; +static uint16 in_stream; +static uint8 *in_buf; +static uint8 bit_ctr[8]; +static uint8 context_states[32]; +static int context_MPS[32]; +static int bitplane_type; +static int high_context_bits; +static int low_context_bits; +static int prev_bits[8]; + +static struct { + uint8 code_size; + uint8 MPS_next; + uint8 LPS_next; +} evolution_table[] = { + /* 0 */ { 0,25,25}, + /* 1 */ { 0, 2, 1}, + /* 2 */ { 0, 3, 1}, + /* 3 */ { 0, 4, 2}, + /* 4 */ { 0, 5, 3}, + /* 5 */ { 1, 6, 4}, + /* 6 */ { 1, 7, 5}, + /* 7 */ { 1, 8, 6}, + /* 8 */ { 1, 9, 7}, + /* 9 */ { 2,10, 8}, + /* 10 */ { 2,11, 9}, + /* 11 */ { 2,12,10}, + /* 12 */ { 2,13,11}, + /* 13 */ { 3,14,12}, + /* 14 */ { 3,15,13}, + /* 15 */ { 3,16,14}, + /* 16 */ { 3,17,15}, + /* 17 */ { 4,18,16}, + /* 18 */ { 4,19,17}, + /* 19 */ { 5,20,18}, + /* 20 */ { 5,21,19}, + /* 21 */ { 6,22,20}, + /* 22 */ { 6,23,21}, + /* 23 */ { 7,24,22}, + /* 24 */ { 7,24,23}, + /* 25 */ { 0,26, 1}, + /* 26 */ { 1,27, 2}, + /* 27 */ { 2,28, 4}, + /* 28 */ { 3,29, 8}, + /* 29 */ { 4,30,12}, + /* 30 */ { 5,31,16}, + /* 31 */ { 6,32,18}, + /* 32 */ { 7,24,22} +}; + +static uint8 run_table[128] = { + 128, 64, 96, 32, 112, 48, 80, 16, 120, 56, 88, 24, 104, 40, 72, + 8, 124, 60, 92, 28, 108, 44, 76, 12, 116, 52, 84, 20, 100, 36, + 68, 4, 126, 62, 94, 30, 110, 46, 78, 14, 118, 54, 86, 22, 102, + 38, 70, 6, 122, 58, 90, 26, 106, 42, 74, 10, 114, 50, 82, 18, + 98, 34, 66, 2, 127, 63, 95, 31, 111, 47, 79, 15, 119, 55, 87, + 23, 103, 39, 71, 7, 123, 59, 91, 27, 107, 43, 75, 11, 115, 51, + 83, 19, 99, 35, 67, 3, 125, 61, 93, 29, 109, 45, 77, 13, 117, + 53, 85, 21, 101, 37, 69, 5, 121, 57, 89, 25, 105, 41, 73, 9, + 113, 49, 81, 17, 97, 33, 65, 1 +}; + +static inline uint8 GetCodeword(int bits){ + uint8 tmp; + + if(!valid_bits){ + in_stream|=*(in_buf++); + valid_bits=8; + } + in_stream<<=1; + valid_bits--; + in_stream^=0x8000; + if(in_stream&0x8000) return 0x80+(1<>8) | (0x7f>>bits); + in_stream<<=bits; + valid_bits-=bits; + if(valid_bits<0){ + in_stream |= (*(in_buf++))<<(-valid_bits); + valid_bits+=8; + } + return run_table[tmp]; +} + +static inline uint8 GolombGetBit(int code_size){ + if(!bit_ctr[code_size]) bit_ctr[code_size]=GetCodeword(code_size); + bit_ctr[code_size]--; + if(bit_ctr[code_size]==0x80){ + bit_ctr[code_size]=0; + return 2; /* secret code for 'last zero'. ones are always last. */ + } + return (bit_ctr[code_size]==0)?1:0; +} + +static inline uint8 ProbGetBit(uint8 context){ + uint8 state=context_states[context]; + uint8 bit=GolombGetBit(evolution_table[state].code_size); + + if(bit&1){ + context_states[context]=evolution_table[state].LPS_next; + if(state<2){ + context_MPS[context]^=1; + return context_MPS[context]; /* just inverted, so just return it */ + } else{ + return context_MPS[context]^1; /* we know bit is 1, so use a constant */ + } + } else if(bit){ + context_states[context]=evolution_table[state].MPS_next; + /* zero here, zero there, no difference so drop through. */ + } + return context_MPS[context]; /* we know bit is 0, so don't bother xoring */ +} + +static inline uint8 GetBit(uint8 cur_bitplane){ + uint8 bit; + + bit=ProbGetBit(((cur_bitplane&1)<<4) + | ((prev_bits[cur_bitplane]&high_context_bits)>>5) + | (prev_bits[cur_bitplane]&low_context_bits)); + + prev_bits[cur_bitplane] <<= 1; + prev_bits[cur_bitplane] |= bit; + return bit; +} + +void SDD1_decompress(uint8 *out, uint8 *in, int len){ + uint8 bit, i, plane; + uint8 byte1, byte2; + + if(len==0) len=0x10000; + + bitplane_type=in[0]>>6; + + switch(in[0]&0x30){ + case 0x00: + high_context_bits=0x01c0; + low_context_bits =0x0001; + break; + case 0x10: + high_context_bits=0x0180; + low_context_bits =0x0001; + break; + case 0x20: + high_context_bits=0x00c0; + low_context_bits =0x0001; + break; + case 0x30: + high_context_bits=0x0180; + low_context_bits =0x0003; + break; + } + + in_stream=(in[0]<<11) | (in[1]<<3); + valid_bits=5; + in_buf=in+2; + memset(bit_ctr, 0, sizeof(bit_ctr)); + memset(context_states, 0, sizeof(context_states)); + memset(context_MPS, 0, sizeof(context_MPS)); + memset(prev_bits, 0, sizeof(prev_bits)); + + switch(bitplane_type){ + case 0: + while(1) { + for(byte1=byte2=0, bit=0x80; bit; bit>>=1){ + if(GetBit(0)) byte1 |= bit; + if(GetBit(1)) byte2 |= bit; + } + *(out++)=byte1; + if(!--len) return; + *(out++)=byte2; + if(!--len) return; + } + break; + case 1: + i=plane=0; + while(1) { + for(byte1=byte2=0, bit=0x80; bit; bit>>=1){ + if(GetBit(plane)) byte1 |= bit; + if(GetBit(plane+1)) byte2 |= bit; + } + *(out++)=byte1; + if(!--len) return; + *(out++)=byte2; + if(!--len) return; + if(!(i+=32)) plane = (plane+2)&7; + } + break; + case 2: + i=plane=0; + while(1) { + for(byte1=byte2=0, bit=0x80; bit; bit>>=1){ + if(GetBit(plane)) byte1 |= bit; + if(GetBit(plane+1)) byte2 |= bit; + } + *(out++)=byte1; + if(!--len) return; + *(out++)=byte2; + if(!--len) return; + if(!(i+=32)) plane ^= 2; + } + break; + case 3: + do { + for(byte1=plane=0, bit=1; bit; bit<<=1, plane++){ + if(GetBit(plane)) byte1 |= bit; + } + *(out++)=byte1; + } while(--len); + break; + } +} + +static uint8 cur_plane; +static uint8 num_bits; +static uint8 next_byte; + +void SDD1_init(uint8 *in){ + bitplane_type=in[0]>>6; + + switch(in[0]&0x30){ + case 0x00: + high_context_bits=0x01c0; + low_context_bits =0x0001; + break; + case 0x10: + high_context_bits=0x0180; + low_context_bits =0x0001; + break; + case 0x20: + high_context_bits=0x00c0; + low_context_bits =0x0001; + break; + case 0x30: + high_context_bits=0x0180; + low_context_bits =0x0003; + break; + } + + in_stream=(in[0]<<11) | (in[1]<<3); + valid_bits=5; + in_buf=in+2; + memset(bit_ctr, 0, sizeof(bit_ctr)); + memset(context_states, 0, sizeof(context_states)); + memset(context_MPS, 0, sizeof(context_MPS)); + memset(prev_bits, 0, sizeof(prev_bits)); + + cur_plane=0; + num_bits=0; +} + +uint8 SDD1_get_byte(void){ + uint8 bit; + uint8 byte=0; + + switch(bitplane_type){ + case 0: + num_bits+=16; + if(num_bits&16){ + next_byte=0; + for(bit=0x80; bit; bit>>=1){ + if(GetBit(0)) byte |= bit; + if(GetBit(1)) next_byte |= bit; + } + return byte; + } else { + return next_byte; + } + + case 1: + num_bits+=16; + if(num_bits&16){ + next_byte=0; + for(bit=0x80; bit; bit>>=1){ + if(GetBit(cur_plane)) byte |= bit; + if(GetBit(cur_plane+1)) next_byte |= bit; + } + return byte; + } else { + if(!num_bits) cur_plane = (cur_plane+2)&7; + return next_byte; + } + + case 2: + num_bits+=16; + if(num_bits&16){ + next_byte=0; + for(bit=0x80; bit; bit>>=1){ + if(GetBit(cur_plane)) byte |= bit; + if(GetBit(cur_plane+1)) next_byte |= bit; + } + return byte; + } else { + if(!num_bits) cur_plane ^= 2; + return next_byte; + } + + case 3: + for(cur_plane=0, bit=1; bit; bit<<=1, cur_plane++){ + if(GetBit(cur_plane)) byte |= bit; + } + return byte; + + default: + /* should never happen */ + return 0; + } +} + diff --git a/src/sdd1emu.h b/src/sdd1emu.h new file mode 100644 index 0000000..e9d4785 --- /dev/null +++ b/src/sdd1emu.h @@ -0,0 +1,104 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#ifndef SDD1EMU_H +#define SDD1EMU_H + +/* for START_EXTERN_C/END_EXTERN_C */ +#include "port.h" + +extern "C" { + +void SDD1_decompress(uint8 *out, uint8 *in, int output_length); + +void SDD1_init(uint8 *in); +uint8 SDD1_get_byte(void); + +} + +#endif diff --git a/src/seta.cpp b/src/seta.cpp new file mode 100644 index 0000000..0600a07 --- /dev/null +++ b/src/seta.cpp @@ -0,0 +1,107 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#include "port.h" +#include "seta.h" + + +void (*SetSETA)(uint32, uint8)=&S9xSetST010; +uint8 (*GetSETA)(uint32)=&S9xGetST010; + +extern "C"{ +uint8 S9xGetSetaDSP(uint32 Address) +{ + return GetSETA(Address); +} + +void S9xSetSetaDSP(uint8 Byte, uint32 Address) +{ + SetSETA(Address, Byte); +} +} + diff --git a/src/seta.h b/src/seta.h new file mode 100644 index 0000000..f857636 --- /dev/null +++ b/src/seta.h @@ -0,0 +1,156 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ + +#ifndef NO_SETA +#ifndef _seta_h +#define _seta_h + +#include "port.h" + +#define ST_010 0x01 +#define ST_011 0x02 +#define ST_018 0x03 + + +extern "C" +{ +uint8 S9xGetSetaDSP(uint32 Address); +void S9xSetSetaDSP(uint8 byte,uint32 Address); +uint8 S9xGetST018(uint32 Address); +void S9xSetST018(uint8 Byte, uint32 Address); + +uint8 S9xGetST010(uint32 Address); +void S9xSetST010(uint32 Address, uint8 Byte); +uint8 S9xGetST011(uint32 Address); +void S9xSetST011(uint32 Address, uint8 Byte); +} + +extern void (*SetSETA)(uint32, uint8); +extern uint8 (*GetSETA)(uint32); + +typedef struct SETA_ST010_STRUCT +{ + uint8 input_params[16]; + uint8 output_params[16]; + uint8 op_reg; + uint8 execute; + bool8 control_enable; +} ST010_Regs; + +typedef struct SETA_ST011_STRUCT +{ + bool8 waiting4command; + uint8 status; + uint8 command; + uint32 in_count; + uint32 in_index; + uint32 out_count; + uint32 out_index; + uint8 parameters [512]; + uint8 output [512]; +} ST011_Regs; + +typedef struct SETA_ST018_STRUCT +{ + bool8 waiting4command; + uint8 status; + uint8 part_command; + uint8 pass; + uint32 command; + uint32 in_count; + uint32 in_index; + uint32 out_count; + uint32 out_index; + uint8 parameters [512]; + uint8 output [512]; +} ST018_Regs; + +#endif +#endif + diff --git a/src/seta010.cpp b/src/seta010.cpp new file mode 100644 index 0000000..c6dc266 --- /dev/null +++ b/src/seta010.cpp @@ -0,0 +1,751 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +//#include "port.h" +#include "memmap.h" +#include "seta.h" + +// Mode 7 scaling constants for all raster lines +const int16 ST010_M7Scale[176] = { + 0x0380, 0x0325, 0x02da, 0x029c, 0x0268, 0x023b, 0x0215, 0x01f3, + 0x01d5, 0x01bb, 0x01a3, 0x018e, 0x017b, 0x016a, 0x015a, 0x014b, + 0x013e, 0x0132, 0x0126, 0x011c, 0x0112, 0x0109, 0x0100, 0x00f8, + 0x00f0, 0x00e9, 0x00e3, 0x00dc, 0x00d6, 0x00d1, 0x00cb, 0x00c6, + 0x00c1, 0x00bd, 0x00b8, 0x00b4, 0x00b0, 0x00ac, 0x00a8, 0x00a5, + 0x00a2, 0x009e, 0x009b, 0x0098, 0x0095, 0x0093, 0x0090, 0x008d, + 0x008b, 0x0088, 0x0086, 0x0084, 0x0082, 0x0080, 0x007e, 0x007c, + 0x007a, 0x0078, 0x0076, 0x0074, 0x0073, 0x0071, 0x006f, 0x006e, + 0x006c, 0x006b, 0x0069, 0x0068, 0x0067, 0x0065, 0x0064, 0x0063, + 0x0062, 0x0060, 0x005f, 0x005e, 0x005d, 0x005c, 0x005b, 0x005a, + 0x0059, 0x0058, 0x0057, 0x0056, 0x0055, 0x0054, 0x0053, 0x0052, + 0x0051, 0x0051, 0x0050, 0x004f, 0x004e, 0x004d, 0x004d, 0x004c, + 0x004b, 0x004b, 0x004a, 0x0049, 0x0048, 0x0048, 0x0047, 0x0047, + 0x0046, 0x0045, 0x0045, 0x0044, 0x0044, 0x0043, 0x0042, 0x0042, + 0x0041, 0x0041, 0x0040, 0x0040, 0x003f, 0x003f, 0x003e, 0x003e, + 0x003d, 0x003d, 0x003c, 0x003c, 0x003b, 0x003b, 0x003a, 0x003a, + 0x003a, 0x0039, 0x0039, 0x0038, 0x0038, 0x0038, 0x0037, 0x0037, + 0x0036, 0x0036, 0x0036, 0x0035, 0x0035, 0x0035, 0x0034, 0x0034, + 0x0034, 0x0033, 0x0033, 0x0033, 0x0032, 0x0032, 0x0032, 0x0031, + 0x0031, 0x0031, 0x0030, 0x0030, 0x0030, 0x0030, 0x002f, 0x002f, + 0x002f, 0x002e, 0x002e, 0x002e, 0x002e, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002c, 0x002c, 0x002c, 0x002c, 0x002b, 0x002b, 0x002b +}; + +// H-DMA hack +bool seta_hack; + +//temporary Op04 requirement +#include + +#ifndef PI +#define PI 3.1415926535897932384626433832795 +#endif + +ST010_Regs ST010; + +uint8 S9xGetST010(uint32 Address) +{ + if(!(Address&0x80000)) + return 0x80; + + if((Address&0xFFF)==0x20) + return ST010.op_reg; + if ((Address&0xFFF)==0x21) + return ST010.execute; + return Memory.SRAM[Address&CPU.Memory_SRAMMask]; +} + +const int16 ST010_SinTable[256] = { + 0x0000, 0x0324, 0x0648, 0x096a, 0x0c8c, 0x0fab, 0x12c8, 0x15e2, + 0x18f9, 0x1c0b, 0x1f1a, 0x2223, 0x2528, 0x2826, 0x2b1f, 0x2e11, + 0x30fb, 0x33df, 0x36ba, 0x398c, 0x3c56, 0x3f17, 0x41ce, 0x447a, + 0x471c, 0x49b4, 0x4c3f, 0x4ebf, 0x5133, 0x539b, 0x55f5, 0x5842, + 0x5a82, 0x5cb3, 0x5ed7, 0x60eb, 0x62f1, 0x64e8, 0x66cf, 0x68a6, + 0x6a6d, 0x6c23, 0x6dc9, 0x6f5e, 0x70e2, 0x7254, 0x73b5, 0x7504, + 0x7641, 0x776b, 0x7884, 0x7989, 0x7a7c, 0x7b5c, 0x7c29, 0x7ce3, + 0x7d89, 0x7e1d, 0x7e9c, 0x7f09, 0x7f61, 0x7fa6, 0x7fd8, 0x7ff5, + 0x7fff, 0x7ff5, 0x7fd8, 0x7fa6, 0x7f61, 0x7f09, 0x7e9c, 0x7e1d, + 0x7d89, 0x7ce3, 0x7c29, 0x7b5c, 0x7a7c, 0x7989, 0x7884, 0x776b, + 0x7641, 0x7504, 0x73b5, 0x7254, 0x70e2, 0x6f5e, 0x6dc9, 0x6c23, + 0x6a6d, 0x68a6, 0x66cf, 0x64e8, 0x62f1, 0x60eb, 0x5ed7, 0x5cb3, + 0x5a82, 0x5842, 0x55f5, 0x539b, 0x5133, 0x4ebf, 0x4c3f, 0x49b4, + 0x471c, 0x447a, 0x41ce, 0x3f17, 0x3c56, 0x398c, 0x36ba, 0x33df, + 0x30fb, 0x2e11, 0x2b1f, 0x2826, 0x2528, 0x2223, 0x1f1a, 0x1c0b, + 0x18f8, 0x15e2, 0x12c8, 0x0fab, 0x0c8c, 0x096a, 0x0648, 0x0324, + 0x0000, -0x0324, -0x0648, -0x096b, -0x0c8c, -0x0fab, -0x12c8, -0x15e2, + -0x18f9, -0x1c0b, -0x1f1a, -0x2223, -0x2528, -0x2826, -0x2b1f, -0x2e11, + -0x30fb, -0x33df, -0x36ba, -0x398d, -0x3c56, -0x3f17, -0x41ce, -0x447a, + -0x471c, -0x49b4, -0x4c3f, -0x4ebf, -0x5133, -0x539b, -0x55f5, -0x5842, + -0x5a82, -0x5cb3, -0x5ed7, -0x60ec, -0x62f1, -0x64e8, -0x66cf, -0x68a6, + -0x6a6d, -0x6c23, -0x6dc9, -0x6f5e, -0x70e2, -0x7254, -0x73b5, -0x7504, + -0x7641, -0x776b, -0x7884, -0x7989, -0x7a7c, -0x7b5c, -0x7c29, -0x7ce3, + -0x7d89, -0x7e1d, -0x7e9c, -0x7f09, -0x7f61, -0x7fa6, -0x7fd8, -0x7ff5, + -0x7fff, -0x7ff5, -0x7fd8, -0x7fa6, -0x7f61, -0x7f09, -0x7e9c, -0x7e1d, + -0x7d89, -0x7ce3, -0x7c29, -0x7b5c, -0x7a7c, -0x7989, -0x7883, -0x776b, + -0x7641, -0x7504, -0x73b5, -0x7254, -0x70e2, -0x6f5e, -0x6dc9, -0x6c23, + -0x6a6d, -0x68a6, -0x66cf, -0x64e8, -0x62f1, -0x60eb, -0x5ed7, -0x5cb3, + -0x5a82, -0x5842, -0x55f5, -0x539a, -0x5133, -0x4ebf, -0x4c3f, -0x49b3, + -0x471c, -0x447a, -0x41cd, -0x3f17, -0x3c56, -0x398c, -0x36b9, -0x33de, + -0x30fb, -0x2e10, -0x2b1f, -0x2826, -0x2527, -0x2223, -0x1f19, -0x1c0b, + -0x18f8, -0x15e2, -0x12c8, -0x0fab, -0x0c8b, -0x096a, -0x0647, -0x0324}; + +const unsigned char ST010_ArcTan[32][32] = { + { 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80}, + { 0x80, 0xa0, 0xad, 0xb3, 0xb6, 0xb8, 0xb9, 0xba, 0xbb, 0xbb, 0xbc, 0xbc, 0xbd, 0xbd, 0xbd, 0xbd, + 0xbd, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbf, 0xbf, 0xbf, 0xbf}, + { 0x80, 0x93, 0xa0, 0xa8, 0xad, 0xb0, 0xb3, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xb9, 0xba, 0xba, 0xbb, + 0xbb, 0xbb, 0xbb, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd}, + { 0x80, 0x8d, 0x98, 0xa0, 0xa6, 0xaa, 0xad, 0xb0, 0xb1, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb7, 0xb8, + 0xb8, 0xb9, 0xb9, 0xba, 0xba, 0xba, 0xba, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbc, 0xbc, 0xbc, 0xbc}, + { 0x80, 0x8a, 0x93, 0x9a, 0xa0, 0xa5, 0xa8, 0xab, 0xad, 0xaf, 0xb0, 0xb2, 0xb3, 0xb4, 0xb5, 0xb5, + 0xb6, 0xb7, 0xb7, 0xb8, 0xb8, 0xb8, 0xb9, 0xb9, 0xb9, 0xba, 0xba, 0xba, 0xba, 0xba, 0xbb, 0xbb}, + { 0x80, 0x88, 0x90, 0x96, 0x9b, 0xa0, 0xa4, 0xa7, 0xa9, 0xab, 0xad, 0xaf, 0xb0, 0xb1, 0xb2, 0xb3, + 0xb4, 0xb4, 0xb5, 0xb6, 0xb6, 0xb6, 0xb7, 0xb7, 0xb8, 0xb8, 0xb8, 0xb9, 0xb9, 0xb9, 0xb9, 0xb9}, + { 0x80, 0x87, 0x8d, 0x93, 0x98, 0x9c, 0xa0, 0xa3, 0xa6, 0xa8, 0xaa, 0xac, 0xad, 0xae, 0xb0, 0xb0, + 0xb1, 0xb2, 0xb3, 0xb4, 0xb4, 0xb5, 0xb5, 0xb6, 0xb6, 0xb6, 0xb7, 0xb7, 0xb7, 0xb8, 0xb8, 0xb8}, + { 0x80, 0x86, 0x8b, 0x90, 0x95, 0x99, 0x9d, 0xa0, 0xa3, 0xa5, 0xa7, 0xa9, 0xaa, 0xac, 0xad, 0xae, + 0xaf, 0xb0, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3, 0xb4, 0xb4, 0xb5, 0xb5, 0xb6, 0xb6, 0xb6, 0xb7, 0xb7}, + { 0x80, 0x85, 0x8a, 0x8f, 0x93, 0x97, 0x9a, 0x9d, 0xa0, 0xa2, 0xa5, 0xa6, 0xa8, 0xaa, 0xab, 0xac, + 0xad, 0xae, 0xaf, 0xb0, 0xb0, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3, 0xb4, 0xb4, 0xb5, 0xb5, 0xb5, 0xb5}, + { 0x80, 0x85, 0x89, 0x8d, 0x91, 0x95, 0x98, 0x9b, 0x9e, 0xa0, 0xa0, 0xa4, 0xa6, 0xa7, 0xa9, 0xaa, + 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0, 0xb0, 0xb1, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3, 0xb4, 0xb4, 0xb4}, + { 0x80, 0x84, 0x88, 0x8c, 0x90, 0x93, 0x96, 0x99, 0x9b, 0x9e, 0xa0, 0xa2, 0xa4, 0xa5, 0xa7, 0xa8, + 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xaf, 0xb0, 0xb0, 0xb1, 0xb2, 0xb2, 0xb2, 0xb3, 0xb3}, + { 0x80, 0x84, 0x87, 0x8b, 0x8e, 0x91, 0x94, 0x97, 0x9a, 0x9c, 0x9e, 0xa0, 0xa2, 0xa3, 0xa5, 0xa6, + 0xa7, 0xa9, 0xaa, 0xab, 0xac, 0xac, 0xad, 0xae, 0xae, 0xaf, 0xb0, 0xb0, 0xb1, 0xb1, 0xb2, 0xb2}, + { 0x80, 0x83, 0x87, 0x8a, 0x8d, 0x90, 0x93, 0x96, 0x98, 0x9a, 0x9c, 0x9e, 0xa0, 0xa2, 0xa3, 0xa5, + 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xac, 0xad, 0xae, 0xae, 0xaf, 0xb0, 0xb0, 0xb0, 0xb1}, + { 0x80, 0x83, 0x86, 0x89, 0x8c, 0x8f, 0x92, 0x94, 0x96, 0x99, 0x9b, 0x9d, 0x9e, 0xa0, 0xa2, 0xa3, + 0xa4, 0xa5, 0xa7, 0xa8, 0xa9, 0xa9, 0xaa, 0xab, 0xac, 0xac, 0xad, 0xae, 0xae, 0xaf, 0xaf, 0xb0}, + { 0x80, 0x83, 0x86, 0x89, 0x8b, 0x8e, 0x90, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9d, 0x9e, 0xa0, 0xa1, + 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xaa, 0xab, 0xac, 0xad, 0xad, 0xae, 0xae, 0xaf}, + { 0x80, 0x83, 0x85, 0x88, 0x8b, 0x8d, 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9b, 0x9d, 0x9f, 0xa0, + 0xa1, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa8, 0xa9, 0xaa, 0xab, 0xab, 0xac, 0xad, 0xad, 0xae}, + { 0x80, 0x83, 0x85, 0x88, 0x8a, 0x8c, 0x8f, 0x91, 0x93, 0x95, 0x97, 0x99, 0x9a, 0x9c, 0x9d, 0x9f, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa5, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xaa, 0xab, 0xab, 0xac, 0xad}, + { 0x80, 0x82, 0x85, 0x87, 0x89, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x96, 0x97, 0x99, 0x9b, 0x9c, 0x9d, + 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa8, 0xa9, 0xaa, 0xaa, 0xab, 0xac}, + { 0x80, 0x82, 0x85, 0x87, 0x89, 0x8b, 0x8d, 0x8f, 0x91, 0x93, 0x95, 0x96, 0x98, 0x99, 0x9b, 0x9c, + 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa7, 0xa8, 0xa9, 0xa9, 0xaa, 0xab}, + { 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x95, 0x97, 0x98, 0x9a, 0x9b, + 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa6, 0xa7, 0xa8, 0xa8, 0xa9, 0xaa}, + { 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x91, 0x93, 0x94, 0x96, 0x97, 0x99, 0x9a, + 0x9b, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa5, 0xa6, 0xa7, 0xa7, 0xa8, 0xa9}, + { 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8b, 0x8d, 0x8f, 0x90, 0x92, 0x94, 0x95, 0x97, 0x98, 0x99, + 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa4, 0xa5, 0xa6, 0xa6, 0xa7, 0xa8}, + { 0x80, 0x82, 0x84, 0x86, 0x87, 0x89, 0x8b, 0x8d, 0x8e, 0x90, 0x91, 0x93, 0x94, 0x96, 0x97, 0x98, + 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa3, 0xa4, 0xa5, 0xa6, 0xa6, 0xa7}, + { 0x80, 0x82, 0x84, 0x85, 0x87, 0x89, 0x8a, 0x8c, 0x8e, 0x8f, 0x91, 0x92, 0x94, 0x95, 0x96, 0x98, + 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4, 0xa5, 0xa5, 0xa6}, + { 0x80, 0x82, 0x83, 0x85, 0x87, 0x88, 0x8a, 0x8c, 0x8d, 0x8f, 0x90, 0x92, 0x93, 0x94, 0x96, 0x97, + 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4, 0xa5, 0xa5}, + { 0x80, 0x82, 0x83, 0x85, 0x86, 0x88, 0x8a, 0x8b, 0x8d, 0x8e, 0x90, 0x91, 0x92, 0x94, 0x95, 0x96, + 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4, 0xa4}, + { 0x80, 0x82, 0x83, 0x85, 0x86, 0x88, 0x89, 0x8b, 0x8c, 0x8e, 0x8f, 0x90, 0x92, 0x93, 0x94, 0x95, + 0x96, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4}, + { 0x80, 0x82, 0x83, 0x85, 0x86, 0x87, 0x89, 0x8a, 0x8c, 0x8d, 0x8e, 0x90, 0x91, 0x92, 0x93, 0x95, + 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9e, 0x9f, 0xa0, 0xa1, 0xa1, 0xa2, 0xa3}, + { 0x80, 0x81, 0x83, 0x84, 0x86, 0x87, 0x89, 0x8a, 0x8b, 0x8d, 0x8e, 0x8f, 0x90, 0x92, 0x93, 0x94, + 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9e, 0x9f, 0xa0, 0xa1, 0xa1, 0xa2}, + { 0x80, 0x81, 0x83, 0x84, 0x86, 0x87, 0x88, 0x8a, 0x8b, 0x8c, 0x8e, 0x8f, 0x90, 0x91, 0x92, 0x93, + 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0x9f, 0xa0, 0xa1, 0xa1}, + { 0x80, 0x81, 0x83, 0x84, 0x85, 0x87, 0x88, 0x89, 0x8b, 0x8c, 0x8d, 0x8e, 0x90, 0x91, 0x92, 0x93, + 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0x9f, 0xa0, 0xa1}, + { 0x80, 0x81, 0x83, 0x84, 0x85, 0x87, 0x88, 0x89, 0x8a, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, 0x92, + 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9c, 0x9d, 0x9e, 0x9f, 0x9f, 0xa0}}; + +short ST010_Sin(short Theta) +{ + return ST010_SinTable[(Theta >> 8) & 0xff]; +} + +short ST010_Cos(short Theta) +{ + return ST010_SinTable[((Theta + 0x4000) >> 8) & 0xff]; +} + +void ST010_OP01(short x0, short y0, short &x1, short &y1, short &Quadrant, short &Theta) +{ + if ((x0 < 0) && (y0 < 0)) + { + x1 = -x0; + y1 = -y0; + Quadrant = -0x8000; + } + else if (x0 < 0) + { + x1 = y0; + y1 = -x0; + Quadrant = -0x4000; + } + else if (y0 < 0) + { + x1 = -y0; + y1 = x0; + Quadrant = 0x4000; + } + else + { + x1 = x0; + y1 = y0; + Quadrant = 0x0000; + } + + while ((x1 > 0x1f) || (y1 > 0x1f)) + { + if (x1 > 1) x1 >>= 1; + if (y1 > 1) y1 >>= 1; + } + + if (y1 == 0) Quadrant += 0x4000; + + Theta = (ST010_ArcTan[y1][x1] << 8) ^ Quadrant; +} + +void ST010_Scale(short Multiplier, short X0, short Y0, int &X1, int &Y1) +{ + X1 = X0 * Multiplier << 1; + Y1 = Y0 * Multiplier << 1; +} + +void ST010_Multiply(short Multiplicand, short Multiplier, int &Product) +{ + Product = Multiplicand * Multiplier << 1; +} + +void ST010_Rotate(short Theta, short X0, short Y0, short &X1, short &Y1) +{ + X1 = (Y0 * ST010_Sin(Theta) >> 15) + (X0 * ST010_Cos(Theta) >> 15); + Y1 = (Y0 * ST010_Cos(Theta) >> 15) - (X0 * ST010_Sin(Theta) >> 15); +} + +void SETA_Distance(short Y0, short X0, short &Distance) +{ + if (X0 < 0) X0 = -X0; + if (Y0 < 0) Y0 = -Y0; + Distance = ((X0 * 0x7af0) + 0x4000) >> 15; +} + +void ST010_SortDrivers(uint16 Positions, uint16 Places[32], uint16 Drivers[32]) +{ + bool Sorted; + uint16 Temp; + + if (Positions > 1) + do { + Sorted = true; + for (int i = 0; i < Positions - 1; i++) + if (Places[i] < Places[i + 1]) + { + Temp = Places[i + 1]; + Places[i + 1] = Places[i]; + Places[i] = Temp; + + Temp = Drivers[i + 1]; + Drivers[i + 1] = Drivers[i]; + Drivers[i] = Temp; + + Sorted = false; + } + Positions--; + } while (!Sorted); +} + +#define ST010_WORD(offset) (Memory.SRAM[offset + 1] << 8) | Memory.SRAM[offset] + +void S9xSetST010(uint32 Address, uint8 Byte) +{ + if(!(Address&0x80000)) + { + ST010.control_enable=TRUE; + return; + } + //printf("Write %06X:%02X\n", Address, Byte); + + if((Address &0xFFF) ==0x20 && ST010.control_enable) + ST010.op_reg=Byte; + if((Address &0xFFF) ==0x21 && ST010.control_enable) + ST010.execute=Byte; + else Memory.SRAM[Address&CPU.Memory_SRAMMask]=Byte; + + if(ST010.execute&0x80) + { + switch(ST010.op_reg) + { + // Sorts Driver Placements + // + // Input + // 0x0024-0x0025 : Positions + // 0x0040-0x007f : Places + // 0x0080-0x00ff : Drivers + // Output + // 0x0040-0x007f : Places + // 0x0080-0x00ff : Drivers + // + case 0x02: + { +#ifdef FAST_LSB_WORD_ACCESS + ST010_SortDrivers(*(short*)&SRAM[0x0024], (uint16*) (SRAM + 0x0040), (uint16*) (SRAM + 0x0080)); +#else + uint16 Places[32]; + uint16 Positions = ST010_WORD(0x0024); + int Pos, Offset; + + Offset = 0; + + for (Pos = 0; Pos < Positions; Pos++) + { + Places[Pos] = ST010_WORD(0x0040 + Offset); + Offset += 2; + } + + ST010_SortDrivers(Positions, Places, (uint16*) (SRAM + 0x0080)); + + Offset = 0; + + for (Pos = 0; Pos < Positions; Pos++) + { + SRAM[0x0040 + Offset]=(uint8)(Places[Pos]); + SRAM[0x0041 + Offset]=(uint8)(Places[Pos] >> 8); + Offset += 2; + } +#endif + break; + + } + + // Two Dimensional Coordinate Scale + // + // Input + // 0x0000-0x0001 : X0 (signed) + // 0x0002-0x0003 : Y0 (signed) + // 0x0004-0x0005 : Multiplier (signed) + // Output + // 0x0010-0x0013 : X1 (signed) + // 0x0014-0x0017 : Y1 (signed) + // + case 0x03: + { +#ifdef FAST_LSB_WORD_ACCESS + ST010_Scale(*(short*)&Memory.SRAM[0x0004], *(short*)&Memory.SRAM[0x0000], *(short*)&Memory.SRAM[0x0002], + (int&) Memory.SRAM[0x0010], (int&) Memory.SRAM[0x0014]); +#else + int x1, y1; + + ST010_Scale(ST010_WORD(0x0004), ST010_WORD(0x0000), ST010_WORD(0x0002), x1, y1); + + Memory.SRAM[0x0010]=(uint8)(x1); + Memory.SRAM[0x0011]=(uint8)(x1 >> 8); + Memory.SRAM[0x0012]=(uint8)(x1 >> 16); + Memory.SRAM[0x0013]=(uint8)(x1 >> 24); + Memory.SRAM[0x0014]=(uint8)(y1); + Memory.SRAM[0x0015]=(uint8)(y1 >> 8); + Memory.SRAM[0x0016]=(uint8)(y1 >> 16); + Memory.SRAM[0x0017]=(uint8)(y1 >> 24); +#endif + break; + } + + // 16-bit Multiplication + // + // Input + // 0x0000-0x0001 : Multiplcand (signed) + // 0x0002-0x0003 : Multiplier (signed) + // Output + // 0x0010-0x0013 : Product (signed) + // + case 0x06: + { +#ifdef FAST_LSB_WORD_ACCESS + ST010_Multiply(*(short*)&Memory.SRAM[0x0000], *(short*)&Memory.SRAM[0x0002], (int&) Memory.SRAM[0x0010]); +#else + int Product; + + ST010_Multiply(ST010_WORD(0x0000), ST010_WORD(0x0002), Product); + + Memory.SRAM[0x0010]=(uint8)(Product); + Memory.SRAM[0x0011]=(uint8)(Product >> 8); + Memory.SRAM[0x0012]=(uint8)(Product >> 16); + Memory.SRAM[0x0013]=(uint8)(Product >> 24); +#endif + break; + } + + // Mode 7 Raster Data Calculation + // + // Input + // 0x0000-0x0001 : Angle (signed) + // Output + // 0x00f0-0x024f : Mode 7 Matrix A + // 0x0250-0x03af : Mode 7 Matrix B + // 0x03b0-0x050f : Mode 7 Matrix C + // 0x0510-0x066f : Mode 7 Matrix D + // + case 0x07: + { + int16 data; + int32 offset = 0; + int16 Theta = ST010_WORD(0x0000); + + for (int32 line = 0; line < 176; line++) + { + // Calculate Mode 7 Matrix A/D data + data = ST010_M7Scale[line] * ST010_Cos(Theta) >> 15; + + Memory.SRAM[0x00f0 + offset]=(uint8)(data); + Memory.SRAM[0x00f1 + offset]=(uint8)(data >> 8); + Memory.SRAM[0x0510 + offset]=(uint8)(data); + Memory.SRAM[0x0511 + offset]=(uint8)(data >> 8); + + // Calculate Mode 7 Matrix B/C data + data = ST010_M7Scale[line] * ST010_Sin(Theta) >> 15; + + Memory.SRAM[0x0250 + offset]=(uint8)(data); + Memory.SRAM[0x0251 + offset]=(uint8)(data >> 8); + + if (data) data = ~data; + + Memory.SRAM[0x03b0 + offset]=(uint8)(data); + Memory.SRAM[0x03b1 + offset]=(uint8)(data >> 8); + + offset += 2; + } + + // Shift Angle for use with Lookup table + Memory.SRAM[0x00] = Memory.SRAM[0x01]; + Memory.SRAM[0x01] = 0x00; + + break; + } + + // Two dimensional Coordinate Rotation + // + // Input + // 0x0000-0x0001 : X0 (signed) + // 0x0002-0x0003 : Y0 (signed) + // 0x0004-0x0005 : Angle (signed) + // Output + // 0x0010-0x0011 : X1 (signed) + // 0x0012-0x0013 : Y1 (signed) + // + case 0x08: + { +#ifdef FAST_LSB_WORD_ACCESS + ST010_Rotate(*(short*)&Memory.SRAM[0x0004], *(short*)&Memory.SRAM[0x0000], *(short*)&Memory.SRAM[0x0002], + (short&) Memory.SRAM[0x0010], (short&) Memory.SRAM[0x0012]); +#else + short x1, y1; + + ST010_Rotate(ST010_WORD(0x0004), ST010_WORD(0x0000), ST010_WORD(0x0002), x1, y1); + + Memory.SRAM[0x0010]=(uint8)(x1); + Memory.SRAM[0x0011]=(uint8)(x1 >> 8); + Memory.SRAM[0x0012]=(uint8)(y1); + Memory.SRAM[0x0013]=(uint8)(y1 >> 8); +#endif + break; + } + + // Input + // 0x0000-0x0001 : DX (signed) + // 0x0002-0x0003 : DY (signed) + // Output + // 0x0010-0x0011 : Angle (signed) + // + case 0x01: + { + Memory.SRAM[0x0006] = Memory.SRAM[0x0002]; + Memory.SRAM[0x0007] = Memory.SRAM[0x0003]; + +#ifdef FAST_LSB_WORD_ACCESS + ST010_OP01(*(short*)&Memory.SRAM[0x0000], *(short*)&Memory.SRAM[0x0002], + (short&) Memory.SRAM[0x0000], (short&) Memory.SRAM[0x0002], + (short&) Memory.SRAM[0x0004], (short&) Memory.SRAM[0x0010]); +#else + short x1, y1, Quadrant, Theta; + + ST010_OP01(ST010_WORD(0x0000), ST010_WORD(0x0002), x1, y1, Quadrant, Theta); + + Memory.SRAM[0x0000]=(uint8)(x1); + Memory.SRAM[0x0001]=(uint8)(x1 >> 8); + Memory.SRAM[0x0002]=(uint8)(y1); + Memory.SRAM[0x0003]=(uint8)(y1 >> 8); + Memory.SRAM[0x0004]=(uint8)(Quadrant); + Memory.SRAM[0x0005]=(uint8)(Quadrant >> 8); + Memory.SRAM[0x0010]=(uint8)(Theta); + Memory.SRAM[0x0011]=(uint8)(Theta >> 8); +#endif + break; + } + + // calculate the vector length of (x,y) + case 0x04: + { + int16 square, x,y; +#ifdef FAST_LSB_WORD_ACCESS + x=*((int16*)Memory.SRAM); + y=*((int16*)&Memory.SRAM[2]); +#else + x=Memory.SRAM[0]|(Memory.SRAM[1]<<8); + y=Memory.SRAM[2]|(Memory.SRAM[3]<<8); +#endif + square=(int16)sqrt((double)(y*y+x*x)); + //SETA_Distance( x,y,square ); + +#ifdef FAST_LSB_WORD_ACCESS + *((int16*)&Memory.SRAM[0x10])=square; +#else + Memory.SRAM[0x10]=(uint8)(square); + Memory.SRAM[0x11]=(uint8)(square>>8); +#endif + break; + } + + // calculate AI orientation based on specific guidelines + case 0x05: + { + int dx,dy; + int16 a1,b1,c1; + uint16 o1; + + bool wrap=false; + + // target (x,y) coordinates + int16 ypos_max = ST010_WORD(0x00C0); + int16 xpos_max = ST010_WORD(0x00C2); + + // current coordinates and direction + int32 ypos = SRAM[0xC4]|(SRAM[0xC5]<<8)|(SRAM[0xC6]<<16)|(SRAM[0xC7]<<24); + int32 xpos = SRAM[0xC8]|(SRAM[0xC9]<<8)|(SRAM[0xCA]<<16)|(SRAM[0xCB]<<24); + uint16 rot = SRAM[0xCC]|(SRAM[0xCD]<<8); + + // physics + uint16 speed = ST010_WORD(0x00D4); + uint16 accel = ST010_WORD(0x00D6); + uint16 speed_max = ST010_WORD(0x00D8); + + // special condition acknowledgment + int16 system = ST010_WORD(0x00DA); + int16 flags = ST010_WORD(0x00DC); + + // new target coordinates + int16 ypos_new = ST010_WORD(0x00DE); + int16 xpos_new = ST010_WORD(0x00E0); + + // mask upper bit + xpos_new &= 0x7FFF; + + // get the current distance + dx = xpos_max-(xpos>>16); + dy = ypos_max-(ypos>>16); + + // quirk: clear and move in9 + SRAM[0xD2]=0xFF; + SRAM[0xD3]=0xFF; + SRAM[0xDA]=0; + SRAM[0xDB]=0; + + // grab the target angle + ST010_OP01(dy,dx,a1,b1,c1,(int16 &)o1); + + // check for wrapping + //if((o1<0x6000 && rot>0xA000) || + // (rot<0x6000 && o1>0xA000)) + //if(o10x8000) + { + o1+=0x8000; + rot+=0x8000; + wrap=true; + } + //o1=0x0000; + //rot=0xFF00; + + uint16 old_speed; + + old_speed = speed; + + // special case + if(abs(o1-rot)==0x8000) + { + speed = 0x100; + } + // slow down for sharp curves + else if(abs(o1-rot)>=0x1000) + { + uint32 slow = abs(o1-rot); + slow >>= 4; // scaling + speed -= slow; + } + // otherwise accelerate + else + { + speed += accel; + if(speed > speed_max) + { + // clip speed + speed = speed_max; + } + } + + // prevent negative/positive overflow + if(abs(old_speed-speed)>0x8000) { + if(old_speedrot && (o1-rot)>0x80) || + (o1=0x80) ) + { + if(o1rot) rot+=0x280; + } + + // turn off wrapping + if(wrap) rot-=0x8000; + + // now check the distances (store for later) + dx = (xpos_max<<16)-xpos; + dy = (ypos_max<<16)-ypos; + dx>>=16; + dy>>=16; + + // if we're in so many units of the target, signal it + if( ( system && (dy<=6 && dy>=-8) && (dx<=126 && dx>=-128)) || + (!system && (dx<=6 && dx>=-8) && (dy<=126 && dy>=-128)) ) + { + // announce our new destination and flag it + xpos_max = xpos_new&0x7FFF; + ypos_max = ypos_new; + flags |= 0x08; + } + + // update position + xpos -= (ST010_Cos(rot) * 0x400 >> 15) * (speed >> 8) << 1; + ypos -= (ST010_Sin(rot) * 0x400 >> 15) * (speed >> 8) << 1; + + // quirk: mask upper byte + xpos &= 0x1FFFFFFF; + ypos &= 0x1FFFFFFF; + + SRAM[0x00C0]=(uint8)(ypos_max); + SRAM[0x00C1]=(uint8)(ypos_max >> 8); + SRAM[0x00C2]=(uint8)(xpos_max); + SRAM[0x00C3]=(uint8)(xpos_max >> 8); + SRAM[0x00C4]=(uint8)(ypos); + SRAM[0x00C5]=(uint8)(ypos >> 8); + SRAM[0x00C6]=(uint8)(ypos >> 16); + SRAM[0x00C7]=(uint8)(ypos >> 24); + SRAM[0x00C8]=(uint8)(xpos); + SRAM[0x00C9]=(uint8)(xpos >> 8); + SRAM[0x00CA]=(uint8)(xpos >> 16); + SRAM[0x00CB]=(uint8)(xpos >> 24); + SRAM[0x00CC]=(uint8)(rot); + SRAM[0x00CD]=(uint8)(rot >> 8); + SRAM[0x00D4]=(uint8)(speed); + SRAM[0x00D5]=(uint8)(speed >> 8); + SRAM[0x00DC]=(uint8)(flags); + SRAM[0x00DD]=(uint8)(flags >> 8); + + break; + } + + default: + printf("Unknown Op\n"); + break; + } + + // lower signal: op processed + ST010.op_reg=0; + ST010.execute=0; + } +} + diff --git a/src/seta011.cpp b/src/seta011.cpp new file mode 100644 index 0000000..364e9ef --- /dev/null +++ b/src/seta011.cpp @@ -0,0 +1,233 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#include +#include "port.h" +#include "seta.h" +#include "memmap.h" + +ST011_Regs ST011; + +// shougi playboard +uint8 board[9][9]; + +// debug +static int line = 0; + +uint8 S9xGetST011(uint32 Address) +{ + uint8 t; + uint16 address = (uint16) Address & 0xFFFF; + + // line counter + line++; + + // status check + if (address == 0x01) + { + t = 0xFF; + } + // read directly from s-ram + else + { + t = Memory.SRAM[address]; + } + + // debug +// if(address<0x150) +// printf( "ST011 R: %06X %02X\n", Address, t); + + return t; +} + +void S9xSetST011(uint32 Address, uint8 Byte) +{ + uint16 address = (uint16) Address & 0xFFFF; + static bool reset = false; + + // debug + line++; + + if(!reset) + { + // bootup values + ST011.waiting4command = true; + reset = true; + } + + // debug +// if(address<0x150) +// printf( "ST011 W: %06X %02X\n", Address, Byte ); + + Memory.SRAM[address]=Byte; + + // op commands/data goes through this address + if(address==0x00) + { + // check for new commands + if (ST011.waiting4command) + { + ST011.waiting4command = false; + ST011.command = Byte; + ST011.in_index = 0; + ST011.out_index = 0; + switch(ST011.command) + { + case 0x01: ST011.in_count = 12*10+8; break; + case 0x02: ST011.in_count = 4; break; + case 0x04: ST011.in_count = 0; break; + case 0x05: ST011.in_count = 0; break; + case 0x06: ST011.in_count = 0; break; + case 0x07: ST011.in_count = 0; break; + case 0x0E: ST011.in_count = 0; break; + default: ST011.waiting4command=true; break; + } + } + else + { + ST011.parameters [ST011.in_index] = Byte; + ST011.in_index++; + } + } + + if (ST011.in_count==ST011.in_index) + { + // Actually execute the command + ST011.waiting4command = true; + ST011.out_index = 0; + switch (ST011.command) + { + // unknown: download playboard + case 0x01: + { + // 9x9 board data: top to bottom, left to right + // Values represent piece types and ownership + for( int lcv=0; lcv<9; lcv++ ) + memcpy( board[lcv], ST011.parameters+lcv*10, 9*1 ); + } + break; + + // unknown + case 0x02: break; + + // unknown + case 0x04: + { + // outputs + Memory.SRAM[0x12C] = 0x00; + //Memory.SRAM[0x12D] = 0x00; + Memory.SRAM[0x12E] = 0x00; + } + break; + + // unknown + case 0x05: + { + // outputs + Memory.SRAM[0x12C] = 0x00; + //Memory.SRAM[0x12D] = 0x00; + Memory.SRAM[0x12E] = 0x00; + } + break; + + // unknown + case 0x06: break; + case 0x07: break; + + // unknown + case 0x0E: + { + // outputs + Memory.SRAM[0x12C] = 0x00; + Memory.SRAM[0x12D] = 0x00; + } + break; + } + } +} + diff --git a/src/seta018.cpp b/src/seta018.cpp new file mode 100644 index 0000000..5390a35 --- /dev/null +++ b/src/seta018.cpp @@ -0,0 +1,255 @@ +/******************************************************************************* + Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + + (c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and + Jerremy Koot (jkoot@snes9x.com) + + (c) Copyright 2001 - 2004 John Weidman (jweidman@slip.net) + + (c) Copyright 2002 - 2004 Brad Jorsch (anomie@users.sourceforge.net), + funkyass (funkyass@spam.shaw.ca), + Joel Yliluoma (http://iki.fi/bisqwit/) + Kris Bleakley (codeviolation@hotmail.com), + Matthew Kendora, + Nach (n-a-c-h@users.sourceforge.net), + Peter Bortas (peter@bortas.org) and + zones (kasumitokoduck@yahoo.com) + + C4 x86 assembler and some C emulation code + (c) Copyright 2000 - 2003 zsKnight (zsknight@zsnes.com), + _Demo_ (_demo_@zsnes.com), and Nach + + C4 C++ code + (c) Copyright 2003 Brad Jorsch + + DSP-1 emulator code + (c) Copyright 1998 - 2004 Ivar (ivar@snes9x.com), _Demo_, Gary Henderson, + John Weidman, neviksti (neviksti@hotmail.com), + Kris Bleakley, Andreas Naive + + DSP-2 emulator code + (c) Copyright 2003 Kris Bleakley, John Weidman, neviksti, Matthew Kendora, and + Lord Nightmare (lord_nightmare@users.sourceforge.net + + OBC1 emulator code + (c) Copyright 2001 - 2004 zsKnight, pagefault (pagefault@zsnes.com) and + Kris Bleakley + Ported from x86 assembler to C by sanmaiwashi + + SPC7110 and RTC C++ emulator code + (c) Copyright 2002 Matthew Kendora with research by + zsKnight, John Weidman, and Dark Force + + S-DD1 C emulator code + (c) Copyright 2003 Brad Jorsch with research by + Andreas Naive and John Weidman + + S-RTC C emulator code + (c) Copyright 2001 John Weidman + + ST010 C++ emulator code + (c) Copyright 2003 Feather, Kris Bleakley, John Weidman and Matthew Kendora + + Super FX x86 assembler emulator code + (c) Copyright 1998 - 2003 zsKnight, _Demo_, and pagefault + + Super FX C emulator code + (c) Copyright 1997 - 1999 Ivar, Gary Henderson and John Weidman + + + SH assembler code partly based on x86 assembler code + (c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se) + + + Specific ports contains the works of other authors. See headers in + individual files. + + Snes9x homepage: http://www.snes9x.com + + Permission to use, copy, modify and distribute Snes9x in both binary and + source form, for non-commercial purposes, is hereby granted without fee, + providing that this license information and copyright notice appear with + all copies and any derived work. + + This software is provided 'as-is', without any express or implied + warranty. In no event shall the authors be held liable for any damages + arising from the use of this software. + + Snes9x is freeware for PERSONAL USE only. Commercial users should + seek permission of the copyright holders first. Commercial use includes + charging money for Snes9x or software derived from Snes9x. + + The copyright holders request that bug fixes and improvements to the code + should be forwarded to them so everyone can benefit from the modifications + in future versions. + + Super NES and Super Nintendo Entertainment System are trademarks of + Nintendo Co., Limited and its subsidiary companies. +*******************************************************************************/ +#include "memmap.h" +#include "seta.h" +//#include "port.h" + +ST018_Regs ST018; + +static int line; // line counter + +extern "C"{ +uint8 S9xGetST018(uint32 Address) +{ + uint8 t = 0; + uint16 address = (uint16) Address & 0xFFFF; + + line++; + + // these roles may be flipped + // op output + if (address == 0x3804) + { + if (ST018.out_count) + { + t = (uint8) ST018.output [ST018.out_index]; + ST018.out_index++; + if (ST018.out_count==ST018.out_index) + ST018.out_count=0; + } + else + t = 0x81; + } + // status register + else if (address == 0x3800) + t = ST018.status; + + printf( "ST018 R: %06X %02X\n", Address, t); + + return t; +} + +void S9xSetST018(uint8 Byte, uint32 Address) +{ + uint16 address = (uint16) Address&0xFFFF; + static bool reset = false; + + printf( "ST018 W: %06X %02X\n", Address, Byte ); + + line++; + + if (!reset) + { + // bootup values + ST018.waiting4command = true; + ST018.part_command = 0; + reset = true; + } + + Memory.SRAM[address]=Byte; + + // default status for now + ST018.status = 0x00; + + // op data goes through this address + if (address==0x3804) + { + // check for new commands: 3 bytes length + if(ST018.waiting4command && ST018.part_command==2) + { + ST018.waiting4command = false; + ST018.command <<= 8; + ST018.command |= Byte; + ST018.in_index = 0; + ST018.out_index = 0; + ST018.part_command = 0; // 3-byte commands + ST018.pass = 0; // data streams into the chip + switch(ST018.command & 0xFFFFFF) + { + case 0x0100: ST018.in_count = 0; break; + case 0xFF00: ST018.in_count = 0; break; + default: ST018.waiting4command = true; break; + } + } + else if(ST018.waiting4command) + { + // 3-byte commands + ST018.part_command++; + ST018.command <<= 8; + ST018.command |= Byte; + } + } + // extra parameters + else if (address==0x3802) + { + ST018.parameters[ST018.in_index] = Byte; + ST018.in_index++; + } + + if (ST018.in_count==ST018.in_index) + { + // Actually execute the command + ST018.waiting4command = true; + ST018.in_index = 0; + ST018.out_index = 0; + switch (ST018.command) + { + // hardware check? + case 0x0100: + ST018.waiting4command = false; + ST018.pass++; + if (ST018.pass==1) + { + ST018.in_count = 1; + ST018.out_count = 2; + + // Overload's research + ST018.output[0x00] = 0x81; + ST018.output[0x01] = 0x81; + } + else + { + //ST018.in_count = 1; + ST018.out_count = 3; + + // no reason to change this + //ST018.output[0x00] = 0x81; + //ST018.output[0x01] = 0x81; + ST018.output[0x02] = 0x81; + + // done processing requests + if (ST018.pass==3) + ST018.waiting4command = true; + } + break; + + // unknown: feels like a security detection + // format identical to 0x0100 + case 0xFF00: + ST018.waiting4command = false; + ST018.pass++; + if (ST018.pass==1) + { + ST018.in_count = 1; + ST018.out_count = 2; + + // Overload's research + ST018.output[0x00] = 0x81; + ST018.output[0x01] = 0x81; + } + else + { + //ST018.in_count = 1; + ST018.out_count = 3; + + // no reason to change this + //ST018.output[0x00] = 0x81; + //ST018.output[0x01] = 0x81; + ST018.output[0x02] = 0x81; + + // done processing requests + if (ST018.pass==3) + ST018.waiting4command = true; + } + break; + } + } +} +} + diff --git a/src/setpcbase.s b/src/setpcbase.s new file mode 100644 index 0000000..6f965ae --- /dev/null +++ b/src/setpcbase.s @@ -0,0 +1,85 @@ +asm_S9xSetPCBase: + .file 1 "os9x_asm_cpu.cpp" + .loc 1 16 0 + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 0, uses_anonymous_args = 0 + + + MOV R1,R0,LSR #MEMMAP_SHIFT + @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so + @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF + @ so AND MEMMAP_MASK is BIC 0xFF000 + BIC R1,R1,#0xFF000 + bic r0, r0, #0xff0000 + + @ R2 <= Map[block] (GetAddress) + LDR R2,[reg_cpu_var,#Map_ofs] + + LDR R2,[R2,R1,LSL #2] + CMP R2,#MAP_LAST + BLO SPCSpecial @ special + + mov regpcbase, r2 + add rpc, r2, r0 + str rpc, [reg_cpu_var, #PC_ofs] + str regpcbase, [reg_cpu_var, #PCBase_ofs] + + bx r3 + + +SPCSpecial: + + LDR PC,[PC,R2,LSL #2] + MOV R0,R0 @ nop, for align + + .long SPC_PPU + .long SPCDefault + .long SPCDefault + .long SPCDefault + .long SPCDefault + .long SPCDefault + .long SPCDefault + .long SPCDefault + .long SPCDefault + .long SPCDefault + .long SPCDefault + .long SPCDefault +/* + MAP_PPU 0 + MAP_CPU 1 + MAP_DSP 2 + MAP_LOROM_SRAM 3 + MAP_HIROM_SRAM 4 + MAP_NONE 5 + MAP_DEBUG 6 + MAP_C4 7 + MAP_BWRAM 8 + MAP_BWRAM_BITMAP 9 + MAP_BWRAM_BITMAP2 10 + MAP_SA1RAM 11 + MAP_LAST 12 +*/ + +vMemory: + .word Memory +.equ _fillram, 20 + +SPC_PPU: + @CPU.PCBase = Memory.FillRAM - 0x2000; + @CPU.PC = CPU.PCBase + (Address & 0xffff); + + ldr r1, vMemory + ldr r2, [r1, #_fillram] + sub r2, r2, #0x2000 + + mov regpcbase, r2 + add rpc, r2, r0 + str rpc, [reg_cpu_var, #PC_ofs] + str regpcbase, [reg_cpu_var, #PCBase_ofs] + + @return; + bx r3 + @------------------- + +SPCDefault: + bx r3 diff --git a/src/snaporig.cpp b/src/snaporig.cpp new file mode 100644 index 0000000..833e1f9 --- /dev/null +++ b/src/snaporig.cpp @@ -0,0 +1,414 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include +#include +#include + +#if defined(__unix) || defined(__linux) || defined(__sun) || defined(__DJGPP) +//#include +#include +#include +#endif + +#include "snapshot.h" +#include "snaporig.h" +#include "memmap.h" +#include "snes9x.h" +#include "65c816.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "apu.h" +#include "soundux.h" + +struct SOrigPPU OrigPPU; +struct SOrigDMA OrigDMA [8]; +struct SOrigRegisters OrigRegisters; +struct SOrigCPUState OrigCPU; +struct SOrigAPU OrigAPU; +SOrigSoundData OrigSoundData; +struct SOrigAPURegisters OrigAPURegisters; +char ROMFilename [1025]; + +static int ReadOrigSnapshot (STREAM); + +bool8_32 S9xLoadOrigSnapshot (const char *filename) +{ + STREAM snapshot = NULL; + if (S9xOpenSnapshotFile (filename, TRUE, &snapshot)) + { + int result; + if ((result = ReadOrigSnapshot (snapshot)) != SUCCESS) + { + S9xCloseSnapshotFile (snapshot); + return (FALSE); + } + S9xCloseSnapshotFile (snapshot); + return (TRUE); + } + return (FALSE); +} + +#ifdef _SNESPPC +#pragma warning(disable : 4018) +#endif +static int ReadBlock (const char *key, void *block, int max_len, STREAM snap) +{ + char buffer [20]; + int len = 0; + int rem = 0; + + if (READ_STREAM (buffer, 11, snap) != 11 || + strncmp (buffer, key, 4) != 0 || + (len = atoi (&buffer [4])) == 0) + return (WRONG_FORMAT); + + if (len > max_len) + { + rem = len - max_len; + len = max_len; + } + if (READ_STREAM (block, len, snap) != len) + return (WRONG_FORMAT); + + if (rem) + { + char *junk = new char [rem]; + READ_STREAM (junk, rem, snap); + delete junk; + } + + return (SUCCESS); +} + +static int ReadOrigSnapshot (STREAM snap) +{ + char buffer [_MAX_PATH]; + char rom_filename [_MAX_PATH]; + int result; + int i; + int j; + + int version; + int len = strlen (ORIG_SNAPSHOT_MAGIC) + 1 + 4 + 1; + if (READ_STREAM (buffer, len, snap) != len) + return (WRONG_FORMAT); + if (strncmp (buffer, ORIG_SNAPSHOT_MAGIC, strlen (ORIG_SNAPSHOT_MAGIC)) != 0) + return (WRONG_FORMAT); + if ((version = atoi (&buffer [strlen (SNAPSHOT_MAGIC) + 1])) > ORIG_SNAPSHOT_VERSION) + return (WRONG_VERSION); + + if ((result = ReadBlock ("NAM:", rom_filename, _MAX_PATH, snap)) != SUCCESS) + return (result); + + if ((result = ReadBlock ("HiR:", buffer, 0x41, snap)) != SUCCESS) + return (result); + + if (strcasecmp (rom_filename, Memory.ROMFilename) != 0 && + strcasecmp (S9xBasename (rom_filename), S9xBasename (Memory.ROMFilename)) != 0) + { + S9xMessage (S9X_WARNING, S9X_FREEZE_ROM_NAME, + "Current loaded ROM image doesn't match that required by freeze-game file."); + } + + S9xReset (); + S9xSetSoundMute (TRUE); + if ((result = ReadBlock ("CPU:", &OrigCPU, sizeof (OrigCPU), snap)) != SUCCESS) + return (result); + OrigCPU.FastROMSpeed = OrigCPU.FastROMSpeed_old; + Memory.FixROMSpeed (); + if (version == 3) + { + OrigCPU.Cycles = OrigCPU.Cycles_old; + OrigCPU.NextEvent = OrigCPU.NextEvent_old; + OrigCPU.V_Counter = OrigCPU.V_Counter_old; + OrigCPU.MemSpeed = OrigCPU.MemSpeed_old; + OrigCPU.MemSpeedx2 = OrigCPU.MemSpeedx2_old; + OrigCPU.FastROMSpeed = OrigCPU.FastROMSpeed_old; + } + CPU.Flags = OrigCPU.Flags; + CPU.BranchSkip = OrigCPU.BranchSkip; + CPU.NMIActive = OrigCPU.NMIActive; + CPU.IRQActive = OrigCPU.IRQActive; + CPU.WaitingForInterrupt = OrigCPU.WaitingForInterrupt; + CPU.WhichEvent = OrigCPU.WhichEvent; + CPU.Cycles = OrigCPU.Cycles; + CPU.NextEvent = OrigCPU.NextEvent; + CPU.V_Counter = OrigCPU.V_Counter; + CPU.MemSpeed = OrigCPU.MemSpeed; + CPU.MemSpeedx2 = OrigCPU.MemSpeedx2; + CPU.FastROMSpeed = OrigCPU.FastROMSpeed; + + if ((result = ReadBlock ("REG:", &OrigRegisters, sizeof (OrigRegisters), snap)) != SUCCESS) + return (result); + + Registers = *(struct SRegisters *) &OrigRegisters; + + if ((result = ReadBlock ("PPU:", &OrigPPU, sizeof (OrigPPU), snap)) != SUCCESS) + return (result); + + if (version == 2) + { + OrigPPU.OBJNameSelect = OrigPPU.OBJNameSelect_old << 13; + OrigPPU.OBJNameBase <<= 1; + OrigPPU.OBJNameSelect <<= 13; + } + PPU.BGMode = OrigPPU.BGMode; + PPU.BG3Priority = OrigPPU.BG3Priority; + PPU.Brightness = OrigPPU.Brightness; + + PPU.VMA.High = OrigPPU.VMA.High; + PPU.VMA.Increment = OrigPPU.VMA.Increment; + PPU.VMA.Address = OrigPPU.VMA.Address; + PPU.VMA.Mask1 = OrigPPU.VMA.Mask1; + PPU.VMA.FullGraphicCount = OrigPPU.VMA.FullGraphicCount; + PPU.VMA.Shift = OrigPPU.VMA.Shift; + + for (i = 0; i < 4; i++) + { + PPU.BG[i].SCBase = OrigPPU.BG[i].SCBase; + PPU.BG[i].VOffset = OrigPPU.BG[i].VOffset; + PPU.BG[i].HOffset = OrigPPU.BG[i].HOffset; + PPU.BG[i].BGSize = OrigPPU.BG[i].BGSize; + PPU.BG[i].NameBase = OrigPPU.BG[i].NameBase; + PPU.BG[i].SCSize = OrigPPU.BG[i].SCSize; + } + + PPU.CGFLIP = OrigPPU.CGFLIP; + for (i = 0; i < 256; i++) + PPU.CGDATA [i] = OrigPPU.CGDATA [i]; + PPU.FirstSprite = OrigPPU.FirstSprite; + for (i = 0; i < 128; i++) + { + PPU.OBJ[i].HPos = OrigPPU.OBJ [i].HPos; + PPU.OBJ[i].VPos = OrigPPU.OBJ [i].VPos; + PPU.OBJ[i].Name = OrigPPU.OBJ [i].Name; + PPU.OBJ[i].VFlip = OrigPPU.OBJ [i].VFlip; + PPU.OBJ[i].HFlip = OrigPPU.OBJ [i].HFlip; + PPU.OBJ[i].Priority = OrigPPU.OBJ [i].Priority; + PPU.OBJ[i].Palette = OrigPPU.OBJ [i].Palette; + PPU.OBJ[i].Size = OrigPPU.OBJ [i].Size; + } + PPU.OAMPriorityRotation = OrigPPU.OAMPriorityRotation; + PPU.OAMAddr = OrigPPU.OAMAddr; + + PPU.OAMFlip = OrigPPU.OAMFlip; + PPU.OAMTileAddress = OrigPPU.OAMTileAddress; + PPU.IRQVBeamPos = OrigPPU.IRQVBeamPos; + PPU.IRQHBeamPos = OrigPPU.IRQHBeamPos; + PPU.VBeamPosLatched = OrigPPU.VBeamPosLatched; + PPU.HBeamPosLatched = OrigPPU.HBeamPosLatched; + + PPU.HBeamFlip = OrigPPU.HBeamFlip; + PPU.VBeamFlip = OrigPPU.VBeamFlip; + PPU.HVBeamCounterLatched = OrigPPU.HVBeamCounterLatched; + + PPU.MatrixA = OrigPPU.MatrixA; + PPU.MatrixB = OrigPPU.MatrixB; + PPU.MatrixC = OrigPPU.MatrixC; + PPU.MatrixD = OrigPPU.MatrixD; + PPU.CentreX = OrigPPU.CentreX; + PPU.CentreY = OrigPPU.CentreY; + PPU.Joypad1ButtonReadPos = OrigPPU.Joypad1ButtonReadPos; + PPU.Joypad2ButtonReadPos = OrigPPU.Joypad2ButtonReadPos; + PPU.Joypad3ButtonReadPos = OrigPPU.Joypad3ButtonReadPos; + + PPU.CGADD = OrigPPU.CGADD; + PPU.FixedColourRed = OrigPPU.FixedColourRed; + PPU.FixedColourGreen = OrigPPU.FixedColourGreen; + PPU.FixedColourBlue = OrigPPU.FixedColourBlue; + PPU.SavedOAMAddr = OrigPPU.SavedOAMAddr; + PPU.ScreenHeight = OrigPPU.ScreenHeight; + PPU.WRAM = OrigPPU.WRAM; + PPU.ForcedBlanking = OrigPPU.ForcedBlanking; + PPU.OBJNameSelect = OrigPPU.OBJNameSelect; + PPU.OBJSizeSelect = OrigPPU.OBJSizeSelect; + PPU.OBJNameBase = OrigPPU.OBJNameBase; + PPU.OAMReadFlip = OrigPPU.OAMReadFlip; + memmove (PPU.OAMData, OrigPPU.OAMData, sizeof (PPU.OAMData)); + PPU.VTimerEnabled = OrigPPU.VTimerEnabled; + PPU.HTimerEnabled = OrigPPU.HTimerEnabled; + PPU.HTimerPosition = OrigPPU.HTimerPosition; + PPU.Mosaic = OrigPPU.Mosaic; + memmove (PPU.BGMosaic, OrigPPU.BGMosaic, sizeof (PPU.BGMosaic)); + PPU.Mode7HFlip = OrigPPU.Mode7HFlip; + PPU.Mode7VFlip = OrigPPU.Mode7VFlip; + PPU.Mode7Repeat = OrigPPU.Mode7Repeat; + PPU.Window1Left = OrigPPU.Window1Left; + PPU.Window1Right = OrigPPU.Window1Right; + PPU.Window2Left = OrigPPU.Window2Left; + PPU.Window2Right = OrigPPU.Window2Right; + for (i = 0; i < 6; i++) + { + PPU.ClipWindowOverlapLogic [i] = OrigPPU.ClipWindowOverlapLogic [i]; + PPU.ClipWindow1Enable [i] = OrigPPU.ClipWindow1Enable [i]; + PPU.ClipWindow2Enable [i] = OrigPPU.ClipWindow2Enable [i]; + PPU.ClipWindow1Inside [i] = OrigPPU.ClipWindow1Inside [i]; + PPU.ClipWindow2Inside [i] = OrigPPU.ClipWindow2Inside [i]; + } + PPU.CGFLIPRead = OrigPPU.CGFLIPRead; + PPU.Need16x8Mulitply = OrigPPU.Need16x8Mulitply; + + IPPU.ColorsChanged = TRUE; + IPPU.OBJChanged = TRUE; + S9xFixColourBrightness (); + IPPU.RenderThisFrame = FALSE; + + if ((result = ReadBlock ("DMA:", OrigDMA, sizeof (OrigDMA), snap)) != SUCCESS) + return (result); + + for (i = 0; i < 8; i++) + { + DMA[i].TransferDirection = OrigDMA[i].TransferDirection; + DMA[i].AAddressFixed = OrigDMA[i].AAddressFixed; + DMA[i].AAddressDecrement = OrigDMA[i].AAddressDecrement; + DMA[i].TransferMode = OrigDMA[i].TransferMode; + DMA[i].ABank = OrigDMA[i].ABank; + DMA[i].AAddress = OrigDMA[i].AAddress; + DMA[i].Address = OrigDMA[i].Address; + DMA[i].BAddress = OrigDMA[i].BAddress; + DMA[i].TransferBytes = OrigDMA[i].TransferBytes; + DMA[i].HDMAIndirectAddressing = OrigDMA[i].HDMAIndirectAddressing; + DMA[i].IndirectAddress = OrigDMA[i].IndirectAddress; + DMA[i].IndirectBank = OrigDMA[i].IndirectBank; + DMA[i].Repeat = OrigDMA[i].Repeat; + DMA[i].LineCount = OrigDMA[i].LineCount; + DMA[i].FirstLine = OrigDMA[i].FirstLine; + } + + if ((result = ReadBlock ("VRA:", Memory.VRAM, 0x10000, snap)) != SUCCESS) + return (result); + if ((result = ReadBlock ("RAM:", Memory.RAM, 0x20000, snap)) != SUCCESS) + return (result); + if ((result = ReadBlock ("SRA:", ::SRAM, 0x10000, snap)) != SUCCESS) + return (result); + if ((result = ReadBlock ("FIL:", Memory.FillRAM, 0x8000, snap)) != SUCCESS) + return (result); + if (ReadBlock ("APU:", &OrigAPU, sizeof (OrigAPU), snap) == SUCCESS) + { + APU = *(struct SAPU *) &OrigAPU; + + if ((result = ReadBlock ("ARE:", &OrigAPURegisters, + sizeof (OrigAPURegisters), snap)) != SUCCESS) + return (result); + APURegisters = *(struct SAPURegisters *) &OrigAPURegisters; + if ((result = ReadBlock ("ARA:", IAPU.RAM, 0x10000, snap)) != SUCCESS) + return (result); + if ((result = ReadBlock ("SOU:", &OrigSoundData, + sizeof (SOrigSoundData), snap)) != SUCCESS) + return (result); + + SoundData.master_volume_left = OrigSoundData.master_volume_left; + SoundData.master_volume_right = OrigSoundData.master_volume_right; + SoundData.echo_volume_left = OrigSoundData.echo_volume_left; + SoundData.echo_volume_right = OrigSoundData.echo_volume_right; + SoundData.echo_enable = OrigSoundData.echo_enable; + SoundData.echo_feedback = OrigSoundData.echo_feedback; + SoundData.echo_ptr = OrigSoundData.echo_ptr; + SoundData.echo_buffer_size = OrigSoundData.echo_buffer_size; + SoundData.echo_write_enabled = OrigSoundData.echo_write_enabled; + SoundData.echo_channel_enable = OrigSoundData.echo_channel_enable; + SoundData.pitch_mod = OrigSoundData.pitch_mod; + + for (i = 0; i < 3; i++) + SoundData.dummy [i] = OrigSoundData.dummy [i]; + for (i = 0; i < NUM_CHANNELS; i++) + { + SoundData.channels [i].state = OrigSoundData.channels [i].state; + SoundData.channels [i].type = OrigSoundData.channels [i].type; + SoundData.channels [i].volume_left = OrigSoundData.channels [i].volume_left; + SoundData.channels [i].volume_right = OrigSoundData.channels [i].volume_right; + SoundData.channels [i].hertz = OrigSoundData.channels [i].frequency; + SoundData.channels [i].count = OrigSoundData.channels [i].count; + SoundData.channels [i].loop = OrigSoundData.channels [i].loop; + SoundData.channels [i].envx = OrigSoundData.channels [i].envx; + SoundData.channels [i].left_vol_level = OrigSoundData.channels [i].left_vol_level; + SoundData.channels [i].right_vol_level = OrigSoundData.channels [i].right_vol_level; + SoundData.channels [i].envx_target = OrigSoundData.channels [i].envx_target; + SoundData.channels [i].env_error = OrigSoundData.channels [i].env_error; + SoundData.channels [i].erate = OrigSoundData.channels [i].erate; + SoundData.channels [i].direction = OrigSoundData.channels [i].direction; + SoundData.channels [i].attack_rate = OrigSoundData.channels [i].attack_rate; + SoundData.channels [i].decay_rate = OrigSoundData.channels [i].decay_rate; + SoundData.channels [i].sustain_rate = OrigSoundData.channels [i].sustain_rate; + SoundData.channels [i].release_rate = OrigSoundData.channels [i].release_rate; + SoundData.channels [i].sustain_level = OrigSoundData.channels [i].sustain_level; + SoundData.channels [i].sample = OrigSoundData.channels [i].sample; + for (j = 0; j < 16; j++) + SoundData.channels [i].decoded [j] = OrigSoundData.channels [i].decoded [j]; + + for (j = 0; j < 2; j++) + SoundData.channels [i].previous [j] = OrigSoundData.channels [i].previous [j]; + + SoundData.channels [i].sample_number = OrigSoundData.channels [i].sample_number; + SoundData.channels [i].last_block = OrigSoundData.channels [i].last_block; + SoundData.channels [i].needs_decode = OrigSoundData.channels [i].needs_decode; + SoundData.channels [i].block_pointer = OrigSoundData.channels [i].block_pointer; + SoundData.channels [i].sample_pointer = OrigSoundData.channels [i].sample_pointer; + SoundData.channels [i].mode = OrigSoundData.channels [i].mode; + } + + S9xSetSoundMute (FALSE); + IAPU.PC = IAPU.RAM + IAPU.PC; + S9xAPUUnpackStatus (); + if (APUCheckDirectPage ()) + IAPU.DirectPage = IAPU.RAM + 0x100; + else + IAPU.DirectPage = IAPU.RAM; + Settings.APUEnabled = TRUE; + CPU.APU_APUExecuting = TRUE; + } + else + { + Settings.APUEnabled = FALSE; + CPU.APU_APUExecuting = FALSE; + S9xSetSoundMute (TRUE); + } + S9xFixSoundAfterSnapshotLoad (); + ICPU.ShiftedPB = Registers.PB << 16; + ICPU.ShiftedDB = Registers.DB << 16; + S9xSetPCBase (ICPU.ShiftedPB + Registers.PC, &CPU); + S9xUnpackStatus (); + S9xFixCycles (&Registers, &ICPU); + S9xReschedule (); + + return (SUCCESS); +} diff --git a/src/snaporig.h b/src/snaporig.h new file mode 100644 index 0000000..b83a71f --- /dev/null +++ b/src/snaporig.h @@ -0,0 +1,330 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _SNAPORIG_H_ +#define _SNAPORIG_H_ + +#define ORIG_SNAPSHOT_MAGIC "#!snes96" +#define ORIG_SNAPSHOT_VERSION 4 + +EXTERN_C bool8_32 S9xLoadOrigSnapshot (const char *filename); + +struct SOrigCPUState{ + uint32 Flags; + short Cycles_old; + short NextEvent_old; + uint8 CurrentFrame; + uint8 FastROMSpeed_old_old; + uint16 V_Counter_old; + bool8_32 BranchSkip; + bool8_32 NMIActive; + bool8_32 IRQActive; + bool8_32 WaitingForInterrupt; + bool8_32 InDMA; + uint8 WhichEvent; + uint8 *PC; + uint8 *PCBase; + uint16 MemSpeed_old; + uint16 MemSpeedx2_old; + uint16 FastROMSpeed_old; + bool8_32 FastDP; + uint8 *PCAtOpcodeStart; + uint8 *WaitAddress; + uint32 WaitCounter; + long Cycles; + long NextEvent; + long V_Counter; + long MemSpeed; + long MemSpeedx2; + long FastROMSpeed; +}; + +struct SOrigAPU +{ + uint32 Cycles; + bool8_32 ShowROM; + uint8 Flags; + uint8 KeyedChannels; + uint8 OutPorts [4]; + uint8 DSP [0x80]; + uint8 ExtraRAM [64]; + uint16 Timer [3]; + uint16 TimerTarget [3]; + bool8_32 TimerEnabled [3]; + bool8_32 TimerValueWritten [3]; +}; + +typedef union +{ +#ifdef LSB_FIRST + struct { uint8 A, Y; } B; +#else + struct { uint8 Y, A; } B; +#endif + uint16 W; +} OrigYAndA; + +struct SOrigAPURegisters{ + uint8 P; + OrigYAndA YA; + uint8 X; + uint8 S; + uint16 PC; +}; + +#define ORIG_MAX_BUFFER_SIZE (1024 * 4) +#define NUM_CHANNELS 8 + +typedef struct { + int state; + int type; + short volume_left; + short volume_right; + int frequency; + int count; + signed short wave [ORIG_MAX_BUFFER_SIZE]; + bool8_32 loop; + int envx; + short left_vol_level; + short right_vol_level; + short envx_target; + unsigned long int env_error; + unsigned long erate; + int direction; + unsigned long attack_rate; + unsigned long decay_rate; + unsigned long sustain_rate; + unsigned long release_rate; + unsigned long sustain_level; + signed short sample; + signed short decoded [16]; + signed short previous [2]; + uint16 sample_number; + bool8_32 last_block; + bool8_32 needs_decode; + uint32 block_pointer; + uint32 sample_pointer; + int *echo_buf_ptr; + int mode; + uint32 dummy [8]; +} OrigChannel; + +typedef struct +{ + short master_volume_left; + short master_volume_right; + short echo_volume_left; + short echo_volume_right; + int echo_enable; + int echo_feedback; + int echo_ptr; + int echo_buffer_size; + int echo_write_enabled; + int echo_channel_enable; + int pitch_mod; + // Just incase they are needed in the future, for snapshot compatibility. + uint32 dummy [3]; + OrigChannel channels [NUM_CHANNELS]; +} SOrigSoundData; + +struct SOrigOBJ +{ + short HPos; + uint16 VPos; + uint16 Name; + uint8 VFlip; + uint8 HFlip; + uint8 Priority; + uint8 Palette; + uint8 Size; + uint8 Prev; + uint8 Next; +}; + +struct SOrigPPU { + uint8 BGMode; + uint8 BG3Priority; + uint8 Brightness; + + struct { + bool8_32 High; + uint8 Increment; + uint16 Address; + uint16 Mask1; + uint16 FullGraphicCount; + uint16 Shift; + } VMA; + + struct { + uint8 TileSize; + uint16 TileAddress; + uint8 Width; + uint8 Height; + uint16 SCBase; + uint16 VOffset; + uint16 HOffset; + bool8_32 ThroughMain; + bool8_32 ThroughSub; + uint8 BGSize; + uint16 NameBase; + uint16 SCSize; + bool8_32 Addition; + } BG [4]; + + bool8_32 CGFLIP; + uint16 CGDATA [256]; + uint8 FirstSprite; + uint8 LastSprite; + struct SOrigOBJ OBJ [129]; + uint8 OAMPriorityRotation; + uint16 OAMAddr; + + uint8 OAMFlip; + uint16 OAMTileAddress; + uint16 IRQVBeamPos; + uint16 IRQHBeamPos; + uint16 VBeamPosLatched; + uint16 HBeamPosLatched; + + uint8 HBeamFlip; + uint8 VBeamFlip; + uint8 HVBeamCounterLatched; + + short MatrixA; + short MatrixB; + short MatrixC; + short MatrixD; + short CentreX; + short CentreY; + uint8 Joypad1ButtonReadPos; + uint8 Joypad2ButtonReadPos; + + uint8 CGADD; + uint8 FixedColourRed; + uint8 FixedColourGreen; + uint8 FixedColourBlue; + uint16 SavedOAMAddr; + uint16 ScreenHeight; + uint32 WRAM; + uint8 BG_Forced; + bool8_32 ForcedBlanking; + bool8_32 OBJThroughMain; + bool8_32 OBJThroughSub; + uint8 OBJSizeSelect; + uint8 OBJNameSelect_old; + uint16 OBJNameBase; + bool8_32 OBJAddition; + uint8 OAMReadFlip; + uint8 OAMData [512 + 32]; + bool8_32 VTimerEnabled; + bool8_32 HTimerEnabled; + short HTimerPosition; + uint8 Mosaic; + bool8_32 BGMosaic [4]; + bool8_32 Mode7HFlip; + bool8_32 Mode7VFlip; + uint8 Mode7Repeat; + uint8 Window1Left; + uint8 Window1Right; + uint8 Window2Left; + uint8 Window2Right; + uint8 ClipCounts [6]; + uint8 ClipLeftEdges [3][6]; + uint8 ClipRightEdges [3][6]; + uint8 ClipWindowOverlapLogic [6]; + uint8 ClipWindow1Enable [6]; + uint8 ClipWindow2Enable [6]; + bool8_32 ClipWindow1Inside [6]; + bool8_32 ClipWindow2Inside [6]; + bool8_32 RecomputeClipWindows; + uint8 CGFLIPRead; + uint16 OBJNameSelect; + bool8_32 Need16x8Mulitply; + uint8 Joypad3ButtonReadPos; + uint8 MouseSpeed[2]; +}; + +struct SOrigDMA { + bool8_32 TransferDirection; + bool8_32 AAddressFixed; + bool8_32 AAddressDecrement; + uint8 TransferMode; + + uint8 ABank; + uint16 AAddress; + uint16 Address; + uint8 BAddress; + + // General DMA only: + uint16 TransferBytes; + + // H-DMA only: + bool8_32 HDMAIndirectAddressing; + uint16 IndirectAddress; + uint8 IndirectBank; + uint8 Repeat; + uint8 LineCount; + uint8 FirstLine; + bool8_32 JustStarted; +}; + +typedef union +{ +#ifdef LSB_FIRST + struct { uint8 l,h; } B; +#else + struct { uint8 h,l; } B; +#endif + uint16 W; +} OrigPair; + +struct SOrigRegisters{ + uint8 PB; + uint8 DB; + OrigPair P; + OrigPair A; + OrigPair D; + OrigPair S; + OrigPair X; + OrigPair Y; + uint16 PC; +}; + +#endif diff --git a/src/snapshot.cpp b/src/snapshot.cpp new file mode 100644 index 0000000..fbcf81f --- /dev/null +++ b/src/snapshot.cpp @@ -0,0 +1,945 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#ifndef __GP32__ +#include +#include +#include +#endif +#if defined(__unix) || defined(__linux) || defined(__sun) || defined(__DJGPP) +#include +#include +#include +#endif + +#include "snapshot.h" +//#include "snaporig.h" +#include "memmap.h" +#include "snes9x.h" +#include "65c816.h" +#include "ppu.h" +#include "cpuexec.h" +#include "display.h" +#include "apu.h" +#include "soundux.h" +#ifdef USE_SA1 +#include "sa1.h" +#endif +#include "srtc.h" +#include "sdd1.h" + + +// notaz: file i/o function pointers for states, +// changing funcs will allow to enable/disable gzipped saves +extern int (*statef_open)(const char *fname, const char *mode); +extern int (*statef_read)(void *p, int l); +extern int (*statef_write)(void *p, int l); +extern void (*statef_close)(); + +extern uint8 *SRAM; + +#ifdef ZSNES_FX +START_EXTERN_C +void S9xSuperFXPreSaveState (); +void S9xSuperFXPostSaveState (); +void S9xSuperFXPostLoadState (); +END_EXTERN_C +#endif + +//bool8 S9xUnfreezeZSNES (const char *filename); + +typedef struct { + int offset; + int size; + int type; +} FreezeData; + +enum { + INT_V, uint8_ARRAY_V, uint16_ARRAY_V, uint32_ARRAY_V +}; + +#define Offset(field,structure) \ + ((int) (((char *) (&(((structure)NULL)->field))) - ((char *) NULL))) + +#define COUNT(ARRAY) (sizeof (ARRAY) / sizeof (ARRAY[0])) + +#undef OFFSET +#define OFFSET(f) Offset(f,struct SCPUState *) + +static FreezeData SnapCPU [] = { + {OFFSET (Flags), 4, INT_V}, + {OFFSET (BranchSkip), 1, INT_V}, + {OFFSET (NMIActive), 1, INT_V}, + {OFFSET (IRQActive), 1, INT_V}, + {OFFSET (WaitingForInterrupt), 1, INT_V}, + {OFFSET (WhichEvent), 1, INT_V}, + {OFFSET (Cycles), 4, INT_V}, + {OFFSET (NextEvent), 4, INT_V}, + {OFFSET (V_Counter), 4, INT_V}, + {OFFSET (MemSpeed), 4, INT_V}, + {OFFSET (MemSpeedx2), 4, INT_V}, + {OFFSET (FastROMSpeed), 4, INT_V} +}; + +#undef OFFSET +#define OFFSET(f) Offset(f,struct SRegisters *) + +static FreezeData SnapRegisters [] = { + {OFFSET (PB), 1, INT_V}, + {OFFSET (DB), 1, INT_V}, + {OFFSET (P.W), 2, INT_V}, + {OFFSET (A.W), 2, INT_V}, + {OFFSET (D.W), 2, INT_V}, + {OFFSET (S.W), 2, INT_V}, + {OFFSET (X.W), 2, INT_V}, + {OFFSET (Y.W), 2, INT_V}, + {OFFSET (PC), 2, INT_V} +}; + +#undef OFFSET +#define OFFSET(f) Offset(f,struct SPPU *) + +static FreezeData SnapPPU [] = { + {OFFSET (BGMode), 1, INT_V}, + {OFFSET (BG3Priority), 1, INT_V}, + {OFFSET (Brightness), 1, INT_V}, + {OFFSET (VMA.High), 1, INT_V}, + {OFFSET (VMA.Increment), 1, INT_V}, + {OFFSET (VMA.Address), 2, INT_V}, + {OFFSET (VMA.Mask1), 2, INT_V}, + {OFFSET (VMA.FullGraphicCount), 2, INT_V}, + {OFFSET (VMA.Shift), 2, INT_V}, + {OFFSET (BG[0].SCBase), 2, INT_V}, + {OFFSET (BG[0].VOffset), 2, INT_V}, + {OFFSET (BG[0].HOffset), 2, INT_V}, + {OFFSET (BG[0].BGSize), 1, INT_V}, + {OFFSET (BG[0].NameBase), 2, INT_V}, + {OFFSET (BG[0].SCSize), 2, INT_V}, + + {OFFSET (BG[1].SCBase), 2, INT_V}, + {OFFSET (BG[1].VOffset), 2, INT_V}, + {OFFSET (BG[1].HOffset), 2, INT_V}, + {OFFSET (BG[1].BGSize), 1, INT_V}, + {OFFSET (BG[1].NameBase), 2, INT_V}, + {OFFSET (BG[1].SCSize), 2, INT_V}, + + {OFFSET (BG[2].SCBase), 2, INT_V}, + {OFFSET (BG[2].VOffset), 2, INT_V}, + {OFFSET (BG[2].HOffset), 2, INT_V}, + {OFFSET (BG[2].BGSize), 1, INT_V}, + {OFFSET (BG[2].NameBase), 2, INT_V}, + {OFFSET (BG[2].SCSize), 2, INT_V}, + + {OFFSET (BG[3].SCBase), 2, INT_V}, + {OFFSET (BG[3].VOffset), 2, INT_V}, + {OFFSET (BG[3].HOffset), 2, INT_V}, + {OFFSET (BG[3].BGSize), 1, INT_V}, + {OFFSET (BG[3].NameBase), 2, INT_V}, + {OFFSET (BG[3].SCSize), 2, INT_V}, + + {OFFSET (CGFLIP), 1, INT_V}, + {OFFSET (CGDATA), 256, uint16_ARRAY_V}, + {OFFSET (FirstSprite), 1, INT_V}, +#define O(N) \ + {OFFSET (OBJ[N].HPos), 2, INT_V}, \ + {OFFSET (OBJ[N].VPos), 2, INT_V}, \ + {OFFSET (OBJ[N].Name), 2, INT_V}, \ + {OFFSET (OBJ[N].VFlip), 1, INT_V}, \ + {OFFSET (OBJ[N].HFlip), 1, INT_V}, \ + {OFFSET (OBJ[N].Priority), 1, INT_V}, \ + {OFFSET (OBJ[N].Palette), 1, INT_V}, \ + {OFFSET (OBJ[N].Size), 1, INT_V} + + O( 0), O( 1), O( 2), O( 3), O( 4), O( 5), O( 6), O( 7), + O( 8), O( 9), O( 10), O( 11), O( 12), O( 13), O( 14), O( 15), + O( 16), O( 17), O( 18), O( 19), O( 20), O( 21), O( 22), O( 23), + O( 24), O( 25), O( 26), O( 27), O( 28), O( 29), O( 30), O( 31), + O( 32), O( 33), O( 34), O( 35), O( 36), O( 37), O( 38), O( 39), + O( 40), O( 41), O( 42), O( 43), O( 44), O( 45), O( 46), O( 47), + O( 48), O( 49), O( 50), O( 51), O( 52), O( 53), O( 54), O( 55), + O( 56), O( 57), O( 58), O( 59), O( 60), O( 61), O( 62), O( 63), + O( 64), O( 65), O( 66), O( 67), O( 68), O( 69), O( 70), O( 71), + O( 72), O( 73), O( 74), O( 75), O( 76), O( 77), O( 78), O( 79), + O( 80), O( 81), O( 82), O( 83), O( 84), O( 85), O( 86), O( 87), + O( 88), O( 89), O( 90), O( 91), O( 92), O( 93), O( 94), O( 95), + O( 96), O( 97), O( 98), O( 99), O(100), O(101), O(102), O(103), + O(104), O(105), O(106), O(107), O(108), O(109), O(110), O(111), + O(112), O(113), O(114), O(115), O(116), O(117), O(118), O(119), + O(120), O(121), O(122), O(123), O(124), O(125), O(126), O(127), +#undef O + {OFFSET (OAMPriorityRotation), 1, INT_V}, + {OFFSET (OAMAddr), 2, INT_V}, + {OFFSET (OAMFlip), 1, INT_V}, + {OFFSET (OAMTileAddress), 2, INT_V}, + {OFFSET (IRQVBeamPos), 2, INT_V}, + {OFFSET (IRQHBeamPos), 2, INT_V}, + {OFFSET (VBeamPosLatched), 2, INT_V}, + {OFFSET (HBeamPosLatched), 2, INT_V}, + {OFFSET (HBeamFlip), 1, INT_V}, + {OFFSET (VBeamFlip), 1, INT_V}, + {OFFSET (HVBeamCounterLatched), 1, INT_V}, + {OFFSET (MatrixA), 2, INT_V}, + {OFFSET (MatrixB), 2, INT_V}, + {OFFSET (MatrixC), 2, INT_V}, + {OFFSET (MatrixD), 2, INT_V}, + {OFFSET (CentreX), 2, INT_V}, + {OFFSET (CentreY), 2, INT_V}, + {OFFSET (Joypad1ButtonReadPos), 1, INT_V}, + {OFFSET (Joypad2ButtonReadPos), 1, INT_V}, + {OFFSET (Joypad3ButtonReadPos), 1, INT_V}, + {OFFSET (CGADD), 1, INT_V}, + {OFFSET (FixedColourRed), 1, INT_V}, + {OFFSET (FixedColourGreen), 1, INT_V}, + {OFFSET (FixedColourBlue), 1, INT_V}, + {OFFSET (SavedOAMAddr), 2, INT_V}, + {OFFSET (ScreenHeight), 2, INT_V}, + {OFFSET (WRAM), 4, INT_V}, + {OFFSET (ForcedBlanking), 1, INT_V}, + {OFFSET (OBJNameSelect), 2, INT_V}, + {OFFSET (OBJSizeSelect), 1, INT_V}, + {OFFSET (OBJNameBase), 2, INT_V}, + {OFFSET (OAMReadFlip), 1, INT_V}, + {OFFSET (VTimerEnabled), 1, INT_V}, + {OFFSET (HTimerEnabled), 1, INT_V}, + {OFFSET (HTimerPosition), 2, INT_V}, + {OFFSET (Mosaic), 1, INT_V}, + {OFFSET (Mode7HFlip), 1, INT_V}, + {OFFSET (Mode7VFlip), 1, INT_V}, + {OFFSET (Mode7Repeat), 1, INT_V}, + {OFFSET (Window1Left), 1, INT_V}, + {OFFSET (Window1Right), 1, INT_V}, + {OFFSET (Window2Left), 1, INT_V}, + {OFFSET (Window2Right), 1, INT_V}, +#define O(N) \ + {OFFSET (ClipWindowOverlapLogic[N]), 1, INT_V}, \ + {OFFSET (ClipWindow1Enable[N]), 1, INT_V}, \ + {OFFSET (ClipWindow2Enable[N]), 1, INT_V}, \ + {OFFSET (ClipWindow1Inside[N]), 1, INT_V}, \ + {OFFSET (ClipWindow2Inside[N]), 1, INT_V} + + O(0), O(1), O(2), O(3), O(4), O(5), + +#undef O + + {OFFSET (CGFLIPRead), 1, INT_V}, + {OFFSET (Need16x8Mulitply), 1, INT_V}, + {OFFSET (BGMosaic), 4, uint8_ARRAY_V}, + {OFFSET (OAMData), 512 + 32, uint8_ARRAY_V}, + {OFFSET (Need16x8Mulitply), 1, INT_V}, + {OFFSET (MouseSpeed), 2, uint8_ARRAY_V} +}; + +#undef OFFSET +#define OFFSET(f) Offset(f,struct SDMA *) + +static FreezeData SnapDMA [] = { +#define O(N) \ + {OFFSET (TransferDirection) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (AAddressFixed) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (AAddressDecrement) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (TransferMode) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (ABank) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (AAddress) + N * sizeof (struct SDMA), 2, INT_V}, \ + {OFFSET (Address) + N * sizeof (struct SDMA), 2, INT_V}, \ + {OFFSET (BAddress) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (TransferBytes) + N * sizeof (struct SDMA), 2, INT_V}, \ + {OFFSET (HDMAIndirectAddressing) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (IndirectAddress) + N * sizeof (struct SDMA), 2, INT_V}, \ + {OFFSET (IndirectBank) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (Repeat) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (LineCount) + N * sizeof (struct SDMA), 1, INT_V}, \ + {OFFSET (FirstLine) + N * sizeof (struct SDMA), 1, INT_V} + + O(0), O(1), O(2), O(3), O(4), O(5), O(6), O(7) +#undef O +}; + +#undef OFFSET +#define OFFSET(f) Offset(f,struct SAPU *) + +static FreezeData SnapAPU [] = { + {OFFSET (Cycles), 4, INT_V}, + {OFFSET (ShowROM), 1, INT_V}, + {OFFSET (Flags), 1, INT_V}, + {OFFSET (KeyedChannels), 1, INT_V}, + {OFFSET (OutPorts), 4, uint8_ARRAY_V}, + {OFFSET (DSP), 0x80, uint8_ARRAY_V}, + {OFFSET (ExtraRAM), 64, uint8_ARRAY_V}, + {OFFSET (Timer), 3, uint16_ARRAY_V}, + {OFFSET (TimerTarget), 3, uint16_ARRAY_V}, + {OFFSET (TimerEnabled), 3, uint8_ARRAY_V}, + {OFFSET (TimerValueWritten), 3, uint8_ARRAY_V} +}; + +#undef OFFSET +#define OFFSET(f) Offset(f,struct SAPURegisters *) + +static FreezeData SnapAPURegisters [] = { + {OFFSET (P) , 1, INT_V}, + {OFFSET (YA.W), 2, INT_V}, + {OFFSET (X) , 1, INT_V}, + {OFFSET (S) , 1, INT_V}, + {OFFSET (PC) , 2, INT_V} +}; + +#undef OFFSET +#undef OFFSET1 +#define OFFSET(f) Offset(f,SSoundData *) + +static FreezeData SnapSoundData [] = { + {OFFSET (master_volume_left), 2, INT_V}, + {OFFSET (master_volume_right), 2, INT_V}, + {OFFSET (echo_volume_left), 2, INT_V}, + {OFFSET (echo_volume_right), 2, INT_V}, + {OFFSET (echo_enable), 4, INT_V}, + {OFFSET (echo_feedback), 4, INT_V}, + {OFFSET (echo_ptr), 4, INT_V}, + {OFFSET (echo_buffer_size), 4, INT_V}, + {OFFSET (echo_write_enabled), 4, INT_V}, + {OFFSET (echo_channel_enable), 4, INT_V}, + {OFFSET (pitch_mod), 4, INT_V}, + {OFFSET (dummy), 3, uint32_ARRAY_V}, +#define O(N) \ + {OFFSET (channels [N].state), 4, INT_V}, \ + {OFFSET (channels [N].type), 4, INT_V}, \ + {OFFSET (channels [N].volume_left), 2, INT_V}, \ + {OFFSET (channels [N].volume_right), 2, INT_V}, \ + {OFFSET (channels [N].hertz), 4, INT_V}, \ + {OFFSET (channels [N].count), 4, INT_V}, \ + {OFFSET (channels [N].loop), 1, INT_V}, \ + {OFFSET (channels [N].envx), 4, INT_V}, \ + {OFFSET (channels [N].left_vol_level), 2, INT_V}, \ + {OFFSET (channels [N].right_vol_level), 2, INT_V}, \ + {OFFSET (channels [N].envx_target), 2, INT_V}, \ + {OFFSET (channels [N].env_error), 4, INT_V}, \ + {OFFSET (channels [N].erate), 4, INT_V}, \ + {OFFSET (channels [N].direction), 4, INT_V}, \ + {OFFSET (channels [N].attack_rate), 4, INT_V}, \ + {OFFSET (channels [N].decay_rate), 4, INT_V}, \ + {OFFSET (channels [N].sustain_rate), 4, INT_V}, \ + {OFFSET (channels [N].release_rate), 4, INT_V}, \ + {OFFSET (channels [N].sustain_level), 4, INT_V}, \ + {OFFSET (channels [N].sample), 2, INT_V}, \ + {OFFSET (channels [N].decoded), 16, uint16_ARRAY_V}, \ + {OFFSET (channels [N].previous16), 2, uint16_ARRAY_V}, \ + {OFFSET (channels [N].sample_number), 2, INT_V}, \ + {OFFSET (channels [N].last_block), 1, INT_V}, \ + {OFFSET (channels [N].needs_decode), 1, INT_V}, \ + {OFFSET (channels [N].block_pointer), 4, INT_V}, \ + {OFFSET (channels [N].sample_pointer), 4, INT_V}, \ + {OFFSET (channels [N].mode), 4, INT_V} + + O(0), O(1), O(2), O(3), O(4), O(5), O(6), O(7) +#undef O +}; + +#ifdef USE_SA1 + +#undef OFFSET +#define OFFSET(f) Offset(f,struct SSA1Registers *) + +static FreezeData SnapSA1Registers [] = { + {OFFSET (PB), 1, INT_V}, + {OFFSET (DB), 1, INT_V}, + {OFFSET (P.W), 2, INT_V}, + {OFFSET (A.W), 2, INT_V}, + {OFFSET (D.W), 2, INT_V}, + {OFFSET (S.W), 2, INT_V}, + {OFFSET (X.W), 2, INT_V}, + {OFFSET (Y.W), 2, INT_V}, + {OFFSET (PC), 2, INT_V} +}; + +#undef OFFSET +#define OFFSET(f) Offset(f,struct SSA1 *) + +static FreezeData SnapSA1 [] = { + {OFFSET (Flags), 4, INT_V}, + {OFFSET (NMIActive), 1, INT_V}, + {OFFSET (IRQActive), 1, INT_V}, + {OFFSET (WaitingForInterrupt), 1, INT_V}, + {OFFSET (op1), 2, INT_V}, + {OFFSET (op2), 2, INT_V}, + {OFFSET (arithmetic_op), 4, INT_V}, + {OFFSET (sum), 8, INT_V}, + {OFFSET (overflow), 1, INT_V} +}; +#endif + +//static char ROMFilename [_MAX_PATH]; +//static char SnapshotFilename [_MAX_PATH]; + +static void Freeze (); +static int Unfreeze (); +void FreezeStruct (char *name, void *base, FreezeData *fields, + int num_fields); +void FreezeBlock (char *name, uint8 *block, int size); + +int UnfreezeStruct (char *name, void *base, FreezeData *fields, + int num_fields); +int UnfreezeBlock (char *name, uint8 *block, int size); + +bool8 Snapshot (const char *filename) +{ + return (S9xFreezeGame (filename)); +} + +bool8 S9xFreezeGame (const char *filename) +{ + if(statef_open(filename, "wb")) + { + Freeze(); + statef_close(); + return (TRUE); + } + return (FALSE); +} + + +bool8 S9xUnfreezeGame (const char *filename) +{ + if(statef_open(filename, "rb")) + { + int result; + if ((result = Unfreeze()) != SUCCESS) + { + switch (result) + { + case WRONG_FORMAT: + S9xMessage (S9X_ERROR, S9X_WRONG_FORMAT, + "File not in Snes9x freeze format"); + S9xReset(); + break; + case WRONG_VERSION: + S9xMessage (S9X_ERROR, S9X_WRONG_VERSION, + "Incompatable Snes9x freeze file format version"); + S9xReset(); + break; + default: + // should never happen + break; + } + statef_close(); + return (FALSE); + } + statef_close(); + return (TRUE); + } + + + return (FALSE); +} + +static void Freeze () +{ + char buffer[1024]; + int i; + + S9xSetSoundMute (TRUE); +#ifdef ZSNES_FX + if (Settings.SuperFX) + S9xSuperFXPreSaveState (); +#endif + + S9xSRTCPreSaveState (); + + for (i = 0; i < 8; i++) + { + SoundData.channels [i].previous16 [0] = (int16) SoundData.channels [i].previous [0]; + SoundData.channels [i].previous16 [1] = (int16) SoundData.channels [i].previous [1]; + } + sprintf (buffer, "%s:%04d\n", SNAPSHOT_MAGIC, SNAPSHOT_VERSION); + statef_write(buffer, strlen (buffer)); + sprintf (buffer, "NAM:%06d:%s%c", strlen (Memory.ROMFilename) + 1, + Memory.ROMFilename, 0); + statef_write(buffer, strlen (buffer) + 1); + FreezeStruct ("CPU", &CPU, SnapCPU, COUNT (SnapCPU)); + FreezeStruct ("REG", &Registers, SnapRegisters, COUNT (SnapRegisters)); + FreezeStruct ("PPU", &PPU, SnapPPU, COUNT (SnapPPU)); + FreezeStruct ("DMA", DMA, SnapDMA, COUNT (SnapDMA)); + +// RAM and VRAM + FreezeBlock ("VRA", Memory.VRAM, 0x10000); + FreezeBlock ("RAM", Memory.RAM, 0x20000); + FreezeBlock ("SRA", ::SRAM, 0x20000); + FreezeBlock ("FIL", Memory.FillRAM, 0x8000); + if (Settings.APUEnabled) + { +// APU + FreezeStruct ("APU", &APU, SnapAPU, COUNT (SnapAPU)); + // copy all SPC700 regs to savestate compatible struct + SAPURegisters spcregs; + spcregs.P = IAPU.P; + spcregs.YA.W = IAPU.YA.W; + spcregs.X = IAPU.X; + spcregs.S = IAPU.S; + spcregs.PC = IAPU.PC - IAPU.RAM; + FreezeStruct ("ARE", &spcregs, SnapAPURegisters, + COUNT (SnapAPURegisters)); + + FreezeBlock ("ARA", IAPU.RAM, 0x10000); + FreezeStruct ("SOU", &SoundData, SnapSoundData, + COUNT (SnapSoundData)); + } +#ifdef USE_SA1 + if (Settings.SA1) + { + SA1Registers.PC = SA1.PC - SA1.PCBase; + S9xSA1PackStatus (); + FreezeStruct ("SA1", &SA1, SnapSA1, COUNT (SnapSA1)); + FreezeStruct ("SAR", &SA1Registers, SnapSA1Registers, + COUNT (SnapSA1Registers)); + } +#endif + S9xSetSoundMute (FALSE); +#ifdef ZSNES_FX + if (Settings.SuperFX) + S9xSuperFXPostSaveState (); +#endif +} + +static int Unfreeze() +{ + // notaz: overflowing the damn Symbian stack again + char buffer [16]; + char rom_filename [512]; + int result; + + int version; + + unsigned int len = strlen (SNAPSHOT_MAGIC) + 1 + 4 + 1; + if (statef_read(buffer, len) != (int)len) + { + return (WRONG_FORMAT); + } + if (strncmp (buffer, SNAPSHOT_MAGIC, strlen (SNAPSHOT_MAGIC)) != 0) + { + return (WRONG_FORMAT); + } + if ((version = atoi (&buffer [strlen (SNAPSHOT_MAGIC) + 1])) > SNAPSHOT_VERSION) + return (WRONG_VERSION); + + if ((result = UnfreezeBlock("NAM", (uint8 *) rom_filename, 512)) != SUCCESS) + return (result); + + if (strcasecmp (rom_filename, Memory.ROMFilename) != 0 && + strcasecmp (S9xBasename (rom_filename), S9xBasename (Memory.ROMFilename)) != 0) + { + S9xMessage (S9X_WARNING, S9X_FREEZE_ROM_NAME, + "Current loaded ROM image doesn't match that required by freeze-game file."); + } + + + + uint32 old_flags = CPU.Flags; +#ifdef USE_SA1 + uint32 sa1_old_flags = SA1.Flags; +#endif + S9xReset (); + S9xSetSoundMute (TRUE); + + if ((result = UnfreezeStruct("CPU", &CPU, SnapCPU, + COUNT (SnapCPU))) != SUCCESS) + return (result); + + + Memory.FixROMSpeed (); + CPU.Flags |= old_flags & (DEBUG_MODE_FLAG | TRACE_FLAG | + SINGLE_STEP_FLAG | FRAME_ADVANCE_FLAG); + if ((result = UnfreezeStruct("REG", &Registers, SnapRegisters, COUNT (SnapRegisters))) != SUCCESS) + return (result); + if ((result = UnfreezeStruct("PPU", &PPU, SnapPPU, COUNT (SnapPPU))) != SUCCESS) + return (result); + + + IPPU.ColorsChanged = TRUE; + IPPU.OBJChanged = TRUE; + CPU.InDMA = FALSE; + // Restore colors from PPU + for (unsigned int i = 0; i < 256; i++) { + IPPU.Red[i] = PPU.CGDATA[i] & 0x1f; + IPPU.Green[i] = (PPU.CGDATA[i] >> 5) & 0x1f; + IPPU.Blue[i] = (PPU.CGDATA[i] >> 10) & 0x1f; + } + + S9xFixColourBrightness (); + IPPU.RenderThisFrame = FALSE; + + if ((result = UnfreezeStruct ("DMA", DMA, SnapDMA, + COUNT (SnapDMA))) != SUCCESS) + return (result); + + if ((result = UnfreezeBlock ("VRA", Memory.VRAM, 0x10000)) != SUCCESS) + return (result); + + if ((result = UnfreezeBlock ("RAM", Memory.RAM, 0x20000)) != SUCCESS) + return (result); + + if ((result = UnfreezeBlock ("SRA", ::SRAM, 0x20000)) != SUCCESS) + return (result); + + if ((result = UnfreezeBlock ("FIL", Memory.FillRAM, 0x8000)) != SUCCESS) + return (result); + + // Restore graphics shadow registers + GFX.r212c_s = Memory.FillRAM[0x212c]; + GFX.r212d_s = Memory.FillRAM[0x212d]; + GFX.r212e_s = Memory.FillRAM[0x212e]; + GFX.r212f_s = Memory.FillRAM[0x212f]; + GFX.r2130_s = Memory.FillRAM[0x2130]; + GFX.r2131_s = Memory.FillRAM[0x2131]; + + if (UnfreezeStruct ("APU", &APU, SnapAPU, COUNT (SnapAPU)) == SUCCESS) + { + SAPURegisters spcregs; + if ((result = UnfreezeStruct ("ARE", &spcregs, SnapAPURegisters, + COUNT (SnapAPURegisters))) != SUCCESS) + return (result); + // reload all SPC700 regs from savestate compatible struct + IAPU.P = spcregs.P; + IAPU.YA.W = spcregs.YA.W; + IAPU.X = spcregs.X; + IAPU.S = spcregs.S; + IAPU.PC = IAPU.RAM + spcregs.PC; + + if ((result = UnfreezeBlock ("ARA", IAPU.RAM, 0x10000)) != SUCCESS) + return (result); + + if ((result = UnfreezeStruct ("SOU", &SoundData, SnapSoundData, + COUNT (SnapSoundData))) != SUCCESS) + return (result); + + // notaz: just to be sure + for(int u=0; u<8; u++) { + SoundData.channels[u].env_ind_attack &= 0xf; + SoundData.channels[u].env_ind_decay &= 0x7; + SoundData.channels[u].env_ind_sustain&= 0x1f; + } + + S9xSetSoundMute (FALSE); + S9xAPUUnpackStatus (); + if (APUCheckDirectPage ()) + IAPU.DirectPage = IAPU.RAM + 0x100; + else + IAPU.DirectPage = IAPU.RAM; + Settings.APUEnabled = TRUE; + /*IAPU.APUExecuting*/CPU.APU_APUExecuting = TRUE; + } + else + { + Settings.APUEnabled = FALSE; + /*IAPU.APUExecuting*/CPU.APU_APUExecuting = FALSE; + S9xSetSoundMute (TRUE); + } +#ifdef USE_SA1 + if ((result = UnfreezeStruct ("SA1", &SA1, SnapSA1, + COUNT(SnapSA1))) == SUCCESS) + { + if ((result = UnfreezeStruct ("SAR", &SA1Registers, + SnapSA1Registers, COUNT (SnapSA1Registers))) != SUCCESS) + return (result); + + S9xFixSA1AfterSnapshotLoad (); + SA1.Flags |= sa1_old_flags & (TRACE_FLAG); + } +#endif + S9xFixSoundAfterSnapshotLoad (); + ICPU.ShiftedPB = Registers.PB << 16; + ICPU.ShiftedDB = Registers.DB << 16; + S9xSetPCBase (ICPU.ShiftedPB + Registers.PC); + +#ifndef ASMCPU + S9xUnpackStatus (); // not needed + S9xFixCycles (); // also not needed? +#endif + S9xReschedule (); +#ifdef ZSNES_FX + if (Settings.SuperFX) + S9xSuperFXPostLoadState (); +#endif + + S9xSRTCPostLoadState (); + if (Settings.SDD1) S9xSDD1PostLoadState (); + + return (SUCCESS); +} + +int FreezeSize (int size, int type) +{ + switch (type) + { + case uint16_ARRAY_V: + return (size * 2); + case uint32_ARRAY_V: + return (size * 4); + default: + return (size); + } +} + +void FreezeStruct(char *name, void *base, FreezeData *fields, + int num_fields) +{ + // Work out the size of the required block + int len = 0; + int i; + int j; + + for (i = 0; i < num_fields; i++) + { + if (fields [i].offset + FreezeSize (fields [i].size, + fields [i].type) > len) + len = fields [i].offset + FreezeSize (fields [i].size, + fields [i].type); + } + +// uint8 *block = new uint8 [len]; + uint8 *block = (uint8*)malloc(len); + uint8 *ptr = block; + uint16 word; + uint32 dword; + int64 qword; + + // Build the block ready to be streamed out + for (i = 0; i < num_fields; i++) + { + switch (fields [i].type) + { + case INT_V: + switch (fields [i].size) + { + case 1: + *ptr++ = *((uint8 *) base + fields [i].offset); + break; + case 2: + word = *((uint16 *) ((uint8 *) base + fields [i].offset)); + *ptr++ = (uint8) (word >> 8); + *ptr++ = (uint8) word; + break; + case 4: + dword = *((uint32 *) ((uint8 *) base + fields [i].offset)); + *ptr++ = (uint8) (dword >> 24); + *ptr++ = (uint8) (dword >> 16); + *ptr++ = (uint8) (dword >> 8); + *ptr++ = (uint8) dword; + break; + case 8: + qword = *((int64 *) ((uint8 *) base + fields [i].offset)); + *ptr++ = (uint8) (qword >> 56); + *ptr++ = (uint8) (qword >> 48); + *ptr++ = (uint8) (qword >> 40); + *ptr++ = (uint8) (qword >> 32); + *ptr++ = (uint8) (qword >> 24); + *ptr++ = (uint8) (qword >> 16); + *ptr++ = (uint8) (qword >> 8); + *ptr++ = (uint8) qword; + break; + } + break; + case uint8_ARRAY_V: + memmove (ptr, (uint8 *) base + fields [i].offset, fields [i].size); + ptr += fields [i].size; + break; + case uint16_ARRAY_V: + for (j = 0; j < fields [i].size; j++) + { + word = *((uint16 *) ((uint8 *) base + fields [i].offset + j * 2)); + *ptr++ = (uint8) (word >> 8); + *ptr++ = (uint8) word; + } + break; + case uint32_ARRAY_V: + for (j = 0; j < fields [i].size; j++) + { + dword = *((uint32 *) ((uint8 *) base + fields [i].offset + j * 4)); + *ptr++ = (uint8) (dword >> 24); + *ptr++ = (uint8) (dword >> 16); + *ptr++ = (uint8) (dword >> 8); + *ptr++ = (uint8) dword; + } + break; + } + } + + FreezeBlock (name, block, len); + + free(block); +} + +void FreezeBlock (char *name, uint8 *block, int size) +{ + char buffer [512]; + sprintf (buffer, "%s:%06d:", name, size); + statef_write(buffer, strlen (buffer)); + statef_write(block, size); + +} + +int UnfreezeStruct (char *name, void *base, FreezeData *fields, + int num_fields) +{ + // Work out the size of the required block + int len = 0; + int i; + int j; + + for (i = 0; i < num_fields; i++) + { + if (fields [i].offset + FreezeSize (fields [i].size, + fields [i].type) > len) + len = fields [i].offset + FreezeSize (fields [i].size, + fields [i].type); + } + + uint8 *block = (uint8*)malloc(len); + uint8 *ptr = block; + uint16 word; + uint32 dword; + int64 qword; + int result; + + if ((result = UnfreezeBlock (name, block, len)) != SUCCESS) + { + free(block); + return (result); + } + + // Unpack the block of data into a C structure + for (i = 0; i < num_fields; i++) + { + switch (fields [i].type) + { + case INT_V: + switch (fields [i].size) + { + case 1: + *((uint8 *) base + fields [i].offset) = *ptr++; + break; + case 2: + word = *ptr++ << 8; + word |= *ptr++; + *((uint16 *) ((uint8 *) base + fields [i].offset)) = word; + break; + case 4: + dword = *ptr++ << 24; + dword |= *ptr++ << 16; + dword |= *ptr++ << 8; + dword |= *ptr++; + *((uint32 *) ((uint8 *) base + fields [i].offset)) = dword; + break; + case 8: + qword = (int64) *ptr++ << 56; + qword |= (int64) *ptr++ << 48; + qword |= (int64) *ptr++ << 40; + qword |= (int64) *ptr++ << 32; + qword |= (int64) *ptr++ << 24; + qword |= (int64) *ptr++ << 16; + qword |= (int64) *ptr++ << 8; + qword |= (int64) *ptr++; + *((int64 *) ((uint8 *) base + fields [i].offset)) = qword; + break; + } + break; + case uint8_ARRAY_V: + memmove ((uint8 *) base + fields [i].offset, ptr, fields [i].size); + ptr += fields [i].size; + break; + case uint16_ARRAY_V: + for (j = 0; j < fields [i].size; j++) + { + word = *ptr++ << 8; + word |= *ptr++; + *((uint16 *) ((uint8 *) base + fields [i].offset + j * 2)) = word; + } + break; + case uint32_ARRAY_V: + for (j = 0; j < fields [i].size; j++) + { + dword = *ptr++ << 24; + dword |= *ptr++ << 16; + dword |= *ptr++ << 8; + dword |= *ptr++; + *((uint32 *) ((uint8 *) base + fields [i].offset + j * 4)) = dword; + } + break; + } + } + +// delete block; + free(block); + return (result); +} + +int UnfreezeBlock(char *name, uint8 *block, int size) +{ + char buffer [20]; + int len = 0; + int rem = 0; + + if (statef_read(buffer, 11) != 11 || + strncmp (buffer, name, 3) != 0 || buffer [3] != ':' || + (len = atoi (&buffer [4])) == 0) + { + return (WRONG_FORMAT); + } + + if (len > size) + { + rem = len - size; + len = size; + } + + if (statef_read(block, len) != len) + { + return (WRONG_FORMAT); + } + + if (rem) + { + char *junk = (char*)malloc(rem); + statef_read(junk, rem); + free(junk); + } + + return (SUCCESS); +} + + diff --git a/src/snapshot.h b/src/snapshot.h new file mode 100644 index 0000000..fb23a42 --- /dev/null +++ b/src/snapshot.h @@ -0,0 +1,63 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _SNAPSHOT_H_ +#define _SNAPSHOT_H_ + +#include +#include "snes9x.h" + +#define SNAPSHOT_MAGIC "#!snes9x" +#define SNAPSHOT_VERSION 1 + +#define SUCCESS 1 +#define WRONG_FORMAT (-1) +#define WRONG_VERSION (-2) +#define FILE_NOT_FOUND (-3) + +START_EXTERN_C +bool8 S9xFreezeGame (const char *filename); +bool8 S9xUnfreezeGame (const char *filename); +bool8 Snapshot (const char *filename); +bool8 S9xLoadSnapshot (const char *filename); +bool8 S9xSPCDump (const char *filename); +END_EXTERN_C + +#endif diff --git a/src/snapshots/do.sh b/src/snapshots/do.sh new file mode 100644 index 0000000..cb8b3bc --- /dev/null +++ b/src/snapshots/do.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +FILE=$(date +%Y%m%d-%k%M) +zip -9 -r pocketsnes-$FILE ../* -x \*.o \*.gpe \*.zip \*~ diff --git a/src/snes9x.cpp b/src/snes9x.cpp new file mode 100644 index 0000000..36e3f44 --- /dev/null +++ b/src/snes9x.cpp @@ -0,0 +1,655 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include +#include + +#include "snes9x.h" +#include "memmap.h" +#include "display.h" +#include "cheats.h" + +#ifdef DEBUGGER +extern FILE *trace; +#endif + +void S9xUsage () +{ + S9xMessage (S9X_INFO, S9X_USAGE, "snes9x: S9xUsage: snes9x \n\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "Where can be:\n"); + + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-cycles or -h Percentage of CPU cycles to execute every scan line (default 90)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-frameskip or -f Screen update frame skip rate (default 2)\n"); + S9xExtraUsage (); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-forcehirom or -F or -FH Force Hi-ROM memory map, useful for hacked ROM imagess.\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-forcelorom or -FL Force Lo-ROM memory map, useful for hacked ROM images.\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-old or -o Enable old-style SNES joypad emulation\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-noold or -no Disbale old-style SNES joypad emulation\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-soundskip or -ss Sound CPU skip-waiting method, 0 - 3 (default 0)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-sound or -S Enable digital sound output (default: enabled)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-nosound or -NS Disable digital sound output\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-sound or -S Enable digital sound output (default: off)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-soundquality or -r Sound sample playback rate/quality, 0-7 (default 4)\n"); + +#ifdef __sgi +/* BS: changed the sample rate values to match the IRIX options */ + S9xMessage (S9X_INFO, S9X_USAGE, "\ + 0 - off, 1 - 8192, 2 - 11025, 3 - 16000,\n\ + 4 - 22050 (default), 5 - 32000, 6 - 44100,\n\ + 7 - 48000\n"); +#else + S9xMessage (S9X_INFO, S9X_USAGE, "\ + 0 - off, 1 - 8192, 2 - 11025, 3 - 16500,\n\ + 4 - 22050 (default), 5 - 29300, 6 - 36600,\n\ + 7 - 44000\n"); +#endif + + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-stereo Enable stereo sound (default: mono sound)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-mono Enable mono sound (default: mono sound)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-buffersize or -B Sound playback buffer size (default auto for playback rate)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-nospeedhacks or -N Disable some internal speed ups that break a few ROMs\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-speedhacks or -SH Enable some internal speed ups that break a few ROMs\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-loadsnapshot or -l \n\ + Load saved game position snapshot file & required ROM\n\ + image.\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-swapjoypads or -s Swap joypad 1 and 2 around\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-pal or -p Fool ROM into thinking that this is a PAL SNES system\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-ntsc or -n Fool ROM into thinking that this is a NTCS SNES system\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-interleaved or -i ROM image is in interleaved format.\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-interleaved2 or -i2 ROM image is in interleaved 2 format\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-nohdma or -H Disable H-DMA emulation (default: enabled)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-hdma or -NH Enable H-DMA emulation (default: enabled)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-layering or -L Swap some background priority levels - helps some games\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-graphicwindows Enable graphic window effects (default: enabled)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-nographicwindows or -nw Disable graphic window effects (default: enabled)\n"); +#ifdef DEBUGGER + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-noirq or -I Disable processor IRQ (for debugging)\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-debug or -d Enter debug mode once ROM has loaded\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-trace or -t Trace CPU instructions to file (WARNING: file gets very large!)\n"); +#endif + +#ifdef JOYSTICK_SUPPORT +#ifdef __linux + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-joydevX /dev/jsY Use joystick device /dev/jsY for emulation of gamepad X\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-joymapX 0 1 2 3 4 5 6 7 Joystick buttons which should be assigned to gamepad X - A B X Y TL TR Start and Select\n"); +#else + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-four or -4 Single standard PC joystick has four buttons\n"); + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-six or -6 Single standard PC joystick has six buttons\n"); +#endif + S9xMessage (S9X_INFO, S9X_USAGE, "\ +-nojoy or -j Disable joystick support\n"); +#endif + + S9xMessage (S9X_INFO, S9X_USAGE, "\ +\nROM image needs to be in Super MagiCom (*.smc), Super FamiCom (*.sfc),\n\ +*.fig, or split (*.1, *.2, or sf32527a, sf32527b, etc) format and can be\n\ +compressed with gzip or compress.\n"); + + exit (1); +} + +#ifdef STORM +extern int dofps; +extern int hicolor; +extern int secondjoy; +extern int minimal; +int prelude=0; +extern int unit; +#endif + +char *S9xParseArgs (char **argv, int argc) +{ + char *rom_filename = NULL; + + for (int i = 1; i < argc; i++) + { + if (*argv[i] == '-') + { + if (strcasecmp (argv [i], "-so") == 0 || + strcasecmp (argv [i], "-sound") == 0) + { + Settings.NextAPUEnabled = TRUE; + } + else if (strcasecmp (argv [i], "-ns") == 0 || + strcasecmp (argv [i], "-nosound") == 0) + { + Settings.NextAPUEnabled = FALSE; + } + else if (strcasecmp (argv [i], "-soundskip") == 0 || + strcasecmp (argv [i], "-sk") == 0) + { + if (i + 1 < argc) + Settings.SoundSkipMethod = atoi (argv [++i]); + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-ra") == 0 || + strcasecmp (argv [i], "-ratio") == 0) + { + if (i + 1 < argc) + { + } + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-h") == 0 || + strcasecmp (argv [i], "-cycles") == 0) + { + if (i + 1 < argc) + { + int p = atoi (argv [++i]); + if (p > 0 && p < 200) + Settings.CyclesPercentage = p; + } + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-nh") == 0 || + strcasecmp (argv [i], "-nohdma") == 0) + { + Settings.DisableHDMA = TRUE; + } + else if (strcasecmp (argv [i], "-ha") == 0 || + strcasecmp (argv [i], "-hdma") == 0) + { + Settings.DisableHDMA = FALSE; + } + else if (strcasecmp (argv [i], "-n") == 0 || + strcasecmp (argv [i], "-nospeedhacks") == 0) + { + Settings.ShutdownMaster = FALSE; + } + else if (strcasecmp (argv [i], "-sh") == 0 || + strcasecmp (argv [i], "-speedhacks") == 0) + { + Settings.ShutdownMaster = TRUE; + } + else if (strcasecmp (argv [i], "-p") == 0 || + strcasecmp (argv [i], "-pal") == 0) + { + Settings.ForcePAL = TRUE; + } + else if (strcasecmp (argv [i], "-n") == 0 || + strcasecmp (argv [i], "-ntsc") == 0) + { + Settings.ForceNTSC = TRUE; + } + else if (strcasecmp (argv [i], "-f") == 0 || + strcasecmp (argv [i], "-frameskip") == 0) + { + if (i + 1 < argc) + Settings.SkipFrames = atoi (argv [++i]) + 1; + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-fh") == 0 || + strcasecmp (argv [i], "-hr") == 0 || + strcasecmp (argv [i], "-hirom") == 0) + Settings.ForceHiROM = TRUE; + else if (strcasecmp (argv [i], "-fl") == 0 || + strcasecmp (argv [i], "-lr") == 0 || + strcasecmp (argv [i], "-lorom") == 0) + Settings.ForceLoROM = TRUE; + else if (strcasecmp (argv [i], "-hd") == 0 || + strcasecmp (argv [i], "-header") == 0 || + strcasecmp (argv [i], "-he") == 0) + { + Settings.ForceHeader = TRUE; + } + else if (strcasecmp (argv [i], "-nhd") == 0 || + strcasecmp (argv [i], "-noheader") == 0) + { + Settings.ForceNoHeader = TRUE; + } + else if (strcasecmp (argv [i], "-bs") == 0) + { + Settings.BS = TRUE; + } +#ifdef DEBUGGER + else if (strcasecmp (argv [i], "-d") == 0 || + strcasecmp (argv [i], "-debug") == 0) + { + CPU.Flags |= DEBUG_MODE_FLAG; + } + else if (strcasecmp (argv [i], "-t") == 0 || + strcasecmp (argv [i], "-trace") == 0) + { + trace = fopen ("trace.log", "wb"); + CPU.Flags |= TRACE_FLAG; + } +#endif + else if (strcasecmp (argv [i], "-L") == 0 || + strcasecmp (argv [i], "-layering") == 0) + Settings.BGLayering = TRUE; + else if (strcasecmp (argv [i], "-nl") == 0 || + strcasecmp (argv [i], "-nolayering") == 0) + Settings.BGLayering = FALSE; + else if (strcasecmp (argv [i], "-O") == 0 || + strcasecmp (argv [i], "-tileredraw") == 0) + { + } + else if (strcasecmp (argv [i], "-no") == 0 || + strcasecmp (argv [i], "-lineredraw") == 0) + { + } + else if (strcasecmp (argv [i], "-tr") == 0 || + strcasecmp (argv [i], "-transparency") == 0) + { + Settings.ForceTransparency = TRUE; + Settings.ForceNoTransparency = FALSE; + } + else if (strcasecmp (argv [i], "-nt") == 0 || + strcasecmp (argv [i], "-notransparency") == 0) + { + Settings.ForceNoTransparency = TRUE; + Settings.ForceTransparency = FALSE; + } + else if (strcasecmp (argv [i], "-hi") == 0 || + strcasecmp (argv [i], "-hires") == 0) + { + Settings.SupportHiRes = TRUE; + } + else if (strcasecmp (argv [i], "-16") == 0 || + strcasecmp (argv [i], "-sixteen") == 0) + { + Settings.SixteenBit = TRUE; + } + else if (strcasecmp (argv [i], "-displayframerate") == 0 || + strcasecmp (argv [i], "-dfr") == 0) + { + Settings.DisplayFrameRate = TRUE; + } + else if (strcasecmp (argv [i], "-s") == 0 || + strcasecmp (argv [i], "-swapjoypads") == 0 || + strcasecmp (argv [i], "-sw") == 0) + Settings.SwapJoypads = TRUE; + else if (strcasecmp (argv [i], "-i") == 0 || + strcasecmp (argv [i], "-interleaved") == 0) + Settings.ForceInterleaved = TRUE; + else if (strcasecmp (argv [i], "-i2") == 0 || + strcasecmp (argv [i], "-interleaved2") == 0) + Settings.ForceInterleaved2 = TRUE; + else if (strcasecmp (argv [i], "-ni") == 0 || + strcasecmp (argv [i], "-nointerleave") == 0) + Settings.ForceNotInterleaved = TRUE; + else if (strcasecmp (argv [i], "-noirq") == 0) + Settings.DisableIRQ = TRUE; + else if (strcasecmp (argv [i], "-nw") == 0 || + strcasecmp (argv [i], "-nowindows") == 0) + { + Settings.DisableGraphicWindows = TRUE; + } + else if (strcasecmp (argv [i], "-windows") == 0) + { + Settings.DisableGraphicWindows = FALSE; + } + else if (strcasecmp (argv [i], "-im7") == 0) + { + Settings.Mode7Interpolate = TRUE; + } + else if (strcasecmp (argv [i], "-gg") == 0 || + strcasecmp (argv [i], "-gamegenie") == 0) + { + if (i + 1 < argc) + { + uint32 address; + uint8 byte; + const char *error; + if ((error = S9xGameGenieToRaw (argv [++i], address, byte)) == NULL) + S9xAddCheat (TRUE, FALSE, address, byte); + else + S9xMessage (S9X_ERROR, S9X_GAME_GENIE_CODE_ERROR, + error); + } + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-ar") == 0 || + strcasecmp (argv [i], "-actionreplay") == 0) + { + if (i + 1 < argc) + { + uint32 address; + uint8 byte; + const char *error; + if ((error = S9xProActionReplayToRaw (argv [++i], address, byte)) == NULL) + S9xAddCheat (TRUE, FALSE, address, byte); + else + S9xMessage (S9X_ERROR, S9X_ACTION_REPLY_CODE_ERROR, + error); + } + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-gf") == 0 || + strcasecmp (argv [i], "-goldfinger") == 0) + { + if (i + 1 < argc) + { + uint32 address; + uint8 bytes [3]; + bool8 sram; + uint8 num_bytes; + const char *error; + if ((error = S9xGoldFingerToRaw (argv [++i], address, sram, + num_bytes, bytes)) == NULL) + { + for (int c = 0; c < num_bytes; c++) + S9xAddCheat (TRUE, FALSE, address + c, bytes [c]); + } + else + S9xMessage (S9X_ERROR, S9X_GOLD_FINGER_CODE_ERROR, + error); + } + else + S9xUsage (); + } + else if (strcasecmp (argv[i], "-ft") == 0 || + strcasecmp (argv [i], "-frametime") == 0) + { + if (i + 1 < argc) + { + double ft; + if (sscanf (argv [++i], "%lf", &ft) == 1) + { +#ifdef __WIN32__ + Settings.FrameTimePAL = (int32) (ft * 1000); + Settings.FrameTimeNTSC = (int32) (ft * 1000); +#else + Settings.FrameTimePAL = (int32) ft; + Settings.FrameTimeNTSC = (int32) ft; +#endif + + } + } + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-e") == 0 || + strcasecmp (argv [i], "-echo") == 0) + Settings.DisableSoundEcho = FALSE; + else if (strcasecmp (argv [i], "-ne") == 0 || + strcasecmp (argv [i], "-noecho") == 0) + Settings.DisableSoundEcho = TRUE; + else if (strcasecmp (argv [i], "-r") == 0 || + strcasecmp (argv [i], "-soundquality") == 0 || + strcasecmp (argv [i], "-sq") == 0) + { + if (i + 1 < argc) + Settings.SoundPlaybackRate = atoi (argv [++i]) & 7; + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-stereo") == 0 || + strcasecmp (argv [i], "-st") == 0) + { + Settings.Stereo = TRUE; + Settings.APUEnabled = TRUE; + Settings.NextAPUEnabled = TRUE; + } + else if (strcasecmp (argv [i], "-mono") == 0) + { + Settings.Stereo = FALSE; + Settings.NextAPUEnabled = TRUE; + } + else if (strcasecmp (argv [i], "-envx") == 0 || + strcasecmp (argv [i], "-ex") == 0) + { + Settings.SoundEnvelopeHeightReading = TRUE; + } + else if (strcasecmp (argv [i], "-nosamplecaching") == 0 || + strcasecmp (argv [i], "-nsc") == 0 || + strcasecmp (argv [i], "-nc") == 0) + { + Settings.DisableSampleCaching = TRUE; + } + else if (strcasecmp (argv [i], "-nomastervolume") == 0 || + strcasecmp (argv [i], "-nmv") == 0) + { + Settings.DisableMasterVolume = TRUE; + } + else if (strcasecmp (argv [i], "-soundsync") == 0 || + strcasecmp (argv [i], "-sy") == 0) + { + Settings.SoundSync = TRUE; + Settings.SoundEnvelopeHeightReading = TRUE; + Settings.InterpolatedSound = TRUE; + } + else if (strcasecmp (argv [i], "-soundsync2") == 0 || + strcasecmp (argv [i], "-sy2") == 0) + { + Settings.SoundSync = 2; + Settings.SoundEnvelopeHeightReading = TRUE; + Settings.InterpolatedSound = TRUE; + } + else if (strcasecmp (argv [i], "-interpolatedsound") == 0 || + strcasecmp (argv [i], "-is") == 0) + { + Settings.InterpolatedSound = TRUE; + } +#ifdef USE_THREADS + else if (strcasecmp (argv [i], "-threadsound") == 0 || + strcasecmp (argv [i], "-ts") == 0) + { + Settings.ThreadSound = TRUE; + } +#endif + else if (strcasecmp (argv [i], "-alt") == 0 || + strcasecmp (argv [i], "-altsampledecode") == 0) + { + Settings.AltSampleDecode = 1; + } + else if (strcasecmp (argv [i], "-fix") == 0) + { + Settings.FixFrequency = 1; + } + else if (strcasecmp (argv [i], "-nosuperfx") == 0 || + strcasecmp (argv [i], "-nosfx") == 0) + Settings.ForceNoSuperFX = TRUE; + else if (strcasecmp (argv [i], "-superfx") == 0 || + strcasecmp (argv [i], "-sfx") == 0) + Settings.ForceSuperFX = TRUE; + else if (strcasecmp (argv [i], "-dsp1") == 0) + Settings.ForceDSP1 = TRUE; + else if (strcasecmp (argv [i], "-nodsp1") == 0) + Settings.ForceNoDSP1 = TRUE; + else if (strcasecmp (argv [i], "-nomultiplayer5") == 0 || + strcasecmp (argv [i], "-nmp") == 0) + Settings.MultiPlayer5 = FALSE; + else if (strcasecmp (argv [i], "-multiplayer5") == 0 || + strcasecmp (argv [i], "-mp") == 0) + { + Settings.MultiPlayer5 = TRUE; + Settings.ControllerOption = SNES_MULTIPLAYER5; + } + else if (strcasecmp (argv [i], "-mouse") == 0 || + strcasecmp (argv [i], "-mo") == 0) + { + Settings.ControllerOption = SNES_MOUSE_SWAPPED; + Settings.Mouse = TRUE; + } + else if (strcasecmp (argv [i], "-nomouse") == 0 || + strcasecmp (argv [i], "-nm") == 0) + { + Settings.Mouse = FALSE; + } + else if (strcasecmp (argv [i], "-superscope") == 0 || + strcasecmp (argv [i], "-ss") == 0) + { + Settings.SuperScope = TRUE; + Settings.ControllerOption = SNES_SUPERSCOPE; + } + else if (strcasecmp (argv [i], "-nosuperscope") == 0 || + strcasecmp (argv [i], "-nss") == 0) + { + Settings.SuperScope = FALSE; + } +#ifdef NETPLAY_SUPPORT + else if (strcasecmp (argv [i], "-port") == 0 || + strcasecmp (argv [i], "-po") == 0) + { + if (i + 1 < argc) + { + Settings.NetPlay = TRUE; + Settings.Port = -atoi (argv [++i]); + } + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-server") == 0 || + strcasecmp (argv [i], "-srv") == 0) + { + if (i + 1 < argc) + { + Settings.NetPlay = TRUE; + strncpy (Settings.ServerName, argv [++i], 127); + Settings.ServerName [127] = 0; + } + else + S9xUsage (); + } + else if (strcasecmp (argv [i], "-net") == 0) + { + Settings.NetPlay = TRUE; + } +#endif +#ifdef STORM + else if (strcasecmp(argv[i],"-nosecondjoy")==0){secondjoy=0;} + else if (strcasecmp(argv[i],"-showfps")==0){dofps=1;} + else if (strcasecmp(argv[i],"-hicolor")==0){hicolor=1;} + else if (strcasecmp(argv[i],"-minimal")==0){minimal=1;printf("Keyboard with exception of ESC switched off!\n");} + else if (strcasecmp(argv[i],"-ahiunit")==0) + { + if (i+1 +#include + +#ifdef __WIN32__ +#include "..\wsnes9x.h" +#include "..\zlib\zlib.h" +#endif + +#include "port.h" +#include "65c816.h" +#include "messages.h" + +#if defined(USE_GLIDE) && !defined(GFX_MULTI_FORMAT) +#define GFX_MULTI_FORMAT +#endif + +#define ROM_NAME_LEN 23 + +#ifdef ZLIB +//#ifndef __WIN32__ +#include "zlib.h" +//#endif +#define STREAM gzFile +#define READ_STREAM(p,l,s) gzread (s,p,l) +#define WRITE_STREAM(p,l,s) gzwrite (s,p,l) +#define OPEN_STREAM(f,m) gzopen (f,m) +#define CLOSE_STREAM(s) gzclose (s) +#define SEEK_STREAM(p,r,s) gzseek(s,p,r) +#else +#ifdef __GP32__ +#define STREAM long * //F_HANDLE * +#define READ_STREAM(p,l,s) gp32_fread ((unsigned char*)p,(long)l,s) +#define WRITE_STREAM(p,l,s) gp32_fwrite ((unsigned char*)p,(long)l,s) +#define OPEN_STREAM(f,m) gp32_fopen ((char*)f,(char*)m) +#define CLOSE_STREAM(s) gp32_fclose (s) +#define SEEK_STREAM(p,r,s) gp32_fseek(p,r,s) + +#else +#define STREAM FILE * +#define READ_STREAM(p,l,s) fread (p,1,l,s) +#define WRITE_STREAM(p,l,s) fwrite (p,1,l,s) +#define OPEN_STREAM(f,m) fopen (f,m) +#define CLOSE_STREAM(s) fclose (s) +#define SEEK_STREAM(p,r,s) fseek(s,p,r) +#define FROM_CURRENT SEEK_CUR +#endif +#endif + + +/* SNES screen width and height */ +#define SNES_WIDTH 256 +#define SNES_HEIGHT 224 +#define SNES_HEIGHT_EXTENDED 239 +#define IMAGE_WIDTH (Settings.SupportHiRes ? SNES_WIDTH * 2 : SNES_WIDTH) +#define IMAGE_HEIGHT (Settings.SupportHiRes ? SNES_HEIGHT_EXTENDED * 2 : SNES_HEIGHT_EXTENDED) + +#define SNES_MAX_NTSC_VCOUNTER 262 +#define SNES_MAX_PAL_VCOUNTER 312 +#define SNES_HCOUNTER_MAX 342 +#define SPC700_TO_65C816_RATIO 2 +#define AUTO_FRAMERATE 200 + +#define PPU_IGNORE_FIXEDCOLCHANGES (1<<0) +#define PPU_IGNORE_WINDOW (1<<1) +#define PPU_IGNORE_ADDSUB (1<<2) +#define PPU_IGNORE_PALWRITE (1<<3) +#define GFX_IGNORE_OBJ (1<<4) +#define GFX_IGNORE_BG0 (1<<5) +#define GFX_IGNORE_BG1 (1<<6) +#define GFX_IGNORE_BG2 (1<<7) +#define GFX_IGNORE_BG3 (1<<8) + +// NTSC master clock signal 21.47727MHz +// PPU: master clock / 4 +// 1 / PPU clock * 342 -> 63.695us +// 63.695us / (1 / 3.579545MHz) -> 228 cycles per scanline +// From Earth Worm Jim: APU executes an average of 65.14285714 cycles per +// scanline giving an APU clock speed of 1.022731096MHz + +// PAL master clock signal 21.28137MHz +// PPU: master clock / 4 +// 1 / PPU clock * 342 -> 64.281us +// 64.281us / (1 / 3.546895MHz) -> 228 cycles per scanline. + +//#define SNES_SCANLINE_TIME (63.695e-6) +//#define SNES_CLOCK_SPEED (3579545) + +//#define SNES_CLOCK_LEN (1.0 / SNES_CLOCK_SPEED) + +//#define SNES_APUTIMER2_CYCLEx10000 ((uint32) 3355824) + +#ifdef VAR_CYCLES +//#define SNES_CYCLES_PER_SCANLINE ((uint32) ((SNES_SCANLINE_TIME / SNES_CLOCK_LEN) * 6 + 0.5)) +#define SNES_CYCLES_PER_SCANLINE ((uint32)(228*6)) +#else +//#define SNES_CYCLES_PER_SCANLINE ((uint32) (SNES_SCANLINE_TIME / SNES_CLOCK_LEN + 0.5)) +#define SNES_CYCLES_PER_SCANLINE ((uint32)(228)) +#endif + +#define SNES_TR_MASK (1 << 4) +#define SNES_TL_MASK (1 << 5) +#define SNES_X_MASK (1 << 6) +#define SNES_A_MASK (1 << 7) +#define SNES_RIGHT_MASK (1 << 8) +#define SNES_LEFT_MASK (1 << 9) +#define SNES_DOWN_MASK (1 << 10) +#define SNES_UP_MASK (1 << 11) +#define SNES_START_MASK (1 << 12) +#define SNES_SELECT_MASK (1 << 13) +#define SNES_Y_MASK (1 << 14) +#define SNES_B_MASK (1 << 15) + +enum { + SNES_MULTIPLAYER5, + SNES_JOYPAD, + SNES_MOUSE_SWAPPED, + SNES_MOUSE, + SNES_SUPERSCOPE, + SNES_JUSTIFIER, + SNES_JUSTIFIER_2, + SNES_MAX_CONTROLLER_OPTIONS +}; + +#define DEBUG_MODE_FLAG (1 << 0) +#define TRACE_FLAG (1 << 1) +#define SINGLE_STEP_FLAG (1 << 2) +#define BREAK_FLAG (1 << 3) +#define SCAN_KEYS_FLAG (1 << 4) +#define SAVE_SNAPSHOT_FLAG (1 << 5) +#define DELAYED_NMI_FLAG (1 << 6) +#define NMI_FLAG (1 << 7) +#define PROCESS_SOUND_FLAG (1 << 8) +#define FRAME_ADVANCE_FLAG (1 << 9) +#define DELAYED_NMI_FLAG2 (1 << 10) +#define IRQ_PENDING_FLAG (1 << 11) + +#ifdef VAR_CYCLES +#define ONE_CYCLE 6 +#define SLOW_ONE_CYCLE 8 +#define TWO_CYCLES 12 +#else +#define ONE_CYCLE 1 +#define SLOW_ONE_CYCLE 1 +#define TWO_CYCLES 2 +#endif + + +#undef MEMMAP_BLOCK_SIZE +#define MEMMAP_BLOCK_SIZE (0x1000) +#undef MEMMAP_NUM_BLOCKS +#define MEMMAP_NUM_BLOCKS (0x1000000 / MEMMAP_BLOCK_SIZE) + +struct SCPUState{ + uint32 Flags; //0 + bool8 BranchSkip; //4 + bool8 NMIActive; //5 + bool8 IRQActive; //6 + bool8 WaitingForInterrupt; //7 + struct SRegisters Regs; //8 + //uint8 PB; //8 --> status + //uint8 DB; //9 + //pair P; //10 + //pair A; //12 + //pair D; //14 + //pair X; //16 + //pair S; //18 + //pair Y; //20 + //uint16 PC; //22 + uint8 *PC; //24 + int32 Cycles; //28 + uint8 *PCBase; //32 + uint8 *PCAtOpcodeStart; //36 + uint8 *WaitAddress; //40 + uint32 WaitCounter; //44 + volatile int32 NextEvent; //48 + int32 V_Counter; //52 + int32 MemSpeed; //56 + int32 MemSpeedx2; //60 + int32 FastROMSpeed; //64 + uint32 AutoSaveTimer; //68 + uint32 NMITriggerPoint; //72 + uint32 NMICycleCount; //76 + uint32 IRQCycleCount; //80 + + bool8 InDMA; //84 + uint8 WhichEvent; //85 + bool8 SRAMModified; //86 + bool8 BRKTriggered; //87 + uint32 _ARM_asm_reserved_1; //88 to stock current jmp table + bool8 TriedInterleavedMode2; //92 + bool8 _ARM_asm_padding1[3]; //93 + + uint8* Memory_Map; //96 + uint8* Memory_WriteMap; //100 + uint32* Memory_MemorySpeed; //104 + uint8* Memory_BlockIsRAM; //108 + uint8* Memory_SRAM; //112 + uint8* Memory_BWRAM; //116 + uint32 Memory_SRAMMask; //120 + bool32 APU_APUExecuting; //124 + bool32 _ARM_asm_padding2; //128 + uint32 _PALMSOS_R9; //132 + uint32 _PALMSOS_R10; //136 + volatile int32 APU_Cycles; //140 notaz + void *DSPGet; + void *DSPSet; + int32 rstatus; +}; + + +#define HBLANK_START_EVENT 0 +#define HBLANK_END_EVENT 1 +#define HTIMER_BEFORE_EVENT 2 +#define HTIMER_AFTER_EVENT 3 +#define NO_EVENT 4 + +struct SSettings{ + // CPU options + bool8 APUEnabled; + bool8 Shutdown; + + uint8 SoundSkipMethod; + long H_Max; + long HBlankStart; + long CyclesPercentage; + bool8 DisableIRQ; + bool8 Paused; + bool8 ForcedPause; + bool8 StopEmulation; + + // Tracing options + bool8 TraceDMA; + bool8 TraceHDMA; + bool8 TraceVRAM; + bool8 TraceUnknownRegisters; + bool8 TraceDSP; + + // Joystick options + bool8 SwapJoypads; + bool8 JoystickEnabled; + + // ROM timing options (see also H_Max above) + bool8 ForcePAL; + bool8 ForceNTSC; + bool8 PAL; + uint32 FrameTimePAL; + uint32 FrameTimeNTSC; + uint32 FrameTime; + uint32 SkipFrames; + + // ROM image options + bool8 ForceLoROM; + bool8 ForceHiROM; + bool8 ForceHeader; + bool8 ForceNoHeader; + bool8 ForceInterleaved; + bool8 ForceInterleaved2; + bool8 ForceNotInterleaved; + + // Peripherial options + bool8 ForceSuperFX; + bool8 ForceNoSuperFX; + bool8 ForceDSP1; + bool8 ForceNoDSP1; + bool8 ForceSA1; + bool8 ForceNoSA1; + bool8 ForceC4; + bool8 ForceNoC4; + bool8 ForceSDD1; + bool8 ForceNoSDD1; + bool8 MultiPlayer5; + bool8 Mouse; + bool8 SuperScope; + bool8 SRTC; + uint32 ControllerOption; + + bool8 ShutdownMaster; + bool8 MultiPlayer5Master; + bool8 SuperScopeMaster; + bool8 MouseMaster; + bool8 SuperFX; + bool8 DSP1Master; + bool8 SA1; + bool8 C4; + bool8 SDD1; + + // Sound options + uint32 SoundPlaybackRate; + bool8 TraceSoundDSP; + bool8 Stereo; + bool8 ReverseStereo; + bool8 SixteenBitSound; + int SoundBufferSize; + int SoundMixInterval; + bool8 SoundEnvelopeHeightReading; + bool8 DisableSoundEcho; + bool8 DisableSampleCaching; + bool8 DisableMasterVolume; + bool8 SoundSync; + bool8 InterpolatedSound; + bool8 ThreadSound; + bool8 Mute; +// bool8 NextAPUEnabled; + uint8 AltSampleDecode; + bool8 FixFrequency; + + // Graphics options + bool8 SixteenBit; + bool8 Transparency; + bool8 SupportHiRes; + bool8 Mode7Interpolate; + + // SNES graphics options + bool8 BGLayering; + bool8 DisableGraphicWindows; + bool8 ForceTransparency; + bool8 ForceNoTransparency; + bool8 DisableHDMA; + bool8 DisplayFrameRate; + + // Others + bool8 NetPlay; + bool8 NetPlayServer; + char ServerName [128]; + int Port; + bool8 GlideEnable; + bool8 OpenGLEnable; + int32 AutoSaveDelay; // Time in seconds before S-RAM auto-saved if modified. + bool8 ApplyCheats; + bool8 TurboMode; + uint32 TurboSkipFrames; + uint32 AutoMaxSkipFrames; + uint32 os9x_hack; + +// Fixes for individual games + uint32 StrikeGunnerOffsetHack; + bool8 ChuckRock; + bool8 StarfoxHack; + bool8 WinterGold; + bool8 Dezaemon; + bool8 WrestlemaniaArcade; + bool8 BS; // Japanese Satellite System games. + bool8 DaffyDuck; + uint8 APURAMInitialValue; + bool8 SDD1Pack; + + bool8 asmspc700; + bool8 SpeedHacks; +#ifdef __WIN32__ + int SoundDriver; +#endif +}; + +struct SSNESGameFixes +{ + uint8 NeedInit0x2137; + uint8 umiharakawaseFix; + uint8 alienVSpredetorFix; + uint8 APU_OutPorts_ReturnValueFix; + uint8 Old_Read0x4200; + uint8 _0x213E_ReturnValue; + uint8 TouhaidenControllerFix; + uint8 SoundEnvelopeHeightReading2; + uint8 SRAMInitialValue; + uint8 Uniracers; + uint8 Flintstones; + uint8 Mode7Hack; +}; + +START_EXTERN_C +extern struct SSettings Settings; +extern struct SCPUState CPU; +extern struct SSNESGameFixes SNESGameFixes; +extern char String [513]; + +void S9xExit (); +void S9xMessage (int type, int number, const char *message); +void S9xLoadSDD1Data (); +END_EXTERN_C + +enum { + PAUSE_NETPLAY_CONNECT = (1 << 0), + PAUSE_TOGGLE_FULL_SCREEN = (1 << 1), + PAUSE_EXIT = (1 << 2), + PAUSE_MENU = (1 << 3), + PAUSE_INACTIVE_WINDOW = (1 << 4), + PAUSE_WINDOW_ICONISED = (1 << 5), + PAUSE_RESTORE_GUI = (1 << 6), + PAUSE_FREEZE_FILE = (1 << 7) +}; +void S9xSetPause (uint32 mask); +void S9xClearPause (uint32 mask); + +#endif diff --git a/src/soundux.cpp b/src/soundux.cpp new file mode 100644 index 0000000..5b46f07 --- /dev/null +++ b/src/soundux.cpp @@ -0,0 +1,1200 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifdef __DJGPP__ +#include +#undef TRUE +#endif + +#include +#include +#include +#include +#include +//#include + +#define CLIP16(v) \ +if ((v) < -32768) \ + (v) = -32768; \ +else \ +if ((v) > 32767) \ + (v) = 32767 + +#define CLIP16_latch(v,l) \ +if ((v) < -32768) \ +{ (v) = -32768; (l)++; }\ +else \ +if ((v) > 32767) \ +{ (v) = 32767; (l)++; } + +#define CLIP24(v) \ +if ((v) < -8388608) \ + (v) = -8388608; \ +else \ +if ((v) > 8388607) \ + (v) = 8388607 + +/* +#define CLIP8(v) \ +if ((v) < -128) \ + (v) = -128; \ +else \ +if ((v) > 127) \ + (v) = 127 +*/ + + +#include "snes9x.h" +#include "soundux.h" +#include "apu.h" +#include "memmap.h" +#include "cpuexec.h" +#include "asmmemfuncs.h" + + +static int wave[SOUND_BUFFER_SIZE]; + +//extern int Echo [24000]; +extern int MixBuffer [SOUND_BUFFER_SIZE]; +//extern int EchoBuffer [SOUND_BUFFER_SIZE]; +//extern int FilterTaps [8]; +extern unsigned long Z; +//extern int Loop [16]; + +extern long FilterValues[4][2]; +//extern int NoiseFreq [32]; + +//#define FIXED_POINT 0x10000UL +#define FIXED_POINT_REMAINDER 0xffffUL +#define FIXED_POINT_SHIFT 16 + +#define VOL_DIV8 0x8000 +#define VOL_DIV16 0x0080 +#define ENVX_SHIFT 24 + +extern "C" void DecodeBlockAsm (int8 *, int16 *, int32 *, int32 *); + +// F is channel's current frequency and M is the 16-bit modulation waveform +// from the previous channel multiplied by the current envelope volume level. +#define PITCH_MOD(F,M) ((F) * ((((unsigned long) (M)) + 0x800000) >> 16) >> 7) +//#define PITCH_MOD(F,M) ((F) * ((((M) & 0x7fffff) >> 14) + 1) >> 8) + +#define LAST_SAMPLE 0xffffff +#define JUST_PLAYED_LAST_SAMPLE(c) ((c)->sample_pointer >= LAST_SAMPLE) + + +static inline void S9xAPUSetEndOfSample (int i, Channel *ch) +{ + ch->state = SOUND_SILENT; + ch->mode = MODE_NONE; + APU.DSP [APU_ENDX] |= 1 << i; + APU.DSP [APU_KON] &= ~(1 << i); + APU.DSP [APU_KOFF] &= ~(1 << i); + APU.KeyedChannels &= ~(1 << i); +} +#ifdef __DJGPP +END_OF_FUNCTION (S9xAPUSetEndOfSample) +#endif + +static inline void S9xAPUSetEndX (int ch) +{ + APU.DSP [APU_ENDX] |= 1 << ch; +} +#ifdef __DJGPP +END_OF_FUNCTION (S9xAPUSetEndX) +#endif + +void S9xSetEchoDelay (int delay) +{ + SoundData.echo_buffer_size = (512 * delay * so.playback_rate) >> 15; // notaz / 32000; + if (so.stereo) + SoundData.echo_buffer_size <<= 1; + if (SoundData.echo_buffer_size) { + while(SoundData.echo_ptr >= SoundData.echo_buffer_size) + SoundData.echo_ptr -= SoundData.echo_buffer_size; + } else + SoundData.echo_ptr = 0; + S9xSetEchoEnable (APU.DSP [APU_EON]); +} + +void S9xSetSoundKeyOff (int channel) +{ + Channel *ch = &SoundData.channels[channel]; + + if (ch->state != SOUND_SILENT) + { + ch->state = SOUND_RELEASE; + ch->mode = MODE_RELEASE; + S9xSetEnvRate (ch, 8, -1, 0, 5<<28); + } +} + +void S9xFixSoundAfterSnapshotLoad () +{ + SoundData.echo_write_enabled = !(APU.DSP [APU_FLG] & 0x20); + SoundData.echo_channel_enable = APU.DSP [APU_EON]; + S9xSetEchoDelay (APU.DSP [APU_EDL] & 0xf); + S9xSetEchoFeedback ((signed char) APU.DSP [APU_EFB]); + + S9xSetFilterCoefficient (0, (signed char) APU.DSP [APU_C0]); + S9xSetFilterCoefficient (1, (signed char) APU.DSP [APU_C1]); + S9xSetFilterCoefficient (2, (signed char) APU.DSP [APU_C2]); + S9xSetFilterCoefficient (3, (signed char) APU.DSP [APU_C3]); + S9xSetFilterCoefficient (4, (signed char) APU.DSP [APU_C4]); + S9xSetFilterCoefficient (5, (signed char) APU.DSP [APU_C5]); + S9xSetFilterCoefficient (6, (signed char) APU.DSP [APU_C6]); + S9xSetFilterCoefficient (7, (signed char) APU.DSP [APU_C7]); + + for (int i = 0; i < 8; i++) + { + SoundData.channels[i].needs_decode = TRUE; + S9xSetSoundFrequency (i, SoundData.channels[i].hertz); + SoundData.channels [i].envxx = SoundData.channels [i].envx << ENVX_SHIFT; + SoundData.channels [i].next_sample = 0; + SoundData.channels [i].previous [0] = (int32) SoundData.channels [i].previous16 [0]; + SoundData.channels [i].previous [1] = (int32) SoundData.channels [i].previous16 [1]; + } + SoundData.master_volume [0] = SoundData.master_volume_left; + SoundData.master_volume [1] = SoundData.master_volume_right; + SoundData.echo_volume [0] = SoundData.echo_volume_left; + SoundData.echo_volume [1] = SoundData.echo_volume_right; + IAPU.Scanline = 0; +} + +void S9xSetEnvelopeHeight (int channel, int level) +{ + Channel *ch = &SoundData.channels[channel]; + + ch->envx = level; + ch->envxx = level << ENVX_SHIFT; + + ch->left_vol_level = (level * ch->volume_left) / 128; + ch->right_vol_level = (level * ch->volume_right) / 128; + + if (ch->envx == 0 && ch->state != SOUND_SILENT && ch->state != SOUND_GAIN) + { + S9xAPUSetEndOfSample (channel, ch); + } +} + +#if 1 +void S9xSetSoundSample (int, uint16) +{ +} +#else +void S9xSetSoundSample (int channel, uint16 sample_number) +{ + register Channel *ch = &SoundData.channels[channel]; + + if (ch->state != SOUND_SILENT && + sample_number != ch->sample_number) + { + int keep = ch->state; + ch->state = SOUND_SILENT; + ch->sample_number = sample_number; + ch->loop = FALSE; + ch->needs_decode = TRUE; + ch->last_block = FALSE; + ch->previous [0] = ch->previous[1] = 0; + ch->block_pointer = *S9xGetSampleAddress(sample_number); + ch->sample_pointer = 0; + ch->state = keep; + } +} +#endif + +static void DecodeBlock (Channel *ch) +{ + if (ch->block_pointer >= 0x10000 - 9) + { + ch->last_block = TRUE; + ch->loop = FALSE; + ch->block = ch->decoded; + memset32 ((uint32_t *) ch->decoded, 0, 8); + return; + } + signed char *compressed = (signed char *) &IAPU.RAM [ch->block_pointer]; + + unsigned char filter = *compressed; + if ((ch->last_block = filter & 1)) + ch->loop = (filter & 2) != 0; + + int16 *raw = ch->block = ch->decoded; + +#ifdef ARM + DecodeBlockAsm (compressed, raw, &ch->previous [0], &ch->previous [1]); +#else + int32 out; + unsigned char shift; + signed char sample1, sample2; + unsigned int i; + + compressed++; + + int32 prev0 = ch->previous [0]; + int32 prev1 = ch->previous [1]; + shift = filter >> 4; + + switch ((filter >> 2) & 3) + { + case 0: + for (i = 8; i != 0; i--) + { + sample1 = *compressed++; + sample2 = sample1 << 4; + sample2 >>= 4; + sample1 >>= 4; + *raw++ = ((int32) sample1 << shift); + *raw++ = ((int32) sample2 << shift); + } + prev1 = *(raw - 2); + prev0 = *(raw - 1); + break; + case 1: + for (i = 8; i != 0; i--) + { + sample1 = *compressed++; + sample2 = sample1 << 4; + sample2 >>= 4; + sample1 >>= 4; + prev0 = (int16) prev0; + *raw++ = prev1 = ((int32) sample1 << shift) + prev0 - (prev0 >> 4); + prev1 = (int16) prev1; + *raw++ = prev0 = ((int32) sample2 << shift) + prev1 - (prev1 >> 4); + } + break; + case 2: + for (i = 8; i != 0; i--) + { + sample1 = *compressed++; + sample2 = sample1 << 4; + sample2 >>= 4; + sample1 >>= 4; + + out = (sample1 << shift) - prev1 + (prev1 >> 4); + prev1 = (int16) prev0; + prev0 &= ~3; + *raw++ = prev0 = out + (prev0 << 1) - (prev0 >> 5) - + (prev0 >> 4); + + out = (sample2 << shift) - prev1 + (prev1 >> 4); + prev1 = (int16) prev0; + prev0 &= ~3; + *raw++ = prev0 = out + (prev0 << 1) - (prev0 >> 5) - + (prev0 >> 4); + } + break; + case 3: + for (i = 8; i != 0; i--) + { + sample1 = *compressed++; + sample2 = sample1 << 4; + sample2 >>= 4; + sample1 >>= 4; + out = (sample1 << shift); + + out = out - prev1 + (prev1 >> 3) + (prev1 >> 4); + prev1 = (int16) prev0; + prev0 &= ~3; + *raw++ = prev0 = out + (prev0 << 1) - (prev0 >> 3) - + (prev0 >> 4) - (prev1 >> 6); + + out = (sample2 << shift); + out = out - prev1 + (prev1 >> 3) + (prev1 >> 4); + prev1 = (int16) prev0; + prev0 &= ~3; + *raw++ = prev0 = out + (prev0 << 1) - (prev0 >> 3) - + (prev0 >> 4) - (prev1 >> 6); + } + break; + } + ch->previous [0] = prev0; + ch->previous [1] = prev1; + +#endif + ch->block_pointer += 9; +} + + +static void MixStereo (int sample_count) +{ + int pitch_mod = SoundData.pitch_mod & (0xFFFFFFFF^APU.DSP[APU_NON]);//~APU.DSP[APU_NON]; + + for (uint32 J = 0; J < NUM_CHANNELS; J++) + { + int32 VL, VR; + Channel *ch = &SoundData.channels[J]; + unsigned long freq0 = ch->frequency; + + if (ch->state == SOUND_SILENT) + continue; + +// freq0 = (unsigned long) ((double) freq0 * 0.985);//uncommented by jonathan gevaryahu, as it is necessary for most cards in linux + + bool8 mod = pitch_mod & (1 << J); + + if (ch->needs_decode) + { + DecodeBlock(ch); + ch->needs_decode = FALSE; + ch->sample = ch->block[0]; + ch->sample_pointer = freq0 >> FIXED_POINT_SHIFT; + if (ch->sample_pointer == 0) + ch->sample_pointer = 1; + if (ch->sample_pointer > SOUND_DECODE_LENGTH) + ch->sample_pointer = SOUND_DECODE_LENGTH - 1; + + ch->next_sample = ch->block[ch->sample_pointer]; + } + VL = (ch->sample * ch-> left_vol_level) / 128; + VR = (ch->sample * ch->right_vol_level) / 128; + + for (uint32 I = 0; I < (uint32) sample_count; I += 2) + { + unsigned long freq = freq0; + + if (mod) + freq = PITCH_MOD(freq, wave [I / 2]); + + ch->env_error += ch->erate; + if (ch->env_error >= FIXED_POINT) + { + uint32 step = ch->env_error >> FIXED_POINT_SHIFT; + + switch (ch->state) + { + case SOUND_ATTACK: + ch->env_error &= FIXED_POINT_REMAINDER; + ch->envx += step << 1; + ch->envxx = ch->envx << ENVX_SHIFT; + + if (ch->envx >= 126) + { + ch->envx = 127; + ch->envxx = 127 << ENVX_SHIFT; + ch->state = SOUND_DECAY; + if (ch->sustain_level != 8) + { + S9xSetEnvRate (ch, ch->decay_rate, -1, + (MAX_ENVELOPE_HEIGHT * ch->sustain_level) >> 3, 1<<28); + break; + } + ch->state = SOUND_SUSTAIN; + S9xSetEnvRate (ch, ch->sustain_rate, -1, 0, 2<<28); + } + break; + + case SOUND_DECAY: + while (ch->env_error >= FIXED_POINT) + { + ch->envxx = (ch->envxx >> 8) * 255; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + if (ch->envx <= ch->envx_target) + { + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto stereo_exit; + } + ch->state = SOUND_SUSTAIN; + S9xSetEnvRate (ch, ch->sustain_rate, -1, 0, 2<<28); + } + break; + + case SOUND_SUSTAIN: + while (ch->env_error >= FIXED_POINT) + { + ch->envxx = (ch->envxx >> 8) * 255; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto stereo_exit; + } + break; + + case SOUND_RELEASE: + while (ch->env_error >= FIXED_POINT) + { + ch->envxx -= (MAX_ENVELOPE_HEIGHT << ENVX_SHIFT) / 256; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto stereo_exit; + } + break; + + case SOUND_INCREASE_LINEAR: + ch->env_error &= FIXED_POINT_REMAINDER; + ch->envx += step << 1; + ch->envxx = ch->envx << ENVX_SHIFT; + + if (ch->envx >= 126) + { + ch->envx = 127; + ch->envxx = 127 << ENVX_SHIFT; + ch->state = SOUND_GAIN; + ch->mode = MODE_GAIN; + S9xSetEnvRate (ch, 0, -1, 0, 0); + } + break; + + case SOUND_INCREASE_BENT_LINE: + if (ch->envx >= (MAX_ENVELOPE_HEIGHT * 3) / 4) + { + while (ch->env_error >= FIXED_POINT) + { + ch->envxx += (MAX_ENVELOPE_HEIGHT << ENVX_SHIFT) / 256; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + } + else + { + ch->env_error &= FIXED_POINT_REMAINDER; + ch->envx += step << 1; + ch->envxx = ch->envx << ENVX_SHIFT; + } + + if (ch->envx >= 126) + { + ch->envx = 127; + ch->envxx = 127 << ENVX_SHIFT; + ch->state = SOUND_GAIN; + ch->mode = MODE_GAIN; + S9xSetEnvRate (ch, 0, -1, 0, 0); + } + break; + + case SOUND_DECREASE_LINEAR: + ch->env_error &= FIXED_POINT_REMAINDER; + ch->envx -= step << 1; + ch->envxx = ch->envx << ENVX_SHIFT; + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto stereo_exit; + } + break; + + case SOUND_DECREASE_EXPONENTIAL: + while (ch->env_error >= FIXED_POINT) + { + ch->envxx = (ch->envxx >> 8) * 255; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto stereo_exit; + } + break; + + case SOUND_GAIN: + S9xSetEnvRate (ch, 0, -1, 0, 0); + break; + } + ch-> left_vol_level = (ch->envx * ch->volume_left) / 128; + ch->right_vol_level = (ch->envx * ch->volume_right) / 128; + VL = (ch->sample * ch-> left_vol_level) / 128; + VR = (ch->sample * ch->right_vol_level) / 128; + } + + ch->count += freq; + if (ch->count >= FIXED_POINT) + { + VL = ch->count >> FIXED_POINT_SHIFT; + ch->sample_pointer += VL; + ch->count &= FIXED_POINT_REMAINDER; + + ch->sample = ch->next_sample; + if (ch->sample_pointer >= SOUND_DECODE_LENGTH) + { + if (JUST_PLAYED_LAST_SAMPLE(ch)) + { + S9xAPUSetEndOfSample (J, ch); + goto stereo_exit; + } + do + { + ch->sample_pointer -= SOUND_DECODE_LENGTH; + if (ch->last_block) + { + if (!ch->loop) + { + ch->sample_pointer = LAST_SAMPLE; + ch->next_sample = ch->sample; + break; + } + else + { + S9xAPUSetEndX (J); + ch->last_block = FALSE; + uint16 *dir = S9xGetSampleAddress (ch->sample_number); + ch->block_pointer = *(dir + 1); + } + } + DecodeBlock (ch); + } while (ch->sample_pointer >= SOUND_DECODE_LENGTH); + if (!JUST_PLAYED_LAST_SAMPLE (ch)) + ch->next_sample = ch->block [ch->sample_pointer]; + } + else + ch->next_sample = ch->block [ch->sample_pointer]; + + if (ch->type != SOUND_SAMPLE) + { + for (;VL > 0; VL--) + if ((so.noise_gen <<= 1) & 0x80000000L) + so.noise_gen ^= 0x0040001L; + ch->sample = (so.noise_gen << 17) >> 17; + } + + VL = (ch->sample * ch-> left_vol_level) / 128; + VR = (ch->sample * ch->right_vol_level) / 128; + } + + if (pitch_mod & (1 << (J + 1))) + wave [I / 2] = ch->sample * ch->envx; + + MixBuffer [I] += VL; + MixBuffer [I+1] += VR; + if (ch->echo_buf_ptr) + { + ch->echo_buf_ptr [I] += VL; + ch->echo_buf_ptr [I+1] += VR; + } + } +stereo_exit: ; + } +} + +static void MixMono (int sample_count) +{ + int pitch_mod = SoundData.pitch_mod & (0xFFFFFFFF^APU.DSP[APU_NON]); + + for (uint32 J = 0; J < NUM_CHANNELS; J++) + { + Channel *ch = &SoundData.channels[J]; + unsigned long freq0 = ch->frequency; + + if (ch->state == SOUND_SILENT) + continue; + +// freq0 = (unsigned long) ((double) freq0 * 0.985); + + bool8 mod = pitch_mod & (1 << J); + + if (ch->needs_decode) + { + DecodeBlock(ch); + ch->needs_decode = FALSE; + ch->sample = ch->block[0]; + ch->sample_pointer = freq0 >> FIXED_POINT_SHIFT; + if (ch->sample_pointer == 0) + ch->sample_pointer = 1; + if (ch->sample_pointer > SOUND_DECODE_LENGTH) + ch->sample_pointer = SOUND_DECODE_LENGTH - 1; + ch->next_sample = ch->block[ch->sample_pointer]; + + } + int32 V = (ch->sample * ch->left_vol_level) / 128; + + for (uint32 I = 0; I < (uint32) sample_count; I++) + { + unsigned long freq = freq0; + + if (mod) + freq = PITCH_MOD(freq, wave [I]); + + ch->env_error += ch->erate; + if (ch->env_error >= FIXED_POINT) + { + uint32 step = ch->env_error >> FIXED_POINT_SHIFT; + + switch (ch->state) + { + case SOUND_ATTACK: + ch->env_error &= FIXED_POINT_REMAINDER; + ch->envx += step << 1; + ch->envxx = ch->envx << ENVX_SHIFT; + + if (ch->envx >= 126) + { + ch->envx = 127; + ch->envxx = 127 << ENVX_SHIFT; + ch->state = SOUND_DECAY; + if (ch->sustain_level != 8) + { + S9xSetEnvRate (ch, ch->decay_rate, -1, + (MAX_ENVELOPE_HEIGHT * ch->sustain_level) >> 3, 1<<28); + break; + } + ch->state = SOUND_SUSTAIN; + S9xSetEnvRate (ch, ch->sustain_rate, -1, 0, 2<<28); + } + break; + + case SOUND_DECAY: + while (ch->env_error >= FIXED_POINT) + { + ch->envxx = (ch->envxx >> 8) * 255; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + if (ch->envx <= ch->envx_target) + { + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto mono_exit; + } + ch->state = SOUND_SUSTAIN; + S9xSetEnvRate (ch, ch->sustain_rate, -1, 0, 2<<28); + } + break; + + case SOUND_SUSTAIN: + while (ch->env_error >= FIXED_POINT) + { + ch->envxx = (ch->envxx >> 8) * 255; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto mono_exit; + } + break; + + case SOUND_RELEASE: + while (ch->env_error >= FIXED_POINT) + { + ch->envxx -= (MAX_ENVELOPE_HEIGHT << ENVX_SHIFT) / 256; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto mono_exit; + } + break; + + case SOUND_INCREASE_LINEAR: + ch->env_error &= FIXED_POINT_REMAINDER; + ch->envx += step << 1; + ch->envxx = ch->envx << ENVX_SHIFT; + + if (ch->envx >= 126) + { + ch->envx = 127; + ch->envxx = 127 << ENVX_SHIFT; + ch->state = SOUND_GAIN; + ch->mode = MODE_GAIN; + S9xSetEnvRate (ch, 0, -1, 0, 0); + } + break; + + case SOUND_INCREASE_BENT_LINE: + if (ch->envx >= (MAX_ENVELOPE_HEIGHT * 3) / 4) + { + while (ch->env_error >= FIXED_POINT) + { + ch->envxx += (MAX_ENVELOPE_HEIGHT << ENVX_SHIFT) / 256; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + } + else + { + ch->env_error &= FIXED_POINT_REMAINDER; + ch->envx += step << 1; + ch->envxx = ch->envx << ENVX_SHIFT; + } + + if (ch->envx >= 126) + { + ch->envx = 127; + ch->envxx = 127 << ENVX_SHIFT; + ch->state = SOUND_GAIN; + ch->mode = MODE_GAIN; + S9xSetEnvRate (ch, 0, -1, 0, 0); + } + break; + + case SOUND_DECREASE_LINEAR: + ch->env_error &= FIXED_POINT_REMAINDER; + ch->envx -= step << 1; + ch->envxx = ch->envx << ENVX_SHIFT; + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto mono_exit; + } + break; + + case SOUND_DECREASE_EXPONENTIAL: + while (ch->env_error >= FIXED_POINT) + { + ch->envxx = (ch->envxx >> 8) * 255; + ch->env_error -= FIXED_POINT; + } + ch->envx = ch->envxx >> ENVX_SHIFT; + if (ch->envx <= 0) + { + S9xAPUSetEndOfSample (J, ch); + goto mono_exit; + } + break; + + case SOUND_GAIN: + S9xSetEnvRate (ch, 0, -1, 0, 0); + break; + } + ch->left_vol_level = (ch->envx * ch->volume_left) / 128; + V = (ch->sample * ch->left_vol_level) / 128; + } + + ch->count += freq; + if (ch->count >= FIXED_POINT) + { + V = ch->count >> FIXED_POINT_SHIFT; + ch->sample_pointer += V; + ch->count &= FIXED_POINT_REMAINDER; + + ch->sample = ch->next_sample; + if (ch->sample_pointer >= SOUND_DECODE_LENGTH) + { + if (JUST_PLAYED_LAST_SAMPLE(ch)) + { + S9xAPUSetEndOfSample (J, ch); + goto mono_exit; + } + do + { + ch->sample_pointer -= SOUND_DECODE_LENGTH; + if (ch->last_block) + { + if (!ch->loop) + { + ch->sample_pointer = LAST_SAMPLE; + ch->next_sample = ch->sample; + break; + } + else + { + ch->last_block = FALSE; + uint16 *dir = S9xGetSampleAddress (ch->sample_number); + ch->block_pointer = *(dir + 1); + S9xAPUSetEndX (J); + } + } + DecodeBlock (ch); + } while (ch->sample_pointer >= SOUND_DECODE_LENGTH); + if (!JUST_PLAYED_LAST_SAMPLE (ch)) + ch->next_sample = ch->block [ch->sample_pointer]; + } + else + ch->next_sample = ch->block [ch->sample_pointer]; + + if (ch->type != SOUND_SAMPLE) + { + for (;V > 0; V--) + if ((so.noise_gen <<= 1) & 0x80000000L) + so.noise_gen ^= 0x0040001L; + ch->sample = (so.noise_gen << 17) >> 17; + } + V = (ch->sample * ch-> left_vol_level) / 128; + } + + MixBuffer [I] += V; + if (ch->echo_buf_ptr) + ch->echo_buf_ptr [I] += V; + + if (pitch_mod & (1 << (J + 1))) + wave [I] = ch->sample * ch->envx; + } +mono_exit: ; + } +} + + +// For backwards compatibility with older port specific code +void S9xMixSamples (signed short *buffer, int sample_count) +{ + S9xMixSamplesO (buffer, sample_count, 0); +} + + +void S9xMixSamplesO (signed short *buffer, int sample_count, int sample_offset) +{ + // 16-bit sound only + int J; + + buffer += sample_offset; + + if (so.mute_sound) + { + memset16((uint16_t*)buffer, 0, sample_count); + return; + } + + memset32 ((uint32_t*)MixBuffer, 0, sample_count); + if (SoundData.echo_enable) + memset32 ((uint32_t*)EchoBuffer, 0, sample_count); + + if (so.stereo) + MixStereo (sample_count); + else + MixMono (sample_count); + + /* Mix and convert waveforms */ + if (SoundData.echo_enable && SoundData.echo_buffer_size) + { + if (so.stereo) + { + int l, r; + int master_vol_l = SoundData.master_volume[0]; + int master_vol_r = SoundData.master_volume[1]; + int echo_vol_l = SoundData.echo_volume[0]; + int echo_vol_r = SoundData.echo_volume[1]; + + // 16-bit stereo sound with echo enabled ... + if (SoundData.no_filter) + { + // ... but no filter defined. + for (J = 0; J < sample_count; J+=2) + { + int E = Echo [SoundData.echo_ptr]; + + Echo[SoundData.echo_ptr++] = (E * SoundData.echo_feedback) / 128 + EchoBuffer[J]; + Echo[SoundData.echo_ptr++] = (E * SoundData.echo_feedback) / 128 + EchoBuffer[J+1]; + + if (SoundData.echo_ptr >= SoundData.echo_buffer_size) + SoundData.echo_ptr = 0; + + l = (MixBuffer[J] * master_vol_l + E * echo_vol_l) / VOL_DIV16; + r = (MixBuffer[J+1] * master_vol_r + E * echo_vol_r) / VOL_DIV16; + + CLIP16(l); + CLIP16(r); + buffer[J] = l; + buffer[J+1] = r; + } + } + else + { + // ... with filter defined. + for (J = 0; J < sample_count; J+=2) + { + register int E = Echo [SoundData.echo_ptr]; + + Loop [(Z - 0) & 15] = E; + + + + E = E * FilterTaps [0]; + E += Loop [(Z - 2) & 15] * FilterTaps [1]; + E += Loop [(Z - 4) & 15] * FilterTaps [2]; + E += Loop [(Z - 6) & 15] * FilterTaps [3]; + E += Loop [(Z - 8) & 15] * FilterTaps [4]; + E += Loop [(Z - 10) & 15] * FilterTaps [5]; + E += Loop [(Z - 12) & 15] * FilterTaps [6]; + E += Loop [(Z - 14) & 15] * FilterTaps [7]; + E /= 128; + Z++; + + Echo[SoundData.echo_ptr++] = (E * SoundData.echo_feedback) / 128 + EchoBuffer[J]; + Echo[SoundData.echo_ptr++] = (E * SoundData.echo_feedback) / 128 + EchoBuffer[J+1]; + + if (SoundData.echo_ptr >= SoundData.echo_buffer_size) + SoundData.echo_ptr = 0; + + l = (MixBuffer[J] * master_vol_l + E * echo_vol_l) / VOL_DIV16; + r = (MixBuffer[J+1] * master_vol_r + E * echo_vol_r) / VOL_DIV16; + + CLIP16(l); + CLIP16(r); + buffer[J] = l; + buffer[J+1] = r; + } + } + } + else + { + int I; + int master_vol_l = SoundData.master_volume[0]; + int echo_vol_l = SoundData.echo_volume[0]; + + // 16-bit mono sound with echo enabled... + if (SoundData.no_filter) + { + // ... no filter defined + for (J = 0; J < sample_count; J++) + { + int E = Echo [SoundData.echo_ptr]; + + Echo[SoundData.echo_ptr++] = (E * SoundData.echo_feedback) / 128 + EchoBuffer[J]; + + if (SoundData.echo_ptr >= SoundData.echo_buffer_size) + SoundData.echo_ptr = 0; + + I = (MixBuffer[J] * master_vol_l + E * echo_vol_l) / VOL_DIV16; + CLIP16(I); + buffer[J] = I; + } + } + else + { + // ... with filter defined + for (J = 0; J < sample_count; J++) + { + register int E = Echo [SoundData.echo_ptr]; + + Loop [(Z - 0) & 7] = E; + E = E * FilterTaps [0]; + E += Loop [(Z - 1) & 7] * FilterTaps [1]; + E += Loop [(Z - 2) & 7] * FilterTaps [2]; + E += Loop [(Z - 3) & 7] * FilterTaps [3]; + E += Loop [(Z - 4) & 7] * FilterTaps [4]; + E += Loop [(Z - 5) & 7] * FilterTaps [5]; + E += Loop [(Z - 6) & 7] * FilterTaps [6]; + E += Loop [(Z - 7) & 7] * FilterTaps [7]; + E /= 128; + Z++; + + Echo[SoundData.echo_ptr++] = (E * SoundData.echo_feedback) / 128 + EchoBuffer[J]; + + if (SoundData.echo_ptr >= SoundData.echo_buffer_size) + SoundData.echo_ptr = 0; + + I = (MixBuffer[J] * master_vol_l + E * echo_vol_l) / VOL_DIV16; + CLIP16(I); + buffer[J] = I; + } + } + } + } + else + { + int l, master_vol_l = SoundData.master_volume[0]; + + if (so.stereo) + { + int r, master_vol_r = SoundData.master_volume[1]; + + // 16-bit stereo sound, no echo + for (J = 0; J < sample_count; J+=2) + { + l = (MixBuffer[J] * master_vol_l) / VOL_DIV16; + r = (MixBuffer[J+1] * master_vol_r) / VOL_DIV16; + + CLIP16(l); + CLIP16(r); + buffer[J] = l; + buffer[J+1] = r; + } + } + else + { + // 16-bit mono sound, no echo + for (J = 0; J < sample_count; J++) + { + l = (MixBuffer[J] * master_vol_l) / VOL_DIV16; + + CLIP16(l); + buffer[J] = l; + } + } + } +} + +#ifdef __DJGPP +END_OF_FUNCTION(S9xMixSamplesO); +#endif + +void S9xResetSound (bool8 full) +{ + for (int i = 0; i < 8; i++) + { + SoundData.channels[i].state = SOUND_SILENT; + SoundData.channels[i].mode = MODE_NONE; + SoundData.channels[i].type = SOUND_SAMPLE; + SoundData.channels[i].volume_left = 0; + SoundData.channels[i].volume_right = 0; + SoundData.channels[i].hertz = 0; + SoundData.channels[i].count = 0; + SoundData.channels[i].loop = FALSE; + SoundData.channels[i].envx_target = 0; + SoundData.channels[i].env_error = 0; + SoundData.channels[i].erate = 0; + SoundData.channels[i].envx = 0; + SoundData.channels[i].envxx = 0; + SoundData.channels[i].left_vol_level = 0; + SoundData.channels[i].right_vol_level = 0; + SoundData.channels[i].direction = 0; + SoundData.channels[i].attack_rate = 0; + SoundData.channels[i].decay_rate = 0; + SoundData.channels[i].sustain_rate = 0; + SoundData.channels[i].release_rate = 0; + SoundData.channels[i].sustain_level = 0; + // notaz + SoundData.channels[i].env_ind_attack = 0; + SoundData.channels[i].env_ind_decay = 0; + SoundData.channels[i].env_ind_sustain = 0; + SoundData.echo_ptr = 0; + SoundData.echo_feedback = 0; + SoundData.echo_buffer_size = 1; + } + FilterTaps [0] = 127; + FilterTaps [1] = 0; + FilterTaps [2] = 0; + FilterTaps [3] = 0; + FilterTaps [4] = 0; + FilterTaps [5] = 0; + FilterTaps [6] = 0; + FilterTaps [7] = 0; + so.mute_sound = TRUE; + so.noise_gen = 1; + + if (full) + { + SoundData.master_volume_left = 0; + SoundData.master_volume_right = 0; + SoundData.echo_volume_left = 0; + SoundData.echo_volume_right = 0; + SoundData.echo_enable = 0; + SoundData.echo_write_enabled = 0; + SoundData.echo_channel_enable = 0; + SoundData.pitch_mod = 0; + SoundData.dummy[0] = 0; + SoundData.dummy[1] = 0; + SoundData.dummy[2] = 0; + SoundData.master_volume[0] = 0; + SoundData.master_volume[1] = 0; + SoundData.echo_volume[0] = 0; + SoundData.echo_volume[1] = 0; + SoundData.noise_hertz = 0; + } + + SoundData.master_volume_left = 127; + SoundData.master_volume_right = 127; + SoundData.master_volume [0] = SoundData.master_volume [1] = 127; + SoundData.no_filter = TRUE; +} + + + +extern unsigned long AttackRate [16]; +extern unsigned long DecayRate [8]; +extern unsigned long SustainRate [32]; +extern unsigned long IncreaseRate [32]; +extern unsigned long DecreaseRateExp [32]; + + +void S9xSetPlaybackRate (uint32 playback_rate) +{ + so.playback_rate = playback_rate; + + if(playback_rate) { + // notaz: calclulate a value (let's call it freqbase) to simplify channel freq calculations later. + so.freqbase = (FIXED_POINT<<11) / playback_rate; + // now precalculate env rates for S9xSetEnvRate + static int steps [] = + { + //0, 64, 1238, 1238, 256, 1, 64, 109, 64, 1238 + 0, 64, 619, 619, 128, 1, 64, 55, 64, 619 + }; + int i, u; + for(i=0; i < 16; i++) + for(u=0; u < 10; u++) + AttackERate[i][u] = (unsigned long) (((int64) FIXED_POINT * 1000 * steps[u]) / + (AttackRate[i] * playback_rate)); + for(i=0; i < 8; i++) + for(u=0; u < 10; u++) + DecayERate[i][u] = (unsigned long) (((int64) FIXED_POINT * 1000 * steps[u]) / + (DecayRate[i] * playback_rate)); + + for(i=0; i < 32; i++) + for(u=0; u < 10; u++) + SustainERate[i][u]= (unsigned long) (((int64) FIXED_POINT * 1000 * steps[u]) / + (SustainRate[i] * playback_rate)); + + for(i=0; i < 32; i++) + for(u=0; u < 10; u++) + IncreaseERate[i][u]=(unsigned long) (((int64) FIXED_POINT * 1000 * steps[u]) / + (IncreaseRate[i] * playback_rate)); + + for(i=0; i < 32; i++) + for(u=0; u < 10; u++) + DecreaseERateExp[i][u] = (unsigned long) (((int64) FIXED_POINT * 1000 * steps[u]) / + (DecreaseRateExp[i] / 2 * playback_rate)); + + for(u=0; u < 10; u++) + KeyOffERate[u] = (unsigned long) (((int64) FIXED_POINT * 1000 * steps[u]) / + (8 * playback_rate)); + } + + S9xSetEchoDelay (APU.DSP [APU_EDL] & 0xf); + for (int i = 0; i < 8; i++) + S9xSetSoundFrequency (i, SoundData.channels [i].hertz); +} + +bool8 S9xInitSound (void) +{ + so.playback_rate = 0; + so.stereo = 0; + + S9xResetSound (TRUE); + S9xSetSoundMute (TRUE); + + return (1); +} + diff --git a/src/soundux.h b/src/soundux.h new file mode 100644 index 0000000..4b313df --- /dev/null +++ b/src/soundux.h @@ -0,0 +1,337 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _SOUND_H_ +#define _SOUND_H_ + +enum { SOUND_SAMPLE = 0, SOUND_NOISE, SOUND_EXTRA_NOISE, SOUND_MUTE }; +enum { SOUND_SILENT, SOUND_ATTACK, SOUND_DECAY, SOUND_SUSTAIN, + SOUND_RELEASE, SOUND_GAIN, SOUND_INCREASE_LINEAR, + SOUND_INCREASE_BENT_LINE, SOUND_DECREASE_LINEAR, + SOUND_DECREASE_EXPONENTIAL}; + +enum { MODE_NONE = SOUND_SILENT, MODE_ADSR, MODE_RELEASE = SOUND_RELEASE, + MODE_GAIN, MODE_INCREASE_LINEAR, MODE_INCREASE_BENT_LINE, + MODE_DECREASE_LINEAR, MODE_DECREASE_EXPONENTIAL}; + +#define MAX_ENVELOPE_HEIGHT 127 +#define ENVELOPE_SHIFT 7 +#define MAX_VOLUME 127 +#define VOLUME_SHIFT 7 +#define VOL_DIV 128 +#define SOUND_DECODE_LENGTH 16 + +#define NUM_CHANNELS 8 +#define SOUND_BUFFER_SIZE (2*44100/50) +#define MAX_BUFFER_SIZE SOUND_BUFFER_SIZE + +#define SOUND_BUFS 4 + +typedef struct { + int playback_rate; + bool8 stereo; + bool8 mute_sound; + uint8 sound_switch; + int noise_gen; + uint32 freqbase; // notaz +} SoundStatus; + +EXTERN_C SoundStatus so; + +typedef struct { + int state; // 0x00 + int type; // 0x04 + short volume_left; // 0x08 + short volume_right; // 0x0A + uint32 hertz; // 0x0C + uint32 frequency; // 0x10 + uint32 count; // 0x14 + bool32 loop; // 0x18 + int envx; // 0x1C + short left_vol_level; // 0x20 + short right_vol_level; // 0x22 + short envx_target; // 0x24 + short padding; // 0x26 + unsigned long int env_error; // 0x28 + unsigned long erate; // 0x2C + int direction; // 0x30 + unsigned long attack_rate; // 0x34 + unsigned long decay_rate; // 0x38 + unsigned long sustain_rate; // 0x3C + unsigned long release_rate; // 0x40 + unsigned long sustain_level; // 0x44 + signed short sample; // 0x48 + signed short decoded [16]; + signed short previous16 [2]; + signed short *block; + uint16 sample_number; + bool8 last_block; + bool8 needs_decode; + uint32 block_pointer; + uint32 sample_pointer; + int *echo_buf_ptr; + int mode; + int32 envxx; + signed short next_sample; + int32 interpolate; + int32 previous [2]; + // notaz + uint8 env_ind_attack; + uint8 env_ind_decay; + uint8 env_ind_sustain; + uint8 dummy1; + // Just incase they are needed in the future, for snapshot compatibility. + uint32 dummy [7]; + //I'll use Fatl's recovery on savestates. + short gaussian[8]; + int g_index; + unsigned short last_valid_header; + uint8 padding2[256-212]; // Last time I checked it, it was 212 bytes long +} Channel; + +typedef struct +{ + short master_volume_left; // 0x00 + short master_volume_right; // 0x02 + short echo_volume_left; // 0x04 + short echo_volume_right; // 0x06 + int echo_enable; // 0x08 + int echo_feedback; // 0x0C + int echo_ptr; // 0x10 + int echo_buffer_size; // 0x14 + int echo_write_enabled; // 0x18 + int echo_channel_enable; // 0x1C + int pitch_mod; // 0x20 + // Just incase they are needed in the future, for snapshot compatibility. + uint32 dummy [3]; // 0x24, 0x28, 0x2C + Channel channels [NUM_CHANNELS]; // 0x30 + bool8 no_filter; + int master_volume [2]; + int echo_volume [2]; + int noise_hertz; +} SSoundData; + +EXTERN_C SSoundData SoundData; + +void S9xSetEnvelopeHeight (int channel, int height); +void S9xSetSoundKeyOff (int channel); +void S9xSetSoundDecayMode (int channel); +void S9xSetSoundAttachMode (int channel); +void S9xSoundStartEnvelope (Channel *); +void S9xSetSoundSample (int channel, uint16 sample_number); +void S9xSetEchoDelay (int byte); +void S9xResetSound (bool8 full); +void S9xFixSoundAfterSnapshotLoad (); +void S9xPlaybackSoundSetting (int channel); +void S9xFixEnvelope (int channel, uint8 gain, uint8 adsr1, uint8 adsr2); +void S9xStartSample (int channel); + +EXTERN_C void S9xMixSamples (signed short *buffer, int sample_count); +EXTERN_C void S9xMixSamplesO(signed short *buffer, int sample_count, int sample_offset); +void S9xSetPlaybackRate (uint32 rate); +bool8 S9xInitSound (void); +#endif + + + +// notaz: some stuff from soundux.cpp to enable their inlining +#include "apu.h" +//#define DEBUG +//#include + +extern int Echo [24000]; +extern int Loop [16]; +extern int FilterTaps [8]; +extern int EchoBuffer [SOUND_BUFFER_SIZE]; +extern int NoiseFreq [32]; + +// precalculated env rates for S9xSetEnvRate +extern unsigned long AttackERate [16][10]; +extern unsigned long DecayERate [8][10]; +extern unsigned long SustainERate [32][10]; +extern unsigned long IncreaseERate [32][10]; +extern unsigned long DecreaseERateExp[32][10]; +extern unsigned long KeyOffERate[10]; + + +#define FIXED_POINT 0x10000UL +#define CLIP8(v) \ +if ((v) < -128) \ + (v) = -128; \ +else \ +if ((v) > 127) \ + (v) = 127 + +static inline void S9xSetSoundMute (bool8 mute) +{ + //bool8 old = so.mute_sound; + so.mute_sound = mute; + //return (old); +} + +static inline void S9xSetEnvRate (Channel *ch, unsigned long rate, int direction, int target, unsigned int mode) +{ + ch->envx_target = target; + + if (rate == ~0UL) + { + ch->direction = 0; + rate = 0; + } + else + ch->direction = direction; + + + if (rate == 0 || so.playback_rate == 0) + ch->erate = 0; + else + { + switch(mode >> 28) { + case 0: // attack + ch->erate = AttackERate[ch->env_ind_attack][ch->state]; + break; + + case 1: // Decay + ch->erate = DecayERate[ch->env_ind_decay][ch->state]; + break; + + case 2: // Sustain + ch->erate = SustainERate[ch->env_ind_sustain][ch->state]; + break; + + case 3: // Increase + ch->erate = IncreaseERate[mode&0x1f][ch->state]; + break; + + case 4: // DecreaseExp + ch->erate = DecreaseERateExp[mode&0x1f][ch->state]; + break; + + case 5: // KeyOff + ch->erate = KeyOffERate[ch->state]; + break; + } + } + +#if 0 + static int steps [] = + { +// 0, 64, 1238, 1238, 256, 1, 64, 109, 64, 1238 + 0, 64, 619, 619, 128, 1, 64, 55, 64, 619 + }; + + if (rate == 0 || so.playback_rate == 0) + ch->erate = 0; + else + { + ch->erate = (unsigned long) + (((int64) FIXED_POINT * 1000 * steps [ch->state]) / + (rate * so.playback_rate)); + } +#endif +} + +static inline void S9xSetEchoEnable (uint8 byte) +{ + SoundData.echo_channel_enable = byte; + if (!SoundData.echo_write_enabled || Settings.DisableSoundEcho) + byte = 0; + if (byte && !SoundData.echo_enable) + { + memset (Echo, 0, sizeof (Echo)); + memset (Loop, 0, sizeof (Loop)); + } + + SoundData.echo_enable = byte; + for (int i = 0; i < 8; i++) + { + if (byte & (1 << i)) + SoundData.channels [i].echo_buf_ptr = EchoBuffer; + else + SoundData.channels [i].echo_buf_ptr = 0; + } +} + +static inline void S9xSetEchoFeedback (int feedback) +{ + CLIP8(feedback); + SoundData.echo_feedback = feedback; +} + +static inline void S9xSetFilterCoefficient (int tap, int value) +{ + FilterTaps [tap & 7] = value; + SoundData.no_filter = (FilterTaps [0] == 127 || FilterTaps [0] == 0) && + FilterTaps [1] == 0 && + FilterTaps [2] == 0 && + FilterTaps [3] == 0 && + FilterTaps [4] == 0 && + FilterTaps [5] == 0 && + FilterTaps [6] == 0 && + FilterTaps [7] == 0; +} + +static inline uint16 *S9xGetSampleAddress (int sample_number) +{ + uint32 addr = (((APU.DSP[APU_DIR] << 8) + (sample_number << 2)) & 0xffff); + return (uint16 *)(IAPU.RAM + addr); +} + +static inline void S9xSetSoundFrequency (int channel, int hertz) // hertz [0~64K<<1] +{ + if (so.playback_rate) + { + if (SoundData.channels[channel].type == SOUND_NOISE) + hertz = NoiseFreq [APU.DSP [APU_FLG] & 0x1f]; +#if 0 // notaz: this compiles to something awful + SoundData.channels[channel].frequency = (int) + (((int64) hertz * FIXED_POINT) / so.playback_rate); +#else + SoundData.channels[channel].frequency = (hertz * so.freqbase) >> 11; +#endif + + /* if (Settings.FixFrequency) + { + SoundData.channels[channel].frequency = + (unsigned long) ((double) SoundData.channels[channel].frequency * 0.980); + }*/ + } +} + diff --git a/src/spc700.cpp b/src/spc700.cpp new file mode 100644 index 0000000..00dd4f8 --- /dev/null +++ b/src/spc700.cpp @@ -0,0 +1,2509 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +#include "snes9x.h" +#include "memmap.h" +#include "display.h" +#include "cpuexec.h" +#include "apu.h" +#include "spc700.h" + +// SPC700/Sound DSP chips have a 24.57MHz crystal on their PCB. + +// we only need the memhandlers +#undef INLINE +#define INLINE extern "C" +#include "apumem.h" + +#define OP1 (*(IAPU.PC + 1)) +#define OP2 (*(IAPU.PC + 2)) + +#ifdef SPC700_SHUTDOWN +#define APUShutdown() \ + if (Settings.Shutdown && (IAPU.PC == IAPU.WaitAddress1 || IAPU.PC == IAPU.WaitAddress2)) \ + { \ + if (IAPU.WaitCounter == 0) \ + { \ + if (!ICPU.CPUExecuting) \ + CPU.APU_Cycles = CPU.Cycles = CPU.NextEvent; \ + else \ + CPU.APU_APUExecuting = FALSE; \ + } \ + else \ + if (IAPU.WaitCounter >= 2) \ + IAPU.WaitCounter = 1; \ + else \ + IAPU.WaitCounter--; \ + } +#else +#define APUShutdown() +#endif + +#define APUSetZN8(b)\ + IAPU._Zero = (b); + +#define APUSetZN16(w)\ + IAPU._Zero = ((w) != 0) | ((w) >> 8); + +void STOP (char *s) +{ + char buffer[100]; + +#ifdef DEBUGGER + S9xAPUOPrint (buffer, IAPU.PC - IAPU.RAM); +#endif + + sprintf (String, "Sound CPU in unknown state executing %s at %04lX\n%s\n", s, IAPU.PC - IAPU.RAM, buffer); + S9xMessage (S9X_ERROR, S9X_APU_STOPPED, String); + APU.TimerEnabled[0] = APU.TimerEnabled[1] = APU.TimerEnabled[2] = FALSE; + CPU.APU_APUExecuting = FALSE; + +#ifdef DEBUGGER + CPU.Flags |= DEBUG_MODE_FLAG; +#else + S9xExit (); +#endif +} + +#define TCALL(n)\ +{\ + PushW ((IAPU.PC - IAPU.RAM + 1)); \ + IAPU.PC = IAPU.RAM + (APU.ExtraRAM [((15 - n) << 1)] + \ + (APU.ExtraRAM [((15 - n) << 1) + 1] << 8)); \ +} + +// XXX: HalfCarry - BJ fixed? +#define SBC(a,b)\ +short Int16 = (short) (a) - (short) (b) + (short) (APUCheckCarry ()) - 1;\ +IAPU._Carry = Int16 >= 0;\ +if ((((a) ^ (b)) & 0x80) && (((a) ^ (uint8) Int16) & 0x80))\ + APUSetOverflow ();\ +else \ + APUClearOverflow (); \ +APUSetHalfCarry ();\ +if(((a) ^ (b) ^ (uint8) Int16) & 0x10)\ + APUClearHalfCarry ();\ +(a) = (uint8) Int16;\ +APUSetZN8 ((uint8) Int16); + +// XXX: HalfCarry - BJ fixed? +#define ADC(a,b)\ +uint16 Work16 = (a) + (b) + APUCheckCarry();\ +IAPU._Carry = Work16 >= 0x100; \ +if (~((a) ^ (b)) & ((b) ^ (uint8) Work16) & 0x80)\ + APUSetOverflow ();\ +else \ + APUClearOverflow (); \ +APUClearHalfCarry ();\ +/*if(((a) ^ (b) ^ (uint8) Int16) & 0x10) notaz: Int16!? */\ +if(((a) ^ (b) ^ (uint8) Work16) & 0x10)\ + APUSetHalfCarry ();\ +(a) = (uint8) Work16;\ +APUSetZN8 ((uint8) Work16); + +#define CMP(a,b)\ +short Int16 = (short) (a) - (short) (b);\ +IAPU._Carry = Int16 >= 0;\ +APUSetZN8 ((uint8) Int16); + +#define ASL(b)\ + IAPU._Carry = ((b) & 0x80) != 0; \ + (b) <<= 1;\ + APUSetZN8 (b); +#define LSR(b)\ + IAPU._Carry = (b) & 1;\ + (b) >>= 1;\ + APUSetZN8 (b); +#define ROL(b)\ + uint16 Work16 = ((b) << 1) | APUCheckCarry (); \ + IAPU._Carry = Work16 >= 0x100; \ + (b) = (uint8) Work16; \ + APUSetZN8 (b); +#define ROR(b)\ + uint16 Work16 = (b) | ((uint16) APUCheckCarry () << 8); \ + IAPU._Carry = (uint8) Work16 & 1; \ + Work16 >>= 1; \ + (b) = (uint8) Work16; \ + APUSetZN8 (b); + +#define Push(b)\ + *(IAPU.RAM + 0x100 + IAPU.S) = b;\ + IAPU.S--; + +#define Pop(b)\ + IAPU.S++;\ + (b) = *(IAPU.RAM + 0x100 + IAPU.S); + +#ifdef FAST_LSB_WORD_ACCESS +#define PushW(w)\ + *(uint16 *) (IAPU.RAM + 0xff + IAPU.S) = w;\ + IAPU.S -= 2; +#define PopW(w)\ + IAPU.S += 2;\ + w = *(uint16 *) (IAPU.RAM + 0xff + IAPU.S); +#else +#define PushW(w)\ + *(IAPU.RAM + 0xff + IAPU.S) = w;\ + *(IAPU.RAM + 0x100 + IAPU.S) = (w >> 8);\ + IAPU.S -= 2; +#define PopW(w)\ + IAPU.S += 2; \ + (w) = *(IAPU.RAM + 0xff + IAPU.S) + (*(IAPU.RAM + 0x100 + IAPU.S) << 8); +#endif + +#define Relative()\ + signed char Int8 = OP1;\ + short Int16 = (int) (IAPU.PC + 2 - IAPU.RAM) + Int8; + +#define Relative2()\ + signed char Int8 = OP2;\ + short Int16 = (int) (IAPU.PC + 3 - IAPU.RAM) + Int8; + +#ifdef FAST_LSB_WORD_ACCESS +#define IndexedXIndirect()\ + IAPU.Address = *(uint16 *) (IAPU.DirectPage + ((OP1 + IAPU.X) & 0xff)); + +#define Absolute()\ + IAPU.Address = *(uint16 *) (IAPU.PC + 1); + +#define AbsoluteX()\ + IAPU.Address = *(uint16 *) (IAPU.PC + 1) + IAPU.X; + +#define AbsoluteY()\ + IAPU.Address = *(uint16 *) (IAPU.PC + 1) + IAPU.YA.B.Y; + +#define MemBit()\ + IAPU.Address = *(uint16 *) (IAPU.PC + 1);\ + IAPU.Bit = (uint8)(IAPU.Address >> 13);\ + IAPU.Address &= 0x1fff; + +#define IndirectIndexedY()\ + IAPU.Address = *(uint16 *) (IAPU.DirectPage + OP1) + IAPU.YA.B.Y; +#else +#define IndexedXIndirect()\ + IAPU.Address = *(IAPU.DirectPage + ((OP1 + IAPU.X) & 0xff)) + \ + (*(IAPU.DirectPage + ((OP1 + IAPU.X + 1) & 0xff)) << 8); +#define Absolute()\ + IAPU.Address = OP1 + (OP2 << 8); + +#define AbsoluteX()\ + IAPU.Address = OP1 + (OP2 << 8) + IAPU.X; + +#define AbsoluteY()\ + IAPU.Address = OP1 + (OP2 << 8) + IAPU.YA.B.Y; + +#define MemBit()\ + IAPU.Address = OP1 + (OP2 << 8);\ + IAPU.Bit = (int8) (IAPU.Address >> 13);\ + IAPU.Address &= 0x1fff; + +#define IndirectIndexedY()\ + IAPU.Address = *(IAPU.DirectPage + OP1) + \ + (*(IAPU.DirectPage + OP1 + 1) << 8) + \ + IAPU.YA.B.Y; + +void Apu00 () +{ +// NOP + IAPU.PC++; +} + +void Apu01 () { TCALL (0) } + +void Apu11 () { TCALL (1) } + +void Apu21 () { TCALL (2) } + +void Apu31 () { TCALL (3) } + +void Apu41 () { TCALL (4) } + +void Apu51 () { TCALL (5) } + +void Apu61 () { TCALL (6) } + +void Apu71 () { TCALL (7) } + +void Apu81 () { TCALL (8) } + +void Apu91 () { TCALL (9) } + +void ApuA1 () { TCALL (10) } + +void ApuB1 () { TCALL (11) } + +void ApuC1 () { TCALL (12) } + +void ApuD1 () { TCALL (13) } + +void ApuE1 () { TCALL (14) } + +void ApuF1 () { TCALL (15) } + +void Apu3F () // CALL absolute +{ + Absolute (); + // 0xB6f for Star Fox 2 + PushW ((IAPU.PC + 3 - IAPU.RAM)); + IAPU.PC = IAPU.RAM + IAPU.Address; +} + +void Apu4F () // PCALL $XX +{ + uint8 Work8 = OP1; + PushW ((IAPU.PC + 2 - IAPU.RAM)); + IAPU.PC = IAPU.RAM + 0xff00 + Work8; +} + +#define SET(b) \ +S9xAPUSetByteZ ((uint8) (S9xAPUGetByteZ (OP1 ) | (1 << (b))), OP1); \ +IAPU.PC += 2 + +void Apu02 () +{ + SET (0); +} + +void Apu22 () +{ + SET (1); +} + +void Apu42 () +{ + SET (2); +} + +void Apu62 () +{ + SET (3); +} + + + +void Apu82 () +{ + + + SET (4); +} + +void ApuA2 () +{ + SET (5); +} + +void ApuC2 () +{ + SET (6); +} + +void ApuE2 () +{ + SET (7); +} + +#define CLR(b) \ +S9xAPUSetByteZ ((uint8) (S9xAPUGetByteZ (OP1) & ~(1 << (b))), OP1); \ +IAPU.PC += 2; + +void Apu12 () +{ + CLR (0); +} + +void Apu32 () +{ + CLR (1); +} + +void Apu52 () +{ + CLR (2); +} + +void Apu72 () +{ + CLR (3); +} + +void Apu92 () +{ + CLR (4); +} + +void ApuB2 () +{ + CLR (5); +} + +void ApuD2 () +{ + CLR (6); +} + +void ApuF2 () +{ + CLR (7); +} + +#define BBS(b) \ +uint8 Work8 = OP1; \ +Relative2 (); \ +if (S9xAPUGetByteZ (Work8) & (1 << (b))) \ +{ \ + IAPU.PC = IAPU.RAM + (uint16) Int16; \ + CPU.APU_Cycles += IAPU.TwoCycles; \ +} \ +else \ + IAPU.PC += 3 + +void Apu03 () +{ + BBS (0); +} + +void Apu23 () +{ + BBS (1); +} + +void Apu43 () +{ + BBS (2); +} + +void Apu63 () +{ + BBS (3); +} + +void Apu83 () +{ + BBS (4); +} + +void ApuA3 () +{ + BBS (5); +} + +void ApuC3 () +{ + BBS (6); +} + +void ApuE3 () +{ + BBS (7); +} + +#define BBC(b) \ +uint8 Work8 = OP1; \ +Relative2 (); \ +if (!(S9xAPUGetByteZ (Work8) & (1 << (b)))) \ +{ \ + IAPU.PC = IAPU.RAM + (uint16) Int16; \ + CPU.APU_Cycles += IAPU.TwoCycles; \ +} \ +else \ + IAPU.PC += 3 + +void Apu13 () +{ + BBC (0); +} + +void Apu33 () +{ + BBC (1); +} + +void Apu53 () +{ + BBC (2); +} + +void Apu73 () +{ + BBC (3); +} + +void Apu93 () +{ + BBC (4); +} + +void ApuB3 () +{ + BBC (5); +} + +void ApuD3 () +{ + BBC (6); +} + +void ApuF3 () +{ + BBC (7); +} + +void Apu04 () +{ +// OR A,dp + IAPU.YA.B.A |= S9xAPUGetByteZ (OP1); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu05 () +{ +// OR A,abs + Absolute (); + IAPU.YA.B.A |= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void Apu06 () +{ +// OR A,(X) + IAPU.YA.B.A |= S9xAPUGetByteZ (IAPU.X); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu07 () +{ +// OR A,(dp+X) + IndexedXIndirect (); + IAPU.YA.B.A |= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu08 () +{ +// OR A,#00 + IAPU.YA.B.A |= OP1; + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu09 () +{ +// OR dp(dest),dp(src) + uint8 Work8 = S9xAPUGetByteZ (OP1); + Work8 |= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + IAPU.PC += 3; +} + +void Apu14 () +{ +// OR A,dp+X + IAPU.YA.B.A |= S9xAPUGetByteZ (OP1 + IAPU.X); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu15 () +{ +// OR A,abs+X + AbsoluteX (); + IAPU.YA.B.A |= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void Apu16 () +{ +// OR A,abs+Y + AbsoluteY (); + IAPU.YA.B.A |= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void Apu17 () +{ +// OR A,(dp)+Y + IndirectIndexedY (); + IAPU.YA.B.A |= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu18 () +{ +// OR dp,#00 + uint8 Work8 = OP1; + Work8 |= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + IAPU.PC += 3; +} + +void Apu19 () +{ +// OR (X),(Y) + uint8 Work8 = S9xAPUGetByteZ (IAPU.X) | S9xAPUGetByteZ (IAPU.YA.B.Y); + APUSetZN8 (Work8); + S9xAPUSetByteZ (Work8, IAPU.X); + IAPU.PC++; +} + +void Apu0A () +{ +// OR1 C,membit + MemBit (); + if (!APUCheckCarry ()) + { + if (S9xAPUGetByte (IAPU.Address) & (1 << IAPU.Bit)) + APUSetCarry (); + } + IAPU.PC += 3; +} + +void Apu2A () +{ +// OR1 C,not membit + MemBit (); + if (!APUCheckCarry ()) + { + if (!(S9xAPUGetByte (IAPU.Address) & (1 << IAPU.Bit))) + APUSetCarry (); + } + IAPU.PC += 3; +} + +void Apu4A () +{ +// AND1 C,membit + MemBit (); + if (APUCheckCarry ()) + { + if (!(S9xAPUGetByte (IAPU.Address) & (1 << IAPU.Bit))) + APUClearCarry (); + } + IAPU.PC += 3; +} + +void Apu6A () +{ +// AND1 C, not membit + MemBit (); + if (APUCheckCarry ()) + { + if ((S9xAPUGetByte (IAPU.Address) & (1 << IAPU.Bit))) + APUClearCarry (); + } + IAPU.PC += 3; +} + +void Apu8A () +{ +// EOR1 C, membit + MemBit (); + if (APUCheckCarry ()) + { + if (S9xAPUGetByte (IAPU.Address) & (1 << IAPU.Bit)) + APUClearCarry (); + } + else + { + if (S9xAPUGetByte (IAPU.Address) & (1 << IAPU.Bit)) + APUSetCarry (); + } + IAPU.PC += 3; +} + +void ApuAA () +{ +// MOV1 C,membit + MemBit (); + if (S9xAPUGetByte (IAPU.Address) & (1 << IAPU.Bit)) + APUSetCarry (); + else + APUClearCarry (); + IAPU.PC += 3; +} + +void ApuCA () +{ +// MOV1 membit,C + MemBit (); + if (APUCheckCarry ()) + { + S9xAPUSetByte (S9xAPUGetByte (IAPU.Address) | (1 << IAPU.Bit), IAPU.Address); + } + else + { + S9xAPUSetByte (S9xAPUGetByte (IAPU.Address) & ~(1 << IAPU.Bit), IAPU.Address); + } + IAPU.PC += 3; +} + +void ApuEA () +{ +// NOT1 membit + MemBit (); + S9xAPUSetByte (S9xAPUGetByte (IAPU.Address) ^ (1 << IAPU.Bit), IAPU.Address); + IAPU.PC += 3; +} + +void Apu0B () +{ +// ASL dp + uint8 Work8 = S9xAPUGetByteZ (OP1); + ASL (Work8); + S9xAPUSetByteZ (Work8, OP1); + IAPU.PC += 2; +} + +void Apu0C () +{ +// ASL abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (IAPU.Address); + ASL (Work8); + S9xAPUSetByte (Work8, IAPU.Address); + IAPU.PC += 3; +} + +void Apu1B () +{ +// ASL dp+X + uint8 Work8 = S9xAPUGetByteZ (OP1 + IAPU.X); + ASL (Work8); + S9xAPUSetByteZ (Work8, OP1 + IAPU.X); + IAPU.PC += 2; +} + +void Apu1C () +{ +// ASL A + ASL (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu0D () +{ +// PUSH PSW + S9xAPUPackStatus (); + Push (IAPU.P); + IAPU.PC++; +} + +void Apu2D () +{ +// PUSH A + Push (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu4D () +{ +// PUSH X + Push (IAPU.X); + IAPU.PC++; +} + +void Apu6D () +{ +// PUSH Y + Push (IAPU.YA.B.Y); + IAPU.PC++; +} + +void Apu8E () +{ +// POP PSW + Pop (IAPU.P); + S9xAPUUnpackStatus (); + if (APUCheckDirectPage ()) + IAPU.DirectPage = IAPU.RAM + 0x100; + else + IAPU.DirectPage = IAPU.RAM; + IAPU.PC++; +} + +void ApuAE () +{ +// POP A + Pop (IAPU.YA.B.A); + IAPU.PC++; +} + +void ApuCE () +{ +// POP X + Pop (IAPU.X); + IAPU.PC++; +} + +void ApuEE () +{ +// POP Y + Pop (IAPU.YA.B.Y); + IAPU.PC++; +} + +void Apu0E () +{ +// TSET1 abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (IAPU.Address); + S9xAPUSetByte (Work8 | IAPU.YA.B.A, IAPU.Address); + Work8 &= IAPU.YA.B.A; + APUSetZN8 (Work8); + IAPU.PC += 3; +} + +void Apu4E () +{ +// TCLR1 abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (IAPU.Address); + S9xAPUSetByte (Work8 & ~IAPU.YA.B.A, IAPU.Address); + Work8 &= IAPU.YA.B.A; + APUSetZN8 (Work8); + IAPU.PC += 3; +} + +void Apu0F () +{ +// BRK + +#if 0 + STOP ("BRK"); +#else + PushW ((IAPU.PC + 1 - IAPU.RAM)); + S9xAPUPackStatus (); + Push (IAPU.P); + APUSetBreak (); + APUClearInterrupt (); +// XXX:Where is the BRK vector ??? + IAPU.PC = IAPU.RAM + APU.ExtraRAM[0x20] + (APU.ExtraRAM[0x21] << 8); +#endif +} + +void ApuEF () +{ +// SLEEP + // XXX: sleep + // STOP ("SLEEP"); + CPU.APU_APUExecuting = FALSE; + IAPU.PC++; +} + +void ApuFF () +{ +// STOP + // STOP ("STOP"); + CPU.APU_APUExecuting = FALSE; + IAPU.PC++; +} + +void Apu10 () +{ +// BPL + Relative (); + if (!APUCheckNegative ()) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + APUShutdown (); + } + else + IAPU.PC += 2; +} + +void Apu30 () +{ +// BMI + Relative (); + if (APUCheckNegative ()) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + APUShutdown (); + } + else + IAPU.PC += 2; +} + +void Apu90 () +{ +// BCC + Relative (); + if (!APUCheckCarry ()) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + APUShutdown (); + } + else + IAPU.PC += 2; +} + +void ApuB0 () +{ +// BCS + Relative (); + if (APUCheckCarry ()) + { + + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + APUShutdown (); + } + else + IAPU.PC += 2; +} + +void ApuD0 () +{ +// BNE + Relative (); + if (!APUCheckZero ()) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + APUShutdown (); + } + else + IAPU.PC += 2; +} + +void ApuF0 () +{ +// BEQ + Relative (); + if (APUCheckZero ()) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + APUShutdown (); + } + else + IAPU.PC += 2; +} + +void Apu50 () +{ +// BVC + Relative (); + if (!APUCheckOverflow ()) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + } + else + IAPU.PC += 2; +} + +void Apu70 () +{ +// BVS + Relative (); + if (APUCheckOverflow ()) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + } + else + IAPU.PC += 2; +} + +void Apu2F () +{ +// BRA + Relative (); + IAPU.PC = IAPU.RAM + (uint16) Int16; +} + +void Apu80 () +{ +// SETC + APUSetCarry (); + IAPU.PC++; +} + +void ApuED () +{ +// NOTC + IAPU._Carry ^= 1; + IAPU.PC++; +} + +void Apu40 () +{ +// SETP + APUSetDirectPage (); + IAPU.DirectPage = IAPU.RAM + 0x100; + IAPU.PC++; +} + +void Apu1A () +{ +// DECW dp + uint16 Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + Work16--; + S9xAPUSetByteZ ((uint8) Work16, OP1); + S9xAPUSetByteZ (Work16 >> 8, OP1 + 1); + APUSetZN16 (Work16); + IAPU.PC += 2; +} + +void Apu5A () +{ +// CMPW YA,dp + uint16 Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + long Int32 = (long) IAPU.YA.W - (long) Work16; + IAPU._Carry = Int32 >= 0; + APUSetZN16 ((uint16) Int32); + IAPU.PC += 2; +} + +void Apu3A () +{ +// INCW dp + uint16 Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + Work16++; + S9xAPUSetByteZ ((uint8) Work16, OP1); + S9xAPUSetByteZ (Work16 >> 8, OP1 + 1); + APUSetZN16 (Work16); + IAPU.PC += 2; +} + +// XXX: HalfCarry - BJ Fixed? Or is it between bits 7 and 8 for ADDW/SUBW? +void Apu7A () +{ +// ADDW YA,dp + uint16 Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + uint32 Work32 = (uint32) IAPU.YA.W + Work16; + IAPU._Carry = Work32 >= 0x10000; + if (~(IAPU.YA.W ^ Work16) & (Work16 ^ (uint16) Work32) & 0x8000) + APUSetOverflow (); + else + APUClearOverflow (); + APUClearHalfCarry (); + if((IAPU.YA.W ^ Work16 ^ (uint16) Work32) & 0x10) + APUSetHalfCarry (); + IAPU.YA.W = (uint16) Work32; + APUSetZN16 (IAPU.YA.W); + IAPU.PC += 2; +} + +// XXX: BJ: i think the old HalfCarry behavior was wrong... +// XXX: Or is it between bits 7 and 8 for ADDW/SUBW? +void Apu9A () +{ +// SUBW YA,dp + uint16 Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + long Int32 = (long) IAPU.YA.W - (long) Work16; + APUClearHalfCarry (); + IAPU._Carry = Int32 >= 0; + if (((IAPU.YA.W ^ Work16) & 0x8000) && + ((IAPU.YA.W ^ (uint16) Int32) & 0x8000)) + APUSetOverflow (); + else + APUClearOverflow (); +// if (((IAPU.YA.W ^ Work16) & 0x0080) && +// ((IAPU.YA.W ^ (uint16) Int32) & 0x0080)) +// APUSetHalfCarry (); // notaz: strange here + APUSetHalfCarry (); +// if((IAPU.YA.W ^ Work16 ^ (uint16) Work32) & 0x10) // notaz: Work32?! + if((IAPU.YA.W ^ Work16 ^ (uint16) Int32) & 0x10) + APUClearHalfCarry (); + IAPU.YA.W = (uint16) Int32; + APUSetZN16 (IAPU.YA.W); + IAPU.PC += 2; +} + +void ApuBA () +{ +// MOVW YA,dp + IAPU.YA.B.A = S9xAPUGetByteZ (OP1); + IAPU.YA.B.Y = S9xAPUGetByteZ (OP1 + 1); + APUSetZN16 (IAPU.YA.W); + IAPU.PC += 2; +} + +void ApuDA () +{ +// MOVW dp,YA + S9xAPUSetByteZ (IAPU.YA.B.A, OP1); + S9xAPUSetByteZ (IAPU.YA.B.Y, OP1 + 1); + IAPU.PC += 2; +} + +void Apu64 () +{ +// CMP A,dp + uint8 Work8 = S9xAPUGetByteZ (OP1); + CMP (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu65 () +{ +// CMP A,abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (IAPU.Address); + CMP (IAPU.YA.B.A, Work8); + IAPU.PC += 3; +} + +void Apu66 () +{ +// CMP A,(X) + uint8 Work8 = S9xAPUGetByteZ (IAPU.X); + CMP (IAPU.YA.B.A, Work8); + IAPU.PC++; +} + +void Apu67 () +{ +// CMP A,(dp+X) + IndexedXIndirect (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + CMP (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu68 () +{ +// CMP A,#00 + uint8 Work8 = OP1; + CMP (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu69 () +{ +// CMP dp(dest), dp(src) + uint8 W1 = S9xAPUGetByteZ (OP1); + uint8 Work8 = S9xAPUGetByteZ (OP2); + CMP (Work8, W1); + IAPU.PC += 3; +} + +void Apu74 () +{ +// CMP A, dp+X + uint8 Work8 = S9xAPUGetByteZ (OP1 + IAPU.X); + CMP (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu75 () +{ +// CMP A,abs+X + AbsoluteX (); + uint8 Work8 = S9xAPUGetByte (IAPU.Address); + CMP (IAPU.YA.B.A, Work8); + IAPU.PC += 3; +} + +void Apu76 () +{ +// CMP A, abs+Y + AbsoluteY (); + uint8 Work8 = S9xAPUGetByte (IAPU.Address); + CMP (IAPU.YA.B.A, Work8); + IAPU.PC += 3; +} + +void Apu77 () +{ +// CMP A,(dp)+Y + IndirectIndexedY (); + uint8 Work8 = S9xAPUGetByte (IAPU.Address); + CMP (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu78 () +{ +// CMP dp,#00 + uint8 Work8 = OP1; + uint8 W1 = S9xAPUGetByteZ (OP2); + CMP (W1, Work8); + IAPU.PC += 3; +} + +void Apu79 () +{ +// CMP (X),(Y) + uint8 W1 = S9xAPUGetByteZ (IAPU.X); + uint8 Work8 = S9xAPUGetByteZ (IAPU.YA.B.Y); + CMP (W1, Work8); + IAPU.PC++; +} + +void Apu1E () +{ +// CMP X,abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (IAPU.Address); + CMP (IAPU.X, Work8); + IAPU.PC += 3; +} + +void Apu3E () +{ +// CMP X,dp + uint8 Work8 = S9xAPUGetByteZ (OP1); + CMP (IAPU.X, Work8); + IAPU.PC += 2; +} + +void ApuC8 () +{ +// CMP X,#00 + CMP (IAPU.X, OP1); + IAPU.PC += 2; +} + +void Apu5E () +{ +// CMP Y,abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + CMP (IAPU.YA.B.Y, Work8); + IAPU.PC += 3; +} + +void Apu7E () +{ +// CMP Y,dp + uint8 Work8 = S9xAPUGetByteZ (OP1); + CMP (IAPU.YA.B.Y, Work8); + IAPU.PC += 2; +} + +void ApuAD () +{ +// CMP Y,#00 + uint8 Work8 = OP1; + CMP (IAPU.YA.B.Y, Work8); + IAPU.PC += 2; +} + +void Apu1F () +{ +// JMP (abs+X) + Absolute (); + IAPU.PC = IAPU.RAM + S9xAPUGetByte (IAPU.Address + IAPU.X) + + (S9xAPUGetByte (IAPU.Address + IAPU.X + 1) << 8); +// XXX: HERE: + // APU.Flags |= TRACE_FLAG; +} + +void Apu5F () +{ +// JMP abs + Absolute (); + IAPU.PC = IAPU.RAM + IAPU.Address; +} + +void Apu20 () +{ +// CLRP + APUClearDirectPage (); + IAPU.DirectPage = IAPU.RAM; + IAPU.PC++; +} + +void Apu60 () +{ +// CLRC + APUClearCarry (); + IAPU.PC++; +} + +void ApuE0 () +{ +// CLRV + APUClearHalfCarry (); + APUClearOverflow (); + IAPU.PC++; +} + +void Apu24 () +{ +// AND A,dp + IAPU.YA.B.A &= S9xAPUGetByteZ (OP1); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu25 () +{ +// AND A,abs + Absolute (); + IAPU.YA.B.A &= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void Apu26 () +{ +// AND A,(X) + IAPU.YA.B.A &= S9xAPUGetByteZ (IAPU.X); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu27 () +{ +// AND A,(dp+X) + IndexedXIndirect (); + IAPU.YA.B.A &= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu28 () +{ +// AND A,#00 + IAPU.YA.B.A &= OP1; + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu29 () +{ +// AND dp(dest),dp(src) + uint8 Work8 = S9xAPUGetByteZ (OP1); + Work8 &= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + IAPU.PC += 3; +} + +void Apu34 () +{ +// AND A,dp+X + IAPU.YA.B.A &= S9xAPUGetByteZ (OP1 + IAPU.X); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu35 () +{ +// AND A,abs+X + AbsoluteX (); + IAPU.YA.B.A &= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void Apu36 () +{ +// AND A,abs+Y + AbsoluteY (); + IAPU.YA.B.A &= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void Apu37 () +{ +// AND A,(dp)+Y + IndirectIndexedY (); + IAPU.YA.B.A &= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu38 () +{ +// AND dp,#00 + uint8 Work8 = OP1; + Work8 &= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + IAPU.PC += 3; +} + +void Apu39 () +{ +// AND (X),(Y) + uint8 Work8 = S9xAPUGetByteZ (IAPU.X) & S9xAPUGetByteZ (IAPU.YA.B.Y); + APUSetZN8 (Work8); + S9xAPUSetByteZ (Work8, IAPU.X); + IAPU.PC++; +} + +void Apu2B () +{ +// ROL dp + uint8 Work8 = S9xAPUGetByteZ (OP1); + ROL (Work8); + S9xAPUSetByteZ (Work8, OP1); + IAPU.PC += 2; +} + +void Apu2C () +{ +// ROL abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + ROL (Work8); + S9xAPUSetByte (Work8, IAPU.Address); + IAPU.PC += 3; +} + +void Apu3B () +{ +// ROL dp+X + uint8 Work8 = S9xAPUGetByteZ (OP1 + IAPU.X); + ROL (Work8); + S9xAPUSetByteZ (Work8, OP1 + IAPU.X); + IAPU.PC += 2; +} + +void Apu3C () +{ +// ROL A + ROL (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu2E () +{ +// CBNE dp,rel + uint8 Work8 = OP1; + Relative2 (); + + if (S9xAPUGetByteZ (Work8) != IAPU.YA.B.A) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + APUShutdown (); + } + else + IAPU.PC += 3; +} + +void ApuDE () +{ +// CBNE dp+X,rel + uint8 Work8 = OP1 + IAPU.X; + Relative2 (); + + if (S9xAPUGetByteZ (Work8) != IAPU.YA.B.A) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + APUShutdown (); + } + else + IAPU.PC += 3; +} + +void Apu3D () +{ +// INC X + IAPU.X++; + APUSetZN8 (IAPU.X); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC++; +} + +void ApuFC () +{ +// INC Y + IAPU.YA.B.Y++; + APUSetZN8 (IAPU.YA.B.Y); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC++; +} + +void Apu1D () +{ +// DEC X + IAPU.X--; + APUSetZN8 (IAPU.X); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC++; +} + +void ApuDC () +{ +// DEC Y + IAPU.YA.B.Y--; + APUSetZN8 (IAPU.YA.B.Y); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC++; +} + +void ApuAB () +{ +// INC dp + uint8 Work8 = S9xAPUGetByteZ (OP1) + 1; + S9xAPUSetByteZ (Work8, OP1); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC += 2; +} + +void ApuAC () +{ +// INC abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (IAPU.Address) + 1; + S9xAPUSetByte (Work8, IAPU.Address); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC += 3; +} + +void ApuBB () +{ +// INC dp+X + uint8 Work8 = S9xAPUGetByteZ (OP1 + IAPU.X) + 1; + S9xAPUSetByteZ (Work8, OP1 + IAPU.X); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC += 2; +} + +void ApuBC () +{ +// INC A + IAPU.YA.B.A++; + APUSetZN8 (IAPU.YA.B.A); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC++; +} + +void Apu8B () +{ +// DEC dp + uint8 Work8 = S9xAPUGetByteZ (OP1) - 1; + S9xAPUSetByteZ (Work8, OP1); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC += 2; +} + +void Apu8C () +{ +// DEC abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))) - 1; + S9xAPUSetByte (Work8, IAPU.Address); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC += 3; +} + +void Apu9B () +{ +// DEC dp+X + uint8 Work8 = S9xAPUGetByteZ (OP1 + IAPU.X) - 1; + S9xAPUSetByteZ (Work8, OP1 + IAPU.X); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC += 2; +} + +void Apu9C () +{ +// DEC A + IAPU.YA.B.A--; + APUSetZN8 (IAPU.YA.B.A); + +#ifdef SPC700_SHUTDOWN + IAPU.WaitCounter++; +#endif + + IAPU.PC++; +} + +void Apu44 () +{ +// EOR A,dp + IAPU.YA.B.A ^= S9xAPUGetByteZ (OP1); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu45 () +{ +// EOR A,abs + Absolute (); + IAPU.YA.B.A ^= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void Apu46 () +{ +// EOR A,(X) + IAPU.YA.B.A ^= S9xAPUGetByteZ (IAPU.X); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu47 () +{ +// EOR A,(dp+X) + IndexedXIndirect (); + IAPU.YA.B.A ^= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu48 () +{ +// EOR A,#00 + IAPU.YA.B.A ^= OP1; + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu49 () +{ +// EOR dp(dest),dp(src) + uint8 Work8 = S9xAPUGetByteZ (OP1); + Work8 ^= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + IAPU.PC += 3; +} + +void Apu54 () +{ +// EOR A,dp+X + IAPU.YA.B.A ^= S9xAPUGetByteZ (OP1 + IAPU.X); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu55 () +{ +// EOR A,abs+X + AbsoluteX (); + IAPU.YA.B.A ^= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void Apu56 () +{ +// EOR A,abs+Y + AbsoluteY (); + IAPU.YA.B.A ^= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void Apu57 () +{ +// EOR A,(dp)+Y + IndirectIndexedY (); + IAPU.YA.B.A ^= S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void Apu58 () +{ +// EOR dp,#00 + uint8 Work8 = OP1; + Work8 ^= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + IAPU.PC += 3; +} + +void Apu59 () +{ +// EOR (X),(Y) + uint8 Work8 = S9xAPUGetByteZ (IAPU.X) ^ S9xAPUGetByteZ (IAPU.YA.B.Y); + APUSetZN8 (Work8); + S9xAPUSetByteZ (Work8, IAPU.X); + IAPU.PC++; +} + +void Apu4B () +{ +// LSR dp + uint8 Work8 = S9xAPUGetByteZ (OP1); + LSR (Work8); + S9xAPUSetByteZ (Work8, OP1); + IAPU.PC += 2; +} + +void Apu4C () +{ +// LSR abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + LSR (Work8); + S9xAPUSetByte (Work8, IAPU.Address); + IAPU.PC += 3; +} + +void Apu5B () +{ +// LSR dp+X + uint8 Work8 = S9xAPUGetByteZ (OP1 + IAPU.X); + LSR (Work8); + S9xAPUSetByteZ (Work8, OP1 + IAPU.X); + IAPU.PC += 2; +} + +void Apu5C () +{ +// LSR A + LSR (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu7D () +{ +// MOV A,X + IAPU.YA.B.A = IAPU.X; + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void ApuDD () +{ +// MOV A,Y + IAPU.YA.B.A = IAPU.YA.B.Y; + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu5D () +{ +// MOV X,A + IAPU.X = IAPU.YA.B.A; + APUSetZN8 (IAPU.X); + IAPU.PC++; +} + +void ApuFD () +{ +// MOV Y,A + IAPU.YA.B.Y = IAPU.YA.B.A; + APUSetZN8 (IAPU.YA.B.Y); + IAPU.PC++; +} + +void Apu9D () +{ +//MOV X,SP + IAPU.X = IAPU.S; + APUSetZN8 (IAPU.X); + IAPU.PC++; +} + +void ApuBD () +{ +// MOV SP,X + IAPU.S = IAPU.X; + IAPU.PC++; +} + +void Apu6B () +{ +// ROR dp + uint8 Work8 = S9xAPUGetByteZ (OP1); + ROR (Work8); + S9xAPUSetByteZ (Work8, OP1); + IAPU.PC += 2; +} + +void Apu6C () +{ +// ROR abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + ROR (Work8); + S9xAPUSetByte (Work8, IAPU.Address); + IAPU.PC += 3; +} + +void Apu7B () +{ +// ROR dp+X + uint8 Work8 = S9xAPUGetByteZ (OP1 + IAPU.X); + ROR (Work8); + S9xAPUSetByteZ (Work8, OP1 + IAPU.X); + IAPU.PC += 2; +} + +void Apu7C () +{ +// ROR A + ROR (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu6E () +{ +// DBNZ dp,rel + uint8 Work8 = OP1; + Relative2 (); + uint8 W1 = S9xAPUGetByteZ (Work8) - 1; + S9xAPUSetByteZ (W1, Work8); + if (W1 != 0) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + } + else + IAPU.PC += 3; +} + +void ApuFE () +{ +// DBNZ Y,rel + Relative (); + IAPU.YA.B.Y--; + if (IAPU.YA.B.Y != 0) + { + IAPU.PC = IAPU.RAM + (uint16) Int16; + CPU.APU_Cycles += IAPU.TwoCycles; + } + else + IAPU.PC += 2; +} + +void Apu6F () +{ +// RET + uint16 Work16; + PopW (Work16); + IAPU.PC = IAPU.RAM + Work16; +} + +void Apu7F () +{ +// RETI + // STOP ("RETI"); + uint16 Work16; + Pop (IAPU.P); + S9xAPUUnpackStatus (); + PopW (Work16); + IAPU.PC = IAPU.RAM + Work16; +} + +void Apu84 () +{ +// ADC A,dp + uint8 Work8 = S9xAPUGetByteZ (OP1); + ADC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu85 () +{ +// ADC A, abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + ADC (IAPU.YA.B.A, Work8); + IAPU.PC += 3; +} + +void Apu86 () +{ +// ADC A,(X) + uint8 Work8 = S9xAPUGetByteZ (IAPU.X); + ADC (IAPU.YA.B.A, Work8); + IAPU.PC++; +} + +void Apu87 () +{ +// ADC A,(dp+X) + IndexedXIndirect (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + ADC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu88 () +{ +// ADC A,#00 + uint8 Work8 = OP1; + ADC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu89 () +{ +// ADC dp(dest),dp(src) + uint8 Work8 = S9xAPUGetByteZ (OP1); + uint8 W1 = S9xAPUGetByteZ (OP2); + ADC (W1, Work8); + S9xAPUSetByteZ (W1, OP2); + IAPU.PC += 3; +} + +void Apu94 () +{ +// ADC A,dp+X + uint8 Work8 = S9xAPUGetByteZ (OP1 + IAPU.X); + ADC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu95 () +{ +// ADC A, abs+X + AbsoluteX (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + ADC (IAPU.YA.B.A, Work8); + IAPU.PC += 3; +} + +void Apu96 () +{ +// ADC A, abs+Y + AbsoluteY (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + ADC (IAPU.YA.B.A, Work8); + IAPU.PC += 3; +} + +void Apu97 () +{ +// ADC A, (dp)+Y + IndirectIndexedY (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + ADC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void Apu98 () +{ +// ADC dp,#00 + uint8 Work8 = OP1; + uint8 W1 = S9xAPUGetByteZ (OP2); + ADC (W1, Work8); + S9xAPUSetByteZ (W1, OP2); + IAPU.PC += 3; +} + +void Apu99 () +{ +// ADC (X),(Y) + uint8 W1 = S9xAPUGetByteZ (IAPU.X); + uint8 Work8 = S9xAPUGetByteZ (IAPU.YA.B.Y); + ADC (W1, Work8); + S9xAPUSetByteZ (W1, IAPU.X); + IAPU.PC++; +} + +void Apu8D () +{ +// MOV Y,#00 + IAPU.YA.B.Y = OP1; + APUSetZN8 (IAPU.YA.B.Y); + IAPU.PC += 2; +} + +void Apu8F () +{ +// MOV dp,#00 + uint8 Work8 = OP1; + S9xAPUSetByteZ (Work8, OP2); + IAPU.PC += 3; +} + +void Apu9E () +{ +// DIV YA,X + if (IAPU.X == 0) + { + APUSetOverflow (); + IAPU.YA.B.Y = 0xff; + IAPU.YA.B.A = 0xff; + } + else + { + APUClearOverflow (); + uint8 Work8 = IAPU.YA.W / IAPU.X; + IAPU.YA.B.Y = IAPU.YA.W % IAPU.X; + IAPU.YA.B.A = Work8; + } +// XXX How should Overflow, Half Carry, Zero and Negative flags be set?? + // APUSetZN16 (IAPU.YA.W); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void Apu9F () +{ +// XCN A + IAPU.YA.B.A = (IAPU.YA.B.A >> 4) | (IAPU.YA.B.A << 4); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void ApuA4 () +{ +// SBC A, dp + uint8 Work8 = S9xAPUGetByteZ (OP1); + SBC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void ApuA5 () +{ +// SBC A, abs + Absolute (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + SBC (IAPU.YA.B.A, Work8); + IAPU.PC += 3; +} + +void ApuA6 () +{ +// SBC A, (X) + uint8 Work8 = S9xAPUGetByteZ (IAPU.X); + SBC (IAPU.YA.B.A, Work8); + IAPU.PC++; +} + +void ApuA7 () +{ +// SBC A,(dp+X) + IndexedXIndirect (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + SBC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void ApuA8 () +{ +// SBC A,#00 + uint8 Work8 = OP1; + SBC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void ApuA9 () +{ +// SBC dp(dest), dp(src) + uint8 Work8 = S9xAPUGetByteZ (OP1); + uint8 W1 = S9xAPUGetByteZ (OP2); + SBC (W1, Work8); + S9xAPUSetByteZ (W1, OP2); + IAPU.PC += 3; +} + +void ApuB4 () +{ +// SBC A, dp+X + uint8 Work8 = S9xAPUGetByteZ (OP1 + IAPU.X); + SBC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void ApuB5 () +{ +// SBC A,abs+X + AbsoluteX (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + SBC (IAPU.YA.B.A, Work8); + IAPU.PC += 3; +} + +void ApuB6 () +{ +// SBC A,abs+Y + AbsoluteY (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + SBC (IAPU.YA.B.A, Work8); + IAPU.PC += 3; +} + +void ApuB7 () +{ +// SBC A,(dp)+Y + IndirectIndexedY (); + uint8 Work8 = S9xAPUGetByte (((IAPU.Address))); + SBC (IAPU.YA.B.A, Work8); + IAPU.PC += 2; +} + +void ApuB8 () +{ +// SBC dp,#00 + uint8 Work8 = OP1; + uint8 W1 = S9xAPUGetByteZ (OP2); + SBC (W1, Work8); + S9xAPUSetByteZ (W1, OP2); + IAPU.PC += 3; +} + +void ApuB9 () +{ +// SBC (X),(Y) + uint8 W1 = S9xAPUGetByteZ (IAPU.X); + uint8 Work8 = S9xAPUGetByteZ (IAPU.YA.B.Y); + SBC (W1, Work8); + S9xAPUSetByteZ (W1, IAPU.X); + IAPU.PC++; +} + +void ApuAF () +{ +// MOV (X)+, A + S9xAPUSetByteZ (IAPU.YA.B.A, IAPU.X++); + IAPU.PC++; +} + +void ApuBE () +{ +// DAS + if ((IAPU.YA.B.A & 0x0f) > 9 || !APUCheckHalfCarry()) + { + IAPU.YA.B.A -= 6; + } + if (IAPU.YA.B.A > 0x9f || !IAPU._Carry) + { + IAPU.YA.B.A -= 0x60; + APUClearCarry (); + } + else { APUSetCarry (); } + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void ApuBF () +{ +// MOV A,(X)+ + IAPU.YA.B.A = S9xAPUGetByteZ (IAPU.X++); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void ApuC0 () +{ +// DI + APUClearInterrupt (); + IAPU.PC++; +} + +void ApuA0 () +{ +// EI + APUSetInterrupt (); + IAPU.PC++; +} + +void ApuC4 () +{ +// MOV dp,A + S9xAPUSetByteZ (IAPU.YA.B.A, OP1); + IAPU.PC += 2; +} + +void ApuC5 () +{ +// MOV abs,A + Absolute (); + S9xAPUSetByte (IAPU.YA.B.A, IAPU.Address); + IAPU.PC += 3; +} + +void ApuC6 () +{ +// MOV (X), A + S9xAPUSetByteZ (IAPU.YA.B.A, IAPU.X); + IAPU.PC++; +} + +void ApuC7 () +{ +// MOV (dp+X),A + IndexedXIndirect (); + S9xAPUSetByte (IAPU.YA.B.A, IAPU.Address); + IAPU.PC += 2; +} + +void ApuC9 () +{ +// MOV abs,X + Absolute (); + S9xAPUSetByte (IAPU.X, IAPU.Address); + IAPU.PC += 3; +} + +void ApuCB () +{ +// MOV dp,Y + S9xAPUSetByteZ (IAPU.YA.B.Y, OP1); + IAPU.PC += 2; +} + +void ApuCC () +{ +// MOV abs,Y + Absolute (); + S9xAPUSetByte (IAPU.YA.B.Y, IAPU.Address); + IAPU.PC += 3; +} + +void ApuCD () +{ +// MOV X,#00 + IAPU.X = OP1; + APUSetZN8 (IAPU.X); + IAPU.PC += 2; +} + +void ApuCF () +{ +// MUL YA + IAPU.YA.W = (uint16) IAPU.YA.B.A * IAPU.YA.B.Y; + APUSetZN16 (IAPU.YA.W); + IAPU.PC++; +} + +void ApuD4 () +{ +// MOV dp+X, A + S9xAPUSetByteZ (IAPU.YA.B.A, OP1 + IAPU.X); + IAPU.PC += 2; +} + +void ApuD5 () +{ +// MOV abs+X,A + AbsoluteX (); + S9xAPUSetByte (IAPU.YA.B.A, IAPU.Address); + IAPU.PC += 3; +} + +void ApuD6 () +{ +// MOV abs+Y,A + AbsoluteY (); + S9xAPUSetByte (IAPU.YA.B.A, IAPU.Address); + IAPU.PC += 3; +} + +void ApuD7 () +{ +// MOV (dp)+Y,A + IndirectIndexedY (); + S9xAPUSetByte (IAPU.YA.B.A, IAPU.Address); + IAPU.PC += 2; +} + +void ApuD8 () +{ +// MOV dp,X + S9xAPUSetByteZ (IAPU.X, OP1); + IAPU.PC += 2; +} + +void ApuD9 () +{ +// MOV dp+Y,X + S9xAPUSetByteZ (IAPU.X, OP1 + IAPU.YA.B.Y); + IAPU.PC += 2; +} + +void ApuDB () +{ +// MOV dp+X,Y + S9xAPUSetByteZ (IAPU.YA.B.Y, OP1 + IAPU.X); + IAPU.PC += 2; +} + +void ApuDF () +{ +// DAA + if ((IAPU.YA.B.A & 0x0f) > 9 || APUCheckHalfCarry()) + { + if(IAPU.YA.B.A > 0xf0) APUSetCarry (); + IAPU.YA.B.A += 6; + //APUSetHalfCarry (); Intel procs do this, but this is a Sony proc... + } + //else { APUClearHalfCarry (); } ditto as above + if (IAPU.YA.B.A > 0x9f || IAPU._Carry) + { + IAPU.YA.B.A += 0x60; + APUSetCarry (); + } + else { APUClearCarry (); } + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void ApuE4 () +{ +// MOV A, dp + IAPU.YA.B.A = S9xAPUGetByteZ (OP1); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void ApuE5 () +{ +// MOV A,abs + Absolute (); + IAPU.YA.B.A = S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void ApuE6 () +{ +// MOV A,(X) + IAPU.YA.B.A = S9xAPUGetByteZ (IAPU.X); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC++; +} + +void ApuE7 () +{ +// MOV A,(dp+X) + IndexedXIndirect (); + IAPU.YA.B.A = S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void ApuE8 () +{ +// MOV A,#00 + IAPU.YA.B.A = OP1; + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void ApuE9 () +{ +// MOV X, abs + Absolute (); + IAPU.X = S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.X); + IAPU.PC += 3; +} + +void ApuEB () +{ +// MOV Y,dp + IAPU.YA.B.Y = S9xAPUGetByteZ (OP1); + APUSetZN8 (IAPU.YA.B.Y); + IAPU.PC += 2; +} + +void ApuEC () +{ +// MOV Y,abs + Absolute (); + IAPU.YA.B.Y = S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.Y); + IAPU.PC += 3; +} + +void ApuF4 () +{ +// MOV A, dp+X + IAPU.YA.B.A = S9xAPUGetByteZ (OP1 + IAPU.X); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void ApuF5 () +{ +// MOV A, abs+X + AbsoluteX (); + IAPU.YA.B.A = S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void ApuF6 () +{ +// MOV A, abs+Y + AbsoluteY (); + IAPU.YA.B.A = S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 3; +} + +void ApuF7 () +{ +// MOV A, (dp)+Y + IndirectIndexedY (); + IAPU.YA.B.A = S9xAPUGetByte (IAPU.Address); + APUSetZN8 (IAPU.YA.B.A); + IAPU.PC += 2; +} + +void ApuF8 () +{ +// MOV X,dp + IAPU.X = S9xAPUGetByteZ (OP1); + APUSetZN8 (IAPU.X); + IAPU.PC += 2; +} + +void ApuF9 () +{ +// MOV X,dp+Y + IAPU.X = S9xAPUGetByteZ (OP1 + IAPU.YA.B.Y); + APUSetZN8 (IAPU.X); + IAPU.PC += 2; +} + +void ApuFA () +{ +// MOV dp(dest),dp(src) + S9xAPUSetByteZ (S9xAPUGetByteZ (OP1), OP2); + IAPU.PC += 3; +} + +void ApuFB () +{ +// MOV Y,dp+X + IAPU.YA.B.Y = S9xAPUGetByteZ (OP1 + IAPU.X); + APUSetZN8 (IAPU.YA.B.Y); + IAPU.PC += 2; +} + +#if defined(NO_INLINE_SET_GET) +#undef INLINE +#define INLINE +#include "apumem.h" +#endif + + +void (*S9xApuOpcodes[256]) (void) = +{ + Apu00, Apu01, Apu02, Apu03, Apu04, Apu05, Apu06, Apu07, + Apu08, Apu09, Apu0A, Apu0B, Apu0C, Apu0D, Apu0E, Apu0F, + Apu10, Apu11, Apu12, Apu13, Apu14, Apu15, Apu16, Apu17, + Apu18, Apu19, Apu1A, Apu1B, Apu1C, Apu1D, Apu1E, Apu1F, + Apu20, Apu21, Apu22, Apu23, Apu24, Apu25, Apu26, Apu27, + Apu28, Apu29, Apu2A, Apu2B, Apu2C, Apu2D, Apu2E, Apu2F, + Apu30, Apu31, Apu32, Apu33, Apu34, Apu35, Apu36, Apu37, + Apu38, Apu39, Apu3A, Apu3B, Apu3C, Apu3D, Apu3E, Apu3F, + Apu40, Apu41, Apu42, Apu43, Apu44, Apu45, Apu46, Apu47, + Apu48, Apu49, Apu4A, Apu4B, Apu4C, Apu4D, Apu4E, Apu4F, + Apu50, Apu51, Apu52, Apu53, Apu54, Apu55, Apu56, Apu57, + Apu58, Apu59, Apu5A, Apu5B, Apu5C, Apu5D, Apu5E, Apu5F, + Apu60, Apu61, Apu62, Apu63, Apu64, Apu65, Apu66, Apu67, + Apu68, Apu69, Apu6A, Apu6B, Apu6C, Apu6D, Apu6E, Apu6F, + Apu70, Apu71, Apu72, Apu73, Apu74, Apu75, Apu76, Apu77, + Apu78, Apu79, Apu7A, Apu7B, Apu7C, Apu7D, Apu7E, Apu7F, + Apu80, Apu81, Apu82, Apu83, Apu84, Apu85, Apu86, Apu87, + Apu88, Apu89, Apu8A, Apu8B, Apu8C, Apu8D, Apu8E, Apu8F, + Apu90, Apu91, Apu92, Apu93, Apu94, Apu95, Apu96, Apu97, + Apu98, Apu99, Apu9A, Apu9B, Apu9C, Apu9D, Apu9E, Apu9F, + ApuA0, ApuA1, ApuA2, ApuA3, ApuA4, ApuA5, ApuA6, ApuA7, + ApuA8, ApuA9, ApuAA, ApuAB, ApuAC, ApuAD, ApuAE, ApuAF, + ApuB0, ApuB1, ApuB2, ApuB3, ApuB4, ApuB5, ApuB6, ApuB7, + ApuB8, ApuB9, ApuBA, ApuBB, ApuBC, ApuBD, ApuBE, ApuBF, + ApuC0, ApuC1, ApuC2, ApuC3, ApuC4, ApuC5, ApuC6, ApuC7, + ApuC8, ApuC9, ApuCA, ApuCB, ApuCC, ApuCD, ApuCE, ApuCF, + ApuD0, ApuD1, ApuD2, ApuD3, ApuD4, ApuD5, ApuD6, ApuD7, + ApuD8, ApuD9, ApuDA, ApuDB, ApuDC, ApuDD, ApuDE, ApuDF, + ApuE0, ApuE1, ApuE2, ApuE3, ApuE4, ApuE5, ApuE6, ApuE7, + ApuE8, ApuE9, ApuEA, ApuEB, ApuEC, ApuED, ApuEE, ApuEF, + ApuF0, ApuF1, ApuF2, ApuF3, ApuF4, ApuF5, ApuF6, ApuF7, + ApuF8, ApuF9, ApuFA, ApuFB, ApuFC, ApuFD, ApuFE, ApuFF +}; + +#endif + diff --git a/src/spc700.h b/src/spc700.h new file mode 100644 index 0000000..8cde84d --- /dev/null +++ b/src/spc700.h @@ -0,0 +1,139 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _SPC700_H_ +#define _SPC700_H_ + +#ifdef SPCTOOL +#define NO_CHANNEL_STRUCT +#include "spctool/dsp.h" +#include "spctool/spc700.h" +#include "spctool/soundmod.h" +#endif + + +#define Carry 1 +#define Zero 2 +#define Interrupt 4 +#define HalfCarry 8 +#define BreakFlag 16 +#define DirectPageFlag 32 +#define Overflow 64 +#define Negative 128 + +#define APUClearCarry() (IAPU._Carry = 0) +#define APUSetCarry() (IAPU._Carry = 1) +#define APUSetInterrupt() (IAPU.P |= Interrupt) +#define APUClearInterrupt() (IAPU.P &= ~Interrupt) +#define APUSetHalfCarry() (IAPU.P |= HalfCarry) +#define APUClearHalfCarry() (IAPU.P &= ~HalfCarry) +#define APUSetBreak() (IAPU.P |= BreakFlag) +#define APUClearBreak() (IAPU.P &= ~BreakFlag) +#define APUSetDirectPage() (IAPU.P |= DirectPageFlag) +#define APUClearDirectPage() (IAPU.P &= ~DirectPageFlag) +#define APUSetOverflow() (IAPU._Overflow = 1) +#define APUClearOverflow() (IAPU._Overflow = 0) + +#define APUCheckZero() (IAPU._Zero == 0) +#define APUCheckCarry() (IAPU._Carry) +#define APUCheckInterrupt() (IAPU.P & Interrupt) +#define APUCheckHalfCarry() (IAPU.P & HalfCarry) +#define APUCheckBreak() (IAPU.P & BreakFlag) +#define APUCheckDirectPage() (IAPU.P & DirectPageFlag) +#define APUCheckOverflow() (IAPU._Overflow) +#define APUCheckNegative() (IAPU._Zero & 0x80) + +//#define APUClearFlags(f) (IAPU.P &= ~(f)) +//#define APUSetFlags(f) (IAPU.P |= (f)) +//#define APUCheckFlag(f) (IAPU.P & (f)) + +typedef union +{ +#ifdef LSB_FIRST + struct { uint8 A, Y; } B; +#else + struct { uint8 Y, A; } B; +#endif + uint16 W; + uint32 _padder; // make sure this whole thing takes 4 bytes +} YAndA; + +struct SAPURegisters{ + uint8 P; + YAndA YA; + uint8 X; + uint8 S; + uint16 PC; +}; + +//EXTERN_C struct SAPURegisters APURegisters; + +// Needed by ILLUSION OF GAIA +//#define ONE_APU_CYCLE 14 +#define ONE_APU_CYCLE 21 + +// Needed by all games written by the software company called Human +//#define ONE_APU_CYCLE_HUMAN 17 +#define ONE_APU_CYCLE_HUMAN 21 + +// 1.953us := 1.024065.54MHz + +#ifdef SPCTOOL +EXTERN_C int32 ESPC (int32); + +#define APU_EXECUTE() \ +{ \ + int32 l = (CPU.Cycles - CPU.APU_Cycles) / 14; \ + if (l > 0) \ + { \ + l -= _EmuSPC(l); \ + CPU.APU_Cycles += l * 14; \ + } \ +} + +#else + + +// return cycles left (always negative) +extern "C" int spc700_execute(int cycles); + +#endif // SPCTOOL + +#endif diff --git a/src/spc700/Makefile b/src/spc700/Makefile new file mode 100644 index 0000000..e412de9 --- /dev/null +++ b/src/spc700/Makefile @@ -0,0 +1,13 @@ +CFLAGS = -Wall + +all : spc700a.s + +spc700a.s : spcgen + ./spcgen + +spcgen : spcgen.o + + +clean : + $(RM) spc700a.s spcgen spcgen.o + diff --git a/src/spc700/Makefile.win b/src/spc700/Makefile.win new file mode 100644 index 0000000..06095b0 --- /dev/null +++ b/src/spc700/Makefile.win @@ -0,0 +1,15 @@ +# Makefile for MS Visual C + +ALL : spc700a.s + +spc700a.s : spcgen.exe + spcgen.exe + +spcgen.exe : + cl /W3 spcgen.c + + +CLEAN : + -@erase spc700a.s + -@erase spcgen.exe + -@erase spcgen.obj diff --git a/src/spc700/debug/apu.h b/src/spc700/debug/apu.h new file mode 100644 index 0000000..dd0451c --- /dev/null +++ b/src/spc700/debug/apu.h @@ -0,0 +1,195 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _apu_h_ +#define _apu_h_ + +#include "spc700.h" + +/* +typedef union +{ + struct { uint8 A, Y; } B; + uint16 W; +} YAndA; +*/ + +struct SIAPU +{ + uint8 *DirectPage; // 0x00 + uint32 Address; // 0x04 c core only + uint8 *WaitAddress1; // 0x08 + uint8 *WaitAddress2; // 0x0C + uint32 WaitCounter; // 0x10 + uint8 *ShadowRAM; // 0x14 + uint8 *CachedSamples; // 0x18 + uint8 _Carry; // 0x1C c core only + uint8 _Overflow; // 0x1D c core only + uint8 Bit; // 0x1E c core only + uint8 pad0; + uint32 TimerErrorCounter; // 0x20 + uint32 Scanline; // 0x24 + int32 OneCycle; // 0x28 + int32 TwoCycles; // 0x2C + // notaz: reordered and moved everything here, for faster context load/save + uint32 *asmJumpTab; // 0x30 + uint8 *PC; // 0x34 + YAndA YA; // 0x38 0x0000YYAA + uint8 P; // 0x3C flags: NODBHIZC + uint8 pad1; + uint8 pad2; + uint8 _Zero; // 0x3F Z=0, when this!=0; also stores neg flag in &0x80 + uint8 X; // 0x40 + uint8 S; // 0x41 stack pointer, default: 0xff + uint16 pad3; + uint8 *RAM; // 0x44 + uint8 *ExtraRAM; // 0x48 shortcut to APU.ExtraRAM + + uint16 memread_addr; + uint8 memread_data; + uint16 memwrite_addr; + uint8 memwrite_data; + int icount; + uint8 opcode; + uint16 ya_prev; + uint8 x_prev; +}; + +struct SAPU +{ + int32 Cycles; + bool8 ShowROM; + uint8 Flags; + uint8 KeyedChannels; + uint8 OutPorts [4]; + uint8 DSP [0x80]; + uint8 ExtraRAM [64]; + uint16 Timer [3]; + uint16 TimerTarget [3]; + bool8 TimerEnabled [3]; + bool8 TimerValueWritten [3]; +}; + +EXTERN_C struct SAPU APU; +EXTERN_C struct SIAPU IAPU; +EXTERN_C struct SIAPU IAPU2; +EXTERN_C struct SIAPU *pIAPU; + +STATIC inline void S9xAPUUnpackStatus() +{ + IAPU._Zero =((IAPU.P & Zero) == 0) | (IAPU.P & Negative); + IAPU._Carry = (IAPU.P & Carry); + IAPU._Overflow = (IAPU.P & Overflow); +} + +STATIC inline void S9xAPUPackStatus() +{ + IAPU.P &= ~(Zero | Negative | Carry | Overflow); + if(IAPU._Carry) IAPU.P |= Carry; + if(!IAPU._Zero) IAPU.P |= Zero; + if(IAPU._Overflow) IAPU.P |= Overflow; + if(IAPU._Zero & 0x80) IAPU.P |= Negative; +} + +START_EXTERN_C +void S9xResetAPU (void); +bool8 S9xInitAPU (); +void S9xDeinitAPU (); +void S9xDecacheSamples (); +int S9xTraceAPU (); +int S9xAPUOPrint (char *buffer, uint16 Address); +void S9xSetAPUControl (uint8 byte); +void S9xSetAPUDSP (uint8 byte); +uint8 S9xGetAPUDSP (); +void S9xSetAPUTimer (uint16 Address, uint8 byte); +bool8 S9xInitSound (int quality, bool8 stereo, int buffer_size); +void S9xOpenCloseSoundTracingFile (bool8); +void S9xPrintAPUState (); +extern int32 S9xAPUCycles [256]; // Scaled cycle lengths +extern int32 S9xAPUCycleLengths [256]; // Raw data. +extern void (*S9xApuOpcodes [256]) (void); +extern void (*S9xApuOpcodesReal [256]) (void); +void APUCompare(); +END_EXTERN_C + + +#define APU_VOL_LEFT 0x00 +#define APU_VOL_RIGHT 0x01 +#define APU_P_LOW 0x02 +#define APU_P_HIGH 0x03 +#define APU_SRCN 0x04 +#define APU_ADSR1 0x05 +#define APU_ADSR2 0x06 +#define APU_GAIN 0x07 +#define APU_ENVX 0x08 +#define APU_OUTX 0x09 + +#define APU_MVOL_LEFT 0x0c +#define APU_MVOL_RIGHT 0x1c +#define APU_EVOL_LEFT 0x2c +#define APU_EVOL_RIGHT 0x3c +#define APU_KON 0x4c +#define APU_KOFF 0x5c +#define APU_FLG 0x6c +#define APU_ENDX 0x7c + +#define APU_EFB 0x0d +#define APU_PMON 0x2d +#define APU_NON 0x3d +#define APU_EON 0x4d +#define APU_DIR 0x5d +#define APU_ESA 0x6d +#define APU_EDL 0x7d + +#define APU_C0 0x0f +#define APU_C1 0x1f +#define APU_C2 0x2f +#define APU_C3 0x3f +#define APU_C4 0x4f +#define APU_C5 0x5f +#define APU_C6 0x6f +#define APU_C7 0x7f + +#define APU_SOFT_RESET 0x80 +#define APU_MUTE 0x40 +#define APU_ECHO_DISABLED 0x20 + +#define FREQUENCY_MASK 0x3fff +#endif diff --git a/src/spc700/debug/apumem.h b/src/spc700/debug/apumem.h new file mode 100644 index 0000000..b1b5f65 --- /dev/null +++ b/src/spc700/debug/apumem.h @@ -0,0 +1,222 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _apumemory_h_ +#define _apumemory_h_ + +START_EXTERN_C +extern uint8 W4; +extern uint8 APUROM[64]; +END_EXTERN_C + +// TODO: restore nondebug version + +INLINE uint8 S9xAPUGetByteZ (uint8 Address) +{ + uint8 res = 0; + pIAPU->memread_addr = Address; + + if (Address >= 0xf0 && pIAPU->DirectPage == pIAPU->RAM) + { + if (Address >= 0xf4 && Address <= 0xf7) + { +#ifdef SPC700_SHUTDOWN + pIAPU->WaitAddress2 = pIAPU->WaitAddress1; + pIAPU->WaitAddress1 = pIAPU->PC; +#endif + res = (pIAPU->RAM [Address]); + } + else if (Address >= 0xfd) + { +#ifdef SPC700_SHUTDOWN + pIAPU->WaitAddress2 = pIAPU->WaitAddress1; + pIAPU->WaitAddress1 = pIAPU->PC; +#endif + uint8 t = pIAPU->RAM [Address]; + if(pIAPU != &IAPU) + pIAPU->RAM [Address] = 0; + res = (t); + } + else if (Address == 0xf3) { + res = (S9xGetAPUDSP ()); + } + else res = (pIAPU->RAM [Address]); + } + else + res = (pIAPU->DirectPage [Address]); + + pIAPU->memread_data = res; + return res; +} + +INLINE void S9xAPUSetByteZ (uint8 val, uint8 Address) +{ + pIAPU->memwrite_addr = Address; + pIAPU->memwrite_data = val; + + if(pIAPU == &IAPU) return; + + if (Address >= 0xf0 && pIAPU->DirectPage == pIAPU->RAM) + { + if (Address == 0xf3) + S9xSetAPUDSP (val); + else + if (Address >= 0xf4 && Address <= 0xf7) + APU.OutPorts [Address - 0xf4] = val; + else + if (Address == 0xf1) + S9xSetAPUControl (val); + else + if (Address < 0xfd) + { + pIAPU->RAM [Address] = val; + if (Address >= 0xfa) + { + if (val == 0) + APU.TimerTarget [Address - 0xfa] = 0x100; + else + APU.TimerTarget [Address - 0xfa] = val; + } + } + } + else + pIAPU->DirectPage [Address] = val; +} + +INLINE uint8 S9xAPUGetByte (uint32 Address) +{ + Address &= 0xffff; + uint8 res = 0; + pIAPU->memread_addr = Address; + + if (Address <= 0xff && Address >= 0xf0) + { + if (Address >= 0xf4 && Address <= 0xf7) + { +#ifdef SPC700_SHUTDOWN + pIAPU->WaitAddress2 = pIAPU->WaitAddress1; + pIAPU->WaitAddress1 = pIAPU->PC; +#endif + res = (pIAPU->RAM [Address]); + } + else if (Address == 0xf3) { + res = (S9xGetAPUDSP ()); + } + else if (Address >= 0xfd) + { +#ifdef SPC700_SHUTDOWN + pIAPU->WaitAddress2 = pIAPU->WaitAddress1; + pIAPU->WaitAddress1 = pIAPU->PC; +#endif + uint8 t = pIAPU->RAM [Address]; + if(pIAPU != &IAPU) + pIAPU->RAM [Address] = 0; + res = (t); + } + else res = (pIAPU->RAM [Address]); + } + else + res = (pIAPU->RAM [Address]); + + pIAPU->memread_data = res; + return res; +} + +INLINE void S9xAPUSetByte (uint8 val, uint32 Address) +{ + Address &= 0xffff; + pIAPU->memwrite_addr = Address; + pIAPU->memwrite_data = val; + + if(pIAPU == &IAPU) return; + + if (Address <= 0xff && Address >= 0xf0) + { + if (Address == 0xf3) + S9xSetAPUDSP (val); + else + if (Address >= 0xf4 && Address <= 0xf7) + APU.OutPorts [Address - 0xf4] = val; + else + if (Address == 0xf1) + S9xSetAPUControl (val); + else + if (Address < 0xfd) + { + pIAPU->RAM [Address] = val; + if (Address >= 0xfa) + { + if (val == 0) + APU.TimerTarget [Address - 0xfa] = 0x100; + else + APU.TimerTarget [Address - 0xfa] = val; + } + } + } + else + { +#if 0 +if (Address >= 0x2500 && Address <= 0x2504) +printf ("%06d %04x <- %02x\n", ICPU.Scanline, Address, val); +if (Address == 0x26c6) +{ + extern FILE *apu_trace; + extern FILE *trace; + APU.Flags |= TRACE_FLAG; + CPU.Flags |= TRACE_FLAG; + if (apu_trace == NULL) + apu_trace = fopen ("aputrace.log", "wb"); + if (trace == NULL) + trace = fopen ("trace.log", "wb"); + printf ("TRACING SWITCHED ON\n"); +} +#endif + if (Address < 0xffc0) + pIAPU->RAM [Address] = val; + else + { + APU.ExtraRAM [Address - 0xffc0] = val; + if (!APU.ShowROM) + pIAPU->RAM [Address] = val; + } + } +} + +#endif diff --git a/src/spc700/debug/port.h b/src/spc700/debug/port.h new file mode 100644 index 0000000..4d7eede --- /dev/null +++ b/src/spc700/debug/port.h @@ -0,0 +1,497 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _PORT_H_ +#define _PORT_H_ + + +// horrible mess here + +int yo_rand(void); + +#ifdef __SYMBIAN32__ + +// debug +#ifdef __DEBUG_PRINT +#undef printf +extern "C" void dprintf(char *format, ...); +#define printf dprintf +#else +#define printf(x...) +#define dprintf(x...) +#endif + +#include + +#define PIXEL_FORMAT RGB565 +#undef GFX_MULTI_FORMAT + +#ifndef snes9x_types_defined +#define snes9x_types_defined + +typedef unsigned char bool8; +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef signed char int8; +typedef signed short int16; +typedef signed int int32; +typedef unsigned int uint32; +typedef long long int64; // correct? +#endif + +#include "pixform.h" + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#if defined(__cplusplus) || defined(c_plusplus) +#define EXTERN_C extern "C" +#define START_EXTERN_C extern "C" { +#define END_EXTERN_C } +#else +#define EXTERN_C extern +#define START_EXTERN_C +#define END_EXTERN_C +#endif + + +#ifndef PATH_MAX +#define PATH_MAX 0x100 // == KMaxFileName +#endif + +/* +#define _MAX_DIR PATH_MAX +#define _MAX_DRIVE 1 +#define _MAX_FNAME PATH_MAX +#define _MAX_EXT 3 +*/ +#define _MAX_PATH PATH_MAX + + +#define ZeroMemory(a,b) memset((a),0,(b)) + +EXTERN_C void S9xGenerateSound (); + +#define SLASH_STR "\\" +#define SLASH_CHAR '\\' + +#define LSB_FIRST +#define STATIC static +#define FASTCALL +#define INLINE inline +#define VOID void +#define PACKING __attribute__ ((packed)) +#define ALIGN_BY_ONE __attribute__ ((aligned (1), packed)) +#define gp32_pause() +#define gm_memset memset +#define CHECK_SOUND() +#define CPU_SHUTDOWN +#define VAR_CYCLES +#define SPC700_C +#define EXECUTE_SUPERFX_PER_LINE +#define OLD_COLOUR_BLENDING +#define _NEWPPU_ +#define gp32_atoi atoi +//#define SPC700_SHUTDOWN // incompatible with ASM_SPC700 +// notaz +//#define ASM_SPC700 +#define SUPER_FX + +#ifndef TITLE +#define TITLE "Snes9x" +#endif + + +#else // __SYMBIAN32__ + + +//#include + +#ifdef __GP32__ + + +//#define __GP32_APUCACHE__ + +#define CHECK_SOUND() + +#define VERSION_MAJOR 0 +#define VERSION_MINOR 3 + +long *gp32_fopen (char *fname,char *mode); +void gp32_fclose (long *s); +long gp32_fread (unsigned char *ptr,long lg,long *s); +long gp32_fwrite (unsigned char *ptr,long lg,long *s); +void gp32_fseek (long position,int ref,long *s); + + +//#undef ZLIB +//#define ZLIB +#define UNZIP_SUPPORT + + +#define SPC700_SHUTDOWN +#define CPU_SHUTDOWN +#define VAR_CYCLES +#define SPC700_C +//#define ZSNES_C4 +//#define ZSNES_FX +#define EXECUTE_SUPERFX_PER_LINE +//#define THREADCPU + + +//#define USE_GLIDE +//#define USE_OPENGL +//#define NETPLAY_SUPPORT +//#define FMOD_SUPPORT +#define OLD_COLOUR_BLENDING + +#endif // __GP32__ + +#ifndef STORM +#ifdef __GP32__ + +extern "C" +{ +#include "gpdef.h" +#include "gpstdlib.h" +#include "gpgraphic.h" +#include "gpfont.h" +#include "gpmm.h" +#include "gpmem.h" +#include "gpstdio.h" +} + +#undef byte +#undef word +#undef dword +#undef qword + +/*typedef unsigned long bool8_32; +typedef unsigned long uint8_32; +typedef unsigned long uint16_32; +typedef long int8_32; +typedef long int16_32;*/ + +#undef time_t +#define time_t long + +char *gp32_strrchr(char *s, char c); +char gp32_toupper(char c); +char *gp32_strupr(char *s); +char *gp32_strlwr(char *s); +int gp32_memcmp(char *s1,char *s2, int lg); +int gp32_strncmp(char *s1,char *s2, int lg); +int gp32_strcasecmp(const char *s1, const char *s2 ); +int gp32_strncasecmp(const char *s1, const char *s2, unsigned n); +long gp32_time(void); +int gp32_pause(void); +int gp32_atoi(char *s); + +#define malloc gm_malloc +#define free gm_free +#define memcpy gm_memcpy + +#define strcpy gm_strcpy +#define strncpy gm_strncpy +#define strcat gm_strcat +#define memset gm_memset +#define memmove gm_memcpy +#define strlen gm_lstrlen +#define strcmp gm_compare +#define memcmp(a,b,c) gp32_memcmp((char*)a,(char*)b,c) +#define strrchr(a,b) gp32_strrchr((char*)a,(char)b) +#define strncmp(a,b,c) gp32_strncmp((char*)a,(char*)b,(int)c) +#define strlwr gp32_strlwr +//#define atoi gp32_atoi + +#define islower(a) ((a>='a')&&(a<='z')) +#define isdigit(a) ((a>='0')&&(a<='9')) +#define isalpha(a) (((a>='0')&&(a<='9'))||((a>='0')&&(a<='9'))||((a>='A')&&(a<='Z'))) +#define toupper(a) (islower(a)?a+'A'-'a':a) + +#define sprintf gm_sprintf + + + +void gp32_printf(char *a); +void gp32_GpTextOut(unsigned char *buffer,int X,int Y,char *A,int col,int bold); +void gp32_GpTextOutBig(unsigned char *buffer,int X,int Y,char *A,int col,int bold); +#define printf //(a) gp32_printf(a) + +#define strcasecmp gp32_strcasecmp +#define strncasecmp gp32_strncasecmp + +#define time(a) gp32_time() + +#define _NEWPPU_ + +//#define PROFILING + +#ifdef PROFILING +void gp32_profile_start(int a); +void gp32_profile_end(int a); +#define PROF_START(a) gp32_profile_start(a) +#define PROF_END(a) gp32_profile_end(a) +#endif + +#elif defined(__SYMBIAN32__) // /__GP32__ +#include +#else +#include +#include +#endif +#else // #ifndef STORM +#include +#include +#endif + +//#include + +#define PIXEL_FORMAT RGB565 +#undef GFX_MULTI_FORMAT + +#if defined(TARGET_OS_MAC) && TARGET_OS_MAC + +#include "zlib.h" +#define ZLIB +#define EXECUTE_SUPERFX_PER_LINE +#define SOUND +#define VAR_CYCLES +#define CPU_SHUTDOWN +#define SPC700_SHUTDOWN +#define PIXEL_FORMAT RGB555 +#define CHECK_SOUND() +#define M_PI 3.14159265359 +#undef _MAX_PATH + +#undef DEBUGGER // Apple Universal Headers sometimes #define DEBUGGER +#undef GFX_MULTI_FORMAT + +int strncasecmp(const char *s1, const char *s2, unsigned n); +int strcasecmp(const char *s1, const char *s2 ); + +#endif + +#ifndef snes9x_types_defined +#define snes9x_types_defined + +typedef unsigned char bool8; + +#ifndef __WIN32kk__ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef signed char int8; +typedef signed short int16; +typedef signed int int32; +typedef unsigned int uint32; +#ifdef __GP32__ +typedef signed __int64 int64; +//typedef signed long int64; +#else +typedef long long int64; +#endif +#else // __WIN32kk__ + +#ifdef __BORLANDC__ +#include +#else + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef signed char int8; +typedef short int16; + +#ifndef WSAAPI +// winsock2.h typedefs int32 as well. +typedef long int32; +#endif + +typedef unsigned int uint32; + +#endif // __BORLANDC__ + +typedef __int64 int64; + +#endif // __WIN32kk__ +#endif // snes9x_types_defined +#include "pixform.h" + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifdef STORM +#define EXTERN_C +#define START_EXTERN_C +#define END_EXTERN_C +#else +#if defined(__cplusplus) || defined(c_plusplus) +#define EXTERN_C extern "C" +#define START_EXTERN_C extern "C" { +#define END_EXTERN_C } +#else +#define EXTERN_C extern +#define START_EXTERN_C +#define END_EXTERN_C +#endif +#endif + +#ifndef __WIN32kk__ + +#ifndef PATH_MAX +#define PATH_MAX 1024 +#endif + +#define _MAX_DIR PATH_MAX +#define _MAX_DRIVE 1 +#define _MAX_FNAME PATH_MAX +#define _MAX_EXT PATH_MAX +#define _MAX_PATH PATH_MAX + +#define ZeroMemory(a,b) memset((a),0,(b)) + +#ifndef __WIN32__ +void _makepath (char *path, const char *drive, const char *dir, const char *fname, const char *ext); +void _splitpath (const char *path, char *drive, char *dir, char *fname, char *ext); +#endif + +#else // __WIN32kk__ +#define strcasecmp stricmp +#define strncasecmp strnicmp +#endif + +EXTERN_C void S9xGenerateSound (); + +#ifdef STORM +EXTERN_C int soundsignal; +EXTERN_C void MixSound(void); +//Yes, CHECK_SOUND is getting defined correctly! +#define CHECK_SOUND if (Settings.APUEnabled) if(SetSignalPPC(0L, soundsignal) & soundsignal) MixSound +#else +#ifndef __GP32__ +#define CHECK_SOUND() +#endif +#endif + +#if defined (__DJGPP)||defined(__GP32__) +#define SLASH_STR "\\" +#define SLASH_CHAR '\\' +#else +#define SLASH_STR "/" +#define SLASH_CHAR '/' +#endif + +#ifdef __linux +typedef void (*SignalHandler)(int); +#define SIG_PF SignalHandler +#endif + +#if defined(__i386__) || defined(__i486__) || defined(__i586__) || \ + defined(__WIN32kk__) || defined(__alpha__) +#define LSB_FIRST +#define FAST_LSB_WORD_ACCESS +#define PACKING +#define ALIGN_BY_ONE + +#else + +#ifdef __GP32__ +#define LSB_FIRST +#define STATIC static +#define FASTCALL +#define INLINE inline +#define VOID void +#else +// must be gp2x +#define LSB_FIRST +#define STATIC static +#define FASTCALL +#define INLINE inline +#define VOID void +#define PACKING __attribute__ ((packed)) +#define ALIGN_BY_ONE __attribute__ ((aligned (1), packed)) +#define gp32_pause() +#define gm_memset memset +#define CHECK_SOUND() +#define VERSION_MAJOR 0 +#define VERSION_MINOR 3 +#define SPC700_SHUTDOWN +#define CPU_SHUTDOWN +#define VAR_CYCLES +#define SPC700_C +#define EXECUTE_SUPERFX_PER_LINE +#define OLD_COLOUR_BLENDING +#define _NEWPPU_ +#define gp32_atoi atoi +#endif + +#endif + +#ifdef __sun +#define TITLE "Snes9X: Solaris" +#endif + +#ifdef __linux +#define TITLE "Snes9X: Linux" +#endif + +#ifndef TITLE +#define TITLE "Snes9x" +#endif + +#ifdef STORM +#define STATIC +#define strncasecmp strnicmp +#else +#define STATIC static +#endif + +#endif // !defined(__SYMBIAN32__) + +#endif // _PORT_H_ diff --git a/src/spc700/debug/spc700.cpp b/src/spc700/debug/spc700.cpp new file mode 100644 index 0000000..5ab21ab --- /dev/null +++ b/src/spc700/debug/spc700.cpp @@ -0,0 +1,2600 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" +#include "memmap.h" +#include "display.h" +#include "cpuexec.h" +#include "apu.h" +#include "spc700.h" + +// SPC700/Sound DSP chips have a 24.57MHz crystal on their PCB. + +//#if defined(ASM_SPC700) +extern "C" { +uint8 S9xAPUGetByteZ (uint8 address); +uint8 S9xAPUGetByte (uint32 address); +void S9xAPUSetByteZ (uint8, uint8 address); +void S9xAPUSetByte (uint8, uint32 address); +} +/* +#elif defined(NO_INLINE_SET_GET) +uint8 S9xAPUGetByteZ (uint8 address); +uint8 S9xAPUGetByte (uint32 address); +void S9xAPUSetByteZ (uint8, uint8 address); +void S9xAPUSetByte (uint8, uint32 address); + +#else +#undef INLINE +#define INLINE inline +#include "apumem.h" +#endif +*/ + +START_EXTERN_C +extern uint8 Work8; +extern uint16 Work16; +extern uint32 Work32; +extern signed char Int8; +extern short Int16; +extern long Int32; +extern short Int16; +extern uint8 W1; +extern uint8 W2; + +END_EXTERN_C + +#define OP1 (*(pIAPU->PC + 1)) +#define OP2 (*(pIAPU->PC + 2)) + +#ifdef SPC700_SHUTDOWN +#define APUShutdown() \ + if (Settings.Shutdown && (pIAPU->PC == pIAPU->WaitAddress1 || pIAPU->PC == pIAPU->WaitAddress2)) \ + { \ + if (pIAPU->WaitCounter == 0) \ + { \ + if (!ICPU.CPUExecuting) \ + CPU.APU_Cycles = CPU.Cycles = CPU.NextEvent; \ + else \ + CPU.APU_APUExecuting = FALSE; \ + } \ + else \ + if (pIAPU->WaitCounter >= 2) \ + pIAPU->WaitCounter = 1; \ + else \ + pIAPU->WaitCounter--; \ + } +#else +#define APUShutdown() +#endif + +#define APUSetZN8(b)\ + pIAPU->_Zero = (b); + +#define APUSetZN16(w)\ + pIAPU->_Zero = ((w) != 0) | ((w) >> 8); + +void STOP (char *s) +{ + char buffer[100]; + +#ifdef DEBUGGER + S9xAPUOPrint (buffer, pIAPU->PC - pIAPU->RAM); +#endif + + sprintf (String, "Sound CPU in unknown state executing %s at %04lX\n%s\n", s, pIAPU->PC - pIAPU->RAM, buffer); + S9xMessage (S9X_ERROR, S9X_APU_STOPPED, String); + APU.TimerEnabled[0] = APU.TimerEnabled[1] = APU.TimerEnabled[2] = FALSE; + CPU.APU_APUExecuting = FALSE; + +#ifdef DEBUGGER + CPU.Flags |= DEBUG_MODE_FLAG; +#else + S9xExit (); +#endif +} + +#define TCALL(n)\ +{\ + PushW ((pIAPU->PC - pIAPU->RAM + 1)); \ + pIAPU->PC = pIAPU->RAM + (APU.ExtraRAM [((15 - n) << 1)] + \ + (APU.ExtraRAM [((15 - n) << 1) + 1] << 8)); \ +} + +// XXX: HalfCarry - BJ fixed? +#define SBC(a,b)\ +Int16 = (short) (a) - (short) (b) + (short) (APUCheckCarry ()) - 1;\ +pIAPU->_Carry = Int16 >= 0;\ +if ((((a) ^ (b)) & 0x80) && (((a) ^ (uint8) Int16) & 0x80))\ + APUSetOverflow ();\ +else \ + APUClearOverflow (); \ +APUSetHalfCarry ();\ +if(((a) ^ (b) ^ (uint8) Int16) & 0x10)\ + APUClearHalfCarry ();\ +(a) = (uint8) Int16;\ +APUSetZN8 ((uint8) Int16); + +// XXX: HalfCarry - BJ fixed? +#define ADC(a,b)\ +Work16 = (a) + (b) + APUCheckCarry();\ +pIAPU->_Carry = Work16 >= 0x100; \ +if (~((a) ^ (b)) & ((b) ^ (uint8) Work16) & 0x80)\ + APUSetOverflow ();\ +else \ + APUClearOverflow (); \ +APUClearHalfCarry ();\ +/*if(((a) ^ (b) ^ (uint8) Int16) & 0x10) notaz: Int16!? */\ +if(((a) ^ (b) ^ (uint8) Work16) & 0x10)\ + APUSetHalfCarry ();\ +(a) = (uint8) Work16;\ +APUSetZN8 ((uint8) Work16); + +#define CMP(a,b)\ +Int16 = (short) (a) - (short) (b);\ +pIAPU->_Carry = Int16 >= 0;\ +APUSetZN8 ((uint8) Int16); + +#define ASL(b)\ + pIAPU->_Carry = ((b) & 0x80) != 0; \ + (b) <<= 1;\ + APUSetZN8 (b); +#define LSR(b)\ + pIAPU->_Carry = (b) & 1;\ + (b) >>= 1;\ + APUSetZN8 (b); +#define ROL(b)\ + Work16 = ((b) << 1) | APUCheckCarry (); \ + pIAPU->_Carry = Work16 >= 0x100; \ + (b) = (uint8) Work16; \ + APUSetZN8 (b); +#define ROR(b)\ + Work16 = (b) | ((uint16) APUCheckCarry () << 8); \ + pIAPU->_Carry = (uint8) Work16 & 1; \ + Work16 >>= 1; \ + (b) = (uint8) Work16; \ + APUSetZN8 (b); + +#define Push(b)\ + *(pIAPU->RAM + 0x100 + pIAPU->S) = b;\ + pIAPU->S--; + +#define Pop(b)\ + pIAPU->S++;\ + (b) = *(pIAPU->RAM + 0x100 + pIAPU->S); + +#ifdef FAST_LSB_WORD_ACCESS +#define PushW(w)\ + *(uint16 *) (pIAPU->RAM + 0xff + pIAPU->S) = w;\ + pIAPU->S -= 2; +#define PopW(w)\ + pIAPU->S += 2;\ + w = *(uint16 *) (pIAPU->RAM + 0xff + pIAPU->S); +#else +#define PushW(w)\ + *(pIAPU->RAM + 0xff + pIAPU->S) = w;\ + *(pIAPU->RAM + 0x100 + pIAPU->S) = (w >> 8);\ + pIAPU->S -= 2; +#define PopW(w)\ + pIAPU->S += 2; \ + (w) = *(pIAPU->RAM + 0xff + pIAPU->S) + (*(pIAPU->RAM + 0x100 + pIAPU->S) << 8); +#endif + +#define Relative()\ + Int8 = OP1;\ + Int16 = (int) (pIAPU->PC + 2 - pIAPU->RAM) + Int8; + +#define Relative2()\ + Int8 = OP2;\ + Int16 = (int) (pIAPU->PC + 3 - pIAPU->RAM) + Int8; + +#ifdef FAST_LSB_WORD_ACCESS +#define IndexedXIndirect()\ + pIAPU->Address = *(uint16 *) (pIAPU->DirectPage + ((OP1 + pIAPU->X) & 0xff)); + +#define Absolute()\ + pIAPU->Address = *(uint16 *) (pIAPU->PC + 1); + +#define AbsoluteX()\ + pIAPU->Address = *(uint16 *) (pIAPU->PC + 1) + pIAPU->X; + +#define AbsoluteY()\ + pIAPU->Address = *(uint16 *) (pIAPU->PC + 1) + pIAPU->YA.B.Y; + +#define MemBit()\ + pIAPU->Address = *(uint16 *) (pIAPU->PC + 1);\ + pIAPU->Bit = (uint8)(pIAPU->Address >> 13);\ + pIAPU->Address &= 0x1fff; + +#define IndirectIndexedY()\ + pIAPU->Address = *(uint16 *) (pIAPU->DirectPage + OP1) + pIAPU->YA.B.Y; +#else +#define IndexedXIndirect()\ + pIAPU->Address = *(pIAPU->DirectPage + ((OP1 + pIAPU->X) & 0xff)) + \ + (*(pIAPU->DirectPage + ((OP1 + pIAPU->X + 1) & 0xff)) << 8); +#define Absolute()\ + pIAPU->Address = OP1 + (OP2 << 8); + +#define AbsoluteX()\ + pIAPU->Address = OP1 + (OP2 << 8) + pIAPU->X; + +#define AbsoluteY()\ + pIAPU->Address = OP1 + (OP2 << 8) + pIAPU->YA.B.Y; + +#define MemBit()\ + pIAPU->Address = OP1 + (OP2 << 8);\ + pIAPU->Bit = (int8) (pIAPU->Address >> 13);\ + pIAPU->Address &= 0x1fff; + +#define IndirectIndexedY()\ + pIAPU->Address = *(pIAPU->DirectPage + OP1) + \ + (*(pIAPU->DirectPage + OP1 + 1) << 8) + \ + pIAPU->YA.B.Y; +#endif + +void Apu00 () +{ +// NOP + pIAPU->PC++; +} + +void Apu01 () { TCALL (0) } + +void Apu11 () { TCALL (1) } + +void Apu21 () { TCALL (2) } + +void Apu31 () { TCALL (3) } + +void Apu41 () { TCALL (4) } + +void Apu51 () { TCALL (5) } + +void Apu61 () { TCALL (6) } + +void Apu71 () { TCALL (7) } + +void Apu81 () { TCALL (8) } + +void Apu91 () { TCALL (9) } + +void ApuA1 () { TCALL (10) } + +void ApuB1 () { TCALL (11) } + +void ApuC1 () { TCALL (12) } + +void ApuD1 () { TCALL (13) } + +void ApuE1 () { TCALL (14) } + +void ApuF1 () { TCALL (15) } + +void Apu3F () // CALL absolute +{ + Absolute (); + // 0xB6f for Star Fox 2 + PushW ((pIAPU->PC + 3 - pIAPU->RAM)); + pIAPU->PC = pIAPU->RAM + pIAPU->Address; +} + +void Apu4F () // PCALL $XX +{ + Work8 = OP1; + PushW ((pIAPU->PC + 2 - pIAPU->RAM)); + pIAPU->PC = pIAPU->RAM + 0xff00 + Work8; +} + +#define SET(b) \ +S9xAPUSetByteZ ((uint8) (S9xAPUGetByteZ (OP1 ) | (1 << (b))), OP1); \ +pIAPU->PC += 2 + +void Apu02 () +{ + SET (0); +} + +void Apu22 () +{ + SET (1); +} + +void Apu42 () +{ + SET (2); +} + +void Apu62 () +{ + SET (3); +} + +void Apu82 () +{ + SET (4); +} + +void ApuA2 () +{ + SET (5); +} + +void ApuC2 () +{ + SET (6); +} + +void ApuE2 () +{ + SET (7); +} + +#define CLR(b) \ +S9xAPUSetByteZ ((uint8) (S9xAPUGetByteZ (OP1) & ~(1 << (b))), OP1); \ +pIAPU->PC += 2; + +void Apu12 () +{ + CLR (0); +} + +void Apu32 () +{ + CLR (1); +} + +void Apu52 () +{ + CLR (2); +} + +void Apu72 () +{ + CLR (3); +} + +void Apu92 () +{ + CLR (4); +} + +void ApuB2 () +{ + CLR (5); +} + +void ApuD2 () +{ + CLR (6); +} + +void ApuF2 () +{ + CLR (7); +} + +#define BBS(b) \ +Work8 = OP1; \ +Relative2 (); \ +if (S9xAPUGetByteZ (Work8) & (1 << (b))) \ +{ \ + pIAPU->PC = pIAPU->RAM + (uint16) Int16; \ + CPU.APU_Cycles += pIAPU->TwoCycles; \ +} \ +else \ + pIAPU->PC += 3 + +void Apu03 () +{ + BBS (0); +} + +void Apu23 () +{ + BBS (1); +} + +void Apu43 () +{ + BBS (2); +} + +void Apu63 () +{ + BBS (3); +} + +void Apu83 () +{ + BBS (4); +} + +void ApuA3 () +{ + BBS (5); +} + +void ApuC3 () +{ + BBS (6); +} + +void ApuE3 () +{ + BBS (7); +} + +#define BBC(b) \ +Work8 = OP1; \ +Relative2 (); \ +if (!(S9xAPUGetByteZ (Work8) & (1 << (b)))) \ +{ \ + pIAPU->PC = pIAPU->RAM + (uint16) Int16; \ + CPU.APU_Cycles += pIAPU->TwoCycles; \ +} \ +else \ + pIAPU->PC += 3 + +void Apu13 () +{ + BBC (0); +} + +void Apu33 () +{ + BBC (1); +} + +void Apu53 () +{ + BBC (2); +} + +void Apu73 () +{ + BBC (3); +} + +void Apu93 () +{ + BBC (4); +} + +void ApuB3 () +{ + BBC (5); +} + +void ApuD3 () +{ + BBC (6); +} + +void ApuF3 () +{ + BBC (7); +} + +void Apu04 () +{ +// OR A,dp + pIAPU->YA.B.A |= S9xAPUGetByteZ (OP1); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu05 () +{ +// OR A,abs + Absolute (); + pIAPU->YA.B.A |= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void Apu06 () +{ +// OR A,(X) + pIAPU->YA.B.A |= S9xAPUGetByteZ (pIAPU->X); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu07 () +{ +// OR A,(dp+X) + IndexedXIndirect (); + pIAPU->YA.B.A |= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu08 () +{ +// OR A,#00 + pIAPU->YA.B.A |= OP1; + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu09 () +{ +// OR dp(dest),dp(src) + Work8 = S9xAPUGetByteZ (OP1); + Work8 |= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + pIAPU->PC += 3; +} + +void Apu14 () +{ +// OR A,dp+X + pIAPU->YA.B.A |= S9xAPUGetByteZ (OP1 + pIAPU->X); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu15 () +{ +// OR A,abs+X + AbsoluteX (); + pIAPU->YA.B.A |= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void Apu16 () +{ +// OR A,abs+Y + AbsoluteY (); + pIAPU->YA.B.A |= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void Apu17 () +{ +// OR A,(dp)+Y + IndirectIndexedY (); + pIAPU->YA.B.A |= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu18 () +{ +// OR dp,#00 + Work8 = OP1; + Work8 |= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + pIAPU->PC += 3; +} + +void Apu19 () +{ +// OR (X),(Y) + Work8 = S9xAPUGetByteZ (pIAPU->X) | S9xAPUGetByteZ (pIAPU->YA.B.Y); + APUSetZN8 (Work8); + S9xAPUSetByteZ (Work8, pIAPU->X); + pIAPU->PC++; +} + +void Apu0A () +{ +// OR1 C,membit + MemBit (); + if (!APUCheckCarry ()) + { + if (S9xAPUGetByte (pIAPU->Address) & (1 << pIAPU->Bit)) + APUSetCarry (); + } + pIAPU->PC += 3; +} + +void Apu2A () +{ +// OR1 C,not membit + MemBit (); + if (!APUCheckCarry ()) + { + if (!(S9xAPUGetByte (pIAPU->Address) & (1 << pIAPU->Bit))) + APUSetCarry (); + } + pIAPU->PC += 3; +} + +void Apu4A () +{ +// AND1 C,membit + MemBit (); + if (APUCheckCarry ()) + { + if (!(S9xAPUGetByte (pIAPU->Address) & (1 << pIAPU->Bit))) + APUClearCarry (); + } + pIAPU->PC += 3; +} + +void Apu6A () +{ +// AND1 C, not membit + MemBit (); + if (APUCheckCarry ()) + { + if ((S9xAPUGetByte (pIAPU->Address) & (1 << pIAPU->Bit))) + APUClearCarry (); + } + pIAPU->PC += 3; +} + +void Apu8A () +{ +// EOR1 C, membit + MemBit (); + if (APUCheckCarry ()) + { + if (S9xAPUGetByte (pIAPU->Address) & (1 << pIAPU->Bit)) + APUClearCarry (); + } + else + { + if (S9xAPUGetByte (pIAPU->Address) & (1 << pIAPU->Bit)) + APUSetCarry (); + } + pIAPU->PC += 3; +} + +void ApuAA () +{ +// MOV1 C,membit + MemBit (); + if (S9xAPUGetByte (pIAPU->Address) & (1 << pIAPU->Bit)) + APUSetCarry (); + else + APUClearCarry (); + pIAPU->PC += 3; +} + +void ApuCA () +{ +// MOV1 membit,C + MemBit (); + if (APUCheckCarry ()) + { + S9xAPUSetByte (S9xAPUGetByte (pIAPU->Address) | (1 << pIAPU->Bit), pIAPU->Address); + } + else + { + S9xAPUSetByte (S9xAPUGetByte (pIAPU->Address) & ~(1 << pIAPU->Bit), pIAPU->Address); + } + pIAPU->PC += 3; +} + +void ApuEA () +{ +// NOT1 membit + MemBit (); + S9xAPUSetByte (S9xAPUGetByte (pIAPU->Address) ^ (1 << pIAPU->Bit), pIAPU->Address); + pIAPU->PC += 3; +} + +void Apu0B () +{ +// ASL dp + Work8 = S9xAPUGetByteZ (OP1); + ASL (Work8); + S9xAPUSetByteZ (Work8, OP1); + pIAPU->PC += 2; +} + +void Apu0C () +{ +// ASL abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + ASL (Work8); + S9xAPUSetByte (Work8, pIAPU->Address); + pIAPU->PC += 3; +} + +void Apu1B () +{ +// ASL dp+X + Work8 = S9xAPUGetByteZ (OP1 + pIAPU->X); + ASL (Work8); + S9xAPUSetByteZ (Work8, OP1 + pIAPU->X); + pIAPU->PC += 2; +} + +void Apu1C () +{ +// ASL A + ASL (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu0D () +{ +// PUSH PSW + S9xAPUPackStatus (); + Push (pIAPU->P); + pIAPU->PC++; +} + +void Apu2D () +{ +// PUSH A + Push (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu4D () +{ +// PUSH X + Push (pIAPU->X); + pIAPU->PC++; +} + +void Apu6D () +{ +// PUSH Y + Push (pIAPU->YA.B.Y); + pIAPU->PC++; +} + +void Apu8E () +{ +// POP PSW + Pop (pIAPU->P); + S9xAPUUnpackStatus (); + if (APUCheckDirectPage ()) + pIAPU->DirectPage = pIAPU->RAM + 0x100; + else + pIAPU->DirectPage = pIAPU->RAM; + pIAPU->PC++; +} + +void ApuAE () +{ +// POP A + Pop (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void ApuCE () +{ +// POP X + Pop (pIAPU->X); + pIAPU->PC++; +} + +void ApuEE () +{ +// POP Y + Pop (pIAPU->YA.B.Y); + pIAPU->PC++; +} + +void Apu0E () +{ +// TSET1 abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + S9xAPUSetByte (Work8 | pIAPU->YA.B.A, pIAPU->Address); + Work8 &= pIAPU->YA.B.A; + APUSetZN8 (Work8); + pIAPU->PC += 3; +} + +void Apu4E () +{ +// TCLR1 abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + S9xAPUSetByte (Work8 & ~pIAPU->YA.B.A, pIAPU->Address); + Work8 &= pIAPU->YA.B.A; + APUSetZN8 (Work8); + pIAPU->PC += 3; +} + +void Apu0F () +{ +// BRK + +#if 0 + STOP ("BRK"); +#else + PushW ((pIAPU->PC + 1 - pIAPU->RAM)); + S9xAPUPackStatus (); + Push (pIAPU->P); + APUSetBreak (); + APUClearInterrupt (); +// XXX:Where is the BRK vector ??? + pIAPU->PC = pIAPU->RAM + APU.ExtraRAM[0x20] + (APU.ExtraRAM[0x21] << 8); +#endif +} + +void ApuEF () +{ +// SLEEP + // XXX: sleep + // STOP ("SLEEP"); + CPU.APU_APUExecuting = FALSE; + pIAPU->PC++; +} + +void ApuFF () +{ +// STOP + // STOP ("STOP"); + CPU.APU_APUExecuting = FALSE; + pIAPU->PC++; +} + +void Apu10 () +{ +// BPL + Relative (); + if (!APUCheckNegative ()) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + APUShutdown (); + } + else + pIAPU->PC += 2; +} + +void Apu30 () +{ +// BMI + Relative (); + if (APUCheckNegative ()) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + APUShutdown (); + } + else + pIAPU->PC += 2; +} + +void Apu90 () +{ +// BCC + Relative (); + if (!APUCheckCarry ()) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + APUShutdown (); + } + else + pIAPU->PC += 2; +} + +void ApuB0 () +{ +// BCS + Relative (); + if (APUCheckCarry ()) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + APUShutdown (); + } + else + pIAPU->PC += 2; +} + +void ApuD0 () +{ +// BNE + Relative (); + if (!APUCheckZero ()) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + APUShutdown (); + } + else + pIAPU->PC += 2; +} + +void ApuF0 () +{ +// BEQ + Relative (); + if (APUCheckZero ()) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + APUShutdown (); + } + else + pIAPU->PC += 2; +} + +void Apu50 () +{ +// BVC + Relative (); + if (!APUCheckOverflow ()) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + } + else + pIAPU->PC += 2; +} + +void Apu70 () +{ +// BVS + Relative (); + if (APUCheckOverflow ()) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + } + else + pIAPU->PC += 2; +} + +void Apu2F () +{ +// BRA + Relative (); + pIAPU->PC = pIAPU->RAM + (uint16) Int16; +} + +void Apu80 () +{ +// SETC + APUSetCarry (); + pIAPU->PC++; +} + +void ApuED () +{ +// NOTC + pIAPU->_Carry ^= 1; + pIAPU->PC++; +} + +void Apu40 () +{ +// SETP + APUSetDirectPage (); + pIAPU->DirectPage = pIAPU->RAM + 0x100; + pIAPU->PC++; +} + +void Apu1A () +{ +// DECW dp + Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + Work16--; + S9xAPUSetByteZ ((uint8) Work16, OP1); + S9xAPUSetByteZ (Work16 >> 8, OP1 + 1); + APUSetZN16 (Work16); + pIAPU->PC += 2; +} + +void Apu5A () +{ +// CMPW YA,dp + Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + Int32 = (long) pIAPU->YA.W - (long) Work16; + pIAPU->_Carry = Int32 >= 0; + APUSetZN16 ((uint16) Int32); + pIAPU->PC += 2; +} + +void Apu3A () +{ +// INCW dp + Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + Work16++; + S9xAPUSetByteZ ((uint8) Work16, OP1); + S9xAPUSetByteZ (Work16 >> 8, OP1 + 1); + APUSetZN16 (Work16); + pIAPU->PC += 2; +} + +// XXX: HalfCarry - BJ Fixed? Or is it between bits 7 and 8 for ADDW/SUBW? +void Apu7A () +{ +// ADDW YA,dp + Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + Work32 = (uint32) pIAPU->YA.W + Work16; + pIAPU->_Carry = Work32 >= 0x10000; + if (~(pIAPU->YA.W ^ Work16) & (Work16 ^ (uint16) Work32) & 0x8000) + APUSetOverflow (); + else + APUClearOverflow (); + APUClearHalfCarry (); + if((pIAPU->YA.W ^ Work16 ^ (uint16) Work32) & 0x10) + APUSetHalfCarry (); + pIAPU->YA.W = (uint16) Work32; + APUSetZN16 (pIAPU->YA.W); + pIAPU->PC += 2; +} + +// XXX: BJ: i think the old HalfCarry behavior was wrong... +// XXX: Or is it between bits 7 and 8 for ADDW/SUBW? +void Apu9A () +{ +// SUBW YA,dp + Work16 = S9xAPUGetByteZ (OP1) + (S9xAPUGetByteZ (OP1 + 1) << 8); + Int32 = (long) pIAPU->YA.W - (long) Work16; + APUClearHalfCarry (); + pIAPU->_Carry = Int32 >= 0; + if (((pIAPU->YA.W ^ Work16) & 0x8000) && + ((pIAPU->YA.W ^ (uint16) Int32) & 0x8000)) + APUSetOverflow (); + else + APUClearOverflow (); +// if (((pIAPU->YA.W ^ Work16) & 0x0080) && +// ((pIAPU->YA.W ^ (uint16) Int32) & 0x0080)) +// APUSetHalfCarry (); // notaz: strange here + APUSetHalfCarry (); +// if((pIAPU->YA.W ^ Work16 ^ (uint16) Work32) & 0x10) // notaz: Work32?! + if((pIAPU->YA.W ^ Work16 ^ (uint16) Int32) & 0x10) + APUClearHalfCarry (); + pIAPU->YA.W = (uint16) Int32; + APUSetZN16 (pIAPU->YA.W); + pIAPU->PC += 2; +} + +void ApuBA () +{ +// MOVW YA,dp + pIAPU->YA.B.A = S9xAPUGetByteZ (OP1); + pIAPU->YA.B.Y = S9xAPUGetByteZ (OP1 + 1); + APUSetZN16 (pIAPU->YA.W); + pIAPU->PC += 2; +} + +void ApuDA () +{ +// MOVW dp,YA + S9xAPUSetByteZ (pIAPU->YA.B.A, OP1); + S9xAPUSetByteZ (pIAPU->YA.B.Y, OP1 + 1); + pIAPU->PC += 2; +} + +void Apu64 () +{ +// CMP A,dp + Work8 = S9xAPUGetByteZ (OP1); + CMP (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu65 () +{ +// CMP A,abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + CMP (pIAPU->YA.B.A, Work8); + pIAPU->PC += 3; +} + +void Apu66 () +{ +// CMP A,(X) + Work8 = S9xAPUGetByteZ (pIAPU->X); + CMP (pIAPU->YA.B.A, Work8); + pIAPU->PC++; +} + +void Apu67 () +{ +// CMP A,(dp+X) + IndexedXIndirect (); + Work8 = S9xAPUGetByte (pIAPU->Address); + CMP (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu68 () +{ +// CMP A,#00 + Work8 = OP1; + CMP (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu69 () +{ +// CMP dp(dest), dp(src) + W1 = S9xAPUGetByteZ (OP1); + Work8 = S9xAPUGetByteZ (OP2); + CMP (Work8, W1); + pIAPU->PC += 3; +} + +void Apu74 () +{ +// CMP A, dp+X + Work8 = S9xAPUGetByteZ (OP1 + pIAPU->X); + CMP (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu75 () +{ +// CMP A,abs+X + AbsoluteX (); + Work8 = S9xAPUGetByte (pIAPU->Address); + CMP (pIAPU->YA.B.A, Work8); + pIAPU->PC += 3; +} + +void Apu76 () +{ +// CMP A, abs+Y + AbsoluteY (); + Work8 = S9xAPUGetByte (pIAPU->Address); + CMP (pIAPU->YA.B.A, Work8); + pIAPU->PC += 3; +} + +void Apu77 () +{ +// CMP A,(dp)+Y + IndirectIndexedY (); + Work8 = S9xAPUGetByte (pIAPU->Address); + CMP (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu78 () +{ +// CMP dp,#00 + Work8 = OP1; + W1 = S9xAPUGetByteZ (OP2); + CMP (W1, Work8); + pIAPU->PC += 3; +} + +void Apu79 () +{ +// CMP (X),(Y) + W1 = S9xAPUGetByteZ (pIAPU->X); + Work8 = S9xAPUGetByteZ (pIAPU->YA.B.Y); + CMP (W1, Work8); + pIAPU->PC++; +} + +void Apu1E () +{ +// CMP X,abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + CMP (pIAPU->X, Work8); + pIAPU->PC += 3; +} + +void Apu3E () +{ +// CMP X,dp + Work8 = S9xAPUGetByteZ (OP1); + CMP (pIAPU->X, Work8); + pIAPU->PC += 2; +} + +void ApuC8 () +{ +// CMP X,#00 + CMP (pIAPU->X, OP1); + pIAPU->PC += 2; +} + +void Apu5E () +{ +// CMP Y,abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + CMP (pIAPU->YA.B.Y, Work8); + pIAPU->PC += 3; +} + +void Apu7E () +{ +// CMP Y,dp + Work8 = S9xAPUGetByteZ (OP1); + CMP (pIAPU->YA.B.Y, Work8); + pIAPU->PC += 2; +} + +void ApuAD () +{ +// CMP Y,#00 + Work8 = OP1; + CMP (pIAPU->YA.B.Y, Work8); + pIAPU->PC += 2; +} + +void Apu1F () +{ +// JMP (abs+X) + Absolute (); + pIAPU->PC = pIAPU->RAM + S9xAPUGetByte (pIAPU->Address + pIAPU->X) + + (S9xAPUGetByte (pIAPU->Address + pIAPU->X + 1) << 8); +// XXX: HERE: + // APU.Flags |= TRACE_FLAG; +} + +void Apu5F () +{ +// JMP abs + Absolute (); + pIAPU->PC = pIAPU->RAM + pIAPU->Address; +} + +void Apu20 () +{ +// CLRP + APUClearDirectPage (); + pIAPU->DirectPage = pIAPU->RAM; + pIAPU->PC++; +} + +void Apu60 () +{ +// CLRC + APUClearCarry (); + pIAPU->PC++; +} + +void ApuE0 () +{ +// CLRV + APUClearHalfCarry (); + APUClearOverflow (); + pIAPU->PC++; +} + +void Apu24 () +{ +// AND A,dp + pIAPU->YA.B.A &= S9xAPUGetByteZ (OP1); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu25 () +{ +// AND A,abs + Absolute (); + pIAPU->YA.B.A &= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void Apu26 () +{ +// AND A,(X) + pIAPU->YA.B.A &= S9xAPUGetByteZ (pIAPU->X); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu27 () +{ +// AND A,(dp+X) + IndexedXIndirect (); + pIAPU->YA.B.A &= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu28 () +{ +// AND A,#00 + pIAPU->YA.B.A &= OP1; + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu29 () +{ +// AND dp(dest),dp(src) + Work8 = S9xAPUGetByteZ (OP1); + Work8 &= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + pIAPU->PC += 3; +} + +void Apu34 () +{ +// AND A,dp+X + pIAPU->YA.B.A &= S9xAPUGetByteZ (OP1 + pIAPU->X); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu35 () +{ +// AND A,abs+X + AbsoluteX (); + pIAPU->YA.B.A &= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void Apu36 () +{ +// AND A,abs+Y + AbsoluteY (); + pIAPU->YA.B.A &= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void Apu37 () +{ +// AND A,(dp)+Y + IndirectIndexedY (); + pIAPU->YA.B.A &= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu38 () +{ +// AND dp,#00 + Work8 = OP1; + Work8 &= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + pIAPU->PC += 3; +} + +void Apu39 () +{ +// AND (X),(Y) + Work8 = S9xAPUGetByteZ (pIAPU->X) & S9xAPUGetByteZ (pIAPU->YA.B.Y); + APUSetZN8 (Work8); + S9xAPUSetByteZ (Work8, pIAPU->X); + pIAPU->PC++; +} + +void Apu2B () +{ +// ROL dp + Work8 = S9xAPUGetByteZ (OP1); + ROL (Work8); + S9xAPUSetByteZ (Work8, OP1); + pIAPU->PC += 2; +} + +void Apu2C () +{ +// ROL abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + ROL (Work8); + S9xAPUSetByte (Work8, pIAPU->Address); + pIAPU->PC += 3; +} + +void Apu3B () +{ +// ROL dp+X + Work8 = S9xAPUGetByteZ (OP1 + pIAPU->X); + ROL (Work8); + S9xAPUSetByteZ (Work8, OP1 + pIAPU->X); + pIAPU->PC += 2; +} + +void Apu3C () +{ +// ROL A + ROL (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu2E () +{ +// CBNE dp,rel + Work8 = OP1; + Relative2 (); + + if (S9xAPUGetByteZ (Work8) != pIAPU->YA.B.A) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + APUShutdown (); + } + else + pIAPU->PC += 3; +} + +void ApuDE () +{ +// CBNE dp+X,rel + Work8 = OP1 + pIAPU->X; + Relative2 (); + + if (S9xAPUGetByteZ (Work8) != pIAPU->YA.B.A) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + APUShutdown (); + } + else + pIAPU->PC += 3; +} + +void Apu3D () +{ +// INC X + pIAPU->X++; + APUSetZN8 (pIAPU->X); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC++; +} + +void ApuFC () +{ +// INC Y + pIAPU->YA.B.Y++; + APUSetZN8 (pIAPU->YA.B.Y); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC++; +} + +void Apu1D () +{ +// DEC X + pIAPU->X--; + APUSetZN8 (pIAPU->X); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC++; +} + +void ApuDC () +{ +// DEC Y + pIAPU->YA.B.Y--; + APUSetZN8 (pIAPU->YA.B.Y); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC++; +} + +void ApuAB () +{ +// INC dp + Work8 = S9xAPUGetByteZ (OP1) + 1; + S9xAPUSetByteZ (Work8, OP1); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC += 2; +} + +void ApuAC () +{ +// INC abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address) + 1; + S9xAPUSetByte (Work8, pIAPU->Address); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC += 3; +} + +void ApuBB () +{ +// INC dp+X + Work8 = S9xAPUGetByteZ (OP1 + pIAPU->X) + 1; + S9xAPUSetByteZ (Work8, OP1 + pIAPU->X); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC += 2; +} + +void ApuBC () +{ +// INC A + pIAPU->YA.B.A++; + APUSetZN8 (pIAPU->YA.B.A); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC++; +} + +void Apu8B () +{ +// DEC dp + Work8 = S9xAPUGetByteZ (OP1) - 1; + S9xAPUSetByteZ (Work8, OP1); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC += 2; +} + +void Apu8C () +{ +// DEC abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address) - 1; + S9xAPUSetByte (Work8, pIAPU->Address); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC += 3; +} + +void Apu9B () +{ +// DEC dp+X + Work8 = S9xAPUGetByteZ (OP1 + pIAPU->X) - 1; + S9xAPUSetByteZ (Work8, OP1 + pIAPU->X); + APUSetZN8 (Work8); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC += 2; +} + +void Apu9C () +{ +// DEC A + pIAPU->YA.B.A--; + APUSetZN8 (pIAPU->YA.B.A); + +#ifdef SPC700_SHUTDOWN + pIAPU->WaitCounter++; +#endif + + pIAPU->PC++; +} + +void Apu44 () +{ +// EOR A,dp + pIAPU->YA.B.A ^= S9xAPUGetByteZ (OP1); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu45 () +{ +// EOR A,abs + Absolute (); + pIAPU->YA.B.A ^= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void Apu46 () +{ +// EOR A,(X) + pIAPU->YA.B.A ^= S9xAPUGetByteZ (pIAPU->X); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu47 () +{ +// EOR A,(dp+X) + IndexedXIndirect (); + pIAPU->YA.B.A ^= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu48 () +{ +// EOR A,#00 + pIAPU->YA.B.A ^= OP1; + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu49 () +{ +// EOR dp(dest),dp(src) + Work8 = S9xAPUGetByteZ (OP1); + Work8 ^= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + pIAPU->PC += 3; +} + +void Apu54 () +{ +// EOR A,dp+X + pIAPU->YA.B.A ^= S9xAPUGetByteZ (OP1 + pIAPU->X); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu55 () +{ +// EOR A,abs+X + AbsoluteX (); + pIAPU->YA.B.A ^= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void Apu56 () +{ +// EOR A,abs+Y + AbsoluteY (); + pIAPU->YA.B.A ^= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void Apu57 () +{ +// EOR A,(dp)+Y + IndirectIndexedY (); + pIAPU->YA.B.A ^= S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void Apu58 () +{ +// EOR dp,#00 + Work8 = OP1; + Work8 ^= S9xAPUGetByteZ (OP2); + S9xAPUSetByteZ (Work8, OP2); + APUSetZN8 (Work8); + pIAPU->PC += 3; +} + +void Apu59 () +{ +// EOR (X),(Y) + Work8 = S9xAPUGetByteZ (pIAPU->X) ^ S9xAPUGetByteZ (pIAPU->YA.B.Y); + APUSetZN8 (Work8); + S9xAPUSetByteZ (Work8, pIAPU->X); + pIAPU->PC++; +} + +void Apu4B () +{ +// LSR dp + Work8 = S9xAPUGetByteZ (OP1); + LSR (Work8); + S9xAPUSetByteZ (Work8, OP1); + pIAPU->PC += 2; +} + +void Apu4C () +{ +// LSR abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + LSR (Work8); + S9xAPUSetByte (Work8, pIAPU->Address); + pIAPU->PC += 3; +} + +void Apu5B () +{ +// LSR dp+X + Work8 = S9xAPUGetByteZ (OP1 + pIAPU->X); + LSR (Work8); + S9xAPUSetByteZ (Work8, OP1 + pIAPU->X); + pIAPU->PC += 2; +} + +void Apu5C () +{ +// LSR A + LSR (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu7D () +{ +// MOV A,X + pIAPU->YA.B.A = pIAPU->X; + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void ApuDD () +{ +// MOV A,Y + pIAPU->YA.B.A = pIAPU->YA.B.Y; + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu5D () +{ +// MOV X,A + pIAPU->X = pIAPU->YA.B.A; + APUSetZN8 (pIAPU->X); + pIAPU->PC++; +} + +void ApuFD () +{ +// MOV Y,A + pIAPU->YA.B.Y = pIAPU->YA.B.A; + APUSetZN8 (pIAPU->YA.B.Y); + pIAPU->PC++; +} + +void Apu9D () +{ +//MOV X,SP + pIAPU->X = pIAPU->S; + APUSetZN8 (pIAPU->X); + pIAPU->PC++; +} + +void ApuBD () +{ +// MOV SP,X + pIAPU->S = pIAPU->X; + pIAPU->PC++; +} + +void Apu6B () +{ +// ROR dp + Work8 = S9xAPUGetByteZ (OP1); + ROR (Work8); + S9xAPUSetByteZ (Work8, OP1); + pIAPU->PC += 2; +} + +void Apu6C () +{ +// ROR abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + ROR (Work8); + S9xAPUSetByte (Work8, pIAPU->Address); + pIAPU->PC += 3; +} + +void Apu7B () +{ +// ROR dp+X + Work8 = S9xAPUGetByteZ (OP1 + pIAPU->X); + ROR (Work8); + S9xAPUSetByteZ (Work8, OP1 + pIAPU->X); + pIAPU->PC += 2; +} + +void Apu7C () +{ +// ROR A + ROR (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu6E () +{ +// DBNZ dp,rel + Work8 = OP1; + Relative2 (); + W1 = S9xAPUGetByteZ (Work8) - 1; + S9xAPUSetByteZ (W1, Work8); + if (W1 != 0) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + } + else + pIAPU->PC += 3; +} + +void ApuFE () +{ +// DBNZ Y,rel + Relative (); + pIAPU->YA.B.Y--; + if (pIAPU->YA.B.Y != 0) + { + pIAPU->PC = pIAPU->RAM + (uint16) Int16; + CPU.APU_Cycles += pIAPU->TwoCycles; + } + else + pIAPU->PC += 2; +} + +void Apu6F () +{ +// RET + PopW (Work16); + pIAPU->PC = pIAPU->RAM + Work16; +} + +void Apu7F () +{ +// RETI + // STOP ("RETI"); + Pop (pIAPU->P); + S9xAPUUnpackStatus (); + PopW (Work16); + pIAPU->PC = pIAPU->RAM + Work16; +} + +void Apu84 () +{ +// ADC A,dp + Work8 = S9xAPUGetByteZ (OP1); + ADC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu85 () +{ +// ADC A, abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + ADC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 3; +} + +void Apu86 () +{ +// ADC A,(X) + Work8 = S9xAPUGetByteZ (pIAPU->X); + ADC (pIAPU->YA.B.A, Work8); + pIAPU->PC++; +} + +void Apu87 () +{ +// ADC A,(dp+X) + IndexedXIndirect (); + Work8 = S9xAPUGetByte (pIAPU->Address); + ADC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu88 () +{ +// ADC A,#00 + Work8 = OP1; + ADC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu89 () +{ +// ADC dp(dest),dp(src) + Work8 = S9xAPUGetByteZ (OP1); + W1 = S9xAPUGetByteZ (OP2); + ADC (W1, Work8); + S9xAPUSetByteZ (W1, OP2); + pIAPU->PC += 3; +} + +void Apu94 () +{ +// ADC A,dp+X + Work8 = S9xAPUGetByteZ (OP1 + pIAPU->X); + ADC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu95 () +{ +// ADC A, abs+X + AbsoluteX (); + Work8 = S9xAPUGetByte (pIAPU->Address); + ADC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 3; +} + +void Apu96 () +{ +// ADC A, abs+Y + AbsoluteY (); + Work8 = S9xAPUGetByte (pIAPU->Address); + ADC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 3; +} + +void Apu97 () +{ +// ADC A, (dp)+Y + IndirectIndexedY (); + Work8 = S9xAPUGetByte (pIAPU->Address); + ADC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void Apu98 () +{ +// ADC dp,#00 + Work8 = OP1; + W1 = S9xAPUGetByteZ (OP2); + ADC (W1, Work8); + S9xAPUSetByteZ (W1, OP2); + pIAPU->PC += 3; +} + +void Apu99 () +{ +// ADC (X),(Y) + W1 = S9xAPUGetByteZ (pIAPU->X); + Work8 = S9xAPUGetByteZ (pIAPU->YA.B.Y); + ADC (W1, Work8); + S9xAPUSetByteZ (W1, pIAPU->X); + pIAPU->PC++; +} + +void Apu8D () +{ +// MOV Y,#00 + pIAPU->YA.B.Y = OP1; + APUSetZN8 (pIAPU->YA.B.Y); + pIAPU->PC += 2; +} + +void Apu8F () +{ +// MOV dp,#00 + Work8 = OP1; + S9xAPUSetByteZ (Work8, OP2); + pIAPU->PC += 3; +} + +void Apu9E () +{ +// DIV YA,X + if (pIAPU->X == 0) + { + APUSetOverflow (); + pIAPU->YA.B.Y = 0xff; + pIAPU->YA.B.A = 0xff; + } + else + { + APUClearOverflow (); + Work8 = pIAPU->YA.W / pIAPU->X; + pIAPU->YA.B.Y = pIAPU->YA.W % pIAPU->X; + pIAPU->YA.B.A = Work8; + } +// XXX How should Overflow, Half Carry, Zero and Negative flags be set?? + // APUSetZN16 (pIAPU->YA.W); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void Apu9F () +{ +// XCN A + pIAPU->YA.B.A = (pIAPU->YA.B.A >> 4) | (pIAPU->YA.B.A << 4); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void ApuA4 () +{ +// SBC A, dp + Work8 = S9xAPUGetByteZ (OP1); + SBC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void ApuA5 () +{ +// SBC A, abs + Absolute (); + Work8 = S9xAPUGetByte (pIAPU->Address); + SBC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 3; +} + +void ApuA6 () +{ +// SBC A, (X) + Work8 = S9xAPUGetByteZ (pIAPU->X); + SBC (pIAPU->YA.B.A, Work8); + pIAPU->PC++; +} + +void ApuA7 () +{ +// SBC A,(dp+X) + IndexedXIndirect (); + Work8 = S9xAPUGetByte (pIAPU->Address); + SBC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void ApuA8 () +{ +// SBC A,#00 + Work8 = OP1; + SBC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void ApuA9 () +{ +// SBC dp(dest), dp(src) + Work8 = S9xAPUGetByteZ (OP1); + W1 = S9xAPUGetByteZ (OP2); + SBC (W1, Work8); + S9xAPUSetByteZ (W1, OP2); + pIAPU->PC += 3; +} + +void ApuB4 () +{ +// SBC A, dp+X + Work8 = S9xAPUGetByteZ (OP1 + pIAPU->X); + SBC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void ApuB5 () +{ +// SBC A,abs+X + AbsoluteX (); + Work8 = S9xAPUGetByte (pIAPU->Address); + SBC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 3; +} + +void ApuB6 () +{ +// SBC A,abs+Y + AbsoluteY (); + Work8 = S9xAPUGetByte (pIAPU->Address); + SBC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 3; +} + +void ApuB7 () +{ +// SBC A,(dp)+Y + IndirectIndexedY (); + Work8 = S9xAPUGetByte (pIAPU->Address); + SBC (pIAPU->YA.B.A, Work8); + pIAPU->PC += 2; +} + +void ApuB8 () +{ +// SBC dp,#00 + Work8 = OP1; + W1 = S9xAPUGetByteZ (OP2); + SBC (W1, Work8); + S9xAPUSetByteZ (W1, OP2); + pIAPU->PC += 3; +} + +void ApuB9 () +{ +// SBC (X),(Y) + W1 = S9xAPUGetByteZ (pIAPU->X); + Work8 = S9xAPUGetByteZ (pIAPU->YA.B.Y); + SBC (W1, Work8); + S9xAPUSetByteZ (W1, pIAPU->X); + pIAPU->PC++; +} + +void ApuAF () +{ +// MOV (X)+, A + S9xAPUSetByteZ (pIAPU->YA.B.A, pIAPU->X++); + pIAPU->PC++; +} + +void ApuBE () +{ +// DAS + if ((pIAPU->YA.B.A & 0x0f) > 9 || !APUCheckHalfCarry()) + { + pIAPU->YA.B.A -= 6; + } + if (pIAPU->YA.B.A > 0x9f || !pIAPU->_Carry) + { + pIAPU->YA.B.A -= 0x60; + APUClearCarry (); + } + else { APUSetCarry (); } + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void ApuBF () +{ +// MOV A,(X)+ + pIAPU->YA.B.A = S9xAPUGetByteZ (pIAPU->X++); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void ApuC0 () +{ +// DI + APUClearInterrupt (); + pIAPU->PC++; +} + +void ApuA0 () +{ +// EI + APUSetInterrupt (); + pIAPU->PC++; +} + +void ApuC4 () +{ +// MOV dp,A + S9xAPUSetByteZ (pIAPU->YA.B.A, OP1); + pIAPU->PC += 2; +} + +void ApuC5 () +{ +// MOV abs,A + Absolute (); + S9xAPUSetByte (pIAPU->YA.B.A, pIAPU->Address); + pIAPU->PC += 3; +} + +void ApuC6 () +{ +// MOV (X), A + S9xAPUSetByteZ (pIAPU->YA.B.A, pIAPU->X); + pIAPU->PC++; +} + +void ApuC7 () +{ +// MOV (dp+X),A + IndexedXIndirect (); + S9xAPUSetByte (pIAPU->YA.B.A, pIAPU->Address); + pIAPU->PC += 2; +} + +void ApuC9 () +{ +// MOV abs,X + Absolute (); + S9xAPUSetByte (pIAPU->X, pIAPU->Address); + pIAPU->PC += 3; +} + +void ApuCB () +{ +// MOV dp,Y + S9xAPUSetByteZ (pIAPU->YA.B.Y, OP1); + pIAPU->PC += 2; +} + +void ApuCC () +{ +// MOV abs,Y + Absolute (); + S9xAPUSetByte (pIAPU->YA.B.Y, pIAPU->Address); + pIAPU->PC += 3; +} + +void ApuCD () +{ +// MOV X,#00 + pIAPU->X = OP1; + APUSetZN8 (pIAPU->X); + pIAPU->PC += 2; +} + +void ApuCF () +{ +// MUL YA + pIAPU->YA.W = (uint16) pIAPU->YA.B.A * pIAPU->YA.B.Y; + APUSetZN16 (pIAPU->YA.W); + pIAPU->PC++; +} + +void ApuD4 () +{ +// MOV dp+X, A + S9xAPUSetByteZ (pIAPU->YA.B.A, OP1 + pIAPU->X); + pIAPU->PC += 2; +} + +void ApuD5 () +{ +// MOV abs+X,A + AbsoluteX (); + S9xAPUSetByte (pIAPU->YA.B.A, pIAPU->Address); + pIAPU->PC += 3; +} + +void ApuD6 () +{ +// MOV abs+Y,A + AbsoluteY (); + S9xAPUSetByte (pIAPU->YA.B.A, pIAPU->Address); + pIAPU->PC += 3; +} + +void ApuD7 () +{ +// MOV (dp)+Y,A + IndirectIndexedY (); + S9xAPUSetByte (pIAPU->YA.B.A, pIAPU->Address); + pIAPU->PC += 2; +} + +void ApuD8 () +{ +// MOV dp,X + S9xAPUSetByteZ (pIAPU->X, OP1); + pIAPU->PC += 2; +} + +void ApuD9 () +{ +// MOV dp+Y,X + S9xAPUSetByteZ (pIAPU->X, OP1 + pIAPU->YA.B.Y); + pIAPU->PC += 2; +} + +void ApuDB () +{ +// MOV dp+X,Y + S9xAPUSetByteZ (pIAPU->YA.B.Y, OP1 + pIAPU->X); + pIAPU->PC += 2; +} + +void ApuDF () +{ +// DAA + if ((pIAPU->YA.B.A & 0x0f) > 9 || APUCheckHalfCarry()) + { + if(pIAPU->YA.B.A > 0xf0) APUSetCarry (); + pIAPU->YA.B.A += 6; + //APUSetHalfCarry (); Intel procs do this, but this is a Sony proc... + } + //else { APUClearHalfCarry (); } ditto as above + if (pIAPU->YA.B.A > 0x9f || pIAPU->_Carry) + { + pIAPU->YA.B.A += 0x60; + APUSetCarry (); + } + else { APUClearCarry (); } + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void ApuE4 () +{ +// MOV A, dp + pIAPU->YA.B.A = S9xAPUGetByteZ (OP1); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void ApuE5 () +{ +// MOV A,abs + Absolute (); + pIAPU->YA.B.A = S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void ApuE6 () +{ +// MOV A,(X) + pIAPU->YA.B.A = S9xAPUGetByteZ (pIAPU->X); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC++; +} + +void ApuE7 () +{ +// MOV A,(dp+X) + IndexedXIndirect (); + pIAPU->YA.B.A = S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void ApuE8 () +{ +// MOV A,#00 + pIAPU->YA.B.A = OP1; + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void ApuE9 () +{ +// MOV X, abs + Absolute (); + pIAPU->X = S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->X); + pIAPU->PC += 3; +} + +void ApuEB () +{ +// MOV Y,dp + pIAPU->YA.B.Y = S9xAPUGetByteZ (OP1); + APUSetZN8 (pIAPU->YA.B.Y); + pIAPU->PC += 2; +} + +void ApuEC () +{ +// MOV Y,abs + Absolute (); + pIAPU->YA.B.Y = S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.Y); + pIAPU->PC += 3; +} + +void ApuF4 () +{ +// MOV A, dp+X + pIAPU->YA.B.A = S9xAPUGetByteZ (OP1 + pIAPU->X); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void ApuF5 () +{ +// MOV A, abs+X + AbsoluteX (); + pIAPU->YA.B.A = S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void ApuF6 () +{ +// MOV A, abs+Y + AbsoluteY (); + pIAPU->YA.B.A = S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 3; +} + +void ApuF7 () +{ +// MOV A, (dp)+Y + IndirectIndexedY (); + pIAPU->YA.B.A = S9xAPUGetByte (pIAPU->Address); + APUSetZN8 (pIAPU->YA.B.A); + pIAPU->PC += 2; +} + +void ApuF8 () +{ +// MOV X,dp + pIAPU->X = S9xAPUGetByteZ (OP1); + APUSetZN8 (pIAPU->X); + pIAPU->PC += 2; +} + +void ApuF9 () +{ +// MOV X,dp+Y + pIAPU->X = S9xAPUGetByteZ (OP1 + pIAPU->YA.B.Y); + APUSetZN8 (pIAPU->X); + pIAPU->PC += 2; +} + +void ApuFA () +{ +// MOV dp(dest),dp(src) + S9xAPUSetByteZ (S9xAPUGetByteZ (OP1), OP2); + pIAPU->PC += 3; +} + +void ApuFB () +{ +// MOV Y,dp+X + pIAPU->YA.B.Y = S9xAPUGetByteZ (OP1 + pIAPU->X); + APUSetZN8 (pIAPU->YA.B.Y); + pIAPU->PC += 2; +} + +//#if defined(ASM_SPC700) +#undef INLINE +#define INLINE extern "C" +#include "apumem.h" +/* +#elif defined(NO_INLINE_SET_GET) +#undef INLINE +#define INLINE +#include "apumem.h" +#endif +*/ + +void (*S9xApuOpcodes[256]) (void) = +{ + Apu00, Apu01, Apu02, Apu03, Apu04, Apu05, Apu06, Apu07, + Apu08, Apu09, Apu0A, Apu0B, Apu0C, Apu0D, Apu0E, Apu0F, + Apu10, Apu11, Apu12, Apu13, Apu14, Apu15, Apu16, Apu17, + Apu18, Apu19, Apu1A, Apu1B, Apu1C, Apu1D, Apu1E, Apu1F, + Apu20, Apu21, Apu22, Apu23, Apu24, Apu25, Apu26, Apu27, + Apu28, Apu29, Apu2A, Apu2B, Apu2C, Apu2D, Apu2E, Apu2F, + Apu30, Apu31, Apu32, Apu33, Apu34, Apu35, Apu36, Apu37, + Apu38, Apu39, Apu3A, Apu3B, Apu3C, Apu3D, Apu3E, Apu3F, + Apu40, Apu41, Apu42, Apu43, Apu44, Apu45, Apu46, Apu47, + Apu48, Apu49, Apu4A, Apu4B, Apu4C, Apu4D, Apu4E, Apu4F, + Apu50, Apu51, Apu52, Apu53, Apu54, Apu55, Apu56, Apu57, + Apu58, Apu59, Apu5A, Apu5B, Apu5C, Apu5D, Apu5E, Apu5F, + Apu60, Apu61, Apu62, Apu63, Apu64, Apu65, Apu66, Apu67, + Apu68, Apu69, Apu6A, Apu6B, Apu6C, Apu6D, Apu6E, Apu6F, + Apu70, Apu71, Apu72, Apu73, Apu74, Apu75, Apu76, Apu77, + Apu78, Apu79, Apu7A, Apu7B, Apu7C, Apu7D, Apu7E, Apu7F, + Apu80, Apu81, Apu82, Apu83, Apu84, Apu85, Apu86, Apu87, + Apu88, Apu89, Apu8A, Apu8B, Apu8C, Apu8D, Apu8E, Apu8F, + Apu90, Apu91, Apu92, Apu93, Apu94, Apu95, Apu96, Apu97, + Apu98, Apu99, Apu9A, Apu9B, Apu9C, Apu9D, Apu9E, Apu9F, + ApuA0, ApuA1, ApuA2, ApuA3, ApuA4, ApuA5, ApuA6, ApuA7, + ApuA8, ApuA9, ApuAA, ApuAB, ApuAC, ApuAD, ApuAE, ApuAF, + ApuB0, ApuB1, ApuB2, ApuB3, ApuB4, ApuB5, ApuB6, ApuB7, + ApuB8, ApuB9, ApuBA, ApuBB, ApuBC, ApuBD, ApuBE, ApuBF, + ApuC0, ApuC1, ApuC2, ApuC3, ApuC4, ApuC5, ApuC6, ApuC7, + ApuC8, ApuC9, ApuCA, ApuCB, ApuCC, ApuCD, ApuCE, ApuCF, + ApuD0, ApuD1, ApuD2, ApuD3, ApuD4, ApuD5, ApuD6, ApuD7, + ApuD8, ApuD9, ApuDA, ApuDB, ApuDC, ApuDD, ApuDE, ApuDF, + ApuE0, ApuE1, ApuE2, ApuE3, ApuE4, ApuE5, ApuE6, ApuE7, + ApuE8, ApuE9, ApuEA, ApuEB, ApuEC, ApuED, ApuEE, ApuEF, + ApuF0, ApuF1, ApuF2, ApuF3, ApuF4, ApuF5, ApuF6, ApuF7, + ApuF8, ApuF9, ApuFA, ApuFB, ApuFC, ApuFD, ApuFE, ApuFF +}; + + +struct SIAPU IAPU2; +struct SIAPU *pIAPU; + +void APUCompare() +{ + IAPU.icount++; + + if(IAPU.PC != IAPU2.PC) { + dprintf("!%02X %5i PC %08X vs %08X", IAPU.opcode, IAPU.icount, IAPU.PC, IAPU2.PC); + exit(1); + } + + if(IAPU.YA.W != IAPU2.YA.W) { + dprintf("!%02X %5i YA %04X vs %04X", IAPU.opcode, IAPU.icount, IAPU.YA.W, IAPU2.YA.W); + dprintf(" (%04X / %02X)", IAPU.ya_prev, IAPU.x_prev); + exit(1); + } + + if((IAPU.P&0x7d) != (IAPU2.P&0x7d)) { + dprintf("!%02X %5i P %02X vs %02X", IAPU.opcode, IAPU.icount, IAPU.P, IAPU2.P); + exit(1); + } + + if(IAPU.X != IAPU2.X) { + dprintf("!%02X %5i X %02X vs %02X", IAPU.opcode, IAPU.icount, IAPU.X, IAPU2.X); + exit(1); + } + + if(IAPU.S != IAPU2.S) { + dprintf("!%02X %5i S %02X vs %02X", IAPU.opcode, IAPU.icount, IAPU.S, IAPU2.S); + exit(1); + } + + if((IAPU._Zero == 0) != (IAPU2._Zero == 0)) { + dprintf("!%02X %5i _Zero %02X vs %02X", IAPU.opcode, IAPU.icount, IAPU._Zero, IAPU2._Zero); + exit(1); + } + + if((IAPU._Zero & 0x80) != (IAPU2._Zero & 0x80)) { + dprintf("!%02X %5i _Zero(n) %02X vs %02X", IAPU.opcode, IAPU.icount, IAPU._Zero, IAPU2._Zero); + exit(1); + } + + if(IAPU.memread_addr != IAPU2.memread_addr) { + dprintf("!%02X %5i memread_addr %04X vs %04X", IAPU.opcode, IAPU.icount, IAPU.memread_addr, IAPU2.memread_addr); + exit(1); + } + + if(IAPU.memread_data != IAPU2.memread_data) { + dprintf("!%02X %5i memread_data %02X@%04X vs %02X@%04X", IAPU.opcode, IAPU.icount, IAPU.memread_data, IAPU.memread_addr, IAPU2.memread_data, IAPU2.memread_addr); + exit(1); + } + + if(IAPU.memwrite_addr != IAPU2.memwrite_addr) { + dprintf("!%02X %5i memwrite_addr %04X vs %04X", IAPU.opcode, IAPU.icount, IAPU.memwrite_addr, IAPU2.memwrite_addr); + exit(1); + } + + if(IAPU.memwrite_data != IAPU2.memwrite_data) { + dprintf("!%02X %5i memwrite_data %02X@%04X vs %02X@%04X", IAPU.opcode, IAPU.icount, IAPU.memwrite_data, IAPU.memwrite_addr, IAPU2.memwrite_data, IAPU2.memwrite_addr); + exit(1); + } +} + + diff --git a/src/spc700/debug/spc700.h b/src/spc700/debug/spc700.h new file mode 100644 index 0000000..507c247 --- /dev/null +++ b/src/spc700/debug/spc700.h @@ -0,0 +1,172 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _SPC700_H_ +#define _SPC700_H_ + +#ifdef SPCTOOL +#define NO_CHANNEL_STRUCT +#include "spctool/dsp.h" +#include "spctool/spc700.h" +#include "spctool/soundmod.h" +#endif + + +#define Carry 1 +#define Zero 2 +#define Interrupt 4 +#define HalfCarry 8 +#define BreakFlag 16 +#define DirectPageFlag 32 +#define Overflow 64 +#define Negative 128 + +#define APUClearCarry() (pIAPU->_Carry = 0) +#define APUSetCarry() (pIAPU->_Carry = 1) +#define APUSetInterrupt() (pIAPU->P |= Interrupt) +#define APUClearInterrupt() (pIAPU->P &= ~Interrupt) +#define APUSetHalfCarry() (pIAPU->P |= HalfCarry) +#define APUClearHalfCarry() (pIAPU->P &= ~HalfCarry) +#define APUSetBreak() (pIAPU->P |= BreakFlag) +#define APUClearBreak() (pIAPU->P &= ~BreakFlag) +#define APUSetDirectPage() (pIAPU->P |= DirectPageFlag) +#define APUClearDirectPage() (pIAPU->P &= ~DirectPageFlag) +#define APUSetOverflow() (pIAPU->_Overflow = 1) +#define APUClearOverflow() (pIAPU->_Overflow = 0) + +#define APUCheckZero() (pIAPU->_Zero == 0) +#define APUCheckCarry() (pIAPU->_Carry) +#define APUCheckInterrupt() (pIAPU->P & Interrupt) +#define APUCheckHalfCarry() (pIAPU->P & HalfCarry) +#define APUCheckBreak() (pIAPU->P & BreakFlag) +#define APUCheckDirectPage() (pIAPU->P & DirectPageFlag) +#define APUCheckOverflow() (pIAPU->_Overflow) +#define APUCheckNegative() (pIAPU->_Zero & 0x80) + +//#define APUClearFlags(f) (IAPU.P &= ~(f)) +//#define APUSetFlags(f) (IAPU.P |= (f)) +//#define APUCheckFlag(f) (IAPU.P & (f)) + +typedef union +{ +#ifdef LSB_FIRST + struct { uint8 A, Y; } B; +#else + struct { uint8 Y, A; } B; +#endif + uint16 W; + uint32 _padder; // make sure this whole thing takes 4 bytes +} YAndA; + +struct SAPURegisters{ + uint8 P; + YAndA YA; + uint8 X; + uint8 S; + uint16 PC; +}; + +//EXTERN_C struct SAPURegisters APURegisters; + +// Needed by ILLUSION OF GAIA +//#define ONE_APU_CYCLE 14 +#define ONE_APU_CYCLE 21 + +// Needed by all games written by the software company called Human +//#define ONE_APU_CYCLE_HUMAN 17 +#define ONE_APU_CYCLE_HUMAN 21 + +// 1.953us := 1.024065.54MHz + +// return cycles left (always negative) +extern "C" int spc700_execute(int cycles); +extern "C" uint32 Spc700JumpTab; + +#ifdef SPCTOOL +EXTERN_C int32 ESPC (int32); + +#define APU_EXECUTE() \ +{ \ + int32 l = (CPU.Cycles - CPU.APU_Cycles) / 14; \ + if (l > 0) \ + { \ + l -= _EmuSPC(l); \ + CPU.APU_Cycles += l * 14; \ + } \ +} + +#else + +#ifdef DEBUGGER +#define APU_EXECUTE1() \ +{ \ + if (APU.Flags & TRACE_FLAG) \ + S9xTraceAPU ();\ + CPU.APU_Cycles += S9xAPUCycles [*IAPU.PC]; \ + (*S9xApuOpcodes[*IAPU.PC]) (); \ +} +#else +#define APU_EXECUTE1() \ +{ \ + IAPU.asmJumpTab = &Spc700JumpTab; \ + memcpy(&IAPU2, &IAPU, sizeof(IAPU)); \ + CPU.APU_Cycles += S9xAPUCycles [*IAPU.PC]; \ + IAPU.opcode = *IAPU.PC; \ + pIAPU = &IAPU; \ + (*S9xApuOpcodes[*IAPU.PC]) (); \ + if(IAPU._Carry) IAPU.P |= Carry; else IAPU.P &= ~Carry; \ + if(IAPU._Overflow) IAPU.P |= Overflow; else IAPU.P &= ~Overflow; \ + pIAPU = &IAPU2; \ + spc700_execute(0); \ + APUCompare(); \ + IAPU.ya_prev = IAPU.YA.W; \ + IAPU.x_prev = IAPU.X; \ +} +#endif + +#define APU_EXECUTE(mode) \ +if (CPU.APU_APUExecuting == mode) \ +{\ + while (CPU.APU_Cycles <= CPU.Cycles) \ + APU_EXECUTE1(); \ +} +#endif + +#endif diff --git a/src/spc700/spcgen.c b/src/spc700/spcgen.c new file mode 100644 index 0000000..5a15bd7 --- /dev/null +++ b/src/spc700/spcgen.c @@ -0,0 +1,2164 @@ +// notaz's SPC700 Emulator +// (c) Copyright 2006 notaz, All rights reserved. +// +// Added some modifications by Bitrider 2010-2011. +// +// this is a rewrite of spc700.cpp in ARM asm, inspired by other asm CPU cores like +// Cyclone and DrZ80. It is meant to be used in Snes9x emulator ports for ARM platforms. +// +// notes: +// "Shutdown" mechanism is not supported, so undefine SPC700_SHUTDOWN in your port.h +// code branches backwards over start of memory are not supported +// (never seen any game doing that) +// +// license: +// the code is released under Snes9x license. It would be nice if the word "notaz" +// would appear somewhere in your documentation or your program's "about" screen +// if you use this :) + +/* + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +int one_apu_cycle[] = {13, 14, 15, 21}; +int current_cycles; + + +// settings +#define VERSION "0.12" +#define APU_EXECUTING_OFF 124 +//#define SPC_DEBUG + + +// includes +#include +#include +#include +#include + + +// timings +int S9xAPUCycles [256] = +{ + /* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f, */ + /* 00 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 5, 4, 5, 4, 6, 8, + /* 10 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 6, 5, 2, 2, 4, 6, + /* 20 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 5, 4, 5, 4, 5, 4, + /* 30 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 6, 5, 2, 2, 3, 8, + /* 40 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 4, 4, 5, 4, 6, 6, + /* 50 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 4, 5, 2, 2, 4, 3, + /* 60 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 4, 4, 5, 4, 5, 5, + /* 70 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 5, 5, 2, 2, 3, 6, + /* 80 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 6, 5, 4, 5, 2, 4, 5, + /* 90 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 5, 5, 2, 2,12, 5, + /* a0 */ 3, 8, 4, 5, 3, 4, 3, 6, 2, 6, 4, 4, 5, 2, 4, 4, + /* b0 */ 2, 8, 4, 5, 4, 5, 5, 6, 5, 5, 5, 5, 2, 2, 3, 4, + /* c0 */ 3, 8, 4, 5, 4, 5, 4, 7, 2, 5, 6, 4, 5, 2, 4, 9, + /* d0 */ 2, 8, 4, 5, 5, 6, 6, 7, 4, 5, 4, 5, 2, 2, 6, 3, + /* e0 */ 2, 8, 4, 5, 3, 4, 3, 6, 2, 4, 5, 3, 4, 3, 4, 3, + /* f0 */ 2, 8, 4, 5, 4, 5, 5, 6, 3, 4, 5, 4, 2, 2, 4, 3 +}; + + +// stuff +static FILE *AsmFile=NULL; +static int opcode=0; // 0-0xff +static int ibuffer = 0; +static char buff[1024]; + + +void ot(char *format, ...) +{ + va_list valist=NULL; + int i, len; + + // notaz: stop me from leaving newlines in the middle of format string + // and generating bad code + for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++); + if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format); + + va_start(valist,format); + if (AsmFile) vfprintf(AsmFile,format,valist); + va_end(valist); +} + +// ot buffered +void otb(char *format, ...) +{ + va_list valist=NULL; + int i, len; + + // notaz: stop me from leaving newlines in the middle of format string + // and generating bad code + for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++); + if(i < len-1 && format[len-1] != '\n') printf(buff, "\nWARNING: possible improper newline placement:\n%s\n", format); + + va_start(valist,format); + if (AsmFile) vsprintf(buff,format,valist); + ibuffer = 1; + va_end(valist); +} + +void flush_buffer() { + if (ibuffer != 0) { + ot(buff); + ibuffer = 0; + } +} + +// trashes: r0, r1, r2 +// return: r0 +// exit at label "2" +static void GetAPUDSP() { + ot("GetAPUDSP: \n"); + ot(" ldrb r1, [spc_ram, #0xf2] \n"); + // r1 = IAPU.RAM [0xf2] + + ot(" mov r0, #0\n"); + ot(" and r2, r1, #0X0f \n"); + // switch (reg & 0xf) { + ot(" cmp r2, #0x08\n"); + ot(" bxeq lr\n"); // APU_ENVX = 8 + // r1 = IAPU.RAM [0xf2] & 0x7f; + + ot(" cmp r2, #0x09\n"); + // return APU.DSP [reg]; + ot(" ldrne r2, .APU_DSP\n"); + ot(" and r1, r1, #0X7f \n"); // r1 = IAPU.RAM[0xf2] & 0x7f + ot(" ldrneb r0, [r2, r1] \n"); + ot(" bxne lr \n"); + + // APU_OUTX = 9 + // if (SoundData.channels [reg >> 4].state == SOUND_SILENT) return 0; + // return ((SoundData.channels [reg >> 4].sample >> 8) | (SoundData.channels [reg >> 4].sample & 0x + ot(" ldr r2, .SOUNDDATA_CHANNELS\n"); + ot(" mov r1, r1, lsr #4 \n"); + //ot(" add r1, r2, r1, asl #8\n"); + //ot(" ldr r0, [r1, #0x0] \n"); // r0 = SoundData.channels[reg >> 4].state + ot(" ldr r0, [r2, r1, asl #8] \n"); + ot(" add r1, r2, r1, asl #8\n"); + ot(" cmp r0, #0 \n"); // SOUND_SILENT = 0 + ot(" ldrneh r1, [r1, #0x48] \n"); // r1 = SoundData.channels[reg >> 4].sample + ot(" bxeq lr \n"); + + ot(" and r0, r1, #0xff\n"); + ot(" orr r0, r0, r1, lsr #8\n"); + ot(" bx lr \n"); + + ot(".APU_DSP:\n"); + ot(" .long APU + 0x0b\n"); // &APU.DSP + ot(".SOUNDDATA_CHANNELS:\n"); + ot(" .long SoundData + 0x30\n"); // &SoundData.channels[0] +} + + +// bitrider +// macros +static void GetByte() { + ot(" mov r1, r0\n"); + + ot(" ldrb r0, [spc_ram, r1] \n"); + + ot(" cmp r1, #0x0ff\n"); + ot(" bhi 1f \n"); + + ot(" cmp r1, #0xf3 \n"); + ot(" addeq lr, pc, #12 \n"); // lr = &ExitPoint + ot(" beq GetAPUDSP \n"); + + ot(" cmp r1, #0xfd \n"); + ot(" movhs r2, #0 \n"); + ot(" strhsb r2, [spc_ram, r1] \n"); + ot("1:\n"); + + +} + +// trashes: r0, r1, r14 +static void GetByteZ() { + ot(" mov r1, r0\n"); + + ot(" cmp r1, #0xf3 \n"); + ot(" addeq lr, pc, #20 \n"); // lr = &ExitPoint + ot(" beq GetAPUDSP \n"); + + ot(" ldr r14, [context, #iapu_directpage]\n"); + ot(" cmp r1, #0xfd \n"); + ot(" ldrb r0, [r14, r1] \n"); + ot(" movhs r2, #0 \n"); + ot(" strhsb r2, [r14, r1] \n"); +} + +static void SetByte(int restore) { + // Still should check for ShowRom + ot(" add r2, r1, #40 \n"); + ot(" tst r2, #0x10000 \n"); + ot(" bne 1f \n"); + + ot(" bic r2, r1, #0x0f\n"); + ot(" cmp r2, #0xf0\n"); + ot(" strneb r0, [spc_ram, r1] \n"); + ot(" bne 3f\n"); + + ot(" add lr, pc, #20\n"); + + ot(" cmp r1, #0xf1 \n"); + ot(" beq S9xSetAPUControl \n"); + + ot(" cmp r1, #0xf3 \n"); // pc + 4 + ot(" beq S9xSetAPUDSP \n"); // pc + 8 + ot(" b S9xAPUSetByteFFtoF0 \n"); // pc + 12 + + ot("1: \n"); + ot(" bl S9xAPUSetByteFFC0 \n"); + ot(" ldr spc_ram, [context, #iapu_ram] \n"); + ot("3: \n"); + +} + +static void SetByteZ(int restore) { + ot(" ldr r2, [context, #iapu_directpage] \n"); + ot(" cmp r2, spc_ram \n"); + ot(" bne 2f \n"); + + ot(" cmp r1, #0xf0 \n"); + ot(" blo 2f \n"); + + ot(" cmp r1, #0xfe \n"); + ot(" bhs 1f \n"); + + if (restore) ot(" add lr, pc, #16\n"); + else ot(" add lr, pc, #20\n"); + + ot(" cmp r1, #0xf1 \n"); + ot(" beq S9xSetAPUControl \n"); + + ot(" cmp r1, #0xf3 \n"); // pc + 4 + ot(" beq S9xSetAPUDSP \n"); // pc + 8 + ot(" b S9xAPUSetByteFFtoF0 \n"); // pc + 12 + //ot("6: \n"); // pc + 16 + if (restore) { + ot(" ldr spc_ram, [context, #iapu_ram] \n"); + ot(" b 1f \n"); + } + ot("2: \n"); + ot(" strb r0, [r2, r1] \n"); + ot("1: \n"); +} + + +// r0-2: Temporary registers +// r3 : current opcode or temp +// r4 : Cycles remaining +// r5 : Pointer to IAPU structure +// r6 : Pointer to Opcode Jump table +// r7 : Current PC +// r8 : YA +// r9 : P (nzzzzzzz ........ ........ NODBHIZC; nzzzzzzz - NZ flag in use (for a little speedup) + +// r10 : X +// r11 : S +// r14 : temp +// lr : RAM pointer + +static void PrintFramework() +{ + + +#ifndef SPC_DEBUG + ot(" .extern IAPU\n"); +#else + ot(" .extern IAPU2\n"); +#endif + ot(" .extern CPU @ for STOP and SLEEP\n"); + ot(" .extern S9xAPUGetByte\n"); + ot(" .extern S9xAPUSetByte\n"); + ot(" .extern S9xAPUGetByteZ\n"); + ot(" .extern S9xAPUSetByteZ\n\n"); + + // bitrider + ot(" .extern S9xGetAPUDSP\n"); + ot(" .extern S9xSetAPUDSP\n"); + ot(" .extern S9xSetAPUControl\n"); + ot(" .extern S9xAPUSetByteFFC0\n"); + ot(" .extern S9xAPUSetByteFFtoF0\n"); + + ot(" .global spc700_execute @ int cycles\n"); + //ot(" .global Spc700JumpTab\n\n"); + for (current_cycles=0; current_cycles < (sizeof(one_apu_cycle) / sizeof(int)); current_cycles++) + ot(" .global Spc700JumpTab_%i\n", one_apu_cycle[current_cycles]); + ot("\n"); + + + ot(" opcode .req r3\n"); + ot(" cycles .req r4\n"); + ot(" context .req r5\n"); + ot(" opcodes .req r6\n"); + ot(" spc_pc .req r7\n"); + ot(" spc_ya .req r8\n"); + ot(" spc_p .req r9\n"); + ot(" spc_x .req r10\n"); + ot(" spc_s .req r11\n"); + ot(" spc_ram .req r12\n\n"); + + ot(" .equ iapu_directpage, 0x00\n"); + ot(" .equ iapu_ram, 0x44\n"); + ot(" .equ iapu_extraram, 0x48\n"); + ot(" .equ iapu_allregs_load, 0x30\n"); + ot(" .equ iapu_allregs_save, 0x34\n\n"); + + ot(" .equ flag_c, 0x01\n"); + ot(" .equ flag_z, 0x02\n"); + ot(" .equ flag_i, 0x04\n"); + ot(" .equ flag_h, 0x08\n"); + ot(" .equ flag_b, 0x10\n"); + ot(" .equ flag_d, 0x20\n"); + ot(" .equ flag_o, 0x40\n"); + ot(" .equ flag_n, 0x80\n\n"); + + ot(" .equ cpu_apu_executing, %i \n\n", APU_EXECUTING_OFF); + // tmp +// ot(" .equ iapu_carry, 0x24\n"); +// ot(" .equ iapu_overflow, 0x26\n\n"); + + ot("@ --------------------------- Framework --------------------------\n"); + ot(" .align 4\n"); + ot("spc700_execute: @ int cycles\n"); + + ot(" stmfd sp!,{r4-r11,lr}\n"); + +#ifndef SPC_DEBUG + ot(" ldr context,=IAPU @ Pointer to SIAPU struct\n"); +#else + ot(" ldr context,=IAPU2 @ Pointer to SIAPU struct\n"); +#endif + ot(" mov cycles,r0 @ Cycles\n"); + ot(" add r0,context,#iapu_allregs_load\n"); + ot(" ldmia r0,{opcodes,spc_pc,spc_ya,spc_p,spc_x,spc_ram}\n"); + + ot(" ldrb opcode,[spc_pc],#1 @ Fetch first opcode\n"); + ot(" mov spc_s,spc_x,lsr #8\n"); + ot(" and spc_x,spc_x,#0xff\n"); + ot("\n"); + + ot(" ldr pc,[opcodes,opcode,lsl #2] @ Jump to opcode handler\n"); + ot("\n\n"); + + + ot("@ We come back here after execution\n"); + ot("spc700End:\n"); + ot(" orr spc_x,spc_x,spc_s,lsl #8\n"); + ot(" add r0,context,#iapu_allregs_save\n"); + ot(" stmia r0,{spc_pc,spc_ya,spc_p,spc_x}\n"); + ot(" mov r0,cycles\n"); + ot(" ldmfd sp!,{r4-r11,pc}\n"); + ot("\n"); + + ot(" .ltorg\n"); + ot("\n"); + + GetAPUDSP(); +} + + +// --------------------------------------------------------------------------- + +// Trashes r0-r3 +static void MemHandler(int set, int z, int save) +{ + //if(set) ot(" bl S9xAPUSetByte%s\n", z ? "Z" : ""); + //else ot(" bl S9xAPUGetByte%s\n", z ? "Z" : ""); + + //if(set) ot(" asm_S9xAPUSetByte%s\n", z ? "Z" : ""); + //else ot(" asm_S9xAPUGetByte%s\n", z ? "Z" : ""); + if(set) { + if (z) SetByteZ(save); + else SetByte(save); + } else { + if (z) GetByteZ(); + else GetByte(); + } + + //if(save) ot(" ldr spc_ram,[context,#iapu_ram]\n"); +} + +// pushes reg, trashes r1 +static void Push(char *reg) +{ + ot(" add r1,spc_ram,spc_s\n"); + ot(" strb %s,[r1,#0x100]\n", reg); + ot(" sub spc_s,spc_s,#1\n"); +} + +// pushes r0, trashes r0,r1 +static void PushW() +{ + ot(" add r1,spc_ram,spc_s\n"); + ot(" sub spc_s,spc_s,#2\n"); + ot(" strb r0,[r1,#0xff]\n"); + ot(" mov r0,r0,lsr #8\n"); + ot(" strb r0,[r1,#0x100]\n"); +} + +// pops to reg +static void Pop(char *reg) +{ + ot(" add %s,spc_ram,spc_s\n", reg); + ot(" ldrb %s,[%s,#(0x100 + 1)]\n", reg, reg); + ot(" add spc_s,spc_s,#1\n"); +} + +// pops to r0, trashes r1 +static void PopW() +{ + ot(" add r1,spc_ram,spc_s\n"); + ot(" ldrb r0,[r1,#(0xff + 2)]\n"); + ot(" ldrb r1,[r1,#(0x100 + 2)]\n"); + ot(" add spc_s,spc_s,#2\n"); + ot(" orr r0,r0,r1,lsl #8\n"); +} + +// // rr <- absolute, trashes r14 +// rr <- absolute + +static void AbsoluteAdd(int r, char *rAdd) +{ + ot(" ldrb r%i,[spc_pc],#1\n", r); + ot(" ldrb r14,[spc_pc],#1\n"); + if (rAdd) ot(" add r%i,r%i,%s\n", r, r, rAdd); + ot(" add r%i,r%i,r14,lsl #8\n", r, r); +} + +// // rr <- absolute, trashes r14 +// rr <- absolute +static void Absolute(int r) +{ + //ot(" ldrb r%i,[spc_pc],#1\n", r); + //ot(" ldrb r14,[spc_pc],#1\n"); + //ot(" orr r%i,r%i,r14,lsl #8\n", r, r); + AbsoluteAdd(r, NULL); +} + + +// rr <- absoluteX, trashes r14 +static void AbsoluteX(int r) +{ + //Absolute(r); + //ot(" ldrb r%i,[spc_pc],#1\n", r); + //ot(" ldrb r14,[spc_pc],#1\n"); + //ot(" add r%i,r%i,spc_x\n", r, r); + //ot(" add r%i,r%i,r14,lsl #8\n", r, r); + AbsoluteAdd(r, "spc_x"); +} + +// r0 <- absoluteY, trashes r1 +static void AbsoluteY(int r) +{ + //Absolute(r); + //ot(" ldrb r%i,[spc_pc],#1\n", r); + //ot(" ldrb r14,[spc_pc],#1\n"); + //ot(" add r%i,r%i,spc_ya,lsr #8\n", r, r); + //ot(" add r%i,r%i,r14,lsl #8\n", r, r); + AbsoluteAdd(r, "spc_ya, lsr #8"); +} + +// rr <- IndirectIndexedY, trashes r14 +static void IndirectIndexedY(int r) +{ + ot(" ldrb r%i,[spc_pc],#1\n", r); + ot(" ldr r14,[context,#iapu_directpage]\n"); + ot(" ldrb r%i,[r14,r%i]!\n", r, r); + ot(" ldrb r14,[r14,#1]\n"); + //ot(" orr r%i,r%i,r14,lsl #8\n", r, r); + ot(" add r%i,r%i,spc_ya,lsr #8\n", r, r); + ot(" add r%i,r%i,r14,lsl #8\n", r, r); +} + +// rr <- address, trashes r14 +static void IndexedXIndirect(int r) +{ + ot(" ldrb r%i,[spc_pc],#1\n", r); + ot(" ldr r14,[context,#iapu_directpage]\n"); // again, interlocks are bad + ot(" add r%i,r%i,spc_x\n", r, r); + ot(" and r%i,r%i,#0xff\n", r, r); + ot(" ldrb r%i,[r14,r%i]!\n", r, r); + ot(" ldrb r14,[r14,#1]\n"); + ot(" orr r%i,r%i,r14,lsl #8\n", r, r); +} + +// sets ZN for reg in *reg, not suitable for Y +static void SetZN8(char *reg) +{ + ot(" and spc_p,spc_p,#0xff\n"); + ot(" orr spc_p,spc_p,%s,lsl #24\n", reg); +} + +// sets ZN for reg in *reg +static void SetZN16(char *reg) +{ + ot(" and spc_p,spc_p,#0xff\n"); + ot(" orr spc_p,spc_p,%s,lsl #16\n", reg); + ot(" tst %s,#0xff\n", reg); + ot(" orrne spc_p,spc_p,#0x01000000\n"); +} + +// does ROL on r0, sets flags +static void Rol() +{ + ot(" mov r0,r0,lsl #1\n"); + ot(" tst spc_p,#flag_c\n"); + ot(" orrne r0,r0,#1\n"); + ot(" tst r0,#0x100\n"); + ot(" orrne spc_p,spc_p,#flag_c\n"); + ot(" biceq spc_p,spc_p,#flag_c\n"); + SetZN8("r0"); +} + +// does ROR on r0, sets flags +static void Ror() +{ + ot(" tst spc_p,#flag_c\n"); + ot(" orrne r0,r0,#0x100\n"); + ot(" movs r0,r0,lsr #1\n"); + ot(" orrcs spc_p,spc_p,#flag_c\n"); + ot(" biccc spc_p,spc_p,#flag_c\n"); + SetZN8("r0"); +} + +// does ASL on r0, sets flags but doesn't cut the shifted bits +static void Asl() +{ + ot(" tst r0,#0x80\n"); + ot(" orrne spc_p,spc_p,#flag_c\n"); + ot(" biceq spc_p,spc_p,#flag_c\n"); + ot(" mov r0,r0,lsl #1\n"); + SetZN8("r0"); +} + +// does LSR on r0, sets flags +static void Lsr() +{ + ot(" tst r0,#0x01\n"); + ot(" orrne spc_p,spc_p,#flag_c\n"); + ot(" biceq spc_p,spc_p,#flag_c\n"); + ot(" mov r0,r0,lsr #1\n"); + SetZN8("r0"); +} + +// CMP rr0,rr1; trashes r14 +static void Cmp(char *r0, char *r1, int and_r0) +{ + char *lop = r0; + + if(and_r0) { ot(" and r14,%s,#0xff\n", r0); lop = "r14"; } + ot(" subs r14,%s,%s\n", lop, r1); + //ot(" orrge spc_p,spc_p,#flag_c\n"); + //ot(" biclt spc_p,spc_p,#flag_c\n"); + ot(" orrcs spc_p,spc_p,#flag_c\n"); + ot(" biccc spc_p,spc_p,#flag_c\n"); + SetZN8("r14"); +} + +// ADC rr0,rr1 -> rr0, trashes r2,r14, does not mask to byte +static void Adc(char *r0, char *r1) +{ + ot(" eor r2,%s,%s\n", r0, r1); // r3=(a) ^ (b) + ot(" movs r14, spc_p, lsr #1\n"); + ot(" adc %s, %s, %s\n", r0, r0, r1); + //ot(" add %s,%s,%s\n", r0, r0, r1); + //ot(" tst spc_p,#flag_c\n"); + //ot(" addne %s,%s,#1\n", r0, r0); + ot(" movs r14,%s,lsr #8\n", r0); + ot(" orrne spc_p,spc_p,#flag_c\n"); + ot(" biceq spc_p,spc_p,#flag_c\n"); + ot(" eor r14,%s,%s\n", r0, r1); // r14=(b) ^ Work16 + ot(" bic r14,r14,r2\n"); // ((b) ^ Work16) & ~((a) ^ (b)) + ot(" tst r14,#0x80\n"); + ot(" orrne spc_p,spc_p,#flag_o\n"); + ot(" biceq spc_p,spc_p,#flag_o\n"); + ot(" eor r14,r2,%s\n", r0); + ot(" tst r14,#0x10\n"); + ot(" orrne spc_p,spc_p,#flag_h\n"); + ot(" biceq spc_p,spc_p,#flag_h\n"); +} + +// SBC rr0,rr1 -> rr0, trashes r2,r3,r14, does not mask to byte +static void Sbc(char *r0, char *r1) +{ + ot(" movs r14,spc_p,lsr #1\n"); + ot(" sbcs r2,%s,%s\n", r0, r1); + ot(" orrge spc_p,spc_p,#flag_c\n"); + ot(" biclt spc_p,spc_p,#flag_c\n"); + ot(" eor r14,%s,r2\n", r0); // r14=(a) ^ Int16 + ot(" eor r3,%s,%s\n", r0, r1); // r3=(a) ^ (b) + ot(" and r14,r14,r3\n"); // ((a) ^ Work16) & ((a) ^ (b)) + ot(" tst r14,#0x80\n"); + ot(" orrne spc_p,spc_p,#flag_o\n"); + ot(" biceq spc_p,spc_p,#flag_o\n"); + ot(" eor r14,r3,r2\n"); + ot(" tst r14,#0x10\n"); + ot(" orreq spc_p,spc_p,#flag_h\n"); + ot(" bicne spc_p,spc_p,#flag_h\n"); + ot(" mov %s,r2\n", r0); +} + + +// +static void TCall() +{ + ot(" sub r0,spc_pc,spc_ram\n"); + PushW(); + ot(" ldr r0,[context,#iapu_extraram]\n"); + ot(" ldrh r0,[r0,#0x%x]\n", (15-(opcode>>4))<<1); + ot(" add spc_pc,spc_ram,r0\n"); +} + +// +static void SetClr1() +{ + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + ot(" %s r0,r0,#0x%02x\n", opcode & 0x10 ? "bic" : "orr", 1<<(opcode>>5)); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); +} + +// +static void BssBbc() +{ + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 1); + ot(" tst r0,#0x%02x\n", 1<<(opcode>>5)); + ot(" add%s spc_pc,spc_pc,#1\n", opcode & 0x10 ? "ne" : "eq"); + ot(" ldr%ssb r0,[spc_pc],#1\n", opcode & 0x10 ? "eq" : "ne"); + ot(" sub%s cycles,cycles,#%i\n",opcode & 0x10 ? "eq" : "ne", one_apu_cycle[current_cycles]*2); + ot(" add%s spc_pc,spc_pc,r0\n", opcode & 0x10 ? "eq" : "ne"); +} + +// +static void Membit() +{ + ot(" ldrb r0,[spc_pc], #1\n"); + ot(" ldrb r3,[spc_pc], #1\n"); + //ot(" orr spc_x,spc_x,r1,lsl #(29-5) + ot(" add r3,r0,r3,lsl #8\n"); //@ store membit where it can survive memhandler call\n"); // saving bit 12 ? + //ot(" mov r1,r1,lsr #5\n"); + //ot(" mov r0,r0,lsl #19\n"); + //ot(" mov r0,r0,lsr #19\n"); + //if((opcode >> 4) >= 0xC) ot(" mov r3, r0\n"); //ot(" stmfd sp!,{r0}\n"); // membit + ot(" bic r0, r3, #0xe000\n"); // Clear bits 15, 14 & 13 => r0 = r0 & 0x1fff + MemHandler(0, 0, 0); + //ot(" mov r1,spc_x,lsr #29\n"); + //ot(" and spc_x,spc_x,#0xff\n"); + ot(" mov r1, r3, lsr #13\n"); // membit = bits[15:13] of memory address + if((opcode >> 4) < 0xC) { + ot(" mov r0,r0,lsr r1\n"); + ot(" tst r0,#1\n"); + switch(opcode >> 4) { + case 0x0: ot(" orrne spc_p,spc_p,#flag_c\n"); break; // OR1 C,membit + case 0x2: ot(" orreq spc_p,spc_p,#flag_c\n"); break; // OR1 C,not membit + case 0x4: ot(" biceq spc_p,spc_p,#flag_c\n"); break; // AND1 C,membit + case 0x6: ot(" bicne spc_p,spc_p,#flag_c\n"); break; // AND1 C, not membit + case 0x8: ot(" eorne spc_p,spc_p,#flag_c\n"); break; // EOR1 C, membit + case 0xA: ot(" orrne spc_p,spc_p,#flag_c\n"); // MOV1 C,membit + ot(" biceq spc_p,spc_p,#flag_c\n"); break; + } + } else { + ot(" mov r2,#1\n"); + ot(" mov r2,r2,lsl r1\n"); + if((opcode >> 4) == 0xC) { // MOV1 membit,C + ot(" tst spc_p,#flag_c\n"); + ot(" orrne r0,r0,r2\n"); + ot(" biceq r0,r0,r2\n"); + } else { // NOT1 membit + ot(" eor r0,r0,r2\n"); + } + //ot(" ldmfd sp!,{r1}\n"); + ot(" bic r1, r3, #0xe000\n"); // Clear bits 15, 14 & 13 => r0 = r0 & 0x1fff + MemHandler(1, 0, 0); + } + //ot(" ldr spc_ram,[context,#iapu_ram] @ restore what memhandler(s) messed up\n"); +} + +// +static void CBranch() +{ + int tests[] = { 0x80000000, 0x40, 0x01, 0xff000000 }; // NOCZ + char *eq = "eq"; + char *ne = "ne"; + + if((opcode>>6) == 3) { // zero test inverts everything + eq = "ne"; + ne = "eq"; + } + + ot(" tst spc_p,#0x%08X\n", tests[opcode>>6]); + ot(" add%s spc_pc,spc_pc,#1\n", opcode & 0x20 ? eq : ne); +/* + ot(" b%s Apu%02X\n", opcode & 0x20 ? eq : ne, opcode); + ot(" sub r0,spc_pc,spc_ram\n"); + ot(" ldrsb r1,[spc_pc],#1\n"); + ot(" add r0,r0,r1\n"); + ot(" mov r0,r0,lsl #16\n"); + ot(" add spc_pc,spc_ram,r0,lsr #16\n"); +*/ + ot(" ldr%ssb r0,[spc_pc],#1\n", opcode & 0x20 ? ne : eq); + + ot(" sub%s cycles,cycles,#%i\n", opcode & 0x20 ? ne : eq, one_apu_cycle[current_cycles]*2); + ot(" add%s spc_pc,spc_pc,r0\n", opcode & 0x20 ? ne : eq); +// ot("Apu%02X:\n", opcode); +} + +// NeededOperation spc_ya,r0 -> spc_ya +static void ArithOpToA() +{ + // special A pre-processing + if((opcode>>5) == 4 || (opcode>>5) == 5) { + ot(" and r1,spc_ya,#0xff00\n"); + ot(" and spc_ya,spc_ya,#0xff\n"); + } + + switch(opcode>>5) { + case 0: ot(" orr spc_ya,spc_ya,r0\n"); break; // OR + case 1: ot(" orr r0,r0,#0xff00\n"); + ot(" and spc_ya,spc_ya,r0\n"); break; // AND + case 2: ot(" eor spc_ya,spc_ya,r0\n"); break; // EOR + case 3: Cmp("spc_ya", "r0", 1); break; // CMP + case 4: Adc("spc_ya", "r0"); break; // ADC + case 5: Sbc("spc_ya", "r0"); break; // SBC + case 6: printf("MOV (reversed)!?\n"); break; // MOV (reversed) + case 7: ot(" and spc_ya,spc_ya,#0xff00\n"); + ot(" orr spc_ya,spc_ya,r0\n"); break; // MOV + } + + if((opcode>>5) != 3) SetZN8("spc_ya"); // only if not Cmp + + // special A post-processing + if((opcode>>5) == 4 || (opcode>>5) == 5) { + ot(" and spc_ya,spc_ya,#0xff\n"); + ot(" orr spc_ya,spc_ya,r1\n"); + } +} + +// +static void ArithmeticToA() +{ + switch(opcode&0x1f) { + case 0x04: // OP A,dp + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 1); + ArithOpToA(); + break; + + case 0x05: // OP A,abs + Absolute(0); + MemHandler(0, 0, 1); + ArithOpToA(); + break; + + case 0x06: // OP A,(X) + ot(" mov r0,spc_x\n"); + MemHandler(0, 1, 1); + ArithOpToA(); + break; + + case 0x07: // OP A,(dp+X) + IndexedXIndirect(0); + MemHandler(0, 0, 1); + ArithOpToA(); + break; + + case 0x08: // OP A,#00 + ot(" ldrb r0,[spc_pc],#1\n"); + ArithOpToA(); + break; + + case 0x14: // OP A,dp+X + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" add r0,r0,spc_x\n"); + MemHandler(0, 1, 1); + ArithOpToA(); + break; + + case 0x15: // OP A,abs+X + AbsoluteX(0); + MemHandler(0, 0, 1); + ArithOpToA(); + break; + + case 0x16: // OP A,abs+Y + AbsoluteY(0); + MemHandler(0, 0, 1); + ArithOpToA(); + break; + + case 0x17: // OP A,(dp)+Y + IndirectIndexedY(0); + MemHandler(0, 0, 1); + ArithOpToA(); + break; + + default: + printf("Op %02X - arithmetic??\n", opcode); + } +} + +void printOpcodes(int apu_cycles) { + for(opcode = 0; opcode < 0x100; opcode++) { + printf("%02X", opcode); + + ot("\n\n"); + //tmp_prologue(); + ot("Apu%02X_%i:\n", opcode, apu_cycles); + + if((opcode & 0x1f) == 0x10) CBranch(); // BXX + if((opcode & 0x0f) == 0x01) TCall(); // TCALL X + if((opcode & 0x0f) == 0x02) SetClr1(); // SET1/CLR1 direct page bit X + if((opcode & 0x0f) == 0x03) BssBbc(); // BBS/BBC direct page bit X + if((opcode & 0x1f) == 0x0A) Membit(); // membit ops + if((opcode & 0x0f) >= 0x04 && (opcode & 0x0f) <= 0x08 && (opcode & 0x1f) != 0x18 && (opcode >> 5) != 6) + ArithmeticToA(); + + + switch(opcode) { + case 0x00: // NOP + break; + + case 0x3F: // CALL absolute + Absolute(2); + ot(" sub r0,spc_pc,spc_ram\n"); + PushW(); + ot(" add spc_pc,spc_ram,r2\n"); + break; + + case 0x4F: // PCALL $XX + ot(" ldrb r2,[spc_pc],#1\n"); + ot(" sub r0,spc_pc,spc_ram\n"); + PushW(); + ot(" add spc_pc,spc_ram,r2\n"); + ot(" add spc_pc,spc_pc,#0xff00\n"); + break; + + case 0x09: // OR dp(dest),dp(src) + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 0); + //ot(" orr spc_x,spc_x,r0,lsl #24 @ save from harm\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + ot(" orr r0, r0, r3\n"); + //ot(" orr r0,r0,spc_x,lsr #24\n"); + //ot(" and spc_x,spc_x,#0xff\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x18: // OR dp,#00 + ot(" ldrb r0,[spc_pc,#1]\n"); + MemHandler(0, 1, 0); + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" orr r0,r0,r1\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x19: // OR (X),(Y) + ot(" mov r0,spc_x\n"); + MemHandler(0, 1, 0); + //ot(" orr spc_x,spc_x,r0,lsl #24\n"); + ot(" mov r3, r0\n"); + ot(" mov r0,spc_ya,lsr #8\n"); + MemHandler(0, 1, 0); + ot(" orr r0, r3, r0\n"); + //ot(" orr r0,r0,spc_x,lsr #24\n"); + //ot(" and spc_x,spc_x,#0xff\n"); + SetZN8("r0"); + ot(" mov r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0x0B: // ASL dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + Asl(); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x0C: // ASL abs + Absolute(0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + MemHandler(0, 0, 0); + Asl(); + //ot(" ldmfd sp!,{r1}\n"); + ot(" mov r1, r3\n"); + MemHandler(1, 0, 1); + break; + + case 0x1B: // ASL dp+X + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" add r0,r0,spc_x\n"); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + MemHandler(0, 1, 0); + Asl(); + //ot(" ldmfd sp!,{r1}\n"); + ot(" mov r1, r3\n"); + MemHandler(1, 1, 1); + break; + + case 0x1C: // ASL A + ot(" tst spc_ya,#0x80\n"); + ot(" orrne spc_p,spc_p,#flag_c\n"); + ot(" biceq spc_p,spc_p,#flag_c\n"); + ot(" and r0,spc_ya,#0x7f\n"); + ot(" and spc_ya,spc_ya,#0xff00\n"); + ot(" orr spc_ya,spc_ya,r0,lsl #1\n"); + SetZN8("spc_ya"); + break; + + case 0x0D: // PUSH PSW + ot(" mov r0,spc_p,lsr #24\n"); + ot(" and r1,r0,#0x80\n"); + ot(" tst r0,r0\n"); + ot(" orreq r1,r1,#flag_z\n"); + ot(" and spc_p,spc_p,#0x7d @ clear N & Z\n"); + ot(" orr spc_p,spc_p,r1\n"); + Push("spc_p"); + otb(" orr spc_p,spc_p,r0,lsl #24\n"); + break; + + case 0x2D: // PUSH A + Push("spc_ya"); + break; + + case 0x4D: // PUSH X + Push("spc_x"); + break; + + case 0x6D: // PUSH Y + ot(" mov r0,spc_ya,lsr #8\n"); + Push("r0"); + break; + + case 0x8E: // POP PSW + Pop("spc_p"); + ot(" and r0,spc_p,#(flag_z|flag_n)\n"); + ot(" eor r0,r0,#flag_z\n"); + ot(" orr spc_p,spc_p,r0,lsl #24\n"); + ot(" tst spc_p,#flag_d\n"); + ot(" addne r0,spc_ram,#0x100\n"); + ot(" moveq r0,spc_ram\n"); + otb(" str r0,[context,#iapu_directpage]\n"); + break; + + case 0xAE: // POP A + Pop("r0"); + ot(" and spc_ya,spc_ya,#0xff00\n"); + otb(" orr spc_ya,spc_ya,r0\n"); + break; + + case 0xCE: // POP X + Pop("spc_x"); + break; + + case 0xEE: // POP X + Pop("r0"); + ot(" and spc_ya,spc_ya,#0xff\n"); + otb(" orr spc_ya,spc_ya,r0,lsl #8\n"); + break; + + case 0x0E: // TSET1 abs + Absolute(0); + ot(" mov r3, r0\n"); + //ot(" orr spc_x,spc_x,r0,lsl #16 @ save from memhandler\n"); + MemHandler(0, 0, 0); + ot(" and r2,r0,spc_ya\n"); + SetZN8("r2"); + ot(" orr r0,r0,spc_ya\n"); + ot(" mov r1, r3\n"); + //ot(" mov r1,spc_x,lsr #16\n"); + //ot(" and spc_x,spc_x,#0xff\n"); + MemHandler(1, 0, 1); + break; + + case 0x4E: // TCLR1 abs + Absolute(0); + ot(" mov r3, r0\n"); + //ot(" orr spc_x,spc_x,r0,lsl #16 @ save from memhandler\n"); + MemHandler(0, 0, 0); + ot(" and r2,r0,spc_ya\n"); + SetZN8("r2"); + ot(" bic r0,r0,spc_ya\n"); + ot(" mov r1, r3\n"); + //ot(" mov r1,spc_x,lsr #16\n"); + //ot(" and spc_x,spc_x,#0xff\n"); + MemHandler(1, 0, 1); + break; + + case 0x0F: // BRK + ot(" sub r0,spc_pc,spc_ram\n"); + PushW(); + ot(" mov r0,spc_p,lsr #24\n"); + ot(" and r1,r0,#0x80\n"); + ot(" tst r0,r0\n"); + ot(" orrne r1,r1,#flag_z\n"); + ot(" and spc_p,spc_p,#0x7d @ clear N & Z\n"); + ot(" orr spc_p,spc_p,r1\n"); + Push("spc_p"); + ot(" orr spc_p,spc_p,#flag_b\n"); + ot(" bic spc_p,spc_p,#flag_i\n"); + ot(" ldr r0,[context,#iapu_extraram]\n"); + ot(" ldrh r0,[r0,#0x20]\n"); + ot(" add spc_pc,spc_ram,r0\n"); + break; + + case 0xEF: // SLEEP + case 0xFF: // STOP: this is to be compatible with yoyofr's code + //ot(" ldr r0,=CPU\n"); + ot(" ldr r0, 5001f\n", apu_cycles); + ot(" mov r1,#0\n"); + //otb(" strb r1,[r0,#122]\n"); + otb(" str r1,[r0,#cpu_apu_executing]\n"); + //tmp_epilogue(); + ot(" subs cycles,cycles,#%i\n", S9xAPUCycles[opcode] * one_apu_cycle[current_cycles]); + ot(" ldrgeb opcode,[spc_pc],#1\n"); + flush_buffer(); + ot(" ldrge pc,[opcodes,opcode,lsl #2]\n"); + ot(" b spc700End\n"); + // don't let code flow until here + ot("5001:\n", apu_cycles); + ot(" .long CPU \n"); + break; + + case 0x2F: // BRA + ot(" ldrsb r0,[spc_pc],#1\n"); + ot(" add spc_pc,spc_pc,r0\n"); + break; + + case 0x80: // SETC + otb(" orr spc_p,spc_p,#flag_c\n"); + break; + + case 0xED: // NOTC + otb(" eor spc_p,spc_p,#flag_c\n"); + break; + + case 0x40: // SETP + ot(" orr spc_p,spc_p,#flag_d\n"); + ot(" add r0,spc_ram,#0x100\n"); + otb(" str r0,[context,#iapu_directpage]\n"); + break; + + case 0x1A: // DECW dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc]\n"); + ot(" add r0,r0,#1\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + ot(" orr r1,r3,r0,lsl #8\n"); + ot(" sub r0,r1,#1\n"); + SetZN16("r0"); + ot(" stmfd sp!,{r0}\n"); + ot(" ldrb r1,[spc_pc]\n"); + MemHandler(1, 1, 0); + ot(" ldmfd sp!,{r0}\n"); + ot(" mov r0,r0,lsr #8\n"); + ot(" ldrb r1,[spc_pc],#1\n"); + + ot(" add r1,r1,#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x5A: // CMPW YA,dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" add r0,r0,#1\n"); + MemHandler(0, 1, 1); + //ot(" ldmfd sp!,{r1}\n"); + ot(" orr r1,r3,r0,lsl #8\n"); + ot(" subs r0,spc_ya,r1\n"); + ot(" orrge spc_p,spc_p,#flag_c\n"); + ot(" biclt spc_p,spc_p,#flag_c\n"); + SetZN16("r0"); + break; + + case 0x3A: // INCW dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc]\n"); + ot(" add r0,r0,#1\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + ot(" orr r1,r3,r0,lsl #8\n"); + ot(" add r0,r1,#1\n"); + SetZN16("r0"); + ot(" stmfd sp!,{r0}\n"); + ot(" ldrb r1,[spc_pc]\n"); + MemHandler(1, 1, 0); + ot(" ldmfd sp!,{r0}\n"); + ot(" mov r0,r0,lsr #8\n"); + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" add r1,r1,#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x7A: // ADDW YA,dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" add r0,r0,#1\n"); + MemHandler(0, 1, 1); + //ot(" ldmfd sp!,{r1}\n"); + ot(" orr r1,r3,r0,lsl #8\n"); + ot(" add r0,spc_ya,r1\n"); + ot(" movs r2,r0,lsr #16\n"); + ot(" orrne spc_p,spc_p,#flag_c\n"); + ot(" biceq spc_p,spc_p,#flag_c\n"); + ot(" bic r2,r0,#0x00ff0000\n"); + ot(" eor r3,r1,r2\n"); // Work16 ^ (uint16) Work32 + ot(" eor r14,spc_ya,r1\n"); + ot(" mvn r14,r14\n"); // ~(pIAPU->YA.W ^ Work16) + ot(" and r14,r14,r3\n"); + ot(" tst r14,#0x8000\n"); + ot(" orrne spc_p,spc_p,#flag_o\n"); + ot(" biceq spc_p,spc_p,#flag_o\n"); + ot(" eor r14,r3,spc_ya\n"); + ot(" tst r14,#0x10\n"); + ot(" orrne spc_p,spc_p,#flag_h\n"); + ot(" biceq spc_p,spc_p,#flag_h\n"); + ot(" mov spc_ya,r2\n"); + SetZN16("spc_ya"); + + break; + + case 0x9A: // SUBW YA,dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" add r0,r0,#1\n"); + MemHandler(0, 1, 1); + //ot(" ldmfd sp!,{r1}\n"); + ot(" orr r1,r3,r0,lsl #8\n"); + ot(" subs r0,spc_ya,r1\n"); + ot(" orrge spc_p,spc_p,#flag_c\n"); + ot(" biclt spc_p,spc_p,#flag_c\n"); + ot(" mov r2,r0,lsl #16\n"); + ot(" mov r2,r2,lsr #16\n"); // r2=(uint16) Int32 + ot(" eor r3,spc_ya,r2\n"); // r3=pIAPU->YA.W ^ (uint16) Int32 + ot(" eor r14,spc_ya,r1\n"); + ot(" and r14,r14,r3\n"); + ot(" tst r14,#0x8000\n"); + ot(" orrne spc_p,spc_p,#flag_o\n"); + ot(" biceq spc_p,spc_p,#flag_o\n"); + ot(" eor r14,r3,r1\n"); + ot(" tst r14,#0x10\n"); + ot(" bicne spc_p,spc_p,#flag_h\n"); + ot(" orreq spc_p,spc_p,#flag_h\n"); + ot(" mov spc_ya,r2\n"); + SetZN16("spc_ya"); + break; + + case 0xBA: // MOVW YA,dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + ot(" ldrb r1, [spc_pc],#1\n"); + ot(" mov spc_ya, r0\n"); // avoiding inter-locks + ot(" add r0, r1, #1\n"); + MemHandler(0, 1, 1); + ot(" orr spc_ya,spc_ya,r0,lsl #8\n"); + SetZN16("spc_ya"); + break; + + case 0xDA: // MOVW dp,YA + ot(" ldrb r1,[spc_pc]\n"); + ot(" mov r0,spc_ya\n"); + MemHandler(1, 1, 0); + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" mov r0,spc_ya,lsr #8\n"); // avoiding inter-locks + ot(" add r1,r1,#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x69: // CMP dp(dest), dp(src) + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 0); + ot(" orr spc_x,spc_x,r0,lsl #24\n"); + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 1); + ot(" mov r1,spc_x,lsr #24\n"); + Cmp("r0", "r1", 0); + otb(" and spc_x,spc_x,#0xff\n"); + break; + + case 0x78: // CMP dp,#00 + ot(" ldrb r0,[spc_pc,#1]\n"); + MemHandler(0, 1, 1); + ot(" ldrb r1,[spc_pc],#2\n"); + Cmp("r0", "r1", 0); + break; + + case 0x79: // CMP (X),(Y) + ot(" mov r0,spc_x\n"); + MemHandler(0, 1, 0); + ot(" orr spc_x,spc_x,r0,lsl #24\n"); + ot(" mov r0,spc_ya,lsr #8\n"); + MemHandler(0, 1, 1); + ot(" mov r1,spc_x,lsr #24\n"); + Cmp("r1", "r0", 0); + otb(" and spc_x,spc_x,#0xff\n"); + break; + + case 0x1E: // CMP X,abs + Absolute(0); + MemHandler(0, 0, 1); + Cmp("spc_x", "r0", 0); + break; + + case 0x3E: // CMP X,dp + ot(" ldrb r0,[spc_pc],#1\n"); + + MemHandler(0, 1, 1); + Cmp("spc_x", "r0", 0); + break; + + case 0xC8: // CMP X,#00 + ot(" ldrb r0,[spc_pc],#1\n"); + Cmp("spc_x", "r0", 0); + break; + + case 0x5E: // CMP Y,abs + Absolute(0); + MemHandler(0, 0, 1); + ot(" mov r1,spc_ya,lsr #8\n"); + Cmp("r1", "r0", 0); + break; + + case 0x7E: // CMP Y,dp + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 1); + ot(" mov r1,spc_ya,lsr #8\n"); + Cmp("r1", "r0", 0); + break; + + case 0xAD: // CMP Y,#00 + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" mov r1,spc_ya,lsr #8\n"); + Cmp("r1", "r0", 0); + break; + + case 0x1F: // JMP (abs+X) + AbsoluteX(0); + ot(" sub sp,sp,#8\n"); + ot(" str r0,[sp,#4]\n"); + MemHandler(0, 0, 0); + ot(" str r0,[sp]\n"); + ot(" ldr r0,[sp,#4]\n"); + ot(" add r0,r0,#1\n"); + MemHandler(0, 0, 1); + ot(" ldr r1,[sp],#8\n"); + ot(" orr r0,r1,r0,lsl #8\n"); + ot(" add spc_pc,spc_ram,r0\n"); + break; + + case 0x5F: // JMP abs + //Absolute(0); + //ot(" add spc_pc,spc_ram,r0\n"); + ot(" ldrb r0, [spc_pc], #1\n"); + ot(" ldrb r14, [spc_pc], #1\n"); + ot(" add spc_pc, r0, spc_ram\n"); + ot(" add spc_pc, spc_pc, r14, lsl #8\n"); + break; + + case 0x20: // CLRP + ot(" bic spc_p,spc_p,#flag_d\n"); + otb(" str spc_ram,[context,#iapu_directpage]\n"); + break; + + case 0x60: // CLRC + otb(" bic spc_p,spc_p,#flag_c\n"); + break; + + case 0xE0: // CLRV + otb(" bic spc_p,spc_p,#(flag_o|flag_h)\n"); + break; + + case 0x29: // AND dp(dest), dp(src) + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + ot(" and r0,r0,r3\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x38: // AND dp,#00 + ot(" ldrb r0,[spc_pc,#1]\n"); + MemHandler(0, 1, 0); + ot(" ldrb r1,[spc_pc],#2\n"); + ot(" and r0,r0,r1\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc,#-1]\n"); + MemHandler(1, 1, 1); + break; + + case 0x39: // AND (X),(Y) + ot(" mov r0,spc_x\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" mov r0,spc_ya,lsr #8\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + ot(" and r0,r0,r3\n"); + SetZN8("r0"); + ot(" mov r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0x2B: // ROL dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + Rol(); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x2C: // ROL abs + Absolute(0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + MemHandler(0, 0, 0); + Rol(); + //ot(" ldmfd sp!,{r1}\n"); + ot(" mov r1, r3\n"); + MemHandler(1, 0, 1); + break; + + case 0x3B: // ROL dp+X + ot(" ldrb r0,[spc_pc]\n"); + ot(" add r0,r0,spc_x\n"); + MemHandler(0, 1, 0); + Rol(); + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" add r1,r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0x3C: // ROL A + ot(" and r0,spc_ya,#0xff\n"); + Rol(); + ot(" and r0,r0,#0xff\n"); + ot(" mov spc_ya,spc_ya,lsr #8\n"); + otb(" orr spc_ya,r0,spc_ya,lsl #8\n"); + break; + + case 0x2E: // CBNE dp,rel + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 1); + ot(" and r1,spc_ya,#0xff\n"); + ot(" cmp r0,r1\n"); + ot(" addeq spc_pc,spc_pc,#1\n"); + ot(" ldrnesb r0,[spc_pc],#1\n"); + ot(" subne cycles,cycles,#%i\n", one_apu_cycle[current_cycles]*2); + ot(" addne spc_pc,spc_pc,r0\n"); + break; + + case 0xDE: // CBNE dp+X,rel + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" add r0,r0,spc_x\n"); + MemHandler(0, 1, 1); + ot(" and r1,spc_ya,#0xff\n"); + ot(" cmp r0,r1\n"); + ot(" addeq spc_pc,spc_pc,#1\n"); + ot(" ldrnesb r0,[spc_pc],#1\n"); + ot(" addne spc_pc,spc_pc,r0\n"); + ot(" subne cycles,cycles,#%i\n", one_apu_cycle[current_cycles]*2); + break; + + case 0x3D: // INC X + ot(" add spc_x,spc_x,#1\n"); + ot(" and spc_x,spc_x,#0xff\n"); + SetZN8("spc_x"); + break; + + case 0xFC: // INC Y + ot(" mov r0,spc_ya,lsr #8\n"); + ot(" add r0,r0,#1\n"); + ot(" and r0,r0,#0xff\n"); + SetZN8("r0"); + ot(" and spc_ya,spc_ya,#0xff\n"); + otb(" orr spc_ya,spc_ya,r0,lsl #8\n"); + break; + + case 0x1D: // DEC X + ot(" sub spc_x,spc_x,#1\n"); + ot(" and spc_x,spc_x,#0xff\n"); + SetZN8("spc_x"); + break; + + case 0xDC: // DEC Y + ot(" mov r0,spc_ya,lsr #8\n"); + ot(" sub r0,r0,#1\n"); + ot(" and r0,r0,#0xff\n"); + SetZN8("r0"); + ot(" and spc_ya,spc_ya,#0xff\n"); + otb(" orr spc_ya,spc_ya,r0,lsl #8\n"); + break; + + case 0xAB: // INC dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + ot(" add r0,r0,#1\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0xAC: // INC abs + Absolute(0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + MemHandler(0, 0, 0); + ot(" add r0,r0,#1\n"); + SetZN8("r0"); + //ot(" ldmfd sp!,{r1}\n"); + ot(" mov r1, r3\n"); + MemHandler(1, 0, 1); + break; + + case 0xBB: // INC dp+X + ot(" ldrb r0,[spc_pc]\n"); + ot(" add r0,r0,spc_x\n"); + MemHandler(0, 1, 0); + ot(" add r0,r0,#1\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" add r1,r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0xBC: // INC A + ot(" and r0,spc_ya,#0xff\n"); + ot(" add r0,r0,#1\n"); + SetZN8("r0"); + ot(" and r0,r0,#0xff\n"); + ot(" mov spc_ya,spc_ya,lsr #8\n"); + otb(" orr spc_ya,r0,spc_ya,lsl #8\n"); + break; + + case 0x8B: // DEC dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + ot(" sub r0,r0,#1\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x8C: // DEC abs + Absolute(0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + MemHandler(0, 0, 0); + ot(" sub r0,r0,#1\n"); + SetZN8("r0"); + //ot(" ldmfd sp!,{r1}\n"); + ot(" mov r1, r3\n"); + MemHandler(1, 0, 1); + break; + + case 0x9B: // DEC dp+X + ot(" ldrb r0,[spc_pc]\n"); + ot(" add r0,r0,spc_x\n"); + MemHandler(0, 1, 0); + ot(" sub r0,r0,#1\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + + ot(" add r1,r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0x9C: // DEC A + ot(" and r0,spc_ya,#0xff\n"); + ot(" sub r0,r0,#1\n"); + SetZN8("r0"); + ot(" and r0,r0,#0xff\n"); + ot(" mov spc_ya,spc_ya,lsr #8\n"); + otb(" orr spc_ya,r0,spc_ya,lsl #8\n"); + break; + + case 0x49: // EOR dp(dest), dp(src) + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + ot(" eor r0,r0,r3\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x58: // EOR dp,#00 + ot(" ldrb r0,[spc_pc,#1]\n"); + MemHandler(0, 1, 0); + ot(" ldrb r1,[spc_pc],#2\n"); + ot(" eor r0,r0,r1\n"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc,#-1]\n"); + MemHandler(1, 1, 1); + break; + + case 0x59: // EOR (X),(Y) + ot(" mov r0,spc_x\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" mov r0,spc_ya,lsr #8\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + ot(" eor r0,r0,r3\n"); + SetZN8("r0"); + ot(" mov r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0x4B: // LSR dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + Lsr(); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x4C: // LSR abs + Absolute(0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + MemHandler(0, 0, 0); + Lsr(); + //ot(" ldmfd sp!,{r1}\n"); + ot(" mov r1, r3\n"); + MemHandler(1, 0, 1); + break; + + case 0x5B: // LSR dp+X + ot(" ldrb r0,[spc_pc]\n"); + ot(" add r0,r0,spc_x\n"); + MemHandler(0, 1, 0); + Lsr(); + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" add r1,r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0x5C: // LSR A + ot(" and r0,spc_ya,#0xff\n"); + Lsr(); + ot(" mov spc_ya,spc_ya,lsr #8\n"); + otb(" orr spc_ya,r0,spc_ya,lsl #8\n"); + break; + + case 0x7D: // MOV A,X + ot(" and spc_ya,spc_ya,#0xff00\n"); + ot(" orr spc_ya,spc_ya,spc_x\n"); + SetZN8("spc_ya"); + break; + + case 0xDD: // MOV A,Y + ot(" and spc_ya,spc_ya,#0xff00\n"); + ot(" orr spc_ya,spc_ya,spc_ya,lsr #8\n"); + SetZN8("spc_ya"); + break; + + case 0x5D: // MOV X,A + ot(" and spc_x,spc_ya,#0xff\n"); + SetZN8("spc_x"); + break; + + case 0xFD: // MOV Y,A + ot(" and spc_ya,spc_ya,#0xff\n"); + ot(" orr spc_ya,spc_ya,spc_ya,lsl #8\n"); + SetZN8("spc_ya"); + break; + + case 0x9D: // MOV X,SP + ot(" mov spc_x,spc_s\n"); + SetZN8("spc_x"); + break; + + case 0xBD: // SP,X + otb(" mov spc_s,spc_x\n"); + break; + + case 0x6B: // ROR dp + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + Ror(); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x6C: // ROR abs + Absolute(0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + MemHandler(0, 0, 0); + Ror(); + ot(" mov r1, r3\n"); + //ot(" ldmfd sp!,{r1}\n"); + MemHandler(1, 0, 1); + break; + + case 0x7B: // ROR dp+X + ot(" ldrb r0,[spc_pc]\n"); + ot(" add r0,r0,spc_x\n"); + MemHandler(0, 1, 0); + Ror(); + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" add r1,r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0x7C: // ROR A + ot(" and r0,spc_ya,#0xff\n"); + Ror(); + ot(" mov spc_ya,spc_ya,lsr #8\n"); + otb(" orr spc_ya,r0,spc_ya,lsl #8\n"); + break; + + case 0x6E: // DBNZ dp,rel + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" sub r0,r0,#1\n"); + ot(" tst r0,r0\n"); + ot(" addeq spc_pc,spc_pc,#1\n"); + ot(" ldrnesb r2,[spc_pc],#1\n"); + ot(" addne spc_pc,spc_pc,r2\n"); + ot(" subne cycles,cycles,#%i\n", one_apu_cycle[current_cycles]*2); + MemHandler(1, 1, 1); + break; + + case 0xFE: // DBNZ Y,rel + ot(" sub spc_ya,spc_ya,#0x100\n"); + ot(" mov spc_ya,spc_ya,lsl #16\n"); + ot(" mov spc_ya,spc_ya,lsr #16\n"); + ot(" movs r0,spc_ya,lsr #8\n"); + ot(" addeq spc_pc,spc_pc,#1\n"); + ot(" ldrnesb r0,[spc_pc],#1\n"); + ot(" addne spc_pc,spc_pc,r0\n"); + ot(" subne cycles,cycles,#%i\n", one_apu_cycle[current_cycles]*2); + break; + + case 0x6F: // RET + PopW(); + ot(" add spc_pc,spc_ram,r0\n"); + break; + + case 0x7F: // RETI + Pop("spc_p"); + ot(" and r0,spc_p,#(flag_z|flag_n)\n"); + ot(" eor r0,r0,#flag_z\n"); + ot(" orr spc_p,spc_p,r0,lsl #24\n"); + ot(" tst spc_p,#flag_d\n"); + ot(" addne r0,spc_ram,#0x100\n"); + ot(" moveq r0,spc_ram\n"); + ot(" str r0,[context,#iapu_directpage]\n"); + PopW(); + ot(" add spc_pc,spc_ram,r0\n"); + break; + + case 0x89: // ADC dp(dest), dp(src) + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + //ot(" mov r1, r3\n"); + Adc("r0", "r3"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x98: // ADC dp,#00 + ot(" ldrb r0,[spc_pc,#1]\n"); + MemHandler(0, 1, 0); + ot(" ldrb r1,[spc_pc],#2\n"); + Adc("r0", "r1"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc,#-1]\n"); + MemHandler(1, 1, 1); + break; + + case 0x99: // ADC (X),(Y) + ot(" mov r0,spc_x\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" mov r0,spc_ya,lsr #8\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + //ot(" mov r1, r3\n"); + Adc("r0", "r3"); + SetZN8("r0"); + ot(" mov r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0x8D: // MOV Y,#00 //-REVISAR + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" and spc_ya,spc_ya,#0xff\n"); + ot(" orr spc_ya,spc_ya,r0,lsl #8\n"); + SetZN8("r0"); + break; + + case 0x8F: // MOV dp,#00 //-REVISAR + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0x9E: // DIV YA,X + ot(" tst spc_x,spc_x @ div by 0?\n"); + ot(" orreq spc_ya,spc_ya,#0xff00\n"); + ot(" orreq spc_ya,spc_ya,#0x00ff\n"); + ot(" orreq spc_p,spc_p,#flag_o\n"); + ot(" beq 1002f\n"); + ot(" bic spc_p,spc_p,#flag_o\n"); + + // division algo from Cyclone (result in r3, remainder instead of divident) + ot("@ Divide spc_ya by spc_x\n"); + ot(" mov r3,#0\n"); + ot(" mov r1,spc_x\n"); + ot("\n"); + + // + /*ot("@ Shift up divisor till it's just less than numerator\n"); + ot("divshift:\n"); + ot(" cmp r1,spc_ya,lsr #1\n"); + ot(" movls r1,r1,lsl #1\n"); + ot(" bcc divshift\n"); + ot("\n");*/ + + //optimised version of code provided by William Blair + ot("@ Shift up divisor till it's just less than numerator\n"); + ot("cmp spc_ya,r1,lsl #8\n"); + ot("movge r1,r1,lsl #8\n"); + ot("cmp spc_ya,r1,lsl #4\n"); + ot("movge r1,r1,lsl #4\n"); + ot("cmp spc_ya,r1,lsl #2\n"); + ot("movge r1,r1,lsl #2\n"); + ot("cmp spc_ya,r1,lsl #1\n"); + ot("movge r1,r1,lsl #1\n"); + + ot("1001:\n"); + ot(" cmp spc_ya,r1\n"); + ot(" adc r3,r3,r3 ;@ Double r3 and add 1 if carry set\n"); + ot(" subcs spc_ya,spc_ya,r1\n"); + ot(" teq r1,spc_x\n"); + ot(" movne r1,r1,lsr #1\n"); + ot(" bne 1001b\n"); + ot("\n"); + + ot(" and spc_ya,spc_ya,#0xff\n"); + ot(" and r3,r3,#0xff\n"); + ot(" orr spc_ya,r3,spc_ya,lsl #8\n"); + + ot("1002:\n"); + SetZN8("spc_ya"); + break; + + case 0x9F: // XCN A + ot(" and r0,spc_ya,#0xff\n"); + ot(" mov r1,r0,lsl #28\n"); + ot(" orr r0,r1,r0,lsl #20\n"); + ot(" and spc_ya,spc_ya,#0xff00\n"); + ot(" orr spc_ya,spc_ya,r0,lsr #24\n"); + SetZN8("spc_ya"); + break; + + case 0xA9: // SBC dp(dest), dp(src) + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" ldrb r0,[spc_pc]\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + //ot(" mov r1, r3\n"); + Sbc("r0", "r3"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0xB8: // SBC dp,#00 + ot(" ldrb r0,[spc_pc,#1]\n"); + MemHandler(0, 1, 0); + ot(" ldrb r1,[spc_pc],#2\n"); + Sbc("r0", "r1"); + SetZN8("r0"); + ot(" ldrb r1,[spc_pc,#-1]\n"); + MemHandler(1, 1, 1); + break; + + case 0xB9: // SBC (X),(Y) + ot(" mov r0,spc_x\n"); + MemHandler(0, 1, 0); + //ot(" stmfd sp!,{r0}\n"); + ot(" mov r3, r0\n"); + ot(" mov r0,spc_ya,lsr #8\n"); + MemHandler(0, 1, 0); + //ot(" ldmfd sp!,{r1}\n"); + //ot(" mov r1, r3\n"); + Sbc("r0", "r3"); + SetZN8("r0"); + ot(" mov r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0xAF: // MOV (X)+, A + ot(" mov r0,spc_ya\n"); + ot(" mov r1,spc_x\n"); + MemHandler(1, 1, 1); + ot(" add spc_x,spc_x,#1\n"); + otb(" and spc_x,spc_x,#0xff\n"); + break; + + case 0xBE: // DAS + ot(" and r0,spc_ya,#0xff\n"); + ot(" and r1,spc_ya,#0x0f\n"); + ot(" cmp r1,#9\n"); + ot(" subhi r0,r0,#6\n"); + ot(" tstls spc_p,#flag_h\n"); + ot(" subeq r0,r0,#6\n"); + ot(" cmp r0,#0x9f\n"); + ot(" bhi 2001f\n"); + ot(" tst spc_p,#flag_c\n"); + ot(" beq 2001f\n"); + ot(" orr spc_p,spc_p,#flag_c\n"); + ot(" b 2002f\n"); + ot("2001:\n"); // tens + ot(" sub r0,r0,#0x60\n"); + ot(" bic spc_p,spc_p,#flag_c\n"); + + ot("2002:\n"); // end + ot(" and spc_ya,spc_ya,#0xff00\n"); + ot(" orr spc_ya,spc_ya,r0\n"); + SetZN8("spc_ya"); + break; + + case 0xBF: // MOV A,(X)+ + ot(" mov r0,spc_x\n"); + MemHandler(0, 1, 1); + ot(" and spc_ya,spc_ya,#0xff00\n"); + ot(" orr spc_ya,spc_ya,r0\n"); + ot(" add spc_x,spc_x,#1\n"); + ot(" and spc_x,spc_x,#0xff\n"); + SetZN8("spc_ya"); + break; + + case 0xC0: // DI + otb(" bic spc_p,spc_p,#flag_i\n"); + break; + + case 0xA0: // EI + otb(" orr spc_p,spc_p,#flag_i\n"); + break; + + case 0xC4: // MOV dp,A + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" mov r0,spc_ya\n"); + MemHandler(1, 1, 1); + break; + + case 0xC5: // MOV abs,A + Absolute(1); + ot(" mov r0,spc_ya\n"); + MemHandler(1, 0, 1); + break; + + case 0xC6: // MOV (X),A + ot(" mov r0,spc_ya\n"); + ot(" mov r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0xC7: // MOV (dp+X),A + IndexedXIndirect(1); + ot(" mov r0,spc_ya\n"); + MemHandler(1, 0, 1); + break; + + case 0xC9: // MOV abs,X + Absolute(1); + ot(" mov r0,spc_x\n"); + MemHandler(1, 0, 1); + break; + + case 0xCB: // MOV dp,Y + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" mov r0,spc_ya,lsr #8\n"); + MemHandler(1, 1, 1); + break; + + case 0xCC: // MOV abs,Y + + Absolute(1); + ot(" mov r0,spc_ya,lsr #8\n"); + MemHandler(1, 0, 1); + break; + + case 0xCD: // MOV X,#00 + ot(" ldrb spc_x,[spc_pc],#1\n"); + SetZN8("spc_x"); + break; + + case 0xCF: // MUL YA + ot(" mov r0,spc_ya,lsr #8\n"); + ot(" and spc_ya,spc_ya,#0xff\n"); + ot(" mul spc_ya,r0,spc_ya\n"); + SetZN16("spc_ya"); + break; + + case 0xD4: // MOV dp+X, A + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" mov r0,spc_ya\n"); + ot(" add r1,r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0xD5: // MOV abs+X,A + AbsoluteX(1); + ot(" mov r0,spc_ya\n"); + MemHandler(1, 0, 1); + break; + + case 0xD6: // MOV abs+Y,A + AbsoluteY(1); + ot(" mov r0,spc_ya\n"); + MemHandler(1, 0, 1); + break; + + case 0xD7: // MOV (dp)+Y,A + IndirectIndexedY(1); + ot(" mov r0,spc_ya\n"); + MemHandler(1, 0, 1); + break; + + case 0xD8: // MOV dp,X + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" mov r0,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0xD9: // MOV dp+Y,X + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" mov r0,spc_x\n"); + ot(" add r1,r1,spc_ya,lsr #8\n"); + MemHandler(1, 1, 1); + break; + + case 0xDB: // MOV dp+X,Y + ot(" ldrb r1,[spc_pc],#1\n"); + ot(" mov r0,spc_ya,lsr #8\n"); + ot(" add r1,r1,spc_x\n"); + MemHandler(1, 1, 1); + break; + + case 0xDF: // DAA + ot(" and r0,spc_ya,#0xff\n"); + ot(" and r1,spc_ya,#0x0f\n"); + ot(" cmp r1,#9\n"); + ot(" addhi r0,r0,#6\n"); + ot(" bls 3001f\n"); + ot(" cmphi r0,#0xf0\n"); + ot(" orrhi spc_p,spc_p,#flag_c\n"); + ot(" b 3002f\n"); + ot("3001:\n"); // testHc + ot(" tst spc_p,#flag_h\n"); + ot(" addne r0,r0,#6\n"); + ot(" beq 3002f\n"); + ot(" cmp r0,#0xf0\n"); + ot(" orrhi spc_p,spc_p,#flag_c\n"); + ot("3002:\n"); // test2 + ot(" tst spc_p,#flag_c\n"); + ot(" addne r0,r0,#0x60\n"); + ot(" bne 3003f\n"); + ot(" cmp r0,#0x9f\n"); + ot(" addhi r0,r0,#0x60\n"); + ot(" orrhi spc_p,spc_p,#flag_c\n"); + ot(" bicls spc_p,spc_p,#flag_c\n"); + ot("3003:\n"); // end + ot(" and spc_ya,spc_ya,#0xff00\n"); + ot(" orr spc_ya,spc_ya,r0\n"); + SetZN8("spc_ya"); + break; + + case 0xE9: // MOV X, abs + Absolute(0); + MemHandler(0, 0, 1); + ot(" mov spc_x,r0\n"); + SetZN8("spc_x"); + break; + + case 0xEB: // MOV Y,dp + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 1); + ot(" and spc_ya,spc_ya,#0xff\n"); + ot(" orr spc_ya,spc_ya,r0,lsl #8\n"); + SetZN8("r0"); + break; + + case 0xEC: // MOV Y,abs + Absolute(0); + MemHandler(0, 0, 1); + ot(" and spc_ya,spc_ya,#0xff\n"); + ot(" orr spc_ya,spc_ya,r0,lsl #8\n"); + SetZN8("r0"); + break; + + case 0xF8: // MOV X,dp + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 1); + ot(" mov spc_x,r0\n"); + SetZN8("spc_x"); + break; + + case 0xF9: // MOV X,dp+Y + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" add r0,r0,spc_ya,lsr #8\n"); + MemHandler(0, 1, 1); + ot(" mov spc_x,r0\n"); + SetZN8("spc_x"); + break; + + case 0xFA: // MOV dp(dest),dp(src) + ot(" ldrb r0,[spc_pc],#1\n"); + MemHandler(0, 1, 0); + ot(" ldrb r1,[spc_pc],#1\n"); + MemHandler(1, 1, 1); + break; + + case 0xFB: // MOV Y,dp+X + ot(" ldrb r0,[spc_pc],#1\n"); + ot(" add r0,r0,spc_x\n"); + MemHandler(0, 1, 1); + ot(" and spc_ya,spc_ya,#0xff\n"); + ot(" orr spc_ya,spc_ya,r0,lsl #8\n"); + SetZN8("r0"); + break; + } + + //tmp_epilogue(); + ot(" subs cycles,cycles,#%i\n", S9xAPUCycles[opcode] * one_apu_cycle[current_cycles]); + ot(" ldrgeb opcode,[spc_pc],#1\n"); + flush_buffer(); + ot(" ldrge pc,[opcodes,opcode,lsl #2]\n"); + ot(" b spc700End\n"); + + printf("\b\b"); + } + + + ot("\n\n"); + +} + + +void printJumpTable(int apu_cycles) { + int i; + ot("@ -------------------------- Jump Table %i --------------------------\n", apu_cycles); + ot("Spc700JumpTab_%i:\n", apu_cycles); + + for (i=0; i < 0x100; i++) + { + if ((i&7)==0) ot(" .long "); + + ot("Apu%02X_%i", i, apu_cycles); + + if ((i&7)==7) ot(" @ %02x\n",i-7); + else if (i+1 < 0x100) ot(", "); + } + +} + +int main() +{ + printf("\n notaz's SPC700 Emulator v%s - Core Creator\n\n", VERSION); + + // Open the assembly file + AsmFile=fopen("spc700a.s", "wt"); if (AsmFile==NULL) return 1; + + ot("@ notaz's SPC700 Emulator v%s - Assembler Output\n\n", VERSION); + ot("@ (c) Copyright 2006 notaz, All rights reserved.\n\n"); + ot("@ Modified by bitrider 2010 - 2011\n\n"); + ot("@ this is a rewrite of spc700.cpp in ARM asm, inspired by other asm CPU cores like\n"); + ot("@ Cyclone and DrZ80. It is meant to be used in Snes9x emulator ports for ARM platforms.\n\n"); + ot("@ the code is released under Snes9x license. See spcgen.c or any other source file\n@ from Snes9x source tree.\n\n\n"); + + PrintFramework(); + + ot(" .align 4\n"); + + for (current_cycles=0; current_cycles < (sizeof(one_apu_cycle) / sizeof(int)); current_cycles++) { + printOpcodes(one_apu_cycle[current_cycles]); + printJumpTable(one_apu_cycle[current_cycles]); + } + + + fclose(AsmFile); AsmFile=NULL; + + printf("Assembling...\n"); + // Assemble the file + //system("as -marmv4t -mthumb-interwork -o spc700a.o spc700a.S"); + printf("Done!\n\n"); + + return 0; +} diff --git a/src/spc700/spcgen.dsp b/src/spc700/spcgen.dsp new file mode 100644 index 0000000..a6bf264 --- /dev/null +++ b/src/spc700/spcgen.dsp @@ -0,0 +1,88 @@ +# Microsoft Developer Studio Project File - Name="spcgen" - Package Owner=<4> +# Microsoft Developer Studio Generated Build File, Format Version 6.00 +# ** DO NOT EDIT ** + +# TARGTYPE "Win32 (x86) Console Application" 0x0103 + +CFG=spcgen - Win32 Debug +!MESSAGE This is not a valid makefile. To build this project using NMAKE, +!MESSAGE use the Export Makefile command and run +!MESSAGE +!MESSAGE NMAKE /f "spcgen.mak". +!MESSAGE +!MESSAGE You can specify a configuration when running NMAKE +!MESSAGE by defining the macro CFG on the command line. For example: +!MESSAGE +!MESSAGE NMAKE /f "spcgen.mak" CFG="spcgen - Win32 Debug" +!MESSAGE +!MESSAGE Possible choices for configuration are: +!MESSAGE +!MESSAGE "spcgen - Win32 Release" (based on "Win32 (x86) Console Application") +!MESSAGE "spcgen - Win32 Debug" (based on "Win32 (x86) Console Application") +!MESSAGE + +# Begin Project +# PROP AllowPerConfigDependencies 0 +# PROP Scc_ProjName "" +# PROP Scc_LocalPath "" +CPP=cl.exe +RSC=rc.exe + +!IF "$(CFG)" == "spcgen - Win32 Release" + +# PROP BASE Use_MFC 0 +# PROP BASE Use_Debug_Libraries 0 +# PROP BASE Output_Dir "Release" +# PROP BASE Intermediate_Dir "Release" +# PROP BASE Target_Dir "" +# PROP Use_MFC 0 +# PROP Use_Debug_Libraries 0 +# PROP Output_Dir "Release" +# PROP Intermediate_Dir "Release" +# PROP Target_Dir "" +# ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c +# ADD CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /c +# ADD BASE RSC /l 0x809 /d "NDEBUG" +# ADD RSC /l 0x809 /d "NDEBUG" +BSC32=bscmake.exe +# ADD BASE BSC32 /nologo +# ADD BSC32 /nologo +LINK32=link.exe +# ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /machine:I386 +# ADD LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /machine:I386 + +!ELSEIF "$(CFG)" == "spcgen - Win32 Debug" + +# PROP BASE Use_MFC 0 +# PROP BASE Use_Debug_Libraries 1 +# PROP BASE Output_Dir "Debug" +# PROP BASE Intermediate_Dir "Debug" +# PROP BASE Target_Dir "" +# PROP Use_MFC 0 +# PROP Use_Debug_Libraries 1 +# PROP Output_Dir "Debug" +# PROP Intermediate_Dir "Debug" +# PROP Target_Dir "" +# ADD BASE CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c +# ADD CPP /nologo /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /YX /FD /GZ /c +# ADD BASE RSC /l 0x809 /d "_DEBUG" +# ADD RSC /l 0x809 /d "_DEBUG" +BSC32=bscmake.exe +# ADD BASE BSC32 /nologo +# ADD BSC32 /nologo +LINK32=link.exe +# ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /debug /machine:I386 /pdbtype:sept +# ADD LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /debug /machine:I386 /pdbtype:sept + +!ENDIF + +# Begin Target + +# Name "spcgen - Win32 Release" +# Name "spcgen - Win32 Debug" +# Begin Source File + +SOURCE=.\spcgen.c +# End Source File +# End Target +# End Project diff --git a/src/spc700/spcgen.dsw b/src/spc700/spcgen.dsw new file mode 100644 index 0000000..7b947fc --- /dev/null +++ b/src/spc700/spcgen.dsw @@ -0,0 +1,29 @@ +Microsoft Developer Studio Workspace File, Format Version 6.00 +# WARNING: DO NOT EDIT OR DELETE THIS WORKSPACE FILE! + +############################################################################### + +Project: "spcgen"=.\spcgen.dsp - Package Owner=<4> + +Package=<5> +{{{ +}}} + +Package=<4> +{{{ +}}} + +############################################################################### + +Global: + +Package=<5> +{{{ +}}} + +Package=<3> +{{{ +}}} + +############################################################################### + diff --git a/src/spc700/spcgen.ncb b/src/spc700/spcgen.ncb new file mode 100644 index 0000000..22b2108 Binary files /dev/null and b/src/spc700/spcgen.ncb differ diff --git a/src/spc700/spcgen.opt b/src/spc700/spcgen.opt new file mode 100644 index 0000000..673f065 Binary files /dev/null and b/src/spc700/spcgen.opt differ diff --git a/src/spc700/spcgen.plg b/src/spc700/spcgen.plg new file mode 100644 index 0000000..8db8f5e --- /dev/null +++ b/src/spc700/spcgen.plg @@ -0,0 +1,32 @@ + + +
+
Build Log

+

+--------------------Configuration: spcgen - Win32 Debug--------------------
+

+
Command Lines

+Creating temporary file "C:\DOCUME~1\Dave\LOCALS~1\Temp\RSP2C.tmp" with contents
+[
+/nologo /MLd /W3 /Gm /GX /ZI /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /D "_MBCS" /Fp"Debug/spcgen.pch" /YX /Fo"Debug/" /Fd"Debug/" /FD /GZ /c 
+"C:\Downloads\squidgesnes0392src\squidgesnes\spc700\spcgen.c"
+]
+Creating command line "cl.exe @C:\DOCUME~1\Dave\LOCALS~1\Temp\RSP2C.tmp" 
+Creating temporary file "C:\DOCUME~1\Dave\LOCALS~1\Temp\RSP2E.tmp" with contents
+[
+kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /incremental:yes /pdb:"Debug/spcgen.pdb" /debug /machine:I386 /out:"Debug/spcgen.exe" /pdbtype:sept 
+.\Debug\spcgen.obj
+]
+Creating command line "link.exe @C:\DOCUME~1\Dave\LOCALS~1\Temp\RSP2E.tmp"
+
Output Window

+Compiling...
+spcgen.c
+Linking...
+
+
+
+
Results

+spcgen.exe - 0 error(s), 0 warning(s)
+
+ + diff --git a/src/spc700a.s b/src/spc700a.s new file mode 100644 index 0000000..6a0fb41 --- /dev/null +++ b/src/spc700a.s @@ -0,0 +1,28366 @@ +@ notaz's SPC700 Emulator v0.12 - Assembler Output + +@ (c) Copyright 2006 notaz, All rights reserved. + +@ Modified by bitrider 2010 + +@ this is a rewrite of spc700.cpp in ARM asm, inspired by other asm CPU cores like +@ Cyclone and DrZ80. It is meant to be used in Snes9x emulator ports for ARM platforms. + +@ the code is released under Snes9x license. See spcgen.c or any other source file +@ from Snes9x source tree. + + + .extern IAPU + .extern CPU @ for STOP and SLEEP + .extern S9xAPUGetByte + .extern S9xAPUSetByte + .extern S9xAPUGetByteZ + .extern S9xAPUSetByteZ + + .extern S9xGetAPUDSP + .extern S9xSetAPUDSP + .extern S9xSetAPUControl + .extern S9xAPUSetByteFFC0 + .extern S9xAPUSetByteFFtoF0 + .global spc700_execute @ int cycles + .global Spc700JumpTab_13 + .global Spc700JumpTab_14 + .global Spc700JumpTab_15 + .global Spc700JumpTab_21 + + opcode .req r3 + cycles .req r4 + context .req r5 + opcodes .req r6 + spc_pc .req r7 + spc_ya .req r8 + spc_p .req r9 + spc_x .req r10 + spc_s .req r11 + spc_ram .req r12 + + .equ iapu_directpage, 0x00 + .equ iapu_ram, 0x44 + .equ iapu_extraram, 0x48 + .equ iapu_allregs_load, 0x30 + .equ iapu_allregs_save, 0x34 + + .equ flag_c, 0x01 + .equ flag_z, 0x02 + .equ flag_i, 0x04 + .equ flag_h, 0x08 + .equ flag_b, 0x10 + .equ flag_d, 0x20 + .equ flag_o, 0x40 + .equ flag_n, 0x80 + + .equ cpu_apu_executing, 124 + +@ --------------------------- Framework -------------------------- + .align 4 +spc700_execute: @ int cycles + stmfd sp!,{r4-r11,lr} + ldr context,=IAPU @ Pointer to SIAPU struct + mov cycles,r0 @ Cycles + add r0,context,#iapu_allregs_load + ldmia r0,{opcodes,spc_pc,spc_ya,spc_p,spc_x,spc_ram} + ldrb opcode,[spc_pc],#1 @ Fetch first opcode + mov spc_s,spc_x,lsr #8 + and spc_x,spc_x,#0xff + + ldr pc,[opcodes,opcode,lsl #2] @ Jump to opcode handler + + +@ We come back here after execution +spc700End: + orr spc_x,spc_x,spc_s,lsl #8 + add r0,context,#iapu_allregs_save + stmia r0,{spc_pc,spc_ya,spc_p,spc_x} + mov r0,cycles + ldmfd sp!,{r4-r11,pc} + + .ltorg + +GetAPUDSP: + ldrb r1, [spc_ram, #0xf2] + mov r0, #0 + and r2, r1, #0X0f + cmp r2, #0x08 + bxeq lr + cmp r2, #0x09 + ldrne r2, .APU_DSP + and r1, r1, #0X7f + ldrneb r0, [r2, r1] + bxne lr + ldr r2, .SOUNDDATA_CHANNELS + mov r1, r1, lsr #4 + ldr r0, [r2, r1, asl #8] + add r1, r2, r1, asl #8 + cmp r0, #0 + ldrneh r1, [r1, #0x48] + bxeq lr + and r0, r1, #0xff + orr r0, r0, r1, lsr #8 + bx lr +.APU_DSP: + .long APU + 0x0b +.SOUNDDATA_CHANNELS: + .long SoundData + 0x30 + .align 4 + + +Apu00_13: + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu01_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1e] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu02_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x01 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu03_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu04_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu05_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu06_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu07_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu08_13: + ldrb r0,[spc_pc],#1 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu09_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0, r0, r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0A_13: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orrne spc_p,spc_p,#flag_c + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0B_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0C_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0D_13: + mov r0,spc_p,lsr #24 + and r1,r0,#0x80 + tst r0,r0 + orreq r1,r1,#flag_z + and spc_p,spc_p,#0x7d @ clear N & Z + orr spc_p,spc_p,r1 + add r1,spc_ram,spc_s + strb spc_p,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,r0,lsl #24 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0E_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r2,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r2,lsl #24 + orr r0,r0,spc_ya + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0F_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + mov r0,spc_p,lsr #24 + and r1,r0,#0x80 + tst r0,r0 + orrne r1,r1,#flag_z + and spc_p,spc_p,#0x7d @ clear N & Z + orr spc_p,spc_p,r1 + add r1,spc_ram,spc_s + strb spc_p,[r1,#0x100] + sub spc_s,spc_s,#1 + orr spc_p,spc_p,#flag_b + bic spc_p,spc_p,#flag_i + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x20] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu10_13: + tst spc_p,#0x80000000 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu11_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1c] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu12_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x01 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu13_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu14_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu15_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu16_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu17_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu18_13: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + orr r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu19_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0, r3, r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1A_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + sub r0,r1,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + stmfd sp!,{r0} + ldrb r1,[spc_pc] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldmfd sp!,{r0} + mov r0,r0,lsr #8 + ldrb r1,[spc_pc],#1 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1B_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r3, r0 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1C_13: + tst spc_ya,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and r0,spc_ya,#0x7f + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1D_13: + sub spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1E_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1F_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + sub sp,sp,#8 + str r0,[sp,#4] + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + str r0,[sp] + ldr r0,[sp,#4] + add r0,r0,#1 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + ldr r1,[sp],#8 + orr r0,r1,r0,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu20_13: + bic spc_p,spc_p,#flag_d + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + str spc_ram,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu21_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1a] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu22_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x02 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu23_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x02 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu24_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu25_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu26_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu27_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu28_13: + ldrb r0,[spc_pc],#1 + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu29_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2A_13: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orreq spc_p,spc_p,#flag_c + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2B_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2C_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2D_13: + add r1,spc_ram,spc_s + strb spc_ya,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2E_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff + cmp r0,r1 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2F_13: + ldrsb r0,[spc_pc],#1 + add spc_pc,spc_pc,r0 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu30_13: + tst spc_p,#0x80000000 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu31_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x18] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu32_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x02 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu33_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x02 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu34_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu35_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu36_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu37_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu38_13: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + and r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu39_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3A_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + add r0,r1,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + stmfd sp!,{r0} + ldrb r1,[spc_pc] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldmfd sp!,{r0} + mov r0,r0,lsr #8 + ldrb r1,[spc_pc],#1 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3B_13: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3C_13: + and r0,spc_ya,#0xff + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3D_13: + add spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3E_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3F_13: + ldrb r2,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r2,r2,r14,lsl #8 + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + add spc_pc,spc_ram,r2 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu40_13: + orr spc_p,spc_p,#flag_d + add r0,spc_ram,#0x100 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + str r0,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu41_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x16] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu42_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x04 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu43_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x04 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu44_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu45_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu46_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu47_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu48_13: + ldrb r0,[spc_pc],#1 + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu49_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4A_13: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + biceq spc_p,spc_p,#flag_c + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4B_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4C_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4D_13: + add r1,spc_ram,spc_s + strb spc_x,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4E_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r2,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r2,lsl #24 + bic r0,r0,spc_ya + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4F_13: + ldrb r2,[spc_pc],#1 + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + add spc_pc,spc_ram,r2 + add spc_pc,spc_pc,#0xff00 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu50_13: + tst spc_p,#0x00000040 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu51_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x14] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu52_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x04 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu53_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x04 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu54_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu55_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu56_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu57_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu58_13: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + eor r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu59_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5A_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + subs r0,spc_ya,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5B_13: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5C_13: + and r0,spc_ya,#0xff + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5D_13: + and spc_x,spc_ya,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5E_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5F_13: + ldrb r0, [spc_pc], #1 + ldrb r14, [spc_pc], #1 + add spc_pc, r0, spc_ram + add spc_pc, spc_pc, r14, lsl #8 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu60_13: + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu61_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x12] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu62_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x08 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu63_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x08 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu64_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu65_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu66_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu67_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu68_13: + ldrb r0,[spc_pc],#1 + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu69_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_x,spc_x,r0,lsl #24 + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_x,lsr #24 + subs r14,r0,r1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6A_13: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + bicne spc_p,spc_p,#flag_c + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6B_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6C_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6D_13: + mov r0,spc_ya,lsr #8 + add r1,spc_ram,spc_s + strb r0,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6E_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + sub r0,r0,#1 + tst r0,r0 + addeq spc_pc,spc_pc,#1 + ldrnesb r2,[spc_pc],#1 + addne spc_pc,spc_pc,r2 + subne cycles,cycles,#26 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6F_13: + add r1,spc_ram,spc_s + ldrb r0,[r1,#(0xff + 2)] + ldrb r1,[r1,#(0x100 + 2)] + add spc_s,spc_s,#2 + orr r0,r0,r1,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu70_13: + tst spc_p,#0x00000040 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu71_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x10] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu72_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x08 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu73_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x08 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu74_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu75_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu76_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu77_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu78_13: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + subs r14,r0,r1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu79_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_x,spc_x,r0,lsl #24 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_x,lsr #24 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7A_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + add r0,spc_ya,r1 + movs r2,r0,lsr #16 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + bic r2,r0,#0x00ff0000 + eor r3,r1,r2 + eor r14,spc_ya,r1 + mvn r14,r14 + and r14,r14,r3 + tst r14,#0x8000 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7B_13: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7C_13: + and r0,spc_ya,#0xff + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7D_13: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,spc_x + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7E_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7F_13: + add spc_p,spc_ram,spc_s + ldrb spc_p,[spc_p,#(0x100 + 1)] + add spc_s,spc_s,#1 + and r0,spc_p,#(flag_z|flag_n) + eor r0,r0,#flag_z + orr spc_p,spc_p,r0,lsl #24 + tst spc_p,#flag_d + addne r0,spc_ram,#0x100 + moveq r0,spc_ram + str r0,[context,#iapu_directpage] + add r1,spc_ram,spc_s + ldrb r0,[r1,#(0xff + 2)] + ldrb r1,[r1,#(0x100 + 2)] + add spc_s,spc_s,#2 + orr r0,r0,r1,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu80_13: + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu81_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xe] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu82_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x10 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu83_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x10 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu84_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu85_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu86_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu87_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu88_13: + ldrb r0,[spc_pc],#1 + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu89_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r2,r0,r3 + movs r14, spc_p, lsr #1 + adc r0, r0, r3 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r3 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8A_13: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + eorne spc_p,spc_p,#flag_c + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8B_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8C_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8D_13: + ldrb r0,[spc_pc],#1 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8E_13: + add spc_p,spc_ram,spc_s + ldrb spc_p,[spc_p,#(0x100 + 1)] + add spc_s,spc_s,#1 + and r0,spc_p,#(flag_z|flag_n) + eor r0,r0,#flag_z + orr spc_p,spc_p,r0,lsl #24 + tst spc_p,#flag_d + addne r0,spc_ram,#0x100 + moveq r0,spc_ram + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + str r0,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8F_13: + ldrb r0,[spc_pc],#1 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu90_13: + tst spc_p,#0x00000001 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu91_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xc] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu92_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x10 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu93_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x10 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu94_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu95_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu96_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu97_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu98_13: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + eor r2,r0,r1 + movs r14, spc_p, lsr #1 + adc r0, r0, r1 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r1 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu99_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r2,r0,r3 + movs r14, spc_p, lsr #1 + adc r0, r0, r3 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r3 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9A_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + subs r0,spc_ya,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + mov r2,r0,lsl #16 + mov r2,r2,lsr #16 + eor r3,spc_ya,r2 + eor r14,spc_ya,r1 + and r14,r14,r3 + tst r14,#0x8000 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r1 + tst r14,#0x10 + bicne spc_p,spc_p,#flag_h + orreq spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9B_13: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9C_13: + and r0,spc_ya,#0xff + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9D_13: + mov spc_x,spc_s + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9E_13: + tst spc_x,spc_x @ div by 0? + orreq spc_ya,spc_ya,#0xff00 + orreq spc_ya,spc_ya,#0x00ff + orreq spc_p,spc_p,#flag_o + beq 1002f + bic spc_p,spc_p,#flag_o +@ Divide spc_ya by spc_x + mov r3,#0 + mov r1,spc_x + +@ Shift up divisor till it's just less than numerator +cmp spc_ya,r1,lsl #8 +movge r1,r1,lsl #8 +cmp spc_ya,r1,lsl #4 +movge r1,r1,lsl #4 +cmp spc_ya,r1,lsl #2 +movge r1,r1,lsl #2 +cmp spc_ya,r1,lsl #1 +movge r1,r1,lsl #1 +1001: + cmp spc_ya,r1 + adc r3,r3,r3 ;@ Double r3 and add 1 if carry set + subcs spc_ya,spc_ya,r1 + teq r1,spc_x + movne r1,r1,lsr #1 + bne 1001b + + and spc_ya,spc_ya,#0xff + and r3,r3,#0xff + orr spc_ya,r3,spc_ya,lsl #8 +1002: + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#156 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9F_13: + and r0,spc_ya,#0xff + mov r1,r0,lsl #28 + orr r0,r1,r0,lsl #20 + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0,lsr #24 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA0_13: + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,#flag_i + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA1_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xa] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA2_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x20 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA3_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x20 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA4_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA5_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA6_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA7_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA8_13: + ldrb r0,[spc_pc],#1 + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA9_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + movs r14,spc_p,lsr #1 + sbcs r2,r0,r3 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r3 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAA_13: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAB_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAC_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAD_13: + ldrb r0,[spc_pc],#1 + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAE_13: + add r0,spc_ram,spc_s + ldrb r0,[r0,#(0x100 + 1)] + add spc_s,spc_s,#1 + and spc_ya,spc_ya,#0xff00 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAF_13: + mov r0,spc_ya + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + add spc_x,spc_x,#1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB0_13: + tst spc_p,#0x00000001 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB1_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x8] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB2_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x20 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB3_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x20 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB4_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB5_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB6_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB7_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB8_13: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + movs r14,spc_p,lsr #1 + sbcs r2,r0,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r1 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB9_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + movs r14,spc_p,lsr #1 + sbcs r2,r0,r3 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r3 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBA_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1, [spc_pc],#1 + mov spc_ya, r0 + add r0, r1, #1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBB_13: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBC_13: + and r0,spc_ya,#0xff + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBD_13: + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + mov spc_s,spc_x + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBE_13: + and r0,spc_ya,#0xff + and r1,spc_ya,#0x0f + cmp r1,#9 + subhi r0,r0,#6 + tstls spc_p,#flag_h + subeq r0,r0,#6 + cmp r0,#0x9f + bhi 2001f + tst spc_p,#flag_c + beq 2001f + orr spc_p,spc_p,#flag_c + b 2002f +2001: + sub r0,r0,#0x60 + bic spc_p,spc_p,#flag_c +2002: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBF_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + add spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC0_13: + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#flag_i + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC1_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x6] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC2_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x40 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC3_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x40 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC4_13: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC5_13: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC6_13: + mov r0,spc_ya + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC7_13: + ldrb r1,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r1,r1,spc_x + and r1,r1,#0xff + ldrb r1,[r14,r1]! + ldrb r14,[r14,#1] + orr r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#91 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC8_13: + ldrb r0,[spc_pc],#1 + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC9_13: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_x + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCA_13: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r2,#1 + mov r2,r2,lsl r1 + tst spc_p,#flag_c + orrne r0,r0,r2 + biceq r0,r0,r2 + bic r1, r3, #0xe000 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCB_13: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCC_13: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_ya,lsr #8 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCD_13: + ldrb spc_x,[spc_pc],#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCE_13: + add spc_x,spc_ram,spc_s + ldrb spc_x,[spc_x,#(0x100 + 1)] + add spc_s,spc_s,#1 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCF_13: + mov r0,spc_ya,lsr #8 + and spc_ya,spc_ya,#0xff + mul spc_ya,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#117 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD0_13: + tst spc_p,#0xFF000000 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD1_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x4] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD2_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x40 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD3_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x40 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD4_13: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD5_13: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,spc_x + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD6_13: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,spc_ya, lsr #8 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD7_13: + ldrb r1,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r1,[r14,r1]! + ldrb r14,[r14,#1] + add r1,r1,spc_ya,lsr #8 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#91 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD8_13: + ldrb r1,[spc_pc],#1 + mov r0,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD9_13: + ldrb r1,[spc_pc],#1 + mov r0,spc_x + add r1,r1,spc_ya,lsr #8 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDA_13: + ldrb r1,[spc_pc] + mov r0,spc_ya + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDB_13: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDC_13: + mov r0,spc_ya,lsr #8 + sub r0,r0,#1 + and r0,r0,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDD_13: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,spc_ya,lsr #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDE_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff + cmp r0,r1 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + addne spc_pc,spc_pc,r0 + subne cycles,cycles,#26 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDF_13: + and r0,spc_ya,#0xff + and r1,spc_ya,#0x0f + cmp r1,#9 + addhi r0,r0,#6 + bls 3001f + cmphi r0,#0xf0 + orrhi spc_p,spc_p,#flag_c + b 3002f +3001: + tst spc_p,#flag_h + addne r0,r0,#6 + beq 3002f + cmp r0,#0xf0 + orrhi spc_p,spc_p,#flag_c +3002: + tst spc_p,#flag_c + addne r0,r0,#0x60 + bne 3003f + cmp r0,#0x9f + addhi r0,r0,#0x60 + orrhi spc_p,spc_p,#flag_c + bicls spc_p,spc_p,#flag_c +3003: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE0_13: + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#(flag_o|flag_h) + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE1_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x2] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE2_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x80 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE3_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#26 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE4_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE5_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE6_13: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE7_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE8_13: + ldrb r0,[spc_pc],#1 + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE9_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEA_13: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r2,#1 + mov r2,r2,lsl r1 + eor r0,r0,r2 + bic r1, r3, #0xe000 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEB_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEC_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuED_13: + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + eor spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEE_13: + add r0,spc_ram,spc_s + ldrb r0,[r0,#(0x100 + 1)] + add spc_s,spc_s,#1 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEF_13: + ldr r0, 5001f + mov r1,#0 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + str r1,[r0,#cpu_apu_executing] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End +5001: + .long CPU + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF0_13: + tst spc_p,#0xFF000000 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF1_13: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x0] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#104 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF2_13: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x80 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF3_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#26 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF4_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF5_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF6_13: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF7_13: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#78 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF8_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF9_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFA_13: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#65 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFB_13: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFC_13: + mov r0,spc_ya,lsr #8 + add r0,r0,#1 + and r0,r0,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFD_13: + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,spc_ya,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#26 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFE_13: + sub spc_ya,spc_ya,#0x100 + mov spc_ya,spc_ya,lsl #16 + mov spc_ya,spc_ya,lsr #16 + movs r0,spc_ya,lsr #8 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + addne spc_pc,spc_pc,r0 + subne cycles,cycles,#26 + subs cycles,cycles,#52 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFF_13: + ldr r0, 5001f + mov r1,#0 + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + str r1,[r0,#cpu_apu_executing] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End +5001: + .long CPU + subs cycles,cycles,#39 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +@ -------------------------- Jump Table 13 -------------------------- +Spc700JumpTab_13: + .long Apu00_13, Apu01_13, Apu02_13, Apu03_13, Apu04_13, Apu05_13, Apu06_13, Apu07_13 @ 00 + .long Apu08_13, Apu09_13, Apu0A_13, Apu0B_13, Apu0C_13, Apu0D_13, Apu0E_13, Apu0F_13 @ 08 + .long Apu10_13, Apu11_13, Apu12_13, Apu13_13, Apu14_13, Apu15_13, Apu16_13, Apu17_13 @ 10 + .long Apu18_13, Apu19_13, Apu1A_13, Apu1B_13, Apu1C_13, Apu1D_13, Apu1E_13, Apu1F_13 @ 18 + .long Apu20_13, Apu21_13, Apu22_13, Apu23_13, Apu24_13, Apu25_13, Apu26_13, Apu27_13 @ 20 + .long Apu28_13, Apu29_13, Apu2A_13, Apu2B_13, Apu2C_13, Apu2D_13, Apu2E_13, Apu2F_13 @ 28 + .long Apu30_13, Apu31_13, Apu32_13, Apu33_13, Apu34_13, Apu35_13, Apu36_13, Apu37_13 @ 30 + .long Apu38_13, Apu39_13, Apu3A_13, Apu3B_13, Apu3C_13, Apu3D_13, Apu3E_13, Apu3F_13 @ 38 + .long Apu40_13, Apu41_13, Apu42_13, Apu43_13, Apu44_13, Apu45_13, Apu46_13, Apu47_13 @ 40 + .long Apu48_13, Apu49_13, Apu4A_13, Apu4B_13, Apu4C_13, Apu4D_13, Apu4E_13, Apu4F_13 @ 48 + .long Apu50_13, Apu51_13, Apu52_13, Apu53_13, Apu54_13, Apu55_13, Apu56_13, Apu57_13 @ 50 + .long Apu58_13, Apu59_13, Apu5A_13, Apu5B_13, Apu5C_13, Apu5D_13, Apu5E_13, Apu5F_13 @ 58 + .long Apu60_13, Apu61_13, Apu62_13, Apu63_13, Apu64_13, Apu65_13, Apu66_13, Apu67_13 @ 60 + .long Apu68_13, Apu69_13, Apu6A_13, Apu6B_13, Apu6C_13, Apu6D_13, Apu6E_13, Apu6F_13 @ 68 + .long Apu70_13, Apu71_13, Apu72_13, Apu73_13, Apu74_13, Apu75_13, Apu76_13, Apu77_13 @ 70 + .long Apu78_13, Apu79_13, Apu7A_13, Apu7B_13, Apu7C_13, Apu7D_13, Apu7E_13, Apu7F_13 @ 78 + .long Apu80_13, Apu81_13, Apu82_13, Apu83_13, Apu84_13, Apu85_13, Apu86_13, Apu87_13 @ 80 + .long Apu88_13, Apu89_13, Apu8A_13, Apu8B_13, Apu8C_13, Apu8D_13, Apu8E_13, Apu8F_13 @ 88 + .long Apu90_13, Apu91_13, Apu92_13, Apu93_13, Apu94_13, Apu95_13, Apu96_13, Apu97_13 @ 90 + .long Apu98_13, Apu99_13, Apu9A_13, Apu9B_13, Apu9C_13, Apu9D_13, Apu9E_13, Apu9F_13 @ 98 + .long ApuA0_13, ApuA1_13, ApuA2_13, ApuA3_13, ApuA4_13, ApuA5_13, ApuA6_13, ApuA7_13 @ a0 + .long ApuA8_13, ApuA9_13, ApuAA_13, ApuAB_13, ApuAC_13, ApuAD_13, ApuAE_13, ApuAF_13 @ a8 + .long ApuB0_13, ApuB1_13, ApuB2_13, ApuB3_13, ApuB4_13, ApuB5_13, ApuB6_13, ApuB7_13 @ b0 + .long ApuB8_13, ApuB9_13, ApuBA_13, ApuBB_13, ApuBC_13, ApuBD_13, ApuBE_13, ApuBF_13 @ b8 + .long ApuC0_13, ApuC1_13, ApuC2_13, ApuC3_13, ApuC4_13, ApuC5_13, ApuC6_13, ApuC7_13 @ c0 + .long ApuC8_13, ApuC9_13, ApuCA_13, ApuCB_13, ApuCC_13, ApuCD_13, ApuCE_13, ApuCF_13 @ c8 + .long ApuD0_13, ApuD1_13, ApuD2_13, ApuD3_13, ApuD4_13, ApuD5_13, ApuD6_13, ApuD7_13 @ d0 + .long ApuD8_13, ApuD9_13, ApuDA_13, ApuDB_13, ApuDC_13, ApuDD_13, ApuDE_13, ApuDF_13 @ d8 + .long ApuE0_13, ApuE1_13, ApuE2_13, ApuE3_13, ApuE4_13, ApuE5_13, ApuE6_13, ApuE7_13 @ e0 + .long ApuE8_13, ApuE9_13, ApuEA_13, ApuEB_13, ApuEC_13, ApuED_13, ApuEE_13, ApuEF_13 @ e8 + .long ApuF0_13, ApuF1_13, ApuF2_13, ApuF3_13, ApuF4_13, ApuF5_13, ApuF6_13, ApuF7_13 @ f0 + .long ApuF8_13, ApuF9_13, ApuFA_13, ApuFB_13, ApuFC_13, ApuFD_13, ApuFE_13, ApuFF_13 @ f8 + + +Apu00_14: + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu01_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1e] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu02_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x01 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu03_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu04_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu05_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu06_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu07_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu08_14: + ldrb r0,[spc_pc],#1 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu09_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0, r0, r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0A_14: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orrne spc_p,spc_p,#flag_c + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0B_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0C_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0D_14: + mov r0,spc_p,lsr #24 + and r1,r0,#0x80 + tst r0,r0 + orreq r1,r1,#flag_z + and spc_p,spc_p,#0x7d @ clear N & Z + orr spc_p,spc_p,r1 + add r1,spc_ram,spc_s + strb spc_p,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,r0,lsl #24 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0E_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r2,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r2,lsl #24 + orr r0,r0,spc_ya + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0F_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + mov r0,spc_p,lsr #24 + and r1,r0,#0x80 + tst r0,r0 + orrne r1,r1,#flag_z + and spc_p,spc_p,#0x7d @ clear N & Z + orr spc_p,spc_p,r1 + add r1,spc_ram,spc_s + strb spc_p,[r1,#0x100] + sub spc_s,spc_s,#1 + orr spc_p,spc_p,#flag_b + bic spc_p,spc_p,#flag_i + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x20] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu10_14: + tst spc_p,#0x80000000 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu11_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1c] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu12_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x01 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu13_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu14_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu15_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu16_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu17_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu18_14: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + orr r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu19_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0, r3, r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1A_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + sub r0,r1,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + stmfd sp!,{r0} + ldrb r1,[spc_pc] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldmfd sp!,{r0} + mov r0,r0,lsr #8 + ldrb r1,[spc_pc],#1 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1B_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r3, r0 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1C_14: + tst spc_ya,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and r0,spc_ya,#0x7f + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1D_14: + sub spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1E_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1F_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + sub sp,sp,#8 + str r0,[sp,#4] + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + str r0,[sp] + ldr r0,[sp,#4] + add r0,r0,#1 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + ldr r1,[sp],#8 + orr r0,r1,r0,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu20_14: + bic spc_p,spc_p,#flag_d + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + str spc_ram,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu21_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1a] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu22_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x02 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu23_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x02 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu24_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu25_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu26_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu27_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu28_14: + ldrb r0,[spc_pc],#1 + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu29_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2A_14: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orreq spc_p,spc_p,#flag_c + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2B_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2C_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2D_14: + add r1,spc_ram,spc_s + strb spc_ya,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2E_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff + cmp r0,r1 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2F_14: + ldrsb r0,[spc_pc],#1 + add spc_pc,spc_pc,r0 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu30_14: + tst spc_p,#0x80000000 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu31_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x18] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu32_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x02 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu33_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x02 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu34_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu35_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu36_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu37_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu38_14: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + and r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu39_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3A_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + add r0,r1,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + stmfd sp!,{r0} + ldrb r1,[spc_pc] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldmfd sp!,{r0} + mov r0,r0,lsr #8 + ldrb r1,[spc_pc],#1 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3B_14: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3C_14: + and r0,spc_ya,#0xff + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3D_14: + add spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3E_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3F_14: + ldrb r2,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r2,r2,r14,lsl #8 + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + add spc_pc,spc_ram,r2 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu40_14: + orr spc_p,spc_p,#flag_d + add r0,spc_ram,#0x100 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + str r0,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu41_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x16] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu42_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x04 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu43_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x04 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu44_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu45_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu46_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu47_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu48_14: + ldrb r0,[spc_pc],#1 + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu49_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4A_14: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + biceq spc_p,spc_p,#flag_c + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4B_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4C_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4D_14: + add r1,spc_ram,spc_s + strb spc_x,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4E_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r2,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r2,lsl #24 + bic r0,r0,spc_ya + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4F_14: + ldrb r2,[spc_pc],#1 + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + add spc_pc,spc_ram,r2 + add spc_pc,spc_pc,#0xff00 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu50_14: + tst spc_p,#0x00000040 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu51_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x14] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu52_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x04 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu53_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x04 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu54_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu55_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu56_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu57_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu58_14: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + eor r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu59_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5A_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + subs r0,spc_ya,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5B_14: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5C_14: + and r0,spc_ya,#0xff + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5D_14: + and spc_x,spc_ya,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5E_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5F_14: + ldrb r0, [spc_pc], #1 + ldrb r14, [spc_pc], #1 + add spc_pc, r0, spc_ram + add spc_pc, spc_pc, r14, lsl #8 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu60_14: + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu61_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x12] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu62_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x08 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu63_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x08 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu64_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu65_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu66_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu67_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu68_14: + ldrb r0,[spc_pc],#1 + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu69_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_x,spc_x,r0,lsl #24 + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_x,lsr #24 + subs r14,r0,r1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6A_14: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + bicne spc_p,spc_p,#flag_c + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6B_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6C_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6D_14: + mov r0,spc_ya,lsr #8 + add r1,spc_ram,spc_s + strb r0,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6E_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + sub r0,r0,#1 + tst r0,r0 + addeq spc_pc,spc_pc,#1 + ldrnesb r2,[spc_pc],#1 + addne spc_pc,spc_pc,r2 + subne cycles,cycles,#28 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6F_14: + add r1,spc_ram,spc_s + ldrb r0,[r1,#(0xff + 2)] + ldrb r1,[r1,#(0x100 + 2)] + add spc_s,spc_s,#2 + orr r0,r0,r1,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu70_14: + tst spc_p,#0x00000040 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu71_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x10] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu72_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x08 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu73_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x08 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu74_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu75_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu76_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu77_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu78_14: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + subs r14,r0,r1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu79_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_x,spc_x,r0,lsl #24 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_x,lsr #24 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7A_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + add r0,spc_ya,r1 + movs r2,r0,lsr #16 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + bic r2,r0,#0x00ff0000 + eor r3,r1,r2 + eor r14,spc_ya,r1 + mvn r14,r14 + and r14,r14,r3 + tst r14,#0x8000 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7B_14: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7C_14: + and r0,spc_ya,#0xff + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7D_14: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,spc_x + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7E_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7F_14: + add spc_p,spc_ram,spc_s + ldrb spc_p,[spc_p,#(0x100 + 1)] + add spc_s,spc_s,#1 + and r0,spc_p,#(flag_z|flag_n) + eor r0,r0,#flag_z + orr spc_p,spc_p,r0,lsl #24 + tst spc_p,#flag_d + addne r0,spc_ram,#0x100 + moveq r0,spc_ram + str r0,[context,#iapu_directpage] + add r1,spc_ram,spc_s + ldrb r0,[r1,#(0xff + 2)] + ldrb r1,[r1,#(0x100 + 2)] + add spc_s,spc_s,#2 + orr r0,r0,r1,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu80_14: + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu81_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xe] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu82_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x10 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu83_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x10 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu84_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu85_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu86_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu87_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu88_14: + ldrb r0,[spc_pc],#1 + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu89_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r2,r0,r3 + movs r14, spc_p, lsr #1 + adc r0, r0, r3 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r3 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8A_14: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + eorne spc_p,spc_p,#flag_c + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8B_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8C_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8D_14: + ldrb r0,[spc_pc],#1 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8E_14: + add spc_p,spc_ram,spc_s + ldrb spc_p,[spc_p,#(0x100 + 1)] + add spc_s,spc_s,#1 + and r0,spc_p,#(flag_z|flag_n) + eor r0,r0,#flag_z + orr spc_p,spc_p,r0,lsl #24 + tst spc_p,#flag_d + addne r0,spc_ram,#0x100 + moveq r0,spc_ram + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + str r0,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8F_14: + ldrb r0,[spc_pc],#1 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu90_14: + tst spc_p,#0x00000001 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu91_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xc] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu92_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x10 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu93_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x10 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu94_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu95_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu96_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu97_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu98_14: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + eor r2,r0,r1 + movs r14, spc_p, lsr #1 + adc r0, r0, r1 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r1 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu99_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r2,r0,r3 + movs r14, spc_p, lsr #1 + adc r0, r0, r3 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r3 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9A_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + subs r0,spc_ya,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + mov r2,r0,lsl #16 + mov r2,r2,lsr #16 + eor r3,spc_ya,r2 + eor r14,spc_ya,r1 + and r14,r14,r3 + tst r14,#0x8000 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r1 + tst r14,#0x10 + bicne spc_p,spc_p,#flag_h + orreq spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9B_14: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9C_14: + and r0,spc_ya,#0xff + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9D_14: + mov spc_x,spc_s + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9E_14: + tst spc_x,spc_x @ div by 0? + orreq spc_ya,spc_ya,#0xff00 + orreq spc_ya,spc_ya,#0x00ff + orreq spc_p,spc_p,#flag_o + beq 1002f + bic spc_p,spc_p,#flag_o +@ Divide spc_ya by spc_x + mov r3,#0 + mov r1,spc_x + +@ Shift up divisor till it's just less than numerator +cmp spc_ya,r1,lsl #8 +movge r1,r1,lsl #8 +cmp spc_ya,r1,lsl #4 +movge r1,r1,lsl #4 +cmp spc_ya,r1,lsl #2 +movge r1,r1,lsl #2 +cmp spc_ya,r1,lsl #1 +movge r1,r1,lsl #1 +1001: + cmp spc_ya,r1 + adc r3,r3,r3 ;@ Double r3 and add 1 if carry set + subcs spc_ya,spc_ya,r1 + teq r1,spc_x + movne r1,r1,lsr #1 + bne 1001b + + and spc_ya,spc_ya,#0xff + and r3,r3,#0xff + orr spc_ya,r3,spc_ya,lsl #8 +1002: + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9F_14: + and r0,spc_ya,#0xff + mov r1,r0,lsl #28 + orr r0,r1,r0,lsl #20 + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0,lsr #24 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA0_14: + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,#flag_i + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA1_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xa] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA2_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x20 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA3_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x20 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA4_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA5_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA6_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA7_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA8_14: + ldrb r0,[spc_pc],#1 + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA9_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + movs r14,spc_p,lsr #1 + sbcs r2,r0,r3 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r3 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAA_14: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAB_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAC_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAD_14: + ldrb r0,[spc_pc],#1 + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAE_14: + add r0,spc_ram,spc_s + ldrb r0,[r0,#(0x100 + 1)] + add spc_s,spc_s,#1 + and spc_ya,spc_ya,#0xff00 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAF_14: + mov r0,spc_ya + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + add spc_x,spc_x,#1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB0_14: + tst spc_p,#0x00000001 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB1_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x8] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB2_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x20 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB3_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x20 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB4_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB5_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB6_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB7_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB8_14: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + movs r14,spc_p,lsr #1 + sbcs r2,r0,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r1 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB9_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + movs r14,spc_p,lsr #1 + sbcs r2,r0,r3 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r3 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBA_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1, [spc_pc],#1 + mov spc_ya, r0 + add r0, r1, #1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBB_14: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBC_14: + and r0,spc_ya,#0xff + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBD_14: + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + mov spc_s,spc_x + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBE_14: + and r0,spc_ya,#0xff + and r1,spc_ya,#0x0f + cmp r1,#9 + subhi r0,r0,#6 + tstls spc_p,#flag_h + subeq r0,r0,#6 + cmp r0,#0x9f + bhi 2001f + tst spc_p,#flag_c + beq 2001f + orr spc_p,spc_p,#flag_c + b 2002f +2001: + sub r0,r0,#0x60 + bic spc_p,spc_p,#flag_c +2002: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBF_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + add spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC0_14: + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#flag_i + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC1_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x6] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC2_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x40 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC3_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x40 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC4_14: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC5_14: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC6_14: + mov r0,spc_ya + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC7_14: + ldrb r1,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r1,r1,spc_x + and r1,r1,#0xff + ldrb r1,[r14,r1]! + ldrb r14,[r14,#1] + orr r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#98 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC8_14: + ldrb r0,[spc_pc],#1 + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC9_14: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_x + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCA_14: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r2,#1 + mov r2,r2,lsl r1 + tst spc_p,#flag_c + orrne r0,r0,r2 + biceq r0,r0,r2 + bic r1, r3, #0xe000 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCB_14: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCC_14: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_ya,lsr #8 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCD_14: + ldrb spc_x,[spc_pc],#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCE_14: + add spc_x,spc_ram,spc_s + ldrb spc_x,[spc_x,#(0x100 + 1)] + add spc_s,spc_s,#1 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCF_14: + mov r0,spc_ya,lsr #8 + and spc_ya,spc_ya,#0xff + mul spc_ya,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD0_14: + tst spc_p,#0xFF000000 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD1_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x4] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD2_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x40 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD3_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x40 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD4_14: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD5_14: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,spc_x + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD6_14: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,spc_ya, lsr #8 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD7_14: + ldrb r1,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r1,[r14,r1]! + ldrb r14,[r14,#1] + add r1,r1,spc_ya,lsr #8 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#98 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD8_14: + ldrb r1,[spc_pc],#1 + mov r0,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD9_14: + ldrb r1,[spc_pc],#1 + mov r0,spc_x + add r1,r1,spc_ya,lsr #8 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDA_14: + ldrb r1,[spc_pc] + mov r0,spc_ya + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDB_14: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDC_14: + mov r0,spc_ya,lsr #8 + sub r0,r0,#1 + and r0,r0,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDD_14: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,spc_ya,lsr #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDE_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff + cmp r0,r1 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + addne spc_pc,spc_pc,r0 + subne cycles,cycles,#28 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDF_14: + and r0,spc_ya,#0xff + and r1,spc_ya,#0x0f + cmp r1,#9 + addhi r0,r0,#6 + bls 3001f + cmphi r0,#0xf0 + orrhi spc_p,spc_p,#flag_c + b 3002f +3001: + tst spc_p,#flag_h + addne r0,r0,#6 + beq 3002f + cmp r0,#0xf0 + orrhi spc_p,spc_p,#flag_c +3002: + tst spc_p,#flag_c + addne r0,r0,#0x60 + bne 3003f + cmp r0,#0x9f + addhi r0,r0,#0x60 + orrhi spc_p,spc_p,#flag_c + bicls spc_p,spc_p,#flag_c +3003: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE0_14: + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#(flag_o|flag_h) + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE1_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x2] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE2_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x80 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE3_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#28 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE4_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE5_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE6_14: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE7_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE8_14: + ldrb r0,[spc_pc],#1 + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE9_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEA_14: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r2,#1 + mov r2,r2,lsl r1 + eor r0,r0,r2 + bic r1, r3, #0xe000 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEB_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEC_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuED_14: + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + eor spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEE_14: + add r0,spc_ram,spc_s + ldrb r0,[r0,#(0x100 + 1)] + add spc_s,spc_s,#1 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEF_14: + ldr r0, 5001f + mov r1,#0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + str r1,[r0,#cpu_apu_executing] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End +5001: + .long CPU + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF0_14: + tst spc_p,#0xFF000000 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF1_14: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x0] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#112 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF2_14: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x80 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF3_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#28 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF4_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF5_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF6_14: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF7_14: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF8_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF9_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFA_14: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#70 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFB_14: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFC_14: + mov r0,spc_ya,lsr #8 + add r0,r0,#1 + and r0,r0,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFD_14: + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,spc_ya,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#28 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFE_14: + sub spc_ya,spc_ya,#0x100 + mov spc_ya,spc_ya,lsl #16 + mov spc_ya,spc_ya,lsr #16 + movs r0,spc_ya,lsr #8 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + addne spc_pc,spc_pc,r0 + subne cycles,cycles,#28 + subs cycles,cycles,#56 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFF_14: + ldr r0, 5001f + mov r1,#0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + str r1,[r0,#cpu_apu_executing] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End +5001: + .long CPU + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +@ -------------------------- Jump Table 14 -------------------------- +Spc700JumpTab_14: + .long Apu00_14, Apu01_14, Apu02_14, Apu03_14, Apu04_14, Apu05_14, Apu06_14, Apu07_14 @ 00 + .long Apu08_14, Apu09_14, Apu0A_14, Apu0B_14, Apu0C_14, Apu0D_14, Apu0E_14, Apu0F_14 @ 08 + .long Apu10_14, Apu11_14, Apu12_14, Apu13_14, Apu14_14, Apu15_14, Apu16_14, Apu17_14 @ 10 + .long Apu18_14, Apu19_14, Apu1A_14, Apu1B_14, Apu1C_14, Apu1D_14, Apu1E_14, Apu1F_14 @ 18 + .long Apu20_14, Apu21_14, Apu22_14, Apu23_14, Apu24_14, Apu25_14, Apu26_14, Apu27_14 @ 20 + .long Apu28_14, Apu29_14, Apu2A_14, Apu2B_14, Apu2C_14, Apu2D_14, Apu2E_14, Apu2F_14 @ 28 + .long Apu30_14, Apu31_14, Apu32_14, Apu33_14, Apu34_14, Apu35_14, Apu36_14, Apu37_14 @ 30 + .long Apu38_14, Apu39_14, Apu3A_14, Apu3B_14, Apu3C_14, Apu3D_14, Apu3E_14, Apu3F_14 @ 38 + .long Apu40_14, Apu41_14, Apu42_14, Apu43_14, Apu44_14, Apu45_14, Apu46_14, Apu47_14 @ 40 + .long Apu48_14, Apu49_14, Apu4A_14, Apu4B_14, Apu4C_14, Apu4D_14, Apu4E_14, Apu4F_14 @ 48 + .long Apu50_14, Apu51_14, Apu52_14, Apu53_14, Apu54_14, Apu55_14, Apu56_14, Apu57_14 @ 50 + .long Apu58_14, Apu59_14, Apu5A_14, Apu5B_14, Apu5C_14, Apu5D_14, Apu5E_14, Apu5F_14 @ 58 + .long Apu60_14, Apu61_14, Apu62_14, Apu63_14, Apu64_14, Apu65_14, Apu66_14, Apu67_14 @ 60 + .long Apu68_14, Apu69_14, Apu6A_14, Apu6B_14, Apu6C_14, Apu6D_14, Apu6E_14, Apu6F_14 @ 68 + .long Apu70_14, Apu71_14, Apu72_14, Apu73_14, Apu74_14, Apu75_14, Apu76_14, Apu77_14 @ 70 + .long Apu78_14, Apu79_14, Apu7A_14, Apu7B_14, Apu7C_14, Apu7D_14, Apu7E_14, Apu7F_14 @ 78 + .long Apu80_14, Apu81_14, Apu82_14, Apu83_14, Apu84_14, Apu85_14, Apu86_14, Apu87_14 @ 80 + .long Apu88_14, Apu89_14, Apu8A_14, Apu8B_14, Apu8C_14, Apu8D_14, Apu8E_14, Apu8F_14 @ 88 + .long Apu90_14, Apu91_14, Apu92_14, Apu93_14, Apu94_14, Apu95_14, Apu96_14, Apu97_14 @ 90 + .long Apu98_14, Apu99_14, Apu9A_14, Apu9B_14, Apu9C_14, Apu9D_14, Apu9E_14, Apu9F_14 @ 98 + .long ApuA0_14, ApuA1_14, ApuA2_14, ApuA3_14, ApuA4_14, ApuA5_14, ApuA6_14, ApuA7_14 @ a0 + .long ApuA8_14, ApuA9_14, ApuAA_14, ApuAB_14, ApuAC_14, ApuAD_14, ApuAE_14, ApuAF_14 @ a8 + .long ApuB0_14, ApuB1_14, ApuB2_14, ApuB3_14, ApuB4_14, ApuB5_14, ApuB6_14, ApuB7_14 @ b0 + .long ApuB8_14, ApuB9_14, ApuBA_14, ApuBB_14, ApuBC_14, ApuBD_14, ApuBE_14, ApuBF_14 @ b8 + .long ApuC0_14, ApuC1_14, ApuC2_14, ApuC3_14, ApuC4_14, ApuC5_14, ApuC6_14, ApuC7_14 @ c0 + .long ApuC8_14, ApuC9_14, ApuCA_14, ApuCB_14, ApuCC_14, ApuCD_14, ApuCE_14, ApuCF_14 @ c8 + .long ApuD0_14, ApuD1_14, ApuD2_14, ApuD3_14, ApuD4_14, ApuD5_14, ApuD6_14, ApuD7_14 @ d0 + .long ApuD8_14, ApuD9_14, ApuDA_14, ApuDB_14, ApuDC_14, ApuDD_14, ApuDE_14, ApuDF_14 @ d8 + .long ApuE0_14, ApuE1_14, ApuE2_14, ApuE3_14, ApuE4_14, ApuE5_14, ApuE6_14, ApuE7_14 @ e0 + .long ApuE8_14, ApuE9_14, ApuEA_14, ApuEB_14, ApuEC_14, ApuED_14, ApuEE_14, ApuEF_14 @ e8 + .long ApuF0_14, ApuF1_14, ApuF2_14, ApuF3_14, ApuF4_14, ApuF5_14, ApuF6_14, ApuF7_14 @ f0 + .long ApuF8_14, ApuF9_14, ApuFA_14, ApuFB_14, ApuFC_14, ApuFD_14, ApuFE_14, ApuFF_14 @ f8 + + +Apu00_15: + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu01_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1e] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu02_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x01 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu03_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu04_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu05_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu06_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu07_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu08_15: + ldrb r0,[spc_pc],#1 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu09_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0, r0, r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0A_15: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orrne spc_p,spc_p,#flag_c + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0B_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0C_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0D_15: + mov r0,spc_p,lsr #24 + and r1,r0,#0x80 + tst r0,r0 + orreq r1,r1,#flag_z + and spc_p,spc_p,#0x7d @ clear N & Z + orr spc_p,spc_p,r1 + add r1,spc_ram,spc_s + strb spc_p,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,r0,lsl #24 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0E_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r2,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r2,lsl #24 + orr r0,r0,spc_ya + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0F_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + mov r0,spc_p,lsr #24 + and r1,r0,#0x80 + tst r0,r0 + orrne r1,r1,#flag_z + and spc_p,spc_p,#0x7d @ clear N & Z + orr spc_p,spc_p,r1 + add r1,spc_ram,spc_s + strb spc_p,[r1,#0x100] + sub spc_s,spc_s,#1 + orr spc_p,spc_p,#flag_b + bic spc_p,spc_p,#flag_i + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x20] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu10_15: + tst spc_p,#0x80000000 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu11_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1c] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu12_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x01 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu13_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu14_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu15_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu16_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu17_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu18_15: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + orr r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu19_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0, r3, r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1A_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + sub r0,r1,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + stmfd sp!,{r0} + ldrb r1,[spc_pc] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldmfd sp!,{r0} + mov r0,r0,lsr #8 + ldrb r1,[spc_pc],#1 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1B_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r3, r0 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1C_15: + tst spc_ya,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and r0,spc_ya,#0x7f + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1D_15: + sub spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1E_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1F_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + sub sp,sp,#8 + str r0,[sp,#4] + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + str r0,[sp] + ldr r0,[sp,#4] + add r0,r0,#1 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + ldr r1,[sp],#8 + orr r0,r1,r0,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu20_15: + bic spc_p,spc_p,#flag_d + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + str spc_ram,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu21_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1a] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu22_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x02 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu23_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x02 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu24_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu25_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu26_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu27_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu28_15: + ldrb r0,[spc_pc],#1 + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu29_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2A_15: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orreq spc_p,spc_p,#flag_c + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2B_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2C_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2D_15: + add r1,spc_ram,spc_s + strb spc_ya,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2E_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff + cmp r0,r1 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2F_15: + ldrsb r0,[spc_pc],#1 + add spc_pc,spc_pc,r0 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu30_15: + tst spc_p,#0x80000000 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu31_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x18] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu32_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x02 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu33_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x02 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu34_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu35_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu36_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu37_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu38_15: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + and r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu39_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3A_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + add r0,r1,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + stmfd sp!,{r0} + ldrb r1,[spc_pc] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldmfd sp!,{r0} + mov r0,r0,lsr #8 + ldrb r1,[spc_pc],#1 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3B_15: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3C_15: + and r0,spc_ya,#0xff + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3D_15: + add spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3E_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3F_15: + ldrb r2,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r2,r2,r14,lsl #8 + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + add spc_pc,spc_ram,r2 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu40_15: + orr spc_p,spc_p,#flag_d + add r0,spc_ram,#0x100 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + str r0,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu41_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x16] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu42_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x04 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu43_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x04 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu44_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu45_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu46_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu47_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu48_15: + ldrb r0,[spc_pc],#1 + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu49_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4A_15: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + biceq spc_p,spc_p,#flag_c + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4B_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4C_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4D_15: + add r1,spc_ram,spc_s + strb spc_x,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4E_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r2,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r2,lsl #24 + bic r0,r0,spc_ya + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4F_15: + ldrb r2,[spc_pc],#1 + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + add spc_pc,spc_ram,r2 + add spc_pc,spc_pc,#0xff00 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu50_15: + tst spc_p,#0x00000040 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu51_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x14] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu52_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x04 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu53_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x04 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu54_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu55_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu56_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu57_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu58_15: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + eor r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu59_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5A_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + subs r0,spc_ya,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5B_15: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5C_15: + and r0,spc_ya,#0xff + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5D_15: + and spc_x,spc_ya,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5E_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5F_15: + ldrb r0, [spc_pc], #1 + ldrb r14, [spc_pc], #1 + add spc_pc, r0, spc_ram + add spc_pc, spc_pc, r14, lsl #8 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu60_15: + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu61_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x12] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu62_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x08 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu63_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x08 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu64_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu65_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu66_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu67_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu68_15: + ldrb r0,[spc_pc],#1 + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu69_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_x,spc_x,r0,lsl #24 + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_x,lsr #24 + subs r14,r0,r1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6A_15: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + bicne spc_p,spc_p,#flag_c + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6B_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6C_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6D_15: + mov r0,spc_ya,lsr #8 + add r1,spc_ram,spc_s + strb r0,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6E_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + sub r0,r0,#1 + tst r0,r0 + addeq spc_pc,spc_pc,#1 + ldrnesb r2,[spc_pc],#1 + addne spc_pc,spc_pc,r2 + subne cycles,cycles,#30 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6F_15: + add r1,spc_ram,spc_s + ldrb r0,[r1,#(0xff + 2)] + ldrb r1,[r1,#(0x100 + 2)] + add spc_s,spc_s,#2 + orr r0,r0,r1,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu70_15: + tst spc_p,#0x00000040 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu71_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x10] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu72_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x08 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu73_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x08 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu74_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu75_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu76_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu77_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu78_15: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + subs r14,r0,r1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu79_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_x,spc_x,r0,lsl #24 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_x,lsr #24 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7A_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + add r0,spc_ya,r1 + movs r2,r0,lsr #16 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + bic r2,r0,#0x00ff0000 + eor r3,r1,r2 + eor r14,spc_ya,r1 + mvn r14,r14 + and r14,r14,r3 + tst r14,#0x8000 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7B_15: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7C_15: + and r0,spc_ya,#0xff + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7D_15: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,spc_x + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7E_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7F_15: + add spc_p,spc_ram,spc_s + ldrb spc_p,[spc_p,#(0x100 + 1)] + add spc_s,spc_s,#1 + and r0,spc_p,#(flag_z|flag_n) + eor r0,r0,#flag_z + orr spc_p,spc_p,r0,lsl #24 + tst spc_p,#flag_d + addne r0,spc_ram,#0x100 + moveq r0,spc_ram + str r0,[context,#iapu_directpage] + add r1,spc_ram,spc_s + ldrb r0,[r1,#(0xff + 2)] + ldrb r1,[r1,#(0x100 + 2)] + add spc_s,spc_s,#2 + orr r0,r0,r1,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu80_15: + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu81_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xe] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu82_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x10 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu83_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x10 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu84_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu85_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu86_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu87_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu88_15: + ldrb r0,[spc_pc],#1 + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu89_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r2,r0,r3 + movs r14, spc_p, lsr #1 + adc r0, r0, r3 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r3 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8A_15: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + eorne spc_p,spc_p,#flag_c + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8B_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8C_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8D_15: + ldrb r0,[spc_pc],#1 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8E_15: + add spc_p,spc_ram,spc_s + ldrb spc_p,[spc_p,#(0x100 + 1)] + add spc_s,spc_s,#1 + and r0,spc_p,#(flag_z|flag_n) + eor r0,r0,#flag_z + orr spc_p,spc_p,r0,lsl #24 + tst spc_p,#flag_d + addne r0,spc_ram,#0x100 + moveq r0,spc_ram + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + str r0,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8F_15: + ldrb r0,[spc_pc],#1 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu90_15: + tst spc_p,#0x00000001 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu91_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xc] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu92_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x10 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu93_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x10 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu94_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu95_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu96_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu97_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu98_15: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + eor r2,r0,r1 + movs r14, spc_p, lsr #1 + adc r0, r0, r1 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r1 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu99_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r2,r0,r3 + movs r14, spc_p, lsr #1 + adc r0, r0, r3 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r3 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9A_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + subs r0,spc_ya,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + mov r2,r0,lsl #16 + mov r2,r2,lsr #16 + eor r3,spc_ya,r2 + eor r14,spc_ya,r1 + and r14,r14,r3 + tst r14,#0x8000 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r1 + tst r14,#0x10 + bicne spc_p,spc_p,#flag_h + orreq spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9B_15: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9C_15: + and r0,spc_ya,#0xff + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9D_15: + mov spc_x,spc_s + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9E_15: + tst spc_x,spc_x @ div by 0? + orreq spc_ya,spc_ya,#0xff00 + orreq spc_ya,spc_ya,#0x00ff + orreq spc_p,spc_p,#flag_o + beq 1002f + bic spc_p,spc_p,#flag_o +@ Divide spc_ya by spc_x + mov r3,#0 + mov r1,spc_x + +@ Shift up divisor till it's just less than numerator +cmp spc_ya,r1,lsl #8 +movge r1,r1,lsl #8 +cmp spc_ya,r1,lsl #4 +movge r1,r1,lsl #4 +cmp spc_ya,r1,lsl #2 +movge r1,r1,lsl #2 +cmp spc_ya,r1,lsl #1 +movge r1,r1,lsl #1 +1001: + cmp spc_ya,r1 + adc r3,r3,r3 ;@ Double r3 and add 1 if carry set + subcs spc_ya,spc_ya,r1 + teq r1,spc_x + movne r1,r1,lsr #1 + bne 1001b + + and spc_ya,spc_ya,#0xff + and r3,r3,#0xff + orr spc_ya,r3,spc_ya,lsl #8 +1002: + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#180 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9F_15: + and r0,spc_ya,#0xff + mov r1,r0,lsl #28 + orr r0,r1,r0,lsl #20 + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0,lsr #24 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA0_15: + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,#flag_i + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA1_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xa] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA2_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x20 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA3_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x20 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA4_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA5_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA6_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA7_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA8_15: + ldrb r0,[spc_pc],#1 + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA9_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + movs r14,spc_p,lsr #1 + sbcs r2,r0,r3 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r3 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAA_15: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAB_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAC_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAD_15: + ldrb r0,[spc_pc],#1 + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAE_15: + add r0,spc_ram,spc_s + ldrb r0,[r0,#(0x100 + 1)] + add spc_s,spc_s,#1 + and spc_ya,spc_ya,#0xff00 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAF_15: + mov r0,spc_ya + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + add spc_x,spc_x,#1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB0_15: + tst spc_p,#0x00000001 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB1_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x8] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB2_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x20 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB3_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x20 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB4_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB5_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB6_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB7_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB8_15: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + movs r14,spc_p,lsr #1 + sbcs r2,r0,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r1 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB9_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + movs r14,spc_p,lsr #1 + sbcs r2,r0,r3 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r3 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBA_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1, [spc_pc],#1 + mov spc_ya, r0 + add r0, r1, #1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBB_15: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBC_15: + and r0,spc_ya,#0xff + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBD_15: + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + mov spc_s,spc_x + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBE_15: + and r0,spc_ya,#0xff + and r1,spc_ya,#0x0f + cmp r1,#9 + subhi r0,r0,#6 + tstls spc_p,#flag_h + subeq r0,r0,#6 + cmp r0,#0x9f + bhi 2001f + tst spc_p,#flag_c + beq 2001f + orr spc_p,spc_p,#flag_c + b 2002f +2001: + sub r0,r0,#0x60 + bic spc_p,spc_p,#flag_c +2002: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBF_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + add spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC0_15: + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#flag_i + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC1_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x6] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC2_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x40 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC3_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x40 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC4_15: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC5_15: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC6_15: + mov r0,spc_ya + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC7_15: + ldrb r1,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r1,r1,spc_x + and r1,r1,#0xff + ldrb r1,[r14,r1]! + ldrb r14,[r14,#1] + orr r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC8_15: + ldrb r0,[spc_pc],#1 + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC9_15: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_x + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCA_15: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r2,#1 + mov r2,r2,lsl r1 + tst spc_p,#flag_c + orrne r0,r0,r2 + biceq r0,r0,r2 + bic r1, r3, #0xe000 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCB_15: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCC_15: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_ya,lsr #8 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCD_15: + ldrb spc_x,[spc_pc],#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCE_15: + add spc_x,spc_ram,spc_s + ldrb spc_x,[spc_x,#(0x100 + 1)] + add spc_s,spc_s,#1 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCF_15: + mov r0,spc_ya,lsr #8 + and spc_ya,spc_ya,#0xff + mul spc_ya,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#135 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD0_15: + tst spc_p,#0xFF000000 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD1_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x4] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD2_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x40 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD3_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x40 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD4_15: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD5_15: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,spc_x + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD6_15: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,spc_ya, lsr #8 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD7_15: + ldrb r1,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r1,[r14,r1]! + ldrb r14,[r14,#1] + add r1,r1,spc_ya,lsr #8 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD8_15: + ldrb r1,[spc_pc],#1 + mov r0,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD9_15: + ldrb r1,[spc_pc],#1 + mov r0,spc_x + add r1,r1,spc_ya,lsr #8 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDA_15: + ldrb r1,[spc_pc] + mov r0,spc_ya + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDB_15: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDC_15: + mov r0,spc_ya,lsr #8 + sub r0,r0,#1 + and r0,r0,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDD_15: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,spc_ya,lsr #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDE_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff + cmp r0,r1 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + addne spc_pc,spc_pc,r0 + subne cycles,cycles,#30 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDF_15: + and r0,spc_ya,#0xff + and r1,spc_ya,#0x0f + cmp r1,#9 + addhi r0,r0,#6 + bls 3001f + cmphi r0,#0xf0 + orrhi spc_p,spc_p,#flag_c + b 3002f +3001: + tst spc_p,#flag_h + addne r0,r0,#6 + beq 3002f + cmp r0,#0xf0 + orrhi spc_p,spc_p,#flag_c +3002: + tst spc_p,#flag_c + addne r0,r0,#0x60 + bne 3003f + cmp r0,#0x9f + addhi r0,r0,#0x60 + orrhi spc_p,spc_p,#flag_c + bicls spc_p,spc_p,#flag_c +3003: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE0_15: + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#(flag_o|flag_h) + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE1_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x2] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE2_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x80 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE3_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#30 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE4_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE5_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE6_15: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE7_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE8_15: + ldrb r0,[spc_pc],#1 + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE9_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEA_15: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r2,#1 + mov r2,r2,lsl r1 + eor r0,r0,r2 + bic r1, r3, #0xe000 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEB_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEC_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuED_15: + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + eor spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEE_15: + add r0,spc_ram,spc_s + ldrb r0,[r0,#(0x100 + 1)] + add spc_s,spc_s,#1 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEF_15: + ldr r0, 5001f + mov r1,#0 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + str r1,[r0,#cpu_apu_executing] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End +5001: + .long CPU + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF0_15: + tst spc_p,#0xFF000000 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF1_15: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x0] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#120 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF2_15: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x80 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF3_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#30 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF4_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF5_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF6_15: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF7_15: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#90 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF8_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF9_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFA_15: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#75 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFB_15: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFC_15: + mov r0,spc_ya,lsr #8 + add r0,r0,#1 + and r0,r0,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFD_15: + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,spc_ya,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#30 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFE_15: + sub spc_ya,spc_ya,#0x100 + mov spc_ya,spc_ya,lsl #16 + mov spc_ya,spc_ya,lsr #16 + movs r0,spc_ya,lsr #8 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + addne spc_pc,spc_pc,r0 + subne cycles,cycles,#30 + subs cycles,cycles,#60 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFF_15: + ldr r0, 5001f + mov r1,#0 + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + str r1,[r0,#cpu_apu_executing] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End +5001: + .long CPU + subs cycles,cycles,#45 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +@ -------------------------- Jump Table 15 -------------------------- +Spc700JumpTab_15: + .long Apu00_15, Apu01_15, Apu02_15, Apu03_15, Apu04_15, Apu05_15, Apu06_15, Apu07_15 @ 00 + .long Apu08_15, Apu09_15, Apu0A_15, Apu0B_15, Apu0C_15, Apu0D_15, Apu0E_15, Apu0F_15 @ 08 + .long Apu10_15, Apu11_15, Apu12_15, Apu13_15, Apu14_15, Apu15_15, Apu16_15, Apu17_15 @ 10 + .long Apu18_15, Apu19_15, Apu1A_15, Apu1B_15, Apu1C_15, Apu1D_15, Apu1E_15, Apu1F_15 @ 18 + .long Apu20_15, Apu21_15, Apu22_15, Apu23_15, Apu24_15, Apu25_15, Apu26_15, Apu27_15 @ 20 + .long Apu28_15, Apu29_15, Apu2A_15, Apu2B_15, Apu2C_15, Apu2D_15, Apu2E_15, Apu2F_15 @ 28 + .long Apu30_15, Apu31_15, Apu32_15, Apu33_15, Apu34_15, Apu35_15, Apu36_15, Apu37_15 @ 30 + .long Apu38_15, Apu39_15, Apu3A_15, Apu3B_15, Apu3C_15, Apu3D_15, Apu3E_15, Apu3F_15 @ 38 + .long Apu40_15, Apu41_15, Apu42_15, Apu43_15, Apu44_15, Apu45_15, Apu46_15, Apu47_15 @ 40 + .long Apu48_15, Apu49_15, Apu4A_15, Apu4B_15, Apu4C_15, Apu4D_15, Apu4E_15, Apu4F_15 @ 48 + .long Apu50_15, Apu51_15, Apu52_15, Apu53_15, Apu54_15, Apu55_15, Apu56_15, Apu57_15 @ 50 + .long Apu58_15, Apu59_15, Apu5A_15, Apu5B_15, Apu5C_15, Apu5D_15, Apu5E_15, Apu5F_15 @ 58 + .long Apu60_15, Apu61_15, Apu62_15, Apu63_15, Apu64_15, Apu65_15, Apu66_15, Apu67_15 @ 60 + .long Apu68_15, Apu69_15, Apu6A_15, Apu6B_15, Apu6C_15, Apu6D_15, Apu6E_15, Apu6F_15 @ 68 + .long Apu70_15, Apu71_15, Apu72_15, Apu73_15, Apu74_15, Apu75_15, Apu76_15, Apu77_15 @ 70 + .long Apu78_15, Apu79_15, Apu7A_15, Apu7B_15, Apu7C_15, Apu7D_15, Apu7E_15, Apu7F_15 @ 78 + .long Apu80_15, Apu81_15, Apu82_15, Apu83_15, Apu84_15, Apu85_15, Apu86_15, Apu87_15 @ 80 + .long Apu88_15, Apu89_15, Apu8A_15, Apu8B_15, Apu8C_15, Apu8D_15, Apu8E_15, Apu8F_15 @ 88 + .long Apu90_15, Apu91_15, Apu92_15, Apu93_15, Apu94_15, Apu95_15, Apu96_15, Apu97_15 @ 90 + .long Apu98_15, Apu99_15, Apu9A_15, Apu9B_15, Apu9C_15, Apu9D_15, Apu9E_15, Apu9F_15 @ 98 + .long ApuA0_15, ApuA1_15, ApuA2_15, ApuA3_15, ApuA4_15, ApuA5_15, ApuA6_15, ApuA7_15 @ a0 + .long ApuA8_15, ApuA9_15, ApuAA_15, ApuAB_15, ApuAC_15, ApuAD_15, ApuAE_15, ApuAF_15 @ a8 + .long ApuB0_15, ApuB1_15, ApuB2_15, ApuB3_15, ApuB4_15, ApuB5_15, ApuB6_15, ApuB7_15 @ b0 + .long ApuB8_15, ApuB9_15, ApuBA_15, ApuBB_15, ApuBC_15, ApuBD_15, ApuBE_15, ApuBF_15 @ b8 + .long ApuC0_15, ApuC1_15, ApuC2_15, ApuC3_15, ApuC4_15, ApuC5_15, ApuC6_15, ApuC7_15 @ c0 + .long ApuC8_15, ApuC9_15, ApuCA_15, ApuCB_15, ApuCC_15, ApuCD_15, ApuCE_15, ApuCF_15 @ c8 + .long ApuD0_15, ApuD1_15, ApuD2_15, ApuD3_15, ApuD4_15, ApuD5_15, ApuD6_15, ApuD7_15 @ d0 + .long ApuD8_15, ApuD9_15, ApuDA_15, ApuDB_15, ApuDC_15, ApuDD_15, ApuDE_15, ApuDF_15 @ d8 + .long ApuE0_15, ApuE1_15, ApuE2_15, ApuE3_15, ApuE4_15, ApuE5_15, ApuE6_15, ApuE7_15 @ e0 + .long ApuE8_15, ApuE9_15, ApuEA_15, ApuEB_15, ApuEC_15, ApuED_15, ApuEE_15, ApuEF_15 @ e8 + .long ApuF0_15, ApuF1_15, ApuF2_15, ApuF3_15, ApuF4_15, ApuF5_15, ApuF6_15, ApuF7_15 @ f0 + .long ApuF8_15, ApuF9_15, ApuFA_15, ApuFB_15, ApuFC_15, ApuFD_15, ApuFE_15, ApuFF_15 @ f8 + + +Apu00_21: + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu01_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1e] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu02_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x01 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu03_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu04_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu05_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu06_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu07_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu08_21: + ldrb r0,[spc_pc],#1 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu09_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0, r0, r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0A_21: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orrne spc_p,spc_p,#flag_c + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0B_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0C_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0D_21: + mov r0,spc_p,lsr #24 + and r1,r0,#0x80 + tst r0,r0 + orreq r1,r1,#flag_z + and spc_p,spc_p,#0x7d @ clear N & Z + orr spc_p,spc_p,r1 + add r1,spc_ram,spc_s + strb spc_p,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,r0,lsl #24 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0E_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r2,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r2,lsl #24 + orr r0,r0,spc_ya + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu0F_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + mov r0,spc_p,lsr #24 + and r1,r0,#0x80 + tst r0,r0 + orrne r1,r1,#flag_z + and spc_p,spc_p,#0x7d @ clear N & Z + orr spc_p,spc_p,r1 + add r1,spc_ram,spc_s + strb spc_p,[r1,#0x100] + sub spc_s,spc_s,#1 + orr spc_p,spc_p,#flag_b + bic spc_p,spc_p,#flag_i + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x20] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu10_21: + tst spc_p,#0x80000000 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu11_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1c] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu12_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x01 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu13_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu14_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu15_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu16_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu17_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu18_21: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + orr r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu19_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0, r3, r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1A_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + sub r0,r1,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + stmfd sp!,{r0} + ldrb r1,[spc_pc] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldmfd sp!,{r0} + mov r0,r0,lsr #8 + ldrb r1,[spc_pc],#1 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1B_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r3, r0 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1C_21: + tst spc_ya,#0x80 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and r0,spc_ya,#0x7f + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0,lsl #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1D_21: + sub spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1E_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu1F_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + sub sp,sp,#8 + str r0,[sp,#4] + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + str r0,[sp] + ldr r0,[sp,#4] + add r0,r0,#1 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + ldr r1,[sp],#8 + orr r0,r1,r0,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu20_21: + bic spc_p,spc_p,#flag_d + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + str spc_ram,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu21_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x1a] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu22_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x02 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu23_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x02 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu24_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu25_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu26_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu27_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu28_21: + ldrb r0,[spc_pc],#1 + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu29_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2A_21: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orreq spc_p,spc_p,#flag_c + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2B_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2C_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2D_21: + add r1,spc_ram,spc_s + strb spc_ya,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2E_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff + cmp r0,r1 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu2F_21: + ldrsb r0,[spc_pc],#1 + add spc_pc,spc_pc,r0 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu30_21: + tst spc_p,#0x80000000 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu31_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x18] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu32_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x02 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu33_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x02 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu34_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu35_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu36_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu37_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + orr r0,r0,#0xff00 + and spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu38_21: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + and r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu39_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3A_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + add r0,r1,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + stmfd sp!,{r0} + ldrb r1,[spc_pc] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldmfd sp!,{r0} + mov r0,r0,lsr #8 + ldrb r1,[spc_pc],#1 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3B_21: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3C_21: + and r0,spc_ya,#0xff + mov r0,r0,lsl #1 + tst spc_p,#flag_c + orrne r0,r0,#1 + tst r0,#0x100 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3D_21: + add spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3E_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu3F_21: + ldrb r2,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r2,r2,r14,lsl #8 + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + add spc_pc,spc_ram,r2 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu40_21: + orr spc_p,spc_p,#flag_d + add r0,spc_ram,#0x100 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + str r0,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu41_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x16] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu42_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x04 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu43_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x04 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu44_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu45_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu46_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu47_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu48_21: + ldrb r0,[spc_pc],#1 + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu49_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4A_21: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + biceq spc_p,spc_p,#flag_c + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4B_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4C_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4D_21: + add r1,spc_ram,spc_s + strb spc_x,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4E_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r2,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r2,lsl #24 + bic r0,r0,spc_ya + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu4F_21: + ldrb r2,[spc_pc],#1 + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + add spc_pc,spc_ram,r2 + add spc_pc,spc_pc,#0xff00 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu50_21: + tst spc_p,#0x00000040 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu51_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x14] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu52_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x04 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu53_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x04 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu54_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu55_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu56_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu57_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + eor spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu58_21: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + eor r0,r0,r1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu59_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r0,r0,r3 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5A_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + subs r0,spc_ya,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #16 + tst r0,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5B_21: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5C_21: + and r0,spc_ya,#0xff + tst r0,#0x01 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + mov r0,r0,lsr #1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5D_21: + and spc_x,spc_ya,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5E_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu5F_21: + ldrb r0, [spc_pc], #1 + ldrb r14, [spc_pc], #1 + add spc_pc, r0, spc_ram + add spc_pc, spc_pc, r14, lsl #8 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu60_21: + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu61_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x12] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu62_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x08 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu63_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x08 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu64_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu65_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu66_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu67_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu68_21: + ldrb r0,[spc_pc],#1 + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu69_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_x,spc_x,r0,lsl #24 + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_x,lsr #24 + subs r14,r0,r1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6A_21: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + bicne spc_p,spc_p,#flag_c + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6B_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6C_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6D_21: + mov r0,spc_ya,lsr #8 + add r1,spc_ram,spc_s + strb r0,[r1,#0x100] + sub spc_s,spc_s,#1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6E_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + sub r0,r0,#1 + tst r0,r0 + addeq spc_pc,spc_pc,#1 + ldrnesb r2,[spc_pc],#1 + addne spc_pc,spc_pc,r2 + subne cycles,cycles,#42 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu6F_21: + add r1,spc_ram,spc_s + ldrb r0,[r1,#(0xff + 2)] + ldrb r1,[r1,#(0x100 + 2)] + add spc_s,spc_s,#2 + orr r0,r0,r1,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu70_21: + tst spc_p,#0x00000040 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu71_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x10] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu72_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x08 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu73_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x08 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu74_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu75_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu76_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu77_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r14,spc_ya,#0xff + subs r14,r14,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu78_21: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + subs r14,r0,r1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu79_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_x,spc_x,r0,lsl #24 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_x,lsr #24 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7A_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + add r0,spc_ya,r1 + movs r2,r0,lsr #16 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + bic r2,r0,#0x00ff0000 + eor r3,r1,r2 + eor r14,spc_ya,r1 + mvn r14,r14 + and r14,r14,r3 + tst r14,#0x8000 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7B_21: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7C_21: + and r0,spc_ya,#0xff + tst spc_p,#flag_c + orrne r0,r0,#0x100 + movs r0,r0,lsr #1 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7D_21: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,spc_x + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7E_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu7F_21: + add spc_p,spc_ram,spc_s + ldrb spc_p,[spc_p,#(0x100 + 1)] + add spc_s,spc_s,#1 + and r0,spc_p,#(flag_z|flag_n) + eor r0,r0,#flag_z + orr spc_p,spc_p,r0,lsl #24 + tst spc_p,#flag_d + addne r0,spc_ram,#0x100 + moveq r0,spc_ram + str r0,[context,#iapu_directpage] + add r1,spc_ram,spc_s + ldrb r0,[r1,#(0xff + 2)] + ldrb r1,[r1,#(0x100 + 2)] + add spc_s,spc_s,#2 + orr r0,r0,r1,lsl #8 + add spc_pc,spc_ram,r0 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu80_21: + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu81_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xe] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu82_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x10 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu83_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x10 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu84_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu85_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu86_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu87_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu88_21: + ldrb r0,[spc_pc],#1 + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu89_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r2,r0,r3 + movs r14, spc_p, lsr #1 + adc r0, r0, r3 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r3 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8A_21: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + eorne spc_p,spc_p,#flag_c + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8B_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8C_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8D_21: + ldrb r0,[spc_pc],#1 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8E_21: + add spc_p,spc_ram,spc_s + ldrb spc_p,[spc_p,#(0x100 + 1)] + add spc_s,spc_s,#1 + and r0,spc_p,#(flag_z|flag_n) + eor r0,r0,#flag_z + orr spc_p,spc_p,r0,lsl #24 + tst spc_p,#flag_d + addne r0,spc_ram,#0x100 + moveq r0,spc_ram + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + str r0,[context,#iapu_directpage] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu8F_21: + ldrb r0,[spc_pc],#1 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu90_21: + tst spc_p,#0x00000001 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu91_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xc] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu92_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x10 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu93_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x10 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu94_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu95_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu96_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu97_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + eor r2,spc_ya,r0 + movs r14, spc_p, lsr #1 + adc spc_ya, spc_ya, r0 + movs r14,spc_ya,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,spc_ya,r0 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,spc_ya + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu98_21: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + eor r2,r0,r1 + movs r14, spc_p, lsr #1 + adc r0, r0, r1 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r1 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu99_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + eor r2,r0,r3 + movs r14, spc_p, lsr #1 + adc r0, r0, r3 + movs r14,r0,lsr #8 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + eor r14,r0,r3 + bic r14,r14,r2 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r2,r0 + tst r14,#0x10 + orrne spc_p,spc_p,#flag_h + biceq spc_p,spc_p,#flag_h + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9A_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc],#1 + add r0,r0,#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r1,r3,r0,lsl #8 + subs r0,spc_ya,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + mov r2,r0,lsl #16 + mov r2,r2,lsr #16 + eor r3,spc_ya,r2 + eor r14,spc_ya,r1 + and r14,r14,r3 + tst r14,#0x8000 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r1 + tst r14,#0x10 + bicne spc_p,spc_p,#flag_h + orreq spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9B_21: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9C_21: + and r0,spc_ya,#0xff + sub r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9D_21: + mov spc_x,spc_s + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9E_21: + tst spc_x,spc_x @ div by 0? + orreq spc_ya,spc_ya,#0xff00 + orreq spc_ya,spc_ya,#0x00ff + orreq spc_p,spc_p,#flag_o + beq 1002f + bic spc_p,spc_p,#flag_o +@ Divide spc_ya by spc_x + mov r3,#0 + mov r1,spc_x + +@ Shift up divisor till it's just less than numerator +cmp spc_ya,r1,lsl #8 +movge r1,r1,lsl #8 +cmp spc_ya,r1,lsl #4 +movge r1,r1,lsl #4 +cmp spc_ya,r1,lsl #2 +movge r1,r1,lsl #2 +cmp spc_ya,r1,lsl #1 +movge r1,r1,lsl #1 +1001: + cmp spc_ya,r1 + adc r3,r3,r3 ;@ Double r3 and add 1 if carry set + subcs spc_ya,spc_ya,r1 + teq r1,spc_x + movne r1,r1,lsr #1 + bne 1001b + + and spc_ya,spc_ya,#0xff + and r3,r3,#0xff + orr spc_ya,r3,spc_ya,lsl #8 +1002: + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#252 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +Apu9F_21: + and r0,spc_ya,#0xff + mov r1,r0,lsl #28 + orr r0,r1,r0,lsl #20 + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0,lsr #24 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA0_21: + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + orr spc_p,spc_p,#flag_i + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA1_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0xa] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA2_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x20 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA3_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x20 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA4_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA5_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA6_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA7_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA8_21: + ldrb r0,[spc_pc],#1 + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuA9_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + movs r14,spc_p,lsr #1 + sbcs r2,r0,r3 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r3 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAA_21: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r0,r0,lsr r1 + tst r0,#1 + orrne spc_p,spc_p,#flag_c + biceq spc_p,spc_p,#flag_c + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAB_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAC_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r3, r0 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1, r3 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAD_21: + ldrb r0,[spc_pc],#1 + mov r1,spc_ya,lsr #8 + subs r14,r1,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAE_21: + add r0,spc_ram,spc_s + ldrb r0,[r0,#(0x100 + 1)] + add spc_s,spc_s,#1 + and spc_ya,spc_ya,#0xff00 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuAF_21: + mov r0,spc_ya + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + add spc_x,spc_x,#1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + and spc_x,spc_x,#0xff + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB0_21: + tst spc_p,#0x00000001 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB1_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x8] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB2_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x20 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB3_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x20 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB4_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB5_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB6_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB7_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and r1,spc_ya,#0xff00 + and spc_ya,spc_ya,#0xff + movs r14,spc_p,lsr #1 + sbcs r2,spc_ya,r0 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,spc_ya,r2 + eor r3,spc_ya,r0 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov spc_ya,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r1 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB8_21: + ldrb r0,[spc_pc,#1] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#2 + movs r14,spc_p,lsr #1 + sbcs r2,r0,r1 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r1 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc,#-1] + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuB9_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov r3, r0 + mov r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + movs r14,spc_p,lsr #1 + sbcs r2,r0,r3 + orrge spc_p,spc_p,#flag_c + biclt spc_p,spc_p,#flag_c + eor r14,r0,r2 + eor r3,r0,r3 + and r14,r14,r3 + tst r14,#0x80 + orrne spc_p,spc_p,#flag_o + biceq spc_p,spc_p,#flag_o + eor r14,r3,r2 + tst r14,#0x10 + orreq spc_p,spc_p,#flag_h + bicne spc_p,spc_p,#flag_h + mov r0,r2 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBA_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1, [spc_pc],#1 + mov spc_ya, r0 + add r0, r1, #1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBB_21: + ldrb r0,[spc_pc] + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + ldrb r1,[spc_pc],#1 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBC_21: + and r0,spc_ya,#0xff + add r0,r0,#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and r0,r0,#0xff + mov spc_ya,spc_ya,lsr #8 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,r0,spc_ya,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBD_21: + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + mov spc_s,spc_x + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBE_21: + and r0,spc_ya,#0xff + and r1,spc_ya,#0x0f + cmp r1,#9 + subhi r0,r0,#6 + tstls spc_p,#flag_h + subeq r0,r0,#6 + cmp r0,#0x9f + bhi 2001f + tst spc_p,#flag_c + beq 2001f + orr spc_p,spc_p,#flag_c + b 2002f +2001: + sub r0,r0,#0x60 + bic spc_p,spc_p,#flag_c +2002: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuBF_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + add spc_x,spc_x,#1 + and spc_x,spc_x,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC0_21: + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#flag_i + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC1_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x6] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC2_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x40 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC3_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x40 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC4_21: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC5_21: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC6_21: + mov r0,spc_ya + mov r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC7_21: + ldrb r1,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r1,r1,spc_x + and r1,r1,#0xff + ldrb r1,[r14,r1]! + ldrb r14,[r14,#1] + orr r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#147 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC8_21: + ldrb r0,[spc_pc],#1 + subs r14,spc_x,r0 + orrcs spc_p,spc_p,#flag_c + biccc spc_p,spc_p,#flag_c + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r14,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuC9_21: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_x + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCA_21: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r2,#1 + mov r2,r2,lsl r1 + tst spc_p,#flag_c + orrne r0,r0,r2 + biceq r0,r0,r2 + bic r1, r3, #0xe000 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCB_21: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCC_21: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,r14,lsl #8 + mov r0,spc_ya,lsr #8 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCD_21: + ldrb spc_x,[spc_pc],#1 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCE_21: + add spc_x,spc_ram,spc_s + ldrb spc_x,[spc_x,#(0x100 + 1)] + add spc_s,spc_s,#1 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuCF_21: + mov r0,spc_ya,lsr #8 + and spc_ya,spc_ya,#0xff + mul spc_ya,r0,spc_ya + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #16 + tst spc_ya,#0xff + orrne spc_p,spc_p,#0x01000000 + subs cycles,cycles,#189 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD0_21: + tst spc_p,#0xFF000000 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD1_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x4] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD2_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x40 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD3_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x40 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD4_21: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD5_21: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,spc_x + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD6_21: + ldrb r1,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r1,r1,spc_ya, lsr #8 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD7_21: + ldrb r1,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r1,[r14,r1]! + ldrb r14,[r14,#1] + add r1,r1,spc_ya,lsr #8 + add r1,r1,r14,lsl #8 + mov r0,spc_ya + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#147 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD8_21: + ldrb r1,[spc_pc],#1 + mov r0,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuD9_21: + ldrb r1,[spc_pc],#1 + mov r0,spc_x + add r1,r1,spc_ya,lsr #8 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDA_21: + ldrb r1,[spc_pc] + mov r0,spc_ya + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +2: + strb r0, [r2, r1] +1: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + add r1,r1,#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDB_21: + ldrb r1,[spc_pc],#1 + mov r0,spc_ya,lsr #8 + add r1,r1,spc_x + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDC_21: + mov r0,spc_ya,lsr #8 + sub r0,r0,#1 + and r0,r0,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDD_21: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,spc_ya,lsr #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDE_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and r1,spc_ya,#0xff + cmp r0,r1 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + addne spc_pc,spc_pc,r0 + subne cycles,cycles,#42 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuDF_21: + and r0,spc_ya,#0xff + and r1,spc_ya,#0x0f + cmp r1,#9 + addhi r0,r0,#6 + bls 3001f + cmphi r0,#0xf0 + orrhi spc_p,spc_p,#flag_c + b 3002f +3001: + tst spc_p,#flag_h + addne r0,r0,#6 + beq 3002f + cmp r0,#0xf0 + orrhi spc_p,spc_p,#flag_c +3002: + tst spc_p,#flag_c + addne r0,r0,#0x60 + bne 3003f + cmp r0,#0x9f + addhi r0,r0,#0x60 + orrhi spc_p,spc_p,#flag_c + bicls spc_p,spc_p,#flag_c +3003: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE0_21: + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + bic spc_p,spc_p,#(flag_o|flag_h) + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE1_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x2] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE2_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + orr r0,r0,#0x80 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE3_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + subne cycles,cycles,#42 + addne spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE4_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE5_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE6_21: + mov r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE7_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + add r0,r0,spc_x + and r0,r0,#0xff + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + orr r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE8_21: + ldrb r0,[spc_pc],#1 + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuE9_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEA_21: + ldrb r0,[spc_pc], #1 + ldrb r3,[spc_pc], #1 + add r3,r0,r3,lsl #8 + bic r0, r3, #0xe000 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + mov r1, r3, lsr #13 + mov r2,#1 + mov r2,r2,lsl r1 + eor r0,r0,r2 + bic r1, r3, #0xe000 + add r2, r1, #40 + tst r2, #0x10000 + bne 1f + bic r2, r1, #0x0f + cmp r2, #0xf0 + strneb r0, [spc_ram, r1] + bne 3f + add lr, pc, #20 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 +1: + bl S9xAPUSetByteFFC0 + ldr spc_ram, [context, #iapu_ram] +3: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEB_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEC_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuED_21: + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + eor spc_p,spc_p,#flag_c + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEE_21: + add r0,spc_ram,spc_s + ldrb r0,[r0,#(0x100 + 1)] + add spc_s,spc_s,#1 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuEF_21: + ldr r0, 5001f + mov r1,#0 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + str r1,[r0,#cpu_apu_executing] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End +5001: + .long CPU + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF0_21: + tst spc_p,#0xFF000000 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF1_21: + sub r0,spc_pc,spc_ram + add r1,spc_ram,spc_s + sub spc_s,spc_s,#2 + strb r0,[r1,#0xff] + mov r0,r0,lsr #8 + strb r0,[r1,#0x100] + ldr r0,[context,#iapu_extraram] + ldrh r0,[r0,#0x0] + add spc_pc,spc_ram,r0 + subs cycles,cycles,#168 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF2_21: + ldrb r0,[spc_pc] + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + bic r0,r0,#0x80 + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF3_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + tst r0,#0x80 + addne spc_pc,spc_pc,#1 + ldreqsb r0,[spc_pc],#1 + subeq cycles,cycles,#42 + addeq spc_pc,spc_pc,r0 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF4_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF5_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_x + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF6_21: + ldrb r0,[spc_pc],#1 + ldrb r14,[spc_pc],#1 + add r0,r0,spc_ya, lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF7_21: + ldrb r0,[spc_pc],#1 + ldr r14,[context,#iapu_directpage] + ldrb r0,[r14,r0]! + ldrb r14,[r14,#1] + add r0,r0,spc_ya,lsr #8 + add r0,r0,r14,lsl #8 + mov r1, r0 + ldrb r0, [spc_ram, r1] + cmp r1, #0x0ff + bhi 1f + cmp r1, #0xf3 + addeq lr, pc, #12 + beq GetAPUDSP + cmp r1, #0xfd + movhs r2, #0 + strhsb r2, [spc_ram, r1] +1: + and spc_ya,spc_ya,#0xff00 + orr spc_ya,spc_ya,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#126 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF8_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuF9_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_ya,lsr #8 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + mov spc_x,r0 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_x,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFA_21: + ldrb r0,[spc_pc],#1 + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + ldrb r1,[spc_pc],#1 + ldr r2, [context, #iapu_directpage] + cmp r2, spc_ram + bne 2f + cmp r1, #0xf0 + blo 2f + cmp r1, #0xfe + bhs 1f + add lr, pc, #16 + cmp r1, #0xf1 + beq S9xSetAPUControl + cmp r1, #0xf3 + beq S9xSetAPUDSP + b S9xAPUSetByteFFtoF0 + ldr spc_ram, [context, #iapu_ram] + b 1f +2: + strb r0, [r2, r1] +1: + subs cycles,cycles,#105 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFB_21: + ldrb r0,[spc_pc],#1 + add r0,r0,spc_x + mov r1, r0 + cmp r1, #0xf3 + addeq lr, pc, #20 + beq GetAPUDSP + ldr r14, [context, #iapu_directpage] + cmp r1, #0xfd + ldrb r0, [r14, r1] + movhs r2, #0 + strhsb r2, [r14, r1] + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,r0,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFC_21: + mov r0,spc_ya,lsr #8 + add r0,r0,#1 + and r0,r0,#0xff + and spc_p,spc_p,#0xff + orr spc_p,spc_p,r0,lsl #24 + and spc_ya,spc_ya,#0xff + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + orr spc_ya,spc_ya,r0,lsl #8 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFD_21: + and spc_ya,spc_ya,#0xff + orr spc_ya,spc_ya,spc_ya,lsl #8 + and spc_p,spc_p,#0xff + orr spc_p,spc_p,spc_ya,lsl #24 + subs cycles,cycles,#42 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFE_21: + sub spc_ya,spc_ya,#0x100 + mov spc_ya,spc_ya,lsl #16 + mov spc_ya,spc_ya,lsr #16 + movs r0,spc_ya,lsr #8 + addeq spc_pc,spc_pc,#1 + ldrnesb r0,[spc_pc],#1 + addne spc_pc,spc_pc,r0 + subne cycles,cycles,#42 + subs cycles,cycles,#84 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +ApuFF_21: + ldr r0, 5001f + mov r1,#0 + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + str r1,[r0,#cpu_apu_executing] + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End +5001: + .long CPU + subs cycles,cycles,#63 + ldrgeb opcode,[spc_pc],#1 + ldrge pc,[opcodes,opcode,lsl #2] + b spc700End + + +@ -------------------------- Jump Table 21 -------------------------- +Spc700JumpTab_21: + .long Apu00_21, Apu01_21, Apu02_21, Apu03_21, Apu04_21, Apu05_21, Apu06_21, Apu07_21 @ 00 + .long Apu08_21, Apu09_21, Apu0A_21, Apu0B_21, Apu0C_21, Apu0D_21, Apu0E_21, Apu0F_21 @ 08 + .long Apu10_21, Apu11_21, Apu12_21, Apu13_21, Apu14_21, Apu15_21, Apu16_21, Apu17_21 @ 10 + .long Apu18_21, Apu19_21, Apu1A_21, Apu1B_21, Apu1C_21, Apu1D_21, Apu1E_21, Apu1F_21 @ 18 + .long Apu20_21, Apu21_21, Apu22_21, Apu23_21, Apu24_21, Apu25_21, Apu26_21, Apu27_21 @ 20 + .long Apu28_21, Apu29_21, Apu2A_21, Apu2B_21, Apu2C_21, Apu2D_21, Apu2E_21, Apu2F_21 @ 28 + .long Apu30_21, Apu31_21, Apu32_21, Apu33_21, Apu34_21, Apu35_21, Apu36_21, Apu37_21 @ 30 + .long Apu38_21, Apu39_21, Apu3A_21, Apu3B_21, Apu3C_21, Apu3D_21, Apu3E_21, Apu3F_21 @ 38 + .long Apu40_21, Apu41_21, Apu42_21, Apu43_21, Apu44_21, Apu45_21, Apu46_21, Apu47_21 @ 40 + .long Apu48_21, Apu49_21, Apu4A_21, Apu4B_21, Apu4C_21, Apu4D_21, Apu4E_21, Apu4F_21 @ 48 + .long Apu50_21, Apu51_21, Apu52_21, Apu53_21, Apu54_21, Apu55_21, Apu56_21, Apu57_21 @ 50 + .long Apu58_21, Apu59_21, Apu5A_21, Apu5B_21, Apu5C_21, Apu5D_21, Apu5E_21, Apu5F_21 @ 58 + .long Apu60_21, Apu61_21, Apu62_21, Apu63_21, Apu64_21, Apu65_21, Apu66_21, Apu67_21 @ 60 + .long Apu68_21, Apu69_21, Apu6A_21, Apu6B_21, Apu6C_21, Apu6D_21, Apu6E_21, Apu6F_21 @ 68 + .long Apu70_21, Apu71_21, Apu72_21, Apu73_21, Apu74_21, Apu75_21, Apu76_21, Apu77_21 @ 70 + .long Apu78_21, Apu79_21, Apu7A_21, Apu7B_21, Apu7C_21, Apu7D_21, Apu7E_21, Apu7F_21 @ 78 + .long Apu80_21, Apu81_21, Apu82_21, Apu83_21, Apu84_21, Apu85_21, Apu86_21, Apu87_21 @ 80 + .long Apu88_21, Apu89_21, Apu8A_21, Apu8B_21, Apu8C_21, Apu8D_21, Apu8E_21, Apu8F_21 @ 88 + .long Apu90_21, Apu91_21, Apu92_21, Apu93_21, Apu94_21, Apu95_21, Apu96_21, Apu97_21 @ 90 + .long Apu98_21, Apu99_21, Apu9A_21, Apu9B_21, Apu9C_21, Apu9D_21, Apu9E_21, Apu9F_21 @ 98 + .long ApuA0_21, ApuA1_21, ApuA2_21, ApuA3_21, ApuA4_21, ApuA5_21, ApuA6_21, ApuA7_21 @ a0 + .long ApuA8_21, ApuA9_21, ApuAA_21, ApuAB_21, ApuAC_21, ApuAD_21, ApuAE_21, ApuAF_21 @ a8 + .long ApuB0_21, ApuB1_21, ApuB2_21, ApuB3_21, ApuB4_21, ApuB5_21, ApuB6_21, ApuB7_21 @ b0 + .long ApuB8_21, ApuB9_21, ApuBA_21, ApuBB_21, ApuBC_21, ApuBD_21, ApuBE_21, ApuBF_21 @ b8 + .long ApuC0_21, ApuC1_21, ApuC2_21, ApuC3_21, ApuC4_21, ApuC5_21, ApuC6_21, ApuC7_21 @ c0 + .long ApuC8_21, ApuC9_21, ApuCA_21, ApuCB_21, ApuCC_21, ApuCD_21, ApuCE_21, ApuCF_21 @ c8 + .long ApuD0_21, ApuD1_21, ApuD2_21, ApuD3_21, ApuD4_21, ApuD5_21, ApuD6_21, ApuD7_21 @ d0 + .long ApuD8_21, ApuD9_21, ApuDA_21, ApuDB_21, ApuDC_21, ApuDD_21, ApuDE_21, ApuDF_21 @ d8 + .long ApuE0_21, ApuE1_21, ApuE2_21, ApuE3_21, ApuE4_21, ApuE5_21, ApuE6_21, ApuE7_21 @ e0 + .long ApuE8_21, ApuE9_21, ApuEA_21, ApuEB_21, ApuEC_21, ApuED_21, ApuEE_21, ApuEF_21 @ e8 + .long ApuF0_21, ApuF1_21, ApuF2_21, ApuF3_21, ApuF4_21, ApuF5_21, ApuF6_21, ApuF7_21 @ f0 + .long ApuF8_21, ApuF9_21, ApuFA_21, ApuFB_21, ApuFC_21, ApuFD_21, ApuFE_21, ApuFF_21 @ f8 diff --git a/src/spc_decode.S b/src/spc_decode.S new file mode 100644 index 0000000..a10f003 --- /dev/null +++ b/src/spc_decode.S @@ -0,0 +1,234 @@ + .align 4 + .globl DecodeBlockAsm + +/* +;Bit-Rate Expand Waveform +; +;Desc: +; Decompresses a 9-byte bit-rate reduced block into 16 16-bit samples. +; This procedure is designed to be recursively called to decompress a series of blocks. +;In: +; R0=ESI-> Sample Block +; R1=EDI -> Output buffer +; R2=EDX =3D Last sample of previous block (32-bit) +; R3=EBX =3D Next to last sample (sign extended from 16-bits) +;Out: +; R0=ESI -> Next Block +; R1=EDI -> After last sample +; R2=EDX =3D Last sample (32-bit) +; R3=EBX =3D Next to last sample (16-bit) +;Destroys: +; R4=EAX +*/ + +@ void DecodeBlockAsm2 (int8 *, int16 *, int32 *, int32 *); +@ DecodeBlockAsm2 (compressed, raw, &ch->previous [0], &ch->previous [1]); + .align 4 +DecodeBlockAsm: + stmfd sp!, {r2, r3, r4, r5, r6, r7} + + LDRB R4,[R0],#1 + + LDR R2,[R2] + LDR R3,[R3] + + CMP R4,#0xD0 + MOVHS R5,#0 + rsblo r5, r4, #0xcf + MOVLO R5,R5,LSR #4 + + MOV R6,#8 + TST R4,#0xC + BEQ Method0 + TST R4,#0x8 + BEQ Method1 + TST R4,#0x4 + BEQ Method2 + B Method3 @ ;Must use method 3 +/* +ALIGN 16 + ;[Smp] ----------------------------------*/ +Method0: + ADD R5,R5,#16 + +.macro MMethod0 +.endm + + +Method0loop: + + @ two in a go + + LDRB R4,[R0],#1 + ldrb r7,[r0],#1 + + MOV R2,R4,LSL #(28) + MOV R4,R4,LSL #(24) + BIC R4,R4,#0x0F000000 + + MOV R4,R4,ASR R5 + MOV R2,R2,ASR R5 + + STRH R4,[R1],#2 + STRH R2,[R1],#2 + + @SUBS R6,R6,#1 + @beq Exit0 + + @LDRB R4,[R0],#1 + + MOV R2,R7,LSL #(28) + MOV R4,R7,LSL #(24) + BIC R4,R4,#0x0F000000 + + MOV R4,R4,ASR R5 + MOV R2,R2,ASR R5 + + STRH R4,[R1],#2 + STRH R2,[R1],#2 + + @SUBS R6,R6,#1 + subs r6, r6, #2 + BNE Method0loop + + mov r3, r4 + + ldmfd sp!, {r0, r1, r4, r5, r6, r7} + STR R2,[R0] + STR R3,[R1] + + bx lr + + +@ ALIGN 16 +@ ;[Delta]+[Smp-1](15/16) ----------------- +Method1: + ADD R7,R5,#16 +Method1loop: + LDRSB R3,[R0] + BIC R3,R3,#0xF + MOV R3,R3,LSL #8 + MOV R3,R3,ASR R5 + + MOV R4,R2,LSL #16 + ADD R3,R3,R4,ASR #16 + SUB R3,R3,R4,ASR #20 + + STRH R3,[R1],#2 + + LDRSB R2,[R0],#1 + MOV R2,R2,LSL #(12+16) + MOV R2,R2,ASR R7 + + MOV R4,R3,LSL #16 + ADD R2,R2,R4,ASR #16 + SUB R2,R2,R4,ASR #20 + + STRH R2,[R1],#2 + + SUBS R6,R6,#1 + BNE Method1loop + + MOV R3,R3,LSL #16 + MOV R3,R3,ASR #16 + + ldmfd sp!, {r0, r1, r4, r5, r6, r7} + + STR R2,[R0] + STR R3,[R1] + + bx lr + + @ ;[Delta]+[Smp-1](61/32)-[Smp-2](30/32) -- +Method2: + ADD R7,R5,#16 +Method2loop: + LDRSB R4,[R0], #1 + mov r12, r4 + BIC R4,R4,#0xF + MOV R4,R4,LSL #8 + MOV R4,R4,ASR R5 + + SUB R4,R4,R3 + ADD R4,R4,R3,ASR #4 + MOV R3,R2 + + BIC R2,R2,#3 + ADD R4,R4,R2,LSL #1 + SUB R4,R4,R2,ASR #4 + SUB R4,R4,R2,ASR #5 + STRH R4,[R1],#2 + + MOV R2,R12,LSL #(12+16) + MOV R2,R2,ASR R7 + + SUB R2,R2,R3 + ADD R2,R2,R3,ASR #4 + MOV R3,R4 + + BIC R4,R4,#3 + ADD R2,R2,R4,LSL #1 + SUB R2,R2,R4,ASR #4 + SUB R2,R2,R4,ASR #5 + + STRH R2,[R1],#2 + + SUBS R6,R6,#1 + BNE Method2loop + + ldmfd sp!, {r0, r1, r4, r5, r6, r7} + STR R2,[R0] + STR R3,[R1] + + bx lr + +Method3: + ADD R7,R5,#16 +Method3loop: + LDRSB R4,[R0], #1 + mov r12, r4 + BIC R4,R4,#0xF + MOV R4,R4,LSL #8 + MOV R4,R4,ASR R5 + + @ ;Subtract 13/16 of second sample ----- + SUB R4,R4,R3 + ADD R4,R4,R3,ASR #3 + ADD R4,R4,R3,ASR #4 + MOV R3,R2 + + @ ;Add 115/64 of last sample ----------- + BIC R2,R2,#3 + ADD R4,R4,R2,LSL #1 + SUB R4,R4,R2,ASR #3 + SUB R4,R4,R2,ASR #4 + SUB R4,R4,R2,ASR #6 + + STRH R4,[R1],#2 + + MOV R2,R12,LSL #(12+16) + MOV R2,R2,ASR R7 + + SUB R2,R2,R3 + ADD R2,R2,R3,ASR #3 + ADD R2,R2,R3,ASR #4 + MOV R3,R4 + + BIC R4,R4,#3 + ADD R2,R2,R4,LSL #1 + SUB R2,R2,R4,ASR #3 + SUB R2,R2,R4,ASR #4 + SUB R2,R2,R4,ASR #6 + + STRH R4,[R1],#2 + + SUBS R6,R6,#1 + BNE Method3loop + + ldmfd sp!, {r0, r1, r4, r5, r6, r7} + STR R2,[R0] + STR R3,[R1] + + bx lr + +.pool diff --git a/src/squidgehack.c b/src/squidgehack.c new file mode 100644 index 0000000..f831bd4 --- /dev/null +++ b/src/squidgehack.c @@ -0,0 +1,45 @@ +#include +#include +#include +#include +#include +#include +#include + +extern char **g_argv; + +/* Call this MMU Hack kernel module after doing mmap, and before doing memset*/ +int mmuhack(void) +{ + char kocmd[1024]; + int i, mmufd = open("/dev/mmuhack", O_RDWR); + + if(mmufd < 0) { + strcpy(kocmd, "/sbin/insmod "); + strncpy(kocmd+13, g_argv[0], 1023-13); + kocmd[1023] = 0; + for (i = strlen(kocmd); i > 0; i--) + if (kocmd[i] == '/') { kocmd[i] = 0; break; } + strcat(kocmd, "/mmuhack.o"); + + printf("Installing NK's kernel module for Squidge MMU Hack (%s)...\n", kocmd); + system(kocmd); + mmufd = open("/dev/mmuhack", O_RDWR); + } + if(mmufd < 0) return 0; + + close(mmufd); + return 1; +} + + +/* Unload MMU Hack kernel module after closing all memory devices*/ +int mmuunhack(void) +{ + int ret; + printf("Removing NK's kernel module for Squidge MMU Hack... "); fflush(stdout); + ret = system("/sbin/rmmod mmuhack"); + printf("done (%i)\n", ret); + + return ret; +} diff --git a/src/squidgehack.h b/src/squidgehack.h new file mode 100644 index 0000000..3a6ee7a --- /dev/null +++ b/src/squidgehack.h @@ -0,0 +1,15 @@ +#ifndef __MMUHACK__ +#define __MMUHACK__ + +#ifdef __cplusplus +extern "C" { +#endif + +extern int mmuhack(void); +extern int mmuunhack(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MMUHACK__ */ diff --git a/src/srtc.cpp b/src/srtc.cpp new file mode 100644 index 0000000..be390f0 --- /dev/null +++ b/src/srtc.cpp @@ -0,0 +1,528 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include +#include "snes9x.h" +#include "srtc.h" +#include "memmap.h" + +/*** The format of the rtc_data structure is: + +Index Description Range (nibble) +----- -------------- --------------------------------------- + + 0 Seconds low 0-9 + 1 Seconds high 0-5 + + 2 Minutes low 0-9 + 3 Minutes high 0-5 + + 4 Hour low 0-9 + 5 Hour high 0-2 + + 6 Day low 0-9 + 7 Day high 0-3 + + 8 Month 1-C (0xC is December, 12th month) + + 9 Year ones 0-9 + A Year tens 0-9 + B Year High 9-B (9=19xx, A=20xx, B=21xx) + + C Day of week 0-6 (0=Sunday, 1=Monday,...,6=Saturday) + +***/ + +SRTC_DATA rtc; + + +static int month_keys[12] = { 1, 4, 4, 0, 2, 5, 0, 3, 6, 1, 4, 6 }; + + +/********************************************************************************************* + * + * Note, if you are doing a save state for this game: + * + * On save: + * + * Call S9xUpdateSrtcTime and save the rtc data structure. + * + * On load: + * + * restore the rtc data structure + * rtc.system_timestamp = time (NULL); + * + * + *********************************************************************************************/ + + +void S9xResetSRTC () +{ + rtc.index = -1; + rtc.mode = MODE_READ; +} + +void S9xHardResetSRTC () +{ + ZeroMemory (&rtc, sizeof (rtc)); + rtc.index = -1; + rtc.mode = MODE_READ; + rtc.count_enable = FALSE; + rtc.needs_init = TRUE; + + // Get system timestamp + rtc.system_timestamp = time (NULL); +} + +/**********************************************************************************************/ +/* S9xSRTCComputeDayOfWeek() */ +/* Return 0-6 for Sunday-Saturday */ +/**********************************************************************************************/ +unsigned int S9xSRTCComputeDayOfWeek () +{ + unsigned year = rtc.data[10]*10 + rtc.data[9]; + unsigned month = rtc.data[8]; + unsigned day = rtc.data[7]*10 + rtc.data[6]; + unsigned day_of_week; + + year += (rtc.data[11] - 9) * 100; + + // Range check the month for valid array indicies + if ( month > 12 ) + month = 1; + + day_of_week = year + (year / 4) + month_keys[month-1] + day - 1; + + if(( year % 4 == 0 ) && ( month <= 2 ) ) + day_of_week--; + + day_of_week %= 7; + + return day_of_week; +} + + +/**********************************************************************************************/ +/* S9xSRTCDaysInMonth() */ +/* Return the number of days in a specific month for a certain year */ +/**********************************************************************************************/ +int S9xSRTCDaysInMmonth( int month, int year ) +{ + int mdays; + + switch ( month ) + { + case 2: + if ( ( year % 4 == 0 ) ) // DKJM2 only uses 199x - 22xx + mdays = 29; + else + mdays = 28; + break; + + case 4: + case 6: + case 9: + case 11: + mdays = 30; + break; + + default: // months 1,3,5,7,8,10,12 + mdays = 31; + break; + } + + return mdays; +} + + +#define DAYTICKS (60*60*24) +#define HOURTICKS (60*60) +#define MINUTETICKS 60 + + +/**********************************************************************************************/ +/* S9xUpdateSrtcTime() */ +/* Advance the S-RTC time if counting is enabled */ +/**********************************************************************************************/ +void S9xUpdateSrtcTime () +{ + time_t cur_systime; + long time_diff; + + // Keep track of game time by computing the number of seconds that pass on the system + // clock and adding the same number of seconds to the S-RTC clock structure. + // I originally tried using mktime and localtime library functions to keep track + // of time but some of the GNU time functions fail when the year goes to 2099 + // (and maybe less) and this would have caused a bug with DKJM2 so I'm doing + // it this way to get around that problem. + + // Note: Dai Kaijyu Monogatari II only allows dates in the range 1996-21xx. + + if (rtc.count_enable && !rtc.needs_init) + { + cur_systime = time (NULL); + + // This method assumes one time_t clock tick is one second + // which should work on PCs and GNU systems. + // If your tick interval is different adjust the + // DAYTICK, HOURTICK, and MINUTETICK defines + + time_diff = (long) (cur_systime - rtc.system_timestamp); + rtc.system_timestamp = cur_systime; + + if ( time_diff > 0 ) + { + int seconds; + int minutes; + int hours; + int days; + int month; + int year; + int temp_days; + + int year_hundreds; + int year_tens; + int year_ones; + + + if ( time_diff > DAYTICKS ) + { + days = time_diff / DAYTICKS; + time_diff = time_diff - days * DAYTICKS; + } + else + { + days = 0; + } + + if ( time_diff > HOURTICKS ) + { + hours = time_diff / HOURTICKS; + time_diff = time_diff - hours * HOURTICKS; + } + else + { + hours = 0; + } + + if ( time_diff > MINUTETICKS ) + { + minutes = time_diff / MINUTETICKS; + time_diff = time_diff - minutes * MINUTETICKS; + } + else + { + minutes = 0; + } + + if ( time_diff > 0 ) + { + seconds = time_diff; + } + else + { + seconds = 0; + } + + + seconds += (rtc.data[1]*10 + rtc.data[0]); + if ( seconds >= 60 ) + { + seconds -= 60; + minutes += 1; + } + + minutes += (rtc.data[3]*10 + rtc.data[2]); + if ( minutes >= 60 ) + { + minutes -= 60; + hours += 1; + } + + hours += (rtc.data[5]*10 + rtc.data[4]); + if ( hours >= 24 ) + { + hours -= 24; + days += 1; + } + + if ( days > 0 ) + { + year = rtc.data[10]*10 + rtc.data[9]; + year += ( 1000 + rtc.data[11] * 100 ); + + month = rtc.data[8]; + days += (rtc.data[7]*10 + rtc.data[6]); + while ( days > (temp_days = S9xSRTCDaysInMmonth( month, year )) ) + { + days -= temp_days; + month += 1; + if ( month > 12 ) + { + year += 1; + month = 1; + } + } + + year_tens = year % 100; + year_ones = year_tens % 10; + year_tens /= 10; + year_hundreds = (year - 1000) / 100; + + rtc.data[6] = days % 10; + rtc.data[7] = days / 10; + rtc.data[8] = month; + rtc.data[9] = year_ones; + rtc.data[10] = year_tens; + rtc.data[11] = year_hundreds; + rtc.data[12] = S9xSRTCComputeDayOfWeek (); + } + + rtc.data[0] = seconds % 10; + rtc.data[1] = seconds / 10; + rtc.data[2] = minutes % 10; + rtc.data[3] = minutes / 10; + rtc.data[4] = hours % 10; + rtc.data[5] = hours / 10; + + return; + } + } +} + + +/**********************************************************************************************/ +/* S9xSetSRTC() */ +/* This function sends data to the S-RTC used in Dai Kaijyu Monogatari II */ +/**********************************************************************************************/ +void S9xSetSRTC (uint8 data, uint16 Address) +{ + + data &= 0x0F; // Data is only 4-bits, mask out unused bits. + + if( data >= 0xD ) + { + // It's an RTC command + + switch ( data ) + { + case 0xD: + rtc.mode = MODE_READ; + rtc.index = -1; + break; + + case 0xE: + rtc.mode = MODE_COMMAND; + break; + + default: + // Ignore the write if it's an 0xF ??? + // Probably should switch back to read mode -- but this + // sequence never occurs in DKJM2 + break; + } + + return; + } + + if ( rtc.mode == MODE_LOAD_RTC ) + { + if ( (rtc.index >= 0) || (rtc.index < MAX_RTC_INDEX) ) + { + rtc.data[rtc.index++] = data; + + if ( rtc.index == MAX_RTC_INDEX ) + { + // We have all the data for the RTC load + + rtc.system_timestamp = time (NULL); // Get local system time + + // Get the day of the week + rtc.data[rtc.index++] = S9xSRTCComputeDayOfWeek (); + + // Start RTC counting again + rtc.count_enable = TRUE; + rtc.needs_init = FALSE; + } + + return; + } + else + { + // Attempting to write too much data + // error(); // ignore?? + } + } + else if ( rtc.mode == MODE_COMMAND ) + { + switch( data ) + { + case COMMAND_CLEAR_RTC: + // Disable RTC counter + rtc.count_enable = FALSE; + + ZeroMemory (rtc.data, MAX_RTC_INDEX+1); + rtc.index = -1; + rtc.mode = MODE_COMMAND_DONE; + break; + + case COMMAND_LOAD_RTC: + // Disable RTC counter + rtc.count_enable = FALSE; + + rtc.index = 0; // Setup for writing + rtc.mode = MODE_LOAD_RTC; + break; + + default: + rtc.mode = MODE_COMMAND_DONE; + // unrecognized command - need to implement. + } + + return; + } + else + { + if ( rtc.mode == MODE_READ ) + { + // Attempting to write while in read mode. Ignore. + } + + if ( rtc.mode == MODE_COMMAND_DONE ) + { + // Maybe this isn't an error. Maybe we should kick off + // a new E command. But is this valid? + } + } +} + +/**********************************************************************************************/ +/* S9xGetSRTC() */ +/* This function retrieves data from the S-RTC */ +/**********************************************************************************************/ +uint8 S9xGetSRTC (uint16 Address) +{ + if ( rtc.mode == MODE_READ ) + { + if ( rtc.index < 0 ) + { + S9xUpdateSrtcTime (); // Only update it if the game reads it + rtc.index++; + return ( 0x0f ); // Send start marker. + } + else if (rtc.index > MAX_RTC_INDEX) + { + rtc.index = -1; // Setup for next set of reads + return ( 0x0f ); // Data done marker. + } + else + { + // Feed out the data + return rtc.data[rtc.index++]; + } + } + else + { + return 0x0; + } +} + +void S9xSRTCPreSaveState () +{ + if (Settings.SRTC) + { + S9xUpdateSrtcTime (); + + int s = Memory.SRAMSize ? + (1 << (Memory.SRAMSize + 3)) * 128 : 0; + if (s > 0x20000) + s = 0x20000; + + SRAM [s + 0] = rtc.needs_init; + SRAM [s + 1] = rtc.count_enable; + memmove (&SRAM [s + 2], rtc.data, MAX_RTC_INDEX + 1); + SRAM [s + 3 + MAX_RTC_INDEX] = rtc.index; + SRAM [s + 4 + MAX_RTC_INDEX] = rtc.mode; + +#ifdef LSB_FIRST + memmove (&SRAM [s + 5 + MAX_RTC_INDEX], &rtc.system_timestamp, 8); +#else + SRAM [s + 5 + MAX_RTC_INDEX] = (uint8) (rtc.system_timestamp >> 0); + SRAM [s + 6 + MAX_RTC_INDEX] = (uint8) (rtc.system_timestamp >> 8); + SRAM [s + 7 + MAX_RTC_INDEX] = (uint8) (rtc.system_timestamp >> 16); + SRAM [s + 8 + MAX_RTC_INDEX] = (uint8) (rtc.system_timestamp >> 24); + SRAM [s + 9 + MAX_RTC_INDEX] = (uint8) (rtc.system_timestamp >> 32); + SRAM [s + 10 + MAX_RTC_INDEX] = (uint8) (rtc.system_timestamp >> 40); + SRAM [s + 11 + MAX_RTC_INDEX] = (uint8) (rtc.system_timestamp >> 48); + SRAM [s + 12 + MAX_RTC_INDEX] = (uint8) (rtc.system_timestamp >> 56); +#endif + } +} + +void S9xSRTCPostLoadState () +{ + if (Settings.SRTC) + { + int s = Memory.SRAMSize ? + (1 << (Memory.SRAMSize + 3)) * 128 : 0; + if (s > 0x20000) + s = 0x20000; + + rtc.needs_init = SRAM [s + 0]; + rtc.count_enable = SRAM [s + 1]; + memmove (rtc.data, &SRAM [s + 2], MAX_RTC_INDEX + 1); + rtc.index = SRAM [s + 3 + MAX_RTC_INDEX]; + rtc.mode = SRAM [s + 4 + MAX_RTC_INDEX]; + +#ifdef LSB_FIRST + memmove (&rtc.system_timestamp, &SRAM [s + 5 + MAX_RTC_INDEX], 8); +#else + rtc.system_timestamp |= (SRAM [s + 5 + MAX_RTC_INDEX] << 0); + rtc.system_timestamp |= (SRAM [s + 6 + MAX_RTC_INDEX] << 8); + rtc.system_timestamp |= (SRAM [s + 7 + MAX_RTC_INDEX] << 16); + rtc.system_timestamp |= (SRAM [s + 8 + MAX_RTC_INDEX] << 24); + rtc.system_timestamp |= (SRAM [s + 9 + MAX_RTC_INDEX] << 32); + rtc.system_timestamp |= (SRAM [s + 10 + MAX_RTC_INDEX] << 40); + rtc.system_timestamp |= (SRAM [s + 11 + MAX_RTC_INDEX] << 48); + rtc.system_timestamp |= (SRAM [s + 12 + MAX_RTC_INDEX] << 56); +#endif + S9xUpdateSrtcTime (); + } +} diff --git a/src/srtc.h b/src/srtc.h new file mode 100644 index 0000000..a4e8abf --- /dev/null +++ b/src/srtc.h @@ -0,0 +1,110 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _srtc_h_ +#define _srtc_h_ + +#if !defined(_SNESPPC) && !defined(__GIZ__) && !defined(__GP2X__) && !defined(__WIZ__) +#include +#endif + +#define MAX_RTC_INDEX 0xC + +#define MODE_READ 0 +#define MODE_LOAD_RTC 1 +#define MODE_COMMAND 2 +#define MODE_COMMAND_DONE 3 + +#define COMMAND_LOAD_RTC 0 +#define COMMAND_CLEAR_RTC 4 + + +/*** The format of the rtc_data structure is: + +Index Description Range (nibble) +----- -------------- --------------------------------------- + + 0 Seconds low 0-9 + 1 Seconds high 0-5 + + 2 Minutes low 0-9 + 3 Minutes high 0-5 + + 4 Hour low 0-9 + 5 Hour high 0-2 + + 6 Day low 0-9 + 7 Day high 0-3 + + 8 Month 1-C (0xC is December, 12th month) + + 9 Year ones 0-9 + A Year tens 0-9 + B Year High 9-B (9=19xx, A=20xx, B=21xx) + + C Day of week 0-6 (0=Sunday, 1=Monday,...,6=Saturday) + +***/ + +typedef struct +{ + bool8_32 needs_init; + bool8_32 count_enable; // Does RTC mark time or is it frozen + uint8 data [MAX_RTC_INDEX+1]; + int8 index; + uint8 mode; + + time_t system_timestamp; // Of latest RTC load time + uint32 pad; +} SRTC_DATA; + +extern SRTC_DATA rtc; + +void S9xUpdateSrtcTime (); +void S9xSetSRTC (uint8 data, uint16 Address); +uint8 S9xGetSRTC (uint16 Address); +void S9xSRTCPreSaveState (); +void S9xSRTCPostLoadState (); +void S9xResetSRTC (); +void S9xHardResetSRTC (); + +#define SRTC_SRAM_PAD (4 + 8 + 1 + MAX_RTC_INDEX) + +#endif // _srtc_h diff --git a/src/strcmp.S b/src/strcmp.S new file mode 100644 index 0000000..57a42a7 --- /dev/null +++ b/src/strcmp.S @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2002 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Adapted for uClibc from NetBSD strcmp.S, version 1.3 2003/04/05 + * by Erik Andersen + */ + + .text + .global strcmp; + .type strcmp,%function + .align 4; + +strcmp: +1: + ldrb r2, [r0], #1 + ldrb r3, [r1], #1 + cmp r2, #1 + cmpcs r2, r3 + beq 1b + sub r0, r2, r3 + //mov pc, lr + bx lr + +.weak strcoll; + strcoll = strcmp + diff --git a/src/strlen.S b/src/strlen.S new file mode 100644 index 0000000..1faf7e2 --- /dev/null +++ b/src/strlen.S @@ -0,0 +1,61 @@ +/* Copyright (C) 1998 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Code contributed by Matthew Wilcox + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +/* size_t strlen(const char *S) + * entry: r0 -> string + * exit: r0 = len + */ + + .text + .global strlen; + .type strlen,%function + .align 4; + +strlen: + bic r1, r0, $3 @ addr of word containing first byte + ldr r2, [r1], $4 @ get the first word + ands r3, r0, $3 @ how many bytes are duff? + rsb r0, r3, $0 @ get - that number into counter. + beq Laligned @ skip into main check routine if no + @ more + orr r2, r2, $0x000000ff @ set this byte to non-zero + subs r3, r3, $1 @ any more to do? + orrgt r2, r2, $0x0000ff00 @ if so, set this byte + subs r3, r3, $1 @ more? + orrgt r2, r2, $0x00ff0000 @ then set. +Laligned: @ here, we have a word in r2. Does it + tst r2, $0x000000ff @ contain any zeroes? + tstne r2, $0x0000ff00 @ + tstne r2, $0x00ff0000 @ + tstne r2, $0xff000000 @ + addne r0, r0, $4 @ if not, the string is 4 bytes longer + ldrne r2, [r1], $4 @ and we continue to the next word + bne Laligned @ +Llastword: @ drop through to here once we find a + tst r2, $0x000000ff @ + addne r0, r0, $1 @ + tstne r2, $0x0000ff00 @ and add up to 3 bytes on to it + addne r0, r0, $1 @ + tstne r2, $0x00ff0000 @ (if first three all non-zero, 4th + addne r0, r0, $1 @ must be zero) + //mov pc,lr + bx lr + +.size strlen,.-strlen; + diff --git a/src/strncmp.S b/src/strncmp.S new file mode 100644 index 0000000..ed7c495 --- /dev/null +++ b/src/strncmp.S @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2002 ARM Ltd + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the company may not be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Adapted for uClibc from NetBSD strncmp.S, version 1.2 2003/04/05 + * by Erik Andersen + */ + + .text + .global strncmp; + .type strncmp,%function + .align 4; + +strncmp: + /* if ((len - 1) < 0) return 0 */ + subs r2, r2, #1 + movmi r0, #0 + //movmi pc, lr + bxmi lr + + /* ip == last src address to compare */ + add ip, r0, r2 +1: + ldrb r2, [r0], #1 + ldrb r3, [r1], #1 + cmp ip, r0 + cmpcs r2, #1 + cmpcs r2, r3 + beq 1b + sub r0, r2, r3 + //mov pc, lr + bx lr diff --git a/src/sys_cacheflush.S b/src/sys_cacheflush.S new file mode 100644 index 0000000..d26f81a --- /dev/null +++ b/src/sys_cacheflush.S @@ -0,0 +1,29 @@ +@ vim:filetype=armasm +#include + + +.global sys_cacheflush @ void *start_addr, void *end_addr + +sys_cacheflush: + mov r2, #0 +#ifdef __ARM_EABI__ + /* EABI version */ + str r7, [sp, #-4]! + mov r7, #(__ARM_NR_cacheflush & 0xff) + orr r7, r7, #(__ARM_NR_cacheflush & 0x00ff00) + orr r7, r7, #(__ARM_NR_cacheflush & 0xff0000) + swi 0 + ldr r7, [sp], #4 +#else + /* OABI */ + swi __ARM_NR_cacheflush +#endif + bx lr + +.global spend_cycles +spend_cycles: + mov r0,r0,lsr #2 + 0:subs r0, r0, #1 + bne 0b + bx lr + diff --git a/src/sys_cacheflush.h b/src/sys_cacheflush.h new file mode 100644 index 0000000..c18e312 --- /dev/null +++ b/src/sys_cacheflush.h @@ -0,0 +1,15 @@ +#ifndef _WIZ_CACHEFLUSH + +#ifdef __cplusplus +extern "C" { +#endif + +extern void sys_cacheflush(void *start_addr, void *end_addr); + +extern void spend_cycles(int c); + +#ifdef __cplusplus +} /* End of extern "C" */ +#endif + +#endif diff --git a/src/theme.c b/src/theme.c new file mode 100644 index 0000000..9b4a0ba --- /dev/null +++ b/src/theme.c @@ -0,0 +1,165 @@ +/* + Simple theming handling library + Under GPL v2 License + 2011 by bitrider +*/ + +#include "string.h" +#include "stdio.h" + +#include "minIni.h" +#include "graphics.h" +#include "config.h" +#include "png.h" + +gBITMAP *tBmpBackground = NULL; +gBITMAP *tBmpBar = NULL; +gBITMAP *tBmpLoading = NULL; +gBITMAP *tBmpInGame = NULL; + +unsigned short tTextColorTitle = RGB16(255, 0, 0); +unsigned short tTextColorFocus = RGB16(0, 0, 0); +unsigned short tTextColorItem = RGB16(255, 255, 255); +unsigned short tTextColorVersion = RGB16(0, 0, 255); +unsigned short tTextColorInfo = RGB16(255, 127, 40); +unsigned short tTextColorLoading = RGB16(255, 255,255); +unsigned short tBackgroundColor = RGB16(0,0,0); + +static gBITMAP *_loadBitmapFromIni(char *ini_file, char *ini_entry, char *dir) { + char f[1024]; + char def[] = "none"; + int len; + gBITMAP *bmp; + + strcpy(f, dir); + len = strlen(f); + ini_gets("bitmaps", ini_entry, def, f + len, sizeof(f) - len, ini_file); + if (strcmp(f + len, def) == 0) { + printf("- No \"%s\" image specified\n", ini_entry); + return NULL; + } + printf("- Loading bitmap: %s", f); + bmp = load_png(f, NULL); + if (!bmp) { + printf(" - ERROR loading file !!\n", f); + return NULL; + } + printf(" - OK\n"); + + return bmp; +} + +static int _loadColorFromIni(char *ini_file, char *ini_entry) { + char f[1024]; + char def[] = "none"; + int r = -1; + int g = -1; + int b = -1; + + ini_gets("colors", ini_entry, def, f, sizeof(f), ini_file); + if (strcmp(f, def) == 0) { + printf("- No \"%s\" color specified\n", ini_entry); + return -1; + } + printf("- Parsing color : %s", ini_entry); + sscanf(f, "RGB(%d, %d, %d)", &r, &g, &b); + if ((r < 0) || (r > 255) || + (g < 0) || (g > 255) || + (b < 0) || (b > 255)) { + printf(" - ERROR parsing color !!\n", f); + return -1; + } + printf(" - OK: RGB(%d,%d,%d)\n", r, g, b); + + return RGB16(r, g, b); +} + +int loadTheme(char *name) { + char themes_dir[] = "themes"; + char ini[1024]; + char dir[1024]; + gBITMAP *bgnd, *bar, *loading, *ingame; + int cTitle, cFocus, cItem, cVersion, cInfo, cLoading, cBackground; + + sprintf(ini, "%s/%s.ini", themes_dir, name); + printf("Loading theme file from: %s\n", ini); + + // Load colors + cTitle = _loadColorFromIni(ini, "text_title"); + cFocus = _loadColorFromIni(ini, "text_focus"); + cItem = _loadColorFromIni(ini, "text_item"); + cVersion = _loadColorFromIni(ini, "text_version"); + cInfo = _loadColorFromIni(ini, "text_info"); + cLoading = _loadColorFromIni(ini, "text_loading"); + cBackground = _loadColorFromIni(ini, "background"); + + // Load bitmaps + sprintf(dir, "%s/%s/", themes_dir, name); // build bitmaps directory + + bgnd = _loadBitmapFromIni(ini, "background", dir); + if (!bgnd) return -1; + + bar = _loadBitmapFromIni(ini, "bar", dir); + if (!bar) { + gDestroyBitmap(bgnd); + return -1; + } + + // Not required: can be null + loading = _loadBitmapFromIni(ini, "loading", dir); + ingame = _loadBitmapFromIni(ini, "ingame", dir); + + // Everything went OK, so replace current theme values with just loaded ones + gDestroyBitmap(tBmpBackground); + tBmpBackground = bgnd; + gDestroyBitmap(tBmpBar); + tBmpBar = bar; + gDestroyBitmap(tBmpInGame); + tBmpInGame = ingame; + gDestroyBitmap(tBmpLoading); + tBmpLoading = loading; + + if (cTitle >= 0) tTextColorTitle = cTitle; + if (cFocus >= 0) tTextColorFocus = cFocus; + if (cItem >= 0) tTextColorItem = cItem; + if (cVersion >= 0) tTextColorVersion = cVersion; + if (cInfo >= 0) tTextColorInfo = cInfo; + if (cLoading >= 0) tTextColorLoading = cLoading; + if (cBackground >= 0) tBackgroundColor = cBackground; + + return 0; +} + +int initTheme() { + char theme[256]; + getConfigValue(CONFIG_THEME, theme, sizeof(theme)); + return loadTheme(theme); +} + +void destroyTheme() { + + // Destroy bitmaps + gDestroyBitmap(tBmpBackground); + tBmpBackground = NULL; + gDestroyBitmap(tBmpBar); + tBmpBar = NULL; + gDestroyBitmap(tBmpLoading); + tBmpLoading = NULL; + gDestroyBitmap(tBmpInGame); + tBmpInGame = NULL; + + // Restore text colors + tTextColorTitle = RGB16(255, 0, 0); + tTextColorFocus = RGB16(0, 0, 0); + tTextColorItem = RGB16(255, 255, 255); + tTextColorVersion = RGB16(0, 0, 255); + tTextColorInfo = RGB16(255, 127, 40); + tTextColorLoading = RGB16(255, 255,255); + tBackgroundColor = RGB16(0,0,0); +} + +int isThemeActive() { + if (tBmpBackground != NULL) return 1; + else return 0; +} + diff --git a/src/theme.h b/src/theme.h new file mode 100644 index 0000000..e6d055d --- /dev/null +++ b/src/theme.h @@ -0,0 +1,32 @@ +#ifndef __THEME_H__ +#define __THEME_H__ + +#include "graphics.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern gBITMAP *tBmpBackground; +extern gBITMAP *tBmpBar; +extern gBITMAP *tBmpLoading; +extern gBITMAP *tBmpInGame; + +extern unsigned short tTextColorTitle; +extern unsigned short tTextColorFocus; +extern unsigned short tTextColorItem; +extern unsigned short tTextColorVersion; +extern unsigned short tTextColorLoading; +extern unsigned short tBackgroundColor; + + +int initTheme(); +int loadTheme(char *name); +void destroyTheme(); +int isThemeActive(); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/tile.cpp b/src/tile.cpp new file mode 100644 index 0000000..74a164c --- /dev/null +++ b/src/tile.cpp @@ -0,0 +1,1350 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#include "snes9x.h" + +#include "memmap.h" +#include "ppu.h" +#include "display.h" +#include "gfx.h" +#include "tile.h" + +#ifdef USE_GLIDE +#include "3d.h" +#endif + +extern uint32 HeadMask [4]; +extern uint32 TailMask [5]; + +uint8 ConvertTile (uint8 *pCache, uint32 TileAddr) +{ + register uint8 *tp = &Memory.VRAM[TileAddr]; + uint32 *p = (uint32 *) pCache; + uint32 non_zero = 0; + uint8 line; + uint32 p1; + uint32 p2; + register uint8 pix; + + switch (BG.BitShift) + { + case 8: + for (line = 8; line != 0; line--, tp += 2) + { + p1 = p2 = 0; + if ((pix = *(tp + 0))) + { + p1 |= odd_high[0][pix >> 4]; + p2 |= odd_low[0][pix & 0xf]; + } + if ((pix = *(tp + 1))) + { + p1 |= even_high[0][pix >> 4]; + p2 |= even_low[0][pix & 0xf]; + } + if ((pix = *(tp + 16))) + { + p1 |= odd_high[1][pix >> 4]; + p2 |= odd_low[1][pix & 0xf]; + } + if ((pix = *(tp + 17))) + { + p1 |= even_high[1][pix >> 4]; + p2 |= even_low[1][pix & 0xf]; + } + if ((pix = *(tp + 32))) + { + p1 |= odd_high[2][pix >> 4]; + p2 |= odd_low[2][pix & 0xf]; + } + if ((pix = *(tp + 33))) + { + p1 |= even_high[2][pix >> 4]; + p2 |= even_low[2][pix & 0xf]; + } + if ((pix = *(tp + 48))) + { + p1 |= odd_high[3][pix >> 4]; + p2 |= odd_low[3][pix & 0xf]; + } + if ((pix = *(tp + 49))) + { + p1 |= even_high[3][pix >> 4]; + p2 |= even_low[3][pix & 0xf]; + } + *p++ = p1; + *p++ = p2; + non_zero |= p1 | p2; + } + break; + + case 4: + for (line = 8; line != 0; line--, tp += 2) + { + p1 = p2 = 0; + if ((pix = *(tp + 0))) + { + p1 |= odd_high[0][pix >> 4]; + p2 |= odd_low[0][pix & 0xf]; + } + if ((pix = *(tp + 1))) + { + p1 |= even_high[0][pix >> 4]; + p2 |= even_low[0][pix & 0xf]; + } + if ((pix = *(tp + 16))) + { + p1 |= odd_high[1][pix >> 4]; + p2 |= odd_low[1][pix & 0xf]; + } + if ((pix = *(tp + 17))) + { + p1 |= even_high[1][pix >> 4]; + p2 |= even_low[1][pix & 0xf]; + } + *p++ = p1; + *p++ = p2; + non_zero |= p1 | p2; + } + break; + + case 2: + for (line = 8; line != 0; line--, tp += 2) + { + p1 = p2 = 0; + if ((pix = *(tp + 0))) + { + p1 |= odd_high[0][pix >> 4]; + p2 |= odd_low[0][pix & 0xf]; + } + if ((pix = *(tp + 1))) + { + p1 |= even_high[0][pix >> 4]; + p2 |= even_low[0][pix & 0xf]; + } + *p++ = p1; + *p++ = p2; + non_zero |= p1 | p2; + } + break; + } + return (non_zero ? TRUE : BLANK_TILE); +} + +INLINE void WRITE_4PIXELS (uint32 Offset, uint8 *Pixels) +{ + register uint8 Pixel; + uint8 *Screen = GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[N])) \ + { \ + Screen [N] = (uint8) GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS_FLIPPED (uint32 Offset, uint8 *Pixels) +{ + register uint8 Pixel; + uint8 *Screen = GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N] = (uint8) GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +inline void WRITE_4PIXELSHI16 (uint32 Offset, uint8 *Pixels) +{ + uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[2*N])) \ + { \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +inline void WRITE_4PIXELSHI16_FLIPPED (uint32 Offset, uint8 *Pixels) +{ + uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[6 - 2*N])) \ + { \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELSx2 (uint32 Offset, uint8 *Pixels) +{ + register uint8 Pixel; + uint8 *Screen = GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [0] && (Pixel = Pixels[N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = (uint8) GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS_FLIPPEDx2 (uint32 Offset, uint8 *Pixels) +{ + register uint8 Pixel; + uint8 *Screen = GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = (uint8) GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELSx2x2 (uint32 Offset, uint8 *Pixels) +{ + register uint8 Pixel; + uint8 *Screen = GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = Screen [GFX_PITCH + N * 2] = \ + Screen [GFX_PITCH + N * 2 + 1] = (uint8) GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = Depth [GFX_PITCH + N * 2] = \ + Depth [GFX_PITCH + N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS_FLIPPEDx2x2 (uint32 Offset, uint8 *Pixels) +{ + register uint8 Pixel; + uint8 *Screen = GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = Screen [GFX_PITCH + N * 2] = \ + Screen [GFX_PITCH + N * 2 + 1] = (uint8) GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = Depth [GFX_PITCH + N * 2] = \ + Depth [GFX_PITCH + N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +void DrawTile (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS, WRITE_4PIXELS_FLIPPED, 4) +} + +void DrawClippedTile (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS, WRITE_4PIXELS_FLIPPED, 4) +} + +void DrawTilex2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELSx2, WRITE_4PIXELS_FLIPPEDx2, 8) +} + +void DrawClippedTilex2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELSx2, WRITE_4PIXELS_FLIPPEDx2, 8) +} + +void DrawTilex2x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELSx2x2, WRITE_4PIXELS_FLIPPEDx2x2, 8) +} + +void DrawClippedTilex2x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELSx2x2, WRITE_4PIXELS_FLIPPEDx2x2, 8) +} + +void DrawLargePixel (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint8 *sp = GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + uint8 pixel; +#define PLOT_PIXEL(screen, pixel) (pixel) + + RENDER_TILE_LARGE (((uint8) GFX.ScreenColors [pixel]), PLOT_PIXEL) +} + +INLINE void WRITE_4PIXELS16 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[N])) \ + { \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPED (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16x2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPEDx2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16x2x2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = Screen [(GFX_PITCH >> 1) + N * 2] = \ + Screen [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = Depth [(GFX_PITCH >> 1) + N * 2] = \ + Depth [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPEDx2x2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = Screen [(GFX_PITCH >> 1) + N * 2] = \ + Screen [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = Depth [(GFX_PITCH >> 1) + N * 2] = \ + Depth [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +void DrawTile16_OBJ (uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount) +{ +// TILE_PREAMBLE + + uint8 *pCache; + uint32 TileAddr = BG.TileAddress + ((Tile & 0x3ff) << 5); + if (Tile & 0x100){ + TileAddr += BG.NameSelect; + } + + TileAddr &= 0xffff; + + uint32 TileNumber; + pCache = &BG.Buffer[(TileNumber = (TileAddr >> 5)) << 6]; + + if (!BG.Buffered [TileNumber]){ + BG.Buffered[TileNumber] = ConvertTile (pCache, TileAddr); + } + + if (BG.Buffered [TileNumber] == BLANK_TILE){ + TileBlank = Tile & 0xFFFFFFFF; + return; + } + + GFX.ScreenColors = &IPPU.ScreenColors [(((Tile >> 10) & 7) << 4) + 128]; + + register uint8* bp; + register int inc; + + if (Tile & V_FLIP){ + bp = pCache + 56 - StartLine; + inc = -8; + } else { + bp = pCache + StartLine; + inc = 8; + } + + uint16* Screen = (uint16 *) GFX.S + Offset; + uint16* Colors = GFX.ScreenColors; + uint8* Depth = GFX.DB + Offset; + int GFX_Z1 = GFX.Z1; + int GFX_Z2 = GFX.Z2; + + if (!(Tile & H_FLIP)){ +#define FN(N) \ + if (GFX_Z1 > Depth[N] && bp[N]){ \ + Screen[N] = Colors[bp[N]]; \ + Depth[N] = GFX_Z2; \ + } + while ( LineCount-- ){ + if ( *(uint32*)bp ){ + FN(0); FN(1); FN(2); FN(3); + } + + if ( *(uint32 *)(bp + 4) ){ + FN(4); FN(5); FN(6); FN(7); + } + bp += inc; + Screen += GFX_PPL; + Depth += GFX_PPL; + } +#undef FN + } else { +#define FN(N, B) \ + if (GFX_Z1 > Depth[N] && bp[B]){ \ + Screen[N] = Colors[bp[B]]; \ + Depth[N] = GFX_Z2; \ + } + while ( LineCount-- ){ + if ( *(uint32 *)(bp + 4) ){ + FN(0, 7); FN(1, 6); FN(2, 5); FN(3, 4); + } + + if ( *(uint32*)bp ){ + FN(4, 3); FN(5, 2); FN(6, 1); FN(7, 0); + } + bp += inc; + Screen += GFX_PPL; + Depth += GFX_PPL; + } +#undef FN + } +} + +void DrawTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount) +{ +// TILE_PREAMBLE + + uint8 *pCache; + uint32 TileAddr = BG.TileAddress + ((Tile & 0x3ff) << BG.TileShift); + + TileAddr &= 0xffff; + + uint32 TileNumber; + pCache = &BG.Buffer[(TileNumber = (TileAddr >> BG.TileShift)) << 6]; + + if (!BG.Buffered [TileNumber]){ + BG.Buffered[TileNumber] = ConvertTile (pCache, TileAddr); + } + + if (BG.Buffered [TileNumber] == BLANK_TILE) + { + TileBlank = Tile & 0xFFFFFFFF; + return; + } + + if (BG.DirectColourMode){ + if (IPPU.DirectColourMapsNeedRebuild){ + S9xBuildDirectColourMaps (); + } + GFX.ScreenColors = DirectColourMaps [(Tile >> 10) & BG.PaletteMask]; + } else { + GFX.ScreenColors = &IPPU.ScreenColors [(((Tile >> 10) & BG.PaletteMask) << BG.PaletteShift) + BG.StartPalette]; + } + + register uint8* bp; + register int inc; + + if (Tile & V_FLIP){ + bp = pCache + 56 - StartLine; + inc = -8; + } else { + bp = pCache + StartLine; + inc = 8; + } + + uint16* Screen = (uint16 *) GFX.S + Offset; + uint16* Colors = GFX.ScreenColors; + uint8* Depth = GFX.DB + Offset; + int GFX_Z1 = GFX.Z1; +// int GFX_Z2 = GFX.Z2; + + if (!(Tile & H_FLIP)){ +#define FN(N) \ + if (GFX_Z1 > Depth[N] && bp[N]){ \ + Screen[N] = Colors[bp[N]]; \ + Depth[N] = GFX_Z1; \ + } + while ( LineCount-- ){ + if ( *(uint32*)bp ){ + FN(0); FN(1); FN(2); FN(3); + } + + if ( *(uint32 *)(bp + 4) ){ + FN(4); FN(5); FN(6); FN(7); + } + bp += inc; + Screen += GFX_PPL; + Depth += GFX_PPL; + } +#undef FN + } else { +#define FN(N, B) \ + if (GFX_Z1 > Depth[N] && bp[B]){ \ + Screen[N] = Colors[bp[B]]; \ + Depth[N] = GFX_Z1; \ + } + while ( LineCount-- ){ + if ( *(uint32 *)(bp + 4) ){ + FN(0, 7); FN(1, 6); FN(2, 5); FN(3, 4); + } + + if ( *(uint32*)bp ){ + FN(4, 3); FN(5, 2); FN(6, 1); FN(7, 0); + } + bp += inc; + Screen += GFX_PPL; + Depth += GFX_PPL; + } +#undef FN + } +} + +void DrawClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16, WRITE_4PIXELS16_FLIPPED, 4) +} + +void DrawTile16x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16x2, WRITE_4PIXELS16_FLIPPEDx2, 8) +} + +void DrawClippedTile16x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16x2, WRITE_4PIXELS16_FLIPPEDx2, 8) +} + +void DrawTile16x2x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16x2x2, WRITE_4PIXELS16_FLIPPEDx2x2, 8) +} + +void DrawClippedTile16x2x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16x2x2, WRITE_4PIXELS16_FLIPPEDx2x2, 8) +} + +void DrawLargePixel16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + uint16 pixel; + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], PLOT_PIXEL) +} + +INLINE void WRITE_4PIXELS16_ADD (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[N])) \ + { \ + if (SubDepth [N]) \ + { \ + if (SubDepth [N] != 1) \ + Screen [N] = COLOR_ADD (GFX.ScreenColors [Pixel], \ + Screen [GFX.Delta + N]); \ + else \ + Screen [N] = COLOR_ADD (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + } \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPED_ADD (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[3 - N])) \ + { \ + if (SubDepth [N]) \ + { \ + if (SubDepth [N] != 1) \ + Screen [N] = COLOR_ADD (GFX.ScreenColors [Pixel], \ + Screen [GFX.Delta + N]); \ + else \ + Screen [N] = COLOR_ADD (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + } \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_ADD1_2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[N])) \ + { \ + if (SubDepth [N]) \ + { \ + if (SubDepth [N] != 1) \ + Screen [N] = (uint16) (COLOR_ADD1_2 (GFX.ScreenColors [Pixel], \ + Screen [GFX.Delta + N])); \ + else \ + Screen [N] = COLOR_ADD (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + } \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPED_ADD1_2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[3 - N])) \ + { \ + if (SubDepth [N]) \ + { \ + if (SubDepth [N] != 1) \ + Screen [N] = (uint16) (COLOR_ADD1_2 (GFX.ScreenColors [Pixel], \ + Screen [GFX.Delta + N])); \ + else \ + Screen [N] = COLOR_ADD (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + } \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_SUB (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[N])) \ + { \ + if (SubDepth [N]) \ + { \ + if (SubDepth [N] != 1) \ + Screen [N] = (uint16) COLOR_SUB (GFX.ScreenColors [Pixel], \ + Screen [GFX.Delta + N]); \ + else \ + Screen [N] = (uint16) COLOR_SUB (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + } \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPED_SUB (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[3 - N])) \ + { \ + if (SubDepth [N]) \ + { \ + if (SubDepth [N] != 1) \ + Screen [N] = (uint16) COLOR_SUB (GFX.ScreenColors [Pixel], \ + Screen [GFX.Delta + N]); \ + else \ + Screen [N] = (uint16) COLOR_SUB (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + } \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_SUB1_2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[N])) \ + { \ + if (SubDepth [N]) \ + { \ + if (SubDepth [N] != 1) \ + Screen [N] = (uint16) COLOR_SUB1_2 (GFX.ScreenColors [Pixel], \ + Screen [GFX.Delta + N]); \ + else \ + Screen [N] = (uint16) COLOR_SUB (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + } \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPED_SUB1_2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[3 - N])) \ + { \ + if (SubDepth [N]) \ + { \ + if (SubDepth [N] != 1) \ + Screen [N] = (uint16) COLOR_SUB1_2 (GFX.ScreenColors [Pixel], \ + Screen [GFX.Delta + N]); \ + else \ + Screen [N] = (uint16) COLOR_SUB (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + } \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + + +void DrawTile16Add (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16_ADD, WRITE_4PIXELS16_FLIPPED_ADD, 4) +} + +void DrawClippedTile16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16_ADD, WRITE_4PIXELS16_FLIPPED_ADD, 4) +} + +void DrawTile16Add1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16_ADD1_2, WRITE_4PIXELS16_FLIPPED_ADD1_2, 4) +} + +void DrawClippedTile16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16_ADD1_2, WRITE_4PIXELS16_FLIPPED_ADD1_2, 4) +} + +void DrawTile16Sub (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16_SUB, WRITE_4PIXELS16_FLIPPED_SUB, 4) +} + +void DrawClippedTile16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16_SUB, WRITE_4PIXELS16_FLIPPED_SUB, 4) +} + +void DrawTile16Sub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16_SUB1_2, WRITE_4PIXELS16_FLIPPED_SUB1_2, 4) +} + +void DrawClippedTile16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16_SUB1_2, WRITE_4PIXELS16_FLIPPED_SUB1_2, 4) +} + +INLINE void WRITE_4PIXELS16_ADDF1_2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[N])) \ + { \ + if (SubDepth [N] == 1) \ + Screen [N] = (uint16) (COLOR_ADD1_2 (GFX.ScreenColors [Pixel], \ + GFX.FixedColour)); \ + else \ + Screen [N] = GFX.ScreenColors [Pixel];\ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPED_ADDF1_2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[3 - N])) \ + { \ + if (SubDepth [N] == 1) \ + Screen [N] = (uint16) (COLOR_ADD1_2 (GFX.ScreenColors [Pixel], \ + GFX.FixedColour)); \ + else \ + Screen [N] = GFX.ScreenColors [Pixel];\ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_SUBF1_2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[N])) \ + { \ + if (SubDepth [N] == 1) \ + Screen [N] = (uint16) COLOR_SUB1_2 (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPED_SUBF1_2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint8 *SubDepth = GFX.SubZBuffer + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[3 - N])) \ + { \ + if (SubDepth [N] == 1) \ + Screen [N] = (uint16) COLOR_SUB1_2 (GFX.ScreenColors [Pixel], \ + GFX.FixedColour); \ + else \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) + +#undef FN +} + +void DrawTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16_ADDF1_2, WRITE_4PIXELS16_FLIPPED_ADDF1_2, 4) +} + +void DrawClippedTile16FixedAdd1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16_ADDF1_2, + WRITE_4PIXELS16_FLIPPED_ADDF1_2, 4) +} + +void DrawTile16FixedSub1_2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16_SUBF1_2, WRITE_4PIXELS16_FLIPPED_SUBF1_2, 4) +} + +void DrawClippedTile16FixedSub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16_SUBF1_2, + WRITE_4PIXELS16_FLIPPED_SUBF1_2, 4) +} + +void DrawLargePixel16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + register uint16 pixel; + +#define LARGE_ADD_PIXEL(s, p) \ +(Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_ADD (p, *(s + GFX.Delta)) : \ + COLOR_ADD (p, GFX.FixedColour)) \ + : p) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_ADD_PIXEL) +} + +void DrawLargePixel16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + register uint16 pixel; + +#define LARGE_ADD_PIXEL1_2(s, p) \ +((uint16) (Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_ADD1_2 (p, *(s + GFX.Delta)) : \ + COLOR_ADD (p, GFX.FixedColour)) \ + : p)) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_ADD_PIXEL1_2) +} + +void DrawLargePixel16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + register uint16 pixel; + +#define LARGE_SUB_PIXEL(s, p) \ +(Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_SUB (p, *(s + GFX.Delta)) : \ + COLOR_SUB (p, GFX.FixedColour)) \ + : p) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_SUB_PIXEL) +} + +void DrawLargePixel16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint16 pixel; + +#define LARGE_SUB_PIXEL1_2(s, p) \ +(Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_SUB1_2 (p, *(s + GFX.Delta)) : \ + COLOR_SUB (p, GFX.FixedColour)) \ + : p) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_SUB_PIXEL1_2) +} + +void DrawHiResTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILEHI(WRITE_4PIXELSHI16, WRITE_4PIXELSHI16_FLIPPED, 4) +} + +void DrawHiResClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILEHI(WRITE_4PIXELSHI16, WRITE_4PIXELSHI16_FLIPPED, 4) +} diff --git a/src/tile.h b/src/tile.h new file mode 100644 index 0000000..8bc5528 --- /dev/null +++ b/src/tile.h @@ -0,0 +1,314 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _TILE_H_ +#define _TILE_H_ + +extern uint32 TileBlank; + +#define TILE_PREAMBLE \ + uint8 *pCache; \ +\ + uint32 TileAddr = (BG.TileAddress + ((Tile & 0x3ff) << BG.TileShift)) & 0xffff; \ +\ + uint32 TileNumber; \ + pCache = &BG.Buffer[(TileNumber = (TileAddr >> BG.TileShift)) << 6]; \ +\ + if (!BG.Buffered [TileNumber]) \ + BG.Buffered[TileNumber] = ConvertTile (pCache, TileAddr); \ +\ + if (BG.Buffered [TileNumber] == BLANK_TILE){ \ + TileBlank = Tile; \ + return; \ + } \ +\ + register uint32 l; \ + GFX.ScreenColors = &GFX.ScreenColorsPre[(Tile & GFX.PaletteMask) >> GFX.PaletteShift]; + + +/* + if (BG.DirectColourMode) GFX.ScreenColors = DirectColourMaps [(Tile >> 10) & BG.PaletteMask]; \ + else GFX.ScreenColors = &IPPU.ScreenColors [(((Tile >> 10) & BG.PaletteMask) << BG.PaletteShift) + BG.StartPalette]; +*/ +#define RENDER_TILE(NORMAL, FLIPPED, N) \ + register int inc; \ + if (!(Tile & V_FLIP)){ \ + bp = pCache + StartLine; \ + inc = 8; \ + } else { \ + bp = pCache + 56 - StartLine; \ + inc = -8; \ + } \ + \ + l = LineCount; \ + if (!(Tile & H_FLIP)){ \ + while ( l-- ){ \ + if (*(uint32 *) bp) \ + NORMAL (Offset, bp); \ + if (*(uint32 *) (bp + 4)) \ + NORMAL (Offset + N, bp + 4); \ + bp += inc, Offset += GFX_PPL; \ + } \ + } else { \ + while ( l-- ){ \ + if (*(uint32 *) (bp + 4)) \ + FLIPPED (Offset, bp + 4); \ + if (*(uint32 *) bp) \ + FLIPPED (Offset + N, bp); \ + bp += inc, Offset += GFX_PPL; \ + } \ + } + +#define TILE_CLIP_PREAMBLE \ + uint32 dd; \ + uint32 d1; \ + uint32 d2; \ +\ + if (StartPixel < 4) \ + { \ + d1 = HeadMask [StartPixel]; \ + if (StartPixel + Width < 4) \ + d1 &= TailMask [StartPixel + Width]; \ + } \ + else \ + d1 = 0; \ +\ + if (StartPixel + Width > 4) \ + { \ + if (StartPixel > 4) \ + d2 = HeadMask [StartPixel - 4]; \ + else \ + d2 = 0xffffffff; \ +\ + d2 &= TailMask [(StartPixel + Width - 4)]; \ + } \ + else \ + d2 = 0; + + +#define RENDER_CLIPPED_TILE(NORMAL, FLIPPED, N) \ + register int inc; \ + if (Tile & V_FLIP){ \ + bp = pCache + 56 - StartLine; \ + inc = -8; \ + } else { \ + bp = pCache + StartLine; \ + inc = 8; \ + } \ + \ + l = LineCount; \ + if (!(Tile & H_FLIP)){ \ + while ( l-- ){ \ + if ((dd = (*(uint32 *) bp) & d1)) \ + NORMAL (Offset, (uint8 *) &dd); \ + if ((dd = (*(uint32 *) (bp + 4)) & d2)) \ + NORMAL (Offset + N, (uint8 *) &dd); \ + bp += inc, Offset += GFX_PPL; \ + } \ + } else { \ + SWAP_DWORD (d1); \ + SWAP_DWORD (d2); \ + while ( l-- ){ \ + if ((dd = *(uint32 *) (bp + 4) & d1)) \ + FLIPPED (Offset, (uint8 *) &dd); \ + if ((dd = *(uint32 *) bp & d2)) \ + FLIPPED (Offset + N, (uint8 *) &dd); \ + bp += inc, Offset += GFX_PPL; \ + } \ + } + +#define RENDER_TILE_LARGE(PIXEL, FUNCTION) \ + if (!(Tile & (V_FLIP | H_FLIP))) \ + { \ + if ((pixel = *(pCache + StartLine + StartPixel))) \ + { \ + pixel = PIXEL; \ + for (l = LineCount; l != 0; l--, sp += GFX_PPL, Depth += GFX_PPL) \ + { \ + for (int z = Pixels - 1; z >= 0; z--) \ + if (GFX.Z1 > Depth [z]) \ + { \ + sp [z] = FUNCTION(sp + z, pixel); \ + Depth [z] = GFX.Z2; \ + }\ + } \ + } \ + } \ + else \ + if (!(Tile & V_FLIP)) \ + { \ + StartPixel = 7 - StartPixel; \ + if ((pixel = *(pCache + StartLine + StartPixel))) \ + { \ + pixel = PIXEL; \ + for (l = LineCount; l != 0; l--, sp += GFX_PPL, Depth += GFX_PPL) \ + { \ + for (int z = Pixels - 1; z >= 0; z--) \ + if (GFX.Z1 > Depth [z]) \ + { \ + sp [z] = FUNCTION(sp + z, pixel); \ + Depth [z] = GFX.Z2; \ + }\ + } \ + } \ + } \ + else \ + if (Tile & H_FLIP) \ + { \ + StartPixel = 7 - StartPixel; \ + if ((pixel = *(pCache + 56 - StartLine + StartPixel))) \ + { \ + pixel = PIXEL; \ + for (l = LineCount; l != 0; l--, sp += GFX_PPL, Depth += GFX_PPL) \ + { \ + for (int z = Pixels - 1; z >= 0; z--) \ + if (GFX.Z1 > Depth [z]) \ + { \ + sp [z] = FUNCTION(sp + z, pixel); \ + Depth [z] = GFX.Z2; \ + }\ + } \ + } \ + } \ + else \ + { \ + if ((pixel = *(pCache + 56 - StartLine + StartPixel))) \ + { \ + pixel = PIXEL; \ + for (l = LineCount; l != 0; l--, sp += GFX_PPL, Depth += GFX_PPL) \ + { \ + for (int z = Pixels - 1; z >= 0; z--) \ + if (GFX.Z1 > Depth [z]) \ + { \ + sp [z] = FUNCTION(sp + z, pixel); \ + Depth [z] = GFX.Z2; \ + }\ + } \ + } \ + } + +#define RENDER_TILEHI(NORMAL, FLIPPED, N) \ + if (!(Tile & (V_FLIP | H_FLIP))) \ + { \ + bp = pCache + StartLine; \ + for (l = LineCount; l != 0; l--, bp += 8, Offset += GFX_PPL) \ + { \ + /*if (*(uint32 *) bp)*/if (((uint32)bp[0])|((uint32)bp[2])|((uint32)bp[4])|((uint32)bp[6])) \ + NORMAL (Offset, bp); \ + } \ + } \ + else \ + if (!(Tile & V_FLIP)) \ + { \ + bp = pCache + StartLine; \ + for (l = LineCount; l != 0; l--, bp += 8, Offset += GFX_PPL) \ + { \ + /*if (*(uint32 *) (bp + 4))*/if (((uint32)bp[0])|((uint32)bp[2])|((uint32)bp[4])|((uint32)bp[6])) \ + FLIPPED (Offset, bp); \ + } \ + } \ + else \ + if (Tile & H_FLIP) \ + { \ + bp = pCache + 56 - StartLine; \ + for (l = LineCount; l != 0; l--, bp -= 8, Offset += GFX_PPL) \ + { \ + /*if (*(uint32 *) (bp + 4))*/if (((uint32)bp[0])|((uint32)bp[2])|((uint32)bp[4])|((uint32)bp[6])) \ + FLIPPED (Offset, bp); \ + } \ + } \ + else \ + { \ + bp = pCache + 56 - StartLine; \ + for (l = LineCount; l != 0; l--, bp -= 8, Offset += GFX_PPL) \ + { \ + /*if (*(uint32 *) bp)*/if (((uint32)bp[0])|((uint32)bp[2])|((uint32)bp[4])|((uint32)bp[6])) \ + NORMAL (Offset, bp); \ + } \ + } + + + +#define RENDER_CLIPPED_TILEHI(NORMAL, FLIPPED, N) \ + d1=(d1&0xFF)|((d1&0xFF0000)>>8)|((d2&0xFF)<<16)|((d2&0xFF0000)<<8);\ + if (!(Tile & (V_FLIP | H_FLIP))) \ + { \ + bp = pCache + StartLine; \ + for (l = LineCount; l != 0; l--, bp += 8, Offset += GFX_PPL) \ + { \ + /*if ((dd = (*(uint32 *) bp) & d1))*/if (dd = (((((uint32)bp[6])<<24)|(((uint32)bp[4])<<16)|(((uint32)bp[2])<<8)|((uint32)bp[0]))&d1)) \ + NORMAL (Offset, (uint8 *) &dd); \ + } \ + } \ + else \ + if (!(Tile & V_FLIP)) \ + { \ + bp = pCache + StartLine; \ + SWAP_DWORD (d1); \ + /*SWAP_DWORD (d2);*/ \ + for (l = LineCount; l != 0; l--, bp += 8, Offset += GFX_PPL) \ + { \ + /*if ((dd = *(uint32 *) (bp + 4) & d1))*/if (dd = (((((uint32)bp[6])<<24)|(((uint32)bp[4])<<16)|(((uint32)bp[2])<<8)|((uint32)bp[0]))&d1)) \ + FLIPPED (Offset, (uint8 *) &dd); \ + } \ + } \ + else \ + if (Tile & H_FLIP) \ + { \ + bp = pCache + 56 - StartLine; \ + SWAP_DWORD (d1); \ + /*SWAP_DWORD (d2);*/ \ + for (l = LineCount; l != 0; l--, bp -= 8, Offset += GFX_PPL) \ + { \ + /*if ((dd = *(uint32 *) (bp + 4) & d1))*/if (dd = (((((uint32)bp[6])<<24)|(((uint32)bp[4])<<16)|(((uint32)bp[2])<<8)|((uint32)bp[0]))&d1)) \ + FLIPPED (Offset, (uint8 *) &dd); \ + } \ + } \ + else \ + { \ + bp = pCache + 56 - StartLine; \ + for (l = LineCount; l != 0; l--, bp -= 8, Offset += GFX_PPL) \ + { \ + /*if ((dd = (*(uint32 *) bp) & d1))*/ if (dd = (((((uint32)bp[6])<<24)|(((uint32)bp[4])<<16)|(((uint32)bp[2])<<8)|((uint32)bp[0]))&d1)) \ + NORMAL (Offset, (uint8 *) &dd); \ + } \ + } + +#endif diff --git a/src/tile16.cpp b/src/tile16.cpp new file mode 100644 index 0000000..5044bd5 --- /dev/null +++ b/src/tile16.cpp @@ -0,0 +1,1920 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +// ARM V5 Assembly by bitrider + +#include "snes9x.h" + +#include "memmap.h" +#include "ppu.h" +#include "display.h" +#include "gfx.h" +#include "tile16.h" + +#ifdef USE_GLIDE +#include "3d.h" +#endif + +extern uint32 HeadMask [4]; +extern uint32 TailMask [5]; + +#define f(from, to_lo, to_hi, pix) \ + " movs " #from ", " #from ", lsl #(17) \n" \ + " addcs " #to_hi ", " #to_hi ", #(1 << ( 0 + 1 + " #pix ")) \n" \ + " addmi " #to_hi ", " #to_hi ", #(1 << ( 8 + 1 + " #pix ")) \n" \ + " movs " #from ", " #from ", lsl #2 \n" \ + " addcs " #to_hi ", " #to_hi ", #(1 << (16 + 1 + " #pix ")) \n" \ + " addmi " #to_hi ", " #to_hi ", #(1 << (24 + 1 + " #pix ")) \n" \ + " movs " #from ", " #from ", lsl #2 \n"\ + " addcs " #to_lo ", " #to_lo ", #(1 << ( 0 + 1 + " #pix ")) \n" \ + " addmi " #to_lo ", " #to_lo ", #(1 << ( 8 + 1 + " #pix ")) \n" \ + " movs " #from ", " #from ", lsl #2 \n" \ + " addcs " #to_lo ", " #to_lo ", #(1 << (16 + 1 + " #pix ")) \n" \ + " addmi " #to_lo ", " #to_lo ", #(1 << (24 + 1 + " #pix ")) \n" \ + \ + " movs " #from ", " #from ", lsl #2 \n"\ + " addcs " #to_hi ", " #to_hi ", #(1 << ( 0 + " #pix ")) \n"\ + " addmi " #to_hi ", " #to_hi ", #(1 << ( 8 + " #pix ")) \n" \ + " movs " #from ", " #from ", lsl #2 \n"\ + " addcs " #to_hi ", " #to_hi ", #(1 << (16 + " #pix ")) \n" \ + " addmi " #to_hi ", " #to_hi ", #(1 << (24 + " #pix ")) \n"\ + " movs " #from ", " #from ", lsl #2 \n"\ + " addcs " #to_lo ", " #to_lo ", #(1 << ( 0 + " #pix ")) \n"\ + " addmi " #to_lo ", " #to_lo ", #(1 << ( 8 + " #pix ")) \n" \ + " movs " #from ", " #from ", lsl #2 \n"\ + " addcs " #to_lo ", " #to_lo ", #(1 << (16 + " #pix ")) \n" \ + " addmi " #to_lo ", " #to_lo ", #(1 << (24 + " #pix ")) \n" + +uint8 ConvertTile8bpp (uint8 *pCache, uint32 TileAddr) +{ + register uint8 *tp = &Memory.VRAM[TileAddr]; + register uint32 *p = (uint32 *) pCache; + register uint32 non_zero; + + asm volatile ( + " mov r0, #8 \n" + " mov %[non_zero], #0 \n" + + "1: \n" + + " mov r1, #0 \n" + " mov r2, #0 \n" + + " ldrh r3, [%[tp], #16] \n" + " ldrh r4, [%[tp], #32] \n" + + f(r3, r2, r1, 2) + f(r4, r2, r1, 4) + + " ldrh r3, [%[tp], #48] \n" + " ldrh r4, [%[tp]], #2 \n" + + f(r3, r2, r1, 6) + f(r4, r2, r1, 0) + + " stmia %[p]!, {r1, r2} \n" + + " orr %[non_zero], %[non_zero], r1 \n" + " orr %[non_zero], %[non_zero], r2 \n" + + " subs r0, r0, #1 \n" + " bne 1b \n" + + : [non_zero] "+r" (non_zero), + [tp] "+r" (tp), + [p] "+r" (p) + : + : "r0", "r1", "r2", "r3", "r4", "cc" + ); + + return (non_zero ? TRUE : BLANK_TILE); +} + +uint8 ConvertTile4bpp (uint8 *pCache, uint32 TileAddr) +{ + register uint8 *tp = &Memory.VRAM[TileAddr]; + register uint32 *p = (uint32 *) pCache; + register uint32 non_zero; + + asm volatile ( + " mov r0, #8 \n" + " mov %[non_zero], #0 \n" + "1: \n" + + " mov r1, #0 \n" + " mov r2, #0 \n" + + " ldrh r3, [%[tp], #16]\n" + " ldrh r4, [%[tp]], #2 \n" + + f(r3, r2, r1, 2) + f(r4, r2, r1, 0) + + " stmia %[p]!, {r1, r2} \n" + + " orr %[non_zero], %[non_zero], r1 \n" + " orr %[non_zero], %[non_zero], r2 \n" + + " subs r0, r0, #1 \n" + " bne 1b \n" + + : [non_zero] "+r" (non_zero), + [tp] "+r" (tp), + [p] "+r" (p) + : + : "r0", "r1", "r2", "r3", "r4", "cc" + ); + + return (non_zero ? TRUE : BLANK_TILE); +} + +uint8 ConvertTile2bpp (uint8 *pCache, uint32 TileAddr) +{ + register uint8 *tp = &Memory.VRAM[TileAddr]; + register uint32 *p = (uint32 *) pCache; + register uint32 non_zero; + + asm volatile ( + " mov r0, #8 \n" + " mov %[non_zero], #0 \n" + "1: \n" + + " ldrh r3, [%[tp]], #2 \n" + + " mov r1, #0 \n" + " mov r2, #0 \n" + + f(r3, r2, r1, 0) + + " stmia %[p]!, {r1, r2} \n" + + " orr %[non_zero], %[non_zero], r1 \n" + " orr %[non_zero], %[non_zero], r2 \n" + + " subs r0, r0, #1 \n" + " bne 1b \n" + + : [non_zero] "+r" (non_zero), + [tp] "+r" (tp), + [p] "+r" (p) + : + : "r0", "r1", "r2", "r3", "cc" + ); + + return (non_zero ? TRUE : BLANK_TILE); +} + + +uint8 (*ConvertTile) (uint8 *pCache, uint32 TileAddr); +void SelectConvertTile() { + switch (BG.BitShift) + { + + case 8: + ConvertTile = &ConvertTile8bpp; + break; + case 4: + ConvertTile = &ConvertTile4bpp; + break; + case 2: + ConvertTile = &ConvertTile2bpp; + break; + } + +} + +void SelectPalette() { + // GFX.ScreenColors = &GFX.ScreenColorsPre[(Tile & GFX.PaletteMask) >> GFX.PaletteShift]; + if (BG.DirectColourMode) { + // GFX.ScreenColors = DirectColourMaps [(Tile >> 10) & BG.PaletteMask]; + + GFX.ScreenColorsPre = DirectColourMaps[0]; + GFX.PaletteMask = BG.PaletteMask << 10; + GFX.PaletteShift = 10; + } else { + // GFX.ScreenColors = &IPPU.ScreenColors [(((Tile >> 10) & BG.PaletteMask) << BG.PaletteShift) + BG.StartPalette]; + + GFX.ScreenColorsPre = &IPPU.ScreenColors[BG.StartPalette]; + GFX.PaletteMask = BG.PaletteMask << 10; + GFX.PaletteShift = 10 - BG.PaletteShift; + } + +} + +inline void WRITE_4PIXELSHI16 (uint32 Offset, uint8 *Pixels) +{ + uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[2*N])) \ + { \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +inline void WRITE_4PIXELSHI16_FLIPPED (uint32 Offset, uint8 *Pixels) +{ + uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[6 - 2*N])) \ + { \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16x2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPEDx2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16x2x2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = Screen [(GFX_PITCH >> 1) + N * 2] = \ + Screen [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = Depth [(GFX_PITCH >> 1) + N * 2] = \ + Depth [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPEDx2x2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = Screen [(GFX_PITCH >> 1) + N * 2] = \ + Screen [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = Depth [(GFX_PITCH >> 1) + N * 2] = \ + Depth [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +#ifdef __FAST_OBJS__ +// DrawNoZTile16 ----------------------------------------- +void DrawNoZTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount) +{ + + TILE_PREAMBLE +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" +#define FN(p) \ + " ldrb r1, [%[bp], #" #p "] \n"\ + " ldrb r0, [%[bp], #(" #p " + 1)] \n"\ + " movs r1, r1, lsl #2 \n"\ + " ldrne r1, [%[colors], r1] \n"\ + " strneb %[gfx_z2], [%[depth], #" #p "] \n"\ + " strneh r1, [%[screen], #(" #p " * 2)] \n"\ + "3: \n"\ + " movs r1, r0, lsl #2 \n"\ + " ldrne r1, [%[colors], r1] \n"\ + " strneb %[gfx_z2], [%[depth], #(" #p " + 1)] \n"\ + " strneh r1, [%[screen], #((" #p " + 1) * 2)] \n"\ + "3: \n" + + FN(0) + FN(2) + FN(4) + FN(6) + // Loop + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r0", "r1", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" +#define FN1(p) \ + " ldrb r1, [%[bp], #( 7 - " #p ")] \n"\ + " ldrb r0, [%[bp], #(7 - " #p " - 1)] \n"\ + " movs r1, r1, lsl #2 \n"\ + " ldrne r1, [%[colors], r1] \n"\ + " strneb %[gfx_z2], [%[depth], #" #p "] \n"\ + " strneh r1, [%[screen], #(" #p " * 2)] \n"\ + "3: \n"\ + " movs r1, r0, lsl #2 \n"\ + " ldrne r1, [%[colors], r1] \n"\ + " strneb %[gfx_z2], [%[depth], #(" #p " + 1)] \n"\ + " strneh r1, [%[screen], #((" #p " + 1) * 2 )] \n"\ + "3: \n" + + FN1(0) + FN1(2) + FN1(4) + FN1(6) + // Loop + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r0", "r1", "cc" // r8 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + FN(2) + FN(4) + FN(6) + // Loop + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + StartLine) + // clobbered + : "r0", "r1", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + FN1(2) + FN1(4) + FN1(6) + // Loop + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + StartLine) + // clobbered + : "r0", "r1", "cc" // r8 & flags + ); + + } + } +#undef FN +#undef FN1 + +} +#endif // #ifdef __FAST_OBJS__ + +// DrawTile16 ----------------------------------------- +void DrawTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" +#define FN(p) \ + " ldrb r9, [%[depth], #" #p "] \n"\ + " ldrb r8, [%[depth], #(" #p " + 1)] \n"\ + " cmp %[gfx_z1], r9 \n"\ + " ldrhib r9, [%[bp], #" #p "] \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" #p "] \n"\ + " strneh r9, [%[screen], #(" #p " * 2)] \n"\ + "3: \n"\ + " cmp %[gfx_z1], r8 \n"\ + " ldrhib r9, [%[bp], #(" #p " + 1)] \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #(" #p " + 1)] \n"\ + " strneh r9, [%[screen], #((" #p " + 1) * 2)] \n"\ + "3: \n" + + FN(0) + FN(2) + FN(4) + FN(6) + // Loop + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" +#define FN1(p) \ + " ldrb r9, [%[depth], #" #p "] \n"\ + " ldrb r8, [%[depth], #(" #p " + 1)] \n"\ + " cmp %[gfx_z1], r9 \n"\ + " ldrhib r9, [%[bp], #( 7 - " #p ")] \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" #p "] \n"\ + " strneh r9, [%[screen], #(" #p " * 2)] \n"\ + "3: \n"\ + " cmp %[gfx_z1], r8 \n"\ + " ldrhib r9, [%[bp], #(7 - " #p " - 1)] \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #(" #p " + 1)] \n"\ + " strneh r9, [%[screen], #((" #p " + 1) * 2 )] \n"\ + "3: \n" + + FN1(0) + FN1(2) + FN1(4) + FN1(6) + // Loop + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + FN(2) + FN(4) + FN(6) + // Loop + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + FN1(2) + FN1(4) + FN1(6) + // Loop + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + StartLine) + // clobbered + : "r9", "r8", "cc" // r8, r9 & flags + ); + + } + } +#undef FN +#undef FN1 + +} + +// DrawClippedTile16 ----------------------------------------- +void DrawClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ +if (Width == 0) return; +if (Width == 8) { + DrawTile16 (Tile, Offset, StartLine, LineCount); + return; + } + + TILE_PREAMBLE +Offset += StartPixel; + +#define FN(p) \ + " ldrb r8, [%[depth], #" #p "] \n"\ + " ldrb r9, [%[bp], #" #p "] \n"\ + " cmp %[gfx_z1], r8 \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" #p "] \n"\ + " strneh r9, [%[screen], #(" #p " * 2)] \n"\ + "3: \n" + +#define FN1(p) \ + " ldrb r8, [%[depth], #" #p "] \n"\ + " ldrb r9, [%[bp], #(7 - " #p ")] \n"\ + " cmp %[gfx_z1], r8 \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" #p "] \n"\ + " strneh r9, [%[screen], #(" #p " * 2)] \n"\ + "3: \n"\ + +switch(Width) { + case 1: +// -- Width = 1 ------ +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + + } + } + break; + case 2: +// -- Width = 2 ------ +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + FN(0) + FN(1) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + + FN1(0) + FN1(1) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + FN(1) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + FN1(1) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + + } + } + + break; + case 3: +// -- Width = 3 ------ +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + FN(0) + FN(1) + FN(2) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + + FN1(0) + FN1(1) + FN1(2) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + FN(1) + FN(2) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + FN1(1) + FN1(2) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + + } + } + + break; + case 4: +// -- Width = 4 ------ +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + FN(0) + FN(1) + FN(2) + FN(3) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + + FN1(0) + FN1(1) + FN1(2) + FN1(3) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + FN(1) + FN(2) + FN(3) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + FN1(1) + FN1(2) + FN1(3) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + + } + } + + break; + case 5: +// -- Width = 5 ------ +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + FN(0) + FN(1) + FN(2) + FN(3) + FN(4) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + + FN1(0) + FN1(1) + FN1(2) + FN1(3) + FN1(4) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + FN(1) + FN(2) + FN(3) + FN(4) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + FN1(1) + FN1(2) + FN1(3) + FN1(4) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + + } + } + + break; + case 6: +// -- Width = 6 ------ +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + FN(0) + FN(1) + FN(2) + FN(3) + FN(4) + FN(5) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + + FN1(0) + FN1(1) + FN1(2) + FN1(3) + FN1(4) + FN1(5) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + FN(1) + FN(2) + FN(3) + FN(4) + FN(5) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + FN1(1) + FN1(2) + FN1(3) + FN1(4) + FN1(5) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + + } + } + + break; + case 7: +// -- Width = 7 ------ +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + FN(0) + FN(1) + FN(2) + FN(3) + FN(4) + FN(5) + FN(6) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + + FN1(0) + FN1(1) + FN1(2) + FN1(3) + FN1(4) + FN1(5) + FN1(6) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN(0) + FN(1) + FN(2) + FN(3) + FN(4) + FN(5) + FN(6) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1(0) + FN1(1) + FN1(2) + FN1(3) + FN1(4) + FN1(5) + FN1(6) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r9", "r8", "cc" // r9 & flags + ); + + } + } + + break; + } + + + + + +#undef FN +#undef FN1 +#undef C + +} +/* +void DrawClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ +if (Width == 0) return; + +if (Width == 8) { + DrawTile16 (Tile, Offset, StartLine, LineCount); + return; + } + + TILE_PREAMBLE +Offset += StartPixel; +// sizeof(FN) = 32 bytes +#define SIZEOF_FN (8 * 4) +#define FN(p) \ + " ldrb r8, [%[depth], #" #p "] \n"\ + " ldrb r9, [%[bp], #" #p "] \n"\ + " cmp %[gfx_z1], r8 \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" #p "] \n"\ + " strneh r9, [%[screen], #(" #p " * 2)] \n"\ + "3: \n" +// sizeof(FN1) = 32 bytes +#define SIZEOF_FN1 (8 * 4) +#define FN1(p) \ + " ldrb r8, [%[depth], #" #p "] \n"\ + " ldrb r9, [%[bp], #(7 - " #p ")] \n"\ + " cmp %[gfx_z1], r8 \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" #p "] \n"\ + " strneh r9, [%[screen], #(" #p " * 2)] \n"\ + "3: \n"\ + +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + " add %[width], %[width], pc \n" + " bx %[width] \n" + "2: \n" + FN(6) + FN(5) + FN(4) + FN(3) + FN(2) + FN(1) + FN(0) + + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bxne %[width] \n" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" ((7 - Width) * SIZEOF_FN), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r8", "r9", "cc" // r8, r9 & flags + ); + } else { + asm volatile ( + " add %[width], %[width], pc \n" + " bx %[width] \n" + "2: \n" + FN1(6) + FN1(5) + FN1(4) + FN1(3) + FN1(2) + FN1(1) + FN1(0) + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bxne %[width] \n" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" ((7 - Width) * SIZEOF_FN1), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r8", "r9", "cc" // r8, r9 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + " add %[width], %[width], pc \n" + " bx %[width] \n" + "2: \n" + FN(6) + FN(5) + FN(4) + FN(3) + FN(2) + FN(1) + FN(0) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bxne %[width] \n" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" ((7 - Width) * SIZEOF_FN), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r8", "r9", "cc" // r8, r9 & flags + ); + } else { + asm volatile ( + " add %[width], %[width], pc \n" + " bx %[width] \n" + "2: \n" + FN1(6) + FN1(5) + FN1(4) + FN1(3) + FN1(2) + FN1(1) + FN1(0) + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bxne %[width] \n" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" ((7 - Width) * SIZEOF_FN1), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r8", "r9", "cc" // r8, r9 & flags + ); + + } + } +} +*/ +void DrawTile16x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + uint32 l; + + RENDER_TILE(WRITE_4PIXELS16x2, WRITE_4PIXELS16_FLIPPEDx2, 8) +} + +void DrawClippedTile16x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + uint32 l; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16x2, WRITE_4PIXELS16_FLIPPEDx2, 8) +} + +void DrawTile16x2x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + uint32 l; + + RENDER_TILE(WRITE_4PIXELS16x2x2, WRITE_4PIXELS16_FLIPPEDx2x2, 8) +} + +void DrawClippedTile16x2x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + uint32 l; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16x2x2, WRITE_4PIXELS16_FLIPPEDx2x2, 8) +} + +void DrawLargePixel16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + uint32 l; + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + uint16 pixel; + +#define PLOT_PIXEL(screen, pixel) (pixel) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], PLOT_PIXEL) +} + + +void DrawLargePixel16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + uint32 l; + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + register uint16 pixel; + +#define LARGE_ADD_PIXEL(s, p) \ +(Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_ADD (p, *(s + GFX.Delta)) : \ + COLOR_ADD (p, GFX.FixedColour)) \ + : p) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_ADD_PIXEL) +} + +void DrawLargePixel16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + uint32 l; + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + register uint16 pixel; + +#define LARGE_ADD_PIXEL1_2(s, p) \ +((uint16) (Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_ADD1_2 (p, *(s + GFX.Delta)) : \ + COLOR_ADD (p, GFX.FixedColour)) \ + : p)) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_ADD_PIXEL1_2) +} + +void DrawLargePixel16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + uint32 l; + + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + register uint16 pixel; + +#define LARGE_SUB_PIXEL(s, p) \ +(Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_SUB (p, *(s + GFX.Delta)) : \ + COLOR_SUB (p, GFX.FixedColour)) \ + : p) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_SUB_PIXEL) +} + +void DrawLargePixel16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + uint32 l; + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint16 pixel; + +#define LARGE_SUB_PIXEL1_2(s, p) \ +(Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_SUB1_2 (p, *(s + GFX.Delta)) : \ + COLOR_SUB (p, GFX.FixedColour)) \ + : p) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_SUB_PIXEL1_2) +} + +void DrawHiResTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + uint32 l; + + register uint8 *bp; + + RENDER_TILEHI(WRITE_4PIXELSHI16, WRITE_4PIXELSHI16_FLIPPED, 4) +} + +void DrawHiResClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + uint32 l; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILEHI(WRITE_4PIXELSHI16, WRITE_4PIXELSHI16_FLIPPED, 4) +} diff --git a/src/tile16.cpp.bak b/src/tile16.cpp.bak new file mode 100644 index 0000000..abc30e0 --- /dev/null +++ b/src/tile16.cpp.bak @@ -0,0 +1,814 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +// ARM V5 Assembly by bitrider + +#include "snes9x.h" + +#include "memmap.h" +#include "ppu.h" +#include "display.h" +#include "gfx.h" +#include "tile16.h" + +#ifdef USE_GLIDE +#include "3d.h" +#endif + +extern uint32 HeadMask [4]; +extern uint32 TailMask [5]; + +uint8 ConvertTile (uint8 *pCache, uint32 TileAddr) +{ + register uint8 *tp = &Memory.VRAM[TileAddr]; + uint32 *p = (uint32 *) pCache; + uint32 non_zero = 0; + uint8 line; + uint32 p1; + uint32 p2; + register uint8 pix; + + switch (BG.BitShift) + { + case 8: + for (line = 8; line != 0; line--, tp += 2) + { + p1 = p2 = 0; + if ((pix = *(tp + 0))) + { + p1 |= odd_high[0][pix >> 4]; + p2 |= odd_low[0][pix & 0xf]; + } + if ((pix = *(tp + 1))) + { + p1 |= even_high[0][pix >> 4]; + p2 |= even_low[0][pix & 0xf]; + } + if ((pix = *(tp + 16))) + { + p1 |= odd_high[1][pix >> 4]; + p2 |= odd_low[1][pix & 0xf]; + } + if ((pix = *(tp + 17))) + { + p1 |= even_high[1][pix >> 4]; + p2 |= even_low[1][pix & 0xf]; + } + if ((pix = *(tp + 32))) + { + p1 |= odd_high[2][pix >> 4]; + p2 |= odd_low[2][pix & 0xf]; + } + if ((pix = *(tp + 33))) + { + p1 |= even_high[2][pix >> 4]; + p2 |= even_low[2][pix & 0xf]; + } + if ((pix = *(tp + 48))) + { + p1 |= odd_high[3][pix >> 4]; + p2 |= odd_low[3][pix & 0xf]; + } + if ((pix = *(tp + 49))) + { + p1 |= even_high[3][pix >> 4]; + p2 |= even_low[3][pix & 0xf]; + } + *p++ = p1; + *p++ = p2; + non_zero |= p1 | p2; + } + break; + + case 4: + for (line = 8; line != 0; line--, tp += 2) + { + p1 = p2 = 0; + if ((pix = *(tp + 0))) + { + p1 |= odd_high[0][pix >> 4]; + p2 |= odd_low[0][pix & 0xf]; + } + if ((pix = *(tp + 1))) + { + p1 |= even_high[0][pix >> 4]; + p2 |= even_low[0][pix & 0xf]; + } + if ((pix = *(tp + 16))) + { + p1 |= odd_high[1][pix >> 4]; + p2 |= odd_low[1][pix & 0xf]; + } + if ((pix = *(tp + 17))) + { + p1 |= even_high[1][pix >> 4]; + p2 |= even_low[1][pix & 0xf]; + } + *p++ = p1; + *p++ = p2; + non_zero |= p1 | p2; + } + break; + + case 2: + for (line = 8; line != 0; line--, tp += 2) + { + p1 = p2 = 0; + if ((pix = *(tp + 0))) + { + p1 |= odd_high[0][pix >> 4]; + p2 |= odd_low[0][pix & 0xf]; + } + if ((pix = *(tp + 1))) + { + p1 |= even_high[0][pix >> 4]; + p2 |= even_low[0][pix & 0xf]; + } + *p++ = p1; + *p++ = p2; + non_zero |= p1 | p2; + } + break; + } + return (non_zero ? TRUE : BLANK_TILE); +} + + +inline void WRITE_4PIXELSHI16 (uint32 Offset, uint8 *Pixels) +{ + uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[2*N])) \ + { \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +inline void WRITE_4PIXELSHI16_FLIPPED (uint32 Offset, uint8 *Pixels) +{ + uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N] && (Pixel = Pixels[6 - 2*N])) \ + { \ + Screen [N] = GFX.ScreenColors [Pixel]; \ + Depth [N] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16x2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPEDx2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16x2x2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = Screen [(GFX_PITCH >> 1) + N * 2] = \ + Screen [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = Depth [(GFX_PITCH >> 1) + N * 2] = \ + Depth [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +INLINE void WRITE_4PIXELS16_FLIPPEDx2x2 (uint32 Offset, uint8 *Pixels) +{ + register uint32 Pixel; + uint16 *Screen = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + +#define FN(N) \ + if (GFX.Z1 > Depth [N * 2] && (Pixel = Pixels[3 - N])) \ + { \ + Screen [N * 2] = Screen [N * 2 + 1] = Screen [(GFX_PITCH >> 1) + N * 2] = \ + Screen [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.ScreenColors [Pixel]; \ + Depth [N * 2] = Depth [N * 2 + 1] = Depth [(GFX_PITCH >> 1) + N * 2] = \ + Depth [(GFX_PITCH >> 1) + N * 2 + 1] = GFX.Z2; \ + } + + FN(0) + FN(1) + FN(2) + FN(3) +#undef FN +} + +// DrawTile16 ----------------------------------------- +void DrawTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" +#define FN(p, p2, p3, p4) \ + " ldrb r9, [%[depth], #" p "] \n"\ + " ldrb r8, [%[depth], #" p3 "] \n"\ + " cmp %[gfx_z1], r9 \n"\ + " ldrhib r9, [%[bp], #" p "] \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p "] \n"\ + " strneh r9, [%[screen], #" p2 "] \n"\ + "3: \n"\ + " cmp %[gfx_z1], r8 \n"\ + " ldrhib r9, [%[bp], #" p3 "] \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p3 "] \n"\ + " strneh r9, [%[screen], #" p4 "] \n"\ + "3: \n" + + FN("0", "0", "1", "2") + FN("2", "4", "3", "6") + FN("4", "8", "5", "10") + FN("6", "12", "7", "14") + // Loop + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" +#define FN1(p, p2, p3, p4, p5, p6) \ + " ldrb r9, [%[depth], #" p "] \n"\ + " ldrb r8, [%[depth], #" p4 "] \n"\ + " cmp %[gfx_z1], r9 \n"\ + " ldrhib r9, [%[bp], #" p3 "] \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p "] \n"\ + " strneh r9, [%[screen], #" p2 "] \n"\ + "3: \n"\ + " cmp %[gfx_z1], r8 \n"\ + " ldrhib r9, [%[bp], #" p6 "] \n"\ + " bls 3f \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p4 "] \n"\ + " strneh r9, [%[screen], #" p5 "] \n"\ + "3: \n" + + FN1("0", "0", "7", "1", "2", "6") + FN1("2", "4", "5", "3", "6", "4") + FN1("4", "8", "3", "5", "10", "2") + FN1("6", "12", "1", "7", "14", "0") + // Loop + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN("0", "0", "1", "2") + FN("2", "4", "3", "6") + FN("4", "8", "5", "10") + FN("6", "12", "7", "14") + // Loop + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1("0", "0", "7", "1", "2", "6") + FN1("2", "4", "5", "3", "6", "4") + FN1("4", "8", "3", "5", "10", "2") + FN1("6", "12", "1", "7", "14", "0") + // Loop + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + + } + } +#undef FN +#undef FN1 + +} + +// DrawClippedTile16 ----------------------------------------- +void DrawClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ +if (Width == 0) return; + + TILE_PREAMBLE + +Offset = Offset + StartPixel; + +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" +#define FN(p) \ + " ldrb r9, [%[depth], #" p "] \n"\ + " cmp %[gfx_z1], r9 \n"\ + " bls 3f \n"\ + " ldrb r9, [%[bp], #" p "] \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p "] \n"\ + " strneh r9, [%[screen], #(" p " * 2)] \n"\ + "3: \n" + +#define C(p) " cmp %[width], #(" p " + 1) \n"\ + " beq 1f \n" + + FN("0") + C("0") + FN("1") + C("1") + FN("2") + C("2") + FN("3") + C("3") + FN("4") + C("4") + FN("5") + C("5") + FN("6") + C("6") + FN("7") + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r9", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" +#define FN1(p) \ + " ldrb r9, [%[depth], #" p "] \n"\ + " cmp %[gfx_z1], r9 \n"\ + " bls 3f \n"\ + " ldrb r9, [%[bp], #(7 - " p ")] \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p "] \n"\ + " strneh r9, [%[screen], #(" p " * 2)] \n"\ + "3: \n"\ + + FN1("0") + C("0") + FN1("1") + C("1") + FN1("2") + C("2") + FN1("3") + C("3") + FN1("4") + C("4") + FN1("5") + C("5") + FN1("6") + C("6") + FN1("7") + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r9", "cc" // r8 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN("0") + C("0") + FN("1") + C("1") + FN("2") + C("2") + FN("3") + C("3") + FN("4") + C("4") + FN("5") + C("5") + FN("6") + C("6") + FN("7") + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r9", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1("0") + C("0") + FN1("1") + C("1") + FN1("2") + C("2") + FN1("3") + C("3") + FN1("4") + C("4") + FN1("5") + C("5") + FN1("6") + C("6") + FN1("7") + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r9", "cc" // r8 & flags + ); + + } + } +#undef FN +#undef FN1 +#undef C + +} + + +void DrawTile16x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16x2, WRITE_4PIXELS16_FLIPPEDx2, 8) +} + +void DrawClippedTile16x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16x2, WRITE_4PIXELS16_FLIPPEDx2, 8) +} + +void DrawTile16x2x2 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILE(WRITE_4PIXELS16x2x2, WRITE_4PIXELS16_FLIPPEDx2x2, 8) +} + +void DrawClippedTile16x2x2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILE(WRITE_4PIXELS16x2x2, WRITE_4PIXELS16_FLIPPEDx2x2, 8) +} + +void DrawLargePixel16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.DB + Offset; + uint16 pixel; + +#define PLOT_PIXEL(screen, pixel) (pixel) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], PLOT_PIXEL) +} + + +void DrawLargePixel16Add (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + register uint16 pixel; + +#define LARGE_ADD_PIXEL(s, p) \ +(Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_ADD (p, *(s + GFX.Delta)) : \ + COLOR_ADD (p, GFX.FixedColour)) \ + : p) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_ADD_PIXEL) +} + +void DrawLargePixel16Add1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + register uint16 pixel; + +#define LARGE_ADD_PIXEL1_2(s, p) \ +((uint16) (Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_ADD1_2 (p, *(s + GFX.Delta)) : \ + COLOR_ADD (p, GFX.FixedColour)) \ + : p)) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_ADD_PIXEL1_2) +} + +void DrawLargePixel16Sub (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + register uint16 pixel; + +#define LARGE_SUB_PIXEL(s, p) \ +(Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_SUB (p, *(s + GFX.Delta)) : \ + COLOR_SUB (p, GFX.FixedColour)) \ + : p) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_SUB_PIXEL) +} + +void DrawLargePixel16Sub1_2 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Pixels, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + + register uint16 *sp = (uint16 *) GFX.S + Offset; + uint8 *Depth = GFX.ZBuffer + Offset; + uint16 pixel; + +#define LARGE_SUB_PIXEL1_2(s, p) \ +(Depth [z + GFX.DepthDelta] ? (Depth [z + GFX.DepthDelta] != 1 ? \ + COLOR_SUB1_2 (p, *(s + GFX.Delta)) : \ + COLOR_SUB (p, GFX.FixedColour)) \ + : p) + + RENDER_TILE_LARGE (GFX.ScreenColors [pixel], LARGE_SUB_PIXEL1_2) +} + +void DrawHiResTile16 (uint32 Tile, uint32 Offset, uint32 StartLine, + uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + RENDER_TILEHI(WRITE_4PIXELSHI16, WRITE_4PIXELSHI16_FLIPPED, 4) +} + +void DrawHiResClippedTile16 (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + register uint8 *bp; + + TILE_CLIP_PREAMBLE + RENDER_CLIPPED_TILEHI(WRITE_4PIXELSHI16, WRITE_4PIXELSHI16_FLIPPED, 4) +} diff --git a/src/tile16.h b/src/tile16.h new file mode 100644 index 0000000..3fc1be6 --- /dev/null +++ b/src/tile16.h @@ -0,0 +1,308 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ +#ifndef _TILE_H_ +#define _TILE_H_ + + +void SelectConvertTile(); +void SelectPalette(); +extern uint8 (*ConvertTile) (uint8 *pCache, uint32 TileAddr); + +extern uint32 TileBlank; + +#define TILE_PREAMBLE \ + uint8 *pCache; \ +\ + uint32 TileAddr = (BG.TileAddress + ((Tile & 0x3ff) << BG.TileShift)) & 0xffff; \ +\ + uint32 TileNumber; \ + pCache = &BG.Buffer[(TileNumber = (TileAddr >> BG.TileShift)) << 6]; \ +\ + if (!BG.Buffered [TileNumber]) BG.Buffered[TileNumber] = ConvertTile (pCache, TileAddr); \ +\ + if (BG.Buffered [TileNumber] == BLANK_TILE){ \ + TileBlank = Tile; \ + return; \ + } \ +\ + GFX.ScreenColors = &GFX.ScreenColorsPre[(Tile & GFX.PaletteMask) >> GFX.PaletteShift]; + +#define RENDER_TILE(NORMAL, FLIPPED, N) \ + register int inc; \ + if (!(Tile & V_FLIP)){ \ + bp = pCache + StartLine; \ + inc = 8; \ + } else { \ + bp = pCache + 56 - StartLine; \ + inc = -8; \ + } \ + \ + l = LineCount; \ + if (!(Tile & H_FLIP)){ \ + while ( l-- ){ \ + NORMAL (Offset, bp); \ + NORMAL (Offset + N, bp + 4); \ + bp += inc, Offset += GFX_PPL; \ + } \ + } else { \ + while ( l-- ){ \ + FLIPPED (Offset, bp + 4); \ + FLIPPED (Offset + N, bp); \ + bp += inc, Offset += GFX_PPL; \ + } \ + } + +#define TILE_CLIP_PREAMBLE \ + uint32 dd; \ + uint32 d1; \ + uint32 d2; \ +\ + if (StartPixel < 4) \ + { \ + d1 = HeadMask [StartPixel]; \ + if (StartPixel + Width < 4) \ + d1 &= TailMask [StartPixel + Width]; \ + } \ + else \ + d1 = 0; \ +\ + if (StartPixel + Width > 4) \ + { \ + if (StartPixel > 4) \ + d2 = HeadMask [StartPixel - 4]; \ + else \ + d2 = 0xffffffff; \ +\ + d2 &= TailMask [(StartPixel + Width - 4)]; \ + } \ + else \ + d2 = 0; + + +#define RENDER_CLIPPED_TILE(NORMAL, FLIPPED, N) \ + register int inc; \ + if (Tile & V_FLIP){ \ + bp = pCache + 56 - StartLine; \ + inc = -8; \ + } else { \ + bp = pCache + StartLine; \ + inc = 8; \ + } \ + \ + l = LineCount; \ + if (!(Tile & H_FLIP)){ \ + while ( l-- ){ \ + if ((dd = (*(uint32 *) bp) & d1)) \ + NORMAL (Offset, (uint8 *) &dd); \ + if ((dd = (*(uint32 *) (bp + 4)) & d2)) \ + NORMAL (Offset + N, (uint8 *) &dd); \ + bp += inc, Offset += GFX_PPL; \ + } \ + } else { \ + SWAP_DWORD (d1); \ + SWAP_DWORD (d2); \ + while ( l-- ){ \ + if ((dd = *(uint32 *) (bp + 4) & d1)) \ + FLIPPED (Offset, (uint8 *) &dd); \ + if ((dd = *(uint32 *) bp & d2)) \ + FLIPPED (Offset + N, (uint8 *) &dd); \ + bp += inc, Offset += GFX_PPL; \ + } \ + } + +#define RENDER_TILE_LARGE(PIXEL, FUNCTION) \ + if (!(Tile & (V_FLIP | H_FLIP))) \ + { \ + if ((pixel = *(pCache + StartLine + StartPixel))) \ + { \ + pixel = PIXEL; \ + for (l = LineCount; l != 0; l--, sp += GFX_PPL, Depth += GFX_PPL) \ + { \ + for (int z = Pixels - 1; z >= 0; z--) \ + if (GFX.Z1 > Depth [z]) \ + { \ + sp [z] = FUNCTION(sp + z, pixel); \ + Depth [z] = GFX.Z2; \ + }\ + } \ + } \ + } \ + else \ + if (!(Tile & V_FLIP)) \ + { \ + StartPixel = 7 - StartPixel; \ + if ((pixel = *(pCache + StartLine + StartPixel))) \ + { \ + pixel = PIXEL; \ + for (l = LineCount; l != 0; l--, sp += GFX_PPL, Depth += GFX_PPL) \ + { \ + for (int z = Pixels - 1; z >= 0; z--) \ + if (GFX.Z1 > Depth [z]) \ + { \ + sp [z] = FUNCTION(sp + z, pixel); \ + Depth [z] = GFX.Z2; \ + }\ + } \ + } \ + } \ + else \ + if (Tile & H_FLIP) \ + { \ + StartPixel = 7 - StartPixel; \ + if ((pixel = *(pCache + 56 - StartLine + StartPixel))) \ + { \ + pixel = PIXEL; \ + for (l = LineCount; l != 0; l--, sp += GFX_PPL, Depth += GFX_PPL) \ + { \ + for (int z = Pixels - 1; z >= 0; z--) \ + if (GFX.Z1 > Depth [z]) \ + { \ + sp [z] = FUNCTION(sp + z, pixel); \ + Depth [z] = GFX.Z2; \ + }\ + } \ + } \ + } \ + else \ + { \ + if ((pixel = *(pCache + 56 - StartLine + StartPixel))) \ + { \ + pixel = PIXEL; \ + for (l = LineCount; l != 0; l--, sp += GFX_PPL, Depth += GFX_PPL) \ + { \ + for (int z = Pixels - 1; z >= 0; z--) \ + if (GFX.Z1 > Depth [z]) \ + { \ + sp [z] = FUNCTION(sp + z, pixel); \ + Depth [z] = GFX.Z2; \ + }\ + } \ + } \ + } + +#define RENDER_TILEHI(NORMAL, FLIPPED, N) \ + if (!(Tile & (V_FLIP | H_FLIP))) \ + { \ + bp = pCache + StartLine; \ + for (l = LineCount; l != 0; l--, bp += 8, Offset += GFX_PPL) \ + { \ + /*if (*(uint32 *) bp)*/if (((uint32)bp[0])|((uint32)bp[2])|((uint32)bp[4])|((uint32)bp[6])) \ + NORMAL (Offset, bp); \ + } \ + } \ + else \ + if (!(Tile & V_FLIP)) \ + { \ + bp = pCache + StartLine; \ + for (l = LineCount; l != 0; l--, bp += 8, Offset += GFX_PPL) \ + { \ + /*if (*(uint32 *) (bp + 4))*/if (((uint32)bp[0])|((uint32)bp[2])|((uint32)bp[4])|((uint32)bp[6])) \ + FLIPPED (Offset, bp); \ + } \ + } \ + else \ + if (Tile & H_FLIP) \ + { \ + bp = pCache + 56 - StartLine; \ + for (l = LineCount; l != 0; l--, bp -= 8, Offset += GFX_PPL) \ + { \ + /*if (*(uint32 *) (bp + 4))*/if (((uint32)bp[0])|((uint32)bp[2])|((uint32)bp[4])|((uint32)bp[6])) \ + FLIPPED (Offset, bp); \ + } \ + } \ + else \ + { \ + bp = pCache + 56 - StartLine; \ + for (l = LineCount; l != 0; l--, bp -= 8, Offset += GFX_PPL) \ + { \ + /*if (*(uint32 *) bp)*/if (((uint32)bp[0])|((uint32)bp[2])|((uint32)bp[4])|((uint32)bp[6])) \ + NORMAL (Offset, bp); \ + } \ + } + + + +#define RENDER_CLIPPED_TILEHI(NORMAL, FLIPPED, N) \ + d1=(d1&0xFF)|((d1&0xFF0000)>>8)|((d2&0xFF)<<16)|((d2&0xFF0000)<<8);\ + if (!(Tile & (V_FLIP | H_FLIP))) \ + { \ + bp = pCache + StartLine; \ + for (l = LineCount; l != 0; l--, bp += 8, Offset += GFX_PPL) \ + { \ + /*if ((dd = (*(uint32 *) bp) & d1))*/if (dd = (((((uint32)bp[6])<<24)|(((uint32)bp[4])<<16)|(((uint32)bp[2])<<8)|((uint32)bp[0]))&d1)) \ + NORMAL (Offset, (uint8 *) &dd); \ + } \ + } \ + else \ + if (!(Tile & V_FLIP)) \ + { \ + bp = pCache + StartLine; \ + SWAP_DWORD (d1); \ + /*SWAP_DWORD (d2);*/ \ + for (l = LineCount; l != 0; l--, bp += 8, Offset += GFX_PPL) \ + { \ + /*if ((dd = *(uint32 *) (bp + 4) & d1))*/if (dd = (((((uint32)bp[6])<<24)|(((uint32)bp[4])<<16)|(((uint32)bp[2])<<8)|((uint32)bp[0]))&d1)) \ + FLIPPED (Offset, (uint8 *) &dd); \ + } \ + } \ + else \ + if (Tile & H_FLIP) \ + { \ + bp = pCache + 56 - StartLine; \ + SWAP_DWORD (d1); \ + /*SWAP_DWORD (d2);*/ \ + for (l = LineCount; l != 0; l--, bp -= 8, Offset += GFX_PPL) \ + { \ + /*if ((dd = *(uint32 *) (bp + 4) & d1))*/if (dd = (((((uint32)bp[6])<<24)|(((uint32)bp[4])<<16)|(((uint32)bp[2])<<8)|((uint32)bp[0]))&d1)) \ + FLIPPED (Offset, (uint8 *) &dd); \ + } \ + } \ + else \ + { \ + bp = pCache + 56 - StartLine; \ + for (l = LineCount; l != 0; l--, bp -= 8, Offset += GFX_PPL) \ + { \ + /*if ((dd = (*(uint32 *) bp) & d1))*/ if (dd = (((((uint32)bp[6])<<24)|(((uint32)bp[4])<<16)|(((uint32)bp[2])<<8)|((uint32)bp[0]))&d1)) \ + NORMAL (Offset, (uint8 *) &dd); \ + } \ + } + +#endif diff --git a/src/tile16_t.h b/src/tile16_t.h new file mode 100644 index 0000000..db1916e --- /dev/null +++ b/src/tile16_t.h @@ -0,0 +1,519 @@ +/* + Templates for + + DrawTile16 + DrawClippedTile16 +*/ + +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "display.h" +#include "gfx.h" +#include "tile16.h" + +#define MACRO_CONCAT(a,b) a##b +#define DEC_DRAW(n) MACRO_CONCAT(void DrawTile16, n)(uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount) +#define DEC_DRAWCLIPPED(n) MACRO_CONCAT(void DrawClippedTile16, n)(uint32 Tile, uint32 Offset, uint32 StartPixel, uint32 Width, uint32 StartLine, uint32 LineCount) + +#ifdef __FAST_OBJS__ + +#define DEC_DRAWNOZ(n) MACRO_CONCAT(void DrawNoZTile16, n)(uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount) + +#define ROW(width) \ + " mov r10, " width " \n" \ + "7:\n" \ + " ldrb r9, [%[bp]], #1 \n"\ + " add %[depth], %[depth], #1 \n"\ + " movs r9, r9, lsl #2 \n"\ + " beq 3f \n"\ + \ + " ldrb r8, [%[subdepth], %[depth]] \n"\ + " ldr r9, [%[colors], r9] \n"\ + " strb %[gfx_z2], [%[depth], #(-1)] \n"\ + \ + " cmp r8, #1 \n"\ + " blo 4f \n"\ + " ldrneh r8, [%[screen], %[delta]] \n"\ + " moveq r8, %[fixedcolour] \n"\ + ROP \ + "4: \n"\ + " strh r9, [%[screen]] \n"\ + \ + "3: \n"\ + " subs r10, r10, #1 \n"\ + " add %[screen], %[screen], #2 \n"\ + " bne 7b \n" + +#define ROW1(width) \ + " mov r10, " width " \n" \ + "7:\n" \ + " ldrb r9, [%[bp]], #-1 \n"\ + " add %[depth], %[depth], #1 \n"\ + " movs r9, r9, lsl #2 \n"\ + " beq 3f \n"\ + \ + " ldrb r8, [%[subdepth], %[depth]] \n"\ + " ldr r9, [%[colors], r9] \n"\ + " strb %[gfx_z2], [%[depth], #(-1)] \n"\ + \ + " cmp r8, #1 \n"\ + " blo 4f \n"\ + " ldrneh r8, [%[screen], %[delta]] \n"\ + " moveq r8, %[fixedcolour] \n"\ + ROP \ + "4: \n"\ + " strh r9, [%[screen]] \n"\ + \ + "3: \n"\ + " subs r10, r10, #1 \n"\ + " add %[screen], %[screen], #2 \n"\ + " bne 7b \n" + + + + +// DrawNoZTile16 ----------------------------------------- +DEC_DRAWNOZ(ROPNAME) +{ + TILE_PREAMBLE + + if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + ROW("#8") + + " sub %[bp], %[bp], #(8+8) \n" + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("#8") + + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + ROW("#8") + + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("#8") + + " add %[bp], %[bp], #(8+8) \n" + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + + } + } +} + +#undef ROW +#undef ROW1 + +#endif // #ifdef __FAST_OBJS__ + + +#define ROW(width) \ + " ldrb r8, [%[depth]], #1 \n"\ + " mov r10, " width " \n" \ + "7:\n" \ + \ + " cmp %[gfx_z1], r8 \n"\ + " ldrhib r9, [%[bp]] \n"\ + " bls 3f \n"\ + \ + " movs r9, r9, lsl #2 \n"\ + " beq 3f \n"\ + \ + " ldrb r8, [%[subdepth], %[depth]] \n"\ + " ldr r9, [%[colors], r9] \n"\ + " strb %[gfx_z2], [%[depth], #(-1)] \n"\ + \ + " cmp r8, #1 \n"\ + " blo 4f \n"\ + " ldrneh r8, [%[screen], %[delta]] \n"\ + " moveq r8, %[fixedcolour] \n"\ + \ + ROP \ + "4: \n"\ + " strh r9, [%[screen]] \n"\ + \ + "3: \n"\ + \ + " subs r10, r10, #1 \n"\ + " add %[bp], %[bp], #1 \n"\ + " add %[screen], %[screen], #2 \n"\ + " ldrneb r8, [%[depth]], #1 \n"\ + " bne 7b \n" + +#define ROW1(width) \ + " ldrb r8, [%[depth]], #1 \n"\ + " mov r10, " width " \n" \ + "7:\n" \ + \ + " cmp %[gfx_z1], r8 \n"\ + " ldrhib r9, [%[bp]] \n"\ + " bls 3f \n"\ + \ + " movs r9, r9, lsl #2 \n"\ + " beq 3f \n"\ + \ + " ldrb r8, [%[subdepth], %[depth]] \n"\ + " ldr r9, [%[colors], r9] \n"\ + " strb %[gfx_z2], [%[depth], #(-1)] \n"\ + \ + " cmp r8, #1 \n"\ + " blo 4f \n"\ + " ldrneh r8, [%[screen], %[delta]] \n"\ + " moveq r8, %[fixedcolour] \n"\ + \ + ROP \ + "4: \n"\ + " strh r9, [%[screen]] \n"\ + \ + "3: \n"\ + \ + " subs r10, r10, #1 \n"\ + " sub %[bp], %[bp], #1 \n"\ + " add %[screen], %[screen], #2 \n"\ + " ldrneb r8, [%[depth]], #1 \n"\ + " bne 7b \n" + + +// DrawTile16 ----------------------------------------- +DEC_DRAW(ROPNAME) +{ + TILE_PREAMBLE + + if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + ROW("#8") + + " sub %[bp], %[bp], #(8+8) \n" + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("#8") + + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + ROW("#8") + + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("#8") + + " add %[bp], %[bp], #(8+8) \n" + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + + } + } +} + +// DrawClippedTile16 ----------------------------------------- +DEC_DRAWCLIPPED(ROPNAME) +{ +if (Width == 0) return; + + TILE_PREAMBLE + +Offset = Offset + StartPixel; +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + ROW("%[width]") + + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + // -- + " sub %[bp], %[bp], %[width] \n" + " sub %[screen], %[screen], %[width], lsl #1 \n" + " sub %[depth], %[depth], %[width] \n" + // -- + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [width] "r" (Width), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("%[width]") + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + // -- + " add %[bp], %[bp], %[width] \n" + " sub %[screen], %[screen], %[width], lsl #1 \n" + " sub %[depth], %[depth], %[width] \n" + // -- + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [width] "r" (Width), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine - StartPixel + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + ROW("%[width]") + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + // -- + " sub %[bp], %[bp], %[width] \n" + " sub %[screen], %[screen], %[width], lsl #1 \n" + " sub %[depth], %[depth], %[width] \n" + // -- + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [width] "r" (Width), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("%[width]") + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + // -- + " add %[bp], %[bp], %[width] \n" + " sub %[screen], %[screen], %[width], lsl #1 \n" + " sub %[depth], %[depth], %[width] \n" + // -- + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (GFX.FixedColour), + [width] "r" (Width), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine - StartPixel + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + + } + } +} diff --git a/src/tile16add.cpp b/src/tile16add.cpp new file mode 100644 index 0000000..2211644 --- /dev/null +++ b/src/tile16add.cpp @@ -0,0 +1,48 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +// ARM V5 Assembly by bitrider + +#include "rops.h" +#define ROPNAME Add +#define ROP ROP_ADD(r9, r8) + +#include "tile16_t.h" diff --git a/src/tile16add1_2.cpp b/src/tile16add1_2.cpp new file mode 100644 index 0000000..ad52769 --- /dev/null +++ b/src/tile16add1_2.cpp @@ -0,0 +1,48 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +// ARM V5 Assembly by bitrider + +#include "rops.h" +#define ROPNAME Add1_2 +#define ROP ROP_ADD1_2(r9, r8) + +#include "tile16_t.h" diff --git a/src/tile16f_t.h b/src/tile16f_t.h new file mode 100644 index 0000000..70b5cff --- /dev/null +++ b/src/tile16f_t.h @@ -0,0 +1,340 @@ +/* + Templates for + + DrawTile16 + DrawClippedTile16 +*/ + +#include "snes9x.h" +#include "memmap.h" +#include "ppu.h" +#include "display.h" +#include "gfx.h" +#include "tile16.h" + +#define ROW(width) \ + " ldrb r8, [%[depth]], #1 \n"\ + " mov r10, " width " \n" \ + "7:\n" \ + \ + " cmp %[gfx_z1], r8 \n"\ + " ldrhib r9, [%[bp]] \n"\ + " bls 3f \n"\ + \ + " movs r9, r9, lsl #2 \n"\ + " beq 3f \n"\ + \ + " ldrb r8, [%[subdepth], %[depth]] \n"\ + " ldr r9, [%[colors], r9] \n"\ + " strb %[gfx_z2], [%[depth], #(-1)] \n"\ + \ + " cmp r8, #1 \n"\ + " bne 4f \n"\ + \ + ROP \ + "4: \n"\ + " strh r9, [%[screen]] \n"\ + \ + "3: \n"\ + \ + " add %[bp], %[bp], #1 \n"\ + " add %[screen], %[screen], #2 \n"\ + " subs r10, r10, #1 \n"\ + " ldrneb r8, [%[depth]], #1 \n"\ + " bne 7b \n" + +#define ROW1(width) \ + " ldrb r8, [%[depth]], #1 \n"\ + " mov r10, " width " \n" \ + "7:\n" \ + \ + " cmp %[gfx_z1], r8 \n"\ + " ldrhib r9, [%[bp]] \n"\ + " bls 3f \n"\ + \ + " movs r9, r9, lsl #2 \n"\ + " beq 3f \n"\ + \ + " ldrb r8, [%[subdepth], %[depth]] \n"\ + " ldr r9, [%[colors], r9] \n"\ + " strb %[gfx_z2], [%[depth], #(-1)] \n"\ + \ + " cmp r8, #1 \n"\ + " bne 4f \n"\ + \ + ROP \ + "4: \n"\ + " strh r9, [%[screen]] \n"\ + \ + "3: \n"\ + \ + " sub %[bp], %[bp], #1 \n"\ + " add %[screen], %[screen], #2 \n"\ + " subs r10, r10, #1 \n"\ + " ldrneb r8, [%[depth]], #1 \n"\ + " bne 7b \n" + + +#define MACRO_CONCAT(a,b) a##b +#define DEC_DRAW(n) MACRO_CONCAT(void DrawTile16, n)(uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount) +#define DEC_DRAWCLIPPED(n) MACRO_CONCAT(void DrawClippedTile16, n)(uint32 Tile, uint32 Offset, uint32 StartPixel, uint32 Width, uint32 StartLine, uint32 LineCount) + + +// DrawTile16 ----------------------------------------- +DEC_DRAW(ROPNAME) +{ + TILE_PREAMBLE + + if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + ROW("#8") + + " sub %[bp], %[bp], #(8+8) \n" + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (FIXEDCOLOUR), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("#8") + + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (FIXEDCOLOUR), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + ROW("#8") + + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (FIXEDCOLOUR), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("#8") + + " add %[bp], %[bp], #(8+8) \n" + " add %[screen], %[screen], #(640-16) \n" + " add %[depth], %[depth], #(320-8) \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (FIXEDCOLOUR), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + + } + } +} + +// DrawClippedTile16 ----------------------------------------- +DEC_DRAWCLIPPED(ROPNAME) +{ +if (Width == 0) return; + + TILE_PREAMBLE + +Offset = Offset + StartPixel; +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + + ROW("%[width]") + + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + // -- + " sub %[bp], %[bp], %[width] \n" + " sub %[screen], %[screen], %[width], lsl #1 \n" + " sub %[depth], %[depth], %[width] \n" + // -- + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (FIXEDCOLOUR), + [width] "r" (Width), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("%[width]") + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + // -- + " add %[bp], %[bp], %[width] \n" + " sub %[screen], %[screen], %[width], lsl #1 \n" + " sub %[depth], %[depth], %[width] \n" + // -- + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (FIXEDCOLOUR), + [width] "r" (Width), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + 56 - StartLine - StartPixel + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + ROW("%[width]") + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + // -- + " sub %[bp], %[bp], %[width] \n" + " sub %[screen], %[screen], %[width], lsl #1 \n" + " sub %[depth], %[depth], %[width] \n" + // -- + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (FIXEDCOLOUR), + [width] "r" (Width), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r8", "r9", "r10", "cc" + ); + } else { + asm volatile ( + "2: \n" + ROW1("%[width]") + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + // -- + " add %[bp], %[bp], %[width] \n" + " sub %[screen], %[screen], %[width], lsl #1 \n" + " sub %[depth], %[depth], %[width] \n" + // -- + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : [lcount] "+r" (LineCount) + // input + : [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [colors] "r" (GFX.ScreenColors), + [delta] "r" (GFX.Delta << 1), + [fixedcolour] "r" (FIXEDCOLOUR), + [width] "r" (Width), + [screen] "r" ((uint16 *) GFX.S + Offset), + [depth] "r" (GFX.ZBuffer + Offset), + [subdepth] "r" (GFX.DepthDelta - 1), + [bp] "r" (pCache + StartLine - StartPixel + 7) + // clobbered + : "r8", "r9", "r10", "cc" + ); + + } + } +} diff --git a/src/tile16fadd1_2.cpp b/src/tile16fadd1_2.cpp new file mode 100644 index 0000000..752416b --- /dev/null +++ b/src/tile16fadd1_2.cpp @@ -0,0 +1,61 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +// ARM V5 Assembly by bitrider + +#define FIXEDCOLOUR (GFX.FixedColour & (~0x01860)) + +#define ROPNAME FixedAdd1_2 + +#define ROP \ + " bic r9, r9, #0b00000100000100000 \n"\ + " bic r9, r9, #0b00001000001000000 \n"\ + " add r9, r9, %[fixedcolour] \n"\ + " mov r9, r9, lsr #1 \n"\ + " tst r9, #0b00000000000100000 \n"\ + " orrne r9, r9, #0b00000000000011111 \n"\ + " tst r9, #0b00000100000000000 \n"\ + " orrne r9, r9, #0b00000011111100000 \n"\ + " tst r9, #0b10000000000000000 \n"\ + " orrne r9, r9, #0b01111100000000000 \n" + + +#include "tile16f_t.h" diff --git a/src/tile16fsub1_2.cpp b/src/tile16fsub1_2.cpp new file mode 100644 index 0000000..a22c4a5 --- /dev/null +++ b/src/tile16fsub1_2.cpp @@ -0,0 +1,64 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +// ARM V5 Assembly by bitrider + +#define FIXEDCOLOUR ((GFX.FixedColour >> 1) & (~0x0C30)) +#define ROPNAME FixedSub1_2 +#define ROP \ + " mov r9, r9, lsr #1 \n"\ + " bic r9, r9, #0b00000010000010000 \n"\ + \ + " bic r8, r8, #0b00000100000100000 \n"\ + " orr r9, r9, #0b00000100000100000 \n"\ + " orr r9, r9, #0b10000000000000000 \n"\ + " sub r9, r9, %[fixedcolour] \n"\ + " tst r9, #0b00000000000100000 \n"\ + " biceq r9, r9, #0b00000000000011111 \n"\ + " tst r9, #0b00000100000000000 \n"\ + " biceq r9, r9, #0b00000011111100000 \n"\ + " tst r9, #0b10000000000000000 \n"\ + " biceq r9, r9, #0b01111100000000000 \n"\ + + +#include "tile16f_t.h" + + diff --git a/src/tile16noprio.cpp b/src/tile16noprio.cpp new file mode 100644 index 0000000..8f39a71 --- /dev/null +++ b/src/tile16noprio.cpp @@ -0,0 +1,407 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +// ARM V5 Assembly by bitrider + + +#include "snes9x.h" + +#include "memmap.h" +#include "ppu.h" +#include "display.h" + #include "gfx.h" +#include "tile16.h" + +#ifdef USE_GLIDE +#include "3d.h" +#endif + +extern uint32 HeadMask [4]; +extern uint32 TailMask [5]; + +extern uint8 ConvertTile (uint8 *pCache, uint32 TileAddr); + +// DrawTile16 ----------------------------------------- +void DrawTile16NoPrio (uint32 Tile, uint32 Offset, uint32 StartLine, uint32 LineCount) +{ + TILE_PREAMBLE + +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" +#define FN(p, p2, p3, p4) \ + " ldrb r9, [%[bp], #" p "] \n"\ + " ldrb r8, [%[bp], #" p3 "] \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p "] \n"\ + " strneh r9, [%[screen], #" p2 "] \n"\ + "3: \n"\ + " movs r9, r8, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p3 "] \n"\ + " strneh r9, [%[screen], #" p4 "] \n"\ + "3: \n" + + FN("0", "0", "1", "2") + FN("2", "4", "3", "6") + FN("4", "8", "5", "10") + FN("6", "12", "7", "14") + // Loop + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" +#define FN1(p, p2, p3, p4, p5, p6) \ + " ldrb r9, [%[bp], #" p3 "] \n"\ + " ldrb r8, [%[bp], #" p6 "] \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p "] \n"\ + " strneh r9, [%[screen], #" p2 "] \n"\ + "3: \n"\ + " movs r9, r8, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p4 "] \n"\ + " strneh r9, [%[screen], #" p5 "] \n"\ + "3: \n" + + FN1("0", "0", "7", "1", "2", "6") + FN1("2", "4", "5", "3", "6", "4") + FN1("4", "8", "3", "5", "10", "2") + FN1("6", "12", "1", "7", "14", "0") + // Loop + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + 56 - StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN("0", "0", "1", "2") + FN("2", "4", "3", "6") + FN("4", "8", "5", "10") + FN("6", "12", "7", "14") + // Loop + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1("0", "0", "7", "1", "2", "6") + FN1("2", "4", "5", "3", "6", "4") + FN1("4", "8", "3", "5", "10", "2") + FN1("6", "12", "1", "7", "14", "0") + // Loop + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [bp] "r" (pCache + StartLine) + // clobbered + : "r9", "r8", "cc" // r8 & flags + ); + + } + } +#undef FN +#undef FN1 + +} + +// DrawClippedTile16NoPrio ----------------------------------------- +void DrawClippedTile16NoPrio (uint32 Tile, uint32 Offset, + uint32 StartPixel, uint32 Width, + uint32 StartLine, uint32 LineCount) +{ +if (Width == 0) return; + + TILE_PREAMBLE + +Offset = Offset + StartPixel; + +if (Tile & V_FLIP){ + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" +#define FN(p) \ + " ldrb r9, [%[bp], #" p "] \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p "] \n"\ + " strneh r9, [%[screen], #(" p " * 2)] \n"\ + "3: \n" + +#define C(p) " cmp %[width], #(" p " + 1) \n"\ + " beq 1f \n" + + FN("0") + C("0") + FN("1") + C("1") + FN("2") + C("2") + FN("3") + C("3") + FN("4") + C("4") + FN("5") + C("5") + FN("6") + C("6") + FN("7") + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine + StartPixel) + // clobbered + : "r9", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" +#define FN1(p) \ + " ldrb r9, [%[bp], #(7 - " p ")] \n"\ + " movs r9, r9, lsl #2 \n"\ + " ldrne r9, [%[colors], r9] \n"\ + " strneb %[gfx_z2], [%[depth], #" p "] \n"\ + " strneh r9, [%[screen], #(" p " * 2)] \n"\ + "3: \n"\ + + FN1("0") + C("0") + FN1("1") + C("1") + FN1("2") + C("2") + FN1("3") + C("3") + FN1("4") + C("4") + FN1("5") + C("5") + FN1("6") + C("6") + FN1("7") + // Loop + "1: \n" + " sub %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + 56 - StartLine - StartPixel) + // clobbered + : "r9", "cc" // r8 & flags + ); + } +} else { + if (!(Tile & H_FLIP)){ + asm volatile ( + "2: \n" + FN("0") + C("0") + FN("1") + C("1") + FN("2") + C("2") + FN("3") + C("3") + FN("4") + C("4") + FN("5") + C("5") + FN("6") + C("6") + FN("7") + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine + StartPixel) + // clobbered + : "r9", "cc" // r8 & flags + ); + } else { + asm volatile ( + "2: \n" + FN1("0") + C("0") + FN1("1") + C("1") + FN1("2") + C("2") + FN1("3") + C("3") + FN1("4") + C("4") + FN1("5") + C("5") + FN1("6") + C("6") + FN1("7") + // Loop + "1: \n" + " add %[bp], %[bp], #8 \n" + " add %[screen], %[screen], #640 \n" + " add %[depth], %[depth], #320 \n" + " subs %[lcount], %[lcount], #1 \n" + " bne 2b" + // output + : // none + // input + : [lcount] "r" (LineCount), + [gfx_z1] "r" (GFX.Z1), + [gfx_z2] "r" (GFX.Z2), + [screen] "r" ((uint16 *) GFX.S + Offset), + [colors] "r" (GFX.ScreenColors), + [depth] "r" (GFX.DB + Offset), + [width] "r" (Width), + [bp] "r" (pCache + StartLine - StartPixel) + // clobbered + : "r9", "cc" // r8 & flags + ); + + } + } +#undef FN +#undef FN1 +#undef C + +} + diff --git a/src/tile16sub.cpp b/src/tile16sub.cpp new file mode 100644 index 0000000..9066e23 --- /dev/null +++ b/src/tile16sub.cpp @@ -0,0 +1,48 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +// ARM V5 Assembly by bitrider + +#include "rops.h" +#define ROPNAME Sub +#define ROP ROP_SUB(r9, r8) + +#include "tile16_t.h" diff --git a/src/tile16sub1_2.cpp b/src/tile16sub1_2.cpp new file mode 100644 index 0000000..0adaa0c --- /dev/null +++ b/src/tile16sub1_2.cpp @@ -0,0 +1,50 @@ +/* + * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator. + * + * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and + * Jerremy Koot (jkoot@snes9x.com) + * + * Super FX C emulator code + * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and + * Gary Henderson. + * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_. + * + * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson. + * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_. + * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com). + * + * DOS port code contains the works of other authors. See headers in + * individual files. + * + * Snes9x homepage: http://www.snes9x.com + * + * Permission to use, copy, modify and distribute Snes9x in both binary and + * source form, for non-commercial purposes, is hereby granted without fee, + * providing that this license information and copyright notice appear with + * all copies and any derived work. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event shall the authors be held liable for any damages + * arising from the use of this software. + * + * Snes9x is freeware for PERSONAL USE only. Commercial users should + * seek permission of the copyright holders first. Commercial use includes + * charging money for Snes9x or software derived from Snes9x. + * + * The copyright holders request that bug fixes and improvements to the code + * should be forwarded to them so everyone can benefit from the modifications + * in future versions. + * + * Super NES and Super Nintendo Entertainment System are trademarks of + * Nintendo Co., Limited and its subsidiary companies. + */ + +// ARM V5 Assembly by bitrider + +#include "rops.h" +#define ROPNAME Sub1_2 +#define ROP ROP_SUB1_2(r9, r8) + +#include "tile16_t.h" + + diff --git a/src/touchscreen.c b/src/touchscreen.c new file mode 100644 index 0000000..90e0b81 --- /dev/null +++ b/src/touchscreen.c @@ -0,0 +1,47 @@ +#include "stdio.h" +#include "stdlib.h" +#include "tslib.h" + +struct tsdev *ts = NULL; + +int InitTouchScreen(void) { + // Taken directly from tslib test sources, slightly modifed + char *tsdevice = NULL; + + if( (tsdevice = getenv("TSLIB_TSDEVICE")) != NULL ) { + ts = ts_open(tsdevice, 1); + } else { + ts = ts_open("/dev/input/event0", 1); + } + + if (!ts) { + perror("ts_open"); + return 0; + } + if (ts_config(ts)) { + perror("ts_config"); + return 0; + } + + return 1; +} + +void DeInitTouchScreen(void) { + // Nothing to do +} + + +// return -1 on error, else pressure value + +int getTouchScreen(int *x, int *y) { + struct ts_sample tsdata; + + if (ts == NULL) return -1; + + if (ts_read(ts, &tsdata, 1) != 1) return -1; + + *x = tsdata.x; + *y = tsdata.y; + return tsdata.pressure; +} + diff --git a/src/touchscreen.h b/src/touchscreen.h new file mode 100644 index 0000000..c475521 --- /dev/null +++ b/src/touchscreen.h @@ -0,0 +1,10 @@ +#ifdef __cplusplus +extern "C" { +#endif + +int InitTouchScreen(void); +int getTouchScreen(int *x, int *y); + +#ifdef __cplusplus +} +#endif diff --git a/src/unzip.c b/src/unzip.c new file mode 100644 index 0000000..3a70629 --- /dev/null +++ b/src/unzip.c @@ -0,0 +1,1598 @@ +/* unzip.c -- IO for uncompress .zip files using zlib + Version 1.01e, February 12th, 2005 + + Copyright (C) 1998-2005 Gilles Vollant + + Read unzip.h for more info +*/ + +/* Decryption code comes from crypt.c by Info-ZIP but has been greatly reduced in terms of +compatibility with older software. The following is from the original crypt.c. Code +woven in by Terry Thorsen 1/2003. +*/ +/* + Copyright (c) 1990-2000 Info-ZIP. All rights reserved. + + See the accompanying file LICENSE, version 2000-Apr-09 or later + (the contents of which are also included in zip.h) for terms of use. + If, for some reason, all these files are missing, the Info-ZIP license + also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html +*/ +/* + crypt.c (full version) by Info-ZIP. Last revised: [see crypt.h] + + The encryption/decryption parts of this source code (as opposed to the + non-echoing password parts) were originally written in Europe. The + whole source package can be freely distributed, including from the USA. + (Prior to January 2000, re-export from the US was a violation of US law.) + */ + +/* + This encryption code is a direct transcription of the algorithm from + Roger Schlafly, described by Phil Katz in the file appnote.txt. This + file (appnote.txt) is distributed with the PKZIP program (even in the + version without encryption capabilities). + */ + + +#include +#include +#include +#include "zlib.h" +#include "unzip.h" + +#ifdef STDC +# include +# include +# include +#endif +#ifdef NO_ERRNO_H + extern int errno; +#else +# include +#endif + + +#ifndef local +# define local static +#endif +/* compile with -Dlocal if your debugger can't find static symbols */ + + +#ifndef CASESENSITIVITYDEFAULT_NO +# if !defined(unix) && !defined(CASESENSITIVITYDEFAULT_YES) +# define CASESENSITIVITYDEFAULT_NO +# endif +#endif + + +#ifndef UNZ_BUFSIZE +#define UNZ_BUFSIZE (16384) +#endif + +#ifndef UNZ_MAXFILENAMEINZIP +#define UNZ_MAXFILENAMEINZIP (256) +#endif + +#ifndef ALLOC +# define ALLOC(size) (malloc(size)) +#endif +#ifndef TRYFREE +# define TRYFREE(p) {if (p) free(p);} +#endif + +#define SIZECENTRALDIRITEM (0x2e) +#define SIZEZIPLOCALHEADER (0x1e) + + + + +const char unz_copyright[] = + " unzip 1.01 Copyright 1998-2004 Gilles Vollant - http://www.winimage.com/zLibDll"; + +/* unz_file_info_interntal contain internal info about a file in zipfile*/ +typedef struct unz_file_info_internal_s +{ + uLong offset_curfile;/* relative offset of local header 4 bytes */ +} unz_file_info_internal; + + +/* file_in_zip_read_info_s contain internal information about a file in zipfile, + when reading and decompress it */ +typedef struct +{ + char *read_buffer; /* internal buffer for compressed data */ + z_stream stream; /* zLib stream structure for inflate */ + + uLong pos_in_zipfile; /* position in byte on the zipfile, for fseek*/ + uLong stream_initialised; /* flag set if stream structure is initialised*/ + + uLong offset_local_extrafield;/* offset of the local extra field */ + uInt size_local_extrafield;/* size of the local extra field */ + uLong pos_local_extrafield; /* position in the local extra field in read*/ + + uLong crc32; /* crc32 of all data uncompressed */ + uLong crc32_wait; /* crc32 we must obtain after decompress all */ + uLong rest_read_compressed; /* number of byte to be decompressed */ + uLong rest_read_uncompressed;/*number of byte to be obtained after decomp*/ + zlib_filefunc_def z_filefunc; + voidpf filestream; /* io structore of the zipfile */ + uLong compression_method; /* compression method (0==store) */ + uLong byte_before_the_zipfile;/* byte before the zipfile, (>0 for sfx)*/ + int raw; +} file_in_zip_read_info_s; + + +/* unz_s contain internal information about the zipfile +*/ +typedef struct +{ + zlib_filefunc_def z_filefunc; + voidpf filestream; /* io structore of the zipfile */ + unz_global_info gi; /* public global information */ + uLong byte_before_the_zipfile;/* byte before the zipfile, (>0 for sfx)*/ + uLong num_file; /* number of the current file in the zipfile*/ + uLong pos_in_central_dir; /* pos of the current file in the central dir*/ + uLong current_file_ok; /* flag about the usability of the current file*/ + uLong central_pos; /* position of the beginning of the central dir*/ + + uLong size_central_dir; /* size of the central directory */ + uLong offset_central_dir; /* offset of start of central directory with + respect to the starting disk number */ + + unz_file_info cur_file_info; /* public info about the current file in zip*/ + unz_file_info_internal cur_file_info_internal; /* private info about it*/ + file_in_zip_read_info_s* pfile_in_zip_read; /* structure about the current + file if we are decompressing it */ + int encrypted; +# ifndef NOUNCRYPT + unsigned long keys[3]; /* keys defining the pseudo-random sequence */ + const unsigned long* pcrc_32_tab; +# endif +} unz_s; + + +#ifndef NOUNCRYPT +#include "crypt.h" +#endif + +/* =========================================================================== + Read a byte from a gz_stream; update next_in and avail_in. Return EOF + for end of file. + IN assertion: the stream s has been sucessfully opened for reading. +*/ + + +local int unzlocal_getByte OF(( + const zlib_filefunc_def* pzlib_filefunc_def, + voidpf filestream, + int *pi)); + +local int unzlocal_getByte(pzlib_filefunc_def,filestream,pi) + const zlib_filefunc_def* pzlib_filefunc_def; + voidpf filestream; + int *pi; +{ + unsigned char c; + int err = (int)ZREAD(*pzlib_filefunc_def,filestream,&c,1); + if (err==1) + { + *pi = (int)c; + return UNZ_OK; + } + else + { + if (ZERROR(*pzlib_filefunc_def,filestream)) + return UNZ_ERRNO; + else + return UNZ_EOF; + } +} + + +/* =========================================================================== + Reads a long in LSB order from the given gz_stream. Sets +*/ +local int unzlocal_getShort OF(( + const zlib_filefunc_def* pzlib_filefunc_def, + voidpf filestream, + uLong *pX)); + +local int unzlocal_getShort (pzlib_filefunc_def,filestream,pX) + const zlib_filefunc_def* pzlib_filefunc_def; + voidpf filestream; + uLong *pX; +{ + uLong x ; + int i; + int err; + + err = unzlocal_getByte(pzlib_filefunc_def,filestream,&i); + x = (uLong)i; + + if (err==UNZ_OK) + err = unzlocal_getByte(pzlib_filefunc_def,filestream,&i); + x += ((uLong)i)<<8; + + if (err==UNZ_OK) + *pX = x; + else + *pX = 0; + return err; +} + +local int unzlocal_getLong OF(( + const zlib_filefunc_def* pzlib_filefunc_def, + voidpf filestream, + uLong *pX)); + +local int unzlocal_getLong (pzlib_filefunc_def,filestream,pX) + const zlib_filefunc_def* pzlib_filefunc_def; + voidpf filestream; + uLong *pX; +{ + uLong x ; + int i; + int err; + + err = unzlocal_getByte(pzlib_filefunc_def,filestream,&i); + x = (uLong)i; + + if (err==UNZ_OK) + err = unzlocal_getByte(pzlib_filefunc_def,filestream,&i); + x += ((uLong)i)<<8; + + if (err==UNZ_OK) + err = unzlocal_getByte(pzlib_filefunc_def,filestream,&i); + x += ((uLong)i)<<16; + + if (err==UNZ_OK) + err = unzlocal_getByte(pzlib_filefunc_def,filestream,&i); + x += ((uLong)i)<<24; + + if (err==UNZ_OK) + *pX = x; + else + *pX = 0; + return err; +} + + +/* My own strcmpi / strcasecmp */ +local int strcmpcasenosensitive_internal (fileName1,fileName2) + const char* fileName1; + const char* fileName2; +{ + for (;;) + { + char c1=*(fileName1++); + char c2=*(fileName2++); + if ((c1>='a') && (c1<='z')) + c1 -= 0x20; + if ((c2>='a') && (c2<='z')) + c2 -= 0x20; + if (c1=='\0') + return ((c2=='\0') ? 0 : -1); + if (c2=='\0') + return 1; + if (c1c2) + return 1; + } +} + + +#ifdef CASESENSITIVITYDEFAULT_NO +#define CASESENSITIVITYDEFAULTVALUE 2 +#else +#define CASESENSITIVITYDEFAULTVALUE 1 +#endif + +#ifndef STRCMPCASENOSENTIVEFUNCTION +#define STRCMPCASENOSENTIVEFUNCTION strcmpcasenosensitive_internal +#endif + +/* + Compare two filename (fileName1,fileName2). + If iCaseSenisivity = 1, comparision is case sensitivity (like strcmp) + If iCaseSenisivity = 2, comparision is not case sensitivity (like strcmpi + or strcasecmp) + If iCaseSenisivity = 0, case sensitivity is defaut of your operating system + (like 1 on Unix, 2 on Windows) + +*/ +extern int ZEXPORT unzStringFileNameCompare (fileName1,fileName2,iCaseSensitivity) + const char* fileName1; + const char* fileName2; + int iCaseSensitivity; +{ + if (iCaseSensitivity==0) + iCaseSensitivity=CASESENSITIVITYDEFAULTVALUE; + + if (iCaseSensitivity==1) + return strcmp(fileName1,fileName2); + + return STRCMPCASENOSENTIVEFUNCTION(fileName1,fileName2); +} + +#ifndef BUFREADCOMMENT +#define BUFREADCOMMENT (0x400) +#endif + +/* + Locate the Central directory of a zipfile (at the end, just before + the global comment) +*/ +local uLong unzlocal_SearchCentralDir OF(( + const zlib_filefunc_def* pzlib_filefunc_def, + voidpf filestream)); + +local uLong unzlocal_SearchCentralDir(pzlib_filefunc_def,filestream) + const zlib_filefunc_def* pzlib_filefunc_def; + voidpf filestream; +{ + unsigned char* buf; + uLong uSizeFile; + uLong uBackRead; + uLong uMaxBack=0xffff; /* maximum size of global comment */ + uLong uPosFound=0; + + if (ZSEEK(*pzlib_filefunc_def,filestream,0,ZLIB_FILEFUNC_SEEK_END) != 0) + return 0; + + + uSizeFile = ZTELL(*pzlib_filefunc_def,filestream); + + if (uMaxBack>uSizeFile) + uMaxBack = uSizeFile; + + buf = (unsigned char*)ALLOC(BUFREADCOMMENT+4); + if (buf==NULL) + return 0; + + uBackRead = 4; + while (uBackReaduMaxBack) + uBackRead = uMaxBack; + else + uBackRead+=BUFREADCOMMENT; + uReadPos = uSizeFile-uBackRead ; + + uReadSize = ((BUFREADCOMMENT+4) < (uSizeFile-uReadPos)) ? + (BUFREADCOMMENT+4) : (uSizeFile-uReadPos); + if (ZSEEK(*pzlib_filefunc_def,filestream,uReadPos,ZLIB_FILEFUNC_SEEK_SET)!=0) + break; + + if (ZREAD(*pzlib_filefunc_def,filestream,buf,uReadSize)!=uReadSize) + break; + + for (i=(int)uReadSize-3; (i--)>0;) + if (((*(buf+i))==0x50) && ((*(buf+i+1))==0x4b) && + ((*(buf+i+2))==0x05) && ((*(buf+i+3))==0x06)) + { + uPosFound = uReadPos+i; + break; + } + + if (uPosFound!=0) + break; + } + TRYFREE(buf); + return uPosFound; +} + +/* + Open a Zip file. path contain the full pathname (by example, + on a Windows NT computer "c:\\test\\zlib114.zip" or on an Unix computer + "zlib/zlib114.zip". + If the zipfile cannot be opened (file doesn't exist or in not valid), the + return value is NULL. + Else, the return value is a unzFile Handle, usable with other function + of this unzip package. +*/ +extern unzFile ZEXPORT unzOpen2 (path, pzlib_filefunc_def) + const char *path; + zlib_filefunc_def* pzlib_filefunc_def; +{ + unz_s us; + unz_s *s; + uLong central_pos,uL; + + uLong number_disk; /* number of the current dist, used for + spaning ZIP, unsupported, always 0*/ + uLong number_disk_with_CD; /* number the the disk with central dir, used + for spaning ZIP, unsupported, always 0*/ + uLong number_entry_CD; /* total number of entries in + the central dir + (same than number_entry on nospan) */ + + int err=UNZ_OK; + + if (unz_copyright[0]!=' ') + return NULL; + + if (pzlib_filefunc_def==NULL) + fill_fopen_filefunc(&us.z_filefunc); + else + us.z_filefunc = *pzlib_filefunc_def; + + us.filestream= (*(us.z_filefunc.zopen_file))(us.z_filefunc.opaque, + path, + ZLIB_FILEFUNC_MODE_READ | + ZLIB_FILEFUNC_MODE_EXISTING); + if (us.filestream==NULL) + return NULL; + + central_pos = unzlocal_SearchCentralDir(&us.z_filefunc,us.filestream); + if (central_pos==0) + err=UNZ_ERRNO; + + if (ZSEEK(us.z_filefunc, us.filestream, + central_pos,ZLIB_FILEFUNC_SEEK_SET)!=0) + err=UNZ_ERRNO; + + /* the signature, already checked */ + if (unzlocal_getLong(&us.z_filefunc, us.filestream,&uL)!=UNZ_OK) + err=UNZ_ERRNO; + + /* number of this disk */ + if (unzlocal_getShort(&us.z_filefunc, us.filestream,&number_disk)!=UNZ_OK) + err=UNZ_ERRNO; + + /* number of the disk with the start of the central directory */ + if (unzlocal_getShort(&us.z_filefunc, us.filestream,&number_disk_with_CD)!=UNZ_OK) + err=UNZ_ERRNO; + + /* total number of entries in the central dir on this disk */ + if (unzlocal_getShort(&us.z_filefunc, us.filestream,&us.gi.number_entry)!=UNZ_OK) + err=UNZ_ERRNO; + + /* total number of entries in the central dir */ + if (unzlocal_getShort(&us.z_filefunc, us.filestream,&number_entry_CD)!=UNZ_OK) + err=UNZ_ERRNO; + + if ((number_entry_CD!=us.gi.number_entry) || + (number_disk_with_CD!=0) || + (number_disk!=0)) + err=UNZ_BADZIPFILE; + + /* size of the central directory */ + if (unzlocal_getLong(&us.z_filefunc, us.filestream,&us.size_central_dir)!=UNZ_OK) + err=UNZ_ERRNO; + + /* offset of start of central directory with respect to the + starting disk number */ + if (unzlocal_getLong(&us.z_filefunc, us.filestream,&us.offset_central_dir)!=UNZ_OK) + err=UNZ_ERRNO; + + /* zipfile comment length */ + if (unzlocal_getShort(&us.z_filefunc, us.filestream,&us.gi.size_comment)!=UNZ_OK) + err=UNZ_ERRNO; + + if ((central_pospfile_in_zip_read!=NULL) + unzCloseCurrentFile(file); + + ZCLOSE(s->z_filefunc, s->filestream); + TRYFREE(s); + return UNZ_OK; +} + + +/* + Write info about the ZipFile in the *pglobal_info structure. + No preparation of the structure is needed + return UNZ_OK if there is no problem. */ +extern int ZEXPORT unzGetGlobalInfo (file,pglobal_info) + unzFile file; + unz_global_info *pglobal_info; +{ + unz_s* s; + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + *pglobal_info=s->gi; + return UNZ_OK; +} + + +/* + Translate date/time from Dos format to tm_unz (readable more easilty) +*/ +local void unzlocal_DosDateToTmuDate (ulDosDate, ptm) + uLong ulDosDate; + tm_unz* ptm; +{ + uLong uDate; + uDate = (uLong)(ulDosDate>>16); + ptm->tm_mday = (uInt)(uDate&0x1f) ; + ptm->tm_mon = (uInt)((((uDate)&0x1E0)/0x20)-1) ; + ptm->tm_year = (uInt)(((uDate&0x0FE00)/0x0200)+1980) ; + + ptm->tm_hour = (uInt) ((ulDosDate &0xF800)/0x800); + ptm->tm_min = (uInt) ((ulDosDate&0x7E0)/0x20) ; + ptm->tm_sec = (uInt) (2*(ulDosDate&0x1f)) ; +} + +/* + Get Info about the current file in the zipfile, with internal only info +*/ +local int unzlocal_GetCurrentFileInfoInternal OF((unzFile file, + unz_file_info *pfile_info, + unz_file_info_internal + *pfile_info_internal, + char *szFileName, + uLong fileNameBufferSize, + void *extraField, + uLong extraFieldBufferSize, + char *szComment, + uLong commentBufferSize)); + +local int unzlocal_GetCurrentFileInfoInternal (file, + pfile_info, + pfile_info_internal, + szFileName, fileNameBufferSize, + extraField, extraFieldBufferSize, + szComment, commentBufferSize) + unzFile file; + unz_file_info *pfile_info; + unz_file_info_internal *pfile_info_internal; + char *szFileName; + uLong fileNameBufferSize; + void *extraField; + uLong extraFieldBufferSize; + char *szComment; + uLong commentBufferSize; +{ + unz_s* s; + unz_file_info file_info; + unz_file_info_internal file_info_internal; + int err=UNZ_OK; + uLong uMagic; + long lSeek=0; + + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + if (ZSEEK(s->z_filefunc, s->filestream, + s->pos_in_central_dir+s->byte_before_the_zipfile, + ZLIB_FILEFUNC_SEEK_SET)!=0) + err=UNZ_ERRNO; + + + /* we check the magic */ + if (err==UNZ_OK) + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&uMagic) != UNZ_OK) + err=UNZ_ERRNO; + else if (uMagic!=0x02014b50) + err=UNZ_BADZIPFILE; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&file_info.version) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&file_info.version_needed) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&file_info.flag) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&file_info.compression_method) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&file_info.dosDate) != UNZ_OK) + err=UNZ_ERRNO; + + unzlocal_DosDateToTmuDate(file_info.dosDate,&file_info.tmu_date); + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&file_info.crc) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&file_info.compressed_size) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&file_info.uncompressed_size) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&file_info.size_filename) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&file_info.size_file_extra) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&file_info.size_file_comment) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&file_info.disk_num_start) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&file_info.internal_fa) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&file_info.external_fa) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&file_info_internal.offset_curfile) != UNZ_OK) + err=UNZ_ERRNO; + + lSeek+=file_info.size_filename; + if ((err==UNZ_OK) && (szFileName!=NULL)) + { + uLong uSizeRead ; + if (file_info.size_filename0) && (fileNameBufferSize>0)) + if (ZREAD(s->z_filefunc, s->filestream,szFileName,uSizeRead)!=uSizeRead) + err=UNZ_ERRNO; + lSeek -= uSizeRead; + } + + + if ((err==UNZ_OK) && (extraField!=NULL)) + { + uLong uSizeRead ; + if (file_info.size_file_extraz_filefunc, s->filestream,lSeek,ZLIB_FILEFUNC_SEEK_CUR)==0) + lSeek=0; + else + err=UNZ_ERRNO; + if ((file_info.size_file_extra>0) && (extraFieldBufferSize>0)) + if (ZREAD(s->z_filefunc, s->filestream,extraField,uSizeRead)!=uSizeRead) + err=UNZ_ERRNO; + lSeek += file_info.size_file_extra - uSizeRead; + } + else + lSeek+=file_info.size_file_extra; + + + if ((err==UNZ_OK) && (szComment!=NULL)) + { + uLong uSizeRead ; + if (file_info.size_file_commentz_filefunc, s->filestream,lSeek,ZLIB_FILEFUNC_SEEK_CUR)==0) + lSeek=0; + else + err=UNZ_ERRNO; + if ((file_info.size_file_comment>0) && (commentBufferSize>0)) + if (ZREAD(s->z_filefunc, s->filestream,szComment,uSizeRead)!=uSizeRead) + err=UNZ_ERRNO; + lSeek+=file_info.size_file_comment - uSizeRead; + } + else + lSeek+=file_info.size_file_comment; + + if ((err==UNZ_OK) && (pfile_info!=NULL)) + *pfile_info=file_info; + + if ((err==UNZ_OK) && (pfile_info_internal!=NULL)) + *pfile_info_internal=file_info_internal; + + return err; +} + + + +/* + Write info about the ZipFile in the *pglobal_info structure. + No preparation of the structure is needed + return UNZ_OK if there is no problem. +*/ +extern int ZEXPORT unzGetCurrentFileInfo (file, + pfile_info, + szFileName, fileNameBufferSize, + extraField, extraFieldBufferSize, + szComment, commentBufferSize) + unzFile file; + unz_file_info *pfile_info; + char *szFileName; + uLong fileNameBufferSize; + void *extraField; + uLong extraFieldBufferSize; + char *szComment; + uLong commentBufferSize; +{ + return unzlocal_GetCurrentFileInfoInternal(file,pfile_info,NULL, + szFileName,fileNameBufferSize, + extraField,extraFieldBufferSize, + szComment,commentBufferSize); +} + +/* + Set the current file of the zipfile to the first file. + return UNZ_OK if there is no problem +*/ +extern int ZEXPORT unzGoToFirstFile (file) + unzFile file; +{ + int err=UNZ_OK; + unz_s* s; + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + s->pos_in_central_dir=s->offset_central_dir; + s->num_file=0; + err=unzlocal_GetCurrentFileInfoInternal(file,&s->cur_file_info, + &s->cur_file_info_internal, + NULL,0,NULL,0,NULL,0); + s->current_file_ok = (err == UNZ_OK); + return err; +} + +/* + Set the current file of the zipfile to the next file. + return UNZ_OK if there is no problem + return UNZ_END_OF_LIST_OF_FILE if the actual file was the latest. +*/ +extern int ZEXPORT unzGoToNextFile (file) + unzFile file; +{ + unz_s* s; + int err; + + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + if (!s->current_file_ok) + return UNZ_END_OF_LIST_OF_FILE; + if (s->gi.number_entry != 0xffff) /* 2^16 files overflow hack */ + if (s->num_file+1==s->gi.number_entry) + return UNZ_END_OF_LIST_OF_FILE; + + s->pos_in_central_dir += SIZECENTRALDIRITEM + s->cur_file_info.size_filename + + s->cur_file_info.size_file_extra + s->cur_file_info.size_file_comment ; + s->num_file++; + err = unzlocal_GetCurrentFileInfoInternal(file,&s->cur_file_info, + &s->cur_file_info_internal, + NULL,0,NULL,0,NULL,0); + s->current_file_ok = (err == UNZ_OK); + return err; +} + + +/* + Try locate the file szFileName in the zipfile. + For the iCaseSensitivity signification, see unzipStringFileNameCompare + + return value : + UNZ_OK if the file is found. It becomes the current file. + UNZ_END_OF_LIST_OF_FILE if the file is not found +*/ +extern int ZEXPORT unzLocateFile (file, szFileName, iCaseSensitivity) + unzFile file; + const char *szFileName; + int iCaseSensitivity; +{ + unz_s* s; + int err; + + /* We remember the 'current' position in the file so that we can jump + * back there if we fail. + */ + unz_file_info cur_file_infoSaved; + unz_file_info_internal cur_file_info_internalSaved; + uLong num_fileSaved; + uLong pos_in_central_dirSaved; + + + if (file==NULL) + return UNZ_PARAMERROR; + + if (strlen(szFileName)>=UNZ_MAXFILENAMEINZIP) + return UNZ_PARAMERROR; + + s=(unz_s*)file; + if (!s->current_file_ok) + return UNZ_END_OF_LIST_OF_FILE; + + /* Save the current state */ + num_fileSaved = s->num_file; + pos_in_central_dirSaved = s->pos_in_central_dir; + cur_file_infoSaved = s->cur_file_info; + cur_file_info_internalSaved = s->cur_file_info_internal; + + err = unzGoToFirstFile(file); + + while (err == UNZ_OK) + { + char szCurrentFileName[UNZ_MAXFILENAMEINZIP+1]; + err = unzGetCurrentFileInfo(file,NULL, + szCurrentFileName,sizeof(szCurrentFileName)-1, + NULL,0,NULL,0); + if (err == UNZ_OK) + { + if (unzStringFileNameCompare(szCurrentFileName, + szFileName,iCaseSensitivity)==0) + return UNZ_OK; + err = unzGoToNextFile(file); + } + } + + /* We failed, so restore the state of the 'current file' to where we + * were. + */ + s->num_file = num_fileSaved ; + s->pos_in_central_dir = pos_in_central_dirSaved ; + s->cur_file_info = cur_file_infoSaved; + s->cur_file_info_internal = cur_file_info_internalSaved; + return err; +} + + +/* +/////////////////////////////////////////// +// Contributed by Ryan Haksi (mailto://cryogen@infoserve.net) +// I need random access +// +// Further optimization could be realized by adding an ability +// to cache the directory in memory. The goal being a single +// comprehensive file read to put the file I need in a memory. +*/ + +/* +typedef struct unz_file_pos_s +{ + uLong pos_in_zip_directory; // offset in file + uLong num_of_file; // # of file +} unz_file_pos; +*/ + +extern int ZEXPORT unzGetFilePos(file, file_pos) + unzFile file; + unz_file_pos* file_pos; +{ + unz_s* s; + + if (file==NULL || file_pos==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + if (!s->current_file_ok) + return UNZ_END_OF_LIST_OF_FILE; + + file_pos->pos_in_zip_directory = s->pos_in_central_dir; + file_pos->num_of_file = s->num_file; + + return UNZ_OK; +} + +extern int ZEXPORT unzGoToFilePos(file, file_pos) + unzFile file; + unz_file_pos* file_pos; +{ + unz_s* s; + int err; + + if (file==NULL || file_pos==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + + /* jump to the right spot */ + s->pos_in_central_dir = file_pos->pos_in_zip_directory; + s->num_file = file_pos->num_of_file; + + /* set the current file */ + err = unzlocal_GetCurrentFileInfoInternal(file,&s->cur_file_info, + &s->cur_file_info_internal, + NULL,0,NULL,0,NULL,0); + /* return results */ + s->current_file_ok = (err == UNZ_OK); + return err; +} + +/* +// Unzip Helper Functions - should be here? +/////////////////////////////////////////// +*/ + +/* + Read the local header of the current zipfile + Check the coherency of the local header and info in the end of central + directory about this file + store in *piSizeVar the size of extra info in local header + (filename and size of extra field data) +*/ +local int unzlocal_CheckCurrentFileCoherencyHeader (s,piSizeVar, + poffset_local_extrafield, + psize_local_extrafield) + unz_s* s; + uInt* piSizeVar; + uLong *poffset_local_extrafield; + uInt *psize_local_extrafield; +{ + uLong uMagic,uData,uFlags; + uLong size_filename; + uLong size_extra_field; + int err=UNZ_OK; + + *piSizeVar = 0; + *poffset_local_extrafield = 0; + *psize_local_extrafield = 0; + + if (ZSEEK(s->z_filefunc, s->filestream,s->cur_file_info_internal.offset_curfile + + s->byte_before_the_zipfile,ZLIB_FILEFUNC_SEEK_SET)!=0) + return UNZ_ERRNO; + + + if (err==UNZ_OK) + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&uMagic) != UNZ_OK) + err=UNZ_ERRNO; + else if (uMagic!=0x04034b50) + err=UNZ_BADZIPFILE; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&uData) != UNZ_OK) + err=UNZ_ERRNO; +/* + else if ((err==UNZ_OK) && (uData!=s->cur_file_info.wVersion)) + err=UNZ_BADZIPFILE; +*/ + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&uFlags) != UNZ_OK) + err=UNZ_ERRNO; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&uData) != UNZ_OK) + err=UNZ_ERRNO; + else if ((err==UNZ_OK) && (uData!=s->cur_file_info.compression_method)) + err=UNZ_BADZIPFILE; + + if ((err==UNZ_OK) && (s->cur_file_info.compression_method!=0) && + (s->cur_file_info.compression_method!=Z_DEFLATED)) + err=UNZ_BADZIPFILE; + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&uData) != UNZ_OK) /* date/time */ + err=UNZ_ERRNO; + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&uData) != UNZ_OK) /* crc */ + err=UNZ_ERRNO; + else if ((err==UNZ_OK) && (uData!=s->cur_file_info.crc) && + ((uFlags & 8)==0)) + err=UNZ_BADZIPFILE; + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&uData) != UNZ_OK) /* size compr */ + err=UNZ_ERRNO; + else if ((err==UNZ_OK) && (uData!=s->cur_file_info.compressed_size) && + ((uFlags & 8)==0)) + err=UNZ_BADZIPFILE; + + if (unzlocal_getLong(&s->z_filefunc, s->filestream,&uData) != UNZ_OK) /* size uncompr */ + err=UNZ_ERRNO; + else if ((err==UNZ_OK) && (uData!=s->cur_file_info.uncompressed_size) && + ((uFlags & 8)==0)) + err=UNZ_BADZIPFILE; + + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&size_filename) != UNZ_OK) + err=UNZ_ERRNO; + else if ((err==UNZ_OK) && (size_filename!=s->cur_file_info.size_filename)) + err=UNZ_BADZIPFILE; + + *piSizeVar += (uInt)size_filename; + + if (unzlocal_getShort(&s->z_filefunc, s->filestream,&size_extra_field) != UNZ_OK) + err=UNZ_ERRNO; + *poffset_local_extrafield= s->cur_file_info_internal.offset_curfile + + SIZEZIPLOCALHEADER + size_filename; + *psize_local_extrafield = (uInt)size_extra_field; + + *piSizeVar += (uInt)size_extra_field; + + return err; +} + +/* + Open for reading data the current file in the zipfile. + If there is no error and the file is opened, the return value is UNZ_OK. +*/ +extern int ZEXPORT unzOpenCurrentFile3 (file, method, level, raw, password) + unzFile file; + int* method; + int* level; + int raw; + const char* password; +{ + int err=UNZ_OK; + uInt iSizeVar; + unz_s* s; + file_in_zip_read_info_s* pfile_in_zip_read_info; + uLong offset_local_extrafield; /* offset of the local extra field */ + uInt size_local_extrafield; /* size of the local extra field */ +# ifndef NOUNCRYPT + char source[12]; +# else + if (password != NULL) + return UNZ_PARAMERROR; +# endif + + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + if (!s->current_file_ok) + return UNZ_PARAMERROR; + + if (s->pfile_in_zip_read != NULL) + unzCloseCurrentFile(file); + + if (unzlocal_CheckCurrentFileCoherencyHeader(s,&iSizeVar, + &offset_local_extrafield,&size_local_extrafield)!=UNZ_OK) + return UNZ_BADZIPFILE; + + pfile_in_zip_read_info = (file_in_zip_read_info_s*) + ALLOC(sizeof(file_in_zip_read_info_s)); + if (pfile_in_zip_read_info==NULL) + return UNZ_INTERNALERROR; + + pfile_in_zip_read_info->read_buffer=(char*)ALLOC(UNZ_BUFSIZE); + pfile_in_zip_read_info->offset_local_extrafield = offset_local_extrafield; + pfile_in_zip_read_info->size_local_extrafield = size_local_extrafield; + pfile_in_zip_read_info->pos_local_extrafield=0; + pfile_in_zip_read_info->raw=raw; + + if (pfile_in_zip_read_info->read_buffer==NULL) + { + TRYFREE(pfile_in_zip_read_info); + return UNZ_INTERNALERROR; + } + + pfile_in_zip_read_info->stream_initialised=0; + + if (method!=NULL) + *method = (int)s->cur_file_info.compression_method; + + if (level!=NULL) + { + *level = 6; + switch (s->cur_file_info.flag & 0x06) + { + case 6 : *level = 1; break; + case 4 : *level = 2; break; + case 2 : *level = 9; break; + } + } + + if ((s->cur_file_info.compression_method!=0) && + (s->cur_file_info.compression_method!=Z_DEFLATED)) + err=UNZ_BADZIPFILE; + + pfile_in_zip_read_info->crc32_wait=s->cur_file_info.crc; + pfile_in_zip_read_info->crc32=0; + pfile_in_zip_read_info->compression_method = + s->cur_file_info.compression_method; + pfile_in_zip_read_info->filestream=s->filestream; + pfile_in_zip_read_info->z_filefunc=s->z_filefunc; + pfile_in_zip_read_info->byte_before_the_zipfile=s->byte_before_the_zipfile; + + pfile_in_zip_read_info->stream.total_out = 0; + + if ((s->cur_file_info.compression_method==Z_DEFLATED) && + (!raw)) + { + pfile_in_zip_read_info->stream.zalloc = (alloc_func)0; + pfile_in_zip_read_info->stream.zfree = (free_func)0; + pfile_in_zip_read_info->stream.opaque = (voidpf)0; + pfile_in_zip_read_info->stream.next_in = (voidpf)0; + pfile_in_zip_read_info->stream.avail_in = 0; + + err=inflateInit2(&pfile_in_zip_read_info->stream, -MAX_WBITS); + if (err == Z_OK) + pfile_in_zip_read_info->stream_initialised=1; + else + { + TRYFREE(pfile_in_zip_read_info); + return err; + } + /* windowBits is passed < 0 to tell that there is no zlib header. + * Note that in this case inflate *requires* an extra "dummy" byte + * after the compressed stream in order to complete decompression and + * return Z_STREAM_END. + * In unzip, i don't wait absolutely Z_STREAM_END because I known the + * size of both compressed and uncompressed data + */ + } + pfile_in_zip_read_info->rest_read_compressed = + s->cur_file_info.compressed_size ; + pfile_in_zip_read_info->rest_read_uncompressed = + s->cur_file_info.uncompressed_size ; + + + pfile_in_zip_read_info->pos_in_zipfile = + s->cur_file_info_internal.offset_curfile + SIZEZIPLOCALHEADER + + iSizeVar; + + pfile_in_zip_read_info->stream.avail_in = (uInt)0; + + s->pfile_in_zip_read = pfile_in_zip_read_info; + +# ifndef NOUNCRYPT + if (password != NULL) + { + int i; + s->pcrc_32_tab = get_crc_table(); + init_keys(password,s->keys,s->pcrc_32_tab); + if (ZSEEK(s->z_filefunc, s->filestream, + s->pfile_in_zip_read->pos_in_zipfile + + s->pfile_in_zip_read->byte_before_the_zipfile, + SEEK_SET)!=0) + return UNZ_INTERNALERROR; + if(ZREAD(s->z_filefunc, s->filestream,source, 12)<12) + return UNZ_INTERNALERROR; + + for (i = 0; i<12; i++) + zdecode(s->keys,s->pcrc_32_tab,source[i]); + + s->pfile_in_zip_read->pos_in_zipfile+=12; + s->encrypted=1; + } +# endif + + + return UNZ_OK; +} + +extern int ZEXPORT unzOpenCurrentFile (file) + unzFile file; +{ + return unzOpenCurrentFile3(file, NULL, NULL, 0, NULL); +} + +extern int ZEXPORT unzOpenCurrentFilePassword (file, password) + unzFile file; + const char* password; +{ + return unzOpenCurrentFile3(file, NULL, NULL, 0, password); +} + +extern int ZEXPORT unzOpenCurrentFile2 (file,method,level,raw) + unzFile file; + int* method; + int* level; + int raw; +{ + return unzOpenCurrentFile3(file, method, level, raw, NULL); +} + +/* + Read bytes from the current file. + buf contain buffer where data must be copied + len the size of buf. + + return the number of byte copied if somes bytes are copied + return 0 if the end of file was reached + return <0 with error code if there is an error + (UNZ_ERRNO for IO error, or zLib error for uncompress error) +*/ +extern int ZEXPORT unzReadCurrentFile (file, buf, len) + unzFile file; + voidp buf; + unsigned len; +{ + int err=UNZ_OK; + uInt iRead = 0; + unz_s* s; + file_in_zip_read_info_s* pfile_in_zip_read_info; + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + pfile_in_zip_read_info=s->pfile_in_zip_read; + + if (pfile_in_zip_read_info==NULL) + return UNZ_PARAMERROR; + + + if ((pfile_in_zip_read_info->read_buffer == NULL)) + return UNZ_END_OF_LIST_OF_FILE; + if (len==0) + return 0; + + pfile_in_zip_read_info->stream.next_out = (Bytef*)buf; + + pfile_in_zip_read_info->stream.avail_out = (uInt)len; + + if ((len>pfile_in_zip_read_info->rest_read_uncompressed) && + (!(pfile_in_zip_read_info->raw))) + pfile_in_zip_read_info->stream.avail_out = + (uInt)pfile_in_zip_read_info->rest_read_uncompressed; + + if ((len>pfile_in_zip_read_info->rest_read_compressed+ + pfile_in_zip_read_info->stream.avail_in) && + (pfile_in_zip_read_info->raw)) + pfile_in_zip_read_info->stream.avail_out = + (uInt)pfile_in_zip_read_info->rest_read_compressed+ + pfile_in_zip_read_info->stream.avail_in; + + while (pfile_in_zip_read_info->stream.avail_out>0) + { + if ((pfile_in_zip_read_info->stream.avail_in==0) && + (pfile_in_zip_read_info->rest_read_compressed>0)) + { + uInt uReadThis = UNZ_BUFSIZE; + if (pfile_in_zip_read_info->rest_read_compressedrest_read_compressed; + if (uReadThis == 0) + return UNZ_EOF; + if (ZSEEK(pfile_in_zip_read_info->z_filefunc, + pfile_in_zip_read_info->filestream, + pfile_in_zip_read_info->pos_in_zipfile + + pfile_in_zip_read_info->byte_before_the_zipfile, + ZLIB_FILEFUNC_SEEK_SET)!=0) + return UNZ_ERRNO; + if (ZREAD(pfile_in_zip_read_info->z_filefunc, + pfile_in_zip_read_info->filestream, + pfile_in_zip_read_info->read_buffer, + uReadThis)!=uReadThis) + return UNZ_ERRNO; + + +# ifndef NOUNCRYPT + if(s->encrypted) + { + uInt i; + for(i=0;iread_buffer[i] = + zdecode(s->keys,s->pcrc_32_tab, + pfile_in_zip_read_info->read_buffer[i]); + } +# endif + + + pfile_in_zip_read_info->pos_in_zipfile += uReadThis; + + pfile_in_zip_read_info->rest_read_compressed-=uReadThis; + + pfile_in_zip_read_info->stream.next_in = + (Bytef*)pfile_in_zip_read_info->read_buffer; + pfile_in_zip_read_info->stream.avail_in = (uInt)uReadThis; + } + + if ((pfile_in_zip_read_info->compression_method==0) || (pfile_in_zip_read_info->raw)) + { + uInt uDoCopy,i ; + + if ((pfile_in_zip_read_info->stream.avail_in == 0) && + (pfile_in_zip_read_info->rest_read_compressed == 0)) + return (iRead==0) ? UNZ_EOF : iRead; + + if (pfile_in_zip_read_info->stream.avail_out < + pfile_in_zip_read_info->stream.avail_in) + uDoCopy = pfile_in_zip_read_info->stream.avail_out ; + else + uDoCopy = pfile_in_zip_read_info->stream.avail_in ; + + for (i=0;istream.next_out+i) = + *(pfile_in_zip_read_info->stream.next_in+i); + + pfile_in_zip_read_info->crc32 = crc32(pfile_in_zip_read_info->crc32, + pfile_in_zip_read_info->stream.next_out, + uDoCopy); + pfile_in_zip_read_info->rest_read_uncompressed-=uDoCopy; + pfile_in_zip_read_info->stream.avail_in -= uDoCopy; + pfile_in_zip_read_info->stream.avail_out -= uDoCopy; + pfile_in_zip_read_info->stream.next_out += uDoCopy; + pfile_in_zip_read_info->stream.next_in += uDoCopy; + pfile_in_zip_read_info->stream.total_out += uDoCopy; + iRead += uDoCopy; + } + else + { + uLong uTotalOutBefore,uTotalOutAfter; + const Bytef *bufBefore; + uLong uOutThis; + int flush=Z_SYNC_FLUSH; + + uTotalOutBefore = pfile_in_zip_read_info->stream.total_out; + bufBefore = pfile_in_zip_read_info->stream.next_out; + + /* + if ((pfile_in_zip_read_info->rest_read_uncompressed == + pfile_in_zip_read_info->stream.avail_out) && + (pfile_in_zip_read_info->rest_read_compressed == 0)) + flush = Z_FINISH; + */ + err=inflate(&pfile_in_zip_read_info->stream,flush); + + if ((err>=0) && (pfile_in_zip_read_info->stream.msg!=NULL)) + err = Z_DATA_ERROR; + + uTotalOutAfter = pfile_in_zip_read_info->stream.total_out; + uOutThis = uTotalOutAfter-uTotalOutBefore; + + pfile_in_zip_read_info->crc32 = + crc32(pfile_in_zip_read_info->crc32,bufBefore, + (uInt)(uOutThis)); + + pfile_in_zip_read_info->rest_read_uncompressed -= + uOutThis; + + iRead += (uInt)(uTotalOutAfter - uTotalOutBefore); + + if (err==Z_STREAM_END) + return (iRead==0) ? UNZ_EOF : iRead; + if (err!=Z_OK) + break; + } + } + + if (err==Z_OK) + return iRead; + return err; +} + + +/* + Give the current position in uncompressed data +*/ +extern z_off_t ZEXPORT unztell (file) + unzFile file; +{ + unz_s* s; + file_in_zip_read_info_s* pfile_in_zip_read_info; + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + pfile_in_zip_read_info=s->pfile_in_zip_read; + + if (pfile_in_zip_read_info==NULL) + return UNZ_PARAMERROR; + + return (z_off_t)pfile_in_zip_read_info->stream.total_out; +} + + +/* + return 1 if the end of file was reached, 0 elsewhere +*/ +extern int ZEXPORT unzeof (file) + unzFile file; +{ + unz_s* s; + file_in_zip_read_info_s* pfile_in_zip_read_info; + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + pfile_in_zip_read_info=s->pfile_in_zip_read; + + if (pfile_in_zip_read_info==NULL) + return UNZ_PARAMERROR; + + if (pfile_in_zip_read_info->rest_read_uncompressed == 0) + return 1; + else + return 0; +} + + + +/* + Read extra field from the current file (opened by unzOpenCurrentFile) + This is the local-header version of the extra field (sometimes, there is + more info in the local-header version than in the central-header) + + if buf==NULL, it return the size of the local extra field that can be read + + if buf!=NULL, len is the size of the buffer, the extra header is copied in + buf. + the return value is the number of bytes copied in buf, or (if <0) + the error code +*/ +extern int ZEXPORT unzGetLocalExtrafield (file,buf,len) + unzFile file; + voidp buf; + unsigned len; +{ + unz_s* s; + file_in_zip_read_info_s* pfile_in_zip_read_info; + uInt read_now; + uLong size_to_read; + + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + pfile_in_zip_read_info=s->pfile_in_zip_read; + + if (pfile_in_zip_read_info==NULL) + return UNZ_PARAMERROR; + + size_to_read = (pfile_in_zip_read_info->size_local_extrafield - + pfile_in_zip_read_info->pos_local_extrafield); + + if (buf==NULL) + return (int)size_to_read; + + if (len>size_to_read) + read_now = (uInt)size_to_read; + else + read_now = (uInt)len ; + + if (read_now==0) + return 0; + + if (ZSEEK(pfile_in_zip_read_info->z_filefunc, + pfile_in_zip_read_info->filestream, + pfile_in_zip_read_info->offset_local_extrafield + + pfile_in_zip_read_info->pos_local_extrafield, + ZLIB_FILEFUNC_SEEK_SET)!=0) + return UNZ_ERRNO; + + if (ZREAD(pfile_in_zip_read_info->z_filefunc, + pfile_in_zip_read_info->filestream, + buf,read_now)!=read_now) + return UNZ_ERRNO; + + return (int)read_now; +} + +/* + Close the file in zip opened with unzipOpenCurrentFile + Return UNZ_CRCERROR if all the file was read but the CRC is not good +*/ +extern int ZEXPORT unzCloseCurrentFile (file) + unzFile file; +{ + int err=UNZ_OK; + + unz_s* s; + file_in_zip_read_info_s* pfile_in_zip_read_info; + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + pfile_in_zip_read_info=s->pfile_in_zip_read; + + if (pfile_in_zip_read_info==NULL) + return UNZ_PARAMERROR; + + + if ((pfile_in_zip_read_info->rest_read_uncompressed == 0) && + (!pfile_in_zip_read_info->raw)) + { + if (pfile_in_zip_read_info->crc32 != pfile_in_zip_read_info->crc32_wait) + err=UNZ_CRCERROR; + } + + + TRYFREE(pfile_in_zip_read_info->read_buffer); + pfile_in_zip_read_info->read_buffer = NULL; + if (pfile_in_zip_read_info->stream_initialised) + inflateEnd(&pfile_in_zip_read_info->stream); + + pfile_in_zip_read_info->stream_initialised = 0; + TRYFREE(pfile_in_zip_read_info); + + s->pfile_in_zip_read=NULL; + + return err; +} + + +/* + Get the global comment string of the ZipFile, in the szComment buffer. + uSizeBuf is the size of the szComment buffer. + return the number of byte copied or an error code <0 +*/ +extern int ZEXPORT unzGetGlobalComment (file, szComment, uSizeBuf) + unzFile file; + char *szComment; + uLong uSizeBuf; +{ + int err=UNZ_OK; + unz_s* s; + uLong uReadThis ; + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + + uReadThis = uSizeBuf; + if (uReadThis>s->gi.size_comment) + uReadThis = s->gi.size_comment; + + if (ZSEEK(s->z_filefunc,s->filestream,s->central_pos+22,ZLIB_FILEFUNC_SEEK_SET)!=0) + return UNZ_ERRNO; + + if (uReadThis>0) + { + *szComment='\0'; + if (ZREAD(s->z_filefunc,s->filestream,szComment,uReadThis)!=uReadThis) + return UNZ_ERRNO; + } + + if ((szComment != NULL) && (uSizeBuf > s->gi.size_comment)) + *(szComment+s->gi.size_comment)='\0'; + return (int)uReadThis; +} + +/* Additions by RX '2004 */ +extern uLong ZEXPORT unzGetOffset (file) + unzFile file; +{ + unz_s* s; + + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + if (!s->current_file_ok) + return 0; + if (s->gi.number_entry != 0 && s->gi.number_entry != 0xffff) + if (s->num_file==s->gi.number_entry) + return 0; + return s->pos_in_central_dir; +} + +extern int ZEXPORT unzSetOffset (file, pos) + unzFile file; + uLong pos; +{ + unz_s* s; + int err; + + if (file==NULL) + return UNZ_PARAMERROR; + s=(unz_s*)file; + + s->pos_in_central_dir = pos; + s->num_file = s->gi.number_entry; /* hack */ + err = unzlocal_GetCurrentFileInfoInternal(file,&s->cur_file_info, + &s->cur_file_info_internal, + NULL,0,NULL,0,NULL,0); + s->current_file_ok = (err == UNZ_OK); + return err; +} diff --git a/src/unzip.h b/src/unzip.h new file mode 100644 index 0000000..14d7a6f --- /dev/null +++ b/src/unzip.h @@ -0,0 +1,356 @@ +/* unzip.h -- IO for uncompress .zip files using zlib + Version 1.01e, February 12th, 2005 + + Copyright (C) 1998-2005 Gilles Vollant + + This unzip package allow extract file from .ZIP file, compatible with PKZip 2.04g + WinZip, InfoZip tools and compatible. + + Multi volume ZipFile (span) are not supported. + Encryption compatible with pkzip 2.04g only supported + Old compressions used by old PKZip 1.x are not supported + + + I WAIT FEEDBACK at mail info@winimage.com + Visit also http://www.winimage.com/zLibDll/unzip.htm for evolution + + Condition of use and distribution are the same than zlib : + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages + arising from the use of this software. + + Permission is granted to anyone to use this software for any purpose, + including commercial applications, and to alter it and redistribute it + freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + 3. This notice may not be removed or altered from any source distribution. + + +*/ + +/* for more info about .ZIP format, see + http://www.info-zip.org/pub/infozip/doc/appnote-981119-iz.zip + http://www.info-zip.org/pub/infozip/doc/ + PkWare has also a specification at : + ftp://ftp.pkware.com/probdesc.zip +*/ + +#ifndef _unz_H +#define _unz_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define NOUNCRYPT + +#ifndef _ZLIB_H +#include "zlib.h" +#endif + +#ifndef _ZLIBIOAPI_H +#include "ioapi.h" +#endif + +#if defined(STRICTUNZIP) || defined(STRICTZIPUNZIP) +/* like the STRICT of WIN32, we define a pointer that cannot be converted + from (void*) without cast */ +typedef struct TagunzFile__ { int unused; } unzFile__; +typedef unzFile__ *unzFile; +#else +typedef voidp unzFile; +#endif + + +#define UNZ_OK (0) +#define UNZ_END_OF_LIST_OF_FILE (-100) +#define UNZ_ERRNO (Z_ERRNO) +#define UNZ_EOF (0) +#define UNZ_PARAMERROR (-102) +#define UNZ_BADZIPFILE (-103) +#define UNZ_INTERNALERROR (-104) +#define UNZ_CRCERROR (-105) + +/* tm_unz contain date/time info */ +typedef struct tm_unz_s +{ + uInt tm_sec; /* seconds after the minute - [0,59] */ + uInt tm_min; /* minutes after the hour - [0,59] */ + uInt tm_hour; /* hours since midnight - [0,23] */ + uInt tm_mday; /* day of the month - [1,31] */ + uInt tm_mon; /* months since January - [0,11] */ + uInt tm_year; /* years - [1980..2044] */ +} tm_unz; + +/* unz_global_info structure contain global data about the ZIPfile + These data comes from the end of central dir */ +typedef struct unz_global_info_s +{ + uLong number_entry; /* total number of entries in + the central dir on this disk */ + uLong size_comment; /* size of the global comment of the zipfile */ +} unz_global_info; + + +/* unz_file_info contain information about a file in the zipfile */ +typedef struct unz_file_info_s +{ + uLong version; /* version made by 2 bytes */ + uLong version_needed; /* version needed to extract 2 bytes */ + uLong flag; /* general purpose bit flag 2 bytes */ + uLong compression_method; /* compression method 2 bytes */ + uLong dosDate; /* last mod file date in Dos fmt 4 bytes */ + uLong crc; /* crc-32 4 bytes */ + uLong compressed_size; /* compressed size 4 bytes */ + uLong uncompressed_size; /* uncompressed size 4 bytes */ + uLong size_filename; /* filename length 2 bytes */ + uLong size_file_extra; /* extra field length 2 bytes */ + uLong size_file_comment; /* file comment length 2 bytes */ + + uLong disk_num_start; /* disk number start 2 bytes */ + uLong internal_fa; /* internal file attributes 2 bytes */ + uLong external_fa; /* external file attributes 4 bytes */ + + tm_unz tmu_date; +} unz_file_info; + +extern int ZEXPORT unzStringFileNameCompare OF ((const char* fileName1, + const char* fileName2, + int iCaseSensitivity)); +/* + Compare two filename (fileName1,fileName2). + If iCaseSenisivity = 1, comparision is case sensitivity (like strcmp) + If iCaseSenisivity = 2, comparision is not case sensitivity (like strcmpi + or strcasecmp) + If iCaseSenisivity = 0, case sensitivity is defaut of your operating system + (like 1 on Unix, 2 on Windows) +*/ + + +extern unzFile ZEXPORT unzOpen OF((const char *path)); +/* + Open a Zip file. path contain the full pathname (by example, + on a Windows XP computer "c:\\zlib\\zlib113.zip" or on an Unix computer + "zlib/zlib113.zip". + If the zipfile cannot be opened (file don't exist or in not valid), the + return value is NULL. + Else, the return value is a unzFile Handle, usable with other function + of this unzip package. +*/ + +extern unzFile ZEXPORT unzOpen2 OF((const char *path, + zlib_filefunc_def* pzlib_filefunc_def)); +/* + Open a Zip file, like unzOpen, but provide a set of file low level API + for read/write the zip file (see ioapi.h) +*/ + +extern int ZEXPORT unzClose OF((unzFile file)); +/* + Close a ZipFile opened with unzipOpen. + If there is files inside the .Zip opened with unzOpenCurrentFile (see later), + these files MUST be closed with unzipCloseCurrentFile before call unzipClose. + return UNZ_OK if there is no problem. */ + +extern int ZEXPORT unzGetGlobalInfo OF((unzFile file, + unz_global_info *pglobal_info)); +/* + Write info about the ZipFile in the *pglobal_info structure. + No preparation of the structure is needed + return UNZ_OK if there is no problem. */ + + +extern int ZEXPORT unzGetGlobalComment OF((unzFile file, + char *szComment, + uLong uSizeBuf)); +/* + Get the global comment string of the ZipFile, in the szComment buffer. + uSizeBuf is the size of the szComment buffer. + return the number of byte copied or an error code <0 +*/ + + +/***************************************************************************/ +/* Unzip package allow you browse the directory of the zipfile */ + +extern int ZEXPORT unzGoToFirstFile OF((unzFile file)); +/* + Set the current file of the zipfile to the first file. + return UNZ_OK if there is no problem +*/ + +extern int ZEXPORT unzGoToNextFile OF((unzFile file)); +/* + Set the current file of the zipfile to the next file. + return UNZ_OK if there is no problem + return UNZ_END_OF_LIST_OF_FILE if the actual file was the latest. +*/ + +extern int ZEXPORT unzLocateFile OF((unzFile file, + const char *szFileName, + int iCaseSensitivity)); +/* + Try locate the file szFileName in the zipfile. + For the iCaseSensitivity signification, see unzStringFileNameCompare + + return value : + UNZ_OK if the file is found. It becomes the current file. + UNZ_END_OF_LIST_OF_FILE if the file is not found +*/ + + +/* ****************************************** */ +/* Ryan supplied functions */ +/* unz_file_info contain information about a file in the zipfile */ +typedef struct unz_file_pos_s +{ + uLong pos_in_zip_directory; /* offset in zip file directory */ + uLong num_of_file; /* # of file */ +} unz_file_pos; + +extern int ZEXPORT unzGetFilePos( + unzFile file, + unz_file_pos* file_pos); + +extern int ZEXPORT unzGoToFilePos( + unzFile file, + unz_file_pos* file_pos); + +/* ****************************************** */ + +extern int ZEXPORT unzGetCurrentFileInfo OF((unzFile file, + unz_file_info *pfile_info, + char *szFileName, + uLong fileNameBufferSize, + void *extraField, + uLong extraFieldBufferSize, + char *szComment, + uLong commentBufferSize)); +/* + Get Info about the current file + if pfile_info!=NULL, the *pfile_info structure will contain somes info about + the current file + if szFileName!=NULL, the filemane string will be copied in szFileName + (fileNameBufferSize is the size of the buffer) + if extraField!=NULL, the extra field information will be copied in extraField + (extraFieldBufferSize is the size of the buffer). + This is the Central-header version of the extra field + if szComment!=NULL, the comment string of the file will be copied in szComment + (commentBufferSize is the size of the buffer) +*/ + +/***************************************************************************/ +/* for reading the content of the current zipfile, you can open it, read data + from it, and close it (you can close it before reading all the file) + */ + +extern int ZEXPORT unzOpenCurrentFile OF((unzFile file)); +/* + Open for reading data the current file in the zipfile. + If there is no error, the return value is UNZ_OK. +*/ + +extern int ZEXPORT unzOpenCurrentFilePassword OF((unzFile file, + const char* password)); +/* + Open for reading data the current file in the zipfile. + password is a crypting password + If there is no error, the return value is UNZ_OK. +*/ + +extern int ZEXPORT unzOpenCurrentFile2 OF((unzFile file, + int* method, + int* level, + int raw)); +/* + Same than unzOpenCurrentFile, but open for read raw the file (not uncompress) + if raw==1 + *method will receive method of compression, *level will receive level of + compression + note : you can set level parameter as NULL (if you did not want known level, + but you CANNOT set method parameter as NULL +*/ + +extern int ZEXPORT unzOpenCurrentFile3 OF((unzFile file, + int* method, + int* level, + int raw, + const char* password)); +/* + Same than unzOpenCurrentFile, but open for read raw the file (not uncompress) + if raw==1 + *method will receive method of compression, *level will receive level of + compression + note : you can set level parameter as NULL (if you did not want known level, + but you CANNOT set method parameter as NULL +*/ + + +extern int ZEXPORT unzCloseCurrentFile OF((unzFile file)); +/* + Close the file in zip opened with unzOpenCurrentFile + Return UNZ_CRCERROR if all the file was read but the CRC is not good +*/ + +extern int ZEXPORT unzReadCurrentFile OF((unzFile file, + voidp buf, + unsigned len)); +/* + Read bytes from the current file (opened by unzOpenCurrentFile) + buf contain buffer where data must be copied + len the size of buf. + + return the number of byte copied if somes bytes are copied + return 0 if the end of file was reached + return <0 with error code if there is an error + (UNZ_ERRNO for IO error, or zLib error for uncompress error) +*/ + +extern z_off_t ZEXPORT unztell OF((unzFile file)); +/* + Give the current position in uncompressed data +*/ + +extern int ZEXPORT unzeof OF((unzFile file)); +/* + return 1 if the end of file was reached, 0 elsewhere +*/ + +extern int ZEXPORT unzGetLocalExtrafield OF((unzFile file, + voidp buf, + unsigned len)); +/* + Read extra field from the current file (opened by unzOpenCurrentFile) + This is the local-header version of the extra field (sometimes, there is + more info in the local-header version than in the central-header) + + if buf==NULL, it return the size of the local extra field + + if buf!=NULL, len is the size of the buffer, the extra header is copied in + buf. + the return value is the number of bytes copied in buf, or (if <0) + the error code +*/ + +/***************************************************************************/ + +/* Get the current file offset */ +extern uLong ZEXPORT unzGetOffset (unzFile file); + +/* Set the current file offset */ +extern int ZEXPORT unzSetOffset (unzFile file, uLong pos); + + + +#ifdef __cplusplus +} +#endif + +#endif /* _unz_H */ diff --git a/src/usbjoy.c b/src/usbjoy.c new file mode 100644 index 0000000..81d1be4 --- /dev/null +++ b/src/usbjoy.c @@ -0,0 +1,297 @@ +/* Title: USB Joystick library + Version 0.2 + Written by Puck2099 (puck2099@gmail.com), (c) 2006. + + + If you use this library or a part of it, please, let it know. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include +#include /* For the definition of NULL */ +#include // For Device open +#include +#include +#include +#include // For Device read + +#include +#include /* For the definition of PATH_MAX */ +#include + +#include "usbjoy.h" + + +/* + Function: joy_open + + Opens a USB joystick and fills its information. + + Parameters: + + joynumber - Joystick's identifier (0 reserved for GP2X's builtin Joystick). + + Returns: + + Filled usbjoy structure. + +*/ +struct usbjoy * joy_open (int joynumber) { + int fd, i; + char path [128]; + struct usbjoy * joy = NULL; + + system ("insmod joydev"); // Loads joydev module + + if (joynumber == 0) { + } + else if (joynumber > 0) { + sprintf (path, "/dev/input/js%d", joynumber-1); + fd = open(path, O_RDONLY, 0); + if (fd > 0) { + joy = (struct usbjoy *) malloc(sizeof(struct usbjoy)); + + // Joystick's file descriptor + joy->fd = fd; + + // Set the joystick to non-blocking read mode + fcntl(joy->fd, F_SETFL, O_NONBLOCK); + + // Joystick's name + ioctl(joy->fd, JSIOCGNAME(128*sizeof(char)), joy->name); + + // Joystick's device + sprintf (joy->device, path); + + // Joystick's buttons + ioctl(joy->fd, JSIOCGBUTTONS, &joy->numbuttons); + + // Joystick's axes + ioctl(joy->fd, JSIOCGAXES, &joy->numaxes); + + // Clean buttons and axes + for (i=0; i<32; i++) joy->statebuttons[i] = 0; + for (i=0; i<4; i++) joy->stateaxes[i] = 0; + } + else { + printf ("ERROR: No Joystick found\n"); + } + } + return joy; +} + +/* + Function: joy_name + + Returns Joystick's name. + + Parameters: + + joy - Selected joystick. + + Returns: + + Joystick's name or NULL if struct is empty. +*/ +char * joy_name (struct usbjoy * joy) { + if (joy != NULL) return joy->name; + else return NULL; +} + + +/* + Function: joy_device + + Returns Joystick's device. + + Parameters: + + joy - Selected joystick. + + Returns: + + Joystick's device or NULL if struct is empty. +*/ +char * joy_device (struct usbjoy * joy) { + if (joy != NULL) return joy->device; + else return NULL; +} + + +/* + Function: joy_buttons + + Returns Joystick's buttons number. + + Parameters: + + joy - Selected joystick. + + Returns: + + Joystick's buttons or 0 if struct is empty. +*/ +int joy_buttons (struct usbjoy * joy) { + if (joy != NULL) return joy->numbuttons; + else return 0; +} + + +/* + Function: joy_axes + + Returns Joystick's axes number. + + Parameters: + + joy - Selected joystick. + + Returns: + + Joystick's axes or 0 if struct is empty. +*/ +int joy_axes (struct usbjoy * joy) { + if (joy != NULL) return joy->numaxes; + else return 0; +} + + +/* + Function: joy_update + + Updates Joystick's internal information ( and fields). + + Parameters: + + joy - Selected joystick. + + Returns: + + 0 - No events registered (no need to update). + 1 - Events registered (a button or axe has been pushed). + -1 - Error: struct is empty. +*/ +int joy_update (struct usbjoy * joy) { + struct js_event events[0xff]; + int i, len; + int event = 0; + if (joy != NULL) { + if ((len=read(joy->fd, events, (sizeof events))) >0) { + len /= sizeof(events[0]); + for ( i=0; istateaxes[JOYLEFT] = joy->stateaxes[JOYRIGHT] = 0; + if (events[i].value < 0) joy->stateaxes[JOYLEFT] = 1; + else if (events[i].value > 0) joy->stateaxes[JOYRIGHT] = 1; + } + else if (events[i].number == 1) { + joy->stateaxes[JOYUP] = joy->stateaxes[JOYDOWN] = 0; + if (events[i].value < 0) joy->stateaxes[JOYUP] = 1; + else if (events[i].value > 0) joy->stateaxes[JOYDOWN] = 1; + } + event = 1; + break; + case JS_EVENT_BUTTON: + joy->statebuttons[events[i].number] = events[i].value; + event = 1; + break; + default: + break; + } + } + } + } + else { + event = -1; + } + return event; +} + + +/* + Function: joy_getbutton + + Returns Joystick's button information. + + Parameters: + + button - Button which value you want to know (from 0 to 31). + joy - Selected joystick. + + Returns: + + 0 - Button NOT pushed. + 1 - Button pushed. + -1 - Error: struct is empty. +*/ +int joy_getbutton (int button, struct usbjoy * joy) { + if (joy != NULL) { + if (button < joy_buttons(joy)) return joy->statebuttons[button]; + else return 0; + } + else return -1; +} + + +/* + Function: joy_getaxe + + Returns Joystick's axes information. + + Parameters: + + axe - Axe which value you want to know (see ). + joy - Selected joystick. + + Returns: + + 0 - Direction NOT pushed. + 1 - Direction pushed. + -1 - Error: struct is empty. +*/ +int joy_getaxe (int axe, struct usbjoy * joy) { + if (joy != NULL) { + if (axe < 4) return joy->stateaxes[axe]; + else return 0; + } + else return -1; +} + + +/* + Function: joy_close + + Closes selected joystick's file descriptor and detroys it's fields. + + Parameters: + + joy - Selected joystick. + + Returns: + + 0 - Joystick successfully closed. + -1 - Error: struct is empty. +*/ +int joy_close (struct usbjoy * joy) { + if (joy != NULL) { + close (joy->fd); + free (joy); + return 0; + } + else return -1; +} diff --git a/src/usbjoy.h b/src/usbjoy.h new file mode 100644 index 0000000..c324744 --- /dev/null +++ b/src/usbjoy.h @@ -0,0 +1,221 @@ +/* Title: USB Joystick library + Version 0.2 + Written by Puck2099 (puck2099@gmail.com), (c) 2006. + + + If you use this library or a part of it, please, let it know. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef USBJOY_H +#define USBJOY_H + +/* + Enumeration: Axes values + This enumeration contains shortcuts to the values used on axes. + + Constants: + JOYUP - Joystick Up + JOYDOWN - Joystick Down + JOYLEFT - Joystick Left + JOYRIGHT - Joystick Right + + See also: + +*/ +#define JOYUP (0) +#define JOYDOWN (1) +#define JOYLEFT (2) +#define JOYRIGHT (3) + + +/* + Struct: usbjoy + + Contains all Joystick needed information. + + Fields: + fd - File descriptor used. + name - Joystick's name. + device - /dev/input/jsX device. + numbuttons - Joystick's buttons. + numaxes - Joystick's axes. + numhats - Joystick's hats. + statebuttons - Current state of each button. + stateaxes - Current state of each direction. +*/ +struct usbjoy { + int fd; + char name [128]; + char device [128]; + int numbuttons; + int numaxes; + int numhats; + int statebuttons[32]; + int stateaxes[4]; +}; + + +/* + Function: joy_open + + Opens a USB joystick and fills its information. + + Parameters: + + joynumber - Joystick's identifier (0 reserved for GP2X's builtin Joystick). + + Returns: + + Filled usbjoy structure. +*/ +struct usbjoy * joy_open (int joynumber); + + +/* + Function: joy_name + + Returns Joystick's name. + + Parameters: + + joy - Selected joystick. + + Returns: + + Joystick's name or NULL if struct is empty. +*/ +char * joy_name (struct usbjoy * joy); + + +/* + Function: joy_device + + Returns Joystick's device. + + Parameters: + + joy - Selected joystick. + + Returns: + + Joystick's device or NULL if struct is empty. +*/ +char * joy_device (struct usbjoy * joy); + +/* + Function: joy_buttons + + Returns Joystick's buttons number. + + Parameters: + + joy - Selected joystick. + + Returns: + + Joystick's buttons or 0 if struct is empty. +*/ +int joy_buttons (struct usbjoy * joy); + +/* + Function: joy_axes + + Returns Joystick's axes number. + + Parameters: + + joy - Selected joystick. + + Returns: + + Joystick's axes or 0 if struct is empty. +*/ +int joy_axes (struct usbjoy * joy); + + +/* + Function: joy_update + + Updates Joystick's internal information ( and fields). + + Parameters: + + joy - Selected joystick. + + Returns: + + 0 - No events registered (no need to update). + 1 - Events registered (a button or axe has been pushed). + -1 - Error: struct is empty. +*/ +int joy_update (struct usbjoy * joy); + + +/* + Function: joy_getbutton + + Returns Joystick's button information. + + Parameters: + + button - Button which value you want to know (from 0 to 31). + joy - Selected joystick. + + Returns: + + 0 - Button NOT pushed. + 1 - Button pushed. + -1 - Error: struct is empty. +*/ +int joy_getbutton (int button, struct usbjoy * joy); + + +/* + Function: joy_getaxe + + Returns Joystick's axes information. + + Parameters: + + axe - Axe which value you want to know (see ). + joy - Selected joystick. + + Returns: + + 0 - Direction NOT pushed. + 1 - Direction pushed. + -1 - Error: struct is empty. +*/ +int joy_getaxe (int axe, struct usbjoy * joy); + +/* + Function: joy_close + + Closes selected joystick's file descriptor and detroys it's fields. + + Parameters: + + joy - Selected joystick. + + Returns: + + 0 - Joystick successfully closed. + -1 - Error: struct is empty. +*/ +int joy_close (struct usbjoy * joy); + +#endif // USBJOY_H diff --git a/src/warm.cpp b/src/warm.cpp new file mode 100644 index 0000000..fa38b6e --- /dev/null +++ b/src/warm.cpp @@ -0,0 +1,148 @@ +/* + * wARM - exporting ARM processor specific privileged services to userspace + * userspace part + * + * Copyright (c) Gražvydas "notaz" Ignotas, 2009 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the organization nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WARM_CODE +#include "warm.h" +#include "sys_cacheflush.h" + +static int warm_fd = -1; + +int warm_init(void) +{ + struct utsname unm; + char buff[128]; + + warm_fd = open("/proc/warm", O_RDWR); + if (warm_fd >= 0) + return 0; + + memset(&unm, 0, sizeof(unm)); + uname(&unm); + snprintf(buff, sizeof(buff), "/sbin/insmod warm_%s.ko", unm.release); + + /* try to insmod */ + system(buff); + warm_fd = open("/proc/warm", O_RDWR); + if (warm_fd >= 0) + return 0; + + fprintf(stderr, "wARM: can't init, acting as sys_cacheflush wrapper\n"); + return -1; +} + +void warm_finish(void) +{ + if (warm_fd >= 0) + close(warm_fd); + system("rmmod warm"); +} + +/* +int warm_cache_op_range(int op, void *addr, unsigned long size) +{ + struct warm_cache_op wop; + int ret; + + if (warm_fd < 0) { + sys_cacheflush(addr, (char *)addr + size); + return -1; + } + + wop.ops = op; + wop.addr = (unsigned long)addr; + wop.size = size; + + ret = ioctl(warm_fd, WARMC_CACHE_OP, &wop); + if (ret != 0) { + perror("WARMC_CACHE_OP failed"); + return -1; + } + + return 0; +} + +int warm_cache_op_all(int op) +{ + return warm_cache_op_range(op, NULL, (size_t)-1); +} +*/ + +int warm_change_cb_range(int cb, int is_set, void *addr, unsigned long size) +{ + struct warm_change_cb ccb; + int ret; + + if (warm_fd < 0) + return -1; + + ccb.addr = (unsigned long)addr; + ccb.size = size; + ccb.cb = cb; + ccb.is_set = is_set; + + ret = ioctl(warm_fd, WARMC_CHANGE_CB, &ccb); + if (ret != 0) { + perror("WARMC_CHANGE_CB failed"); + return -1; + } + + return 0; +} + +int warm_change_cb_upper(int cb, int is_set) +{ + return warm_change_cb_range(cb, is_set, 0, 0); +} + +unsigned long warm_virt2phys(const void *ptr) +{ + unsigned long ptrio; + int ret; + + ptrio = (unsigned long)ptr; + ret = ioctl(warm_fd, WARMC_VIRT2PHYS, &ptrio); + if (ret != 0) { + perror("WARMC_VIRT2PHYS failed"); + return (unsigned long)-1; + } + + return ptrio; +} + diff --git a/src/warm.h b/src/warm.h new file mode 100644 index 0000000..a3fdd6b --- /dev/null +++ b/src/warm.h @@ -0,0 +1,100 @@ +/* + * wARM - exporting ARM processor specific privileged services to userspace + * library functions + * + * Copyright (c) Gražvydas "notaz" Ignotas, 2009 + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the organization nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __WARM_H__ +#define __WARM_H__ 1 + +/* cache operations (warm_cache_op_*): + * o clean - write dirty data to memory, but also leave in cache. + * o invalidate - throw away everything in cache, losing dirty data. + * + * Write buffer is always drained, no ops will only drain WB + */ +#define WOP_D_CLEAN (1 << 0) +#define WOP_D_INVALIDATE (1 << 1) +#define WOP_I_INVALIDATE (1 << 2) + +/* change C and B bits (warm_change_cb_*) + * if is_set in not zero, bits are set, else cleared. + * the address for range function is virtual address. + */ +#define WCB_C_BIT (1 << 0) +#define WCB_B_BIT (1 << 1) + +#ifndef __ASSEMBLER__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +int warm_init(void); + +int warm_cache_op_range(int ops, void *virt_addr, unsigned long size); +int warm_cache_op_all(int ops); + +int warm_change_cb_upper(int cb, int is_set); +int warm_change_cb_range(int cb, int is_set, void *virt_addr, unsigned long size); + +unsigned long warm_virt2phys(const void *ptr); + +void warm_finish(void); + +#ifdef __cplusplus +} +#endif + +/* internal */ +#ifdef WARM_CODE + +#include + +#define WARM_IOCTL_BASE 'A' + +struct warm_cache_op +{ + unsigned long addr; + unsigned long size; + int ops; +}; + +struct warm_change_cb +{ + unsigned long addr; + unsigned long size; + int cb; + int is_set; +}; + +#define WARMC_CACHE_OP _IOW(WARM_IOCTL_BASE, 0, struct warm_cache_op) +#define WARMC_CHANGE_CB _IOW(WARM_IOCTL_BASE, 1, struct warm_change_cb) +#define WARMC_VIRT2PHYS _IOWR(WARM_IOCTL_BASE, 2, unsigned long) + +#endif /* WARM_CODE */ +#endif /* !__ASSEMBLER__ */ +#endif /* __WARM_H__ */ diff --git a/src/wiz_mmuhack.c b/src/wiz_mmuhack.c new file mode 100644 index 0000000..f2204d6 --- /dev/null +++ b/src/wiz_mmuhack.c @@ -0,0 +1,28 @@ +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +void wiz_mmuhack(int mem_fd) +{ + int mmufd = open("/dev/mmuhack", O_RDWR); + + + if(mmufd < 0) { + printf ("Installing NK's kernel module for Squidge MMU Hack...\n"); + system("/sbin/insmod mmuhack.ko"); + mmufd = open("/dev/mmuhack", O_RDWR); + } + if(mmufd < 0) return 0; + + close(mmufd); + return 1; +} + diff --git a/src/wiz_sdk.c b/src/wiz_sdk.c new file mode 100644 index 0000000..c36c40e --- /dev/null +++ b/src/wiz_sdk.c @@ -0,0 +1,752 @@ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "menu.h" +#include "wiz_sdk.h" +#include +#include "polluxregs.h" +#include +#include "asmmemfuncs.h" +#include "pollux_set.h" +#include "warm.h" + +#define SYS_CLK_FREQ 27 +#define BUFFERS 4 + +static int fb_size=(320*240*2); //+(16*2); + +//unsigned long gp2x_ticks_per_second=7372800/1000; +unsigned long wiz_dev[3]={0,0,0}; +unsigned long wiz_physvram[BUFFERS]={0,0,0,0}; + +unsigned short *framebuffer16[BUFFERS]={0,0,0,0}; +static unsigned short *framebuffer_mmap[BUFFERS]={0,0,0,0}; +unsigned short gp2x_sound_buffer[4+((44100*2)*8)]; //*2=stereo, *4=max buffers + +volatile short *pOutput[8]; +int InitFramebuffer=0; +int Timer=0; +volatile int SoundThreadFlag=0; +volatile int CurrentSoundBank=0; +int CurrentFrameBuffer=0; +int CurrentFrag=0; + +// 1024x8 8x8 font, i love it :) +const unsigned int font8x8[]= {0x0,0x0,0xc3663c18,0x3c2424e7,0xe724243c,0x183c66c3,0xc16f3818,0x18386fc1,0x83f61c18,0x181cf683,0xe7c3993c,0x3c99c3,0x3f7fffff,0xe7cf9f,0x3c99c3e7,0xe7c399,0x3160c080,0x40e1b,0xcbcbc37e,0x7ec3c3db,0x3c3c3c18,0x81c087e,0x8683818,0x60f0e08,0x81422418,0x18244281,0xbd5a2418,0x18245abd,0x818181ff,0xff8181,0xa1c181ff,0xff8995,0x63633e,0x3e6363,0x606060,0x606060,0x3e60603e,0x3e0303,0x3e60603e,0x3e6060,0x3e636363,0x606060,0x3e03033e,0x3e6060,0x3e03033e,0x3e6363,0x60603e,0x606060,0x3e63633e,0x3e6363,0x3e63633e,0x3e6060,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x18181818,0x180018,0x666666,0x0,0x367f3600,0x367f36,0x3c067c18,0x183e60,0x18366600,0x62660c,0xe1c361c,0x6e337b,0x181818,0x0,0x18183870,0x703818,0x18181c0e,0xe1c18,0xff3c6600,0x663c,0x7e181800,0x1818,0x0,0x60c0c00,0x7e000000,0x0,0x0,0x181800,0x18306040,0x2060c,0x6e76663c,0x3c6666,0x18181c18,0x7e1818,0x3060663c,0x7e0c18,0x3018307e,0x3c6660,0x363c3830,0x30307e,0x603e067e,0x3c6660,0x3e06063c,0x3c6666,0x1830607e,0xc0c0c,0x3c66663c,0x3c6666,0x7c66663c,0x1c3060,0x181800,0x1818,0x181800,0xc1818,0xc183060,0x603018,0x7e0000,0x7e00,0x30180c06,0x60c18,0x3060663c,0x180018,0x5676663c,0x7c0676,0x66663c18,0x66667e,0x3e66663e,0x3e6666,0x606663c,0x3c6606,0x6666361e,0x1e3666,0x3e06067e,0x7e0606,0x3e06067e,0x60606,0x7606067c,0x7c6666,0x7e666666,0x666666,0x1818183c,0x3c1818,0x60606060,0x3c6660,0xe1e3666,0x66361e,0x6060606,0x7e0606,0x6b7f7763,0x636363,0x7e7e6e66,0x666676,0x6666663c,0x3c6666,0x3e66663e,0x60606,0x6666663c,0x6c366e,0x3e66663e,0x666636,0x3c06663c,0x3c6660,0x1818187e,0x181818,0x66666666,0x7c6666,0x66666666,0x183c66,0x6b636363,0x63777f,0x183c6666,0x66663c,0x3c666666,0x181818,0x1830607e,0x7e060c,0x18181878,0x781818,0x180c0602,0x406030,0x1818181e,0x1e1818,0x63361c08,0x0,0x0,0x7f0000,0xc060300,0x0,0x603c0000,0x7c667c,0x663e0606,0x3e6666,0x63c0000,0x3c0606,0x667c6060,0x7c6666,0x663c0000,0x3c067e,0xc3e0c38,0xc0c0c,0x667c0000,0x3e607c66,0x663e0606,0x666666,0x181c0018,0x3c1818,0x18180018,0xe181818,0x36660606,0x66361e,0x1818181c,0x3c1818,0x7f370000,0x63636b,0x663e0000,0x666666,0x663c0000,0x3c6666,0x663e0000,0x63e6666,0x667c0000,0x607c6666,0x663e0000,0x60606,0x67c0000,0x3e603c,0x187e1800,0x701818,0x66660000,0x7c6666,0x66660000,0x183c66,0x63630000,0x363e6b,0x3c660000,0x663c18,0x66660000,0x3e607c66,0x307e0000,0x7e0c18,0xc181870,0x701818,0x18181818,0x18181818,0x3018180e,0xe1818,0x794f0600,0x30}; + +pthread_t gp2x_sound_thread=0, gp2x_sound_thread_exit=0; + +uint32_t bkregs32[15]; /* backing up values */ +int layer_width[2]; +volatile uint32_t *memregs32; +volatile uint16_t *memregs16; +volatile uint8_t *memregs8; + +extern unsigned short * pOutputScreen; + +/* Sets the dirty flag for the MLC */ +static void lc_dirtymlc(void) +{ + MLCCONTROLT |= BIT(3); +} + +#define FBIO_MAGIC 'D' +#define FBIO_LCD_CHANGE_CONTROL _IOW(FBIO_MAGIC, 90, unsigned int[2]) +#define LCD_DIRECTION_ON_CMD 5 /* 320x240 */ +#define LCD_DIRECTION_OFF_CMD 6 /* 240x320 */ + +void lc_screensize(int w, int h) { + unsigned int send[2]; + int fb_fd = open("/dev/fb0", O_RDWR); + send[1] = 0; + /* alter MLC to rotate the display */ + if(w == 320 && h == 240) { + send[0] = LCD_DIRECTION_ON_CMD; + } else if(w == 240 && h == 320) { + send[0] = LCD_DIRECTION_OFF_CMD; + } + + /* send command to display controller */ + ioctl(fb_fd, FBIO_LCD_CHANGE_CONTROL, &send); + close(fb_fd); + /* apply the MLC changes */ + MLCSCREENSIZE = ((h-1)<<16) | (w-1); + lc_dirtymlc(); +} + +/* Sets the dirty flag for the layer */ +static void lc_dirtylayer(int layer) +{ + if(layer == 0) { + MLCCONTROL0 |= BIT(4); + } else { + MLCCONTROL1 |= BIT(4); + } +} + +/* Sets layer position */ +static void lc_layerpos(int layer, int x1, int y1, int x2, int y2) +{ + unsigned int temp_lr, temp_tb; + temp_lr = (x1 << 16) | x2; + temp_tb = (y1 << 16) | y2; + + if(layer == 0) { + MLCLEFTRIGHT0 = temp_lr; + MLCTOPBOTTOM0 = temp_tb; + } else { + MLCLEFTRIGHT1 = temp_lr; + MLCTOPBOTTOM1 = temp_tb; + } + lc_dirtylayer(layer); + + layer_width[layer] = (x2-x1)+1; +} + +/* Sets stride registers */ +static void lc_setstride(int layer, int hs, int vs) +{ + /* set how many bytes the MLC is supposed to read */ + if(layer == 0) { + MLCHSTRIDE0 = hs; + MLCVSTRIDE0 = vs; + } else { + MLCHSTRIDE1 = hs; + MLCVSTRIDE1 = vs; + } + lc_dirtylayer(layer); +} + +/* Sets layer properties */ +static void lc_setlayer(int layer, unsigned int onoff, unsigned int alpha, unsigned int invert, unsigned int trans, unsigned int mode) +{ + /* set layer properties register */ + unsigned int temp; + temp = 0; + if(onoff) temp |= BIT(5); + if(alpha) temp |= BIT(2); + if(invert) temp |= BIT(1); + if(trans) temp |= BIT(0); + temp |= BIT(12); + temp |= BIT(14); + temp |= BIT(15); + temp |= (mode<<16); + + if(layer == 0) { + MLCCONTROL0 = temp; + } else { + MLCCONTROL1= temp; + } + lc_dirtylayer(layer); + + int pixel_width = 0; + /* set stride based on pixel width*/ + switch(mode) { + case RGB565: + case BGR565: + case XRGB1555: + case XBGR1555: + case XRGB4444: + case XBGR4444: + case XRGB8332: + case XBGR8332: + case ARGB1555: + case ABGR1555: + case ARGB4444: + case ABGR4444: + case ARGB8332: + case ABGR8332: + pixel_width = 2; + break; + case RGB888: + case BGR888: + pixel_width = 3; + break; + case ARGB8888: + case ABGR8888: + pixel_width = 4; + break; + case PTRGB565: + pixel_width = 1; + break; + default: + break; + } + lc_setstride(layer, pixel_width, pixel_width*layer_width[layer]); +} + +/* Sets the background colour */ +static void lc_setbgcol(unsigned int colour) +{ + /* colour to be displayed where no layers cover */ + MLCBGCOLOR = colour; + lc_dirtymlc(); +} + +/* +######################## +Graphics functions +######################## + */ + +static void debug(char *text, int pause) +{ + gp_clearFramebuffer16(framebuffer16[currFB],0); + gp_drawString(0,0,strlen(text),text,(unsigned short)MENU_RGB(31,31,31),framebuffer16[currFB]); + MenuFlip(); + if(pause) MenuPause(); + +} + +static int clipping_x1 = 0; +static int clipping_x2 = 319; +static int clipping_y1 = 0; +static int clipping_y2 = 239; + +void gp_setClipping(int x1, int y1, int x2, int y2) { + if (x1 < 0) x1 = 0; + if (x1 > 319) x1 = 319; + if (x2 < 0) x2 = 0; + if (x2 > 319) x2 = 319; + if (y1 < 0) y1 = 0; + if (y1 > 239) y1 = 239; + if (y2 < 0) y2 = 0; + if (y2 > 239) y2 = 239; + + if (x1 < x2) { + clipping_x1 = x1; + clipping_x2 = x2; + } else { + clipping_x2 = x1; + clipping_x1 = x2; + } + + if (y1 < y2) { + clipping_y1 = y1; + clipping_y2 = y2; + } else { + clipping_y2 = y1; + clipping_y1 = y2; + } +} + +static __inline__ +void gp_drawPixel16 ( int x, int y, unsigned short c, unsigned short *framebuffer ) +{ + if ((x < clipping_x1) || (x > clipping_x2) || (y < clipping_y1) || (y > clipping_y2)) return; + *(framebuffer +(320*y)+x ) = c; +} +static +void set_char8x8_16bpp (int xx,int yy,int offset,unsigned short mode,unsigned short *framebuffer) +{ + unsigned int y, pixel; + offset *= 2; + pixel = font8x8[0 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y, mode, framebuffer); + } + pixel = font8x8[1 + offset]; + for (y = 0; y < 4; y++) + { + if (pixel&(1<<(0+(y<<3)))) gp_drawPixel16(xx+0, yy+y+4, mode, framebuffer); + if (pixel&(1<<(1+(y<<3)))) gp_drawPixel16(xx+1, yy+y+4, mode, framebuffer); + if (pixel&(1<<(2+(y<<3)))) gp_drawPixel16(xx+2, yy+y+4, mode, framebuffer); + if (pixel&(1<<(3+(y<<3)))) gp_drawPixel16(xx+3, yy+y+4, mode, framebuffer); + if (pixel&(1<<(4+(y<<3)))) gp_drawPixel16(xx+4, yy+y+4, mode, framebuffer); + if (pixel&(1<<(5+(y<<3)))) gp_drawPixel16(xx+5, yy+y+4, mode, framebuffer); + if (pixel&(1<<(6+(y<<3)))) gp_drawPixel16(xx+6, yy+y+4, mode, framebuffer); + if (pixel&(1<<(7+(y<<3)))) gp_drawPixel16(xx+7, yy+y+4, mode, framebuffer); + + } +} + +void gp_drawString (int x,int y,int len,char *buffer,unsigned short color,void *framebuffer) +{ + int l,base=0; + + for (l=0;l= 8) CurrentSoundBank = 0; + + //if (SoundThreadFlag==SOUND_THREAD_SOUND_ON) + //{ + write(wiz_dev[1], (void *)pOutput[CurrentSoundBank], gp2x_sound_buffer[1]); + CurrentSoundBank = (CurrentSoundBank + 1) & 7; + ioctl(wiz_dev[1], SOUND_PCM_SYNC, 0); + //ts.tv_sec=0, ts.tv_nsec=(gp2x_sound_buffer[3]<<16)|gp2x_sound_buffer[2]; + //nanosleep(&ts, NULL); +/* + } + else + { + write(wiz_dev[1], (void *)&gp2x_sound_buffer[4], gp2x_sound_buffer[1]); + //ioctl(wiz_dev[1], SOUND_PCM_SYNC, 0); + //ts.tv_sec=0, ts.tv_nsec=(gp2x_sound_buffer[3]<<16)|gp2x_sound_buffer[2]; + //nanosleep(&ts, NULL); + } +*/ + } + + return NULL; +} + +void gp_sound_volume(int l, int r) +{ + if(!wiz_dev[2]) + { + wiz_dev[2] = open("/dev/mixer", O_WRONLY); + } + + l=((l<<8)|r); + ioctl(wiz_dev[2], SOUND_MIXER_WRITE_PCM, &l); +} + +/* +unsigned long gp_timer_read(void) +{ + // Once again another peice of direct hardware access bites the dust + // the code below is broken in firmware 2.1.1 so I've replaced it with a + // to a linux function which seems to work + //return gp2x_memregl[0x0A00>>2]/gp2x_ticks_per_second; + struct timeval tval; // timing + + gettimeofday(&tval, 0); + //tval.tv_usec + //tval.tv_sec + return (tval.tv_sec*1000000)+tval.tv_usec; +} +*/ + +int gp_initSound(int rate, int bits, int stereo, int Hz, int frag) +{ + int status; + int i=0; + int nonblocking=1; + unsigned int bufferStart=0; + int result; + char text[256]; + + //int frag=0x00020010; // double buffer - frag size = 1<<0xf = 32768 + + //8 = 256 = 2 fps loss = good sound + //9 = 512 = 1 fps loss = good sound + //A = 1024 = + //f = 32768 = 0 fps loss = bad sound + /* + if ((frag!= CurrentFrag)&&(wiz_dev[1]!=0)) + { + // Different frag config required + // close device in order to re-adjust + close(wiz_dev[1]); + wiz_dev[1]=0; + } + */ + + if (wiz_dev[1]==0) + { + wiz_dev[1] = open("/dev/dsp", O_WRONLY); + printf("Opening sound device: %x\r\n",wiz_dev[1]); + //ioctl(wiz_dev[1], SNDCTL_DSP_SETFRAGMENT, &frag); + //CurrentFrag=frag; // save frag config + } + + //ioctl(wiz_dev[3], SNDCTL_DSP_RESET, 0); + result=ioctl(wiz_dev[1], SNDCTL_DSP_SPEED, &rate); + if(result==-1) + { + debug("Error setting DSP Speed",1); + return(-1); + } + + result=ioctl(wiz_dev[1], SNDCTL_DSP_SETFMT, &bits); + if(result==-1) + { + debug("Error setting DSP format",1); + return(-1); + } + + result=ioctl(wiz_dev[1], SNDCTL_DSP_STEREO, &stereo); + if(result==-1) + { + debug("Error setting DSP format",1); + return(-1); + } + //printf("Disable Blocking: %x\r\n",ioctl(wiz_dev[3], 0x5421, &nonblocking)); + + gp2x_sound_buffer[1]=(gp2x_sound_buffer[0]=(rate/Hz)) << (stereo + (bits==16)); + gp2x_sound_buffer[2]=(1000000000/Hz)&0xFFFF; + gp2x_sound_buffer[3]=(1000000000/Hz)>>16; + + bufferStart= (unsigned int)&gp2x_sound_buffer[4]; + pOutput[0] = (short*)bufferStart+(0*gp2x_sound_buffer[1]); + pOutput[1] = (short*)bufferStart+(1*gp2x_sound_buffer[1]); + pOutput[2] = (short*)bufferStart+(2*gp2x_sound_buffer[1]); + pOutput[3] = (short*)bufferStart+(3*gp2x_sound_buffer[1]); + pOutput[4] = (short*)bufferStart+(4*gp2x_sound_buffer[1]); + pOutput[5] = (short*)bufferStart+(5*gp2x_sound_buffer[1]); + pOutput[6] = (short*)bufferStart+(6*gp2x_sound_buffer[1]); + pOutput[7] = (short*)bufferStart+(7*gp2x_sound_buffer[1]); + + if(!gp2x_sound_thread) + { + pthread_create( &gp2x_sound_thread, NULL, gp2x_sound_play, NULL); + //atexit(gp_Reset); + } + + for(i=0;i<(gp2x_sound_buffer[1]*8);i++) + { + gp2x_sound_buffer[4+i] = 0; + } + + return(0); +} + +void gp_stopSound(void) +{ + unsigned int i=0; + gp2x_sound_thread_exit=1; + printf("Killing Thread\r\n"); + for(i=0;i<(gp2x_sound_buffer[1]*8);i++) + { + gp2x_sound_buffer[4+i] = 0; + } + usleep(100000); + printf("Thread is dead\r\n"); + gp2x_sound_thread=0; + gp2x_sound_thread_exit=0; + CurrentSoundBank=0; +} + + +/* +######################## +System functions +######################## + */ +void gp_Reset(void) +{ + unsigned int i=0; + + gp_setCpuspeed(533); + + if( gp2x_sound_thread) + { + gp2x_sound_thread_exit=1; + usleep(500); + } + + MLCADDRESS0 = bkregs32[0]; MLCADDRESS1 = bkregs32[1]; MLCCONTROL0 = bkregs32[2]; MLCCONTROL1 = bkregs32[3]; MLCLEFTRIGHT0 = bkregs32[4]; + MLCTOPBOTTOM0 = bkregs32[5]; MLCLEFTRIGHT1 = bkregs32[6]; MLCTOPBOTTOM1 = bkregs32[7]; MLCBGCOLOR = bkregs32[8]; MLCHSTRIDE0 = bkregs32[9]; + MLCVSTRIDE0 = bkregs32[10]; MLCHSTRIDE1 = bkregs32[11]; MLCVSTRIDE1 = bkregs32[12]; DPCCTRL1 = bkregs32[13]; MLCSCREENSIZE = bkregs32[14]; + + lc_dirtylayer(0); + lc_dirtylayer(1); + lc_dirtymlc(); + + munmap((void *)memregs32, 0x20000); + + munmap(framebuffer_mmap[0], fb_size * BUFFERS); + + if (wiz_dev[0]) close(wiz_dev[0]); + if (wiz_dev[1]) close(wiz_dev[1]); + if (wiz_dev[2]) close(wiz_dev[2]); + + fcloseall(); + + chdir("/usr/gp2x"); + execl("gp2xmenu",NULL); +} + +void gp_video_RGB_setscaling(int W, int H) +{ + uint16_t * pSource = (uint16_t *)pOutputScreen; + uint16_t * pTarget = (uint16_t *)framebuffer16[currFB]; + unsigned short y; + unsigned short x; + if (H == 239) + { + for (y = 240; y != 0; y--) + { + pSource+=32; + for (x = 64; x != 0; x--) + { + pTarget[0] = pSource[0]; + pTarget[1] = pSource[1]; + pTarget[2] = pSource[2]; + pTarget[3] = pSource[3]; + pTarget[4] = pSource[3]; + pTarget+=5; + pSource+=4; + } + pSource+=32; + } + } + else // 224 + { + pSource += 2560; + unsigned short pos = 2; + for (y = 240; y != 0; y--) + { + pSource+=32; + for (x = 64; x != 0; x--) + { + pTarget[0] = pSource[0]; + pTarget[1] = pSource[1]; + pTarget[2] = pSource[2]; + pTarget[3] = pSource[3]; + pTarget[4] = pSource[3]; + pTarget+=5; + pSource+=4; + } + pSource+=32; + pos--; + + if (pos == 0) + { + pSource -= 320; + pos = 14; + } + } + } +} + +#define COLORMIX(a, b) ( ((((a & 0xF81F) + (b & 0xF81F)) >> 1) & 0xF81F) | ((((a & 0x07E0) + (b & 0x07E0)) >> 1) & 0x07E0) ) +void gp_video_RGB_setHZscaling(int W, int H) +{ + uint16_t * pSource = (uint16_t *)pOutputScreen; + uint16_t * pTarget = (uint16_t *)framebuffer16[currFB]; + unsigned short y; + unsigned short x; + + if (H == 224) + { + pSource += 2560; + pTarget += 2560; + } + for (y = H; y != 0; y--) + { + pSource+=32; + for (x = 64; x != 0; x--) + { + pTarget[0] = pSource[0]; + pTarget[1] = pSource[1]; + pTarget[2] = pSource[2]; + pTarget[3] = COLORMIX(pSource[2],pSource[3]); + pTarget[4] = pSource[3]; + pTarget+=5; + pSource+=4; + } + pSource+=32; + } +} + +void gp_setCpuspeed(unsigned int MHZ) +{ + unsigned long v; + unsigned mdiv, pdiv=9, sdiv=0; + + mdiv= (MHZ * pdiv) / SYS_CLK_FREQ; + mdiv &= 0x3FF; + v= pdiv<<18 | mdiv<<8 | sdiv; + + PLLSETREG0 = v; + PWRMODE |= 0x8000; +} + +// craigix: --trc 6 --tras 4 --twr 1 --tmrd 1 --trfc 1 --trp 2 --trcd 2 +// set_RAM_Timings(6, 4, 1, 1, 1, 2, 2); +void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD) +{ +} + +void set_gamma(int g100) +{ +} + + + + + diff --git a/src/wiz_sdk.h b/src/wiz_sdk.h new file mode 100644 index 0000000..1a613c9 --- /dev/null +++ b/src/wiz_sdk.h @@ -0,0 +1,64 @@ +#ifndef _WIZ_SDK_H_ +#define _WIZ_SDK_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define UPPERMEM_START 0x3000000 +//0x2A00000 +#define UPPERMEM_SIZE (0x4000000-UPPERMEM_START) + +#define SOUND_THREAD_SOUND_ON 1 +#define SOUND_THREAD_SOUND_OFF 2 +#define SOUND_THREAD_PAUSE 3 + +#define INP_BUTTON_UP (18) +#define INP_BUTTON_LEFT (16) +#define INP_BUTTON_DOWN (19) +#define INP_BUTTON_RIGHT (17) +#define INP_BUTTON_START (9) +#define INP_BUTTON_SELECT (8) +#define INP_BUTTON_L (7) +#define INP_BUTTON_R (6) +#define INP_BUTTON_A (20) +#define INP_BUTTON_B (21) +#define INP_BUTTON_X (22) +#define INP_BUTTON_Y (23) +#define INP_BUTTON_VOL_UP (10) +#define INP_BUTTON_VOL_DOWN (11) + +void gp_setClipping(int x1, int y1, int x2, int y2); +void gp_drawString (int x,int y,int len,char *buffer,unsigned short color,void *framebuffer); +void gp_clearFramebuffer16(unsigned short *framebuffer, unsigned short pal); +void gp_setCpuspeed(unsigned int cpuspeed); +void gp_initGraphics(unsigned short bpp, int flip, int applyMmuHack); +void gp_setFramebuffer(int flip, int sync); +int gp_initSound(int rate, int bits, int stereo, int Hz, int frag); +void gp_stopSound(void); +void gp_Reset(void); +void gp_sound_volume(int l, int r); +//unsigned long gp_timer_read(void); +#define gp_timer_read clock + +unsigned int gp_getButton(unsigned char enable_diagnals); +void gp_video_RGB_setscaling(int W, int H); +void gp_video_RGB_setHZscaling(int W, int H); +void set_gamma(int g100); +void set_RAM_Timings(int tRC, int tRAS, int tWR, int tMRD, int tRFC, int tRP, int tRCD); + +extern volatile int SoundThreadFlag; +extern volatile int CurrentSoundBank; +extern int CurrentFrameBuffer; +extern volatile short *pOutput[]; +extern unsigned short *framebuffer16[]; +extern unsigned long wiz_physvram[]; +extern volatile unsigned short *wiz_memregs; +extern void *uppermem; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/zip.c b/src/zip.c new file mode 100644 index 0000000..762fcef --- /dev/null +++ b/src/zip.c @@ -0,0 +1,1218 @@ +/* zip.c -- IO on .zip files using zlib + Version 1.01e, February 12th, 2005 + + 27 Dec 2004 Rolf Kalbermatter + Modification to zipOpen2 to support globalComment retrieval. + + Copyright (C) 1998-2005 Gilles Vollant + + Read zip.h for more info +*/ + + +#include +#include +#include +#include +#include "zlib.h" +#include "zip.h" + +#ifdef STDC +# include +# include +# include +#endif +#ifdef NO_ERRNO_H + extern int errno; +#else +# include +#endif + + +#ifndef local +# define local static +#endif +/* compile with -Dlocal if your debugger can't find static symbols */ + +#ifndef VERSIONMADEBY +# define VERSIONMADEBY (0x0) /* platform depedent */ +#endif + +#ifndef Z_BUFSIZE +#define Z_BUFSIZE (16384) +#endif + +#ifndef Z_MAXFILENAMEINZIP +#define Z_MAXFILENAMEINZIP (256) +#endif + +#ifndef ALLOC +# define ALLOC(size) (malloc(size)) +#endif +#ifndef TRYFREE +# define TRYFREE(p) {if (p) free(p);} +#endif + +/* +#define SIZECENTRALDIRITEM (0x2e) +#define SIZEZIPLOCALHEADER (0x1e) +*/ + +/* I've found an old Unix (a SunOS 4.1.3_U1) without all SEEK_* defined.... */ + +#ifndef SEEK_CUR +#define SEEK_CUR 1 +#endif + +#ifndef SEEK_END +#define SEEK_END 2 +#endif + +#ifndef SEEK_SET +#define SEEK_SET 0 +#endif + +#ifndef DEF_MEM_LEVEL +#if MAX_MEM_LEVEL >= 8 +# define DEF_MEM_LEVEL 8 +#else +# define DEF_MEM_LEVEL MAX_MEM_LEVEL +#endif +#endif +const char zip_copyright[] = + " zip 1.01 Copyright 1998-2004 Gilles Vollant - http://www.winimage.com/zLibDll"; + + +#define SIZEDATA_INDATABLOCK (4096-(4*4)) + +#define LOCALHEADERMAGIC (0x04034b50) +#define CENTRALHEADERMAGIC (0x02014b50) +#define ENDHEADERMAGIC (0x06054b50) + +#define FLAG_LOCALHEADER_OFFSET (0x06) +#define CRC_LOCALHEADER_OFFSET (0x0e) + +#define SIZECENTRALHEADER (0x2e) /* 46 */ + +typedef struct linkedlist_datablock_internal_s +{ + struct linkedlist_datablock_internal_s* next_datablock; + uLong avail_in_this_block; + uLong filled_in_this_block; + uLong unused; /* for future use and alignement */ + unsigned char data[SIZEDATA_INDATABLOCK]; +} linkedlist_datablock_internal; + +typedef struct linkedlist_data_s +{ + linkedlist_datablock_internal* first_block; + linkedlist_datablock_internal* last_block; +} linkedlist_data; + + +typedef struct +{ + z_stream stream; /* zLib stream structure for inflate */ + int stream_initialised; /* 1 is stream is initialised */ + uInt pos_in_buffered_data; /* last written byte in buffered_data */ + + uLong pos_local_header; /* offset of the local header of the file + currenty writing */ + char* central_header; /* central header data for the current file */ + uLong size_centralheader; /* size of the central header for cur file */ + uLong flag; /* flag of the file currently writing */ + + int method; /* compression method of file currenty wr.*/ + int raw; /* 1 for directly writing raw data */ + Byte buffered_data[Z_BUFSIZE];/* buffer contain compressed data to be writ*/ + uLong dosDate; + uLong crc32; + int encrypt; +#ifndef NOCRYPT + unsigned long keys[3]; /* keys defining the pseudo-random sequence */ + const unsigned long* pcrc_32_tab; + int crypt_header_size; +#endif +} curfile_info; + +typedef struct +{ + zlib_filefunc_def z_filefunc; + voidpf filestream; /* io structore of the zipfile */ + linkedlist_data central_dir;/* datablock with central dir in construction*/ + int in_opened_file_inzip; /* 1 if a file in the zip is currently writ.*/ + curfile_info ci; /* info on the file curretly writing */ + + uLong begin_pos; /* position of the beginning of the zipfile */ + uLong add_position_when_writting_offset; + uLong number_entry; +#ifndef NO_ADDFILEINEXISTINGZIP + char *globalcomment; +#endif +} zip_internal; + + + +#ifndef NOCRYPT +#define INCLUDECRYPTINGCODE_IFCRYPTALLOWED +#include "crypt.h" +#endif + +local linkedlist_datablock_internal* allocate_new_datablock() +{ + linkedlist_datablock_internal* ldi; + ldi = (linkedlist_datablock_internal*) + ALLOC(sizeof(linkedlist_datablock_internal)); + if (ldi!=NULL) + { + ldi->next_datablock = NULL ; + ldi->filled_in_this_block = 0 ; + ldi->avail_in_this_block = SIZEDATA_INDATABLOCK ; + } + return ldi; +} + +local void free_datablock(ldi) + linkedlist_datablock_internal* ldi; +{ + while (ldi!=NULL) + { + linkedlist_datablock_internal* ldinext = ldi->next_datablock; + TRYFREE(ldi); + ldi = ldinext; + } +} + +local void init_linkedlist(ll) + linkedlist_data* ll; +{ + ll->first_block = ll->last_block = NULL; +} + +local void free_linkedlist(ll) + linkedlist_data* ll; +{ + free_datablock(ll->first_block); + ll->first_block = ll->last_block = NULL; +} + + +local int add_data_in_datablock(ll,buf,len) + linkedlist_data* ll; + const void* buf; + uLong len; +{ + linkedlist_datablock_internal* ldi; + const unsigned char* from_copy; + + if (ll==NULL) + return ZIP_INTERNALERROR; + + if (ll->last_block == NULL) + { + ll->first_block = ll->last_block = allocate_new_datablock(); + if (ll->first_block == NULL) + return ZIP_INTERNALERROR; + } + + ldi = ll->last_block; + from_copy = (unsigned char*)buf; + + while (len>0) + { + uInt copy_this; + uInt i; + unsigned char* to_copy; + + if (ldi->avail_in_this_block==0) + { + ldi->next_datablock = allocate_new_datablock(); + if (ldi->next_datablock == NULL) + return ZIP_INTERNALERROR; + ldi = ldi->next_datablock ; + ll->last_block = ldi; + } + + if (ldi->avail_in_this_block < len) + copy_this = (uInt)ldi->avail_in_this_block; + else + copy_this = (uInt)len; + + to_copy = &(ldi->data[ldi->filled_in_this_block]); + + for (i=0;ifilled_in_this_block += copy_this; + ldi->avail_in_this_block -= copy_this; + from_copy += copy_this ; + len -= copy_this; + } + return ZIP_OK; +} + + + +/****************************************************************************/ + +#ifndef NO_ADDFILEINEXISTINGZIP +/* =========================================================================== + Inputs a long in LSB order to the given file + nbByte == 1, 2 or 4 (byte, short or long) +*/ + +local int ziplocal_putValue OF((const zlib_filefunc_def* pzlib_filefunc_def, + voidpf filestream, uLong x, int nbByte)); +local int ziplocal_putValue (pzlib_filefunc_def, filestream, x, nbByte) + const zlib_filefunc_def* pzlib_filefunc_def; + voidpf filestream; + uLong x; + int nbByte; +{ + unsigned char buf[4]; + int n; + for (n = 0; n < nbByte; n++) + { + buf[n] = (unsigned char)(x & 0xff); + x >>= 8; + } + if (x != 0) + { /* data overflow - hack for ZIP64 (X Roche) */ + for (n = 0; n < nbByte; n++) + { + buf[n] = 0xff; + } + } + + if (ZWRITE(*pzlib_filefunc_def,filestream,buf,nbByte)!=(uLong)nbByte) + return ZIP_ERRNO; + else + return ZIP_OK; +} + +local void ziplocal_putValue_inmemory OF((void* dest, uLong x, int nbByte)); +local void ziplocal_putValue_inmemory (dest, x, nbByte) + void* dest; + uLong x; + int nbByte; +{ + unsigned char* buf=(unsigned char*)dest; + int n; + for (n = 0; n < nbByte; n++) { + buf[n] = (unsigned char)(x & 0xff); + x >>= 8; + } + + if (x != 0) + { /* data overflow - hack for ZIP64 */ + for (n = 0; n < nbByte; n++) + { + buf[n] = 0xff; + } + } +} + +/****************************************************************************/ + + +local uLong ziplocal_TmzDateToDosDate(ptm,dosDate) + const tm_zip* ptm; + uLong dosDate; +{ + uLong year = (uLong)ptm->tm_year; + if (year>1980) + year-=1980; + else if (year>80) + year-=80; + return + (uLong) (((ptm->tm_mday) + (32 * (ptm->tm_mon+1)) + (512 * year)) << 16) | + ((ptm->tm_sec/2) + (32* ptm->tm_min) + (2048 * (uLong)ptm->tm_hour)); +} + + +/****************************************************************************/ + +local int ziplocal_getByte OF(( + const zlib_filefunc_def* pzlib_filefunc_def, + voidpf filestream, + int *pi)); + +local int ziplocal_getByte(pzlib_filefunc_def,filestream,pi) + const zlib_filefunc_def* pzlib_filefunc_def; + voidpf filestream; + int *pi; +{ + unsigned char c; + int err = (int)ZREAD(*pzlib_filefunc_def,filestream,&c,1); + if (err==1) + { + *pi = (int)c; + return ZIP_OK; + } + else + { + if (ZERROR(*pzlib_filefunc_def,filestream)) + return ZIP_ERRNO; + else + return ZIP_EOF; + } +} + + +/* =========================================================================== + Reads a long in LSB order from the given gz_stream. Sets +*/ +local int ziplocal_getShort OF(( + const zlib_filefunc_def* pzlib_filefunc_def, + voidpf filestream, + uLong *pX)); + +local int ziplocal_getShort (pzlib_filefunc_def,filestream,pX) + const zlib_filefunc_def* pzlib_filefunc_def; + voidpf filestream; + uLong *pX; +{ + uLong x ; + int i; + int err; + + err = ziplocal_getByte(pzlib_filefunc_def,filestream,&i); + x = (uLong)i; + + if (err==ZIP_OK) + err = ziplocal_getByte(pzlib_filefunc_def,filestream,&i); + x += ((uLong)i)<<8; + + if (err==ZIP_OK) + *pX = x; + else + *pX = 0; + return err; +} + +local int ziplocal_getLong OF(( + const zlib_filefunc_def* pzlib_filefunc_def, + voidpf filestream, + uLong *pX)); + +local int ziplocal_getLong (pzlib_filefunc_def,filestream,pX) + const zlib_filefunc_def* pzlib_filefunc_def; + voidpf filestream; + uLong *pX; +{ + uLong x ; + int i; + int err; + + err = ziplocal_getByte(pzlib_filefunc_def,filestream,&i); + x = (uLong)i; + + if (err==ZIP_OK) + err = ziplocal_getByte(pzlib_filefunc_def,filestream,&i); + x += ((uLong)i)<<8; + + if (err==ZIP_OK) + err = ziplocal_getByte(pzlib_filefunc_def,filestream,&i); + x += ((uLong)i)<<16; + + if (err==ZIP_OK) + err = ziplocal_getByte(pzlib_filefunc_def,filestream,&i); + x += ((uLong)i)<<24; + + if (err==ZIP_OK) + *pX = x; + else + *pX = 0; + return err; +} + +#ifndef BUFREADCOMMENT +#define BUFREADCOMMENT (0x400) +#endif +/* + Locate the Central directory of a zipfile (at the end, just before + the global comment) +*/ +local uLong ziplocal_SearchCentralDir OF(( + const zlib_filefunc_def* pzlib_filefunc_def, + voidpf filestream)); + +local uLong ziplocal_SearchCentralDir(pzlib_filefunc_def,filestream) + const zlib_filefunc_def* pzlib_filefunc_def; + voidpf filestream; +{ + unsigned char* buf; + uLong uSizeFile; + uLong uBackRead; + uLong uMaxBack=0xffff; /* maximum size of global comment */ + uLong uPosFound=0; + + if (ZSEEK(*pzlib_filefunc_def,filestream,0,ZLIB_FILEFUNC_SEEK_END) != 0) + return 0; + + + uSizeFile = ZTELL(*pzlib_filefunc_def,filestream); + + if (uMaxBack>uSizeFile) + uMaxBack = uSizeFile; + + buf = (unsigned char*)ALLOC(BUFREADCOMMENT+4); + if (buf==NULL) + return 0; + + uBackRead = 4; + while (uBackReaduMaxBack) + uBackRead = uMaxBack; + else + uBackRead+=BUFREADCOMMENT; + uReadPos = uSizeFile-uBackRead ; + + uReadSize = ((BUFREADCOMMENT+4) < (uSizeFile-uReadPos)) ? + (BUFREADCOMMENT+4) : (uSizeFile-uReadPos); + if (ZSEEK(*pzlib_filefunc_def,filestream,uReadPos,ZLIB_FILEFUNC_SEEK_SET)!=0) + break; + + if (ZREAD(*pzlib_filefunc_def,filestream,buf,uReadSize)!=uReadSize) + break; + + for (i=(int)uReadSize-3; (i--)>0;) + if (((*(buf+i))==0x50) && ((*(buf+i+1))==0x4b) && + ((*(buf+i+2))==0x05) && ((*(buf+i+3))==0x06)) + { + uPosFound = uReadPos+i; + break; + } + + if (uPosFound!=0) + break; + } + TRYFREE(buf); + return uPosFound; +} +#endif /* !NO_ADDFILEINEXISTINGZIP*/ + +/************************************************************/ +extern zipFile ZEXPORT zipOpen2 (pathname, append, globalcomment, pzlib_filefunc_def) + const char *pathname; + int append; + zipcharpc* globalcomment; + zlib_filefunc_def* pzlib_filefunc_def; +{ + zip_internal ziinit; + zip_internal* zi; + int err=ZIP_OK; + + + if (pzlib_filefunc_def==NULL) + fill_fopen_filefunc(&ziinit.z_filefunc); + else + ziinit.z_filefunc = *pzlib_filefunc_def; + + ziinit.filestream = (*(ziinit.z_filefunc.zopen_file)) + (ziinit.z_filefunc.opaque, + pathname, + (append == APPEND_STATUS_CREATE) ? + (ZLIB_FILEFUNC_MODE_READ | ZLIB_FILEFUNC_MODE_WRITE | ZLIB_FILEFUNC_MODE_CREATE) : + (ZLIB_FILEFUNC_MODE_READ | ZLIB_FILEFUNC_MODE_WRITE | ZLIB_FILEFUNC_MODE_EXISTING)); + + if (ziinit.filestream == NULL) + return NULL; + ziinit.begin_pos = ZTELL(ziinit.z_filefunc,ziinit.filestream); + ziinit.in_opened_file_inzip = 0; + ziinit.ci.stream_initialised = 0; + ziinit.number_entry = 0; + ziinit.add_position_when_writting_offset = 0; + init_linkedlist(&(ziinit.central_dir)); + + + zi = (zip_internal*)ALLOC(sizeof(zip_internal)); + if (zi==NULL) + { + ZCLOSE(ziinit.z_filefunc,ziinit.filestream); + return NULL; + } + + /* now we add file in a zipfile */ +# ifndef NO_ADDFILEINEXISTINGZIP + ziinit.globalcomment = NULL; + if (append == APPEND_STATUS_ADDINZIP) + { + uLong byte_before_the_zipfile;/* byte before the zipfile, (>0 for sfx)*/ + + uLong size_central_dir; /* size of the central directory */ + uLong offset_central_dir; /* offset of start of central directory */ + uLong central_pos,uL; + + uLong number_disk; /* number of the current dist, used for + spaning ZIP, unsupported, always 0*/ + uLong number_disk_with_CD; /* number the the disk with central dir, used + for spaning ZIP, unsupported, always 0*/ + uLong number_entry; + uLong number_entry_CD; /* total number of entries in + the central dir + (same than number_entry on nospan) */ + uLong size_comment; + + central_pos = ziplocal_SearchCentralDir(&ziinit.z_filefunc,ziinit.filestream); + if (central_pos==0) + err=ZIP_ERRNO; + + if (ZSEEK(ziinit.z_filefunc, ziinit.filestream, + central_pos,ZLIB_FILEFUNC_SEEK_SET)!=0) + err=ZIP_ERRNO; + + /* the signature, already checked */ + if (ziplocal_getLong(&ziinit.z_filefunc, ziinit.filestream,&uL)!=ZIP_OK) + err=ZIP_ERRNO; + + /* number of this disk */ + if (ziplocal_getShort(&ziinit.z_filefunc, ziinit.filestream,&number_disk)!=ZIP_OK) + err=ZIP_ERRNO; + + /* number of the disk with the start of the central directory */ + if (ziplocal_getShort(&ziinit.z_filefunc, ziinit.filestream,&number_disk_with_CD)!=ZIP_OK) + err=ZIP_ERRNO; + + /* total number of entries in the central dir on this disk */ + if (ziplocal_getShort(&ziinit.z_filefunc, ziinit.filestream,&number_entry)!=ZIP_OK) + err=ZIP_ERRNO; + + /* total number of entries in the central dir */ + if (ziplocal_getShort(&ziinit.z_filefunc, ziinit.filestream,&number_entry_CD)!=ZIP_OK) + err=ZIP_ERRNO; + + if ((number_entry_CD!=number_entry) || + (number_disk_with_CD!=0) || + (number_disk!=0)) + err=ZIP_BADZIPFILE; + + /* size of the central directory */ + if (ziplocal_getLong(&ziinit.z_filefunc, ziinit.filestream,&size_central_dir)!=ZIP_OK) + err=ZIP_ERRNO; + + /* offset of start of central directory with respect to the + starting disk number */ + if (ziplocal_getLong(&ziinit.z_filefunc, ziinit.filestream,&offset_central_dir)!=ZIP_OK) + err=ZIP_ERRNO; + + /* zipfile global comment length */ + if (ziplocal_getShort(&ziinit.z_filefunc, ziinit.filestream,&size_comment)!=ZIP_OK) + err=ZIP_ERRNO; + + if ((central_pos0) + { + ziinit.globalcomment = ALLOC(size_comment+1); + if (ziinit.globalcomment) + { + size_comment = ZREAD(ziinit.z_filefunc, ziinit.filestream,ziinit.globalcomment,size_comment); + ziinit.globalcomment[size_comment]=0; + } + } + + byte_before_the_zipfile = central_pos - + (offset_central_dir+size_central_dir); + ziinit.add_position_when_writting_offset = byte_before_the_zipfile ; + + { + uLong size_central_dir_to_read = size_central_dir; + size_t buf_size = SIZEDATA_INDATABLOCK; + void* buf_read = (void*)ALLOC(buf_size); + if (ZSEEK(ziinit.z_filefunc, ziinit.filestream, + offset_central_dir + byte_before_the_zipfile, + ZLIB_FILEFUNC_SEEK_SET) != 0) + err=ZIP_ERRNO; + + while ((size_central_dir_to_read>0) && (err==ZIP_OK)) + { + uLong read_this = SIZEDATA_INDATABLOCK; + if (read_this > size_central_dir_to_read) + read_this = size_central_dir_to_read; + if (ZREAD(ziinit.z_filefunc, ziinit.filestream,buf_read,read_this) != read_this) + err=ZIP_ERRNO; + + if (err==ZIP_OK) + err = add_data_in_datablock(&ziinit.central_dir,buf_read, + (uLong)read_this); + size_central_dir_to_read-=read_this; + } + TRYFREE(buf_read); + } + ziinit.begin_pos = byte_before_the_zipfile; + ziinit.number_entry = number_entry_CD; + + if (ZSEEK(ziinit.z_filefunc, ziinit.filestream, + offset_central_dir+byte_before_the_zipfile,ZLIB_FILEFUNC_SEEK_SET)!=0) + err=ZIP_ERRNO; + } + + if (globalcomment) + { + *globalcomment = ziinit.globalcomment; + } +# endif /* !NO_ADDFILEINEXISTINGZIP*/ + + if (err != ZIP_OK) + { +# ifndef NO_ADDFILEINEXISTINGZIP + TRYFREE(ziinit.globalcomment); +# endif /* !NO_ADDFILEINEXISTINGZIP*/ + TRYFREE(zi); + return NULL; + } + else + { + *zi = ziinit; + return (zipFile)zi; + } +} + +extern zipFile ZEXPORT zipOpen (pathname, append) + const char *pathname; + int append; +{ + return zipOpen2(pathname,append,NULL,NULL); +} + +extern int ZEXPORT zipOpenNewFileInZip3 (file, filename, zipfi, + extrafield_local, size_extrafield_local, + extrafield_global, size_extrafield_global, + comment, method, level, raw, + windowBits, memLevel, strategy, + password, crcForCrypting) + zipFile file; + const char* filename; + const zip_fileinfo* zipfi; + const void* extrafield_local; + uInt size_extrafield_local; + const void* extrafield_global; + uInt size_extrafield_global; + const char* comment; + int method; + int level; + int raw; + int windowBits; + int memLevel; + int strategy; + const char* password; + uLong crcForCrypting; +{ + zip_internal* zi; + uInt size_filename; + uInt size_comment; + uInt i; + int err = ZIP_OK; + +# ifdef NOCRYPT + if (password != NULL) + return ZIP_PARAMERROR; +# endif + + if (file == NULL) + return ZIP_PARAMERROR; + if ((method!=0) && (method!=Z_DEFLATED)) + return ZIP_PARAMERROR; + + zi = (zip_internal*)file; + + if (zi->in_opened_file_inzip == 1) + { + err = zipCloseFileInZip (file); + if (err != ZIP_OK) + return err; + } + + + if (filename==NULL) + filename="-"; + + if (comment==NULL) + size_comment = 0; + else + size_comment = (uInt)strlen(comment); + + size_filename = (uInt)strlen(filename); + + if (zipfi == NULL) + zi->ci.dosDate = 0; + else + { + if (zipfi->dosDate != 0) + zi->ci.dosDate = zipfi->dosDate; + else zi->ci.dosDate = ziplocal_TmzDateToDosDate(&zipfi->tmz_date,zipfi->dosDate); + } + + zi->ci.flag = 0; + if ((level==8) || (level==9)) + zi->ci.flag |= 2; + if ((level==2)) + zi->ci.flag |= 4; + if ((level==1)) + zi->ci.flag |= 6; + if (password != NULL) + zi->ci.flag |= 1; + + zi->ci.crc32 = 0; + zi->ci.method = method; + zi->ci.encrypt = 0; + zi->ci.stream_initialised = 0; + zi->ci.pos_in_buffered_data = 0; + zi->ci.raw = raw; + zi->ci.pos_local_header = ZTELL(zi->z_filefunc,zi->filestream) ; + zi->ci.size_centralheader = SIZECENTRALHEADER + size_filename + + size_extrafield_global + size_comment; + zi->ci.central_header = (char*)ALLOC((uInt)zi->ci.size_centralheader); + + ziplocal_putValue_inmemory(zi->ci.central_header,(uLong)CENTRALHEADERMAGIC,4); + /* version info */ + ziplocal_putValue_inmemory(zi->ci.central_header+4,(uLong)VERSIONMADEBY,2); + ziplocal_putValue_inmemory(zi->ci.central_header+6,(uLong)20,2); + ziplocal_putValue_inmemory(zi->ci.central_header+8,(uLong)zi->ci.flag,2); + ziplocal_putValue_inmemory(zi->ci.central_header+10,(uLong)zi->ci.method,2); + ziplocal_putValue_inmemory(zi->ci.central_header+12,(uLong)zi->ci.dosDate,4); + ziplocal_putValue_inmemory(zi->ci.central_header+16,(uLong)0,4); /*crc*/ + ziplocal_putValue_inmemory(zi->ci.central_header+20,(uLong)0,4); /*compr size*/ + ziplocal_putValue_inmemory(zi->ci.central_header+24,(uLong)0,4); /*uncompr size*/ + ziplocal_putValue_inmemory(zi->ci.central_header+28,(uLong)size_filename,2); + ziplocal_putValue_inmemory(zi->ci.central_header+30,(uLong)size_extrafield_global,2); + ziplocal_putValue_inmemory(zi->ci.central_header+32,(uLong)size_comment,2); + ziplocal_putValue_inmemory(zi->ci.central_header+34,(uLong)0,2); /*disk nm start*/ + + if (zipfi==NULL) + ziplocal_putValue_inmemory(zi->ci.central_header+36,(uLong)0,2); + else + ziplocal_putValue_inmemory(zi->ci.central_header+36,(uLong)zipfi->internal_fa,2); + + if (zipfi==NULL) + ziplocal_putValue_inmemory(zi->ci.central_header+38,(uLong)0,4); + else + ziplocal_putValue_inmemory(zi->ci.central_header+38,(uLong)zipfi->external_fa,4); + + ziplocal_putValue_inmemory(zi->ci.central_header+42,(uLong)zi->ci.pos_local_header- zi->add_position_when_writting_offset,4); + + for (i=0;ici.central_header+SIZECENTRALHEADER+i) = *(filename+i); + + for (i=0;ici.central_header+SIZECENTRALHEADER+size_filename+i) = + *(((const char*)extrafield_global)+i); + + for (i=0;ici.central_header+SIZECENTRALHEADER+size_filename+ + size_extrafield_global+i) = *(comment+i); + if (zi->ci.central_header == NULL) + return ZIP_INTERNALERROR; + + + /* write the local header */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)LOCALHEADERMAGIC,4); + + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)20,2);/* version needed to extract */ + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)zi->ci.flag,2); + + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)zi->ci.method,2); + + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)zi->ci.dosDate,4); + + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)0,4); /* crc 32, unknown */ + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)0,4); /* compressed size, unknown */ + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)0,4); /* uncompressed size, unknown */ + + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)size_filename,2); + + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)size_extrafield_local,2); + + if ((err==ZIP_OK) && (size_filename>0)) + if (ZWRITE(zi->z_filefunc,zi->filestream,filename,size_filename)!=size_filename) + err = ZIP_ERRNO; + + if ((err==ZIP_OK) && (size_extrafield_local>0)) + if (ZWRITE(zi->z_filefunc,zi->filestream,extrafield_local,size_extrafield_local) + !=size_extrafield_local) + err = ZIP_ERRNO; + + zi->ci.stream.avail_in = (uInt)0; + zi->ci.stream.avail_out = (uInt)Z_BUFSIZE; + zi->ci.stream.next_out = zi->ci.buffered_data; + zi->ci.stream.total_in = 0; + zi->ci.stream.total_out = 0; + + if ((err==ZIP_OK) && (zi->ci.method == Z_DEFLATED) && (!zi->ci.raw)) + { + zi->ci.stream.zalloc = (alloc_func)0; + zi->ci.stream.zfree = (free_func)0; + zi->ci.stream.opaque = (voidpf)0; + + if (windowBits>0) + windowBits = -windowBits; + + err = deflateInit2(&zi->ci.stream, level, + Z_DEFLATED, windowBits, memLevel, strategy); + + if (err==Z_OK) + zi->ci.stream_initialised = 1; + } +# ifndef NOCRYPT + zi->ci.crypt_header_size = 0; + if ((err==Z_OK) && (password != NULL)) + { + unsigned char bufHead[RAND_HEAD_LEN]; + unsigned int sizeHead; + zi->ci.encrypt = 1; + zi->ci.pcrc_32_tab = get_crc_table(); + /*init_keys(password,zi->ci.keys,zi->ci.pcrc_32_tab);*/ + + sizeHead=crypthead(password,bufHead,RAND_HEAD_LEN,zi->ci.keys,zi->ci.pcrc_32_tab,crcForCrypting); + zi->ci.crypt_header_size = sizeHead; + + if (ZWRITE(zi->z_filefunc,zi->filestream,bufHead,sizeHead) != sizeHead) + err = ZIP_ERRNO; + } +# endif + + if (err==Z_OK) + zi->in_opened_file_inzip = 1; + return err; +} + +extern int ZEXPORT zipOpenNewFileInZip2(file, filename, zipfi, + extrafield_local, size_extrafield_local, + extrafield_global, size_extrafield_global, + comment, method, level, raw) + zipFile file; + const char* filename; + const zip_fileinfo* zipfi; + const void* extrafield_local; + uInt size_extrafield_local; + const void* extrafield_global; + uInt size_extrafield_global; + const char* comment; + int method; + int level; + int raw; +{ + return zipOpenNewFileInZip3 (file, filename, zipfi, + extrafield_local, size_extrafield_local, + extrafield_global, size_extrafield_global, + comment, method, level, raw, + -MAX_WBITS, DEF_MEM_LEVEL, Z_DEFAULT_STRATEGY, + NULL, 0); +} + +extern int ZEXPORT zipOpenNewFileInZip (file, filename, zipfi, + extrafield_local, size_extrafield_local, + extrafield_global, size_extrafield_global, + comment, method, level) + zipFile file; + const char* filename; + const zip_fileinfo* zipfi; + const void* extrafield_local; + uInt size_extrafield_local; + const void* extrafield_global; + uInt size_extrafield_global; + const char* comment; + int method; + int level; +{ + return zipOpenNewFileInZip2 (file, filename, zipfi, + extrafield_local, size_extrafield_local, + extrafield_global, size_extrafield_global, + comment, method, level, 0); +} + +local int zipFlushWriteBuffer(zi) + zip_internal* zi; +{ + int err=ZIP_OK; + + if (zi->ci.encrypt != 0) + { +#ifndef NOCRYPT + uInt i; + int t; + for (i=0;ici.pos_in_buffered_data;i++) + zi->ci.buffered_data[i] = zencode(zi->ci.keys, zi->ci.pcrc_32_tab, + zi->ci.buffered_data[i],t); +#endif + } + if (ZWRITE(zi->z_filefunc,zi->filestream,zi->ci.buffered_data,zi->ci.pos_in_buffered_data) + !=zi->ci.pos_in_buffered_data) + err = ZIP_ERRNO; + zi->ci.pos_in_buffered_data = 0; + return err; +} + +extern int ZEXPORT zipWriteInFileInZip (file, buf, len) + zipFile file; + const void* buf; + unsigned len; +{ + zip_internal* zi; + int err=ZIP_OK; + + if (file == NULL) + return ZIP_PARAMERROR; + zi = (zip_internal*)file; + + if (zi->in_opened_file_inzip == 0) + return ZIP_PARAMERROR; + + zi->ci.stream.next_in = (void*)buf; + zi->ci.stream.avail_in = len; + zi->ci.crc32 = crc32(zi->ci.crc32,buf,len); + + while ((err==ZIP_OK) && (zi->ci.stream.avail_in>0)) + { + if (zi->ci.stream.avail_out == 0) + { + if (zipFlushWriteBuffer(zi) == ZIP_ERRNO) + err = ZIP_ERRNO; + zi->ci.stream.avail_out = (uInt)Z_BUFSIZE; + zi->ci.stream.next_out = zi->ci.buffered_data; + } + + + if(err != ZIP_OK) + break; + + if ((zi->ci.method == Z_DEFLATED) && (!zi->ci.raw)) + { + uLong uTotalOutBefore = zi->ci.stream.total_out; + err=deflate(&zi->ci.stream, Z_NO_FLUSH); + zi->ci.pos_in_buffered_data += (uInt)(zi->ci.stream.total_out - uTotalOutBefore) ; + + } + else + { + uInt copy_this,i; + if (zi->ci.stream.avail_in < zi->ci.stream.avail_out) + copy_this = zi->ci.stream.avail_in; + else + copy_this = zi->ci.stream.avail_out; + for (i=0;ici.stream.next_out)+i) = + *(((const char*)zi->ci.stream.next_in)+i); + { + zi->ci.stream.avail_in -= copy_this; + zi->ci.stream.avail_out-= copy_this; + zi->ci.stream.next_in+= copy_this; + zi->ci.stream.next_out+= copy_this; + zi->ci.stream.total_in+= copy_this; + zi->ci.stream.total_out+= copy_this; + zi->ci.pos_in_buffered_data += copy_this; + } + } + } + return err; +} + +extern int ZEXPORT zipCloseFileInZipRaw (file, uncompressed_size, crc32) + zipFile file; + uLong uncompressed_size; + uLong crc32; +{ + zip_internal* zi; + uLong compressed_size; + int err=ZIP_OK; + if (file == NULL) + return ZIP_PARAMERROR; + zi = (zip_internal*)file; + + if (zi->in_opened_file_inzip == 0) + return ZIP_PARAMERROR; + zi->ci.stream.avail_in = 0; + + if ((zi->ci.method == Z_DEFLATED) && (!zi->ci.raw)) + while (err==ZIP_OK) + { + uLong uTotalOutBefore; + if (zi->ci.stream.avail_out == 0) + { + if (zipFlushWriteBuffer(zi) == ZIP_ERRNO) + err = ZIP_ERRNO; + zi->ci.stream.avail_out = (uInt)Z_BUFSIZE; + zi->ci.stream.next_out = zi->ci.buffered_data; + } + uTotalOutBefore = zi->ci.stream.total_out; + err=deflate(&zi->ci.stream, Z_FINISH); + zi->ci.pos_in_buffered_data += (uInt)(zi->ci.stream.total_out - uTotalOutBefore) ; + } + + if (err==Z_STREAM_END) + err=ZIP_OK; /* this is normal */ + + if ((zi->ci.pos_in_buffered_data>0) && (err==ZIP_OK)) + if (zipFlushWriteBuffer(zi)==ZIP_ERRNO) + err = ZIP_ERRNO; + + if ((zi->ci.method == Z_DEFLATED) && (!zi->ci.raw)) + { + err=deflateEnd(&zi->ci.stream); + zi->ci.stream_initialised = 0; + } + + if (!zi->ci.raw) + { + crc32 = (uLong)zi->ci.crc32; + uncompressed_size = (uLong)zi->ci.stream.total_in; + } + compressed_size = (uLong)zi->ci.stream.total_out; +# ifndef NOCRYPT + compressed_size += zi->ci.crypt_header_size; +# endif + + ziplocal_putValue_inmemory(zi->ci.central_header+16,crc32,4); /*crc*/ + ziplocal_putValue_inmemory(zi->ci.central_header+20, + compressed_size,4); /*compr size*/ + if (zi->ci.stream.data_type == Z_ASCII) + ziplocal_putValue_inmemory(zi->ci.central_header+36,(uLong)Z_ASCII,2); + ziplocal_putValue_inmemory(zi->ci.central_header+24, + uncompressed_size,4); /*uncompr size*/ + + if (err==ZIP_OK) + err = add_data_in_datablock(&zi->central_dir,zi->ci.central_header, + (uLong)zi->ci.size_centralheader); + free(zi->ci.central_header); + + if (err==ZIP_OK) + { + long cur_pos_inzip = ZTELL(zi->z_filefunc,zi->filestream); + if (ZSEEK(zi->z_filefunc,zi->filestream, + zi->ci.pos_local_header + 14,ZLIB_FILEFUNC_SEEK_SET)!=0) + err = ZIP_ERRNO; + + if (err==ZIP_OK) + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,crc32,4); /* crc 32, unknown */ + + if (err==ZIP_OK) /* compressed size, unknown */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,compressed_size,4); + + if (err==ZIP_OK) /* uncompressed size, unknown */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,uncompressed_size,4); + + if (ZSEEK(zi->z_filefunc,zi->filestream, + cur_pos_inzip,ZLIB_FILEFUNC_SEEK_SET)!=0) + err = ZIP_ERRNO; + } + + zi->number_entry ++; + zi->in_opened_file_inzip = 0; + + return err; +} + +extern int ZEXPORT zipCloseFileInZip (file) + zipFile file; +{ + return zipCloseFileInZipRaw (file,0,0); +} + +extern int ZEXPORT zipClose (file, global_comment) + zipFile file; + const char* global_comment; +{ + zip_internal* zi; + int err = 0; + uLong size_centraldir = 0; + uLong centraldir_pos_inzip ; + uInt size_global_comment; + if (file == NULL) + return ZIP_PARAMERROR; + zi = (zip_internal*)file; + + if (zi->in_opened_file_inzip == 1) + { + err = zipCloseFileInZip (file); + } + +#ifndef NO_ADDFILEINEXISTINGZIP + if (global_comment==NULL) + global_comment = zi->globalcomment; +#endif + if (global_comment==NULL) + size_global_comment = 0; + else + size_global_comment = (uInt)strlen(global_comment); + + centraldir_pos_inzip = ZTELL(zi->z_filefunc,zi->filestream); + if (err==ZIP_OK) + { + linkedlist_datablock_internal* ldi = zi->central_dir.first_block ; + while (ldi!=NULL) + { + if ((err==ZIP_OK) && (ldi->filled_in_this_block>0)) + if (ZWRITE(zi->z_filefunc,zi->filestream, + ldi->data,ldi->filled_in_this_block) + !=ldi->filled_in_this_block ) + err = ZIP_ERRNO; + + size_centraldir += ldi->filled_in_this_block; + ldi = ldi->next_datablock; + } + } + free_datablock(zi->central_dir.first_block); + + if (err==ZIP_OK) /* Magic End */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)ENDHEADERMAGIC,4); + + if (err==ZIP_OK) /* number of this disk */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)0,2); + + if (err==ZIP_OK) /* number of the disk with the start of the central directory */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)0,2); + + if (err==ZIP_OK) /* total number of entries in the central dir on this disk */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)zi->number_entry,2); + + if (err==ZIP_OK) /* total number of entries in the central dir */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)zi->number_entry,2); + + if (err==ZIP_OK) /* size of the central directory */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)size_centraldir,4); + + if (err==ZIP_OK) /* offset of start of central directory with respect to the + starting disk number */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream, + (uLong)(centraldir_pos_inzip - zi->add_position_when_writting_offset),4); + + if (err==ZIP_OK) /* zipfile comment length */ + err = ziplocal_putValue(&zi->z_filefunc,zi->filestream,(uLong)size_global_comment,2); + + if ((err==ZIP_OK) && (size_global_comment>0)) + if (ZWRITE(zi->z_filefunc,zi->filestream, + global_comment,size_global_comment) != size_global_comment) + err = ZIP_ERRNO; + + if (ZCLOSE(zi->z_filefunc,zi->filestream) != 0) + if (err == ZIP_OK) + err = ZIP_ERRNO; + +#ifndef NO_ADDFILEINEXISTINGZIP + TRYFREE(zi->globalcomment); +#endif + TRYFREE(zi); + + return err; +} diff --git a/src/zip.h b/src/zip.h new file mode 100644 index 0000000..5fee09b --- /dev/null +++ b/src/zip.h @@ -0,0 +1,237 @@ +/* zip.h -- IO for compress .zip files using zlib + Version 1.01e, February 12th, 2005 + + Copyright (C) 1998-2005 Gilles Vollant + + This unzip package allow creates .ZIP file, compatible with PKZip 2.04g + WinZip, InfoZip tools and compatible. + Multi volume ZipFile (span) are not supported. + Encryption compatible with pkzip 2.04g only supported + Old compressions used by old PKZip 1.x are not supported + + For uncompress .zip file, look at unzip.h + + + I WAIT FEEDBACK at mail info@winimage.com + Visit also http://www.winimage.com/zLibDll/unzip.html for evolution + + Condition of use and distribution are the same than zlib : + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages + arising from the use of this software. + + Permission is granted to anyone to use this software for any purpose, + including commercial applications, and to alter it and redistribute it + freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + 3. This notice may not be removed or altered from any source distribution. + + +*/ + +/* for more info about .ZIP format, see + http://www.info-zip.org/pub/infozip/doc/appnote-981119-iz.zip + http://www.info-zip.org/pub/infozip/doc/ + PkWare has also a specification at : + ftp://ftp.pkware.com/probdesc.zip +*/ + +#ifndef _zip_H +#define _zip_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define NOCRYPT + +#ifndef _ZLIB_H +#include "zlib.h" +#endif + +#ifndef _ZLIBIOAPI_H +#include "ioapi.h" +#endif + +#if defined(STRICTZIP) || defined(STRICTZIPUNZIP) +/* like the STRICT of WIN32, we define a pointer that cannot be converted + from (void*) without cast */ +typedef struct TagzipFile__ { int unused; } zipFile__; +typedef zipFile__ *zipFile; +#else +typedef voidp zipFile; +#endif + +#define ZIP_OK (0) +#define ZIP_EOF (0) +#define ZIP_ERRNO (Z_ERRNO) +#define ZIP_PARAMERROR (-102) +#define ZIP_BADZIPFILE (-103) +#define ZIP_INTERNALERROR (-104) + +#ifndef DEF_MEM_LEVEL +# if MAX_MEM_LEVEL >= 8 +# define DEF_MEM_LEVEL 8 +# else +# define DEF_MEM_LEVEL MAX_MEM_LEVEL +# endif +#endif +/* default memLevel */ + +/* tm_zip contain date/time info */ +typedef struct tm_zip_s +{ + uInt tm_sec; /* seconds after the minute - [0,59] */ + uInt tm_min; /* minutes after the hour - [0,59] */ + uInt tm_hour; /* hours since midnight - [0,23] */ + uInt tm_mday; /* day of the month - [1,31] */ + uInt tm_mon; /* months since January - [0,11] */ + uInt tm_year; /* years - [1980..2044] */ +} tm_zip; + +typedef struct +{ + tm_zip tmz_date; /* date in understandable format */ + uLong dosDate; /* if dos_date == 0, tmu_date is used */ +/* uLong flag; */ /* general purpose bit flag 2 bytes */ + + uLong internal_fa; /* internal file attributes 2 bytes */ + uLong external_fa; /* external file attributes 4 bytes */ +} zip_fileinfo; + +typedef const char* zipcharpc; + + +#define APPEND_STATUS_CREATE (0) +#define APPEND_STATUS_CREATEAFTER (1) +#define APPEND_STATUS_ADDINZIP (2) + +extern zipFile ZEXPORT zipOpen OF((const char *pathname, int append)); +/* + Create a zipfile. + pathname contain on Windows XP a filename like "c:\\zlib\\zlib113.zip" or on + an Unix computer "zlib/zlib113.zip". + if the file pathname exist and append==APPEND_STATUS_CREATEAFTER, the zip + will be created at the end of the file. + (useful if the file contain a self extractor code) + if the file pathname exist and append==APPEND_STATUS_ADDINZIP, we will + add files in existing zip (be sure you don't add file that doesn't exist) + If the zipfile cannot be opened, the return value is NULL. + Else, the return value is a zipFile Handle, usable with other function + of this zip package. +*/ + +/* Note : there is no delete function into a zipfile. + If you want delete file into a zipfile, you must open a zipfile, and create another + Of couse, you can use RAW reading and writing to copy the file you did not want delte +*/ + +extern zipFile ZEXPORT zipOpen2 OF((const char *pathname, + int append, + zipcharpc* globalcomment, + zlib_filefunc_def* pzlib_filefunc_def)); + +extern int ZEXPORT zipOpenNewFileInZip OF((zipFile file, + const char* filename, + const zip_fileinfo* zipfi, + const void* extrafield_local, + uInt size_extrafield_local, + const void* extrafield_global, + uInt size_extrafield_global, + const char* comment, + int method, + int level)); +/* + Open a file in the ZIP for writing. + filename : the filename in zip (if NULL, '-' without quote will be used + *zipfi contain supplemental information + if extrafield_local!=NULL and size_extrafield_local>0, extrafield_local + contains the extrafield data the the local header + if extrafield_global!=NULL and size_extrafield_global>0, extrafield_global + contains the extrafield data the the local header + if comment != NULL, comment contain the comment string + method contain the compression method (0 for store, Z_DEFLATED for deflate) + level contain the level of compression (can be Z_DEFAULT_COMPRESSION) +*/ + + +extern int ZEXPORT zipOpenNewFileInZip2 OF((zipFile file, + const char* filename, + const zip_fileinfo* zipfi, + const void* extrafield_local, + uInt size_extrafield_local, + const void* extrafield_global, + uInt size_extrafield_global, + const char* comment, + int method, + int level, + int raw)); + +/* + Same than zipOpenNewFileInZip, except if raw=1, we write raw file + */ + +extern int ZEXPORT zipOpenNewFileInZip3 OF((zipFile file, + const char* filename, + const zip_fileinfo* zipfi, + const void* extrafield_local, + uInt size_extrafield_local, + const void* extrafield_global, + uInt size_extrafield_global, + const char* comment, + int method, + int level, + int raw, + int windowBits, + int memLevel, + int strategy, + const char* password, + uLong crcForCtypting)); + +/* + Same than zipOpenNewFileInZip2, except + windowBits,memLevel,,strategy : see parameter strategy in deflateInit2 + password : crypting password (NULL for no crypting) + crcForCtypting : crc of file to compress (needed for crypting) + */ + + +extern int ZEXPORT zipWriteInFileInZip OF((zipFile file, + const void* buf, + unsigned len)); +/* + Write data in the zipfile +*/ + +extern int ZEXPORT zipCloseFileInZip OF((zipFile file)); +/* + Close the current file in the zipfile +*/ + +extern int ZEXPORT zipCloseFileInZipRaw OF((zipFile file, + uLong uncompressed_size, + uLong crc32)); +/* + Close the current file in the zipfile, for fiel opened with + parameter raw=1 in zipOpenNewFileInZip2 + uncompressed_size and crc32 are value for the uncompressed size +*/ + +extern int ZEXPORT zipClose OF((zipFile file, + const char* global_comment)); +/* + Close the zipfile +*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _zip_H */ diff --git a/src/zip/do.sh b/src/zip/do.sh new file mode 100644 index 0000000..d368948 --- /dev/null +++ b/src/zip/do.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +FILE=$(date +%Y%m%d-%k%M) +zip -9 pbit-$FILE ../pocketsnes_wiz_fast.gpe -- cgit v1.2.3