From dfa2d3cc68616ddc7e5c5fd1bb9f250fa44cd2fd Mon Sep 17 00:00:00 2001 From: Nebuleon Fumika Date: Tue, 5 Feb 2013 01:33:39 -0500 Subject: Add include files from BassAceGold's library, release 2 fix 2.2. --- sdk-modifications/include/archdefs.h | 2356 +++++++++++++++++++++ sdk-modifications/include/bit_ops.h | 58 + sdk-modifications/include/console.h | 9 + sdk-modifications/include/directory.h | 172 ++ sdk-modifications/include/ds2_cpu.h | 57 + sdk-modifications/include/ds2_cpuclock.h | 21 + sdk-modifications/include/ds2_dma.h | 142 ++ sdk-modifications/include/ds2_excpt.h | 55 + sdk-modifications/include/ds2_fcntl.h | 51 + sdk-modifications/include/ds2_malloc.h | 32 + sdk-modifications/include/ds2_mmc_api.h | 56 + sdk-modifications/include/ds2_timer.h | 50 + sdk-modifications/include/ds2_types.h | 45 + sdk-modifications/include/ds2io.h | 285 +++ sdk-modifications/include/fat.h | 118 ++ sdk-modifications/include/fatdir.h | 81 + sdk-modifications/include/fatdir_ex.h | 18 + sdk-modifications/include/fatfile.h | 89 + sdk-modifications/include/fatfile_ex.h | 19 + sdk-modifications/include/file_allocation_table.h | 64 + sdk-modifications/include/filetime.h | 44 + sdk-modifications/include/fs_api.h | 151 ++ sdk-modifications/include/fs_cache.h | 118 ++ sdk-modifications/include/fs_common.h | 129 ++ sdk-modifications/include/fs_unicode.h | 16 + sdk-modifications/include/mem_allocate.h | 47 + sdk-modifications/include/mips.h | 820 +++++++ sdk-modifications/include/mipsregs.h | 985 +++++++++ sdk-modifications/include/mmc_api.h | 56 + sdk-modifications/include/partition.h | 131 ++ sdk-modifications/include/tcm.h | 10 + 31 files changed, 6285 insertions(+) create mode 100755 sdk-modifications/include/archdefs.h create mode 100755 sdk-modifications/include/bit_ops.h create mode 100755 sdk-modifications/include/console.h create mode 100755 sdk-modifications/include/directory.h create mode 100755 sdk-modifications/include/ds2_cpu.h create mode 100644 sdk-modifications/include/ds2_cpuclock.h create mode 100644 sdk-modifications/include/ds2_dma.h create mode 100755 sdk-modifications/include/ds2_excpt.h create mode 100755 sdk-modifications/include/ds2_fcntl.h create mode 100755 sdk-modifications/include/ds2_malloc.h create mode 100755 sdk-modifications/include/ds2_mmc_api.h create mode 100755 sdk-modifications/include/ds2_timer.h create mode 100755 sdk-modifications/include/ds2_types.h create mode 100755 sdk-modifications/include/ds2io.h create mode 100755 sdk-modifications/include/fat.h create mode 100755 sdk-modifications/include/fatdir.h create mode 100755 sdk-modifications/include/fatdir_ex.h create mode 100755 sdk-modifications/include/fatfile.h create mode 100755 sdk-modifications/include/fatfile_ex.h create mode 100755 sdk-modifications/include/file_allocation_table.h create mode 100755 sdk-modifications/include/filetime.h create mode 100755 sdk-modifications/include/fs_api.h create mode 100755 sdk-modifications/include/fs_cache.h create mode 100755 sdk-modifications/include/fs_common.h create mode 100755 sdk-modifications/include/fs_unicode.h create mode 100755 sdk-modifications/include/mem_allocate.h create mode 100755 sdk-modifications/include/mips.h create mode 100755 sdk-modifications/include/mipsregs.h create mode 100755 sdk-modifications/include/mmc_api.h create mode 100755 sdk-modifications/include/partition.h create mode 100755 sdk-modifications/include/tcm.h (limited to 'sdk-modifications/include') diff --git a/sdk-modifications/include/archdefs.h b/sdk-modifications/include/archdefs.h new file mode 100755 index 0000000..37c61b8 --- /dev/null +++ b/sdk-modifications/include/archdefs.h @@ -0,0 +1,2356 @@ +/************************************************************************** +* * +* PROJECT : MIPS port for uC/OS-II * +* * +* MODULE : ARCHDEFS.h * +* * +* AUTHOR : Michael Anburaj * +* URL : http://geocities.com/michaelanburaj/ * +* EMAIL: michaelanburaj@hotmail.com * +* * +* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board * +* * +* TOOL-CHAIN : SDE & Cygnus * +* * +* DESCRIPTION : * +* Architecture definitions. * +* * +**************************************************************************/ + + +#ifndef __ARCHDEFS_H__ +#define __ARCHDEFS_H__ + + +/* ********************************************************************* */ +/* Module configuration */ + + +/* ********************************************************************* */ +/* Interface macro & data definition */ + +/* + * Utility defines for cross platform handling of 64bit constants. + */ + +#if !defined(Append) + #define Append(c,s) (c##s) +#endif + +#if !defined(__assembler) && !defined(MIPSAVPENV) + #if defined(NT) + #if !defined(UNS64Const) + #define UNS64Const(c) Append(c,ui64) + #endif + + #if !defined(INT64Const) + #define INT64Const(c) Append(c,i64) + #endif + #else + #if !defined(UNS64Const) + #define UNS64Const(c) Append(c,ull) + #endif + + #if !defined(INT64Const) + #define INT64Const(c) Append(c,ll) + #endif + #endif +#else /* Not C or C++ */ + #if !defined(UNS64Const) + #define UNS64Const(c) c + #endif + + #if !defined(INT64Const) + #define INT64Const(c) c + #endif +#endif /* C or C++ */ + + +/* + ************************************************************************ + * I N S T R U C T I O N F O R M A T S * + ************************************************************************ + * + * The following definitions describe each field in an instruction. There + * is one diagram for each type of instruction, with field definitions + * following the diagram for that instruction. Note that if a field of + * the same name and position is defined in an earlier diagram, it is + * not defined again in the subsequent diagram. Only new fields are + * defined for each diagram. + * + * R-Type (operate) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | rs | rt | rd | sa | | + * | Opcode | | | Tcode | func | + * | | Bcode | | sel | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnOpcode 26 +#define M_InstnOpcode (0x3f << S_InstnOpcode) +#define S_InstnRS 21 +#define M_InstnRS (0x1f << S_InstnRS) +#define S_InstnRT 16 +#define M_InstnRT (0x1f << S_InstnRT) +#define S_InstnRD 11 +#define M_InstnRD (0x1f << S_InstnRD) +#define S_InstnSA 6 +#define M_InstnSA (0x1f << S_InstnSA) +#define S_InstnTcode 6 +#define M_InstnTcode (0x3ff << S_InstnTcode) +#define S_InstnBcode 6 +#define M_InstnBcode (0xfffff << S_InstnBcode) +#define S_InstnFunc 0 +#define M_InstnFunc (0x3f << S_InstnFunc) +#define S_InstnSel 0 +#define M_InstnSel (0x7 << S_InstnSel) + +/* + * I-Type (load, store, branch, immediate) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | rt | Offset | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnOffset 0 +#define M_InstnOffset (0xffff << S_InstnOffset) + +/* + * I-Type (pref) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | hint | Offset | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnHint S_InstnRT +#define M_InstnHint M_InstnRT + +/* + * J-Type (jump) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | JIndex | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnJIndex 0 +#define M_InstnJIndex (0x03ffffff << S_InstnJIndex) + +/* + * FP R-Type (operate) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | fmt | ft | fs | fd | func | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnFmt S_InstnRS +#define M_InstnFmt M_InstnRS +#define S_InstnFT S_InstnRT +#define M_InstnFT M_InstnRT +#define S_InstnFS S_InstnRD +#define M_InstnFS M_InstnRD +#define S_InstnFD S_InstnSA +#define M_InstnFD M_InstnSA + +/* + * FP R-Type (cpu <-> cpu data movement)) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | sub | rt | fs | 0 | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnSub S_InstnRS +#define M_InstnSub M_InstnRS + +/* + * FP R-Type (compare) + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | | | | |C| | + * | Opcode | fmt | ft | fs | cc |0|A| func | + * | | | | | | |B| | + * | | | | | | |S| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnCCcmp 8 +#define M_InstnCCcmp (0x7 << S_InstnCCcmp) +#define S_InstnCABS 6 +#define M_InstnCABS (0x1 << S_InstnCABS) + +/* + * FP R-Type (FPR conditional move on FP cc) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | fmt | cc |n|t| fs | fd | func | + * | | | |d|f| | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnCC 18 +#define M_InstnCC (0x7 << S_InstnCC) +#define S_InstnND 17 +#define M_InstnND (0x1 << S_InstnND) +#define S_InstnTF 16 +#define M_InstnTF (0x1 << S_InstnTF) + +/* + * FP R-Type (3-operand operate) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | fr | ft | fs | fd | op4 | fmt3| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnFR S_InstnRS +#define M_InstnFR M_InstnRS +#define S_InstnOp4 3 +#define M_InstnOp4 (0x7 << S_InstnOp4) +#define S_InstnFmt3 0 +#define M_InstnFmt3 (0x7 << S_InstnFmt3) + +/* + * FP R-Type (Indexed load, store) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | rt | 0 | fd | func | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ +/* + * FP R-Type (prefx) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | rt | hint | 0 | func | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define S_InstnHintX S_InstnRD +#define M_InstnHintX M_InstnRD + +/* + * FP R-Type (GPR conditional move on FP cc) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | cc |n|t| rd | 0 | func | + * | | | |d|f| | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +/* + * FP I-Type (load, store) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | rs | ft | Offset | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +/* + * FP I-Type (branch) + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Opcode | fmt | cc |n|t| Offset | + * | | | |d|f| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + + +/* + ************************************************************************* + * V I R T U A L A D D R E S S D E F I N I T I O N S * + ************************************************************************* + */ + +#ifdef MIPSADDR64 +#define A_K0BASE UNS64Const(0xffffffff80000000) +#define A_K1BASE UNS64Const(0xffffffffa0000000) +#define A_K2BASE UNS64Const(0xffffffffc0000000) +#define A_K3BASE UNS64Const(0xffffffffe0000000) +#define A_REGION UNS64Const(0xc000000000000000) +#define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) +#else +#define A_K0BASE 0x80000000 +#define A_K1BASE 0xa0000000 +#define A_K2BASE 0xc0000000 +#define A_K3BASE 0xe0000000 +#endif +#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ + + +#ifdef MIPS_Model64 + +#define S_VMAP64 62 +#define M_VMAP64 UNS64Const(0xc000000000000000) + +#define K_VMode11 3 +#define K_VMode10 2 +#define K_VMode01 1 +#define K_VMode00 0 + +#define S_KSEG3 29 +#define M_KSEG3 (0x7 << S_KSEG3) +#define K_KSEG3 7 + +#define S_SSEG 29 +#define M_SSEG (0x7 << S_KSEG3) +#define K_SSEG 6 + +#define S_KSSEG 29 +#define M_KSSEG (0x7 << S_KSEG3) +#define K_KSSEG 6 + +#define S_KSEG1 29 +#define M_KSEG1 (0x7 << S_KSEG3) +#define K_KSEG1 5 + +#define S_KSEG0 29 +#define M_KSEG0 (0x7 << S_KSEG3) +#define K_KSEG0 4 + +#define S_XKSEG 29 +#define M_XKSEG (0x7 << S_KSEG3) +#define K_XKSEG 3 + +#define S_USEG 31 +#define M_USEG (0x1 << S_USEG) +#define K_USEG 0 + +#define S_EjtagProbeMem 20 +#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) +#define K_EjtagProbeMem 0 + + + +#else + +#define S_KSEG3 29 +#define M_KSEG3 (0x7 << S_KSEG3) +#define K_KSEG3 7 + +#define S_KSSEG 29 +#define M_KSSEG (0x7 << S_KSSEG) +#define K_KSSEG 6 + +#define S_SSEG 29 +#define M_SSEG (0x7 << S_SSEG) +#define K_SSEG 6 + +#define S_KSEG1 29 +#define M_KSEG1 (0x7 << S_KSEG1) +#define K_KSEG1 5 + +#define S_KSEG0 29 +#define M_KSEG0 (0x7 << S_KSEG0) +#define K_KSEG0 4 + +#define S_KUSEG 31 +#define M_KUSEG (0x1 << S_KUSEG) +#define K_KUSEG 0 + +#define S_SUSEG 31 +#define M_SUSEG (0x1 << S_SUSEG) +#define K_SUSEG 0 + +#define S_USEG 31 +#define M_USEG (0x1 << S_USEG) +#define K_USEG 0 + +#define K_EjtagLower 0xff200000 +#define K_EjtagUpper 0xff3fffff + +#define S_EjtagProbeMem 20 +#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) +#define K_EjtagProbeMem 0 + +#endif + + + +/* + ************************************************************************* + * C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S * + ************************************************************************* + */ + +/* + * Cache encodings + */ +#define K_CachePriI 0 /* Primary Icache */ +#define K_CachePriD 1 /* Primary Dcache */ +#define K_CachePriU 1 /* Unified primary */ +#define K_CacheTerU 2 /* Unified Tertiary */ +#define K_CacheSecU 3 /* Unified secondary */ + + +/* + * Function encodings + */ +#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ +#define K_CacheIndexInv 0 /* Index invalidate */ +#define K_CacheIndexWBInv 0 /* Index writeback invalidate */ +#define K_CacheIndexLdTag 1 /* Index load tag */ +#define K_CacheIndexStTag 2 /* Index store tag */ +#define K_CacheHitInv 4 /* Hit Invalidate */ +#define K_CacheFill 5 /* Fill (Icache only) */ +#define K_CacheHitWBInv 5 /* Hit writeback invalidate */ +#define K_CacheHitWB 6 /* Hit writeback */ +#define K_CacheFetchLock 7 /* Fetch and lock */ + +#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) +#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) +#define DCIndexInv DCIndexWBInv +#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) +#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) +#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) +#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) +#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) +#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) +#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) +#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) +#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) +#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) +#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) + + +/* + ************************************************************************* + * P R E F E T C H I N S T R U C T I O N H I N T S * + ************************************************************************* + */ + +#define PrefLoad 0 +#define PrefStore 1 +#define PrefLoadStreamed 4 +#define PrefStoreStreamed 5 +#define PrefLoadRetained 6 +#define PrefStoreRetained 7 +#define PrefWBInval 25 +#define PrefNudge 25 + + +/* + ************************************************************************* + * C P U R E G I S T E R D E F I N I T I O N S * + ************************************************************************* + */ + + +/* + ************************************************************************* + * S O F T W A R E G P R N A M E S * + ************************************************************************* + */ + +#define zero $0 +#define AT $1 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 +#define k1 $27 +#define gp $28 +#define sp $29 +#define fp $30 +#define ra $31 + +/* + * The following registers are used by the AVP environment and + * are not part of the normal software definitions. + */ + +#ifdef MIPSAVPENV +#define repc $25 /* Expected exception PC */ +#define tid $30 /* Current test case address */ +#endif + + +/* + ************************************************************************* + * H A R D W A R E G P R N A M E S * + ************************************************************************* + * + * In the AVP environment, several of the `r' names are removed from the + * name space because they are used by the kernel for special purposes. + * Removing them causes assembly rather than runtime errors for tests that + * use the `r' names. + * + * - r25 (repc) is used as the expected PC on an exception + * - r26-r27 (k0, k1) are used in the exception handler + * - r30 (tid) is used as the current test address + */ + +#define r0 $0 +#define r1 $1 +#define r2 $2 +#define r3 $3 +#define r4 $4 +#define r5 $5 +#define r6 $6 +#define r7 $7 +#define r8 $8 +#define r9 $9 +#define r10 $10 +#define r11 $11 +#define r12 $12 +#define r13 $13 +#define r14 $14 +#define r15 $15 +#define r16 $16 +#define r17 $17 +#define r18 $18 +#define r19 $19 +#define r20 $20 +#define r21 $21 +#define r22 $22 +#define r23 $23 +#define r24 $24 +#ifdef MIPSAVPENV +#define r25 r25_unknown +#define r26 r26_unknown +#define r27 r27_unknown +#else +#define r25 $25 +#define r26 $26 +#define r27 $27 +#endif +#define r28 $28 +#define r29 $29 +#ifdef MIPSAVPENV +#define r30 r30_unknown +#else +#define r30 $30 +#endif +#define r31 $31 + + +/* + ************************************************************************* + * H A R D W A R E G P R I N D I C E S * + ************************************************************************* + * + * These definitions provide the index (number) of the GPR, as opposed + * to the assembler register name ($n). + */ + +#define R_r0 0 +#define R_r1 1 +#define R_r2 2 +#define R_r3 3 +#define R_r4 4 +#define R_r5 5 +#define R_r6 6 +#define R_r7 7 +#define R_r8 8 +#define R_r9 9 +#define R_r10 10 +#define R_r11 11 +#define R_r12 12 +#define R_r13 13 +#define R_r14 14 +#define R_r15 15 +#define R_r16 16 +#define R_r17 17 +#define R_r18 18 +#define R_r19 19 +#define R_r20 20 +#define R_r21 21 +#define R_r22 22 +#define R_r23 23 +#define R_r24 24 +#define R_r25 25 +#define R_r26 26 +#define R_r27 27 +#define R_r28 28 +#define R_r29 29 +#define R_r30 30 +#define R_r31 31 +#define R_hi 32 /* Hi register */ +#define R_lo 33 /* Lo register */ + + +/* + ************************************************************************* + * S O F T W A R E G P R M A S K S * + ************************************************************************* + * + * These definitions provide the bit mask corresponding to the GPR number + */ + +#define M_AT (1<<1) +#define M_v0 (1<<2) +#define M_v1 (1<<3) +#define M_a0 (1<<4) +#define M_a1 (1<<5) +#define M_a2 (1<<6) +#define M_a3 (1<<7) +#define M_t0 (1<<8) +#define M_t1 (1<<9) +#define M_t2 (1<<10) +#define M_t3 (1<<11) +#define M_t4 (1<<12) +#define M_t5 (1<<13) +#define M_t6 (1<<14) +#define M_t7 (1<<15) +#define M_s0 (1<<16) +#define M_s1 (1<<17) +#define M_s2 (1<<18) +#define M_s3 (1<<19) +#define M_s4 (1<<20) +#define M_s5 (1<<21) +#define M_s6 (1<<22) +#define M_s7 (1<<23) +#define M_t8 (1<<24) +#define M_t9 (1<<25) +#define M_k0 (1<<26) +#define M_k1 (1<<27) +#define M_gp (1<<28) +#define M_sp (1<<29) +#define M_fp (1<<30) +#define M_ra (1<<31) + + +/* + ************************************************************************* + * C P 0 R E G I S T E R D E F I N I T I O N S * + ************************************************************************* + * Each register has the following definitions: + * + * C0_rrr The register number (as a $n value) + * R_C0_rrr The register index (as an integer corresponding + * to the register number) + * + * Each field in a register has the following definitions: + * + * S_rrrfff The shift count required to right-justify + * the field. This corresponds to the bit + * number of the right-most bit in the field. + * M_rrrfff The Mask required to isolate the field. + * + * Register diagrams included below as comments correspond to the + * MIPS32 and MIPS64 architecture specifications. Refer to other + * sources for register diagrams for older architectures. + */ + + +/* + ************************************************************************ + * I N D E X R E G I S T E R ( 0 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |P| 0 | Index | Index + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Index $0 +#define R_C0_Index 0 +#define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_IndexP 31 /* Probe failure (R)*/ +#define M_IndexP (0x1 << S_IndexP) + +#define S_IndexIndex 0 /* TLB index (R/W)*/ +#define M_IndexIndex (0x3f << S_IndexIndex) + +#define M_Index0Fields 0x7fffffc0 +#define M_IndexRFields 0x80000000 + + +/* + ************************************************************************ + * R A N D O M R E G I S T E R ( 1 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Index | Random + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Random $1 +#define R_C0_Random 1 +#define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_RandomIndex 0 /* TLB random index (R)*/ +#define M_RandomIndex (0x3f << S_RandomIndex) + +#define M_Random0Fields 0xffffffc0 +#define M_RandomRFields 0x0000003f + + +/* + ************************************************************************ + * E N T R Y L O 0 R E G I S T E R ( 2 ) * + ************************************************************************ + * + * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo0 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_EntryLo0 $2 +#define R_C0_EntryLo0 2 +#define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_EntryLoPFN 6 /* PFN (R/W) */ +#define M_EntryLoPFN (0xffffff << S_EntryLoPFN) +#define S_EntryLoC 3 /* Coherency attribute (R/W) */ +#define M_EntryLoC (0x7 << S_EntryLoC) +#define S_EntryLoD 2 /* Dirty (R/W) */ +#define M_EntryLoD (0x1 << S_EntryLoD) +#define S_EntryLoV 1 /* Valid (R/W) */ +#define M_EntryLoV (0x1 << S_EntryLoV) +#define S_EntryLoG 0 /* Global (R/W) */ +#define M_EntryLoG (0x1 << S_EntryLoG) +#define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ +#define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ +#define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ + +#define M_EntryLo0Fields 0x00000000 +#define M_EntryLoRFields 0xc0000000 +#define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) +#define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) + +/* + * Cache attribute values in the C field of EntryLo and the + * K0 field of Config + */ +#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ +#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ +#define K_CacheAttrU 2 /* Uncached */ +#define K_CacheAttrC 3 /* Cacheable */ +#define K_CacheAttrCN 3 /* Cacheable, non-coherent */ +#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ +#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ +#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ +#define K_CacheAttrUA 7 /* Uncached accelerated */ + + +/* + ************************************************************************ + * E N T R Y L O 1 R E G I S T E R ( 3 ) * + ************************************************************************ + * + * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo1 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_EntryLo1 $3 +#define R_C0_EntryLo1 3 +#define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ + +/* + * Field definitions are as given for EntryLo0 above + */ + + +/* + ************************************************************************ + * C O N T E X T R E G I S T E R ( 4 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // PTEBase | BadVPN<31:13> | 0 | Context + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Context $4 +#define R_C0_Context 4 +#define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_ContextPTEBase 23 /* PTE base (R/W) */ +#define M_ContextPTEBase (0x1ff << S_ContextPTEBase) +#define S_ContextBadVPN 4 /* BadVPN2 (R) */ +#define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) +#define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ +#define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ + +#define M_Context0Fields 0x0000000f +#define M_ContextRFields 0x007ffff0 +#define M_Context0Fields64 UNS64Const(0x000000000000000f) +#define M_ContextRFields64 UNS64Const(0x00000000007ffff0) + + +/* + ************************************************************************ + * P A G E M A S K R E G I S T E R ( 5 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Mask | 0 | PageMask + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_PageMask $5 +#define R_C0_PageMask 5 /* Mask (R/W) */ +#define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_PageMaskMask 13 +#define M_PageMaskMask (0xfff << S_PageMaskMask) + +#define M_PageMask0Fields 0xfe001fff +#define M_PageMaskRFields 0x00000000 + +/* + * Values in the Mask field + */ +#define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ +#define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ +#define K_PageMask64K 0x00f +#define K_PageMask256K 0x03f +#define K_PageMask1M 0x0ff +#define K_PageMask4M 0x3ff +#define K_PageMask16M 0xfff + +#define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ +#define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ +#define M_PageMask64K (K_PageMask64K << S_PageMaskMask) +#define M_PageMask256K (K_PageMask256K << S_PageMaskMask) +#define M_PageMask1M (K_PageMask1M << S_PageMaskMask) +#define M_PageMask4M (K_PageMask4M << S_PageMaskMask) +#define M_PageMask16M (K_PageMask16M << S_PageMaskMask) + + +/* + ************************************************************************ + * W I R E D R E G I S T E R ( 6 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Index | Wired + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Wired $6 +#define R_C0_Wired 6 +#define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_WiredIndex 0 /* TLB wired boundary (R/W) */ +#define M_WiredIndex (0x3f << S_WiredIndex) + +#define M_Wired0Fields 0xffffffc0 +#define M_WiredRFields 0x00000000 + + +/* + ************************************************************************ + * B A D V A D D R R E G I S T E R ( 8 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // Bad Virtual Address | BadVAddr + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_BadVAddr $8 +#define R_C0_BadVAddr 8 +#define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ + +#define M_BadVAddr0Fields 0x00000000 +#define M_BadVAddrRFields 0xffffffff +#define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) +#define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) + +/* + ************************************************************************ + * C O U N T R E G I S T E R ( 9 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Count Value | Count + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Count $9 +#define R_C0_Count 9 +#define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_Count0Fields 0x00000000 +#define M_CountRFields 0x00000000 + + +/* + ************************************************************************ + * E N T R Y H I R E G I S T E R ( 1 0 ) * + ************************************************************************ + * + * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | R | Fill // VPN2 | 0 | ASID | EntryHi + * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_EntryHi $10 +#define R_C0_EntryHi 10 +#define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_EntryHiR64 62 /* Region (R/W) */ +#define M_EntryHiR64 UNS64Const(0xc000000000000000) +#define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ +#define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) +#define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) +#define S_EntryHiASID 0 /* ASID (R/W) */ +#define M_EntryHiASID (0xff << S_EntryHiASID) +#define S_EntryHiVPN_Shf S_EntryHiVPN2 + +#define M_EntryHi0Fields 0x00001f00 +#define M_EntryHiRFields 0x00000000 +#define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) +#define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) + + +/* + ************************************************************************ + * C O M P A R E R E G I S T E R ( 1 1 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Compare Value | Compare + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Compare $11 +#define R_C0_Compare 11 +#define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_Compare0Fields 0x00000000 +#define M_CompareRFields 0x00000000 + + +/* + ************************************************************************ + * S T A T U S R E G I S T E R ( 1 2 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I| + * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status + * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Status $12 +#define R_C0_Status 12 +#define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_StatusCU 28 /* Coprocessor enable (R/W) */ +#define M_StatusCU (0xf << S_StatusCU) +#define S_StatusCU3 31 +#define M_StatusCU3 (0x1 << S_StatusCU3) +#define S_StatusCU2 30 +#define M_StatusCU2 (0x1 << S_StatusCU2) +#define S_StatusCU1 29 +#define M_StatusCU1 (0x1 << S_StatusCU1) +#define S_StatusCU0 28 +#define M_StatusCU0 (0x1 << S_StatusCU0) +#define S_StatusRP 27 /* Enable reduced power mode (R/W) */ +#define M_StatusRP (0x1 << S_StatusRP) +#define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ +#define M_StatusFR (0x1 << S_StatusFR) +#define S_StatusRE 25 /* Enable reverse endian (R/W) */ +#define M_StatusRE (0x1 << S_StatusRE) +#define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ +#define M_StatusMX (0x1 << S_StatusMX) +#define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ +#define M_StatusPX (0x1 << S_StatusPX) +#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ +#define M_StatusBEV (0x1 << S_StatusBEV) +#define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ +#define M_StatusTS (0x1 << S_StatusTS) +#define S_StatusSR 20 /* Denote soft reset (R/W) */ +#define M_StatusSR (0x1 << S_StatusSR) +#define S_StatusNMI 19 +#define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ +#define S_StatusIM 8 /* Interrupt mask (R/W) */ +#define M_StatusIM (0xff << S_StatusIM) +#define S_StatusIM7 15 +#define M_StatusIM7 (0x1 << S_StatusIM7) +#define S_StatusIM6 14 +#define M_StatusIM6 (0x1 << S_StatusIM6) +#define S_StatusIM5 13 +#define M_StatusIM5 (0x1 << S_StatusIM5) +#define S_StatusIM4 12 +#define M_StatusIM4 (0x1 << S_StatusIM4) +#define S_StatusIM3 11 +#define M_StatusIM3 (0x1 << S_StatusIM3) +#define S_StatusIM2 10 +#define M_StatusIM2 (0x1 << S_StatusIM2) +#define S_StatusIM1 9 +#define M_StatusIM1 (0x1 << S_StatusIM1) +#define S_StatusIM0 8 +#define M_StatusIM0 (0x1 << S_StatusIM0) +#define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ +#define M_StatusKX (0x1 << S_StatusKX) +#define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ +#define M_StatusSX (0x1 << S_StatusSX) +#define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ +#define M_StatusUX (0x1 << S_StatusUX) +#define S_StatusKSU 3 /* Two-bit current mode (R/W) */ +#define M_StatusKSU (0x3 << S_StatusKSU) +#define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ +#define M_StatusUM (0x1 << S_StatusUM) +#define S_StatusSM 3 /* Supervisor mode (R/W) */ +#define M_StatusSM (0x1 << S_StatusSM) +#define S_StatusERL 2 /* Denotes error level (R/W) */ +#define M_StatusERL (0x1 << S_StatusERL) +#define S_StatusEXL 1 /* Denotes exception level (R/W) */ +#define M_StatusEXL (0x1 << S_StatusEXL) +#define S_StatusIE 0 /* Enables interrupts (R/W) */ +#define M_StatusIE (0x1 << S_StatusIE) + +#define M_Status0Fields 0x00040000 +#define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ +#define M_Status0Fields64 0x00040000 +#define M_StatusRFields64 0x00000000 + +/* + * Values in the KSU field + */ +#define K_StatusKSU_U 2 /* User mode in KSU field */ +#define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ +#define K_StatusKSU_K 0 /* Kernel mode in KSU field */ + + +/* + ************************************************************************ + * C A U S E R E G I S T E R ( 1 3 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |B| | C | |I|W| |I|I|I|I|I|I|I|I| | | R | + * |D| | E | Rsvd |V|P| Rsvd |P|P|P|P|P|P|P|P| | ExcCode | s | Cause + * | | | | | | | |7|6|5|4|3|2|1|0| | | v | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Cause $13 +#define R_C0_Cause 13 +#define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_CauseBD 31 +#define M_CauseBD (0x1 << S_CauseBD) +#define S_CauseCE 28 +#define M_CauseCE (0x3<< S_CauseCE) +#define S_CauseIV 23 +#define M_CauseIV (0x1 << S_CauseIV) +#define S_CauseWP 22 +#define M_CauseWP (0x1 << S_CauseWP) +#define S_CauseIP 8 +#define M_CauseIP (0xff << S_CauseIP) +#define S_CauseIPEXT 10 +#define M_CauseIPEXT (0x3f << S_CauseIPEXT) +#define S_CauseIP7 15 +#define M_CauseIP7 (0x1 << S_CauseIP7) +#define S_CauseIP6 14 +#define M_CauseIP6 (0x1 << S_CauseIP6) +#define S_CauseIP5 13 +#define M_CauseIP5 (0x1 << S_CauseIP5) +#define S_CauseIP4 12 +#define M_CauseIP4 (0x1 << S_CauseIP4) +#define S_CauseIP3 11 +#define M_CauseIP3 (0x1 << S_CauseIP3) +#define S_CauseIP2 10 +#define M_CauseIP2 (0x1 << S_CauseIP2) +#define S_CauseIP1 9 +#define M_CauseIP1 (0x1 << S_CauseIP1) +#define S_CauseIP0 8 +#define M_CauseIP0 (0x1 << S_CauseIP0) +#define S_CauseExcCode 2 +#define M_CauseExcCode (0x1f << S_CauseExcCode) + +#define M_Cause0Fields 0x4f3f0083 +#define M_CauseRFields 0xb000fc7c + +/* + * Values in the CE field + */ +#define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ +#define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ +#define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ +#define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ + +/* + * Values in the ExcCode field + */ +#define EX_INT 0 /* Interrupt */ +#define EXC_INT (EX_INT << S_CauseExcCode) +#define EX_MOD 1 /* TLB modified */ +#define EXC_MOD (EX_MOD << S_CauseExcCode) +#define EX_TLBL 2 /* TLB exception (load or ifetch) */ +#define EXC_TLBL (EX_TLBL << S_CauseExcCode) +#define EX_TLBS 3 /* TLB exception (store) */ +#define EXC_TLBS (EX_TLBS << S_CauseExcCode) +#define EX_ADEL 4 /* Address error (load or ifetch) */ +#define EXC_ADEL (EX_ADEL << S_CauseExcCode) +#define EX_ADES 5 /* Address error (store) */ +#define EXC_ADES (EX_ADES << S_CauseExcCode) +#define EX_IBE 6 /* Instruction Bus Error */ +#define EXC_IBE (EX_IBE << S_CauseExcCode) +#define EX_DBE 7 /* Data Bus Error */ +#define EXC_DBE (EX_DBE << S_CauseExcCode) +#define EX_SYS 8 /* Syscall */ +#define EXC_SYS (EX_SYS << S_CauseExcCode) +#define EX_SYSCALL EX_SYS +#define EXC_SYSCALL EXC_SYS +#define EX_BP 9 /* Breakpoint */ +#define EXC_BP (EX_BP << S_CauseExcCode) +#define EX_BREAK EX_BP +#define EXC_BREAK EXC_BP +#define EX_RI 10 /* Reserved instruction */ +#define EXC_RI (EX_RI << S_CauseExcCode) +#define EX_CPU 11 /* CoProcessor Unusable */ +#define EXC_CPU (EX_CPU << S_CauseExcCode) +#define EX_OV 12 /* OVerflow */ +#define EXC_OV (EX_OV << S_CauseExcCode) +#define EX_TR 13 /* Trap instruction */ +#define EXC_TR (EX_TR << S_CauseExcCode) +#define EX_TRAP EX_TR +#define EXC_TRAP EXC_TR +#define EX_FPE 15 /* floating point exception */ +#define EXC_FPE (EX_FPE << S_CauseExcCode) +#define EX_C2E 18 /* COP2 exception */ +#define EXC_C2E (EX_C2E << S_CauseExcCode) +#define EX_MDMX 22 /* MDMX exception */ +#define EXC_MDMX (EX_MDMX << S_CauseExcCode) +#define EX_WATCH 23 /* Watch exception */ +#define EXC_WATCH (EX_WATCH << S_CauseExcCode) +#define EX_MCHECK 24 /* Machine check exception */ +#define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) +#define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ +#define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) + + +/* + ************************************************************************ + * E P C R E G I S T E R ( 1 4 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // Exception PC | EPC + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_EPC $14 +#define R_C0_EPC 14 + +#define M_EPC0Fields 0x00000000 +#define M_EPCRFields 0x00000000 +#define M_EPC0Fields64 UNS64Const(0x0000000000000000) +#define M_EPCRFields64 UNS64Const(0x0000000000000000) + +/* + ************************************************************************ + * P R I D R E G I S T E R ( 1 5 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Company Opts | Company ID | Procesor ID | Revision | PRId + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_PRId $15 +#define R_C0_PRId 15 +#define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_PRIdCoOpt 24 /* Company options (R) */ +#define M_PRIdCoOpt (0xff << S_PRIdCoOpt) +#define S_PRIdCoID 16 /* Company ID (R) */ +#define M_PRIdCoID (0xff << S_PRIdCoID) +#define S_PRIdImp 8 /* Implementation ID (R) */ +#define M_PRIdImp (0xff << S_PRIdImp) +#define S_PRIdRev 0 /* Revision (R) */ +#define M_PRIdRev (0xff << S_PRIdRev) + +#define M_PRId0Fields 0x00000000 +#define M_PRIdRFields 0xffffffff +/* + * Values in the Company ID field + */ +#define K_PRIdCoID_MIPS 1 +#define K_PRIdCoID_Broadcom 2 +#define K_PRIdCoID_Alchemy 3 +#define K_PRIdCoID_SiByte 4 +#define K_PRIdCoID_SandCraft 5 +#define K_PRIdCoID_Philips 6 +#define K_PRIdCoID_NextAvailable 7 /* Next available encoding */ + + +/* + * Values in the implementation number field + */ +#define K_PRIdImp_Jade 0x80 +#define K_PRIdImp_Opal 0x81 +#define K_PRIdImp_Ruby 0x82 +#define K_PRIdImp_JadeLite 0x83 +#define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ +#define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ +#define K_PRIdImp_4KSc 0x86 /* Coral */ + +#define K_PRIdImp_R3000 0x01 +#define K_PRIdImp_R4000 0x04 +#define K_PRIdImp_R10000 0x09 +#define K_PRIdImp_R4300 0x0b +#define K_PRIdImp_R5000 0x23 +#define K_PRIdImp_R5200 0x28 +#define K_PRIdImp_R5400 0x54 + +/* + ************************************************************************ + * C O N F I G R E G I S T E R ( 1 6 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |M| |B| A | A | | K | Config + * | | Reserved for Implementations|E| T | R | Reserved | 0 | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Config $16 +#define R_C0_Config 16 +#define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_ConfigMore 31 /* Additional config registers present (R) */ +#define M_ConfigMore (0x1 << S_ConfigMore) +#define S_ConfigImpl 16 /* Implementation-specific fields */ +#define M_ConfigImpl (0x7fff << S_ConfigImpl) +#define S_ConfigBE 15 /* Denotes big-endian operation (R) */ +#define M_ConfigBE (0x1 << S_ConfigBE) +#define S_ConfigAT 13 /* Architecture type (R) */ +#define M_ConfigAT (0x3 << S_ConfigAT) +#define S_ConfigAR 10 /* Architecture revision (R) */ +#define M_ConfigAR (0x7 << S_ConfigAR) +#define S_ConfigMT 7 /* MMU Type (R) */ +#define M_ConfigMT (0x7 << S_ConfigMT) +#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ +#define M_ConfigK0 (0x7 << S_ConfigK0) + +/* + * The following definitions are technically part of the "reserved for + * implementations" field, but are the semi-standard definition used in + * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3 + * references. For that reason, they are included here, but may be + * overridden by true implementation-specific definitions + */ +#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ +#define M_ConfigK23 (0x7 << S_ConfigK23) +#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ +#define M_ConfigKU (0x7 << S_ConfigKU) + +#define M_Config0Fields 0x00000078 +#define M_ConfigRFields 0x8000ff80 + +/* + * Values in the AT field + */ +#define K_ConfigAT_MIPS32 0 /* MIPS32 */ +#define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ +#define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ + +/* + * Values in the MT field + */ +#define K_ConfigMT_NoMMU 0 /* No MMU */ +#define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ +#define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ +#define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ + + +/* + ************************************************************************ + * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |M| MMU Size | IS | IL | IA | DS | DL | DA |C|M|P|W|C|E|F| Config1 + * | | | | | | | | |2|D|C|R|A|P|P| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Config1 $16,1 +#define R_C0_Config1 16 + +#define S_Config1More 31 /* Additional Config registers present (R) */ +#define M_Config1More (0x1 << S_Config1More) +#define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ +#define M_Config1MMUSize (0x3f << S_Config1MMUSize) +#define S_Config1IS 22 /* Icache sets per way (R) */ +#define M_Config1IS (0x7 << S_Config1IS) +#define S_Config1IL 19 /* Icache line size (R) */ +#define M_Config1IL (0x7 << S_Config1IL) +#define S_Config1IA 16 /* Icache associativity - 1 (R) */ +#define M_Config1IA (0x7 << S_Config1IA) +#define S_Config1DS 13 /* Dcache sets per way (R) */ +#define M_Config1DS (0x7 << S_Config1DS) +#define S_Config1DL 10 /* Dcache line size (R) */ +#define M_Config1DL (0x7 << S_Config1DL) +#define S_Config1DA 7 /* Dcache associativity (R) */ +#define M_Config1DA (0x7 << S_Config1DA) +#define S_Config1C2 6 /* Coprocessor 2 present (R) */ +#define M_Config1C2 (0x1 << S_Config1C2) +#define S_Config1MD 5 /* Denotes MDMX present (R) */ +#define M_Config1MD (0x1 << S_Config1MD) +#define S_Config1PC 4 /* Denotes performance counters present (R) */ +#define M_Config1PC (0x1 << S_Config1PC) +#define S_Config1WR 3 /* Denotes watch registers present (R) */ +#define M_Config1WR (0x1 << S_Config1WR) +#define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ +#define M_Config1CA (0x1 << S_Config1CA) +#define S_Config1EP 1 /* Denotes EJTAG present (R) */ +#define M_Config1EP (0x1 << S_Config1EP) +#define S_Config1FP 0 /* Denotes floating point present (R) */ +#define M_Config1FP (0x1 << S_Config1FP) + +#define M_Config10Fields 0x00000060 +#define M_Config1RFields 0x7fffff9f + +/* + * The following macro generates a table that is indexed + * by the Icache or Dcache sets field in Config1 and + * contains the decoded value of sets per way + */ +#define Config1CacheSets() \ + HALF(64); \ + HALF(128); \ + HALF(256); \ + HALF(512); \ + HALF(1024); \ + HALF(2048); \ + HALF(4096); \ + HALF(8192); + +/* + * The following macro generates a table that is indexed + * by the Icache or Dcache line size field in Config1 and + * contains the decoded value of the cache line size, in bytes + */ +#define Config1CacheLineSize() \ + HALF(0); \ + HALF(4); \ + HALF(8); \ + HALF(16); \ + HALF(32); \ + HALF(64); \ + HALF(128); \ + HALF(256); + + +/* + ************************************************************************ + * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |M| | | | | | | | | | | | |S|T| Config1 + * | | | | | | | | | | | | | |M|L| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Config2 $16,2 +#define R_C0_Config2 16 + +#define S_Config2More 31 /* Additional Config registers present (R) */ +#define M_Config2More (0x1 << S_Config2More) +#define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ +#define M_Config2SM (0x1 << S_Config2SM) +#define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ +#define M_Config2TL (0x1 << S_Config2TL) + +#define M_Config20Fields 0xfffffffc +#define M_Config2RFields 0x00000003 + +/* + ************************************************************************ + * L L A D D R R E G I S T E R ( 1 7 ) * + ************************************************************************ + * + * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // LL Physical Address | LLAddr + * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_LLAddr $17 +#define R_C0_LLAddr 17 +#define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_LLAddr0Fields 0x00000000 +#define M_LLAddrRFields 0x00000000 +#define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) +#define M_LLAddrRFields64 UNS64Const(0x0000000000000000) + + +/* + ************************************************************************ + * W A T C H L O R E G I S T E R ( 1 8 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // Watch Virtual Address |I|R|W| WatchLo + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_WatchLo $18 +#define R_C0_WatchLo 18 +#define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ +#define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) +#define S_WatchLoI 2 /* Enable Istream watch (R/W) */ +#define M_WatchLoI (0x1 << S_WatchLoI) +#define S_WatchLoR 1 /* Enable data read watch (R/W) */ +#define M_WatchLoR (0x1 << S_WatchLoR) +#define S_WatchLoW 0 /* Enable data write watch (R/W) */ +#define M_WatchLoW (0x1 << S_WatchLoW) + +#define M_WatchLo0Fields 0x00000000 +#define M_WatchLoRFields 0x00000000 +#define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) +#define M_WatchLoRFields64 UNS64Const(0x0000000000000000) + +#define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) + + +/* + ************************************************************************ + * W A T C H H I R E G I S T E R ( 1 9 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_WatchHi $19 +#define R_C0_WatchHi 19 +#define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ +#define M_WatchHiM (0x1 << S_WatchHiM) +#define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ +#define M_WatchHiG (0x1 << S_WatchHiG) +#define S_WatchHiASID 16 /* ASID value to match (R/W) */ +#define M_WatchHiASID (0xff << S_WatchHiASID) +#define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ +#define M_WatchHiMask (0x1ff << S_WatchHiMask) + +#define M_WatchHi0Fields 0x3f00f007 +#define M_WatchHiRFields 0x80000000 + + +/* + ************************************************************************ + * X C O N T E X T R E G I S T E R ( 2 0 ) * + ************************************************************************ + * + * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // PTEBase | R | BadVPN2<39:13> | 0 | XContext + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_XContext $20 +#define R_C0_XContext 20 +#define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_XContextBadVPN2 4 /* BadVPN2 (R) */ +#define S_XContextBadVPN S_XContextBadVPN2 + +#define M_XContext0Fields 0x0000000f + + +/* + ************************************************************************ + * D E B U G R E G I S T E R ( 2 3 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D| + * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S| + * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S| + * | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug + * | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | | + * | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | | + * | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | | + * | | | | | | | | | | | | |r|r| | | | | | | | | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_Debug $23 /* EJTAG */ +#define R_C0_Debug 23 + +#define S_DebugDBD 31 /* Debug branch delay (R) */ +#define M_DebugDBD (0x1 << S_DebugDBD) +#define S_DebugDM 30 /* Debug mode (R) */ +#define M_DebugDM (0x1 << S_DebugDM) +#define S_DebugNoDCR 29 /* No debug control register present (R) */ +#define M_DebugNoDCR (0x1 << S_DebugNoDCR) +#define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ +#define M_DebugLSNM (0x1 << S_DebugLSNM) +#define S_DebugDoze 27 /* Doze (R) */ +#define M_DebugDoze (0x1 << S_DebugDoze) +#define S_DebugHalt 26 /* Halt (R) */ +#define M_DebugHalt (0x1 << S_DebugHalt) +#define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ +#define M_DebugCountDM (0x1 << S_DebugCountDM) +#define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ +#define M_DebugIBusEP (0x1 << S_DebugIBusEP) +#define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ +#define M_DebugMCheckP (0x1 << S_DebugMCheckP) +#define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ +#define M_DebugCacheEP (0x1 << S_DebugCacheEP) +#define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ +#define M_DebugDBusEP (0x1 << S_DebugDBusEP) +#define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ +#define M_DebugIEXI (0x1 << S_DebugIEXI) +#define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ +#define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) +#define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ +#define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) +#define S_DebugEJTAGver 15 /* EJTAG version number (R) */ +#define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) +#define S_DebugDExcCode 10 /* Debug exception code (R) */ +#define M_DebugDExcCode (0x1f << S_DebugDExcCode) +#define S_DebugNoSSt 9 /* No single step implemented (R) */ +#define M_DebugNoSSt (0x1 << S_DebugNoSSt) +#define S_DebugSSt 8 /* Single step enable (R/W) */ +#define M_DebugSSt (0x1 << S_DebugSSt) +#define S_DebugDINT 5 /* Debug interrupt (R) */ +#define M_DebugDINT (0x1 << S_DebugDINT) +#define S_DebugDIB 4 /* Debug instruction break (R) */ +#define M_DebugDIB (0x1 << S_DebugDIB) +#define S_DebugDDBS 3 /* Debug data break store (R) */ +#define M_DebugDDBS (0x1 << S_DebugDDBS) +#define S_DebugDDBL 2 /* Debug data break load (R) */ +#define M_DebugDDBL (0x1 << S_DebugDDBL) +#define S_DebugDBp 1 /* Debug breakpoint (R) */ +#define M_DebugDBp (0x1 << S_DebugDBp) +#define S_DebugDSS 0 /* Debug single step (R) */ +#define M_DebugDSS (0x1 << S_DebugDSS) + +#define M_Debug0Fields 0x01f000c0 +#define M_DebugRFields 0xec0ffe3f + + +/* + ************************************************************************ + * D E P C R E G I S T E R ( 2 4 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // EJTAG Debug Exception PC | DEPC + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + + +#define C0_DEPC $24 +#define R_C0_DEPC 24 + +#define M_DEEPC0Fields 0x00000000 +#define M_DEEPCRFields 0x00000000 +#define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) +#define M_DEEPCRFields64 UNS64Const(0x0000000000000000) + + +/* + ************************************************************************ + * P E R F C N T R E G I S T E R ( 2 5 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | | | |I| | | |E| + * |M| 0 | Event |E|U|S|K|X| PerfCnt + * | | | | | | | |L| + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Event Count | PerfCnt + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_PerfCnt $25 +#define R_C0_PerfCnt 25 +#define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define S_PerfCntM 31 /* More performance counters exist (R) */ +#define M_PerfCntM (1 << S_PerfCntM) +#define S_PerfCntEvent 5 /* Enabled event (R/W) */ +#define M_PerfCntEvent (0x3f << S_PerfCntEvent) +#define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ +#define M_PerfCntIE (1 << S_PerfCntIE) +#define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ +#define M_PerfCntU (1 << S_PerfCntU) +#define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ +#define M_PerfCntS (1 << S_PerfCntS) +#define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ +#define M_PerfCntK (1 << S_PerfCntK) +#define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ +#define M_PerfCntEXL (1 << S_PerfCntEXL) + +#define M_PerfCnt0Fields 0x7ffff800 +#define M_PerfCntRFields 0x80000000 + + +/* + ************************************************************************ + * E R R C T L R E G I S T E R ( 2 6 ) * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Error Control | ErrCtl + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_ErrCtl $26 +#define R_C0_ErrCtl 26 +#define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ +#define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_ErrCtl0Fields 0x00000000 +#define M_ErrCtlRFields 0x00000000 + + +/* + ************************************************************************ + * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | Cache Error Control | CacheErr + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_CacheErr $27 +#define R_C0_CacheErr 27 +#define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_CacheErr0Fields 0x00000000 +#define M_CachErrRFields 0x00000000 + + +/* + ************************************************************************ + * T A G L O R E G I S T E R ( 2 8 ) * TagLo + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | TagLo | TagLo + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_TagLo $28 +#define R_C0_TagLo 28 +#define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ + +/* + * Some implementations use separate TagLo registers for the + * instruction and data caches. In those cases, the following + * definitions can be used in relevant code + */ + +#define C0_ITagLo $28,0 +#define C0_DTagLo $28,2 + +#define M_TagLo0Fields 0x00000000 +#define M_TagLoRFields 0x00000000 + + +/* + ************************************************************************ + * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | DataLo | DataLo + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_DataLo $28,1 +#define R_C0_DataLo 28 + +/* + * Some implementations use separate DataLo registers for the + * instruction and data caches. In those cases, the following + * definitions can be used in relevant code + */ + +#define C0_IDataLo $28,1 +#define C0_DDataLo $28,3 + +#define M_DataLo0Fields 0x00000000 +#define M_DataLoRFields 0xffffffff + + +/* + ************************************************************************ + * T A G H I R E G I S T E R ( 2 9 ) * TagHi + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | TagHi | TagHi + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_TagHi $29 +#define R_C0_TagHi 29 +#define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ + +/* + * Some implementations use separate TagHi registers for the + * instruction and data caches. In those cases, the following + * definitions can be used in relevant code + */ + +#define C0_ITagHi $29,0 +#define C0_DTagHi $29,2 + +#define M_TagHi0Fields 0x00000000 +#define M_TagHiRFields 0x00000000 + + +/* + ************************************************************************ + * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | DataHi | DataHi + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_DataHi $29,1 +#define R_C0_DataHi 29 + +/* + * Some implementations use separate DataHi registers for the + * instruction and data caches. In those cases, the following + * definitions can be used in relevant code + */ + +#define C0_IDataHi $29,1 +#define C0_DDataHi $29,3 + +#define M_DataHi0Fields 0x00000000 +#define M_DataHiRFields 0xffffffff + + +/* + ************************************************************************ + * E R R O R E P C R E G I S T E R ( 3 0 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // Error PC | ErrorEPC + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_ErrorEPC $30 +#define R_C0_ErrorEPC 30 +#define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ + +#define M_ErrorEPC0Fields 0x00000000 +#define M_ErrorEPCRFields 0x00000000 +#define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) +#define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) + + +/* + ************************************************************************ + * D E S A V E R E G I S T E R ( 3 1 ) * + ************************************************************************ + * + * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | // EJTAG Register Save Value | DESAVE + * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C0_DESAVE $31 +#define R_C0_DESAVE 31 + +#define M_DESAVE0Fields 0x00000000 +#define M_DESAVERFields 0x00000000 +#define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) +#define M_DESAVERFields64 UNS64Const(0x0000000000000000) + + +/* + ************************************************************************* + * C P 1 R E G I S T E R D E F I N I T I O N S * + ************************************************************************* + */ + + +/* + ************************************************************************* + * H A R D W A R E F P R N A M E S * + ************************************************************************* + */ + +#define fp0 $f0 +#define fp1 $f1 +#define fp2 $f2 +#define fp3 $f3 +#define fp4 $f4 +#define fp5 $f5 +#define fp6 $f6 +#define fp7 $f7 +#define fp8 $f8 +#define fp9 $f9 +#define fp10 $f10 +#define fp11 $f11 +#define fp12 $f12 +#define fp13 $f13 +#define fp14 $f14 +#define fp15 $f15 +#define fp16 $f16 +#define fp17 $f17 +#define fp18 $f18 +#define fp19 $f19 +#define fp20 $f20 +#define fp21 $f21 +#define fp22 $f22 +#define fp23 $f23 +#define fp24 $f24 +#define fp25 $f25 +#define fp26 $f26 +#define fp27 $f27 +#define fp28 $f28 +#define fp29 $f29 +#define fp30 $f30 +#define fp31 $f31 + +/* + * The following definitions are used to convert an FPR name + * into the corresponding even or odd name, respectively. + * This is used in macro substitution in the AVPs. + */ + +#define fp1_even $f0 +#define fp3_even $f2 +#define fp5_even $f4 +#define fp7_even $f6 +#define fp9_even $f8 +#define fp11_even $f10 +#define fp13_even $f12 +#define fp15_even $f14 +#define fp17_even $f16 +#define fp19_even $f18 +#define fp21_even $f20 +#define fp23_even $f22 +#define fp25_even $f24 +#define fp27_even $f26 +#define fp29_even $f28 +#define fp31_even $f30 + +#define fp0_odd $f1 +#define fp2_odd $f3 +#define fp4_odd $f5 +#define fp6_odd $f7 +#define fp8_odd $f9 +#define fp10_odd $f11 +#define fp12_odd $f13 +#define fp14_odd $f15 +#define fp16_odd $f17 +#define fp18_odd $f19 +#define fp20_odd $f21 +#define fp22_odd $f23 +#define fp24_odd $f25 +#define fp26_odd $f27 +#define fp28_odd $f29 +#define fp30_odd $f31 + + +/* + ************************************************************************* + * H A R D W A R E F P R I N D I C E S * + ************************************************************************* + * + * These definitions provide the index (number) of the FPR, as opposed + * to the assembler register name ($n). + */ + +#define R_fp0 0 +#define R_fp1 1 +#define R_fp2 2 +#define R_fp3 3 +#define R_fp4 4 +#define R_fp5 5 +#define R_fp6 6 +#define R_fp7 7 +#define R_fp8 8 +#define R_fp9 9 +#define R_fp10 10 +#define R_fp11 11 +#define R_fp12 12 +#define R_fp13 13 +#define R_fp14 14 +#define R_fp15 15 +#define R_fp16 16 +#define R_fp17 17 +#define R_fp18 18 +#define R_fp19 19 +#define R_fp20 20 +#define R_fp21 21 +#define R_fp22 22 +#define R_fp23 23 +#define R_fp24 24 +#define R_fp25 25 +#define R_fp26 26 +#define R_fp27 27 +#define R_fp28 28 +#define R_fp29 29 +#define R_fp30 30 +#define R_fp31 31 + + +/* + ************************************************************************* + * H A R D W A R E F C R N A M E S * + ************************************************************************* + */ + +#define fc0 $0 +#define fc25 $25 +#define fc26 $26 +#define fc28 $28 +#define fc31 $31 + + +/* + ************************************************************************* + * H A R D W A R E F C R I N D I C E S * + ************************************************************************* + * + * These definitions provide the index (number) of the FCR, as opposed + * to the assembler register name ($n). + */ + +#define R_fc0 0 +#define R_fc25 25 +#define R_fc26 26 +#define R_fc28 28 +#define R_fc31 31 + + +/* + ************************************************************************* + * H A R D W A R E F C C N A M E S * + ************************************************************************* + */ + +#define cc0 $fcc0 +#define cc1 $fcc1 +#define cc2 $fcc2 +#define cc3 $fcc3 +#define cc4 $fcc4 +#define cc5 $fcc5 +#define cc6 $fcc6 +#define cc7 $fcc7 + + +/* + ************************************************************************* + * H A R D W A R E F C C I N D I C E S * + ************************************************************************* + * + * These definitions provide the index (number) of the CC, as opposed + * to the assembler register name ($n). + */ + +#define R_cc0 0 +#define R_cc1 1 +#define R_cc2 2 +#define R_cc3 3 +#define R_cc4 4 +#define R_cc5 5 +#define R_cc6 6 +#define R_cc7 7 + + +/* + ************************************************************************ + * I M P L E M E N T A T I O N R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * |Reserved for Additional|3|P|D|S| Implementation| Revision | FIR + * | Configuration Bits |D|S| | | | | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FIR $0 +#define R_C1_FIR 0 + +#define S_FIRConfigS 16 +#define M_FIRConfigS (0x1 << S_FIRConfigS) +#define S_FIRConfigD 17 +#define M_FIRConfigD (0x1 << S_FIRConfigD) +#define S_FIRConfigPS 18 +#define M_FIRConfigPS (0x1 << S_FIRConfigPS) +#define S_FIRConfig3D 19 +#define M_FIRConfig3D (0x1 << S_FIRConfig3D) +#define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) + +#define S_FIRImp 8 +#define M_FIRImp (0xff << S_FIRImp) + +#define S_FIRRev 0 +#define M_FIRRev (0xff << S_FIRRev) + +#define M_FIR0Fields 0xfff00000 +#define M_FIRRFields 0x000fffff + +/* + ************************************************************************ + * C O N D I T I O N C O D E S R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | CC | FCCR + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FCCR $25 +#define R_C1_FCCR 25 + +#define S_FCCRCC 0 +#define M_FCCRCC (0xff << S_FCCRCC) +#define S_FCCRCC7 7 +#define M_FCCRCC7 (0x1 << S_FCCRCC7) +#define S_FCCRCC6 6 +#define M_FCCRCC6 (0x1 << S_FCCRCC6) +#define S_FCCRCC5 5 +#define M_FCCRCC5 (0x1 << S_FCCRCC5) +#define S_FCCRCC4 4 +#define M_FCCRCC4 (0x1 << S_FCCRCC4) +#define S_FCCRCC3 3 +#define M_FCCRCC3 (0x1 << S_FCCRCC3) +#define S_FCCRCC2 2 +#define M_FCCRCC2 (0x1 << S_FCCRCC2) +#define S_FCCRCC1 1 +#define M_FCCRCC1 (0x1 << S_FCCRCC1) +#define S_FCCRCC0 0 +#define M_FCCRCC0 (0x1 << S_FCCRCC0) + +#define M_FCCR0Fields 0xffffff00 +#define M_FCCRRFields 0x000000ff + + +/* + ************************************************************************ + * E X C E P T I O N S R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Cause | 0 | Flags | 0 | FEXR + * | |E|V|Z|O|U|I| |V|Z|O|U|I| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FEXR $26 +#define R_C1_FEXR 26 + +#define S_FEXRExc 12 +#define M_FEXRExc (0x3f << S_FEXRExc) +#define S_FEXRExcE 17 +#define M_FEXRExcE (0x1 << S_FEXRExcE) +#define S_FEXRExcV 16 +#define M_FEXRExcV (0x1 << S_FEXRExcV) +#define S_FEXRExcZ 15 +#define M_FEXRExcZ (0x1 << S_FEXRExcZ) +#define S_FEXRExcO 14 +#define M_FEXRExcO (0x1 << S_FEXRExcO) +#define S_FEXRExcU 13 +#define M_FEXRExcU (0x1 << S_FEXRExcU) +#define S_FEXRExcI 12 +#define M_FEXRExcI (0x1 << S_FEXRExcI) + +#define S_FEXRFlg 2 +#define M_FEXRFlg (0x1f << S_FEXRFlg) +#define S_FEXRFlgV 6 +#define M_FEXRFlgV (0x1 << S_FEXRFlgV) +#define S_FEXRFlgZ 5 +#define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) +#define S_FEXRFlgO 4 +#define M_FEXRFlgO (0x1 << S_FEXRFlgO) +#define S_FEXRFlgU 3 +#define M_FEXRFlgU (0x1 << S_FEXRFlgU) +#define S_FEXRFlgI 2 +#define M_FEXRFlgI (0x1 << S_FEXRFlgI) + +#define M_FEXR0Fields 0xfffc0f83 +#define M_FEXRRFields 0x00000000 + + +/* + ************************************************************************ + * E N A B L E S R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | 0 | Enables | 0 |F|RM | FENR + * | |V|Z|O|U|I| |S| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FENR $28 +#define R_C1_FENR 28 + +#define S_FENREna 7 +#define M_FENREna (0x1f << S_FENREna) +#define S_FENREnaV 11 +#define M_FENREnaV (0x1 << S_FENREnaV) +#define S_FENREnaZ 10 +#define M_FENREnaZ (0x1 << S_FENREnaZ) +#define S_FENREnaO 9 +#define M_FENREnaO (0x1 << S_FENREnaO) +#define S_FENREnaU 8 +#define M_FENREnaU (0x1 << S_FENREnaU) +#define S_FENREnaI 7 +#define M_FENREnaI (0x1 << S_FENREnaI) + +#define S_FENRFS 2 +#define M_FENRFS (0x1 << S_FENRFS) + +#define S_FENRRM 0 +#define M_FENRRM (0x3 << S_FENRRM) + +#define M_FENR0Fields 0xfffff078 +#define M_FENRRFields 0x00000000 + + +/* + ************************************************************************ + * C O N T R O L / S T A T U S R E G I S T E R * + ************************************************************************ + * + * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | FCC |F|C|Imp| 0 | Cause | Enables | Flags | RM| FCSR + * |7|6|5|4|3|2|1|S|C| | |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I| | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + */ + +#define C1_FCSR $31 +#define R_C1_FCSR 31 + +#define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ +#define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) +#define S_FCSRCC7 31 +#define M_FCSRCC7 (0x1 << S_FCSRCC7) +#define S_FCSRCC6 30 +#define M_FCSRCC6 (0x1 << S_FCSRCC6) +#define S_FCSRCC5 29 +#define M_FCSRCC5 (0x1 << S_FCSRCC5) +#define S_FCSRCC4 28 +#define M_FCSRCC4 (0x1 << S_FCSRCC4) +#define S_FCSRCC3 27 +#define M_FCSRCC3 (0x1 << S_FCSRCC3) +#define S_FCSRCC2 26 +#define M_FCSRCC2 (0x1 << S_FCSRCC2) +#define S_FCSRCC1 25 +#define M_FCSRCC1 (0x1 << S_FCSRCC1) + +#define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ +#define M_FCSRFS (0x1 << S_FCSRFS) + +#define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ +#define M_FCSRCC0 (0x1 << S_FCSRCC0) +#define S_FCSRCC S_FCSRCC0 +#define M_FCSRCC M_FCSRCC0 + +#define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ +#define M_FCSRImpl (0x3 << S_FCSRImpl) + +#define S_FCSRExc 12 /* Exception cause (R/W) */ +#define M_FCSRExc (0x3f << S_FCSRExc) +#define S_FCSRExcE 17 +#define M_FCSRExcE (0x1 << S_FCSRExcE) +#define S_FCSRExcV 16 +#define M_FCSRExcV (0x1 << S_FCSRExcV) +#define S_FCSRExcZ 15 +#define M_FCSRExcZ (0x1 << S_FCSRExcZ) +#define S_FCSRExcO 14 +#define M_FCSRExcO (0x1 << S_FCSRExcO) +#define S_FCSRExcU 13 +#define M_FCSRExcU (0x1 << S_FCSRExcU) +#define S_FCSRExcI 12 +#define M_FCSRExcI (0x1 << S_FCSRExcI) + +#define S_FCSREna 7 /* Exception enable (R/W) */ +#define M_FCSREna (0x1f << S_FCSREna) +#define S_FCSREnaV 11 +#define M_FCSREnaV (0x1 << S_FCSREnaV) +#define S_FCSREnaZ 10 +#define M_FCSREnaZ (0x1 << S_FCSREnaZ) +#define S_FCSREnaO 9 +#define M_FCSREnaO (0x1 << S_FCSREnaO) +#define S_FCSREnaU 8 +#define M_FCSREnaU (0x1 << S_FCSREnaU) +#define S_FCSREnaI 7 +#define M_FCSREnaI (0x1 << S_FCSREnaI) + +#define S_FCSRFlg 2 /* Exception flags (R/W) */ +#define M_FCSRFlg (0x1f << S_FCSRFlg) +#define S_FCSRFlgV 6 +#define M_FCSRFlgV (0x1 << S_FCSRFlgV) +#define S_FCSRFlgZ 5 +#define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) +#define S_FCSRFlgO 4 +#define M_FCSRFlgO (0x1 << S_FCSRFlgO) +#define S_FCSRFlgU 3 +#define M_FCSRFlgU (0x1 << S_FCSRFlgU) +#define S_FCSRFlgI 2 +#define M_FCSRFlgI (0x1 << S_FCSRFlgI) + +#define S_FCSRRM 0 /* Rounding mode (R/W) */ +#define M_FCSRRM (0x3 << S_FCSRRM) + +#define M_FCSR0Fields 0x001c0000 +#define M_FCSRRFields 0x00000000 + +/* + * Values in the rounding mode field (of both FCSR and FCCR) + */ +#define K_FCSRRM_RN 0 +#define K_FCSRRM_RZ 1 +#define K_FCSRRM_RP 2 +#define K_FCSRRM_RM 3 + + +/* ********************************************************************* */ +/* Interface function definition */ + + +/* ********************************************************************* */ + +#endif /* __ARCHDEFS_H__ */ diff --git a/sdk-modifications/include/bit_ops.h b/sdk-modifications/include/bit_ops.h new file mode 100755 index 0000000..f823db7 --- /dev/null +++ b/sdk-modifications/include/bit_ops.h @@ -0,0 +1,58 @@ +/* + bit_ops.h + Functions for dealing with conversion of data between types + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-07-11 - Chishm + * Original release +*/ + +#ifndef _BIT_OPS_H +#define _BIT_OPS_H + +/*----------------------------------------------------------------- +Functions to deal with little endian values stored in u8 arrays +-----------------------------------------------------------------*/ +static inline u16 u8array_to_u16 (const u8* item, int offset) { + return ( item[offset] | (item[offset + 1] << 8)); +} + +static inline u32 u8array_to_u32 (const u8* item, int offset) { + return ( item[offset] | (item[offset + 1] << 8) | (item[offset + 2] << 16) | (item[offset + 3] << 24)); +} + +static inline void u16_to_u8array (u8* item, int offset, u16 value) { + item[offset] = (u8)value; + item[offset + 1] = (u8)(value >> 8); +} + +static inline void u32_to_u8array (u8* item, int offset, u32 value) { + item[offset] = (u8)value; + item[offset + 1] = (u8)(value >> 8); + item[offset + 2] = (u8)(value >> 16); + item[offset + 3] = (u8)(value >> 24); +} + +#endif // _BIT_OPS_H diff --git a/sdk-modifications/include/console.h b/sdk-modifications/include/console.h new file mode 100755 index 0000000..f6d74a4 --- /dev/null +++ b/sdk-modifications/include/console.h @@ -0,0 +1,9 @@ +#ifndef __CONSOLE_H__ +#define __CONSOLE_H__ +#include "ds2io.h" + +extern int ConsoleInit(unsigned short front_color, unsigned short background_color, enum SCREEN_ID screen, unsigned int buf_size); + +extern int cprintf(const char *format, ...); + +#endif //__CONSOLE_H__ diff --git a/sdk-modifications/include/directory.h b/sdk-modifications/include/directory.h new file mode 100755 index 0000000..00046a9 --- /dev/null +++ b/sdk-modifications/include/directory.h @@ -0,0 +1,172 @@ +/* + directory.h + Reading, writing and manipulation of the directory structure on + a FAT partition + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-07-11 - Chishm + * Original release +*/ + +#ifndef _DIRECTORY_H +#define _DIRECTORY_H + +#include + +#include "fs_common.h" +#include "partition.h" + +#define DIR_ENTRY_DATA_SIZE 0x20 +#define MAX_FILENAME_LENGTH 256 +#define MAX_ALIAS_LENGTH 13 +#define LFN_ENTRY_LENGTH 13 +#define FAT16_ROOT_DIR_CLUSTER 0 + +#define DIR_SEPARATOR '/' + +// File attributes +#define ATTRIB_ARCH 0x20 // Archive +#define ATTRIB_DIR 0x10 // Directory +#define ATTRIB_LFN 0x0F // Long file name +#define ATTRIB_VOL 0x08 // Volume +#define ATTRIB_SYS 0x04 // System +#define ATTRIB_HID 0x02 // Hidden +#define ATTRIB_RO 0x01 // Read only + +typedef enum {FT_DIRECTORY, FT_FILE} FILE_TYPE; + +typedef struct { + u32 cluster; + u32 sector; + s32 offset; +} DIR_ENTRY_POSITION; + +typedef struct { + u8 entryData[DIR_ENTRY_DATA_SIZE]; + DIR_ENTRY_POSITION dataStart; // Points to the start of the LFN entries of a file, or the alias for no LFN + DIR_ENTRY_POSITION dataEnd; // Always points to the file/directory's alias entry + char d_name[MAX_FILENAME_LENGTH + MAX_FILENAME_LENGTH*2]; //Store name string using UTF8 coding + //u16 unicodeFilename[MAX_FILENAME_LENGTH]; +} DIR_ENTRY; + +// Directory entry offsets +enum DIR_ENTRY_offset { + DIR_ENTRY_name = 0x00, + DIR_ENTRY_extension = 0x08, + DIR_ENTRY_attributes = 0x0B, + DIR_ENTRY_reserved = 0x0C, + DIR_ENTRY_cTime_ms = 0x0D, + DIR_ENTRY_cTime = 0x0E, + DIR_ENTRY_cDate = 0x10, + DIR_ENTRY_aDate = 0x12, + DIR_ENTRY_clusterHigh = 0x14, + DIR_ENTRY_mTime = 0x16, + DIR_ENTRY_mDate = 0x18, + DIR_ENTRY_cluster = 0x1A, + DIR_ENTRY_fileSize = 0x1C +}; + +/* +Returns true if the file specified by entry is a directory +*/ +static inline bool _FAT_directory_isDirectory (DIR_ENTRY* entry) { + return ((entry->entryData[DIR_ENTRY_attributes] & ATTRIB_DIR) != 0); +} + +static inline bool _FAT_directory_isWritable (DIR_ENTRY* entry) { + return ((entry->entryData[DIR_ENTRY_attributes] & ATTRIB_RO) == 0); +} + +static inline bool _FAT_directory_isDot (DIR_ENTRY* entry) { + return ((entry->d_name[0] == '.') && ((entry->d_name[1] == '\0') || + ((entry->d_name[1] == '.') && entry->d_name[2] == '\0'))); +} + +/* +Reads the first directory entry from the directory starting at dirCluster +Places result in entry +entry will be destroyed even if no directory entry is found +Returns true on success, false on failure +*/ +bool _FAT_directory_getFirstEntry (PARTITION* partition, DIR_ENTRY* entry, u32 dirCluster); + +/* +Reads the next directory entry after the one already pointed to by entry +Places result in entry +entry will be destroyed even if no directory entry is found +Returns true on success, false on failure +*/ +bool _FAT_directory_getNextEntry (PARTITION* partition, DIR_ENTRY* entry); + +/* +Gets the directory entry corrsponding to the supplied path +entry will be destroyed even if no directory entry is found +pathEnd specifies the end of the path string, for cutting strings short if needed + specify NULL to use the full length of path + pathEnd is only a suggestion, and the path string will be searched up until the next PATH_SEPARATOR + after pathEND. +Returns true on success, false on failure +*/ +bool _FAT_directory_entryFromPath (PARTITION* partition, DIR_ENTRY* entry, const char* path, const char* pathEnd); + +/* +Changes the current directory to the one specified by path +Returns true on success, false on failure +*/ +bool _FAT_directory_chdir (PARTITION* partition, const char* path); + +/* +Removes the directory entry specified by entry +Assumes that entry is valid +Returns true on success, false on failure +*/ +bool _FAT_directory_removeEntry (PARTITION* partition, DIR_ENTRY* entry); + +/* +Add a directory entry to the directory specified by dirCluster +The fileData, dataStart and dataEnd elements of the DIR_ENTRY struct are +updated with the new directory entry position and alias. +Returns true on success, false on failure +*/ +bool _FAT_directory_addEntry (PARTITION* partition, DIR_ENTRY* entry, u32 dirCluster); + +/* +Get the start cluster of a file from it's entry data +*/ +u32 _FAT_directory_entryGetCluster (const u8* entryData); + +/* +Fill in the file name and entry data of DIR_ENTRY* entry. +Assumes that the entry's dataStart and dataEnd are correct +Returns true on success, false on failure +*/ +bool _FAT_directory_entryFromPosition (PARTITION* partition, DIR_ENTRY* entry); + +/* +Fill in a stat struct based on a file entry +*/ +void _FAT_directory_entryStat (PARTITION* partition, DIR_ENTRY* entry, struct stat *st); + +#endif // _DIRECTORY_H diff --git a/sdk-modifications/include/ds2_cpu.h b/sdk-modifications/include/ds2_cpu.h new file mode 100755 index 0000000..d4b7144 --- /dev/null +++ b/sdk-modifications/include/ds2_cpu.h @@ -0,0 +1,57 @@ +#ifndef __DS2_CPU_H__ +#define __DS2_CPU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +//exception handle + + +//cache operationr +//invalidate instruction cache +extern void __icache_invalidate_all(void); + +//invalidate data cache +extern void __dcache_invalidate_all(void); + +//data cache writeback +extern void __dcache_writeback_all(void); + +//data cache writeback and invalidate +extern void _dcache_wback_inv(unsigned long addr, unsigned long size); + + +//interruption operation +//clear CPU's interrupt state and enable global interrupt +extern void sti(void); + +//disable global interrupt +extern void cli(void); + +//disable global interrupt and store the global interrupt state +//return: interrupt state +extern unsigned int spin_lock_irqsave(void); + +//restore global interrupt state +extern void spin_unlock_irqrestore(unsigned int val); + + +//CPU frequence +//There are 14 levels, 0 to 13, 13 level have the highest clock frequence +extern int ds2_setCPUclocklevel(unsigned int num); + +//print colock frequence CPU +extern void printf_clock(void); + +//delay n us +extern void udelay(unsigned int usec); + +//delay n ms +extern void mdelay(unsigned int msec); + +#ifdef __cplusplus +} +#endif + +#endif //__DS2_CPU_H__ diff --git a/sdk-modifications/include/ds2_cpuclock.h b/sdk-modifications/include/ds2_cpuclock.h new file mode 100644 index 0000000..3263ed0 --- /dev/null +++ b/sdk-modifications/include/ds2_cpuclock.h @@ -0,0 +1,21 @@ +#ifndef _DS2_CPUCLOCK_H__ +#define _DS2_CPUCLOCK_H__ + + +#define CPU_MAX_LEVEL_EX 18 + +#ifdef __cplusplus +extern "C" { +#endif + +extern int ds2_getCPUClock(void); +extern int ds2_setCPULevel(unsigned int level); +extern void ds2_udelay(unsigned int usec); +extern void ds2_mdelay(unsigned int msec); + + +#ifdef __cplusplus +} +#endif + +#endif //__DS2_CPUCLOCK_H__ diff --git a/sdk-modifications/include/ds2_dma.h b/sdk-modifications/include/ds2_dma.h new file mode 100644 index 0000000..9a306cf --- /dev/null +++ b/sdk-modifications/include/ds2_dma.h @@ -0,0 +1,142 @@ +#ifndef _DS2_DMA_H__ +#define _DS2_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#define MAX_DMA_NUM 6 /* max 6 channels */ + + +// DMA request source register +#define DMAC_DRSR_RS_BIT 0 +#define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT) + + +// DMA channel command register +#define DMAC_DCMD_SAI (1 << 23) /* source address increment */ +#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */ + +#define DMAC_DCMD_SWDH_BIT 14 /* source port width */ +#define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT) +#define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT) +#define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT) + +#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */ +#define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT) +#define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT) + #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT) + +#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */ +#define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT) +#define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT) +#define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT) +#define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT) +#define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT) + +#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */ + + +//detect if channel has completed job +#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */ +#define DMAC_BASE 0xB3020000 +#define REG32(addr) *((volatile u32 *)(addr)) +#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */ +#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n))) + +#define ds2_DMA_isBusy(n) \ + !( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT ) + + +/* +Copy modes + +*/ + +#define DMA_MODE32BYTE DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \ + DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TM + +#define DMA_MODE16BYTE DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \ + DMAC_DCMD_DS_16BYTE | DMAC_DCMD_TM + +#define DMA_MODE32BIT DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \ + DMAC_DCMD_DS_32BIT + +#define DMA_MODE16BIT DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \ + DMAC_DCMD_DS_16BIT + +#define DMA_MODE8BIT DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_8 | \ + DMAC_DCMD_DS_8BIT | DMAC_DCMD_TM + +#define DMA_MODECOPY DMAC_DCMD_SAI + + + +extern int _dmaCopy(int ch, void *dest, void *src, unsigned int size, unsigned int flags); + +/* + * Copy 'size' bytes from src to dest, in blocks of 32 bytes. + * size is in bytes and must be a multiple of 32. + * Both src and dest must be aligned to 32 bytes. + * Returns 0 on failure, non-zero on success. + */ +#define ds2_DMAcopy_32Byte(ch, dest, src, size)\ + _dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE32BYTE) + +/* + * Copy 'size' bytes from src to dest, in blocks of 16 bytes. + * size is in bytes and must be a multiple of 16. + * Both src and dest must be aligned to 16 bytes. + * Returns 0 on failure, non-zero on success. + */ +#define ds2_DMAcopy_16Byte(ch, dest, src, size)\ + _dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE16BYTE); + +/* + * Copy 'size' bytes from src to dest, in blocks of 32 bits (4 bytes). + * size is in bytes and must be a multiple of 4. + * Both src and dest must be aligned to 32 bits (4 bytes). + * Returns 0 on failure, non-zero on success. + */ +#define ds2_DMAcopy_32Bit(ch, dest, src, size)\ + _dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE32BIT); + +/* + * Copy 'size' bytes from src to dest, in blocks of 16 bits (2 bytes). + * size is in bytes and must be a multiple of 2. + * Both src and dest must be aligned to 16 bits (2 bytes). + * Returns 0 on failure, non-zero on success. + */ +#define ds2_DMAcopy_16Bit(ch, dest, src, size)\ + _dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE16BIT) + +/* + * Copy 'size' individual bytes (8 bits at a time) from src to dest. + * Returns 0 on failure, non-zero on success. + */ +#define ds2_DMAcopy_8Bit(ch, dest, src, size)\ + _dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE8BIT) + + + +//Stop DMA transfer +extern void dma_stop(int ch); + +#define ds2_DMA_stop(ch)\ + dma_stop(ch) + +//Wait DMA transfer over +extern int dma_wait_finish(int ch); + +#define ds2_DMA_wait(ch)\ + dma_wait_finish(ch) + + + +#ifdef __cplusplus +} +#endif + +#endif //__DMA_H__ + diff --git a/sdk-modifications/include/ds2_excpt.h b/sdk-modifications/include/ds2_excpt.h new file mode 100755 index 0000000..08fe77e --- /dev/null +++ b/sdk-modifications/include/ds2_excpt.h @@ -0,0 +1,55 @@ +#ifndef __DS2_EXCPT_H__ +#define __DS2_EXCPT_H__ + +#include +extern unsigned int Process_RA; +extern unsigned int Process_SP; + +#define SAVE_PROCESS_REGISTER() \ + do{ unsigned int sr ; \ + sr = read_c0_status(); \ + write_c0_status((sr&(~1))); \ + __asm__ __volatile__( \ + "sw $31,0x00(%0)\n\t" \ + "sw $29,0x00(%1)\n\t" \ + : \ + : "r" (&Process_RA),"r" (&Process_SP)); \ + write_c0_status(sr); \ + }while(0) + +#define RESTORE_PROCESS_REGISTER() \ + __asm__ __volatile__( \ + "lw $31,0x00(%0)\n\t" \ + "lw $29,0x00(%1)\n\t" \ + : \ + : "r" (&Process_RA),"r" (&Process_SP)) + +inline static void excpt_exit(x) \ +{ + unsigned int sr; + sr = read_c0_status(); + write_c0_status(sr & (~1)); + __asm__ __volatile__("lw $2,0x00(%0)\n\t" :: "r" (&x)); + RESTORE_PROCESS_REGISTER(); + write_c0_status(sr); + __asm__ __volatile__( + "jr $31\n\t" + "nop\n\t" + ); +} + +typedef void (*PFun_Exception_Handler)(unsigned int); + +//Setup handle to process the exception +//except_index: exception number +//except_handle: handle to process the exception +//arg: argument to the handle +extern int Setup_except_handle(unsigned int except_index, PFun_Exception_Handler except_handle, unsigned int arg); + +//Add a write watched exception, if the CPU write the addr, a exception will +// generated, the watch exception's number is 23 +//addr: address to be watched +extern void add_watch_point(unsigned int addr); + +#endif //__DS2_EXCPT_H__ + diff --git a/sdk-modifications/include/ds2_fcntl.h b/sdk-modifications/include/ds2_fcntl.h new file mode 100755 index 0000000..2c69221 --- /dev/null +++ b/sdk-modifications/include/ds2_fcntl.h @@ -0,0 +1,51 @@ +#ifndef __libc_fcntl_h__ +#define __libc_fcntl_h__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define O_RDONLY (1 << 0) +#define O_WRONLY (2 << 0) +#define O_RDWR (3 << 0) +#define O_APPEND (1 << 2) +#define O_CREAT (1 << 3) +#define O_DSYNC (1 << 4) +#define O_EXCL (1 << 5) +#define O_NOCTTY (1 << 6) +#define O_NONBLOCK (1 << 7) +#define O_RSYNC (1 << 8) +#define O_SYNC (1 << 9) +#define O_TRUNC (1 << 10) +#define O_CREATE O_CREAT + +#define O_ACCMODE 0x3 + +#define F_CLOEXEC (1 << 11) + +#define F_DUPFD 1 +#define F_GETFD 2 +#define F_SETFD 3 +#define F_GETFL 4 +#define F_SETFL 5 +#define F_GETLK 6 +#define F_SETLK 7 +#define F_SETLKW 8 +#define F_GETOWN 9 +#define F_SETOWN 10 +#define _F_LAST F_SETOWN + +#define _F_FILE_DESC (F_CLOEXEC) +#define _O_FILE_CREATE (O_CREAT | O_EXCL | O_NOCTTY | O_TRUNC) +#define _O_FILE_STATUS (O_APPEND | O_DSYNC | O_NONBLOCK | O_RSYNC | O_SYNC) +#define _O_UNSUPPORTED (0) + +extern int open(const char* path, int oflag, ...); +extern int fcntl(int fildes, int cmd, ...); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/sdk-modifications/include/ds2_malloc.h b/sdk-modifications/include/ds2_malloc.h new file mode 100755 index 0000000..5f158f7 --- /dev/null +++ b/sdk-modifications/include/ds2_malloc.h @@ -0,0 +1,32 @@ +#ifndef __DS2_MALLOC_H__ +#define __DS2_MALLOC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void heapInit(unsigned int start, unsigned int end); + +extern void* Drv_alloc(unsigned int nbytes); +extern void Drv_deAlloc(void* address); +extern void* Drv_realloc(void* address, unsigned int nbytes); +extern void* Drv_calloc(unsigned int nmem, unsigned int size); + +#ifdef __cplusplus +} +#endif + +#define malloc Drv_alloc +#define calloc Drv_calloc +#define realloc Drv_realloc +#define free Drv_deAlloc + +#ifdef __cplusplus +#include +inline void* operator new ( size_t s ) { return malloc( s ); } +inline void* operator new[] ( size_t s ) { return malloc( s ); } +inline void operator delete ( void* p ) { free( p ); } +inline void operator delete[] ( void* p ) { free( p ); } +#endif + +#endif //__DS2_MALLOC_H__ diff --git a/sdk-modifications/include/ds2_mmc_api.h b/sdk-modifications/include/ds2_mmc_api.h new file mode 100755 index 0000000..28e75ef --- /dev/null +++ b/sdk-modifications/include/ds2_mmc_api.h @@ -0,0 +1,56 @@ +#ifndef __MMC_API_H__ +#define __MMC_API_H__ + +/* Error codes */ +enum mmc_result_t { + MMC_NO_RESPONSE = -1, + MMC_NO_ERROR = 0, + MMC_ERROR_OUT_OF_RANGE, + MMC_ERROR_ADDRESS, + MMC_ERROR_BLOCK_LEN, + MMC_ERROR_ERASE_SEQ, + MMC_ERROR_ERASE_PARAM, + MMC_ERROR_WP_VIOLATION, + MMC_ERROR_CARD_IS_LOCKED, + MMC_ERROR_LOCK_UNLOCK_FAILED, + MMC_ERROR_COM_CRC, + MMC_ERROR_ILLEGAL_COMMAND, + MMC_ERROR_CARD_ECC_FAILED, + MMC_ERROR_CC, + MMC_ERROR_GENERAL, + MMC_ERROR_UNDERRUN, + MMC_ERROR_OVERRUN, + MMC_ERROR_CID_CSD_OVERWRITE, + MMC_ERROR_STATE_MISMATCH, + MMC_ERROR_HEADER_MISMATCH, + MMC_ERROR_TIMEOUT, + MMC_ERROR_CRC, + MMC_ERROR_DRIVER_FAILURE, +}; + + +/* Get card's sectors*/ + +extern unsigned int MMC_GetSize(void); + + +/* initialize MMC/SD card */ +extern int MMC_Initialize(void); + +/* read a single block from MMC/SD card */ +extern int MMC_ReadBlock(unsigned int blockaddr, unsigned char *recbuf); + +/* read multi blocks from MMC/SD card */ +extern int MMC_ReadMultiBlock(unsigned int blockaddr, unsigned int blocknum, unsigned char *recbuf); + +/* write a block to MMC/SD card */ +extern int MMC_WriteBlock(unsigned int blockaddr, unsigned char *recbuf); + +/* write multi blocks to MMC/SD card */ +extern int MMC_WriteMultiBlock(unsigned int blockaddr, unsigned int blocknum, unsigned char *recbuf); + +/* detect MMC/SD card */ +extern int MMC_DetectStatus(void); + +#endif /* __MMC_API_H__ */ + diff --git a/sdk-modifications/include/ds2_timer.h b/sdk-modifications/include/ds2_timer.h new file mode 100755 index 0000000..3e5c3bc --- /dev/null +++ b/sdk-modifications/include/ds2_timer.h @@ -0,0 +1,50 @@ +#ifndef __DS2_TIMER_H__ +#define __DS2_TIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* +* Function: register a timer interruptting periodly +* channel: timer id, from 0 to 1 +* period: interrupt period, unit is us, period < 2.5s +* handle: interrupt handle, if handle = NULL, the timer will not generate interrupt +* arg: argument to the interrupt handle +*/ +extern int initTimer(unsigned int channel, unsigned int period, void (*handle)(unsigned int), int arg); + +/* +* Function: set the timer run +*/ +extern void runTimer(unsigned int channel); + +/* +* Function: stop timer +*/ +extern void stopTimer(unsigned int channel); + +/* +* Function: reset timer +*/ +extern void resetTimer(unsigned int channel); + +/* +* Function: read value of timer +*/ +extern unsigned int readTimer(unsigned int channel); + + +#define SYSTIME_UNIT 42667 +/* +* Function: get the elapsed time since DS2 started +* it's uint is 42.667us, it will overflow after 50.9 horus since DS2 started +*/ +extern unsigned int getSysTime(void); + +#ifdef __cplusplus +} +#endif + +#endif //__DS2_TIMER_H__ + diff --git a/sdk-modifications/include/ds2_types.h b/sdk-modifications/include/ds2_types.h new file mode 100755 index 0000000..3ec59bf --- /dev/null +++ b/sdk-modifications/include/ds2_types.h @@ -0,0 +1,45 @@ +#ifndef __DS2_TYPES_H__ +#define __DS2_TYPES_H__ + +#ifndef u8 +#define u8 unsigned char +#endif + +#ifndef s8 +#define s8 char +#endif + +#ifndef u16 +#define u16 unsigned short +#endif + +#ifndef s16 +#define s16 short +#endif + +#ifndef u32 +#define u32 unsigned int +#endif + +#ifndef s32 +#define s32 int +#endif + +#ifndef u64 +#define u64 unsigned long long +#endif + +#ifndef s64 +#define s64 long long +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#define FALSE 0 +#endif + +#endif //__DS2_TYPES_H__ diff --git a/sdk-modifications/include/ds2io.h b/sdk-modifications/include/ds2io.h new file mode 100755 index 0000000..e715cef --- /dev/null +++ b/sdk-modifications/include/ds2io.h @@ -0,0 +1,285 @@ +#ifndef __DS2IO_H__ +#define __DS2IO_H__ + +#ifndef BIT +#define BIT(a) (1< +#include "partition.h" +#include "directory.h" +#include "file_allocation_table.h" +//#include "unicode/unicode.h" +#include "fatdir_ex.h" +#include "fatfile_ex.h" + +//typedef enum {PI_DEFAULT, PI_SLOT_1, PI_SLOT_2, PI_CUSTOM} PARTITION_INTERFACE; + +struct IO_INTERFACE_STRUCT ; + +/* +Initialise any inserted block-devices. +Add the fat device driver to the devoptab, making it available for standard file functions. +cacheSize: The number of pages to allocate for each inserted block-device +setAsDefaultDevice: if true, make this the default device driver for file operations +*/ +bool fatInit (u32 cacheSize, bool setAsDefaultDevice); + +/* +Calls fatInit with setAsDefaultDevice = true and cacheSize optimised for the host system. +*/ +bool fatInitDefault (void); + +/* +Special initialize for RPG card +*/ +bool fatInitRPG (void); + +/* +Mount the device specified by partitionNumber +PD_DEFAULT is not allowed, use _FAT_partition_setDefaultDevice +PD_CUSTOM is not allowed, use _FAT_partition_mountCustomDevice +*/ +bool fatMountNormalInterface (PARTITION_INTERFACE partitionNumber, u32 cacheSize); + +/* +Mount a partition on a custom device +*/ +bool fatMountCustomInterface (struct IO_INTERFACE_STRUCT* device, u32 cacheSize); + +/* +Unmount the partition specified by partitionNumber +If there are open files, it will fail +*/ +bool fatUnmount (PARTITION_INTERFACE partitionNumber); + + +/* +Forcibly unmount the partition specified by partitionNumber +Any open files on the partition will become invalid +The cache will be invalidated, and any unflushed writes will be lost +*/ +bool fatUnsafeUnmount (PARTITION_INTERFACE partitionNumber); + +/* +Set the default device for access by fat: and fat0: +PD_DEFAULT is unallowed. +Doesn't do anything useful on GBA, since there is only one device +*/ +bool fatSetDefaultInterface (PARTITION_INTERFACE partitionNumber); + +#ifdef __cplusplus +} +#endif + +#endif // _LIBFAT_H diff --git a/sdk-modifications/include/fatdir.h b/sdk-modifications/include/fatdir.h new file mode 100755 index 0000000..529e401 --- /dev/null +++ b/sdk-modifications/include/fatdir.h @@ -0,0 +1,81 @@ +/* + fatdir.h + + Functions used by the newlib disc stubs to interface with + this library + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-08-13 - Chishm + * Moved all externally visible directory related functions to fatdir + * Added _FAT_mkdir_r + + 2006-08-14 - Chishm + * Added directory iterator functions + + 2007-01-10 - Chishm + * Updated directory iterator functions for DevkitPro r20 +*/ + + +#ifndef _FATDIR_H +#define _FATDIR_H + +//#include +#include +//#include +#include "fs_common.h" +#include "directory.h" + +typedef struct { + PARTITION* partition; + DIR_ENTRY currentEntry; + u32 startCluster; + u32 posEntry; + bool inUse; + bool validEntry; +} DIR_STATE_STRUCT; + +extern int _FAT_stat_r (struct _reent *r, const char *path, struct stat *st); + +extern int _FAT_link_r (struct _reent *r, const char *existing, const char *newLink); + +extern int _FAT_unlink_r (struct _reent *r, const char *name); + +extern int _FAT_chdir_r (struct _reent *r, const char *name); + +extern int _FAT_rename_r (struct _reent *r, const char *oldName, const char *newName); + +extern int _FAT_mkdir_r (struct _reent *r, const char *path, int mode); + +/* +Directory iterator functions +*/ +extern DIR_STATE_STRUCT* _FAT_diropen_r(struct _reent *r, DIR_STATE_STRUCT *dirState, const char *path); +extern int _FAT_dirreset_r (struct _reent *r, DIR_STATE_STRUCT *dirState); +extern int _FAT_dirnext_r (struct _reent *r, DIR_STATE_STRUCT *dirState, struct stat *filestat); +extern int _FAT_dirclose_r (struct _reent *r, DIR_STATE_STRUCT *dirState); + + +#endif // _FATDIR_H diff --git a/sdk-modifications/include/fatdir_ex.h b/sdk-modifications/include/fatdir_ex.h new file mode 100755 index 0000000..fbac46f --- /dev/null +++ b/sdk-modifications/include/fatdir_ex.h @@ -0,0 +1,18 @@ +#ifndef _FATDIR_EX_H_ +#define _FATDIR_EX_H_ + +#include "fatdir.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int dirnextl (DIR_ITER *dirState, char *filename, char *longFilename, struct stat *filestat); +int renamex( const char *oldName, const char *newName ); + +#ifdef __cplusplus +} +#endif + + +#endif//_FATDIR_EX_H_ diff --git a/sdk-modifications/include/fatfile.h b/sdk-modifications/include/fatfile.h new file mode 100755 index 0000000..4869562 --- /dev/null +++ b/sdk-modifications/include/fatfile.h @@ -0,0 +1,89 @@ +/* + fatfile.h + + Functions used by the newlib disc stubs to interface with + this library + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-07-11 - Chishm + * Original release + + 2006-07-17 - Chishm + * Made all path inputs const char* + * Added _FAT_rename_r + + 2006-07-24 - Chishm + * Removed padding workaround from FILE_STRUCT + + 2006-08-13 - Chishm + * Moved all externally visible directory related functions to fatdir +*/ + + +#ifndef _FATFILE_H +#define _FATFILE_H + +//#include +#include + +#include "fs_common.h" +#include "partition.h" +#include "directory.h" + +typedef struct { + u32 cluster; + u32 sector; + s32 byte; +} FILE_POSITION; + +typedef struct { + int fd; + u32 filesize; + u32 startCluster; + u32 currentPosition; + FILE_POSITION rwPosition; + FILE_POSITION appendPosition; + bool read; + bool write; + bool append; + bool inUse; + PARTITION* partition; + DIR_ENTRY_POSITION dirEntryStart; // Points to the start of the LFN entries of a file, or the alias for no LFN + DIR_ENTRY_POSITION dirEntryEnd; // Always points to the file's alias entry +} FILE_STRUCT; + +extern int _FAT_open_r (struct _reent *r, void *fileStruct, const char *path, int flags); + +extern int _FAT_close_r (struct _reent *r, int fd); + +extern int _FAT_write_r (struct _reent *r,int fd, const char *ptr, int len); + +extern int _FAT_read_r (struct _reent *r, int fd, char *ptr, int len); + +extern int _FAT_seek_r (struct _reent *r, int fd,int pos, int dir); + +extern int _FAT_fstat_r (struct _reent *r, int fd, struct stat *st); + +#endif // _FATFILE_H diff --git a/sdk-modifications/include/fatfile_ex.h b/sdk-modifications/include/fatfile_ex.h new file mode 100755 index 0000000..c434b63 --- /dev/null +++ b/sdk-modifications/include/fatfile_ex.h @@ -0,0 +1,19 @@ +#ifndef _FATFILE_EX_H_ +#define _FATFILE_EX_H_ + +#include +#include "fatfile.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int freadex( void * buffer, int _size, int _n, FILE * f ); +int fwritex( const void * buffer, int _size, int _n, FILE * f ); + +#ifdef __cplusplus +} +#endif + + +#endif//_FATFILE_EX_H_ diff --git a/sdk-modifications/include/file_allocation_table.h b/sdk-modifications/include/file_allocation_table.h new file mode 100755 index 0000000..4fb4149 --- /dev/null +++ b/sdk-modifications/include/file_allocation_table.h @@ -0,0 +1,64 @@ +/* + file_allocation_table.h + Reading, writing and manipulation of the FAT structure on + a FAT partition + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-07-11 - Chishm + * Original release + + 2006-10-01 - Chishm + * Added _FAT_fat_linkFreeClusterCleared to clear a cluster when it is allocated +*/ + +#ifndef _FAT_H +#define _FAT_H + +#include "fs_common.h" +#include "partition.h" + +#define CLUSTER_EOF_16 0xFFFF +#define CLUSTER_EOF 0x0FFFFFFF +#define CLUSTER_FREE 0x0000 +#define CLUSTER_FIRST 0x0002 + +#define CLUSTERS_PER_FAT12 4085 +#define CLUSTERS_PER_FAT16 65525 + + +u32 _FAT_fat_nextCluster(PARTITION* partition, u32 cluster); + +u32 _FAT_fat_linkFreeCluster(PARTITION* partition, u32 cluster); +u32 _FAT_fat_linkFreeClusterCleared (PARTITION* partition, u32 cluster); + +bool _FAT_fat_clearLinks (PARTITION* partition, u32 cluster); + +u32 _FAT_fat_lastCluster (PARTITION* partition, u32 cluster); + +static inline u32 _FAT_fat_clusterToSector (PARTITION* partition, u32 cluster) { + return (cluster >= 2) ? ((cluster - 2) * partition->sectorsPerCluster) + partition->dataStart : partition->rootDirStart; +} + +#endif // _FAT_H diff --git a/sdk-modifications/include/filetime.h b/sdk-modifications/include/filetime.h new file mode 100755 index 0000000..fa651a7 --- /dev/null +++ b/sdk-modifications/include/filetime.h @@ -0,0 +1,44 @@ +/* + filetime.h + Conversion of file time and date values to various other types + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-07-11 - Chishm + * Original release +*/ + +#ifndef _FILETIME_H +#define _FILETIME_H + +#include "fs_common.h" +#include + +u16 _FAT_filetime_getTimeFromRTC (void); +u16 _FAT_filetime_getDateFromRTC (void); + +time_t _FAT_filetime_to_time_t (u16 time, u16 date); + + +#endif // _FILETIME_H diff --git a/sdk-modifications/include/fs_api.h b/sdk-modifications/include/fs_api.h new file mode 100755 index 0000000..b3431b6 --- /dev/null +++ b/sdk-modifications/include/fs_api.h @@ -0,0 +1,151 @@ +#ifndef __FS_API_H__ +#define __FS_API_H__ +//v1.0 + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sys/stat.h" +#include "fatfile.h" +#include "fatdir.h" + + +#define mode_t unsigned int +#define size_t unsigned int + +extern int fat_init(void); + +extern FILE_STRUCT* fat_fopen(const char *file, const char *mode); + +extern size_t fat_fread(void *buf, size_t size, size_t count, FILE_STRUCT *fp); + +extern size_t fat_fwrite(const void *buf, size_t size, size_t count, FILE_STRUCT *fp); + +extern int fat_fclose(FILE_STRUCT *fp); + +extern int fat_fseek(FILE_STRUCT *fp, long offset, int whence); + +extern long fat_ftell(FILE_STRUCT *fp); + +extern int fat_feof(FILE_STRUCT *fp); + +extern int fat_ferror(FILE_STRUCT *fp); + +extern void fat_clearerr(FILE_STRUCT *fp); + +extern int fat_fflush(FILE_STRUCT *fp); + +extern int fat_fgetc(FILE_STRUCT *fp); + +extern char* fat_fgets(char *buf, int n, FILE_STRUCT *fp); + +extern int fat_fputc(int ch, FILE_STRUCT *fp); + +extern int fat_fputs(const char *s, FILE_STRUCT *fp); + +extern int fat_remove(const char *filename); + +extern int fat_rename(const char *oldName, const char *newName); + +extern int fat_setHidden(const char *name, unsigned char hide); + +extern int fat_isHidden(struct stat *st); + +extern int fat_getShortName(const char *fullName, char *outName); + +extern void fat_rewind(FILE_STRUCT *fp); + +extern int fat_fstat(int fildes, struct stat *buf); + +extern int fat_fprintf(void* fp, const char *format, ...); + +extern int fat_fscanf(FILE_STRUCT *fp, const char *format, ...); + +extern DIR_STATE_STRUCT* fat_opendir(const char *name); + +extern DIR_ENTRY* fat_readdir(DIR_STATE_STRUCT *dirp); + +extern long fat_telldir(DIR_STATE_STRUCT *dirp); + +extern void fat_seekdir(DIR_STATE_STRUCT *dirp, long int loc); + +extern int fat_closedir(DIR_STATE_STRUCT *dirp); + +extern int fat_chdir(const char *path); + +extern char* fat_getcwd(char *buf, size_t size); + +extern int fat_mkdir(const char *path, mode_t mode); + +extern int fat_rmdir(const char *path); + +extern int fat_lstat(const char *path, struct stat *buf); + +extern DIR_ENTRY* fat_readdir_ex(DIR_STATE_STRUCT *dirp, struct stat *statbuf); + +#ifndef SEEK_SET +#define SEEK_SET 0 /* Seek from beginning of file. */ +#endif + +#ifndef SEEK_CUR +#define SEEK_CUR 1 /* Seek from current position. */ +#endif + +#ifndef SEEK_END +#define SEEK_END 2 /* Seek from end of file. */ +#endif + +//#define S_ISDIR(st) (st.st_mode & S_IFDIR) + +#define FILE FILE_STRUCT +#define fopen fat_fopen +#define fread fat_fread +#define fwrite fat_fwrite +#define fclose fat_fclose +#define fgets fat_fgets +#define fseek fat_fseek +#define ftell fat_ftell +#define feof fat_feof +#define ferror fat_ferror +#define fclearerr fat_clearerr +#define fflush fat_fflush +#define fgetc fat_fgetc +#define fgets fat_fgets +#define fputc fat_fputc +#define fputs fat_fputs +#define fprintf fat_fprintf +#define fscanf fat_fscanf +#define remove fat_remove + +#define DIR DIR_STATE_STRUCT +#define dirent DIR_ENTRY +#define opendir fat_opendir +#define readdir fat_readdir +#define telldir fat_telldir +#define seekdir fat_seekdir +#define closedir fat_closedir +#define chdir fat_chdir +#define getcwd fat_getcwd +#define mkdir fat_mkdir +#define rmdir fat_rmdir + +#define lstat fat_lstat +#define fstat fat_fstat + +#define S_ISHID(st_mode) ((st_mode & S_IHIDDEN) != 0) + +//the extended version of readdir_ex +#define readdir_ex fat_readdir_ex + +#define MAX_PATH 512 +#define MAX_FILE 512 + +//Misc function +extern bool fat_getDiskSpaceInfo( char * diskName, unsigned int *total, unsigned int *used, unsigned int *freeSpace ); + +#ifdef __cplusplus +} +#endif + +#endif //__FS_API_H__ diff --git a/sdk-modifications/include/fs_cache.h b/sdk-modifications/include/fs_cache.h new file mode 100755 index 0000000..b0ab9be --- /dev/null +++ b/sdk-modifications/include/fs_cache.h @@ -0,0 +1,118 @@ +/* + cache.h + The cache is not visible to the user. It should be flushed + when any file is closed or changes are made to the filesystem. + + This cache implements a least-used-page replacement policy. This will + distribute sectors evenly over the pages, so if less than the maximum + pages are used at once, they should all eventually remain in the cache. + This also has the benefit of throwing out old sectors, so as not to keep + too many stale pages around. + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-07-11 - Chishm + * Original release +*/ + +#ifndef _CACHE_H +#define _CACHE_H + +#include "fs_common.h" +#include "disc_io/disc_io.h" + +#define CACHE_PAGE_SIZE BYTES_PER_READ + +typedef struct { + u32 sector; + u32 count; + bool dirty; +} CACHE_ENTRY; + +typedef struct { + const IO_INTERFACE* disc; + u32 numberOfPages; + CACHE_ENTRY* cacheEntries; + u8* pages; +} CACHE; + + +/* +Read data from a sector in the cache +If the sector is not in the cache, it will be swapped in +offset is the position to start reading from +size is the amount of data to read +Precondition: offset + size <= BYTES_PER_READ +*/ +bool _FAT_cache_readPartialSector (CACHE* cache, void* buffer, u32 sector, u32 offset, u32 size); + +/* +Write data to a sector in the cache +If the sector is not in the cache, it will be swapped in. +When the sector is swapped out, the data will be written to the disc +offset is the position to start reading from +size is the amount of data to read +Precondition: offset + size <= BYTES_PER_READ +*/ +bool _FAT_cache_writePartialSector (CACHE* cache, const void* buffer, u32 sector, u32 offset, u32 size); + +/* +Write data to a sector in the cache, zeroing the sector first +If the sector is not in the cache, it will be swapped in. +When the sector is swapped out, the data will be written to the disc +offset is the position to start reading from +size is the amount of data to read +Precondition: offset + size <= BYTES_PER_READ +*/ +bool _FAT_cache_eraseWritePartialSector (CACHE* cache, const void* buffer, u32 sector, u32 offset, u32 size); + +/* +Read a full sector from the cache +*/ +static inline bool _FAT_cache_readSector (CACHE* cache, void* buffer, u32 sector) { + return _FAT_cache_readPartialSector (cache, buffer, sector, 0, BYTES_PER_READ); +} + +/* +Write a full sector to the cache +*/ +static inline bool _FAT_cache_writeSector (CACHE* cache, const void* buffer, u32 sector) { + return _FAT_cache_writePartialSector (cache, buffer, sector, 0, BYTES_PER_READ); +} + +/* +Write any dirty sectors back to disc and clear out the contents of the cache +*/ +bool _FAT_cache_flush (CACHE* cache); + +/* +Clear out the contents of the cache without writing any dirty sectors first +*/ +void _FAT_cache_invalidate (CACHE* cache); + +CACHE* _FAT_cache_constructor (u32 numberOfPages, const IO_INTERFACE* discInterface); + +void _FAT_cache_destructor (CACHE* cache); + +#endif // _CACHE_H diff --git a/sdk-modifications/include/fs_common.h b/sdk-modifications/include/fs_common.h new file mode 100755 index 0000000..c482775 --- /dev/null +++ b/sdk-modifications/include/fs_common.h @@ -0,0 +1,129 @@ +/* + common.h + Common definitions and included files for the FATlib + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-07-11 - Chishm + * Original release +*/ + +#ifndef _COMMON_H +#define _COMMON_H + +// When compiling for NDS, make sure NDS is defined +#ifndef NDS + #if defined ARM9 || defined ARM7 + #define NDS + #endif +#endif + +#if 0 +#ifdef NDS + #include +#else + #include "gba_types.h" +#endif +#endif + +#define BYTES_PER_READ 512 + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef bool +#define bool int +#endif + +#ifndef false +#define false 0 +#endif + +#ifndef true +#define true 1 +#endif + +#ifndef u8 +#define u8 unsigned char +#endif + +#ifndef u16 +#define u16 unsigned short +#endif + +#ifndef u32 +#define u32 unsigned long +#endif + +#ifndef s32 +#define s32 long +#endif + +struct _reent +{ + /* FILE is a big struct and may change over time. To try to achieve binary + compatibility with future versions, put stdin,stdout,stderr here. + These are pointers into member __sf defined below. */ +// __FILE *_stdin, *_stdout, *_stderr; /* XXX */ + + int _errno; /* local copy of errno */ + +// int _inc; /* used by tmpnam */ + +// char *_emergency; + +// int __sdidinit; /* 1 means stdio has been init'd */ + +// int _current_category; /* unused */ +// _CONST char *_current_locale; /* unused */ + +// struct _mprec *_mp; + +// void _EXFNPTR(__cleanup, (struct _reent *)); + +// int _gamma_signgam; + + /* used by some fp conversion routines */ +// int _cvtlen; /* should be size_t */ +// char *_cvtbuf; + +// struct _rand48 *_r48; +// struct __tm *_localtime_buf; +// char *_asctime_buf; + + /* signal info */ +// void (**(_sig_func))(int); + + /* atexit stuff */ +// struct _atexit *_atexit; +// struct _atexit _atexit0; + +// struct _glue __sglue; /* root of glue chain */ +// __FILE *__sf; /* file descriptors */ +// struct _misc_reent *_misc; /* strtok, multibyte states */ +// char *_signal_buf; /* strsignal */ +}; + +#endif // _COMMON_H diff --git a/sdk-modifications/include/fs_unicode.h b/sdk-modifications/include/fs_unicode.h new file mode 100755 index 0000000..45e9d0a --- /dev/null +++ b/sdk-modifications/include/fs_unicode.h @@ -0,0 +1,16 @@ +#ifndef __FS_UNICODE_H__ +#define __FS_UNICODE_H__ + +extern void _FAT_utf8_to_unicode16( const char* src, u16* dest ); + +extern void _FAT_unicode16_to_utf8( const u16* src, char* dest); + +extern u32 _unistrnlen( const u16* unistr, u32 maxlen ); + +extern int _unistrncmp( const u16 * src, const u16 * dest, u32 maxlen ); + +extern const u16 * _unistrchr( const u16 * str, u16 unichar ); + +int _uniisalnum( u8 ch ); + +#endif //__FS_UNICODE_H__ diff --git a/sdk-modifications/include/mem_allocate.h b/sdk-modifications/include/mem_allocate.h new file mode 100755 index 0000000..844f6df --- /dev/null +++ b/sdk-modifications/include/mem_allocate.h @@ -0,0 +1,47 @@ +/* + mem_allocate.h + Memory allocation and destruction calls + Replace these calls with custom allocators if + malloc is unavailable + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-07-11 - Chishm + * Original release +*/ + +#ifndef _MEM_ALLOCATE_H +#define _MEM_ALLOCATE_H + +#include "ds2_malloc.h" + +static inline void* _FAT_mem_allocate (size_t size) { + return ((void*)malloc (size)); +} + +static inline void _FAT_mem_free (void* mem) { + return (free ((void*)mem)); +} + +#endif // _MEM_ALLOCATE_H diff --git a/sdk-modifications/include/mips.h b/sdk-modifications/include/mips.h new file mode 100755 index 0000000..3792565 --- /dev/null +++ b/sdk-modifications/include/mips.h @@ -0,0 +1,820 @@ +/************************************************************************** +* * +* PROJECT : MIPS port for uC/OS-II * +* * +* MODULE : MIPS.h * +* * +* AUTHOR : Michael Anburaj * +* URL : http://geocities.com/michaelanburaj/ * +* EMAIL: michaelanburaj@hotmail.com * +* * +* PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board * +* * +* TOOL-CHAIN : SDE & Cygnus * +* * +* DESCRIPTION : * +* MIPS processor definitions. * +* The basic CPU definitions are found in the file archdefs.h, which * +* is included by mips.h. * +* * +* mips.h implements aliases for some of the definitions in archdefs.h * +* and adds various definitions. * +* * +**************************************************************************/ + + +#ifndef __MIPS_H__ +#define __MIPS_H__ + +#include "archdefs.h" + + +/* ********************************************************************* */ +/* Module configuration */ + + +/* ********************************************************************* */ +/* Interface macro & data definition */ + +#ifndef MSK +#define MSK(n) ((1 << (n)) - 1) +#endif + +/* CPU registers */ +#define SYS_CPUREG_ZERO 0 +#define SYS_CPUREG_AT 1 +#define SYS_CPUREG_V0 2 +#define SYS_CPUREG_V1 3 +#define SYS_CPUREG_A0 4 +#define SYS_CPUREG_A1 5 +#define SYS_CPUREG_A2 6 +#define SYS_CPUREG_A3 7 +#define SYS_CPUREG_T0 8 +#define SYS_CPUREG_T1 9 +#define SYS_CPUREG_T2 10 +#define SYS_CPUREG_T3 11 +#define SYS_CPUREG_T4 12 +#define SYS_CPUREG_T5 13 +#define SYS_CPUREG_T6 14 +#define SYS_CPUREG_T7 15 +#define SYS_CPUREG_S0 16 +#define SYS_CPUREG_S1 17 +#define SYS_CPUREG_S2 18 +#define SYS_CPUREG_S3 19 +#define SYS_CPUREG_S4 20 +#define SYS_CPUREG_S5 21 +#define SYS_CPUREG_S6 22 +#define SYS_CPUREG_S7 23 +#define SYS_CPUREG_T8 24 +#define SYS_CPUREG_T9 25 +#define SYS_CPUREG_K0 26 +#define SYS_CPUREG_K1 27 +#define SYS_CPUREG_GP 28 +#define SYS_CPUREG_SP 29 +#define SYS_CPUREG_S8 30 +#define SYS_CPUREG_FP SYS_CPUREG_S8 +#define SYS_CPUREG_RA 31 + + +/* CPU register fp ($30) has an alias s8 */ +#define s8 fp + + +/* Aliases for System Control Coprocessor (CP0) registers */ +#define C0_INDEX C0_Index +#define C0_RANDOM C0_Random +#define C0_ENTRYLO0 C0_EntryLo0 +#define C0_ENTRYLO1 C0_EntryLo1 +#define C0_CONTEXT C0_Context +#define C0_PAGEMASK C0_PageMask +#define C0_WIRED C0_Wired +#define C0_BADVADDR C0_BadVAddr +#define C0_COUNT C0_Count +#define C0_ENTRYHI C0_EntryHi +#define C0_COMPARE C0_Compare +#define C0_STATUS C0_Status +#define C0_CAUSE C0_Cause + +#ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */ +#undef C0_PRID +#endif +#define C0_PRID C0_PRId + +#define C0_CONFIG C0_Config +#define C0_CONFIG1 C0_Config1 +#define C0_LLADDR C0_LLAddr +#define C0_WATCHLO C0_WatchLo +#define C0_WATCHHI C0_WatchHi +#define C0_DEBUG C0_Debug +#define C0_PERFCNT C0_PerfCnt +#define C0_ERRCTL C0_ErrCtl +#define C0_CACHEERR C0_CacheErr +#define C0_TAGLO C0_TagLo +#define C0_DATALO C0_DataLo +#define C0_TAGHI C0_TagHi +#define C0_DATAHI C0_DataHi +#define C0_ERROREPC C0_ErrorEPC +#if 0 +#define C0_DESAVE C0_DESAVE +#define C0_EPC C0_EPC +#define C0_DEPC C0_DEPC +#endif + +/* System Control Coprocessor (CP0) registers select fields */ +#define C0_INDEX_SEL 0 /* TLB Index */ +#define C0_RANDOM_SEL 0 /* TLB Random */ +#define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */ +#define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */ +#define C0_CONTEXT_SEL 0 /* Context */ +#define C0_PAGEMASK_SEL 0 /* TLB PageMask */ +#define C0_WIRED_SEL 0 /* TLB Wired */ +#define C0_BADVADDR_SEL 0 /* Bad Virtual Address */ +#define C0_COUNT_SEL 0 /* Count */ +#define C0_ENTRYHI_SEL 0 /* TLB EntryHi */ +#define C0_COMPARE_SEL 0 /* Compare */ +#define C0_STATUS_SEL 0 /* Processor Status */ +#define C0_CAUSE_SEL 0 /* Exception Cause */ +#define C0_EPC_SEL 0 /* Exception PC */ +#define C0_PRID_SEL 0 /* Processor Revision Indentifier */ +#define C0_CONFIG_SEL 0 /* Config */ +#define C0_CONFIG1_SEL 1 /* Config1 */ +#define C0_LLADDR_SEL 0 /* LLAddr */ +#define C0_WATCHLO_SEL 0 /* WatchpointLo */ +#define C0_WATCHHI_SEL 0 /* WatchpointHi */ +#define C0_DEBUG_SEL 0 /* EJTAG Debug Register */ +#define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */ +#define C0_PERFCNT_SEL 0 /* Performance counter interface */ +#define C0_ERRCTL_SEL 0 /* ERRCTL */ +#define C0_CACHEERR_SEL 0 /* CacheErr */ +#define C0_TAGLO_SEL 0 /* TagLo */ +#define C0_DATALO_SEL 1 /* DataLo */ +#define C0_DTAGLO_SEL 2 /* DTagLo */ +#define C0_TAGHI_SEL 0 /* TagHi */ +#define C0_DATAHI_SEL 1 /* DataHi */ +#define C0_DTAGHI_SEL 2 /* DTagHi */ +#define C0_ERROREPC_SEL 0 /* ErrorEPC */ +#define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */ + + +/* C0_CONFIG register encoding */ + +#define C0_CONFIG_M_SHF S_ConfigMore +#define C0_CONFIG_M_MSK M_ConfigMore +#define C0_CONFIG_M_BIT C0_CONFIG_M_MSK + +#define C0_CONFIG_BE_SHF S_ConfigBE +#define C0_CONFIG_BE_MSK M_ConfigBE +#define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK + +#define C0_CONFIG_AT_SHF S_ConfigAT +#define C0_CONFIG_AT_MSK M_ConfigAT +#define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32 +#define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S +#define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64 + +#define C0_CONFIG_AR_SHF S_ConfigAR +#define C0_CONFIG_AR_MSK M_ConfigAR + +#define C0_CONFIG_MT_SHF S_ConfigMT +#define C0_CONFIG_MT_MSK M_ConfigMT +#define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU +#define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU +#define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU +#define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU + +#define C0_CONFIG_K0_SHF S_ConfigK0 +#define C0_CONFIG_K0_MSK M_ConfigK0 +#define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA +#define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA +#define C0_CONFIG_K0_UNCACHED K_CacheAttrU +#define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN +#define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE +#define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS +#define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU +#define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA + + +/* WC field. + * + * This feature is present specifically to support configuration + * testing of the core in a lead vehicle, and is not supported + * in any other environment. Attempting to use this feature + * outside of the scope of a lead vehicle is a violation of the + * MIPS Architecture, and may cause unpredictable operation of + * the processor. + */ +#define C0_CONFIG_WC_SHF 19 +#define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF) +#define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK + + +/* C0_CONFIG1 register encoding */ + +#define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize +#define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize + +#define C0_CONFIG1_IS_SHF S_Config1IS +#define C0_CONFIG1_IS_MSK M_Config1IS + +#define C0_CONFIG1_IL_SHF S_Config1IL +#define C0_CONFIG1_IL_MSK M_Config1IL + +#define C0_CONFIG1_IA_SHF S_Config1IA +#define C0_CONFIG1_IA_MSK M_Config1IA + +#define C0_CONFIG1_DS_SHF S_Config1DS +#define C0_CONFIG1_DS_MSK M_Config1DS + +#define C0_CONFIG1_DL_SHF S_Config1DL +#define C0_CONFIG1_DL_MSK M_Config1DL + +#define C0_CONFIG1_DA_SHF S_Config1DA +#define C0_CONFIG1_DA_MSK M_Config1DA + +#define C0_CONFIG1_WR_SHF S_Config1WR +#define C0_CONFIG1_WR_MSK M_Config1WR +#define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK + +#define C0_CONFIG1_CA_SHF S_Config1CA +#define C0_CONFIG1_CA_MSK M_Config1CA +#define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK + +#define C0_CONFIG1_EP_SHF S_Config1EP +#define C0_CONFIG1_EP_MSK M_Config1EP +#define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK + +#define C0_CONFIG1_FP_SHF S_Config1FP +#define C0_CONFIG1_FP_MSK M_Config1FP +#define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK + + +/* C0_STATUS register encoding */ + +#define C0_STATUS_CU3_SHF S_StatusCU3 +#define C0_STATUS_CU3_MSK M_StatusCU3 +#define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK + +#define C0_STATUS_CU2_SHF S_StatusCU2 +#define C0_STATUS_CU2_MSK M_StatusCU2 +#define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK + +#define C0_STATUS_CU1_SHF S_StatusCU1 +#define C0_STATUS_CU1_MSK M_StatusCU1 +#define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK + +#define C0_STATUS_CU0_SHF S_StatusCU1 +#define C0_STATUS_CU0_MSK M_StatusCU1 +#define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK + +#define C0_STATUS_RP_SHF S_StatusRP +#define C0_STATUS_RP_MSK M_StatusRP +#define C0_STATUS_RP_BIT C0_STATUS_RP_MSK + +#define C0_STATUS_FR_SHF S_StatusFR +#define C0_STATUS_FR_MSK M_StatusFR +#define C0_STATUS_FR_BIT C0_STATUS_FR_MSK + +#define C0_STATUS_RE_SHF S_StatusRE +#define C0_STATUS_RE_MSK M_StatusRE +#define C0_STATUS_RE_BIT C0_STATUS_RE_MSK + +#define C0_STATUS_BEV_SHF S_StatusBEV +#define C0_STATUS_BEV_MSK M_StatusBEV +#define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK + +#define C0_STATUS_TS_SHF S_StatusTS +#define C0_STATUS_TS_MSK M_StatusTS +#define C0_STATUS_TS_BIT C0_STATUS_TS_MSK + +#define C0_STATUS_SR_SHF S_StatusSR +#define C0_STATUS_SR_MSK M_StatusSR +#define C0_STATUS_SR_BIT C0_STATUS_SR_MSK + +#define C0_STATUS_NMI_SHF S_StatusNMI +#define C0_STATUS_NMI_MSK M_StatusNMI +#define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK + +#define C0_STATUS_IM_SHF S_StatusIM +#define C0_STATUS_IM_MSK M_StatusIM +/* Note that the the definitions below indicate the interrupt number + * rather than the mask. + * (0..1 for SW interrupts and 2...7 for HW interrupts) + */ +#define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM) +#define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM) +#define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM) +#define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM) +#define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM) +#define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM) +#define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM) +#define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM) + +/* Max interrupt code */ +#define C0_STATUS_IM_MAX C0_STATUS_IM_HW5 + +#define C0_STATUS_KSU_SHF S_StatusKSU +#define C0_STATUS_KSU_MSK M_StatusKSU + +#define C0_STATUS_UM_SHF S_StatusUM +#define C0_STATUS_UM_MSK M_StatusUM +#define C0_STATUS_UM_BIT C0_STATUS_UM_MSK + +#define C0_STATUS_ERL_SHF S_StatusERL +#define C0_STATUS_ERL_MSK M_StatusERL +#define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK + +#define C0_STATUS_EXL_SHF S_StatusEXL +#define C0_STATUS_EXL_MSK M_StatusEXL +#define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK + +#define C0_STATUS_IE_SHF S_StatusIE +#define C0_STATUS_IE_MSK M_StatusIE +#define C0_STATUS_IE_BIT C0_STATUS_IE_MSK + + +/* C0_PRID register encoding */ + +#define C0_PRID_OPT_SHF S_PRIdCoOpt +#define C0_PRID_OPT_MSK M_PRIdCoOpt + +#define C0_PRID_COMP_SHF S_PRIdCoID +#define C0_PRID_COMP_MSK M_PRIdCoID +#define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS +#define C0_PRID_COMP_NOT_MIPS32_64 0 + +#define C0_PRID_PRID_SHF S_PRIdImp +#define C0_PRID_PRID_MSK M_PRIdImp + +/* Jade */ +#define C0_PRID_PRID_4Kc K_PRIdImp_Jade +#define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */ +/* Emerald */ +#define C0_PRID_PRID_4KEc K_PRIdImp_4KEc +#define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp +/* Coral */ +#define C0_PRID_PRID_4KSc K_PRIdImp_4KSc +/* Opal */ +#define C0_PRID_PRID_5K K_PRIdImp_Opal +/* Ruby */ +#define C0_PRID_PRID_20Kc K_PRIdImp_Ruby +/* Other CPUs */ +#define C0_PRID_PRID_R4000 K_PRIdImp_R4000 +#define C0_PRID_PRID_RM52XX K_PRIdImp_R5200 +#define C0_PRID_PRID_RM70XX 0x27 + +#define C0_PRID_REV_SHF S_PRIdRev +#define C0_PRID_REV_MSK M_PRIdRev + + +#define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \ + C0_PRID_COMP_SHF) | \ + (C0_PRID_PRID_4Kc << \ + C0_PRID_PRID_SHF) \ + ) + +#define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \ + C0_PRID_COMP_SHF) | \ + (C0_PRID_PRID_4Kmp << \ + C0_PRID_PRID_SHF) \ + ) + +#define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \ + C0_PRID_COMP_SHF) | \ + (C0_PRID_PRID_4KEc << \ + C0_PRID_PRID_SHF) \ + ) + +#define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \ + C0_PRID_COMP_SHF) | \ + (C0_PRID_PRID_4KEmp << \ + C0_PRID_PRID_SHF) \ + ) + +#define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \ + C0_PRID_COMP_SHF) | \ + (C0_PRID_PRID_4KSc << \ + C0_PRID_PRID_SHF) \ + ) + +#define MIPS_5K ( (C0_PRID_COMP_MIPS << \ + C0_PRID_COMP_SHF) | \ + (C0_PRID_PRID_5K << \ + C0_PRID_PRID_SHF) \ + ) + +#define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \ + C0_PRID_COMP_SHF) | \ + (C0_PRID_PRID_20Kc << \ + C0_PRID_PRID_SHF) \ + ) + +#define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ + C0_PRID_COMP_SHF) | \ + (C0_PRID_PRID_RM52XX << \ + C0_PRID_PRID_SHF) \ + ) + +#define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ + C0_PRID_COMP_SHF) | \ + (C0_PRID_PRID_RM70XX << \ + C0_PRID_PRID_SHF) \ + ) + +/* C0_ENTRYHI register encoding */ + +#define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2 +#define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2 + +#define C0_ENTRYHI_ASID_SHF S_EntryHiASID +#define C0_ENTRYHI_ASID_MSK M_EntryHiASID + + +/* C0_CAUSE register encoding */ + +#define C0_CAUSE_BD_SHF S_CauseBD +#define C0_CAUSE_BD_MSK M_CauseBD +#define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK + +#define C0_CAUSE_CE_SHF S_CauseCE +#define C0_CAUSE_CE_MSK M_CauseCE + +#define C0_CAUSE_IV_SHF S_CauseIV +#define C0_CAUSE_IV_MSK M_CauseIV +#define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK + +#define C0_CAUSE_WP_SHF S_CauseWP +#define C0_CAUSE_WP_MSK M_CauseWP +#define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK + +#define C0_CAUSE_IP_SHF S_CauseIP +#define C0_CAUSE_IP_MSK M_CauseIP + +#define C0_CAUSE_CODE_SHF S_CauseExcCode +#define C0_CAUSE_CODE_MSK M_CauseExcCode + +#define C0_CAUSE_CODE_INT EX_INT +#define C0_CAUSE_CODE_MOD EX_MOD +#define C0_CAUSE_CODE_TLBL EX_TLBL +#define C0_CAUSE_CODE_TLBS EX_TLBS +#define C0_CAUSE_CODE_ADEL EX_ADEL +#define C0_CAUSE_CODE_ADES EX_ADES +#define C0_CAUSE_CODE_IBE EX_IBE +#define C0_CAUSE_CODE_DBE EX_DBE +#define C0_CAUSE_CODE_SYS EX_SYS +#define C0_CAUSE_CODE_BP EX_BP +#define C0_CAUSE_CODE_RI EX_RI +#define C0_CAUSE_CODE_CPU EX_CPU +#define C0_CAUSE_CODE_OV EX_OV +#define C0_CAUSE_CODE_TR EV_TR +#define C0_CAUSE_CODE_FPE EX_FPE +#define C0_CAUSE_CODE_WATCH EX_WATCH +#define C0_CAUSE_CODE_MCHECK EX_MCHECK + +/* Max cause code */ +#define C0_CAUSE_CODE_MAX EX_MCHECK + + +/* C0_PAGEMASK register encoding */ +#define C0_PAGEMASK_MASK_SHF S_PageMaskMask +#define C0_PAGEMASK_MASK_MSK M_PageMaskMask +#define C0_PAGEMASK_MASK_4K K_PageMask4K +#define C0_PAGEMASK_MASK_16K K_PageMask16K +#define C0_PAGEMASK_MASK_64K K_PageMask64K +#define C0_PAGEMASK_MASK_256K K_PageMask256K +#define C0_PAGEMASK_MASK_1M K_PageMask1M +#define C0_PAGEMASK_MASK_4M K_PageMask4M +#define C0_PAGEMASK_MASK_16M K_PageMask16M + + +/* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */ +#define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN +#define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN + +#define C0_ENTRYLO0_C_SHF S_EntryLoC +#define C0_ENTRYLO0_C_MSK M_EntryLoC + +#define C0_ENTRYLO0_D_SHF S_EntryLoD +#define C0_ENTRYLO0_D_MSK M_EntryLoD + +#define C0_ENTRYLO0_V_SHF S_EntryLoV +#define C0_ENTRYLO0_V_MSK M_EntryLoV + +#define C0_ENTRYLO0_G_SHF S_EntryLoG +#define C0_ENTRYLO0_G_MSK M_EntryLoG + + +/* FPU (CP1) FIR register encoding */ +#define C1_FIR_3D_SHF S_FIRConfig3D +#define C1_FIR_3D_MSK M_FIRConfig3D + +#define C1_FIR_PS_SHF S_FIRConfigPS +#define C1_FIR_PS_MSK M_FIRConfigPS + +#define C1_FIR_D_SHF S_FIRConfigD +#define C1_FIR_D_MSK M_FIRConfigD + +#define C1_FIR_S_SHF S_FIRConfigS +#define C1_FIR_S_MSK M_FIRConfigS + +#define C1_FIR_PRID_SHF S_FIRImp +#define C1_FIR_PRID_MSK M_FIRImp + +#define C1_FIR_REV_SHF S_FIRRev +#define C1_FIR_REV_MSK M_FIRRev + + +/* FPU (CP1) FCSR control/status register */ +#define C1_FCSR_FCC_SHF S_FCSRFCC7_1 +#define C1_FCSR_FCC_MSK M_FCSRFCC7_1 + +#define C1_FCSR_FS_SHF S_FCSRFS +#define C1_FCSR_FS_MSK M_FCSRFS +#define C1_FCSR_FS_BIT C1_FCSR_FS_MSK + +#define C1_FCSR_CC_SHF S_FCSRCC +#define C1_FCSR_CC_MSK M_FCSRCC + +#define C1_FCSR_IMPL_SHF S_FCSRImpl +#define C1_FCSR_IMPL_MSK M_FCSRImpl + +#define C1_FCSR_EXC_SHF S_FCSRExc +#define C1_FCSR_EXC_MSK M_FCSRExc + +#define C1_FCSR_ENA_SHF S_FCSREna +#define C1_FCSR_ENA_MSK M_FCSREna + +#define C1_FCSR_FLG_SHF S_FCSRFlg +#define C1_FCSR_FLG_MSK M_FCSRFlg + +#define C1_FCSR_RM_SHF S_FCSRRM +#define C1_FCSR_RM_MSK M_FCSRRM +#define C1_FCSR_RM_RN K_FCSRRM_RN +#define C1_FCSR_RM_RZ K_FCSRRM_RZ +#define C1_FCSR_RM_RP K_FCSRRM_RP +#define C1_FCSR_RM_RM K_FCSRRM_RM + + + +/* cache operations */ + +#define CACHE_OP( code, type ) ( ((code) << 2) | (type) ) + +#define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0) +#define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0) +#define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0) +#define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1) +#define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1) +#define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1) +#define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3) + +#define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0) +#define ICACHE_ADDR_FILL CACHE_OP(0x5, 0) +#define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0) +#define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1) +#define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1) +#define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1) +#define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1) + +#define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3) + +/* Workaround for bug in early revisions of MIPS 4K family of + * processors. Only relevant in early engineering samples of test + * chips (RTL revision <= 3.0). + * + * The bug is described in : + * + * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet + * MIPS Document No: MD00003 + * + * The bug is identified as : C16 + */ +#ifndef SET_MIPS0 +#define SET_MIPS0() +#define SET_PUSH() +#define SET_POP() +#endif +#define ICACHE_INVALIDATE_WORKAROUND(reg) \ +SET_PUSH(); \ +SET_MIPS0(); \ + la reg, 999f; \ +SET_POP(); \ + cache ICACHE_ADDR_FILL, 0(reg); \ + sync; \ + nop; nop; nop; nop; \ +999: + +/* EMPTY_PIPELINE is used for the below cache invalidation operations. + * When $I is invalidated, there will still be operations in the + * pipeline. We make sure these are 'nop' operations. + */ +#define EMPTY_PIPELINE nop; nop; nop; nop + +#define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \ + ICACHE_INVALIDATE_WORKAROUND(scratch); \ + cache ICACHE_INDEX_INVALIDATE, 0(index); \ + EMPTY_PIPELINE + +#define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \ + ICACHE_INVALIDATE_WORKAROUND(scratch); \ + cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \ + EMPTY_PIPELINE + +/* The sync used in the below macro is there in case we are installing + * a new instruction (flush $D, sync, invalidate $I sequence). + */ +#define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \ + cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \ + sync; \ + EMPTY_PIPELINE + +/* Config1 cache field decoding */ +#define CACHE_CALC_SPW(s) ( 64 << (s) ) +#define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 ) +#define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) ) +#define CACHE_CALC_ASSOC(a) ( (a) + 1 ) + + +/**** Move from/to Coprocessor operations ****/ + +/* We use ssnop instead of nop operations in order to handle + * superscalar CPUs. + * The "sll zero,zero,1" notation is compiler backwards compatible. + */ +#define SSNOP sll zero,zero,1 +#define NOPS SSNOP; SSNOP; SSNOP; SSNOP + +#define MFLO(dst) \ + mflo dst;\ + NOPS + +/* Workaround for bug in early revisions of MIPS 4K family of + * processors. + * + * This concerns the nop instruction before mtc0 in the + * MTC0 macro below. + * + * The bug is described in : + * + * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet + * MIPS Document No: MD00003 + * + * The bug is identified as : C27 + */ + +#define MTC0(src, dst) \ + nop; \ + mtc0 src,dst;\ + NOPS + +#define DMTC0(src, dst) \ + nop; \ + dmtc0 src,dst;\ + NOPS + +#define MFC0(dst, src) \ + mfc0 dst,src;\ + NOPS + +#define DMFC0(dst, src) \ + dmfc0 dst,src;\ + NOPS + +#define MFC0_SEL_OPCODE(dst, src, sel)\ + .##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\ + NOPS + +#define MTC0_SEL_OPCODE(dst, src, sel)\ + .##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\ + NOPS + +#define LDC1(dst, src, offs)\ + .##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs)) + +#define SDC1(src, dst, offs)\ + .##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs)) + + +/* Instruction opcode fields */ +#define OPC_SPECIAL 0x0 +#define OPC_REGIM 0x1 +#define OPC_J 0x2 +#define OPC_JAL 0x3 +#define OPC_BEQ 0x4 +#define OPC_BNE 0x5 +#define OPC_BLEZ 0x6 +#define OPC_BGTZ 0x7 +#define OPC_COP1 0x11 +#define OPC_JALX 0x1D +#define OPC_BEQL 0x14 +#define OPC_BNEL 0x15 +#define OPC_BLEZL 0x16 +#define OPC_BGTZL 0x17 + +/* Instruction function fields */ +#define FUNC_JR 0x8 +#define FUNC_JALR 0x9 + +/* Instruction rt fields */ +#define RT_BLTZ 0x0 +#define RT_BGEZ 0x1 +#define RT_BLTZL 0x2 +#define RT_BGEZL 0x3 +#define RT_BLTZAL 0x10 +#define RT_BGEZAL 0x11 +#define RT_BLTZALL 0x12 +#define RT_BGEZALL 0x13 + +/* Instruction rs fields */ +#define RS_BC1 0x08 + +/* Access macros for instruction fields */ +#define MIPS_OPCODE( instr) ((instr) >> 26) +#define MIPS_FUNCTION(instr) ((instr) & MSK(6)) +#define MIPS_RT(instr) (((instr) >> 16) & MSK(5)) +#define MIPS_RS(instr) (((instr) >> 21) & MSK(5)) +#define MIPS_OFFSET(instr) ((instr) & 0xFFFF) +#define MIPS_TARGET(instr) ((instr) & MSK(26)) + +/* Instructions */ +#define OPCODE_DERET 0x4200001f +#define OPCODE_BREAK 0x0005000d +#define OPCODE_NOP 0 +#define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) ) + +#define DERET .##word OPCODE_DERET + +/* MIPS16e opcodes and instruction field access macros */ + +#define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f) +#define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7) +#define MIPS16E_X(inst) (((inst) >> 26) & 0x1) +#define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f) +#define MIPS16E_RY(inst) (((inst) >> 5) & 0x3) +#define MIPS16E_OPC_EXTEND 0x1e +#define MIPS16E_OPC_JAL_X 0x03 +#define MIPS16E_OPC_B 0x02 +#define MIPS16E_OPC_BEQZ 0x04 +#define MIPS16E_OPC_BNEZ 0x05 +#define MIPS16E_OPC_I8 0x0c +#define MIPS16E_I8_FUNC_BTEQZ 0x00 +#define MIPS16E_I8_FUNC_BTNEZ 0x01 +#define MIPS16E_X_JALX 0x01 +#define MIPS16E_OPC_RR 0x1d +#define MIPS16E_RR_FUNC_JALRC 0x00 +#define MIPS16E_RR_RY_JRRX 0x00 +#define MIPS16E_RR_RY_JRRA 0x01 +#define MIPS16E_RR_RY_JALR 0x02 +#define MIPS16E_RR_RY_JRCRX 0x04 +#define MIPS16E_RR_RY_JRCRA 0x05 +#define MIPS16E_RR_RY_JALRC 0x06 + +#define MIPS16E_OPCODE_BREAK 0xE805 +#define MIPS16E_OPCODE_NOP 0x6500 + +/* MIPS reset vector */ +#define MIPS_RESET_VECTOR 0x1fc00000 + +/* Clock periods per count register increment */ +#define MIPS4K_COUNT_CLK_PER_CYCLE 2 +#define MIPS5K_COUNT_CLK_PER_CYCLE 2 +#define MIPS20Kc_COUNT_CLK_PER_CYCLE 1 + + +/**** MIPS 4K/5K families specific fields of CONFIG register ****/ + +#define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23 +#define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF) + +#define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU +#define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF) + + +/**** MIPS 20Kc specific fields of CONFIG register ****/ + +#define C0_CONFIG_MIPS20KC_EC_SHF 28 +#define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF) + +#define C0_CONFIG_MIPS20KC_DD_SHF 27 +#define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF) +#define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK + +#define C0_CONFIG_MIPS20KC_LP_SHF 26 +#define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF) +#define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK + +#define C0_CONFIG_MIPS20KC_SP_SHF 25 +#define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF) +#define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK + +#define C0_CONFIG_MIPS20KC_TI_SHF 24 +#define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF) +#define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK + + +/* ********************************************************************* */ +/* Interface function definition */ + + +/* ********************************************************************* */ + +#endif /* #ifndef __MIPS_H__ */ diff --git a/sdk-modifications/include/mipsregs.h b/sdk-modifications/include/mipsregs.h new file mode 100755 index 0000000..5eaac44 --- /dev/null +++ b/sdk-modifications/include/mipsregs.h @@ -0,0 +1,985 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle + * Copyright (C) 2000 Silicon Graphics, Inc. + * Modified for further R[236]000 support by Paul M. Antoine, 1996. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2003 Maciej W. Rozycki + */ +#ifndef _ASM_MIPSREGS_H +#define _ASM_MIPSREGS_H + +#include +#include + +/* + * The following macros are especially useful for __asm__ + * inline assembler. + */ +#ifndef __STR +#define __STR(x) #x +#endif +#ifndef STR +#define STR(x) __STR(x) +#endif + +/* + * Configure language + */ +#ifdef __ASSEMBLY__ +#define _ULCAST_ +#else +#define _ULCAST_ (unsigned long) +#endif + +/* + * Coprocessor 0 register names + */ +#define CP0_INDEX $0 +#define CP0_RANDOM $1 +#define CP0_ENTRYLO0 $2 +#define CP0_ENTRYLO1 $3 +#define CP0_CONF $3 +#define CP0_CONTEXT $4 +#define CP0_PAGEMASK $5 +#define CP0_WIRED $6 +#define CP0_INFO $7 +#define CP0_BADVADDR $8 +#define CP0_COUNT $9 +#define CP0_ENTRYHI $10 +#define CP0_COMPARE $11 +#define CP0_STATUS $12 +#define CP0_CAUSE $13 +#define CP0_EPC $14 +#define CP0_PRID $15 +#define CP0_CONFIG $16 +#define CP0_LLADDR $17 +#define CP0_WATCHLO $18 +#define CP0_WATCHHI $19 +#define CP0_XCONTEXT $20 +#define CP0_FRAMEMASK $21 +#define CP0_DIAGNOSTIC $22 +#define CP0_DEBUG $23 +#define CP0_DEPC $24 +#define CP0_PERFORMANCE $25 +#define CP0_ECC $26 +#define CP0_CACHEERR $27 +#define CP0_TAGLO $28 +#define CP0_TAGHI $29 +#define CP0_ERROREPC $30 +#define CP0_DESAVE $31 + +/* + * R4640/R4650 cp0 register names. These registers are listed + * here only for completeness; without MMU these CPUs are not useable + * by Linux. A future ELKS port might take make Linux run on them + * though ... + */ +#define CP0_IBASE $0 +#define CP0_IBOUND $1 +#define CP0_DBASE $2 +#define CP0_DBOUND $3 +#define CP0_CALG $17 +#define CP0_IWATCH $18 +#define CP0_DWATCH $19 + +/* + * Coprocessor 0 Set 1 register names + */ +#define CP0_S1_DERRADDR0 $26 +#define CP0_S1_DERRADDR1 $27 +#define CP0_S1_INTCONTROL $20 + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + +/* + * Coprocessor 1 (FPU) register names + */ +#define CP1_REVISION $0 +#define CP1_STATUS $31 + +/* + * FPU Status Register Values + */ +/* + * Status Register Values + */ + +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ + +/* + * X the exception cause indicator + * E the exception enable + * S the sticky/flag bit +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 + +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 + +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 + +/* rounding mode */ +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + + +/* + * Values for PageMask register + */ +#ifdef CONFIG_CPU_VR41XX + +/* Why doesn't stupidity hurt ... */ + +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 + +#else + +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M 0x1fffe000 + +#endif + +/* + * Values used for computation of new tlb entries + */ +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 +#define PL_64M 26 +#define PL_256M 28 + +/* + * R4x00 interrupt enable / cause bits + */ +#define IE_SW0 (_ULCAST_(1) << 8) +#define IE_SW1 (_ULCAST_(1) << 9) +#define IE_IRQ0 (_ULCAST_(1) << 10) +#define IE_IRQ1 (_ULCAST_(1) << 11) +#define IE_IRQ2 (_ULCAST_(1) << 12) +#define IE_IRQ3 (_ULCAST_(1) << 13) +#define IE_IRQ4 (_ULCAST_(1) << 14) +#define IE_IRQ5 (_ULCAST_(1) << 15) + +/* + * R4x00 interrupt cause bits + */ +#define C_SW0 (_ULCAST_(1) << 8) +#define C_SW1 (_ULCAST_(1) << 9) +#define C_IRQ0 (_ULCAST_(1) << 10) +#define C_IRQ1 (_ULCAST_(1) << 11) +#define C_IRQ2 (_ULCAST_(1) << 12) +#define C_IRQ3 (_ULCAST_(1) << 13) +#define C_IRQ4 (_ULCAST_(1) << 14) +#define C_IRQ5 (_ULCAST_(1) << 15) + +/* + * Bitfields in the R4xx0 cp0 status register + */ +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 + +/* + * Bitfields in the R[23]000 cp0 status register. + */ +#define ST0_IEC 0x00000001 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 +/* bits 6 & 7 are reserved on R[23]000 */ +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 + +/* + * Bits specific to the R4640/R4650 + */ +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) + +/* + * Bitfields in the TX39 family CP0 Configuration Register 3 + */ +#define TX39_CONF_ICS_SHIFT 19 +#define TX39_CONF_ICS_MASK 0x00380000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 + +#define TX39_CONF_DCS_SHIFT 16 +#define TX39_CONF_DCS_MASK 0x00070000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_RF_SHIFT 10 +#define TX39_CONF_RF_MASK 0x00000c00 +#define TX39_CONF_DOZE 0x00000200 +#define TX39_CONF_HALT 0x00000100 +#define TX39_CONF_LOCK 0x00000080 +#define TX39_CONF_ICE 0x00000020 +#define TX39_CONF_DCE 0x00000010 +#define TX39_CONF_IRSIZE_SHIFT 2 +#define TX39_CONF_IRSIZE_MASK 0x0000000c +#define TX39_CONF_DRSIZE_SHIFT 0 +#define TX39_CONF_DRSIZE_MASK 0x00000003 + +/* + * Status register bits available in all MIPS CPUs. + */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ + +/* + * Bitfields and bit numbers in the coprocessor 0 cause register. + * + * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. + */ +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) + +/* + * Bits in the coprocessor 0 config register. + */ +/* Generic bits. */ +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) + +/* Bits common to various processors. */ +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) + +/* Bits specific to the R4xx0. */ +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) + +/* Bits specific to the R5000. */ +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) + +/* Bits specific to the R10000. */ +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) + +/* Bits specific to the VR41xx. */ +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) + +/* Bits specific to the R30xx. */ +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) + +/* Bits specific to the TX49. */ +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) + +/* Bits specific to the MIPS32/64 PRA. */ +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) + +/* + * R10000 performance counter definitions. + * + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... + */ + +/* + * Events counted by counter #0 + */ +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 + +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 + +/* + * These flags define in which priviledge mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ + +#ifndef __ASSEMBLY__ + +#define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE) +#define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2)) + +/* + * Functions to access the r10k performance counter and control registers + */ +#define read_r10k_perf_cntr(counter) \ +({ unsigned int __res; \ + __asm__ __volatile__( \ + "mfpc\t%0, "STR(counter) \ + : "=r" (__res)); \ + __res;}) + +#define write_r10k_perf_cntr(counter,val) \ + __asm__ __volatile__( \ + "mtpc\t%0, "STR(counter) \ + : : "r" (val)); + +#define read_r10k_perf_cntl(counter) \ +({ unsigned int __res; \ + __asm__ __volatile__( \ + "mfps\t%0, "STR(counter) \ + : "=r" (__res)); \ + __res;}) + +#define write_r10k_perf_cntl(counter,val) \ + __asm__ __volatile__( \ + "mtps\t%0, "STR(counter) \ + : : "r" (val)); + +/* + * Macros to access the system control coprocessor + */ + +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __read_64bit_c0_register(source, sel) \ +({ unsigned long __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ +} while (0) + +#define __write_64bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ +} while (0) + +#define __read_ulong_c0_register(reg, sel) \ + ((sizeof(unsigned long) == 4) ? \ + __read_32bit_c0_register(reg, sel) : \ + __read_64bit_c0_register(reg, sel)) + +#define __write_ulong_c0_register(reg, sel, val) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ +} while (0) + +/* + * These versions are only needed for systems with more than 38 bits of + * physical address space running the 32-bit kernel. That's none atm :-) + */ +#define __read_64bit_c0_split(source, sel) \ +({ \ + unsigned long long val; \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + local_irq_restore(flags); \ + \ + val; \ +}) + +#define __write_64bit_c0_split(source, sel, val) \ +do { \ + unsigned long flags; \ + \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(flags); \ +} while (0) + +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) + +#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) + +#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) + +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) + +#define read_c0_context() __read_ulong_c0_register($4, 0) +#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) + +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) + +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) + +#define read_c0_info() __read_32bit_c0_register($7, 0) + +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) + +#define read_c0_entryhi() __read_ulong_c0_register($10, 0) +#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) + +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) + +#define read_c0_status() __read_32bit_c0_register($12, 0) +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) + +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) + +#define read_c0_prid() __read_32bit_c0_register($15, 0) + +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) + +/* + * The WatchLo register. There may be upto 8 of them. + */ +#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) +#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) +#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) +#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) +#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) +#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) +#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) +#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) +#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) +#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) +#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) +#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) +#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) +#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) +#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) +#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) + +/* + * The WatchHi register. There may be upto 8 of them. + */ +#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) +#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) +#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) +#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) +#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) +#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) +#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) +#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) + +#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) +#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) +#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) +#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) +#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) +#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) +#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) +#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) + +#define read_c0_xcontext() __read_ulong_c0_register($20, 0) +#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) + +#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) +#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) + +#define read_c0_framemask() __read_32bit_c0_register($21, 0) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) + +#define read_c0_debug() __read_32bit_c0_register($23, 0) +#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) + +#define read_c0_depc() __read_ulong_c0_register($24, 0) +#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) + +#define read_c0_ecc() __read_32bit_c0_register($26, 0) +#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) + +#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) + +#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) + +#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) + +#define read_c0_taglo() __read_32bit_c0_register($28, 0) +#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) + +#define read_c0_taghi() __read_32bit_c0_register($29, 0) +#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) + +#define read_c0_errorepc() __read_ulong_c0_register($30, 0) +#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) + +#define read_c0_epc() __read_ulong_c0_register($14, 0) +#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) + +#if 1 +/* + * Macros to access the system control coprocessor + */ +#define read_32bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "mfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +#define read_32bit_cp0_set1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +/* + * For now use this only with interrupts disabled! + */ +#define read_64bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0,"STR(source)"\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res;}) + +#define write_32bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_32bit_cp0_set1_register(register,value) \ + __asm__ __volatile__( \ + "ctc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_64bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%0,"STR(register)"\n\t" \ + ".set\tmips0" \ + : : "r" (value)) + +/* + * This should be changed when we get a compiler that support the MIPS32 ISA. + */ +#define read_mips32_cp0_config1() \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + "#.set\tmips64\n\t" \ + "#mfc0\t$1, $16, 1\n\t" \ + "#.set\tmips0\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ + __res;}) + +#endif +/* + * Macros to access the floating point coprocessor control registers + */ +#define read_32bit_cp1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc1\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +/* TLB operations. */ +static inline void tlb_probe(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbp\n\t" + ".set reorder"); +} + +static inline void tlb_read(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbr\n\t" + ".set reorder"); +} + +static inline void tlb_write_indexed(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwi\n\t" + ".set reorder"); +} + +static inline void tlb_write_random(void) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + "tlbwr\n\t" + ".set reorder"); +} + +/* + * Manipulate bits in a c0 register. + */ +#define __BUILD_SET_C0(name,register) \ +static inline unsigned int \ +set_c0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res |= set; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +clear_c0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~clear; \ + write_c0_##name(res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +change_c0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ + \ + res = read_c0_##name(); \ + res &= ~change; \ + res |= (new & change); \ + write_c0_##name(res); \ + \ + return res; \ +} + +__BUILD_SET_C0(status,CP0_STATUS) +__BUILD_SET_C0(cause,CP0_CAUSE) +__BUILD_SET_C0(config,CP0_CONFIG) + +#define set_cp0_status(x) set_c0_status(x) +#define set_cp0_cause(x) set_c0_cause(x) +#define set_cp0_config(x) set_c0_config(x) + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_MIPSREGS_H */ diff --git a/sdk-modifications/include/mmc_api.h b/sdk-modifications/include/mmc_api.h new file mode 100755 index 0000000..28e75ef --- /dev/null +++ b/sdk-modifications/include/mmc_api.h @@ -0,0 +1,56 @@ +#ifndef __MMC_API_H__ +#define __MMC_API_H__ + +/* Error codes */ +enum mmc_result_t { + MMC_NO_RESPONSE = -1, + MMC_NO_ERROR = 0, + MMC_ERROR_OUT_OF_RANGE, + MMC_ERROR_ADDRESS, + MMC_ERROR_BLOCK_LEN, + MMC_ERROR_ERASE_SEQ, + MMC_ERROR_ERASE_PARAM, + MMC_ERROR_WP_VIOLATION, + MMC_ERROR_CARD_IS_LOCKED, + MMC_ERROR_LOCK_UNLOCK_FAILED, + MMC_ERROR_COM_CRC, + MMC_ERROR_ILLEGAL_COMMAND, + MMC_ERROR_CARD_ECC_FAILED, + MMC_ERROR_CC, + MMC_ERROR_GENERAL, + MMC_ERROR_UNDERRUN, + MMC_ERROR_OVERRUN, + MMC_ERROR_CID_CSD_OVERWRITE, + MMC_ERROR_STATE_MISMATCH, + MMC_ERROR_HEADER_MISMATCH, + MMC_ERROR_TIMEOUT, + MMC_ERROR_CRC, + MMC_ERROR_DRIVER_FAILURE, +}; + + +/* Get card's sectors*/ + +extern unsigned int MMC_GetSize(void); + + +/* initialize MMC/SD card */ +extern int MMC_Initialize(void); + +/* read a single block from MMC/SD card */ +extern int MMC_ReadBlock(unsigned int blockaddr, unsigned char *recbuf); + +/* read multi blocks from MMC/SD card */ +extern int MMC_ReadMultiBlock(unsigned int blockaddr, unsigned int blocknum, unsigned char *recbuf); + +/* write a block to MMC/SD card */ +extern int MMC_WriteBlock(unsigned int blockaddr, unsigned char *recbuf); + +/* write multi blocks to MMC/SD card */ +extern int MMC_WriteMultiBlock(unsigned int blockaddr, unsigned int blocknum, unsigned char *recbuf); + +/* detect MMC/SD card */ +extern int MMC_DetectStatus(void); + +#endif /* __MMC_API_H__ */ + diff --git a/sdk-modifications/include/partition.h b/sdk-modifications/include/partition.h new file mode 100755 index 0000000..0777b54 --- /dev/null +++ b/sdk-modifications/include/partition.h @@ -0,0 +1,131 @@ +/* + partition.h + Functions for mounting and dismounting partitions + on various block devices. + + Copyright (c) 2006 Michael "Chishm" Chisholm + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + 3. The name of the author may not be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + 2006-07-11 - Chishm + * Original release +*/ + +#ifndef _PARTITION_H +#define _PARTITION_H + +#include "fs_common.h" + +#include "disc_io/disc.h" +#include "fs_cache.h" + +// Device name +extern const char* DEVICE_NAME; + +// Filesystem type +typedef enum {FS_UNKNOWN, FS_FAT12, FS_FAT16, FS_FAT32} FS_TYPE; + +#ifdef NDS +typedef enum {PI_DEFAULT, PI_SLOT_1, PI_SLOT_2, PI_CUSTOM} PARTITION_INTERFACE; +#else +typedef enum {PI_CART_SLOT} PARTITION_INTERFACE; +#endif + +typedef struct { + u32 fatStart; + u32 sectorsPerFat; + u32 lastCluster; + u32 firstFree; +} FAT; + +typedef struct { + const IO_INTERFACE* disc; + CACHE* cache; + // Info about the partition + bool readOnly; // If this is set, then do not try writing to the disc + FS_TYPE filesysType; + u32 totalSize; + u32 rootDirStart; + u32 rootDirCluster; + u32 numberOfSectors; + u32 dataStart; + u32 bytesPerSector; + u32 sectorsPerCluster; + u32 bytesPerCluster; + FAT fat; + // Values that may change after construction + u32 cwdCluster; // Current working directory cluser + u32 openFileCount; +} PARTITION; + +/* +Mount the device specified by partitionDevice +PD_DEFAULT is not allowed, use _FAT_partition_setDefaultDevice +PD_CUSTOM is not allowed, use _FAT_partition_mountCustomDevice +*/ +bool _FAT_partition_mount (PARTITION_INTERFACE partitionNumber, u32 cacheSize); + +/* +Mount a partition on a custom device +*/ +bool _FAT_partition_mountCustomInterface (const IO_INTERFACE* device, u32 cacheSize); + + +/* +Free Mount a partition on a custom device +*/ +bool _FAT_partition_freeMount( int partitionNumber, const IO_INTERFACE* device, u32 cacheSize); + + +/* +Unmount the partition specified by partitionNumber +If there are open files, it will fail +*/ +bool _FAT_partition_unmount (PARTITION_INTERFACE partitionNumber); + +/* +Forcibly unmount the partition specified by partitionNumber +Any open files on the partition will become invalid +The cache will be invalidated, and any unflushed writes will be lost +*/ +bool _FAT_partition_unsafeUnmount (PARTITION_INTERFACE partitionNumber); + +/* +Set the default device for access by fat: and fat0:, +based on the device number +*/ +bool _FAT_partition_setDefaultInterface (PARTITION_INTERFACE partitionNumber); + +/* +Set the default device for access by fat: and fat0:, +based on the partition pointer +*/ +bool _FAT_partition_setDefaultPartition (PARTITION* partition); + +/* +Return the partition specified in a path +For instance, "fat0:", "fat:", "/" and "fat:/" will all +return the default partition +*/ +PARTITION* _FAT_partition_getPartitionFromPath (const char* path); + +#endif // _PARTITION_H diff --git a/sdk-modifications/include/tcm.h b/sdk-modifications/include/tcm.h new file mode 100755 index 0000000..4de3333 --- /dev/null +++ b/sdk-modifications/include/tcm.h @@ -0,0 +1,10 @@ +#ifndef __TCM_H +#define __TCM_H + +/* +* Function: makes cpu to idle state. It will be waken up by RTC in the next second. +* Of course, it can be waken up by keys at any time. +*/ +int enable_enter_idle(void); + +#endif -- cgit v1.2.3