From e708c127fa51beab567a9ce0e3ab53b58c997773 Mon Sep 17 00:00:00 2001
From: Nebuleon Fumika
Date: Tue, 18 Dec 2012 22:53:49 -0500
Subject: Un-inline a bunch of stuff.

With the MIPS instruction cache, this means that two consecutive SNES CPU instructions using e.g. the same addressing style or the same opcode have a chance that the second one will use the first one's code and that it will be cached.
---
 source/apumem.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'source/apumem.h')

diff --git a/source/apumem.h b/source/apumem.h
index 8f6dfa4..573b52c 100644
--- a/source/apumem.h
+++ b/source/apumem.h
@@ -95,7 +95,7 @@ extern uint8 W4;
 extern uint8 APUROM[64];
 END_EXTERN_C
 
-INLINE uint8 S9xAPUGetByteZ (uint8 Address)
+uint8 S9xAPUGetByteZ (uint8 Address)
 {
     if (Address >= 0xf0 && IAPU.DirectPage == IAPU.RAM)
     {
@@ -127,7 +127,7 @@ INLINE uint8 S9xAPUGetByteZ (uint8 Address)
 	return (IAPU.DirectPage [Address]);
 }
 
-INLINE void S9xAPUSetByteZ (uint8 byte, uint8 Address)
+void S9xAPUSetByteZ (uint8 byte, uint8 Address)
 {
     if (Address >= 0xf0 && IAPU.DirectPage == IAPU.RAM)
     {
@@ -156,7 +156,7 @@ INLINE void S9xAPUSetByteZ (uint8 byte, uint8 Address)
 	IAPU.DirectPage [Address] = byte;
 }
 
-INLINE uint8 S9xAPUGetByte (uint32 Address)
+uint8 S9xAPUGetByte (uint32 Address)
 {
     Address &= 0xffff;
     
@@ -189,7 +189,7 @@ INLINE uint8 S9xAPUGetByte (uint32 Address)
 	return (IAPU.RAM [Address]);
 }
 
-INLINE void S9xAPUSetByte (uint8 byte, uint32 Address)
+void S9xAPUSetByte (uint8 byte, uint32 Address)
 {
     Address &= 0xffff;
     
-- 
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