Merge git://github.com/notaz/pcsx_rearmed

11 files changed, 318 insertions, 309 deletions

diff --git a/Makefile.libretro b/Makefile.libretro
index 4ec6212..3ff091a 100644
--- a/Makefile.libretro
+++ b/Makefile.libretro
@@ -19,61 +19,61 @@ AS ?= as
 CC_AS ?= $(CC)
 
 ifeq ($(platform), unix)
-   TARGET := snes9x_next_libretro.so
+   TARGET := libretro_pcsx_rearmed.so
    fpic := -fPIC
    SHARED := -shared -Wl,--version-script=libretro/link.T
 else ifeq ($(platform), osx)
-   TARGET := snes9x_next_libretro.dylib
+   TARGET := libretro_pcsx_rearmed.dylib
    fpic := -fPIC
    SHARED := -dynamiclib
 else ifeq ($(platform), ios)
 ARCH := arm
-   TARGET := snes9x_next_libretro.dylib
+   TARGET := libretro_pcsx_rearmed.dylib
    fpic := -fPIC
    SHARED := -dynamiclib
 
    CC = clang -arch armv7 -isysroot $(IOSSDK)
    CXX = clang++ -arch armv7 -isysroot $(IOSSDK)
    CC_AS = perl ./tools/gas-preprocessor.pl $(CC)
-   CFLAGS += -mcpu=cortex-a8 -mtune=cortex-a8 -mfpu=neon
+   CFLAGS += -mcpu=cortex-a8 -mtune=cortex-a8 -mfpu=neon -marm
    ASFLAGS += -mcpu=cortex-a8 -mtune=cortex-a8 -mfpu=neon
    HAVE_NEON = 1
 #TODO
 #   BUILTIN_GPU = neon
-#   USE_DYNAREC = 1
+   USE_DYNAREC = 1
    CFLAGS += -DIOS
 else ifeq ($(platform), ps3)
-   TARGET := snes9x_next_libretro_ps3.a
+   TARGET := libretro_pcsx_rearmed_ps3.a
    CC = $(CELL_SDK)/host-win32/ppu/bin/ppu-lv2-gcc.exe
    AR = $(CELL_SDK)/host-win32/ppu/bin/ppu-lv2-ar.exe
    CFLAGS += -DBLARGG_BIG_ENDIAN=1 -D__ppc__
 else ifeq ($(platform), sncps3)
-   TARGET := snes9x_next_libretro_ps3.a
+   TARGET := libretro_pcsx_rearmed_ps3.a
    CC = $(CELL_SDK)/host-win32/sn/bin/ps3ppusnc.exe
    AR = $(CELL_SDK)/host-win32/sn/bin/ps3snarl.exe
    CFLAGS += -DBLARGG_BIG_ENDIAN=1 -D__ppc__
 else ifeq ($(platform), psl1ght)
-   TARGET := snes9x_next_libretro_psl1ght.a
+   TARGET := libretro_pcsx_rearmed_psl1ght.a
    CC = $(PS3DEV)/ppu/bin/ppu-gcc$(EXE_EXT)
    AR = $(PS3DEV)/ppu/bin/ppu-ar$(EXE_EXT)
    CFLAGS += -DBLARGG_BIG_ENDIAN=1 -D__ppc__
 else ifeq ($(platform), psp1)
-	TARGET := snes9x_next_libretro_psp1.a
+	TARGET := libretro_pcsx_rearmed_psp1.a
 	CC = psp-gcc$(EXE_EXT)
 	AR = psp-ar$(EXE_EXT)
 	CFLAGS += -DPSP -G0
 else ifeq ($(platform), xenon)
-   TARGET := snes9x_next_libretro_xenon360.a
+   TARGET := libretro_pcsx_rearmed_xenon360.a
    CC = xenon-gcc$(EXE_EXT)
    AR = xenon-ar$(EXE_EXT)
    CFLAGS += -D__LIBXENON__ -m32 -D__ppc__
 else ifeq ($(platform), ngc)
-   TARGET := snes9x_next_libretro_ngc.a
+   TARGET := libretro_pcsx_rearmed_ngc.a
    CC = $(DEVKITPPC)/bin/powerpc-eabi-gcc$(EXE_EXT)
    AR = $(DEVKITPPC)/bin/powerpc-eabi-ar$(EXE_EXT)
    CFLAGS += -DGEKKO -DHW_DOL -mrvl -mcpu=750 -meabi -mhard-float -DBLARGG_BIG_ENDIAN=1 -D__ppc__
 else ifeq ($(platform), wii)
-   TARGET := snes9x_next_libretro_wii.a
+   TARGET := libretro_pcsx_rearmed_wii.a
    CC = $(DEVKITPPC)/bin/powerpc-eabi-gcc$(EXE_EXT)
    AR = $(DEVKITPPC)/bin/powerpc-eabi-ar$(EXE_EXT)
    CFLAGS += -DGEKKO -DHW_RVL -mrvl -mcpu=750 -meabi -mhard-float -DBLARGG_BIG_ENDIAN=1 -D__ppc__
@@ -114,3 +114,8 @@ PLUGINS =
 NO_CONFIG_MAK = yes
 
 include Makefile
+
+# workaround segfault for this file seen on:
+# Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
+libpcsxcore/new_dynarec/pcsxmem.o: libpcsxcore/new_dynarec/pcsxmem.c
+	$(CC) -c -o $@ $< $(CPPFLAGS) $(CFLAGS) -Os
diff --git a/include/arm_features.h b/include/arm_features.h
index a1adfef..abfd876 100644
--- a/include/arm_features.h
+++ b/include/arm_features.h
@@ -25,20 +25,23 @@
 
 /* no need for HAVE_NEON - GCC defines __ARM_NEON__ consistently */
 
-/* global function/external variable */
+/* global function/external symbol */
 #ifndef __MACH__
+#define ESYM(name) name
+
 #define FUNCTION(name) \
-  .global name; \
+  .globl name; \
   .type name, %function; \
   name
 
-#define EVAR(name) name
 #else
+#define ESYM(name) _##name
+
 #define FUNCTION(name) \
-  .globl _##name; \
-  _##name
+  .globl ESYM(name); \
+  name: \
+  ESYM(name)
 
-#define EVAR(name) _##name
 #endif
 
 #endif /* __ARM_FEATURES_H__ */
diff --git a/libpcsxcore/debug.c b/libpcsxcore/debug.c
index 307a002..763dc45 100644
--- a/libpcsxcore/debug.c
+++ b/libpcsxcore/debug.c
@@ -396,7 +396,7 @@ void ProcessDebug() {
         if ((psxRegs.code >> 26) == 3) {
             MarkMap(_JumpTarget_, MAP_EXEC_JAL);
         }
-        if (((psxRegs.code >> 26) == 0) && ((psxRegs.code && 0x3F) == 9)) {
+        if (((psxRegs.code >> 26) == 0) && ((psxRegs.code & 0x3F) == 9)) {
             MarkMap(_Rd_, MAP_EXEC_JAL);
         }
     }
diff --git a/libpcsxcore/gte_neon.S b/libpcsxcore/gte_neon.S
index 3c71f55..fe153e2 100644
--- a/libpcsxcore/gte_neon.S
+++ b/libpcsxcore/gte_neon.S
@@ -6,29 +6,12 @@
  */
 
 #include "arm_features.h"
+#include "new_dynarec/linkage_offsets.h"
 
 .syntax unified
-
-.bss
-.align 6 @ cacheline
-
-scratch:
-.rept 8*8*2/4
-    .word 0
-.endr
-
 .text
 .align 2
 
-.macro ldr_scratch rd
-#ifndef __PIC__
-    movw        \rd, #:lower16:scratch
-    movt        \rd, #:upper16:scratch
-#else
-    ldr         \rd, =scratch
-#endif
-.endm
-
 @ XXX: gteMAC calc shouldn't be saturating, but it is here
 
 @ approximate gteMAC|123 flags
@@ -150,7 +133,7 @@ FUNCTION(gteRTPS_neon): @ r0=CP2 (d,c),
     push        {r4-r6,lr}
 
 @    fmrx        r4, fpscr      @ vmrs? at least 40 cycle hit
-    ldr_scratch r1
+    ldr		r1, [r0, #LO_cop2_to_scratch_buf]
     mov         r12, #0
 
     vldmia      r0, {d8}       @ VXYZ(0)
@@ -302,7 +285,7 @@ FUNCTION(gteRTPS_neon): @ r0=CP2 (d,c),
 FUNCTION(gteRTPT_neon): @ r0=CP2 (d,c),
     push        {r4-r11,lr}
 
-    ldr_scratch r1
+    ldr		r1, [r0, #LO_cop2_to_scratch_buf]
     mov         r12, #0
 
     rtpx_preload
diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c
index 1d944c2..8fe88fd 100644
--- a/libpcsxcore/new_dynarec/assem_arm.c
+++ b/libpcsxcore/new_dynarec/assem_arm.c
@@ -493,7 +493,7 @@ void alloc_reg(struct regstat *cur,int i,signed char reg)
       }
     }
   }
-  printf("This shouldn't happen (alloc_reg)");exit(1);
+  SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
 }
 
 void alloc_reg64(struct regstat *cur,int i,signed char reg)
@@ -659,7 +659,7 @@ void alloc_reg64(struct regstat *cur,int i,signed char reg)
       }
     }
   }
-  printf("This shouldn't happen");exit(1);
+  SysPrintf("This shouldn't happen");exit(1);
 }
 
 // Allocate a temporary register.  This is done without regard to
@@ -782,7 +782,7 @@ void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
       }
     }
   }
-  printf("This shouldn't happen");exit(1);
+  SysPrintf("This shouldn't happen");exit(1);
 }
 // Allocate a specific ARM register.
 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
@@ -899,7 +899,7 @@ u_int genjmp(u_int addr)
   int offset=addr-(int)out-8;
   if(offset<-33554432||offset>=33554432) {
     if (addr>2) {
-      printf("genjmp: out of range: %08x\n", offset);
+      SysPrintf("genjmp: out of range: %08x\n", offset);
       exit(1);
     }
     return 0;
@@ -1033,7 +1033,7 @@ void emit_loadreg(int r, int hr)
 {
 #ifdef FORCE32
   if(r&64) {
-    printf("64bit load in 32bit mode!\n");
+    SysPrintf("64bit load in 32bit mode!\n");
     assert(0);
     return;
   }
@@ -1058,7 +1058,7 @@ void emit_storereg(int r, int hr)
 {
 #ifdef FORCE32
   if(r&64) {
-    printf("64bit store in 32bit mode!\n");
+    SysPrintf("64bit store in 32bit mode!\n");
     assert(0);
     return;
   }
@@ -3288,7 +3288,7 @@ do_writestub(int n)
     emit_writeword(rt,(int)&dword);
     emit_writeword(r?rth:rt,(int)&dword+4);
 #else
-    printf("STORED_STUB\n");
+    SysPrintf("STORED_STUB\n");
 #endif
   }
   //emit_pusha();
@@ -3397,7 +3397,7 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target,
     emit_writeword(rt,(int)&dword);
     emit_writeword(target?rth:rt,(int)&dword+4);
 #else
-    printf("STORED_STUB\n");
+    SysPrintf("STORED_STUB\n");
 #endif
   }
   //emit_pusha();
@@ -3720,12 +3720,12 @@ generate_map_const(u_int addr,int reg) {
 
 #else
 
-static int do_tlb_r() { return 0; }
-static int do_tlb_r_branch() { return 0; }
-static int gen_tlb_addr_r() { return 0; }
-static int do_tlb_w() { return 0; }
-static int do_tlb_w_branch() { return 0; }
-static int gen_tlb_addr_w() { return 0; }
+static int do_tlb_r(int a, ...) { return 0; }
+static int do_tlb_r_branch(int a, ...) { return 0; }
+static int gen_tlb_addr_r(int a, ...) { return 0; }
+static int do_tlb_w(int a, ...) { return 0; }
+static int do_tlb_w_branch(int a, ...) { return 0; }
+static int gen_tlb_addr_w(int a, ...) { return 0; }
 
 #endif // DISABLE_TLB
 
diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
index 02e108f..324071d 100644
--- a/libpcsxcore/new_dynarec/emu_if.c
+++ b/libpcsxcore/new_dynarec/emu_if.c
@@ -25,6 +25,7 @@
 #define evprintf(...)
 
 char invalid_code[0x100000];
+static u32 scratch_buf[8*8*2] __attribute__((aligned(64)));
 u32 event_cycles[PSXINT_COUNT];
 
 static void schedule_timeslice(void)
@@ -286,6 +287,7 @@ static int ari64_init()
 #endif
 	psxH_ptr = psxH;
 	zeromem_ptr = zero_mem;
+	scratch_buf_ptr = scratch_buf;
 
 	return 0;
 }
@@ -386,6 +388,7 @@ int new_dynarec_hacks;
 void *psxH_ptr;
 void *zeromem_ptr;
 u8 zero_mem[0x1000];
+void *scratch_buf_ptr;
 void new_dynarec_init() { (void)ari64_execute; }
 void new_dyna_start() {}
 void new_dynarec_cleanup() {}
diff --git a/libpcsxcore/new_dynarec/emu_if.h b/libpcsxcore/new_dynarec/emu_if.h
index 72f6c27..3980490 100644
--- a/libpcsxcore/new_dynarec/emu_if.h
+++ b/libpcsxcore/new_dynarec/emu_if.h
@@ -83,6 +83,7 @@ void rcnt2_read_count_m1(u32 addr, u32, u32 cycles);
 extern unsigned int address;
 extern void *psxH_ptr;
 extern void *zeromem_ptr;
+extern void *scratch_buf_ptr;
 
 // same as invalid_code, just a region for ram write checks (inclusive)
 extern u32 inv_code_start, inv_code_end;
@@ -98,6 +99,8 @@ void pcsx_mtc0_ds(u32 reg, u32 val);
 /* misc */
 extern void (*psxHLEt[])();
 
+extern void SysPrintf(const char *fmt, ...);
+
 #ifdef RAM_FIXED
 #define rdram ((u_int)0x80000000)
 #else
diff --git a/libpcsxcore/new_dynarec/linkage_arm.S b/libpcsxcore/new_dynarec/linkage_arm.S
index 5a76f8e..0c5b205 100644
--- a/libpcsxcore/new_dynarec/linkage_arm.S
+++ b/libpcsxcore/new_dynarec/linkage_arm.S
@@ -1,7 +1,7 @@
 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
  *   linkage_arm.s for PCSX                                                *
  *   Copyright (C) 2009-2011 Ari64                                         *
- *   Copyright (C) 2010-2011 Gražvydas "notaz" Ignotas                     *
+ *   Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas                     *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
@@ -20,151 +20,93 @@
  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
 
 #include "arm_features.h"
-
-
-	.global	dynarec_local
-	.global	reg
-	.global	hi
-	.global	lo
-	.global reg_cop0
-	.global reg_cop2d
-	.global reg_cop2c
-	.global	FCR0
-	.global	FCR31
-	.global	next_interupt
-	.global	cycle_count
-	.global	last_count
-	.global	pending_exception
-	.global	pcaddr
-	.global	stop
-	.global	invc_ptr
-	.global	address
-	.global	branch_target
-	.global	PC
-	.global	mini_ht
-	.global	restore_candidate
-	/* psx */
-	.global psxRegs
-	.global mem_rtab
-	.global mem_wtab
-	.global psxH_ptr
-	.global zeromem_ptr
-	.global inv_code_start
-	.global inv_code_end
-	.global rcnts
+#include "linkage_offsets.h"
+
+
+#ifdef __MACH__
+#define dynarec_local		ESYM(dynarec_local)
+#define add_link		ESYM(add_link)
+#define new_recompile_block	ESYM(new_recompile_block)
+#define get_addr		ESYM(get_addr)
+#define get_addr_ht		ESYM(get_addr_ht)
+#define clean_blocks		ESYM(clean_blocks)
+#define gen_interupt		ESYM(gen_interupt)
+#define psxException		ESYM(psxException)
+#define execI			ESYM(execI)
+#define invalidate_addr		ESYM(invalidate_addr)
+#endif
 
 	.bss
 	.align	4
+	.global dynarec_local
 	.type	dynarec_local, %object
-	.size	dynarec_local, dynarec_local_end-dynarec_local
+	.size	dynarec_local, LO_dynarec_local_size
 dynarec_local:
-	.space	dynarec_local_end-dynarec_local
-next_interupt = dynarec_local + 64
-	.type	next_interupt, %object
-	.size	next_interupt, 4
-cycle_count = next_interupt + 4
-	.type	cycle_count, %object
-	.size	cycle_count, 4
-last_count = cycle_count + 4
-	.type	last_count, %object
-	.size	last_count, 4
-pending_exception = last_count + 4
-	.type	pending_exception, %object
-	.size	pending_exception, 4
-stop = pending_exception + 4
-	.type	stop, %object
-	.size	stop, 4
-invc_ptr = stop + 4
-	.type	invc_ptr, %object
-	.size	invc_ptr, 4
-address = invc_ptr + 4
-	.type	address, %object
-	.size	address, 4
-psxRegs = address + 4
+	.space	LO_dynarec_local_size
+
+#define DRC_VAR_(name, vname, size_) \
+	vname = dynarec_local + LO_##name; \
+	.global vname; \
+	.type	vname, %object; \
+	.size	vname, size_
+
+#define DRC_VAR(name, size_) \
+	DRC_VAR_(name, ESYM(name), size_)
+
+DRC_VAR(next_interupt, 4)
+DRC_VAR(cycle_count, 4)
+DRC_VAR(last_count, 4)
+DRC_VAR(pending_exception, 4)
+DRC_VAR(stop, 4)
+DRC_VAR(invc_ptr, 4)
+DRC_VAR(address, 4)
+DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
 
 /* psxRegs */
-	.type	psxRegs, %object
-	.size	psxRegs, psxRegs_end-psxRegs
-reg = psxRegs
-	.type	reg, %object
-	.size	reg, 128
-lo = reg + 128
-	.type	lo, %object
-	.size	lo, 4
-hi = lo + 4
-	.type	hi, %object
-	.size	hi, 4
-reg_cop0 = hi + 4
-	.type	reg_cop0, %object
-	.size	reg_cop0, 128
-reg_cop2d = reg_cop0 + 128
-	.type	reg_cop2d, %object
-	.size	reg_cop2d, 128
-reg_cop2c = reg_cop2d + 128
-	.type	reg_cop2c, %object
-	.size	reg_cop2c, 128
-PC = reg_cop2c + 128
-pcaddr = PC
-	.type	PC, %object
-	.size	PC, 4
-code = PC + 4
-	.type	code, %object
-	.size	code, 4
-cycle = code + 4
-	.type	cycle, %object
-	.size	cycle, 4
-interrupt = cycle + 4
-	.type	interrupt, %object
-	.size	interrupt, 4
-intCycle = interrupt + 4
-	.type	intCycle, %object
-	.size	intCycle, 256
-psxRegs_end = intCycle + 256
-
-rcnts = psxRegs_end
-	.type	rcnts, %object
-	.size	rcnts, 7*4*4
-rcnts_end = rcnts + 7*4*4
-
-mem_rtab = rcnts_end
-	.type	mem_rtab, %object
-	.size	mem_rtab, 4
-mem_wtab = mem_rtab + 4
-	.type	mem_wtab, %object
-	.size	mem_wtab, 4
-psxH_ptr = mem_wtab + 4
-	.type	psxH_ptr, %object
-	.size	psxH_ptr, 4
-zeromem_ptr = psxH_ptr + 4
-	.type	zeromem_ptr, %object
-	.size	zeromem_ptr, 4
-inv_code_start = zeromem_ptr + 4
-	.type	inv_code_start, %object
-	.size	inv_code_start, 4
-inv_code_end = inv_code_start + 4
-	.type	inv_code_end, %object
-	.size	inv_code_end, 4
-branch_target = inv_code_end + 4
-	.type	branch_target, %object
-	.size	branch_target, 4
-align0 = branch_target + 4 /* unused/alignment */
-	.type	align0, %object
-	.size	align0, 16
-mini_ht = align0 + 16
-	.type	mini_ht, %object
-	.size	mini_ht, 256
-restore_candidate = mini_ht + 256
-	.type	restore_candidate, %object
-	.size	restore_candidate, 512
-dynarec_local_end = restore_candidate + 512
+DRC_VAR(reg, 128)
+DRC_VAR(lo, 4)
+DRC_VAR(hi, 4)
+DRC_VAR(reg_cop0, 128)
+DRC_VAR(reg_cop2d, 128)
+DRC_VAR(reg_cop2c, 128)
+DRC_VAR(pcaddr, 4)
+@DRC_VAR(code, 4)
+@DRC_VAR(cycle, 4)
+@DRC_VAR(interrupt, 4)
+@DRC_VAR(intCycle, 256)
+
+DRC_VAR(rcnts, 7*4*4)
+DRC_VAR(mem_rtab, 4)
+DRC_VAR(mem_wtab, 4)
+DRC_VAR(psxH_ptr, 4)
+DRC_VAR(zeromem_ptr, 4)
+DRC_VAR(inv_code_start, 4)
+DRC_VAR(inv_code_end, 4)
+DRC_VAR(branch_target, 4)
+DRC_VAR(scratch_buf_ptr, 4)
+@DRC_VAR(align0, 12) /* unused/alignment */
+DRC_VAR(mini_ht, 256)
+DRC_VAR(restore_candidate, 512)
 
 /* unused */
-FCR0 = align0
-	.type	FCR0, %object
-	.size	FCR0, 4
-FCR31 = align0
-	.type	FCR31, %object
-	.size	FCR31, 4
+DRC_VAR(FCR0, 4)
+DRC_VAR(FCR31, 4)
+
+#ifdef __MACH__
+	.data
+	.align 2
+ptr_jump_in:
+	.word	ESYM(jump_in)
+ptr_jump_dirty:
+	.word	ESYM(jump_dirty)
+ptr_hash_table:
+	.word	ESYM(hash_table)
+#endif
+
+
+	.syntax unified
+	.text
+	.align	2
 
 #ifndef HAVE_ARMV5
 .macro blx rd
@@ -177,11 +119,27 @@ FCR31 = align0
 #if defined(__ARM_ARCH_7A__) && !defined(__PIC__)
 	movw	\reg, #:lower16:\var
 	movt	\reg, #:upper16:\var
+#elif defined(__ARM_ARCH_7A__) && defined(__MACH__)
+	movw	\reg, #:lower16:(\var-(1678f+4))
+	movt	\reg, #:upper16:(\var-(1678f+4))
+1678:
+	add	\reg, pc
 #else
 	ldr	\reg, =\var
 #endif
 .endm
 
+.macro load_varadr_ext reg var
+#if defined(__ARM_ARCH_7A__) && defined(__MACH__) && defined(__PIC__)
+	movw	\reg, #:lower16:(ptr_\var-(1678f+4))
+	movt	\reg, #:upper16:(ptr_\var-(1678f+4))
+1678:
+	ldr	\reg, [pc, \reg]
+#else
+	load_varadr \reg \var
+#endif
+.endm
+
 .macro mov_16 reg imm
 #ifdef __ARM_ARCH_7A__
 	movw	\reg, #\imm
@@ -205,7 +163,7 @@ FCR31 = align0
 .macro dyna_linker_main
 	/* r0 = virtual target address */
 	/* r1 = instruction to patch */
-	ldr	r3, .jiptr
+	load_varadr_ext r3, jump_in
 	/* get_page */
 	lsr     r2, r0, #12
 	mov	r6, #4096
@@ -255,10 +213,10 @@ FCR31 = align0
 3:
 	/* hash_table lookup */
 	cmp	r2, #2048
-	ldr	r3, .jdptr
+	load_varadr_ext r3, jump_dirty
 	eor	r4, r0, r0, lsl #16
 	lslcc	r2, r0, #9
-	ldr	r6, .htptr
+	load_varadr_ext r6, hash_table
 	lsr	r4, r4, #12
 	lsrcc	r2, r2, #21
 	bic	r4, r4, #15
@@ -290,8 +248,6 @@ FCR31 = align0
 8:
 .endm
 
-	.text
-	.align	2
 
 FUNCTION(dyna_linker):
 	/* r0 = virtual target address */
@@ -314,21 +270,21 @@ FUNCTION(exec_pagefault):
 	/* r0 = instruction pointer */
 	/* r1 = fault address */
 	/* r2 = cause */
-	ldr	r3, [fp, #reg_cop0+48-dynarec_local] /* Status */
+	ldr	r3, [fp, #LO_reg_cop0+48] /* Status */
 	mvn	r6, #0xF000000F
-	ldr	r4, [fp, #reg_cop0+16-dynarec_local] /* Context */
+	ldr	r4, [fp, #LO_reg_cop0+16] /* Context */
 	bic	r6, r6, #0x0F800000
-	str	r0, [fp, #reg_cop0+56-dynarec_local] /* EPC */
+	str	r0, [fp, #LO_reg_cop0+56] /* EPC */
 	orr	r3, r3, #2
-	str	r1, [fp, #reg_cop0+32-dynarec_local] /* BadVAddr */
+	str	r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
 	bic	r4, r4, r6
-	str	r3, [fp, #reg_cop0+48-dynarec_local] /* Status */
+	str	r3, [fp, #LO_reg_cop0+48] /* Status */
 	and	r5, r6, r1, lsr #9
-	str	r2, [fp, #reg_cop0+52-dynarec_local] /* Cause */
+	str	r2, [fp, #LO_reg_cop0+52] /* Cause */
 	and	r1, r1, r6, lsl #9
-	str	r1, [fp, #reg_cop0+40-dynarec_local] /* EntryHi */
+	str	r1, [fp, #LO_reg_cop0+40] /* EntryHi */
 	orr	r4, r4, r5
-	str	r4, [fp, #reg_cop0+16-dynarec_local] /* Context */
+	str	r4, [fp, #LO_reg_cop0+16] /* Context */
 	mov	r0, #0x80000000
 	bl	get_addr_ht
 	mov	pc, r0
@@ -356,12 +312,6 @@ FUNCTION(dyna_linker_ds):
 	sub	r0, r1, #4
 	b	exec_pagefault
 	.size	dyna_linker_ds, .-dyna_linker_ds
-.jiptr:
-	.word	jump_in
-.jdptr:
-	.word	jump_dirty
-.htptr:
-	.word	hash_table
 
 	.align	2
 
@@ -424,7 +374,7 @@ FUNCTION(jump_vaddr_r7):
 	add	r0, r7, #0
 	.size	jump_vaddr_r7, .-jump_vaddr_r7
 FUNCTION(jump_vaddr):
-	ldr	r1, .htptr
+	load_varadr_ext r1, hash_table
 	mvn	r3, #15
 	and	r2, r3, r2, lsr #12
 	ldr	r2, [r1, r2]!
@@ -433,16 +383,16 @@ FUNCTION(jump_vaddr):
 	ldr	r2, [r1, #8]
 	teq	r2, r0
 	ldreq	pc, [r1, #12]
-	str	r10, [fp, #cycle_count-dynarec_local]
+	str	r10, [fp, #LO_cycle_count]
 	bl	get_addr
-	ldr	r10, [fp, #cycle_count-dynarec_local]
+	ldr	r10, [fp, #LO_cycle_count]
 	mov	pc, r0
 	.size	jump_vaddr, .-jump_vaddr
 
 	.align	2
 
 FUNCTION(verify_code_ds):
-	str	r8, [fp, #branch_target-dynarec_local]
+	str	r8, [fp, #LO_branch_target]
 FUNCTION(verify_code_vm):
 FUNCTION(verify_code):
 	/* r1 = source */
@@ -472,7 +422,7 @@ FUNCTION(verify_code):
 .D3:
 	teqeq	r4, r5
 .D4:
-	ldr	r8, [fp, #branch_target-dynarec_local]
+	ldr	r8, [fp, #LO_branch_target]
 	moveq	pc, lr
 .D5:
 	bl	get_addr
@@ -482,15 +432,15 @@ FUNCTION(verify_code):
 
 	.align	2
 FUNCTION(cc_interrupt):
-	ldr	r0, [fp, #last_count-dynarec_local]
+	ldr	r0, [fp, #LO_last_count]
 	mov	r1, #0
 	mov	r2, #0x1fc
 	add	r10, r0, r10
-	str	r1, [fp, #pending_exception-dynarec_local]
+	str	r1, [fp, #LO_pending_exception]
 	and	r2, r2, r10, lsr #17
-	add	r3, fp, #restore_candidate-dynarec_local
-	str	r10, [fp, #cycle-dynarec_local] /* PCSX cycles */
-@@	str	r10, [fp, #reg_cop0+36-dynarec_local] /* Count */
+	add	r3, fp, #LO_restore_candidate
+	str	r10, [fp, #LO_cycle]		/* PCSX cycles */
+@@	str	r10, [fp, #LO_reg_cop0+36]	/* Count */
 	ldr	r4, [r2, r3]
 	mov	r10, lr
 	tst	r4, r4
@@ -498,18 +448,18 @@ FUNCTION(cc_interrupt):
 .E1:
 	bl	gen_interupt
 	mov	lr, r10
-	ldr	r10, [fp, #cycle-dynarec_local]
-	ldr	r0, [fp, #next_interupt-dynarec_local]
-	ldr	r1, [fp, #pending_exception-dynarec_local]
-	ldr	r2, [fp, #stop-dynarec_local]
-	str	r0, [fp, #last_count-dynarec_local]
+	ldr	r10, [fp, #LO_cycle]
+	ldr	r0, [fp, #LO_next_interupt]
+	ldr	r1, [fp, #LO_pending_exception]
+	ldr	r2, [fp, #LO_stop]
+	str	r0, [fp, #LO_last_count]
 	sub	r10, r10, r0
 	tst	r2, r2
-	ldmnefd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
+	ldmfdne	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
 	tst	r1, r1
 	moveq	pc, lr
 .E2:
-	ldr	r0, [fp, #pcaddr-dynarec_local]
+	ldr	r0, [fp, #LO_pcaddr]
 	bl	get_addr_ht
 	mov	pc, r0
 .E4:
@@ -528,7 +478,7 @@ FUNCTION(cc_interrupt):
 
 	.align	2
 FUNCTION(do_interrupt):
-	ldr	r0, [fp, #pcaddr-dynarec_local]
+	ldr	r0, [fp, #LO_pcaddr]
 	bl	get_addr_ht
 	add	r10, r10, #2
 	mov	pc, r0
@@ -538,13 +488,13 @@ FUNCTION(do_interrupt):
 FUNCTION(fp_exception):
 	mov	r2, #0x10000000
 .E7:
-	ldr	r1, [fp, #reg_cop0+48-dynarec_local] /* Status */
+	ldr	r1, [fp, #LO_reg_cop0+48] /* Status */
 	mov	r3, #0x80000000
-	str	r0, [fp, #reg_cop0+56-dynarec_local] /* EPC */
+	str	r0, [fp, #LO_reg_cop0+56] /* EPC */
 	orr	r1, #2
 	add	r2, r2, #0x2c
-	str	r1, [fp, #reg_cop0+48-dynarec_local] /* Status */
-	str	r2, [fp, #reg_cop0+52-dynarec_local] /* Cause */
+	str	r1, [fp, #LO_reg_cop0+48] /* Status */
+	str	r2, [fp, #LO_reg_cop0+52] /* Cause */
 	add	r0, r3, #0x80
 	bl	get_addr_ht
 	mov	pc, r0
@@ -557,13 +507,13 @@ FUNCTION(fp_exception_ds):
 
 	.align	2
 FUNCTION(jump_syscall):
-	ldr	r1, [fp, #reg_cop0+48-dynarec_local] /* Status */
+	ldr	r1, [fp, #LO_reg_cop0+48] /* Status */
 	mov	r3, #0x80000000
-	str	r0, [fp, #reg_cop0+56-dynarec_local] /* EPC */
+	str	r0, [fp, #LO_reg_cop0+56] /* EPC */
 	orr	r1, #2
 	mov	r2, #0x20
-	str	r1, [fp, #reg_cop0+48-dynarec_local] /* Status */
-	str	r2, [fp, #reg_cop0+52-dynarec_local] /* Cause */
+	str	r1, [fp, #LO_reg_cop0+48] /* Status */
+	str	r2, [fp, #LO_reg_cop0+52] /* Cause */
 	add	r0, r3, #0x80
 	bl	get_addr_ht
 	mov	pc, r0
@@ -572,52 +522,52 @@ FUNCTION(jump_syscall):
 
 	.align	2
 FUNCTION(jump_syscall_hle):
-	str	r0, [fp, #pcaddr-dynarec_local] /* PC must be set to EPC for psxException */
-	ldr	r2, [fp, #last_count-dynarec_local]
+	str	r0, [fp, #LO_pcaddr] /* PC must be set to EPC for psxException */
+	ldr	r2, [fp, #LO_last_count]
 	mov	r1, #0    /* in delay slot */
 	add	r2, r2, r10
 	mov	r0, #0x20 /* cause */
-	str	r2, [fp, #cycle-dynarec_local] /* PCSX cycle counter */
+	str	r2, [fp, #LO_cycle] /* PCSX cycle counter */
 	bl	psxException
 
-	/* note: psxException might do recorsive recompiler call from it's HLE code,
+	/* note: psxException might do recursive recompiler call from it's HLE code,
 	 * so be ready for this */
 pcsx_return:
-	ldr	r1, [fp, #next_interupt-dynarec_local]
-	ldr	r10, [fp, #cycle-dynarec_local]
-	ldr	r0, [fp, #pcaddr-dynarec_local]
+	ldr	r1, [fp, #LO_next_interupt]
+	ldr	r10, [fp, #LO_cycle]
+	ldr	r0, [fp, #LO_pcaddr]
 	sub	r10, r10, r1
-	str	r1, [fp, #last_count-dynarec_local]
+	str	r1, [fp, #LO_last_count]
 	bl	get_addr_ht
 	mov	pc, r0
 	.size	jump_syscall_hle, .-jump_syscall_hle
 
 	.align	2
 FUNCTION(jump_hlecall):
-	ldr	r2, [fp, #last_count-dynarec_local]
-	str	r0, [fp, #pcaddr-dynarec_local]
+	ldr	r2, [fp, #LO_last_count]
+	str	r0, [fp, #LO_pcaddr]
 	add	r2, r2, r10
 	adr	lr, pcsx_return
-	str	r2, [fp, #cycle-dynarec_local] /* PCSX cycle counter */
+	str	r2, [fp, #LO_cycle] /* PCSX cycle counter */
 	bx	r1
 	.size	jump_hlecall, .-jump_hlecall
 
 	.align	2
 FUNCTION(jump_intcall):
-	ldr	r2, [fp, #last_count-dynarec_local]
-	str	r0, [fp, #pcaddr-dynarec_local]
+	ldr	r2, [fp, #LO_last_count]
+	str	r0, [fp, #LO_pcaddr]
 	add	r2, r2, r10
 	adr	lr, pcsx_return
-	str	r2, [fp, #cycle-dynarec_local] /* PCSX cycle counter */
+	str	r2, [fp, #LO_cycle] /* PCSX cycle counter */
 	b	execI
 	.size	jump_hlecall, .-jump_hlecall
 
 	.align	2
 FUNCTION(new_dyna_leave):
-	ldr	r0, [fp, #last_count-dynarec_local]
+	ldr	r0, [fp, #LO_last_count]
 	add	r12, fp, #28
 	add	r10, r0, r10
-	str	r10, [fp, #cycle-dynarec_local]
+	str	r10, [fp, #LO_cycle]
 	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
 	.size	new_dyna_leave, .-new_dyna_leave
 
@@ -692,9 +642,9 @@ FUNCTION(invalidate_addr_r12):
 	mov	r0, r12
 	.size	invalidate_addr_r12, .-invalidate_addr_r12
 	.align	2
-FUNCTION(invalidate_addr_call):
-	ldr	r12, [fp, #inv_code_start-dynarec_local]
-	ldr	lr, [fp, #inv_code_end-dynarec_local]
+invalidate_addr_call:
+	ldr	r12, [fp, #LO_inv_code_start]
+	ldr	lr, [fp, #LO_inv_code_end]
 	cmp	r0, r12
 	cmpcs   lr, r0
 	blcc	invalidate_addr
@@ -706,11 +656,11 @@ FUNCTION(new_dyna_start):
 	/* ip is stored to conform EABI alignment */
 	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
 	load_varadr fp, dynarec_local
-	ldr	r0, [fp, #pcaddr-dynarec_local]
+	ldr	r0, [fp, #LO_pcaddr]
 	bl	get_addr_ht
-	ldr	r1, [fp, #next_interupt-dynarec_local]
-	ldr	r10, [fp, #cycle-dynarec_local]
-	str	r1, [fp, #last_count-dynarec_local]
+	ldr	r1, [fp, #LO_next_interupt]
+	ldr	r10, [fp, #LO_cycle]
+	str	r1, [fp, #LO_last_count]
 	sub	r10, r10, r1
 	mov	pc, r0
 	.size	new_dyna_start, .-new_dyna_start
@@ -723,7 +673,7 @@ FUNCTION(new_dyna_start):
 	/* r0 = address, r1 = handler_tab, r2 = cycles */
 	lsl	r3, r0, #20
 	lsr	r3, #(20+\tab_shift)
-	ldr	r12, [fp, #last_count-dynarec_local]
+	ldr	r12, [fp, #LO_last_count]
 	ldr	r1, [r1, r3, lsl #2]
 	add	r2, r2, r12
 	lsls	r1, #1
@@ -734,17 +684,17 @@ FUNCTION(new_dyna_start):
 	\readop	r0, [r1, r3, lsl #\tab_shift]
 .endif
 	movcc	pc, lr
-	str	r2, [fp, #cycle-dynarec_local]
+	str	r2, [fp, #LO_cycle]
 	bx	r1
 .endm
 
 FUNCTION(jump_handler_read8):
 	add     r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
-	pcsx_read_mem ldrccb, 0
+	pcsx_read_mem ldrbcc, 0
 
 FUNCTION(jump_handler_read16):
 	add     r1, #0x1000/4*4              @ shift to r16 part
-	pcsx_read_mem ldrcch, 1
+	pcsx_read_mem ldrbcc, 1
 
 FUNCTION(jump_handler_read32):
 	pcsx_read_mem ldrcc, 2
@@ -755,7 +705,7 @@ FUNCTION(jump_handler_read32):
 	lsl	r12,r0, #20
 	lsr	r12, #(20+\tab_shift)
 	ldr	r3, [r3, r12, lsl #2]
-	str	r0, [fp, #address-dynarec_local]      @ some handlers still need it..
+	str	r0, [fp, #LO_address]      @ some handlers still need it..
 	lsls	r3, #1
 	mov     r0, r2                                @ cycle return in case of direct store
 .if \tab_shift == 1
@@ -765,50 +715,50 @@ FUNCTION(jump_handler_read32):
 	\wrtop	r1, [r3, r12, lsl #\tab_shift]
 .endif
 	movcc	pc, lr
-	ldr	r12, [fp, #last_count-dynarec_local]
+	ldr	r12, [fp, #LO_last_count]
 	mov     r0, r1
 	add	r2, r2, r12
 	push	{r2, lr}
-	str	r2, [fp, #cycle-dynarec_local]
+	str	r2, [fp, #LO_cycle]
 	blx	r3
 
-	ldr	r0, [fp, #next_interupt-dynarec_local]
+	ldr	r0, [fp, #LO_next_interupt]
 	pop	{r2, r3}
-	str	r0, [fp, #last_count-dynarec_local]
+	str	r0, [fp, #LO_last_count]
 	sub	r0, r2, r0
 	bx	r3
 .endm
 
 FUNCTION(jump_handler_write8):
 	add     r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
-	pcsx_write_mem strccb, 0
+	pcsx_write_mem strbcc, 0
 
 FUNCTION(jump_handler_write16):
 	add     r3, #0x1000/4*4              @ shift to r16 part
-	pcsx_write_mem strcch, 1
+	pcsx_write_mem strhcc, 1
 
 FUNCTION(jump_handler_write32):
 	pcsx_write_mem strcc, 2
 
 FUNCTION(jump_handler_write_h):
 	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
-	ldr	r12, [fp, #last_count-dynarec_local]
-	str	r0, [fp, #address-dynarec_local]      @ some handlers still need it..
+	ldr	r12, [fp, #LO_last_count]
+	str	r0, [fp, #LO_address]      @ some handlers still need it..
 	add	r2, r2, r12
 	mov     r0, r1
 	push	{r2, lr}
-	str	r2, [fp, #cycle-dynarec_local]
+	str	r2, [fp, #LO_cycle]
 	blx	r3
 
-	ldr	r0, [fp, #next_interupt-dynarec_local]
+	ldr	r0, [fp, #LO_next_interupt]
 	pop	{r2, r3}
-	str	r0, [fp, #last_count-dynarec_local]
+	str	r0, [fp, #LO_last_count]
 	sub	r0, r2, r0
 	bx	r3
 
 FUNCTION(jump_handle_swl):
 	/* r0 = address, r1 = data, r2 = cycles */
-	ldr	r3, [fp, #mem_wtab-dynarec_local]
+	ldr	r3, [fp, #LO_mem_wtab]
 	mov	r12,r0,lsr #12
 	ldr	r3, [r3, r12, lsl #2]
 	lsls	r3, #1
@@ -832,8 +782,8 @@ FUNCTION(jump_handle_swl):
 	tst	r3, #1
 	lsrne	r1, #16		@ 1
 	lsreq	r12, r1, #24	@ 0
-	strneh	r1, [r3, #-1]
-	streqb	r12, [r3]
+	strhne	r1, [r3, #-1]
+	strbeq	r12, [r3]
 	bx	lr
 4:
 	mov	r0, r2
@@ -843,7 +793,7 @@ FUNCTION(jump_handle_swl):
 
 FUNCTION(jump_handle_swr):
 	/* r0 = address, r1 = data, r2 = cycles */
-	ldr	r3, [fp, #mem_wtab-dynarec_local]
+	ldr	r3, [fp, #LO_mem_wtab]
 	mov	r12,r0,lsr #12
 	ldr	r3, [r3, r12, lsl #2]
 	lsls	r3, #1
@@ -852,8 +802,8 @@ FUNCTION(jump_handle_swr):
 	and	r12,r3, #3
 	mov	r0, r2
 	cmp	r12,#2
-	strgtb	r1, [r3]	@ 3
-	streqh	r1, [r3]	@ 2
+	strbgt	r1, [r3]	@ 3
+	strheq	r1, [r3]	@ 2
 	cmp	r12,#1
 	strlt	r1, [r3]	@ 0
 	bxne	lr
@@ -869,9 +819,9 @@ FUNCTION(jump_handle_swr):
 
 .macro rcntx_read_mode0 num
 	/* r0 = address, r2 = cycles */
-	ldr	r3, [fp, #rcnts-dynarec_local+6*4+7*4*\num] @ cycleStart
+	ldr	r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
 	mov	r0, r2, lsl #16
-	sub	r0, r3, lsl #16
+	sub	r0, r0, r3, lsl #16
 	lsr	r0, #16
 	bx	lr
 .endm
@@ -887,7 +837,7 @@ FUNCTION(rcnt2_read_count_m0):
 
 FUNCTION(rcnt0_read_count_m1):
 	/* r0 = address, r2 = cycles */
-	ldr	r3, [fp, #rcnts-dynarec_local+6*4+7*4*0] @ cycleStart
+	ldr	r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
 	mov_16	r1, 0x3334
 	sub	r2, r2, r3
 	mul	r0, r1, r2		@ /= 5
@@ -896,7 +846,7 @@ FUNCTION(rcnt0_read_count_m1):
 
 FUNCTION(rcnt1_read_count_m1):
 	/* r0 = address, r2 = cycles */
-	ldr	r3, [fp, #rcnts-dynarec_local+6*4+7*4*1]
+	ldr	r3, [fp, #LO_rcnts+6*4+7*4*1]
 	mov_24	r1, 0x1e6cde
 	sub	r2, r2, r3
 	umull	r3, r0, r1, r2		@ ~ /= hsync_cycles, max ~0x1e6cdd
@@ -904,9 +854,9 @@ FUNCTION(rcnt1_read_count_m1):
 
 FUNCTION(rcnt2_read_count_m1):
 	/* r0 = address, r2 = cycles */
-	ldr	r3, [fp, #rcnts-dynarec_local+6*4+7*4*2]
+	ldr	r3, [fp, #LO_rcnts+6*4+7*4*2]
 	mov	r0, r2, lsl #16-3
-	sub	r0, r3, lsl #16-3
+	sub	r0, r0, r3, lsl #16-3
 	lsr	r0, #16			@ /= 8
 	bx	lr
 
diff --git a/libpcsxcore/new_dynarec/linkage_offsets.h b/libpcsxcore/new_dynarec/linkage_offsets.h
new file mode 100644
index 0000000..f7e1911
--- /dev/null
+++ b/libpcsxcore/new_dynarec/linkage_offsets.h
@@ -0,0 +1,41 @@
+
+#define LO_next_interupt	64
+#define LO_cycle_count		(LO_next_interupt + 4)
+#define LO_last_count		(LO_cycle_count + 4)
+#define LO_pending_exception	(LO_last_count + 4)
+#define LO_stop			(LO_pending_exception + 4)
+#define LO_invc_ptr		(LO_stop + 4)
+#define LO_address		(LO_invc_ptr + 4)
+#define LO_psxRegs		(LO_address + 4)
+#define LO_reg			(LO_psxRegs)
+#define LO_lo			(LO_reg + 128)
+#define LO_hi			(LO_lo + 4)
+#define LO_reg_cop0		(LO_hi + 4)
+#define LO_reg_cop2d		(LO_reg_cop0 + 128)
+#define LO_reg_cop2c		(LO_reg_cop2d + 128)
+#define LO_PC			(LO_reg_cop2c + 128)
+#define LO_pcaddr		(LO_PC)
+#define LO_code			(LO_PC + 4)
+#define LO_cycle		(LO_code + 4)
+#define LO_interrupt		(LO_cycle + 4)
+#define LO_intCycle		(LO_interrupt + 4)
+#define LO_psxRegs_end		(LO_intCycle + 256)
+#define LO_rcnts		(LO_psxRegs_end)
+#define LO_rcnts_end		(LO_rcnts + 7*4*4)
+#define LO_mem_rtab		(LO_rcnts_end)
+#define LO_mem_wtab		(LO_mem_rtab + 4)
+#define LO_psxH_ptr		(LO_mem_wtab + 4)
+#define LO_zeromem_ptr		(LO_psxH_ptr + 4)
+#define LO_inv_code_start	(LO_zeromem_ptr + 4)
+#define LO_inv_code_end		(LO_inv_code_start + 4)
+#define LO_branch_target	(LO_inv_code_end + 4)
+#define LO_scratch_buf_ptr	(LO_branch_target + 4)
+#define LO_align0		(LO_scratch_buf_ptr + 4)
+#define LO_mini_ht		(LO_align0 + 12)
+#define LO_restore_candidate	(LO_mini_ht + 256)
+#define LO_dynarec_local_size	(LO_restore_candidate + 512)
+
+#define LO_FCR0			(LO_align0)
+#define LO_FCR31		(LO_align0)
+
+#define LO_cop2_to_scratch_buf	(LO_scratch_buf_ptr - LO_reg_cop2d)
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index a3b766a..8437008 100644
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -44,6 +44,14 @@
 #ifdef __BLACKBERRY_QNX__
 #undef __clear_cache
 #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
+#elif defined(__MACH__)
+#include <libkern/OSCacheControl.h>
+#define __clear_cache mach_clear_cache
+static void __clear_cache(void *start, void *end) {
+  size_t len = (char *)end - (char *)start;
+  sys_dcache_flush(start, len);
+  sys_icache_invalidate(start, len);
+}
 #endif
 
 #define MAXBLOCK 4096
@@ -656,7 +664,7 @@ uint64_t get_const(struct regstat *cur,signed char reg)
       return current_constmap[hr];
     }
   }
-  printf("Unknown constant in r%d\n",reg);
+  SysPrintf("Unknown constant in r%d\n",reg);
   exit(1);
 }
 
@@ -1997,7 +2005,7 @@ void delayslot_alloc(struct regstat *current,int i)
     case HLECALL:
     case SPAN:
       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
-      printf("Disabled speculative precompilation\n");
+      SysPrintf("Disabled speculative precompilation\n");
       stop_after_jal=1;
       break;
     case IMM16:
@@ -3369,7 +3377,7 @@ void store_assemble(int i,struct regstat *i_regs)
   // basic current block modification detection..
   // not looking back as that should be in mips cache already
   if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
-    printf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
+    SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
     assert(i_regs->regmap==regs[i].regmap); // not delay slot
     if(i_regs->regmap==regs[i].regmap) {
       load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
@@ -4077,7 +4085,7 @@ void ds_assemble(int i,struct regstat *i_regs)
     case CJUMP:
     case SJUMP:
     case FJUMP:
-      printf("Jump in the delay slot.  This is probably a bug.\n");
+      SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
   }
   is_delayslot=0;
 }
@@ -4970,7 +4978,7 @@ void ds_assemble_entry(int i)
     case CJUMP:
     case SJUMP:
     case FJUMP:
-      printf("Jump in the delay slot.  This is probably a bug.\n");
+      SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
   }
   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
@@ -5248,7 +5256,7 @@ void do_ccstub(int n)
       }
       emit_writeword(r,(int)&pcaddr);
     }
-    else {printf("Unknown branch type in do_ccstub\n");exit(1);}
+    else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
   }
   // Update cycle count
   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
@@ -6805,7 +6813,7 @@ static void pagespan_ds()
     case CJUMP:
     case SJUMP:
     case FJUMP:
-      printf("Jump in the delay slot.  This is probably a bug.\n");
+      SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
   }
   int btaddr=get_reg(regs[0].regmap,BTREG);
   if(btaddr<0) {
@@ -8037,11 +8045,11 @@ void new_dynarec_init()
   if (mmap (out, 1<<TARGET_SIZE_2,
             PROT_READ | PROT_WRITE | PROT_EXEC,
             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
-            -1, 0) <= 0) {printf("mmap() failed\n");}
+            -1, 0) <= 0) {SysPrintf("mmap() failed\n");}
 #else
   // not all systems allow execute in data segment by default
   if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
-    printf("mprotect() failed\n");
+    SysPrintf("mprotect() failed\n");
 #endif
 #ifdef MUPEN64
   rdword=&readmem_dword;
@@ -8100,20 +8108,20 @@ void new_dynarec_init()
   ram_offset=(u_int)rdram-0x80000000;
 #endif
   if (ram_offset!=0)
-    printf("warning: RAM is not directly mapped, performance will suffer\n");
+    SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
 }
 
 void new_dynarec_cleanup()
 {
   int n;
   #if BASE_ADDR_FIXED
-  if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
+  if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
   #endif
   for(n=0;n<4096;n++) ll_clear(jump_in+n);
   for(n=0;n<4096;n++) ll_clear(jump_out+n);
   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
   #ifdef ROM_COPY
-  if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
+  if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
   #endif
 }
 
@@ -8210,7 +8218,7 @@ int new_recompile_block(int addr)
   }
 #endif
   else {
-    printf("Compile at bogus memory address: %x \n", (int)addr);
+    SysPrintf("Compile at bogus memory address: %x \n", (int)addr);
     exit(1);
   }
 
@@ -8539,7 +8547,7 @@ int new_recompile_block(int addr)
       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
 #endif
       default: strcpy(insn[i],"???"); type=NI;
-        printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
+        SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
         break;
     }
     itype[i]=type;
@@ -8814,7 +8822,7 @@ int new_recompile_block(int addr)
       // branch in delay slot?
       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
         // don't handle first branch and call interpreter if it's hit
-        printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
+        SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
         do_in_intrp=1;
       }
       // basic load delay detection
@@ -8822,14 +8830,14 @@ int new_recompile_block(int addr)
         int t=(ba[i-1]-start)/4;
         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
           // jump target wants DS result - potential load delay effect
-          printf("load delay @%08x (%08x)\n", addr + i*4, addr);
+          SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
           do_in_intrp=1;
           bt[t+1]=1; // expected return from interpreter
         }
         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
           // v0 overwrite like this is a sign of trouble, bail out
-          printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
+          SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
           do_in_intrp=1;
         }
       }
@@ -8876,7 +8884,7 @@ int new_recompile_block(int addr)
     // Stop if we're compiling junk
     if(itype[i]==NI&&opcode[i]==0x11) {
       done=stop_after_jal=1;
-      printf("Disabled speculative precompilation\n");
+      SysPrintf("Disabled speculative precompilation\n");
     }
   }
   slen=i;
@@ -9093,7 +9101,7 @@ int new_recompile_block(int addr)
         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
         current.u|=1;
         current.uu|=1;
-      } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
+      } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
     }
     is_ds[i]=ds;
     if(ds) {
@@ -10159,7 +10167,7 @@ int new_recompile_block(int addr)
                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
                 {
-                  printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
+                  SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
                 }
                 regmap_pre[i+1][hr]=-1;
diff --git a/plugins/dfsound/arm_utils.S b/plugins/dfsound/arm_utils.S
index ddc3714..cbcc7f7 100644
--- a/plugins/dfsound/arm_utils.S
+++ b/plugins/dfsound/arm_utils.S
@@ -10,15 +10,28 @@
 
 #include "arm_features.h"
 
+#ifdef __MACH__
+.data
+.align 2
+ptr_ChanBuf:   .word _ChanBuf
+ptr_SSumLR:    .word _SSumLR
+ptr_sRVBStart: .word _sRVBStart
+#endif
+
 .text
 .align 2
 
 .macro load_varadr reg var
 #if defined(__ARM_ARCH_7A__) && !defined(__PIC__)
-	movw	\reg, #:lower16:EVAR(\var)
-	movt	\reg, #:upper16:EVAR(\var)
+	movw	\reg, #:lower16:ESYM(\var)
+	movt	\reg, #:upper16:ESYM(\var)
+#elif defined(__ARM_ARCH_7A__) && defined(__MACH__)
+	movw	\reg, #:lower16:(ptr_\var-(1678f+4))
+	movt	\reg, #:upper16:(ptr_\var-(1678f+4))
+1678:
+	ldr	\reg, [pc, \reg]
 #else
-	ldr	\reg, =EVAR(\var)
+	ldr	\reg, =ESYM(\var)
 #endif
 .endm