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| author | notaz | 2011-02-16 23:38:06 +0200 |
|---|---|---|
| committer | notaz | 2011-02-17 17:05:11 +0200 |
| commit | 619e5ded1a7bfe68dc95782ac9a510f746319683 (patch) | |
| tree | 9d981a4b4764a395543eb29668b40f3e1b4d83d8 | |
| parent | 0bbd14543fec5fd4f5664b676771812663235252 (diff) | |
| download | pcsx_rearmed-619e5ded1a7bfe68dc95782ac9a510f746319683.tar.gz pcsx_rearmed-619e5ded1a7bfe68dc95782ac9a510f746319683.tar.bz2 pcsx_rearmed-619e5ded1a7bfe68dc95782ac9a510f746319683.zip | |
drc: merge register types from Ari64's code
but don't merge RAM_OFFSET stuff, I don't want to mess with this yet
| -rw-r--r-- | libpcsxcore/new_dynarec/new_dynarec.c | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 9bc0f60..1435017 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -134,19 +134,21 @@ struct ll_entry #define CSREG 35 // Coprocessor status #define CCREG 36 // Cycle count #define INVCP 37 // Pointer to invalid_code -#define TEMPREG 38 -#define FTEMP 38 // FPU/LDL/LDR temporary register -#define PTEMP 39 // Prefetch temporary register -#define TLREG 40 // TLB mapping offset -#define RHASH 41 // Return address hash -#define RHTBL 42 // Return address hash table address -#define RTEMP 43 // JR/JALR address register -#define MAXREG 43 -#define AGEN1 44 // Address generation temporary register -#define AGEN2 45 // Address generation temporary register -#define MGEN1 46 // Maptable address generation temporary register -#define MGEN2 47 // Maptable address generation temporary register -#define BTREG 48 // Branch target temporary register +#define MMREG 38 // Pointer to memory_map +#define ROREG 39 // ram offset (if rdram!=0x80000000) +#define TEMPREG 40 +#define FTEMP 40 // FPU temporary register +#define PTEMP 41 // Prefetch temporary register +#define TLREG 42 // TLB mapping offset +#define RHASH 43 // Return address hash +#define RHTBL 44 // Return address hash table address +#define RTEMP 45 // JR/JALR address register +#define MAXREG 45 +#define AGEN1 46 // Address generation temporary register +#define AGEN2 47 // Address generation temporary register +#define MGEN1 48 // Maptable address generation temporary register +#define MGEN2 49 // Maptable address generation temporary register +#define BTREG 50 // Branch target temporary register /* instruction types */ #define NOP 0 // No operation |