get rid of old memhandlers

6 files changed, 67 insertions, 675 deletions

diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c
index 57c6e91..786838d 100644
--- a/libpcsxcore/new_dynarec/assem_arm.c
+++ b/libpcsxcore/new_dynarec/assem_arm.c
@@ -245,6 +245,7 @@ int verify_dirty(int addr)
   #endif
   if((*ptr&0xFF000000)!=0xeb000000) ptr++;
   assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
+#ifndef DISABLE_TLB
   u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
   if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
     unsigned int page=source>>12;
@@ -255,6 +256,7 @@ int verify_dirty(int addr)
     }
     source = source+(map_value<<2);
   }
+#endif
   //printf("verify_dirty: %x %x %x\n",source,copy,len);
   return !memcmp((void *)source,(void *)copy,len);
 }
@@ -298,11 +300,13 @@ void get_bounds(int addr,u_int *start,u_int *end)
   #endif
   if((*ptr&0xFF000000)!=0xeb000000) ptr++;
   assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
+#ifndef DISABLE_TLB
   u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
   if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
     if(memory_map[source>>12]>=0x80000000) source = 0;
     else source = source+(memory_map[source>>12]<<2);
   }
+#endif
   *start=source;
   *end=source+len;
 }
@@ -3508,6 +3512,8 @@ do_cop1stub(int n)
   emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
 }
 
+#ifndef DISABLE_TLB
+
 /* TLB */
 
 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
@@ -3591,6 +3597,17 @@ generate_map_const(u_int addr,int reg) {
   emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
 }
 
+#else
+
+static int do_tlb_r() { return 0; }
+static int do_tlb_r_branch() { return 0; }
+static int gen_tlb_addr_r() { return 0; }
+static int do_tlb_w() { return 0; }
+static int do_tlb_w_branch() { return 0; }
+static int gen_tlb_addr_w() { return 0; }
+
+#endif // DISABLE_TLB
+
 /* Special assem */
 
 void shift_assemble_arm(int i,struct regstat *i_regs)
@@ -4061,18 +4078,20 @@ void cop0_assemble(int i,struct regstat *i_regs)
     signed char s=get_reg(i_regs->regmap,rs1[i]);
     char copr=(source[i]>>11)&0x1f;
     assert(s>=0);
+#ifdef MUPEN64
     emit_writeword(s,(int)&readmem_dword);
     wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
-#ifdef MUPEN64
     emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
     emit_movimm((source[i]>>11)&0x1f,1);
     emit_writeword(0,(int)&PC);
     emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
+#else
+    wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
 #endif
     if(copr==9||copr==11||copr==12||copr==13) {
-      emit_readword((int)&last_count,ECX);
+      emit_readword((int)&last_count,HOST_TEMPREG);
       emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
-      emit_add(HOST_CCREG,ECX,HOST_CCREG);
+      emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
       emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
       emit_writeword(HOST_CCREG,(int)&Count);
     }
@@ -4089,19 +4108,23 @@ void cop0_assemble(int i,struct regstat *i_regs)
         emit_writeword(HOST_CCREG,(int)&last_count);
         emit_movimm(0,HOST_CCREG);
         emit_storereg(CCREG,HOST_CCREG);
+        if(s!=1)
+          emit_mov(s,1);
         emit_movimm(copr,0);
         emit_call((int)pcsx_mtc0_ds);
         return;
       }
 #endif
-      emit_movimm(start+i*4+4,0);
-      emit_movimm(0,1);
-      emit_writeword(0,(int)&pcaddr);
-      emit_writeword(1,(int)&pending_exception);
+      emit_movimm(start+i*4+4,HOST_TEMPREG);
+      emit_writeword(HOST_TEMPREG,(int)&pcaddr);
+      emit_movimm(0,HOST_TEMPREG);
+      emit_writeword(HOST_TEMPREG,(int)&pending_exception);
     }
     //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
     //else
 #ifdef PCSX
+    if(s!=1)
+      emit_mov(s,1);
     emit_movimm(copr,0);
     emit_call((int)pcsx_mtc0);
 #else
diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
index 56c6b77..9203c74 100644
--- a/libpcsxcore/new_dynarec/emu_if.c
+++ b/libpcsxcore/new_dynarec/emu_if.c
@@ -116,17 +116,17 @@ void gen_interupt()
 // from interpreter
 extern void MTC0(int reg, u32 val);
 
-void pcsx_mtc0(u32 reg)
+void pcsx_mtc0(u32 reg, u32 val)
 {
-	evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
-	MTC0(reg, readmem_word);
+	evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
+	MTC0(reg, val);
 	gen_interupt();
 }
 
-void pcsx_mtc0_ds(u32 reg)
+void pcsx_mtc0_ds(u32 reg, u32 val)
 {
-	evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
-	MTC0(reg, readmem_word);
+	evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
+	MTC0(reg, val);
 }
 
 void new_dyna_save(void)
diff --git a/libpcsxcore/new_dynarec/emu_if.h b/libpcsxcore/new_dynarec/emu_if.h
index 0d954df..beb517c 100644
--- a/libpcsxcore/new_dynarec/emu_if.h
+++ b/libpcsxcore/new_dynarec/emu_if.h
@@ -47,19 +47,7 @@ void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
 void jump_handle_swl(u32 addr, u32 data, u32 cycles);
 void jump_handle_swr(u32 addr, u32 data, u32 cycles);
 
-extern void (*readmem[0x10000])();
-extern void (*readmemb[0x10000])();
-extern void (*readmemh[0x10000])();
-extern void (*writemem[0x10000])();
-extern void (*writememb[0x10000])();
-extern void (*writememh[0x10000])();
-
 extern unsigned int address;
-extern unsigned int readmem_word; /* same as readmem_dword */
-extern unsigned int word;	/* write */
-extern unsigned short hword;
-extern unsigned char byte;
-
 extern void *psxH_ptr;
 
 // same as invalid_code, just a region for ram write checks (inclusive)
@@ -70,8 +58,8 @@ extern unsigned int next_interupt;
 extern int pending_exception;
 
 /* called by drc */
-void pcsx_mtc0(u32 reg);
-void pcsx_mtc0_ds(u32 reg);
+void pcsx_mtc0(u32 reg, u32 val);
+void pcsx_mtc0_ds(u32 reg, u32 val);
 
 /* misc */
 extern void (*psxHLEt[])();
diff --git a/libpcsxcore/new_dynarec/linkage_arm.s b/libpcsxcore/new_dynarec/linkage_arm.s
index c1bc8c9..23a69cf 100644
--- a/libpcsxcore/new_dynarec/linkage_arm.s
+++ b/libpcsxcore/new_dynarec/linkage_arm.s
@@ -40,22 +40,14 @@ rdram = 0x80000000
 	.global	stop
 	.global	invc_ptr
 	.global	address
-	.global	readmem_dword
-	.global	readmem_word
-	.global	dword
-	.global	word
-	.global	hword
-	.global	byte
 	.global	branch_target
 	.global	PC
 	.global	mini_ht
 	.global	restore_candidate
-	.global	memory_map
 	/* psx */
 	.global psxRegs
 	.global mem_rtab
 	.global mem_wtab
-	.global nd_pcsx_io
 	.global psxH_ptr
 	.global inv_code_start
 	.global inv_code_end
@@ -87,29 +79,7 @@ invc_ptr = stop + 4
 address = invc_ptr + 4
 	.type	address, %object
 	.size	address, 4
-readmem_dword = address + 4
-readmem_word = readmem_dword
-	.type	readmem_dword, %object
-	.size	readmem_dword, 8
-dword = readmem_dword + 8
-	.type	dword, %object
-	.size	dword, 8
-word = dword + 8
-	.type	word, %object
-	.size	word, 4
-hword = word + 4
-	.type	hword, %object
-	.size	hword, 2
-byte = hword + 2
-	.type	byte, %object
-	.size	byte, 1 /* 1 byte free */
-FCR0 = hword + 4
-	.type	FCR0, %object
-	.size	FCR0, 4
-FCR31 = FCR0 + 4
-	.type	FCR31, %object
-	.size	FCR31, 4
-psxRegs = FCR31 + 4
+psxRegs = address + 4
 
 /* psxRegs */
 	.type	psxRegs, %object
@@ -156,38 +126,7 @@ mem_rtab = psxRegs_end
 mem_wtab = mem_rtab + 4
 	.type	mem_wtab, %object
 	.size	mem_wtab, 4
-
-/* nd_pcsx_io */
-nd_pcsx_io = mem_wtab + 4
-	.type	nd_pcsx_io, %object
-	.size	nd_pcsx_io, nd_pcsx_io_end-nd_pcsx_io
-tab_read8 = nd_pcsx_io
-	.type	tab_read8, %object
-	.size	tab_read8, 4
-tab_read16 = tab_read8 + 4
-	.type	tab_read16, %object
-	.size	tab_read16, 4
-tab_read32 = tab_read16 + 4
-	.type	tab_read32, %object
-	.size	tab_read32, 4
-tab_write8 = tab_read32 + 4
-	.type	tab_write8, %object
-	.size	tab_write8, 4
-tab_write16 = tab_write8 + 4
-	.type	tab_write16, %object
-	.size	tab_write16, 4
-tab_write32 = tab_write16 + 4
-	.type	tab_write32, %object
-	.size	tab_write32, 4
-spu_readf = tab_write32 + 4
-	.type	spu_readf, %object
-	.size	spu_readf, 4
-spu_writef = spu_readf + 4
-	.type	spu_writef, %object
-	.size	spu_writef, 4
-nd_pcsx_io_end = spu_writef + 4
-
-psxH_ptr = nd_pcsx_io_end
+psxH_ptr = mem_wtab + 4
 	.type	psxH_ptr, %object
 	.size	psxH_ptr, 4
 inv_code_start = psxH_ptr + 4
@@ -196,22 +135,27 @@ inv_code_start = psxH_ptr + 4
 inv_code_end = inv_code_start + 4
 	.type	inv_code_end, %object
 	.size	inv_code_end, 4
-align0 = inv_code_end + 4 /* just for alignment */
-	.type	align0, %object
-	.size	align0, 4
-branch_target = align0 + 4
+branch_target = inv_code_end + 4
 	.type	branch_target, %object
 	.size	branch_target, 4
-mini_ht = branch_target + 4
+align0 = branch_target + 4 /* unused/alignment */
+	.type	align0, %object
+	.size	align0, 4
+mini_ht = align0 + 4
 	.type	mini_ht, %object
 	.size	mini_ht, 256
 restore_candidate = mini_ht + 256
 	.type	restore_candidate, %object
 	.size	restore_candidate, 512
-memory_map = restore_candidate + 512
-	.type	memory_map, %object
-	.size	memory_map, 4194304
-dynarec_local_end = memory_map + 4194304
+dynarec_local_end = restore_candidate + 512
+
+/* unused */
+FCR0 = align0
+	.type	FCR0, %object
+	.size	FCR0, 4
+FCR31 = align0
+	.type	FCR31, %object
+	.size	FCR31, 4
 
 .macro load_var_adr reg var
 .if HAVE_ARMV7
@@ -694,22 +638,6 @@ new_dyna_leave:
 	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
 	.size	new_dyna_leave, .-new_dyna_leave
 
-	/* these are used to call memhandlers */
-	.align	2
-	.global	indirect_jump_indexed
-	.type	indirect_jump_indexed, %function
-indirect_jump_indexed:
-	ldr	r0, [r0, r1, lsl #2]
-	.global	indirect_jump
-	.type	indirect_jump, %function
-indirect_jump:
-	ldr	r12, [fp, #last_count-dynarec_local]
-	add	r2, r2, r12 
-	str	r2, [fp, #cycle-dynarec_local]
-	mov	pc, r0
-	.size	indirect_jump, .-indirect_jump
-	.size	indirect_jump_indexed, .-indirect_jump_indexed
-
 	.align	2
 	.global	invalidate_addr_r0
 	.type	invalidate_addr_r0, %function
@@ -835,28 +763,6 @@ new_dyna_start:
 /* --------------------------------------- */
 
 .align	2
-.global	ari_read_ram8
-.global	ari_read_ram16
-.global	ari_read_ram32
-.global	ari_read_ram_mirror8
-.global	ari_read_ram_mirror16
-.global	ari_read_ram_mirror32
-.global	ari_write_ram8
-.global	ari_write_ram16
-.global	ari_write_ram32
-.global	ari_write_ram_mirror8
-.global	ari_write_ram_mirror16
-.global	ari_write_ram_mirror32
-.global	ari_write_ram_mirror_ro32
-.global	ari_read_bios8
-.global	ari_read_bios16
-.global	ari_read_bios32
-.global	ari_read_io8
-.global	ari_read_io16
-.global	ari_read_io32
-.global	ari_write_io8
-.global	ari_write_io16
-.global	ari_write_io32
 .global	jump_handler_read8
 .global	jump_handler_read16
 .global	jump_handler_read32
@@ -867,270 +773,6 @@ new_dyna_start:
 .global jump_handle_swl
 .global jump_handle_swr
 
-.macro ari_read_ram bic_const op
-	ldr	r0, [fp, #address-dynarec_local]
-.if \bic_const
-	bic	r0, r0, #\bic_const
-.endif
-	\op	r0, [r0]
-	str	r0, [fp, #readmem_dword-dynarec_local]
-	mov	pc, lr
-.endm
-
-ari_read_ram8:
-	ari_read_ram 0, ldrb
-
-ari_read_ram16:
-	ari_read_ram 1, ldrh
-
-ari_read_ram32:
-	ari_read_ram 3, ldr
-
-.macro ari_read_ram_mirror mvn_const, op
-	ldr	r0, [fp, #address-dynarec_local]
-	mvn	r1, #\mvn_const
-	and	r0, r1, lsr #11
-	orr	r0, r0, #1<<31
-	\op	r0, [r0]
-	str	r0, [fp, #readmem_dword-dynarec_local]
-	mov	pc, lr
-.endm
-
-ari_read_ram_mirror8:
-	ari_read_ram_mirror 0, ldrb
-
-ari_read_ram_mirror16:
-	ari_read_ram_mirror (1<<11), ldrh
-
-ari_read_ram_mirror32:
-	ari_read_ram_mirror (3<<11), ldr
-
-/* invalidation is already taken care of by the caller */
-.macro ari_write_ram bic_const var pf
-	ldr	r0, [fp, #address-dynarec_local]
-	ldr\pf	r1, [fp, #\var-dynarec_local]
-.if \bic_const
-	bic	r0, r0, #\bic_const
-.endif
-	str\pf	r1, [r0]
-	mov	pc, lr
-.endm
-
-ari_write_ram8:
-	ari_write_ram 0, byte, b
-
-ari_write_ram16:
-	ari_write_ram 1, hword, h
-
-ari_write_ram32:
-	ari_write_ram 3, word,
-
-.macro ari_write_ram_mirror mvn_const var pf
-	ldr	r0, [fp, #address-dynarec_local]
-	mvn	r3, #\mvn_const
-	ldr\pf	r1, [fp, #\var-dynarec_local]
-	and	r0, r3, lsr #11
-	ldr	r2, [fp, #invc_ptr-dynarec_local]
-	orr	r0, r0, #1<<31
-	ldrb	r2, [r2, r0, lsr #12]
-	str\pf	r1, [r0]
-	tst	r2, r2
-	movne	pc, lr
-	ldr	r1, [fp, #inv_code_start-dynarec_local]
-	ldr	r2, [fp, #inv_code_end-dynarec_local]
-	cmp	r0, r1
-	cmpcs   r2, r0
-	movcs	pc, lr
-	nop
-	b	invalidate_addr
-.endm
-
-ari_write_ram_mirror8:
-	ari_write_ram_mirror 0, byte, b
-
-ari_write_ram_mirror16:
-	ari_write_ram_mirror (1<<11), hword, h
-
-ari_write_ram_mirror32:
-	ari_write_ram_mirror (3<<11), word,
-
-ari_write_ram_mirror_ro32:
-	load_var_adr r0, pcsx_ram_is_ro
-	ldr	r0, [r0]
-	tst	r0, r0
-	movne	pc, lr
-	nop
-	b	ari_write_ram_mirror32
-
-
-.macro ari_read_bios_mirror bic_const op
-	ldr	r0, [fp, #address-dynarec_local]
-	orr	r0, r0, #0x80000000
-	bic	r0, r0, #(0x20000000|\bic_const)	@ map to 0x9fc...
-	\op	r0, [r0]
-	str	r0, [fp, #readmem_dword-dynarec_local]
-	mov	pc, lr
-.endm
-
-ari_read_bios8:
-	ari_read_bios_mirror 0, ldrb
-
-ari_read_bios16:
-	ari_read_bios_mirror 1, ldrh
-
-ari_read_bios32:
-	ari_read_bios_mirror 3, ldr
-
-
-@ for testing
-.macro ari_read_io_old tab_shift
-	str     lr, [sp, #-8]! @ EABI alignment..
-.if \tab_shift == 0
-	bl	psxHwRead32
-.endif
-.if \tab_shift == 1
-	bl	psxHwRead16
-.endif
-.if \tab_shift == 2
-	bl	psxHwRead8
-.endif
-	str	r0, [fp, #readmem_dword-dynarec_local]
-	ldr     pc, [sp], #8
-.endm
-
-.macro ari_read_io readop mem_tab tab_shift
-	ldr	r0, [fp, #address-dynarec_local]
-	ldr	r1, [fp, #psxH_ptr-dynarec_local]
-.if \tab_shift == 0
-	bic	r0, r0, #3
-.endif
-.if \tab_shift == 1
-	bic	r0, r0, #1
-.endif
-	bic	r2, r0, #0x1f800000
-	ldr	r12,[fp, #\mem_tab-dynarec_local]
-	subs	r3, r2, #0x1000
-	blo	2f
-@	ari_read_io_old \tab_shift
-	cmp	r3, #0x880
-	bhs	1f
-	ldr	r12,[r12, r3, lsl #\tab_shift]
-	tst	r12,r12
-	beq	2f
-0:
-	str     lr, [sp, #-8]! @ EABI alignment..
-	blx	r12
-	str	r0, [fp, #readmem_dword-dynarec_local]
-	ldr     pc, [sp], #8
-
-1:
-.if \tab_shift == 1 @ read16
-	cmp	r2, #0x1c00
-	blo	2f
-	cmp	r2, #0x1e00
-	bhs	2f
-	ldr	r12,[fp, #spu_readf-dynarec_local]
-	b	0b
-.endif
-2:
-	@ no handler, just read psxH
-	\readop	r0, [r1, r2]
-	str	r0, [fp, #readmem_dword-dynarec_local]
-	mov	pc, lr
-.endm
-
-ari_read_io8:
-	ari_read_io ldrb, tab_read8, 2
-
-ari_read_io16:
-	ari_read_io ldrh, tab_read16, 1
-
-ari_read_io32:
-	ari_read_io ldr, tab_read32, 0
-
-.macro ari_write_io_old tab_shift
-.if \tab_shift == 0
-	b	psxHwWrite32
-.endif
-.if \tab_shift == 1
-	b	psxHwWrite16
-.endif
-.if \tab_shift == 2
-	b	psxHwWrite8
-.endif
-.endm
-
-.macro ari_write_io pf var mem_tab tab_shift
-	ldr	r0, [fp, #address-dynarec_local]
-	ldr\pf	r1, [fp, #\var-dynarec_local]
-.if \tab_shift == 0
-	bic	r0, r0, #3
-.endif
-.if \tab_shift == 1
-	bic	r0, r0, #1
-.endif
-	bic	r2, r0, #0x1f800000
-	ldr	r12,[fp, #\mem_tab-dynarec_local]
-	subs	r3, r2, #0x1000
-	blo	0f
-@	ari_write_io_old \tab_shift
-	cmp	r3, #0x880
-	bhs	1f
-	ldr	r12,[r12, r3, lsl #\tab_shift]
-	mov	r0, r1
-	tst	r12,r12
-	bxne	r12
-0:
-	ldr	r3, [fp, #psxH_ptr-dynarec_local]
-	str\pf	r1, [r2, r3]
-	mov	pc, lr
-1:
-	cmp	r2, #0x1c00
-	blo	0b
-	cmp	r2, #0x1e00
-.if \tab_shift != 0
-	ldrlo	pc, [fp, #spu_writef-dynarec_local]
-.else
-	@ write32 to SPU - very rare case (is this correct?)
-	bhs	0b
-	add	r2, r0, #2
-	mov	r3, r1, lsr #16
-	push	{r2,r3,lr}
-	mov	lr, pc
-	ldr	pc, [fp, #spu_writef-dynarec_local]
-	pop	{r0,r1,lr}
-	ldr	pc, [fp, #spu_writef-dynarec_local]
-.endif
-	nop
-	b	0b
-.endm
-
-ari_write_io8:
-	@ PCSX always writes to psxH, so do we for consistency
-	ldr	r0, [fp, #address-dynarec_local]
-	ldr	r3, [fp, #psxH_ptr-dynarec_local]
-	ldrb	r1, [fp, #byte-dynarec_local]
-	bic	r2, r0, #0x1f800000
-	ldr	r12,[fp, #tab_write8-dynarec_local]
-	strb	r1, [r2, r3]
-	subs	r3, r2, #0x1000
-	movlo	pc, lr
-@	ari_write_io_old 2
-	cmp	r3, #0x880
-	movhs	pc, lr
-	ldr	r12,[r12, r3, lsl #2]
-	mov	r0, r1
-	tst	r12,r12
-	bxne	r12
-	mov	pc, lr
-
-ari_write_io16:
-	ari_write_io h, hword, tab_write16, 1
-
-ari_write_io32:
-	ari_write_io , word, tab_write32, 0
-
-/* */
 
 .macro pcsx_read_mem readop tab_shift
 	/* r0 = address, r1 = handler_tab, r2 = cycles */
@@ -1250,7 +892,7 @@ jump_handle_swl:
 	bx	lr
 4:
 	mov	r0, r2
-	b	abort
+@	b	abort
 	bx	lr		@ TODO?
 
 
@@ -1276,7 +918,7 @@ jump_handle_swr:
 	bx	lr
 4:
 	mov	r0, r2
-	b	abort
+@	b	abort
 	bx	lr		@ TODO?
 
 
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index 2c9130b..64ea3bc 100644
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -380,7 +380,9 @@ void *get_addr(u_int vaddr)
         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
         invalid_code[vaddr>>12]=0;
         inv_code_start=inv_code_end=~0;
+#ifndef DISABLE_TLB
         memory_map[vaddr>>12]|=0x40000000;
+#endif
         if(vpage<2048) {
 #ifndef DISABLE_TLB
           if(tlb_LUT_r[vaddr>>12]) {
@@ -1338,11 +1340,13 @@ void clean_blocks(u_int page)
               inv|=invalid_code[i];
             }
           }
+#ifndef DISABLE_TLB
           if((signed int)head->vaddr>=(signed int)0xC0000000) {
             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
             //printf("addr=%x start=%x end=%x\n",addr,start,end);
             if(addr<start||addr>=end) inv=1;
           }
+#endif
           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
             inv=1;
           }
@@ -4223,6 +4227,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
         //  printf("poor load scheduling!\n");
       }
       else if(c) {
+#ifndef DISABLE_TLB
         if(rm>=0) {
           if(!entry||entry[rm]!=mgr) {
             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
@@ -4237,6 +4242,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
             }
           }
         }
+#endif
         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
           if(!entry||entry[ra]!=agr) {
             if (opcode[i]==0x22||opcode[i]==0x26) {
@@ -4265,7 +4271,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
   // Preload constants for next instruction
   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
     int agr,ra;
-    #ifndef HOST_IMM_ADDR32
+    #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
     // Mapper entry
     agr=MGEN1+((i+1)&1);
     ra=get_reg(i_regs->regmap,agr);
@@ -7901,13 +7907,13 @@ void new_dynarec_clear_full()
   // TLB
 #ifndef DISABLE_TLB
   using_tlb=0;
-#endif
   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
     memory_map[n]=-1;
   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
     memory_map[n]=((u_int)rdram-0x80000000)>>2;
   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
     memory_map[n]=-1;
+#endif
   for(n=0;n<4096;n++) ll_clear(jump_in+n);
   for(n=0;n<4096;n++) ll_clear(jump_out+n);
   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index d5ec002..70f1376 100644
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -17,47 +17,10 @@
 #define memprintf(...)
 
 static u8 unmapped_mem[0x1000];
-int pcsx_ram_is_ro;
 
-static void read_mem8()
+u32 read_mem_dummy()
 {
-	memprintf("ari64_read_mem8  %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
-	readmem_word = psxMemRead8(address) & 0xff;
-}
-
-static void read_mem16()
-{
-	memprintf("ari64_read_mem16 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
-	readmem_word = psxMemRead16(address) & 0xffff;
-}
-
-static void read_mem32()
-{
-	memprintf("ari64_read_mem32 %08x @%08x %u\n", address, psxRegs.pc, psxRegs.cycle);
-	readmem_word = psxMemRead32(address);
-}
-
-static void write_mem8()
-{
-	memprintf("ari64_write_mem8  %08x,       %02x @%08x %u\n", address, byte, psxRegs.pc, psxRegs.cycle);
-	psxMemWrite8(address, byte);
-}
-
-static void write_mem16()
-{
-	memprintf("ari64_write_mem16 %08x,     %04x @%08x %u\n", address, hword, psxRegs.pc, psxRegs.cycle);
-	psxMemWrite16(address, hword);
-}
-
-static void write_mem32()
-{
-	memprintf("ari64_write_mem32 %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
-	psxMemWrite32(address, word);
-}
-
-static void read_mem_dummy()
-{
-	readmem_word = 0;
+	return 0;
 }
 
 static void write_mem_dummy(u32 data)
@@ -65,56 +28,6 @@ static void write_mem_dummy(u32 data)
 	memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
 }
 
-extern void ari_read_ram8();
-extern void ari_read_ram16();
-extern void ari_read_ram32();
-extern void ari_read_ram_mirror8();
-extern void ari_read_ram_mirror16();
-extern void ari_read_ram_mirror32();
-extern void ari_write_ram8();
-extern void ari_write_ram16();
-extern void ari_write_ram32();
-extern void ari_write_ram_mirror8();
-extern void ari_write_ram_mirror16();
-extern void ari_write_ram_mirror32();
-extern void ari_write_ram_mirror_ro32();
-extern void ari_read_bios8();
-extern void ari_read_bios16();
-extern void ari_read_bios32();
-extern void ari_read_io8();
-extern void ari_read_io16();
-extern void ari_read_io32();
-extern void ari_write_io8();
-extern void ari_write_io16();
-extern void ari_write_io32();
-
-void (*readmem[0x10000])();
-void (*readmemb[0x10000])();
-void (*readmemh[0x10000])();
-void (*writemem[0x10000])();
-void (*writememb[0x10000])();
-void (*writememh[0x10000])();
-
-static void write_biu_()
-{
-	memprintf("write_biu %08x, %08x @%08x %u\n", address, word, psxRegs.pc, psxRegs.cycle);
-
-	if (address != 0xfffe0130)
-		return;
-
-	switch (word) {
-	case 0x800: case 0x804:
-		pcsx_ram_is_ro = 1;
-		break;
-	case 0: case 0x1e988:
-		pcsx_ram_is_ro = 0;
-		break;
-	default:
-		memprintf("write_biu: unexpected val: %08x\n", word);
-		break;
-	}
-}
-
 /* IO handlers */
 static u32 io_read_sio16()
 {
@@ -224,114 +137,6 @@ static void io_spu_write32(u32 value)
 	wfunc(a + 2, value >> 16);
 }
 
-/* IO tables for 1000-1880 */
-#define IOADR8(a)  ((a) & 0xfff)
-#define IOADR16(a) (((a) & 0xfff) >> 1)
-#define IOADR32(a) (((a) & 0xfff) >> 2)
-
-static const void *io_read8 [0x880] = {
-	[IOADR8(0x1040)] = sioRead8,
-	[IOADR8(0x1800)] = cdrRead0,
-	[IOADR8(0x1801)] = cdrRead1,
-	[IOADR8(0x1802)] = cdrRead2,
-	[IOADR8(0x1803)] = cdrRead3,
-};
-static const void *io_read16[0x880/2] = {
-	[IOADR16(0x1040)] = io_read_sio16,
-	[IOADR16(0x1044)] = sioReadStat16,
-	[IOADR16(0x1048)] = sioReadMode16,
-	[IOADR16(0x104a)] = sioReadCtrl16,
-	[IOADR16(0x104e)] = sioReadBaud16,
-	[IOADR16(0x1100)] = io_rcnt_read_count0,
-	[IOADR16(0x1104)] = io_rcnt_read_mode0,
-	[IOADR16(0x1108)] = io_rcnt_read_target0,
-	[IOADR16(0x1110)] = io_rcnt_read_count1,
-	[IOADR16(0x1114)] = io_rcnt_read_mode1,
-	[IOADR16(0x1118)] = io_rcnt_read_target1,
-	[IOADR16(0x1120)] = io_rcnt_read_count2,
-	[IOADR16(0x1124)] = io_rcnt_read_mode2,
-	[IOADR16(0x1128)] = io_rcnt_read_target2,
-};
-static const void *io_read32[0x880/4] = {
-	[IOADR32(0x1040)] = io_read_sio32,
-	[IOADR32(0x1100)] = io_rcnt_read_count0,
-	[IOADR32(0x1104)] = io_rcnt_read_mode0,
-	[IOADR32(0x1108)] = io_rcnt_read_target0,
-	[IOADR32(0x1110)] = io_rcnt_read_count1,
-	[IOADR32(0x1114)] = io_rcnt_read_mode1,
-	[IOADR32(0x1118)] = io_rcnt_read_target1,
-	[IOADR32(0x1120)] = io_rcnt_read_count2,
-	[IOADR32(0x1124)] = io_rcnt_read_mode2,
-	[IOADR32(0x1128)] = io_rcnt_read_target2,
-//	[IOADR32(0x1810)] = GPU_readData,
-//	[IOADR32(0x1814)] = GPU_readStatus,
-	[IOADR32(0x1820)] = mdecRead0,
-	[IOADR32(0x1824)] = mdecRead1,
-};
-// write(u32 val)
-static const void *io_write8 [0x880] = {
-	[IOADR8(0x1040)] = sioWrite8,
-	[IOADR8(0x1800)] = cdrWrite0,
-	[IOADR8(0x1801)] = cdrWrite1,
-	[IOADR8(0x1802)] = cdrWrite2,
-	[IOADR8(0x1803)] = cdrWrite3,
-};
-static const void *io_write16[0x880/2] = {
-	[IOADR16(0x1040)] = io_write_sio16,
-	[IOADR16(0x1044)] = sioWriteStat16,
-	[IOADR16(0x1048)] = sioWriteMode16,
-	[IOADR16(0x104a)] = sioWriteCtrl16,
-	[IOADR16(0x104e)] = sioWriteBaud16,
-	[IOADR16(0x1070)] = io_write_ireg16,
-	[IOADR16(0x1074)] = io_write_imask16,
-	[IOADR16(0x1100)] = io_rcnt_write_count0,
-	[IOADR16(0x1104)] = io_rcnt_write_mode0,
-	[IOADR16(0x1108)] = io_rcnt_write_target0,
-	[IOADR16(0x1110)] = io_rcnt_write_count1,
-	[IOADR16(0x1114)] = io_rcnt_write_mode1,
-	[IOADR16(0x1118)] = io_rcnt_write_target1,
-	[IOADR16(0x1120)] = io_rcnt_write_count2,
-	[IOADR16(0x1124)] = io_rcnt_write_mode2,
-	[IOADR16(0x1128)] = io_rcnt_write_target2,
-};
-static const void *io_write32[0x880/4] = {
-	[IOADR32(0x1040)] = io_write_sio32,
-	[IOADR32(0x1070)] = io_write_ireg32,
-	[IOADR32(0x1074)] = io_write_imask32,
-	[IOADR32(0x1088)] = io_write_chcr0,
-	[IOADR32(0x1098)] = io_write_chcr1,
-	[IOADR32(0x10a8)] = io_write_chcr2,
-	[IOADR32(0x10b8)] = io_write_chcr3,
-	[IOADR32(0x10c8)] = io_write_chcr4,
-	[IOADR32(0x10e8)] = io_write_chcr6,
-	[IOADR32(0x10f4)] = io_write_dma_icr32,
-	[IOADR32(0x1100)] = io_rcnt_write_count0,
-	[IOADR32(0x1104)] = io_rcnt_write_mode0,
-	[IOADR32(0x1108)] = io_rcnt_write_target0,
-	[IOADR32(0x1110)] = io_rcnt_write_count1,
-	[IOADR32(0x1114)] = io_rcnt_write_mode1,
-	[IOADR32(0x1118)] = io_rcnt_write_target1,
-	[IOADR32(0x1120)] = io_rcnt_write_count2,
-	[IOADR32(0x1124)] = io_rcnt_write_mode2,
-	[IOADR32(0x1128)] = io_rcnt_write_target2,
-//	[IOADR32(0x1810)] = GPU_writeData,
-//	[IOADR32(0x1814)] = GPU_writeStatus,
-	[IOADR32(0x1820)] = mdecWrite0,
-	[IOADR32(0x1824)] = mdecWrite1,
-};
-
-// this has to be in .bss to link into dynarec_local
-struct {
-	void *tab_read8;
-	void *tab_read16;
-	void *tab_read32;
-	void *tab_write8;
-	void *tab_write16;
-	void *tab_write32;
-	void *spu_readf;
-	void *spu_writef;
-} nd_pcsx_io;
-
 static u32 *mem_readtab;
 static u32 *mem_writetab;
 static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
@@ -401,7 +206,7 @@ static void write_biu(u32 value)
 void new_dyna_pcsx_mem_init(void)
 {
 	int i;
-#if 1
+
 	// have to map these further to keep tcache close to .text
 	mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
 		MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
@@ -562,69 +367,6 @@ void new_dyna_pcsx_mem_init(void)
 
 	mem_rtab = mem_readtab;
 	mem_wtab = mem_writetab;
-#endif
-///
-	// default/unmapped handlers
-	for (i = 0; i < 0x10000; i++) {
-		readmemb[i] = read_mem8;
-		readmemh[i] = read_mem16;
-		readmem[i] = read_mem32;
-		writememb[i] = write_mem8;
-		writememh[i] = write_mem16;
-		writemem[i] = write_mem32;
-#if 1
-		readmemb[i] = readmemh[i] = readmem[i] = read_mem_dummy;
-		writememb[i] = writememh[i] = writemem[i] = write_mem_dummy;
-#endif
-	}
-
-#if 1
-	// RAM mirrors
-	for (i = 0; i < 0x80; i++) {
-		readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_ram_mirror8;
-		readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_ram_mirror16;
-		readmem[i]  = readmem [0x8000|i] = readmem [0xa000|i] = ari_read_ram_mirror32;
-		writememb[i] = writememb[0x8000|i] = writememb[0xa000|i] = ari_write_ram_mirror8;
-		writememh[i] = writememh[0x8000|i] = writememh[0xa000|i] = ari_write_ram_mirror16;
-		writemem[i]  = writemem [0x8000|i] = writemem [0xa000|i] = ari_write_ram_mirror32;
-	}
-
-	// stupid BIOS RAM check
-	writemem[0] = ari_write_ram_mirror_ro32;
-	pcsx_ram_is_ro = 0;
-
-	// RAM direct
-	for (i = 0x8000; i < 0x8020; i++) {
-		readmemb[i] = ari_read_ram8;
-		readmemh[i] = ari_read_ram16;
-		readmem[i] = ari_read_ram32;
-	}
-
-	// BIOS and it's mirrors
-	for (i = 0x1fc0; i < 0x1fc8; i++) {
-		readmemb[i] = readmemb[0x8000|i] = readmemb[0xa000|i] = ari_read_bios8;
-		readmemh[i] = readmemh[0x8000|i] = readmemh[0xa000|i] = ari_read_bios16;
-		readmem[i]  = readmem[0x8000|i]  = readmem[0xa000|i]  = ari_read_bios32;
-	}
-
-	// I/O
-	readmemb[0x1f80] = ari_read_io8;
-	readmemh[0x1f80] = ari_read_io16;
-	readmem[0x1f80]  = ari_read_io32;
-	writememb[0x1f80] = ari_write_io8;
-	writememh[0x1f80] = ari_write_io16;
-	writemem[0x1f80]  = ari_write_io32;
-
-	writemem[0xfffe] = write_biu_;
-#endif
-
-	// fill IO tables
-	nd_pcsx_io.tab_read8 = io_read8;
-	nd_pcsx_io.tab_read16 = io_read16;
-	nd_pcsx_io.tab_read32 = io_read32;
-	nd_pcsx_io.tab_write8 = io_write8;
-	nd_pcsx_io.tab_write16 = io_write16;
-	nd_pcsx_io.tab_write32 = io_write32;
 }
 
 void new_dyna_pcsx_mem_reset(void)
@@ -640,13 +382,4 @@ void new_dyna_pcsx_mem_reset(void)
 
 	map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
 	map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
-
-	nd_pcsx_io.spu_readf = SPU_readRegister;
-	nd_pcsx_io.spu_writef = SPU_writeRegister;
-
-	io_read32[IOADR32(0x1810)] = GPU_readData;
-	io_read32[IOADR32(0x1814)] = GPU_readStatus;
-	io_write32[IOADR32(0x1810)] = GPU_writeData;
-	io_write32[IOADR32(0x1814)] = GPU_writeStatus;
 }
-