psx_gpu: partial interlace mode support

2 files changed, 74 insertions, 1 deletions

diff --git a/plugins/gpu_neon/psx_gpu/psx_gpu.c b/plugins/gpu_neon/psx_gpu/psx_gpu.c
index 7c1503b..9e84ace 100644
--- a/plugins/gpu_neon/psx_gpu/psx_gpu.c
+++ b/plugins/gpu_neon/psx_gpu/psx_gpu.c
@@ -401,6 +401,48 @@ void setup_blocks_shaded_untextured_undithered_unswizzled_indirect(
 
 void flush_render_block_buffer(psx_gpu_struct *psx_gpu)
 {
+  if((psx_gpu->interlace_mode & RENDER_INTERLACE_ENABLED) &&
+   (psx_gpu->primitive_type == PRIMITIVE_TYPE_SPRITE))
+  {
+    u32 num_blocks_dest = 0;
+    block_struct *block_src = psx_gpu->blocks; 
+    block_struct *block_dest = psx_gpu->blocks;
+
+    u16 *vram_ptr = psx_gpu->vram_ptr;
+    u32 i;
+
+    if(psx_gpu->interlace_mode & RENDER_INTERLACE_ODD)
+    {
+      for(i = 0; i < psx_gpu->num_blocks; i++)
+      {
+        u32 fb_offset = (u32)((u8 *)block_src->fb_ptr - (u8 *)vram_ptr);
+        if(fb_offset & (1 << 11))
+        {
+          *block_dest = *block_src;
+          num_blocks_dest++;
+          block_dest++;
+        }
+        block_src++;
+      }
+    }
+    else
+    {
+      for(i = 0; i < psx_gpu->num_blocks; i++)
+      {
+        u32 fb_offset = (u32)((u8 *)block_src->fb_ptr - (u8 *)vram_ptr);
+        if((fb_offset & (1 << 11)) == 0)
+        {
+          *block_dest = *block_src;
+          num_blocks_dest++;
+          block_dest++;
+        }
+        block_src++;
+      }
+    }
+
+    psx_gpu->num_blocks = num_blocks_dest;
+  }
+
   if(psx_gpu->num_blocks)
   {
     render_block_handler_struct *render_block_handler =
@@ -2987,6 +3029,28 @@ void render_triangle(psx_gpu_struct *psx_gpu, vertex_struct *vertexes,
   spans += psx_gpu->num_spans;
 #endif
 
+  if(psx_gpu->interlace_mode & RENDER_INTERLACE_ENABLED)
+  {
+    u32 i;
+
+    if(psx_gpu->interlace_mode & RENDER_INTERLACE_ODD)
+    {
+      for(i = 0; i < psx_gpu->num_spans; i++)
+      {
+        if((psx_gpu->span_edge_data[i].y & 1) == 0)
+          psx_gpu->span_edge_data[i].num_blocks = 0;
+      }
+    }
+    else
+    {
+      for(i = 0; i < psx_gpu->num_spans; i++)
+      {
+        if(psx_gpu->span_edge_data[i].y & 1)
+          psx_gpu->span_edge_data[i].num_blocks = 0;
+      }
+    }
+  }
+
   u32 render_state = flags &
    (RENDER_FLAGS_MODULATE_TEXELS | RENDER_FLAGS_BLEND | 
    RENDER_FLAGS_TEXTURE_MAP | RENDER_FLAGS_SHADE);
@@ -4457,6 +4521,8 @@ void initialize_psx_gpu(psx_gpu_struct *psx_gpu, u16 *vram)
   psx_gpu->texture_mask_width = 0xFF;
   psx_gpu->texture_mask_height = 0xFF;
 
+  psx_gpu->interlace_mode = 0;
+
   memset(psx_gpu->vram_ptr, 0, sizeof(u16) * 1024 * 512);
 
   initialize_reciprocal_table();
diff --git a/plugins/gpu_neon/psx_gpu/psx_gpu.h b/plugins/gpu_neon/psx_gpu/psx_gpu.h
index 137dda9..4605c39 100644
--- a/plugins/gpu_neon/psx_gpu/psx_gpu.h
+++ b/plugins/gpu_neon/psx_gpu/psx_gpu.h
@@ -53,6 +53,12 @@ typedef enum
   RENDER_STATE_MASK_EVALUATE   = 0x20,
 } render_state_enum;
 
+typedef enum
+{
+  RENDER_INTERLACE_ENABLED     = 0x1,
+  RENDER_INTERLACE_ODD         = 0x2
+} render_interlace_enum;
+
 typedef struct
 {
   u16 left_x;
@@ -172,10 +178,11 @@ typedef struct
   u8 texture_window_y;
 
   u8 primitive_type;
+  u8 interlace_mode;
 
   // Align up to 64 byte boundary to keep the upcoming buffers cache line
   // aligned
-  u8 reserved_a[1];
+  //u8 reserved_a[0];
 
   // 8KB
   block_struct blocks[MAX_BLOCKS_PER_ROW];