core: update to newer interrupt code, seems to affect timings too

pcsxr-svn commit:
Author: weimingzhi
Date:   Sat Aug 7 23:52:44 2010 +0000

    refactored the interrupt scheduling code a bit to make it a little
    more readable than using those "magic" numbers.

12 files changed, 112 insertions, 84 deletions

diff --git a/ChangeLog b/ChangeLog
index 0c16957..4a92d70 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,17 @@
+August 7, 2010 Wei Mingzhi <whistler_wmz@users.sf.net>

+

+ * libpcsxcore/r3000a.h: Refactored the interrupt scheduling code to make it a

+   little more readable than using the "magic" numbers.

+ * libpcsxcore/r3000a.c: Likewise.

+ * libpcsxcore/cdrom.c: Likewise.

+ * libpcsxcore/mdec.c: Likewise.

+ * libpcsxcore/sio.c: Likewise.

+ * libpcsxcore/psxdma.h: Likewise.

+ * libpcsxcore/misc.c: Bumped savestate version.

+ * debian/changelog: Updated version.

+ * macosx/Info.plist: Likewise.

+ * po/zh_TW.po: Corrected a minor translation error.

+

 August 2, 2010 Wei Mingzhi <whistler_wmz@users.sf.net>

 

  * macosx/Pcsx.xcodeproj/project.pbxproj: Added some more optimizations

diff --git a/libpcsxcore/cdrom.c b/libpcsxcore/cdrom.c
index d7f4d80..ae59a63 100644
--- a/libpcsxcore/cdrom.c
+++ b/libpcsxcore/cdrom.c
@@ -92,17 +92,17 @@ static struct CdrStat stat;
 static struct SubQ *subq;
 
 #define CDR_INT(eCycle) { \
-	psxRegs.interrupt |= 0x4; \
-	psxRegs.intCycle[2 + 1] = eCycle; \
-	psxRegs.intCycle[2] = psxRegs.cycle; \
-	new_dyna_set_event(0, eCycle); \
+	psxRegs.interrupt |= (1 << PSXINT_CDR); \
+	psxRegs.intCycle[PSXINT_CDR].cycle = eCycle; \
+	psxRegs.intCycle[PSXINT_CDR].sCycle = psxRegs.cycle; \
+	new_dyna_set_event(PSXINT_CDR, eCycle); \
 }
 
 #define CDREAD_INT(eCycle) { \
-	psxRegs.interrupt |= 0x40000; \
-	psxRegs.intCycle[2 + 16 + 1] = eCycle; \
-	psxRegs.intCycle[2 + 16] = psxRegs.cycle; \
-	new_dyna_set_event(2, eCycle); \
+	psxRegs.interrupt |= (1 << PSXINT_CDREAD); \
+	psxRegs.intCycle[PSXINT_CDREAD].cycle = eCycle; \
+	psxRegs.intCycle[PSXINT_CDREAD].sCycle = psxRegs.cycle; \
+	new_dyna_set_event(PSXINT_CDREAD, eCycle); \
 }
 
 #define StartReading(type, eCycle) { \
@@ -115,7 +115,7 @@ static struct SubQ *subq;
 #define StopReading() { \
 	if (cdr.Reading) { \
 		cdr.Reading = 0; \
-		psxRegs.interrupt &= ~0x40000; \
+		psxRegs.interrupt &= ~(1 << PSXINT_CDREAD); \
 	} \
 	cdr.StatP &= ~0x20;\
 }
diff --git a/libpcsxcore/mdec.c b/libpcsxcore/mdec.c
index 5e84152..f9b8d58 100644
--- a/libpcsxcore/mdec.c
+++ b/libpcsxcore/mdec.c
@@ -543,12 +543,11 @@ void mdec1Interrupt() {
 	if (HW_DMA1_CHCR & SWAP32(0x01000000)) {
 		// Set a fixed value totaly arbitrarie another sound value is
 		// PSXCLK / 60 or PSXCLK / 50 since the bug happened at end of frame.
-		// PSXCLK / 1000 seems good for FF9. (for FF9 need < ~28000)
+		// PSXCLK / 500 seems good for FF9.
 		// CAUTION: commented interrupt-handling may lead to problems, keep an eye ;-)
-		MDECOUTDMA_INT(PSXCLK / 1000 * BIAS);
-//		psxRegs.interrupt |= 0x02000000;
-//		psxRegs.intCycle[5 + 24 + 1] *= 8;
-//		psxRegs.intCycle[5 + 24] = psxRegs.cycle;
+		MDECOUTDMA_INT(PSXCLK / 500);
+//		MDECOUTDMA_INT(psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle * 8);
+
 		HW_DMA1_CHCR &= SWAP32(~0x01000000);
 		DMA_INTERRUPT(1);
 	} else {
diff --git a/libpcsxcore/misc.c b/libpcsxcore/misc.c
index 38a516c..3236945 100644
--- a/libpcsxcore/misc.c
+++ b/libpcsxcore/misc.c
@@ -458,7 +458,7 @@ static const char PcsxHeader[32] = "STv4 PCSX v" PACKAGE_VERSION;
 
 // Savestate Versioning!
 // If you make changes to the savestate version, please increment the value below.
-static const u32 SaveVersion = 0x8b410004;
+static const u32 SaveVersion = 0x8b410005;
 
 int SaveState(const char *file) {
 	gzFile f;
diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
index 7f7d8f8..428f58b 100644
--- a/libpcsxcore/new_dynarec/emu_if.c
+++ b/libpcsxcore/new_dynarec/emu_if.c
@@ -12,6 +12,7 @@
 #include "emu_if.h"
 #include "pcsxmem.h"
 #include "../psxhle.h"
+#include "../r3000a.h"
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
 
@@ -19,7 +20,7 @@
 #define evprintf(...)
 
 char invalid_code[0x100000];
-u32 event_cycles[7];
+u32 event_cycles[PSXINT_COUNT];
 
 static void schedule_timeslice(void)
 {
diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index a526ac5..dc3ce69 100644
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -134,7 +134,7 @@ static void io_write_imask16(u32 value)
 {
 	psxHu16ref(0x1074) = value;
 	if (psxHu16ref(0x1070) & value)
-		new_dyna_set_event(6, 1);
+		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 }
 
 static void io_write_ireg32(u32 value)
@@ -148,7 +148,7 @@ static void io_write_imask32(u32 value)
 {
 	psxHu32ref(0x1074) = value;
 	if (psxHu32ref(0x1070) & value)
-		new_dyna_set_event(6, 1);
+		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 }
 
 static void io_write_dma_icr32(u32 value)
diff --git a/libpcsxcore/psxdma.h b/libpcsxcore/psxdma.h
index 6736cdb..b73781f 100644
--- a/libpcsxcore/psxdma.h
+++ b/libpcsxcore/psxdma.h
@@ -30,24 +30,24 @@ extern "C" {
 #include "psxmem.h"
 
 #define GPUDMA_INT(eCycle) { \
-	psxRegs.interrupt |= 0x01000000; \
-	psxRegs.intCycle[3 + 24 + 1] = eCycle; \
-	psxRegs.intCycle[3 + 24] = psxRegs.cycle; \
-	new_dyna_set_event(3, eCycle); \
+	psxRegs.interrupt |= (1 << PSXINT_GPUDMA); \
+	psxRegs.intCycle[PSXINT_GPUDMA].cycle = eCycle; \
+	psxRegs.intCycle[PSXINT_GPUDMA].sCycle = psxRegs.cycle; \
+	new_dyna_set_event(PSXINT_GPUDMA, eCycle); \
 }
 
 #define SPUDMA_INT(eCycle) { \
-    psxRegs.interrupt |= 0x04000000; \
-    psxRegs.intCycle[1 + 24 + 1] = eCycle; \
-    psxRegs.intCycle[1 + 24] = psxRegs.cycle; \
-    new_dyna_set_event(5, eCycle); \
+	psxRegs.interrupt |= (1 << PSXINT_SPUDMA); \
+	psxRegs.intCycle[PSXINT_SPUDMA].cycle = eCycle; \
+	psxRegs.intCycle[PSXINT_SPUDMA].sCycle = psxRegs.cycle; \
+	new_dyna_set_event(PSXINT_SPUDMA, eCycle); \
 }
 
 #define MDECOUTDMA_INT(eCycle) { \
-	psxRegs.interrupt |= 0x02000000; \
-	psxRegs.intCycle[5 + 24 + 1] = eCycle; \
-	psxRegs.intCycle[5 + 24] = psxRegs.cycle; \
-	new_dyna_set_event(4, eCycle); \
+	psxRegs.interrupt |= (1 << PSXINT_MDECOUTDMA); \
+	psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle = eCycle; \
+	psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle = psxRegs.cycle; \
+	new_dyna_set_event(PSXINT_MDECOUTDMA, eCycle); \
 }
 
 void psxDma2(u32 madr, u32 bcr, u32 chcr);
diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c
index f265e19..0c5320a 100644
--- a/libpcsxcore/psxhw.c
+++ b/libpcsxcore/psxhw.c
@@ -432,7 +432,7 @@ void psxHwWrite16(u32 add, u16 value) {
 #endif
 			psxHu16ref(0x1074) = SWAPu16(value);
 			if (psxHu16ref(0x1070) & value)
-				new_dyna_set_event(6, 1);
+				new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 			return;
 
 		case 0x1f801100:
@@ -546,7 +546,7 @@ void psxHwWrite32(u32 add, u32 value) {
 #endif
 			psxHu32ref(0x1074) = SWAPu32(value);
 			if (psxHu32ref(0x1070) & value)
-				new_dyna_set_event(6, 1);
+				new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
 			return;
 
 #ifdef PSXHW_LOG
diff --git a/libpcsxcore/psxmem.h b/libpcsxcore/psxmem.h
index a5c6c4a..d9fee00 100644
--- a/libpcsxcore/psxmem.h
+++ b/libpcsxcore/psxmem.h
@@ -138,20 +138,6 @@ void psxMemWrite16(u32 mem, u16 value);
 void psxMemWrite32(u32 mem, u32 value);
 void *psxMemPointer(u32 mem);
 
-extern u32 event_cycles[7];
-extern u32 next_interupt;
-
-#define new_dyna_set_event(e, c) { \
-	s32 c_ = c; \
-	u32 abs_ = psxRegs.cycle + c_; \
-	s32 odi_ = next_interupt - psxRegs.cycle; \
-	event_cycles[e] = abs_; \
-	if (c_ < odi_) { \
-		/*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
-		next_interupt = abs_; \
-	} \
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
index 8c6289e..27c247b 100644
--- a/libpcsxcore/r3000a.c
+++ b/libpcsxcore/r3000a.c
@@ -115,39 +115,39 @@ void psxBranchTest() {
 		psxRcntUpdate();
 
 	if (psxRegs.interrupt) {
-		if ((psxRegs.interrupt & 0x80) && !Config.Sio) { // sio
-			if ((psxRegs.cycle - psxRegs.intCycle[7]) >= psxRegs.intCycle[7 + 1]) {
-				psxRegs.interrupt &= ~0x80;
+		if ((psxRegs.interrupt & (1 << PSXINT_SIO)) && !Config.Sio) { // sio
+			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
+				psxRegs.interrupt &= ~(1 << PSXINT_SIO);
 				sioInterrupt();
 			}
 		}
-		if (psxRegs.interrupt & 0x04) { // cdr
-			if ((psxRegs.cycle - psxRegs.intCycle[2]) >= psxRegs.intCycle[2 + 1]) {
-				psxRegs.interrupt &= ~0x04;
+		if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
+			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
+				psxRegs.interrupt &= ~(1 << PSXINT_CDR);
 				cdrInterrupt();
 			}
 		}
-		if (psxRegs.interrupt & 0x040000) { // cdr read
-			if ((psxRegs.cycle - psxRegs.intCycle[2 + 16]) >= psxRegs.intCycle[2 + 16 + 1]) {
-				psxRegs.interrupt &= ~0x040000;
+		if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
+			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
+				psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
 				cdrReadInterrupt();
 			}
 		}
-		if (psxRegs.interrupt & 0x01000000) { // gpu dma
-			if ((psxRegs.cycle - psxRegs.intCycle[3 + 24]) >= psxRegs.intCycle[3 + 24 + 1]) {
-				psxRegs.interrupt &= ~0x01000000;
+		if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
+			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
+				psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
 				gpuInterrupt();
 			}
 		}
-		if (psxRegs.interrupt & 0x02000000) { // mdec out dma
-			if ((psxRegs.cycle - psxRegs.intCycle[5 + 24]) >= psxRegs.intCycle[5 + 24 + 1]) {
-				psxRegs.interrupt &= ~0x02000000;
+		if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
+			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
+				psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
 				mdec1Interrupt();
 			}
 		}
-		if (psxRegs.interrupt & 0x04000000) { // spu dma
-			if ((psxRegs.cycle - psxRegs.intCycle[1 + 24]) >= psxRegs.intCycle[1 + 24 + 1]) {
-				psxRegs.interrupt &= ~0x04000000;
+		if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
+			if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
+				psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
 				spuInterrupt();
 			}
 		}
diff --git a/libpcsxcore/r3000a.h b/libpcsxcore/r3000a.h
index 9379f45..a2fcca3 100644
--- a/libpcsxcore/r3000a.h
+++ b/libpcsxcore/r3000a.h
@@ -145,6 +145,17 @@ typedef union {
 	PAIR p[32];
 } psxCP2Ctrl;
 
+enum {
+	PSXINT_SIO = 0,
+	PSXINT_CDR,
+	PSXINT_CDREAD,
+	PSXINT_GPUDMA,
+	PSXINT_MDECOUTDMA,
+	PSXINT_SPUDMA,
+	PSXINT_NEWDRC_CHECK,
+	PSXINT_COUNT
+};
+
 typedef struct {
 	psxGPRRegs GPR;		/* General Purpose Registers */
 	psxCP0Regs CP0;		/* Coprocessor0 Registers */
@@ -154,11 +165,26 @@ typedef struct {
     u32 code;			/* The instruction */
 	u32 cycle;
 	u32 interrupt;
-	u32 intCycle[32];
+	struct { u32 sCycle, cycle; } intCycle[32];
 } psxRegisters;
 
 extern psxRegisters psxRegs;
 
+/* new_dynarec stuff */
+extern u32 event_cycles[PSXINT_COUNT];
+extern u32 next_interupt;
+
+#define new_dyna_set_event(e, c) { \
+	s32 c_ = c; \
+	u32 abs_ = psxRegs.cycle + c_; \
+	s32 odi_ = next_interupt - psxRegs.cycle; \
+	event_cycles[e] = abs_; \
+	if (c_ < odi_) { \
+		/*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
+		next_interupt = abs_; \
+	} \
+}
+
 #if defined(__BIGENDIAN__)
 
 #define _i32(x) *(s32 *)&x
diff --git a/libpcsxcore/sio.c b/libpcsxcore/sio.c
index b63f56b..8a30797 100644
--- a/libpcsxcore/sio.c
+++ b/libpcsxcore/sio.c
@@ -65,24 +65,26 @@ static unsigned int padst;
 
 char Mcd1Data[MCD_SIZE], Mcd2Data[MCD_SIZE];
 
+#define SIO_INT(eCycle) { \
+	if (!Config.Sio) { \
+		psxRegs.interrupt |= (1 << PSXINT_SIO); \
+		psxRegs.intCycle[PSXINT_SIO].cycle = eCycle; \
+		psxRegs.intCycle[PSXINT_SIO].sCycle = psxRegs.cycle; \
+		new_dyna_set_event(PSXINT_SIO, eCycle); \
+	} \
+}
+
 // clk cycle byte
 // 4us * 8bits = (PSXCLK / 1000000) * 32; (linuzappz)
 // TODO: add SioModePrescaler and BaudReg
-static inline void SIO_INT() {
-	if (!Config.Sio) {
-		psxRegs.interrupt |= 0x80;
-		psxRegs.intCycle[7 + 1] = 400;
-		psxRegs.intCycle[7] = psxRegs.cycle;
-		new_dyna_set_event(1, 400);
-	}
-}
+#define SIO_CYCLES		535
 
 void sioWrite8(unsigned char value) {
 #ifdef PAD_LOG
 	PAD_LOG("sio write8 %x\n", value);
 #endif
 	switch (padst) {
-		case 1: SIO_INT();
+		case 1: SIO_INT(SIO_CYCLES);
 			if ((value & 0x40) == 0x40) {
 				padst = 2; parp = 1;
 				if (!Config.UseNet) {
@@ -120,7 +122,7 @@ void sioWrite8(unsigned char value) {
 			parp++;
 /*			if (buf[1] == 0x45) {
 				buf[parp] = 0;
-				SIO_INT();
+				SIO_INT(SIO_CYCLES);
 				return;
 			}*/
 			if (!Config.UseNet) {
@@ -131,13 +133,13 @@ void sioWrite8(unsigned char value) {
 			}
 
 			if (parp == bufcount) { padst = 0; return; }
-			SIO_INT();
+			SIO_INT(SIO_CYCLES);
 			return;
 	}
 
 	switch (mcdst) {
 		case 1:
-			SIO_INT();
+			SIO_INT(SIO_CYCLES);
 			if (rdwr) { parp++; return; }
 			parp = 1;
 			switch (value) {
@@ -147,7 +149,7 @@ void sioWrite8(unsigned char value) {
 			}
 			return;
 		case 2: // address H
-			SIO_INT();
+			SIO_INT(SIO_CYCLES);
 			adrH = value;
 			*buf = 0;
 			parp = 0;
@@ -155,7 +157,7 @@ void sioWrite8(unsigned char value) {
 			mcdst = 3;
 			return;
 		case 3: // address L
-			SIO_INT();
+			SIO_INT(SIO_CYCLES);
 			adrL = value;
 			*buf = adrH;
 			parp = 0;
@@ -163,7 +165,7 @@ void sioWrite8(unsigned char value) {
 			mcdst = 4;
 			return;
 		case 4:
-			SIO_INT();
+			SIO_INT(SIO_CYCLES);
 			parp = 0;
 			switch (rdwr) {
 				case 1: // read
@@ -205,7 +207,7 @@ void sioWrite8(unsigned char value) {
 			if (rdwr == 2) {
 				if (parp < 128) buf[parp + 1] = value;
 			}
-			SIO_INT();
+			SIO_INT(SIO_CYCLES);
 			return;
 	}
 
@@ -253,7 +255,7 @@ void sioWrite8(unsigned char value) {
 			bufcount = 2;
 			parp = 0;
 			padst = 1;
-			SIO_INT();
+			SIO_INT(SIO_CYCLES);
 			return;
 		case 0x81: // start memcard
 			StatReg |= RX_RDY;
@@ -262,7 +264,7 @@ void sioWrite8(unsigned char value) {
 			bufcount = 3;
 			mcdst = 1;
 			rdwr = 0;
-			SIO_INT();
+			SIO_INT(SIO_CYCLES);
 			return;
 	}
 }
@@ -280,7 +282,7 @@ void sioWriteCtrl16(unsigned short value) {
 	if ((CtrlReg & SIO_RESET) || (!CtrlReg)) {
 		padst = 0; mcdst = 0; parp = 0;
 		StatReg = TX_RDY | TX_EMPTY;
-		psxRegs.interrupt &= ~0x80;
+		psxRegs.interrupt &= ~(1 << PSXINT_SIO);
 	}
 }