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authormeepingsnesroms2017-09-01 11:21:48 -0700
committerGitHub2017-09-01 11:21:48 -0700
commit6c5b8733e0b286d5a4b4d9b7899e4c17a92cd04a (patch)
tree924720c49ac10c9ab3c98e3d3e06c8f4a06bc33c /libpcsxcore/new_dynarec/arm/linkage_arm.S
parent646a63e41c53e5c1c971a4e305d4627dcee43c5e (diff)
parent874706c9a527d43f1a737b772225c120da86c31e (diff)
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Merge pull request #2 from libretro/master
Update from master
Diffstat (limited to 'libpcsxcore/new_dynarec/arm/linkage_arm.S')
-rw-r--r--libpcsxcore/new_dynarec/arm/linkage_arm.S12
1 files changed, 6 insertions, 6 deletions
diff --git a/libpcsxcore/new_dynarec/arm/linkage_arm.S b/libpcsxcore/new_dynarec/arm/linkage_arm.S
index b630142..269eb99 100644
--- a/libpcsxcore/new_dynarec/arm/linkage_arm.S
+++ b/libpcsxcore/new_dynarec/arm/linkage_arm.S
@@ -93,7 +93,7 @@ DRC_VAR(restore_candidate, 512)
DRC_VAR(FCR0, 4)
DRC_VAR(FCR31, 4)
-#ifdef __MACH__
+#ifdef TEXRELS_FORBIDDEN
.data
.align 2
ptr_jump_in:
@@ -117,21 +117,21 @@ ptr_hash_table:
#endif
.macro load_varadr reg var
-#if defined(HAVE_ARMV7) && !defined(__PIC__)
- movw \reg, #:lower16:\var
- movt \reg, #:upper16:\var
-#elif defined(HAVE_ARMV7) && defined(__MACH__)
+#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
movw \reg, #:lower16:(\var-(1678f+8))
movt \reg, #:upper16:(\var-(1678f+8))
1678:
add \reg, pc
+#elif defined(HAVE_ARMV7) && !defined(__PIC__)
+ movw \reg, #:lower16:\var
+ movt \reg, #:upper16:\var
#else
ldr \reg, =\var
#endif
.endm
.macro load_varadr_ext reg var
-#if defined(HAVE_ARMV7) && defined(__MACH__) && defined(__PIC__)
+#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
movw \reg, #:lower16:(ptr_\var-(1678f+8))
movt \reg, #:upper16:(ptr_\var-(1678f+8))
1678: