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| author | twinaphex | 2017-05-03 03:55:32 +0200 |
|---|---|---|
| committer | twinaphex | 2017-05-03 03:55:32 +0200 |
| commit | f0a02fdcf0043d9afa9c4b26c38c28cb761e1e10 (patch) | |
| tree | c4200a0cd30014da03c08455a6f619fedde4bc31 /libpcsxcore/new_dynarec/arm | |
| parent | ee091481d4aa4a525f84f9c499641c9ba49b8164 (diff) | |
| parent | 0e4ad31902f206e2c6945632bb1f558eae941ff1 (diff) | |
| download | pcsx_rearmed-f0a02fdcf0043d9afa9c4b26c38c28cb761e1e10.tar.gz pcsx_rearmed-f0a02fdcf0043d9afa9c4b26c38c28cb761e1e10.tar.bz2 pcsx_rearmed-f0a02fdcf0043d9afa9c4b26c38c28cb761e1e10.zip | |
Merge https://github.com/notaz/pcsx_rearmed
Diffstat (limited to 'libpcsxcore/new_dynarec/arm')
| -rw-r--r-- | libpcsxcore/new_dynarec/arm/linkage_arm.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/libpcsxcore/new_dynarec/arm/linkage_arm.S b/libpcsxcore/new_dynarec/arm/linkage_arm.S index b630142..269eb99 100644 --- a/libpcsxcore/new_dynarec/arm/linkage_arm.S +++ b/libpcsxcore/new_dynarec/arm/linkage_arm.S @@ -93,7 +93,7 @@ DRC_VAR(restore_candidate, 512) DRC_VAR(FCR0, 4) DRC_VAR(FCR31, 4) -#ifdef __MACH__ +#ifdef TEXRELS_FORBIDDEN .data .align 2 ptr_jump_in: @@ -117,21 +117,21 @@ ptr_hash_table: #endif .macro load_varadr reg var -#if defined(HAVE_ARMV7) && !defined(__PIC__) - movw \reg, #:lower16:\var - movt \reg, #:upper16:\var -#elif defined(HAVE_ARMV7) && defined(__MACH__) +#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) movw \reg, #:lower16:(\var-(1678f+8)) movt \reg, #:upper16:(\var-(1678f+8)) 1678: add \reg, pc +#elif defined(HAVE_ARMV7) && !defined(__PIC__) + movw \reg, #:lower16:\var + movt \reg, #:upper16:\var #else ldr \reg, =\var #endif .endm .macro load_varadr_ext reg var -#if defined(HAVE_ARMV7) && defined(__MACH__) && defined(__PIC__) +#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN) movw \reg, #:lower16:(ptr_\var-(1678f+8)) movt \reg, #:upper16:(ptr_\var-(1678f+8)) 1678: |