diff options
| author | notaz | 2012-04-15 19:49:49 +0300 |
|---|---|---|
| committer | notaz | 2012-04-18 03:24:40 +0300 |
| commit | a327ad27099341fb6eed61aa0419dff418429f96 (patch) | |
| tree | 43461c310c044269b3c52f9d94e0e814b0fe4a37 /libpcsxcore/new_dynarec/assem_arm.h | |
| parent | 3a321131b0f1d75685b7487517fc84738f4186d2 (diff) | |
| download | pcsx_rearmed-a327ad27099341fb6eed61aa0419dff418429f96.tar.gz pcsx_rearmed-a327ad27099341fb6eed61aa0419dff418429f96.tar.bz2 pcsx_rearmed-a327ad27099341fb6eed61aa0419dff418429f96.zip | |
support emulated RAM mapped at offset
Thanks to CatalystG for some initial code and testing.
Diffstat (limited to 'libpcsxcore/new_dynarec/assem_arm.h')
| -rw-r--r-- | libpcsxcore/new_dynarec/assem_arm.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h index 7ed8caf..0148a95 100644 --- a/libpcsxcore/new_dynarec/assem_arm.h +++ b/libpcsxcore/new_dynarec/assem_arm.h @@ -22,8 +22,12 @@ //#undef USE_MINI_HT #endif +#ifndef BASE_ADDR_FIXED #ifndef __ANDROID__ #define BASE_ADDR_FIXED 1 +#else +#define BASE_ADDR_FIXED 0 +#endif #endif #ifdef FORCE32 @@ -61,13 +65,10 @@ extern char *invc_ptr; #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes // Code generator target address -#ifdef BASE_ADDR_FIXED +#if BASE_ADDR_FIXED // "round" address helpful for debug #define BASE_ADDR 0x1000000 #else extern char translation_cache[1 << TARGET_SIZE_2]; #define BASE_ADDR translation_cache #endif - -// This is defined in linkage_arm.s, but gcc -O3 likes this better -#define rdram ((unsigned int *)0x80000000) |