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| author | notaz | 2011-10-19 01:54:19 +0300 |
|---|---|---|
| committer | notaz | 2011-10-30 23:48:07 +0200 |
| commit | 054175e91a93116649ea1802790cb842516a85dc (patch) | |
| tree | 8d2d300c99d53b2cda81556c91d641ee46559380 /libpcsxcore/new_dynarec/emu_if.h | |
| parent | 2167bef61daaeb12ceb59c3c577fc636e9011d6d (diff) | |
| download | pcsx_rearmed-054175e91a93116649ea1802790cb842516a85dc.tar.gz pcsx_rearmed-054175e91a93116649ea1802790cb842516a85dc.tar.bz2 pcsx_rearmed-054175e91a93116649ea1802790cb842516a85dc.zip | |
drc: do MVMVA decoding; parametrize handlers
Diffstat (limited to 'libpcsxcore/new_dynarec/emu_if.h')
| -rw-r--r-- | libpcsxcore/new_dynarec/emu_if.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/libpcsxcore/new_dynarec/emu_if.h b/libpcsxcore/new_dynarec/emu_if.h index 90e32e7..6b6305c 100644 --- a/libpcsxcore/new_dynarec/emu_if.h +++ b/libpcsxcore/new_dynarec/emu_if.h @@ -24,6 +24,31 @@ extern int reg_cop0[]; #define Count psxRegs.cycle // psxRegs.CP0.n.Count /* COP2/GTE */ +enum gte_opcodes { + GTE_RTPS = 0x01, + GTE_NCLIP = 0x06, + GTE_OP = 0x0c, + GTE_DPCS = 0x10, + GTE_INTPL = 0x11, + GTE_MVMVA = 0x12, + GTE_NCDS = 0x13, + GTE_CDP = 0x14, + GTE_NCDT = 0x16, + GTE_NCCS = 0x1b, + GTE_CC = 0x1c, + GTE_NCS = 0x1e, + GTE_NCT = 0x20, + GTE_SQR = 0x28, + GTE_DCPL = 0x29, + GTE_DPCT = 0x2a, + GTE_AVSZ3 = 0x2d, + GTE_AVSZ4 = 0x2e, + GTE_RTPT = 0x30, + GTE_GPF = 0x3d, + GTE_GPL = 0x3e, + GTE_NCCT = 0x3f, +}; + extern int reg_cop2d[], reg_cop2c[]; extern void *gte_handlers[64]; extern void *gte_handlers_nf[64]; @@ -57,6 +82,7 @@ void rcnt2_read_count_m1(u32 addr, u32, u32 cycles); extern unsigned int address; extern void *psxH_ptr; +extern void *zeromem_ptr; // same as invalid_code, just a region for ram write checks (inclusive) extern u32 inv_code_start, inv_code_end; |