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| author | Twinaphex | 2016-04-22 17:06:53 +0200 |
|---|---|---|
| committer | Twinaphex | 2016-04-22 17:06:53 +0200 |
| commit | 18ef7635b0b265350eb8304a26edeb8d4b0b2e19 (patch) | |
| tree | 93e9704ebb9395c4f6c7bab847d9df7abb005d3d /libpcsxcore/new_dynarec/linkage_arm.S | |
| parent | 4ed8f00a1221b15925117f1c7413b4640e6e7198 (diff) | |
| parent | 163249087400935f084080127990bc762e83319c (diff) | |
| download | pcsx_rearmed-18ef7635b0b265350eb8304a26edeb8d4b0b2e19.tar.gz pcsx_rearmed-18ef7635b0b265350eb8304a26edeb8d4b0b2e19.tar.bz2 pcsx_rearmed-18ef7635b0b265350eb8304a26edeb8d4b0b2e19.zip | |
Merge pull request #33 from dankcushions/master
Merging in latest upstream changes
Diffstat (limited to 'libpcsxcore/new_dynarec/linkage_arm.S')
| -rw-r--r-- | libpcsxcore/new_dynarec/linkage_arm.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/libpcsxcore/new_dynarec/linkage_arm.S b/libpcsxcore/new_dynarec/linkage_arm.S index 50b577b..95af8b4 100644 --- a/libpcsxcore/new_dynarec/linkage_arm.S +++ b/libpcsxcore/new_dynarec/linkage_arm.S @@ -116,10 +116,10 @@ ptr_hash_table: #endif .macro load_varadr reg var -#if defined(__ARM_ARCH_7A__) && !defined(__PIC__) +#if defined(HAVE_ARMV7) && !defined(__PIC__) movw \reg, #:lower16:\var movt \reg, #:upper16:\var -#elif defined(__ARM_ARCH_7A__) && defined(__MACH__) +#elif defined(HAVE_ARMV7) && defined(__MACH__) movw \reg, #:lower16:(\var-(1678f+8)) movt \reg, #:upper16:(\var-(1678f+8)) 1678: @@ -130,7 +130,7 @@ ptr_hash_table: .endm .macro load_varadr_ext reg var -#if defined(__ARM_ARCH_7A__) && defined(__MACH__) && defined(__PIC__) +#if defined(HAVE_ARMV7) && defined(__MACH__) && defined(__PIC__) movw \reg, #:lower16:(ptr_\var-(1678f+8)) movt \reg, #:upper16:(ptr_\var-(1678f+8)) 1678: @@ -141,7 +141,7 @@ ptr_hash_table: .endm .macro mov_16 reg imm -#ifdef __ARM_ARCH_7A__ +#ifdef HAVE_ARMV7 movw \reg, #\imm #else mov \reg, #(\imm & 0x00ff) @@ -150,7 +150,7 @@ ptr_hash_table: .endm .macro mov_24 reg imm -#ifdef __ARM_ARCH_7A__ +#ifdef HAVE_ARMV7 movw \reg, #(\imm & 0xffff) movt \reg, #(\imm >> 16) #else |