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| author | twinaphex | 2013-03-18 01:16:31 +0100 |
|---|---|---|
| committer | twinaphex | 2013-03-18 01:16:31 +0100 |
| commit | 22dade5ca95efa7fb3530023dbab77f8516bfed7 (patch) | |
| tree | 40a660c1e7a806abe03b2c9f2e6389073894877b /libpcsxcore/new_dynarec | |
| parent | 24f4865eff11beb6348d9e0e310d593477359afe (diff) | |
| parent | 101e053c72e9299bfbd1cbf6a8de9ba6cff11e4c (diff) | |
| download | pcsx_rearmed-22dade5ca95efa7fb3530023dbab77f8516bfed7.tar.gz pcsx_rearmed-22dade5ca95efa7fb3530023dbab77f8516bfed7.tar.bz2 pcsx_rearmed-22dade5ca95efa7fb3530023dbab77f8516bfed7.zip | |
Merge git://github.com/notaz/pcsx_rearmed
Diffstat (limited to 'libpcsxcore/new_dynarec')
| -rw-r--r-- | libpcsxcore/new_dynarec/new_dynarec.c | 16 | ||||
| -rw-r--r-- | libpcsxcore/new_dynarec/pcsxmem.c | 6 |
2 files changed, 19 insertions, 3 deletions
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index bab5ec8..21c9669 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -279,6 +279,8 @@ int tracedebug=0; //#define DEBUG_CYCLE_COUNT 1 +#define NO_CYCLE_PENALTY_THR 12 + int cycle_multiplier; // 100 for 1.0 static int CLOCK_ADJUST(int x) @@ -4981,6 +4983,7 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) int count; int jaddr; int idle=0; + int t=0; if(itype[i]==RJUMP) { *adj=0; @@ -4988,7 +4991,7 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) //if(ba[i]>=start && ba[i]<(start+slen*4)) if(internal_branch(branch_regs[i].is32,ba[i])) { - int t=(ba[i]-start)>>2; + t=(ba[i]-start)>>2; if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle else *adj=ccadj[t]; } @@ -5007,7 +5010,14 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) emit_jmp(0); } else if(*adj==0||invert) { - emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG); + int cycles=CLOCK_ADJUST(count+2); + // faster loop HACK + if (t&&*adj) { + int rel=t-i; + if(-NO_CYCLE_PENALTY_THR<rel&&rel<0) + cycles=CLOCK_ADJUST(*adj)+count+2-*adj; + } + emit_addimm_and_set_flags(cycles,HOST_CCREG); jaddr=(int)out; emit_jns(0); } @@ -9853,7 +9863,7 @@ int new_recompile_block(int addr) // GTE runs in parallel until accessed, divide by 2 for a rough guess cc+=gte_cycletab[source[i]&0x3f]/2; } - else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues + else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues { cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER) } diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c index a42852a..3d14904 100644 --- a/libpcsxcore/new_dynarec/pcsxmem.c +++ b/libpcsxcore/new_dynarec/pcsxmem.c @@ -338,11 +338,17 @@ void new_dyna_pcsx_mem_init(void) // scratchpad map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH); + map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH); map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH); + map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH); // I/O map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1); + map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1); + map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1); map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1); + map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1); + map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1); // L2 // unmapped tables |