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author | notaz | 2011-10-20 02:17:22 +0300 |
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committer | notaz | 2011-10-30 23:48:08 +0200 |
commit | 27727b63bc3da8a9e0affc33fe9d3e0ad1b1d42d (patch) | |
tree | 1f0e68259a2400f50447c32e47ec7a6745ba3c4d /libpcsxcore/new_dynarec | |
parent | 7c621bf0bfcabc7697e03bd4350fbed1fac81f2a (diff) | |
download | pcsx_rearmed-27727b63bc3da8a9e0affc33fe9d3e0ad1b1d42d.tar.gz pcsx_rearmed-27727b63bc3da8a9e0affc33fe9d3e0ad1b1d42d.tar.bz2 pcsx_rearmed-27727b63bc3da8a9e0affc33fe9d3e0ad1b1d42d.zip |
drc: avoid invcode checks on close addesses
yes this makes it possible to miss something, but I hope
it's not going to happen and will deal with it if it does.
Diffstat (limited to 'libpcsxcore/new_dynarec')
-rw-r--r-- | libpcsxcore/new_dynarec/assem_arm.c | 1 | ||||
-rw-r--r-- | libpcsxcore/new_dynarec/new_dynarec.c | 20 |
2 files changed, 16 insertions, 5 deletions
diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c index ddbfafa..5373e70 100644 --- a/libpcsxcore/new_dynarec/assem_arm.c +++ b/libpcsxcore/new_dynarec/assem_arm.c @@ -3209,7 +3209,6 @@ do_writestub(int n) set_jump_target(restore_jump,(int)out); restore_regs(reglist); ra=stubs[n][2]; - if(!restore_jump) ra+=4*3; // skip invcode check emit_jmp(ra); #else // if !PCSX if(addr<0) addr=get_reg(i_regmap,-1); diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index e2c63ed..e6036b2 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -59,6 +59,7 @@ struct regstat uint64_t uu; u_int wasconst; u_int isconst; + u_int waswritten; // regs that were used as store base before uint64_t constmap[HOST_REGS]; }; @@ -3298,7 +3299,7 @@ void store_assemble(int i,struct regstat *i_regs) jaddr=0; } #endif - if(!using_tlb) { + if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) { if(!c||memtarget) { #ifdef DESTRUCTIVE_SHIFT // The x86 shift operation is 'destructive'; it overwrites the @@ -3572,7 +3573,7 @@ void storelr_assemble(int i,struct regstat *i_regs) } if(!c||!memtarget) add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist); - if(!using_tlb) { + if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) { #ifdef RAM_OFFSET int map=get_reg(i_regs->regmap,ROREG); if(map<0) map=HOST_TEMPREG; @@ -3750,7 +3751,7 @@ void c1ls_assemble(int i,struct regstat *i_regs) emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp); type=STORED_STUB; } - if(!using_tlb) { + if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))) { if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1 #ifndef DESTRUCTIVE_SHIFT temp=offset||c||s<0?ar:s; @@ -3869,7 +3870,7 @@ void c2ls_assemble(int i,struct regstat *i_regs) } if(jaddr2) add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist); - if (opcode[i]==0x3a) { // SWC2 + if (!(i_regs->waswritten&(1<<rs1[i]))&&opcode[i]==0x3a) { // SWC2 #if defined(HOST_IMM8) int ir=get_reg(i_regs->regmap,INVCP); assert(ir>=0); @@ -8787,6 +8788,7 @@ int new_recompile_block(int addr) dirty_reg(¤t,CCREG); current.isconst=0; current.wasconst=0; + current.waswritten=0; int ds=0; int cc=0; int hr=-1; @@ -8815,6 +8817,7 @@ int new_recompile_block(int addr) if(current.regmap[hr]==0) current.regmap[hr]=-1; } current.isconst=0; + current.waswritten=0; } if(i>1) { @@ -9441,6 +9444,14 @@ int new_recompile_block(int addr) } memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap)); } + + if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800) + current.waswritten|=1<<rs1[i-1]; + current.waswritten&=~(1<<rt1[i]); + current.waswritten&=~(1<<rt2[i]); + if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800) + current.waswritten&=~(1<<rs1[i]); + /* Branch post-alloc */ if(i>0) { @@ -9770,6 +9781,7 @@ int new_recompile_block(int addr) } } if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; + regs[i].waswritten=current.waswritten; } /* Pass 4 - Cull unused host registers */ |