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| author | notaz | 2011-10-26 00:00:05 +0300 |
|---|---|---|
| committer | notaz | 2011-10-30 23:48:08 +0200 |
| commit | 15d0ba027cfbe88c69b539cc0c9ac6769e577c78 (patch) | |
| tree | 9f141f4538c9c52485da7d16640b491fbf883490 /libpcsxcore | |
| parent | 042c72873a51a9807a9b233b5b28c97c3d72f5d5 (diff) | |
| download | pcsx_rearmed-15d0ba027cfbe88c69b539cc0c9ac6769e577c78.tar.gz pcsx_rearmed-15d0ba027cfbe88c69b539cc0c9ac6769e577c78.tar.bz2 pcsx_rearmed-15d0ba027cfbe88c69b539cc0c9ac6769e577c78.zip | |
drc: detect sw irqs properly
Diffstat (limited to 'libpcsxcore')
| -rw-r--r-- | libpcsxcore/new_dynarec/emu_if.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c index 38d9492..00af7f7 100644 --- a/libpcsxcore/new_dynarec/emu_if.c +++ b/libpcsxcore/new_dynarec/emu_if.c @@ -110,6 +110,8 @@ void pcsx_mtc0(u32 reg, u32 val) evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle); MTC0(reg, val); gen_interupt(); + if (Cause & Status & 0x0300) // possible sw irq + pending_exception = 1; } void pcsx_mtc0_ds(u32 reg, u32 val) |