Merge branch 'mainline' into libretro

7 files changed, 786 insertions, 4225 deletions

diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c
index 708c8ae..21640f8 100644
--- a/libpcsxcore/new_dynarec/assem_arm.c
+++ b/libpcsxcore/new_dynarec/assem_arm.c
@@ -19,7 +19,6 @@
  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
 
-#ifdef PCSX
 #include "../gte.h"
 #define FLAGLESS
 #include "../gte.h"
@@ -27,10 +26,12 @@
 #include "../gte_arm.h"
 #include "../gte_neon.h"
 #include "pcnt.h"
-#endif
 #include "arm_features.h"
 
-#if !BASE_ADDR_FIXED
+#if   defined(BASE_ADDR_FIXED)
+#elif defined(BASE_ADDR_DYNAMIC)
+char *translation_cache;
+#else
 char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096)));
 #endif
 
@@ -40,19 +41,16 @@ char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096)));
 #define CALLER_SAVE_REGS 0x120f
 #endif
 
+#define unused __attribute__((unused))
+
 extern int cycle_count;
 extern int last_count;
 extern int pcaddr;
 extern int pending_exception;
 extern int branch_target;
 extern uint64_t readmem_dword;
-#ifdef MUPEN64
-extern precomp_instr fake_pc;
-#endif
 extern void *dynarec_local;
-extern u_int memory_map[1048576];
 extern u_int mini_ht[32][2];
-extern u_int rounding_modes[4];
 
 void indirect_jump_indexed();
 void indirect_jump();
@@ -119,13 +117,11 @@ const u_int invalidate_addr_reg[16] = {
   0,
   0};
 
-#include "fpu.h"
-
-unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
+static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
 
 /* Linker */
 
-void set_jump_target(int addr,u_int target)
+static void set_jump_target(int addr,u_int target)
 {
   u_char *ptr=(u_char *)addr;
   u_int *ptr2=(u_int *)ptr;
@@ -159,7 +155,8 @@ void set_jump_target(int addr,u_int target)
 // This optionally copies the instruction from the target of the branch into
 // the space before the branch.  Works, but the difference in speed is
 // usually insignificant.
-void set_jump_target_fillslot(int addr,u_int target,int copy)
+#if 0
+static void set_jump_target_fillslot(int addr,u_int target,int copy)
 {
   u_char *ptr=(u_char *)addr;
   u_int *ptr2=(u_int *)ptr;
@@ -188,46 +185,43 @@ void set_jump_target_fillslot(int addr,u_int target,int copy)
     *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
   }
 }
+#endif
 
 /* Literal pool */
-add_literal(int addr,int val)
+static void add_literal(int addr,int val)
 {
   assert(literalcount<sizeof(literals)/sizeof(literals[0]));
   literals[literalcount][0]=addr;
   literals[literalcount][1]=val;
-  literalcount++; 
-} 
+  literalcount++;
+}
 
-void *kill_pointer(void *stub)
+// from a pointer to external jump stub (which was produced by emit_extjump2)
+// find where the jumping insn is
+static void *find_extjump_insn(void *stub)
 {
   int *ptr=(int *)(stub+4);
-  assert((*ptr&0x0ff00000)==0x05900000);
+  assert((*ptr&0x0fff0000)==0x059f0000); // ldr rx, [pc, #ofs]
   u_int offset=*ptr&0xfff;
-  int **l_ptr=(void *)ptr+offset+8;
-  int *i_ptr=*l_ptr;
-  set_jump_target((int)i_ptr,(int)stub);
-  return i_ptr;
+  void **l_ptr=(void *)ptr+offset+8;
+  return *l_ptr;
 }
 
 // find where external branch is liked to using addr of it's stub:
 // get address that insn one after stub loads (dyna_linker arg1),
 // treat it as a pointer to branch insn,
 // return addr where that branch jumps to
-int get_pointer(void *stub)
+static int get_pointer(void *stub)
 {
   //printf("get_pointer(%x)\n",(int)stub);
-  int *ptr=(int *)(stub+4);
-  assert((*ptr&0x0fff0000)==0x059f0000);
-  u_int offset=*ptr&0xfff;
-  int **l_ptr=(void *)ptr+offset+8;
-  int *i_ptr=*l_ptr;
+  int *i_ptr=find_extjump_insn(stub);
   assert((*i_ptr&0x0f000000)==0x0a000000);
   return (int)i_ptr+((*i_ptr<<8)>>6)+8;
 }
 
 // Find the "clean" entry point from a "dirty" entry point
 // by skipping past the call to verify_code
-u_int get_clean_addr(int addr)
+static u_int get_clean_addr(int addr)
 {
   int *ptr=(int *)addr;
   #ifndef HAVE_ARMV7
@@ -244,9 +238,8 @@ u_int get_clean_addr(int addr)
   return (u_int)ptr;
 }
 
-int verify_dirty(int addr)
+static int verify_dirty(u_int *ptr)
 {
-  u_int *ptr=(u_int *)addr;
   #ifndef HAVE_ARMV7
   // get from literal pool
   assert((*ptr&0xFFFF0000)==0xe59f0000);
@@ -266,30 +259,18 @@ int verify_dirty(int addr)
   #endif
   if((*ptr&0xFF000000)!=0xeb000000) ptr++;
   assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
-#ifndef DISABLE_TLB
-  u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
-  if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
-    unsigned int page=source>>12;
-    unsigned int map_value=memory_map[page];
-    if(map_value>=0x80000000) return 0;
-    while(page<((source+len-1)>>12)) {
-      if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
-    }
-    source = source+(map_value<<2);
-  }
-#endif
   //printf("verify_dirty: %x %x %x\n",source,copy,len);
   return !memcmp((void *)source,(void *)copy,len);
 }
 
 // This doesn't necessarily find all clean entry points, just
 // guarantees that it's not dirty
-int isclean(int addr)
+static int isclean(int addr)
 {
   #ifndef HAVE_ARMV7
-  int *ptr=((u_int *)addr)+4;
+  u_int *ptr=((u_int *)addr)+4;
   #else
-  int *ptr=((u_int *)addr)+6;
+  u_int *ptr=((u_int *)addr)+6;
   #endif
   if((*ptr&0xFF000000)!=0xeb000000) ptr++;
   if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
@@ -300,7 +281,7 @@ int isclean(int addr)
 }
 
 // get source that block at addr was compiled from (host pointers)
-void get_bounds(int addr,u_int *start,u_int *end)
+static void get_bounds(int addr,u_int *start,u_int *end)
 {
   u_int *ptr=(u_int *)addr;
   #ifndef HAVE_ARMV7
@@ -322,13 +303,6 @@ void get_bounds(int addr,u_int *start,u_int *end)
   #endif
   if((*ptr&0xFF000000)!=0xeb000000) ptr++;
   assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
-#ifndef DISABLE_TLB
-  u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
-  if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
-    if(memory_map[source>>12]>=0x80000000) source = 0;
-    else source = source+(memory_map[source>>12]<<2);
-  }
-#endif
   *start=source;
   *end=source+len;
 }
@@ -337,25 +311,25 @@ void get_bounds(int addr,u_int *start,u_int *end)
 
 // Note: registers are allocated clean (unmodified state)
 // if you intend to modify the register, you must call dirty_reg().
-void alloc_reg(struct regstat *cur,int i,signed char reg)
+static void alloc_reg(struct regstat *cur,int i,signed char reg)
 {
   int r,hr;
   int preferred_reg = (reg&7);
   if(reg==CCREG) preferred_reg=HOST_CCREG;
   if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
-  
+
   // Don't allocate unused registers
   if((cur->u>>reg)&1) return;
-  
+
   // see if it's already allocated
   for(hr=0;hr<HOST_REGS;hr++)
   {
     if(cur->regmap[hr]==reg) return;
   }
-  
+
   // Keep the same mapping if the register was already allocated in a loop
   preferred_reg = loop_reg(i,reg,preferred_reg);
-  
+
   // Try to allocate the preferred register
   if(cur->regmap[preferred_reg]==-1) {
     cur->regmap[preferred_reg]=reg;
@@ -376,7 +350,7 @@ void alloc_reg(struct regstat *cur,int i,signed char reg)
     cur->isconst&=~(1<<preferred_reg);
     return;
   }
-  
+
   // Clear any unneeded registers
   // We try to keep the mapping consistent, if possible, because it
   // makes branches easier (especially loops).  So we try to allocate
@@ -419,7 +393,7 @@ void alloc_reg(struct regstat *cur,int i,signed char reg)
       return;
     }
   }
-  
+
   // Ok, now we have to evict someone
   // Pick a register we hopefully won't need soon
   u_char hsn[MAXREG+1];
@@ -502,26 +476,26 @@ void alloc_reg(struct regstat *cur,int i,signed char reg)
   SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
 }
 
-void alloc_reg64(struct regstat *cur,int i,signed char reg)
+static void alloc_reg64(struct regstat *cur,int i,signed char reg)
 {
   int preferred_reg = 8+(reg&1);
   int r,hr;
-  
+
   // allocate the lower 32 bits
   alloc_reg(cur,i,reg);
-  
+
   // Don't allocate unused registers
   if((cur->uu>>reg)&1) return;
-  
+
   // see if the upper half is already allocated
   for(hr=0;hr<HOST_REGS;hr++)
   {
     if(cur->regmap[hr]==reg+64) return;
   }
-  
+
   // Keep the same mapping if the register was already allocated in a loop
   preferred_reg = loop_reg(i,reg,preferred_reg);
-  
+
   // Try to allocate the preferred register
   if(cur->regmap[preferred_reg]==-1) {
     cur->regmap[preferred_reg]=reg|64;
@@ -542,7 +516,7 @@ void alloc_reg64(struct regstat *cur,int i,signed char reg)
     cur->isconst&=~(1<<preferred_reg);
     return;
   }
-  
+
   // Clear any unneeded registers
   // We try to keep the mapping consistent, if possible, because it
   // makes branches easier (especially loops).  So we try to allocate
@@ -585,7 +559,7 @@ void alloc_reg64(struct regstat *cur,int i,signed char reg)
       return;
     }
   }
-  
+
   // Ok, now we have to evict someone
   // Pick a register we hopefully won't need soon
   u_char hsn[MAXREG+1];
@@ -671,17 +645,17 @@ void alloc_reg64(struct regstat *cur,int i,signed char reg)
 // Allocate a temporary register.  This is done without regard to
 // dirty status or whether the register we request is on the unneeded list
 // Note: This will only allocate one register, even if called multiple times
-void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
+static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
 {
   int r,hr;
   int preferred_reg = -1;
-  
+
   // see if it's already allocated
   for(hr=0;hr<HOST_REGS;hr++)
   {
     if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
   }
-  
+
   // Try to allocate any available register
   for(hr=HOST_REGS-1;hr>=0;hr--) {
     if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
@@ -691,7 +665,7 @@ void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
       return;
     }
   }
-  
+
   // Find an unneeded register
   for(hr=HOST_REGS-1;hr>=0;hr--)
   {
@@ -720,7 +694,7 @@ void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
       }
     }
   }
-  
+
   // Ok, now we have to evict someone
   // Pick a register we hopefully won't need soon
   // TODO: we might want to follow unconditional jumps here
@@ -790,12 +764,13 @@ void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
   }
   SysPrintf("This shouldn't happen");exit(1);
 }
+
 // Allocate a specific ARM register.
-void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
+static void alloc_arm_reg(struct regstat *cur,int i,signed char reg,int hr)
 {
   int n;
   int dirty=0;
-  
+
   // see if it's already allocated (and dealloc it)
   for(n=0;n<HOST_REGS;n++)
   {
@@ -804,7 +779,7 @@ void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
       cur->regmap[n]=-1;
     }
   }
-  
+
   cur->regmap[hr]=reg;
   cur->dirty&=~(1<<hr);
   cur->dirty|=dirty<<hr;
@@ -812,7 +787,7 @@ void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
 }
 
 // Alloc cycle count into dedicated register
-alloc_cc(struct regstat *cur,int i)
+static void alloc_cc(struct regstat *cur,int i)
 {
   alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
 }
@@ -822,7 +797,7 @@ alloc_cc(struct regstat *cur,int i)
 
 /* Assembler */
 
-char regname[16][4] = {
+static unused char regname[16][4] = {
  "r0",
  "r1",
  "r2",
@@ -840,39 +815,21 @@ char regname[16][4] = {
  "lr",
  "pc"};
 
-void output_byte(u_char byte)
-{
-  *(out++)=byte;
-}
-void output_modrm(u_char mod,u_char rm,u_char ext)
-{
-  assert(mod<4);
-  assert(rm<8);
-  assert(ext<8);
-  u_char byte=(mod<<6)|(ext<<3)|rm;
-  *(out++)=byte;
-}
-void output_sib(u_char scale,u_char index,u_char base)
-{
-  assert(scale<4);
-  assert(index<8);
-  assert(base<8);
-  u_char byte=(scale<<6)|(index<<3)|base;
-  *(out++)=byte;
-}
-void output_w32(u_int word)
+static void output_w32(u_int word)
 {
   *((u_int *)out)=word;
   out+=4;
 }
-u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
+
+static u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
 {
   assert(rd<16);
   assert(rn<16);
   assert(rm<16);
   return((rn<<16)|(rd<<12)|rm);
 }
-u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
+
+static u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
 {
   assert(rd<16);
   assert(rn<16);
@@ -880,7 +837,8 @@ u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
   assert((shift&1)==0);
   return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
 }
-u_int genimm(u_int imm,u_int *encoded)
+
+static u_int genimm(u_int imm,u_int *encoded)
 {
   *encoded=0;
   if(imm==0) return 1;
@@ -895,12 +853,15 @@ u_int genimm(u_int imm,u_int *encoded)
   }
   return 0;
 }
-void genimm_checked(u_int imm,u_int *encoded)
+
+static void genimm_checked(u_int imm,u_int *encoded)
 {
   u_int ret=genimm(imm,encoded);
   assert(ret);
+  (void)ret;
 }
-u_int genjmp(u_int addr)
+
+static u_int genjmp(u_int addr)
 {
   int offset=addr-(int)out-8;
   if(offset<-33554432||offset>=33554432) {
@@ -913,96 +874,99 @@ u_int genjmp(u_int addr)
   return ((u_int)offset>>2)&0xffffff;
 }
 
-void emit_mov(int rs,int rt)
+static void emit_mov(int rs,int rt)
 {
   assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
   output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
 }
 
-void emit_movs(int rs,int rt)
+static void emit_movs(int rs,int rt)
 {
   assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
   output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
 }
 
-void emit_add(int rs1,int rs2,int rt)
+static void emit_add(int rs1,int rs2,int rt)
 {
   assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_adds(int rs1,int rs2,int rt)
+static void emit_adds(int rs1,int rs2,int rt)
 {
   assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_adcs(int rs1,int rs2,int rt)
+static void emit_adcs(int rs1,int rs2,int rt)
 {
   assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_sbc(int rs1,int rs2,int rt)
+static void emit_sbc(int rs1,int rs2,int rt)
 {
   assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_sbcs(int rs1,int rs2,int rt)
+static void emit_sbcs(int rs1,int rs2,int rt)
 {
   assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_neg(int rs, int rt)
+static void emit_neg(int rs, int rt)
 {
   assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
   output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
 }
 
-void emit_negs(int rs, int rt)
+static void emit_negs(int rs, int rt)
 {
   assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
   output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
 }
 
-void emit_sub(int rs1,int rs2,int rt)
+static void emit_sub(int rs1,int rs2,int rt)
 {
   assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_subs(int rs1,int rs2,int rt)
+static void emit_subs(int rs1,int rs2,int rt)
 {
   assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_zeroreg(int rt)
+static void emit_zeroreg(int rt)
 {
   assem_debug("mov %s,#0\n",regname[rt]);
   output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
 }
 
-void emit_loadlp(u_int imm,u_int rt)
+static void emit_loadlp(u_int imm,u_int rt)
 {
   add_literal((int)out,imm);
   assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
   output_w32(0xe5900000|rd_rn_rm(rt,15,0));
 }
-void emit_movw(u_int imm,u_int rt)
+
+static void emit_movw(u_int imm,u_int rt)
 {
   assert(imm<65536);
   assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
   output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
 }
-void emit_movt(u_int imm,u_int rt)
+
+static void emit_movt(u_int imm,u_int rt)
 {
   assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
   output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
 }
-void emit_movimm(u_int imm,u_int rt)
+
+static void emit_movimm(u_int imm,u_int rt)
 {
   u_int armval;
   if(genimm(imm,&armval)) {
@@ -1029,21 +993,20 @@ void emit_movimm(u_int imm,u_int rt)
     #endif
   }
 }
-void emit_pcreladdr(u_int rt)
+
+static void emit_pcreladdr(u_int rt)
 {
   assem_debug("add %s,pc,#?\n",regname[rt]);
   output_w32(0xe2800000|rd_rn_rm(rt,15,0));
 }
 
-void emit_loadreg(int r, int hr)
+static void emit_loadreg(int r, int hr)
 {
-#ifdef FORCE32
   if(r&64) {
     SysPrintf("64bit load in 32bit mode!\n");
     assert(0);
     return;
   }
-#endif
   if((r&63)==0)
     emit_zeroreg(hr);
   else {
@@ -1060,15 +1023,14 @@ void emit_loadreg(int r, int hr)
     output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
   }
 }
-void emit_storereg(int r, int hr)
+
+static void emit_storereg(int r, int hr)
 {
-#ifdef FORCE32
   if(r&64) {
     SysPrintf("64bit store in 32bit mode!\n");
     assert(0);
     return;
   }
-#endif
   int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
   if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
   if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
@@ -1080,13 +1042,13 @@ void emit_storereg(int r, int hr)
   output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
 }
 
-void emit_test(int rs, int rt)
+static void emit_test(int rs, int rt)
 {
   assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
   output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
 }
 
-void emit_testimm(int rs,int imm)
+static void emit_testimm(int rs,int imm)
 {
   u_int armval;
   assem_debug("tst %s,#%d\n",regname[rs],imm);
@@ -1094,7 +1056,7 @@ void emit_testimm(int rs,int imm)
   output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
 }
 
-void emit_testeqimm(int rs,int imm)
+static void emit_testeqimm(int rs,int imm)
 {
   u_int armval;
   assem_debug("tsteq %s,$%d\n",regname[rs],imm);
@@ -1102,36 +1064,37 @@ void emit_testeqimm(int rs,int imm)
   output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
 }
 
-void emit_not(int rs,int rt)
+static void emit_not(int rs,int rt)
 {
   assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
   output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
 }
 
-void emit_mvnmi(int rs,int rt)
+static void emit_mvnmi(int rs,int rt)
 {
   assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
   output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
 }
 
-void emit_and(u_int rs1,u_int rs2,u_int rt)
+static void emit_and(u_int rs1,u_int rs2,u_int rt)
 {
   assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_or(u_int rs1,u_int rs2,u_int rt)
+static void emit_or(u_int rs1,u_int rs2,u_int rt)
 {
   assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
 }
-void emit_or_and_set_flags(int rs1,int rs2,int rt)
+
+static void emit_or_and_set_flags(int rs1,int rs2,int rt)
 {
   assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
+static void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
 {
   assert(rs<16);
   assert(rt<16);
@@ -1140,7 +1103,7 @@ void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
   output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
 }
 
-void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
+static void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
 {
   assert(rs<16);
   assert(rt<16);
@@ -1149,13 +1112,13 @@ void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
   output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
 }
 
-void emit_xor(u_int rs1,u_int rs2,u_int rt)
+static void emit_xor(u_int rs1,u_int rs2,u_int rt)
 {
   assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_addimm(u_int rs,int imm,u_int rt)
+static void emit_addimm(u_int rs,int imm,u_int rt)
 {
   assert(rs<16);
   assert(rt<16);
@@ -1196,7 +1159,7 @@ void emit_addimm(u_int rs,int imm,u_int rt)
   else if(rs!=rt) emit_mov(rs,rt);
 }
 
-void emit_addimm_and_set_flags(int imm,int rt)
+static void emit_addimm_and_set_flags(int imm,int rt)
 {
   assert(imm>-65536&&imm<65536);
   u_int armval;
@@ -1218,49 +1181,28 @@ void emit_addimm_and_set_flags(int imm,int rt)
     output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
   }
 }
-void emit_addimm_no_flags(u_int imm,u_int rt)
+
+static void emit_addimm_no_flags(u_int imm,u_int rt)
 {
   emit_addimm(rt,imm,rt);
 }
 
-void emit_addnop(u_int r)
+static void emit_addnop(u_int r)
 {
   assert(r<16);
   assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
   output_w32(0xe2800000|rd_rn_rm(r,r,0));
 }
 
-void emit_adcimm(u_int rs,int imm,u_int rt)
+static void emit_adcimm(u_int rs,int imm,u_int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
   assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
 }
-/*void emit_sbcimm(int imm,u_int rt)
-{
-  u_int armval;
-  genimm_checked(imm,&armval);
-  assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
-  output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
-}*/
-void emit_sbbimm(int imm,u_int rt)
-{
-  assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
-  assert(rt<8);
-  if(imm<128&&imm>=-128) {
-    output_byte(0x83);
-    output_modrm(3,rt,3);
-    output_byte(imm);
-  }
-  else
-  {
-    output_byte(0x81);
-    output_modrm(3,rt,3);
-    output_w32(imm);
-  }
-}
-void emit_rscimm(int rs,int imm,u_int rt)
+
+static void emit_rscimm(int rs,int imm,u_int rt)
 {
   assert(0);
   u_int armval;
@@ -1269,7 +1211,7 @@ void emit_rscimm(int rs,int imm,u_int rt)
   output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
+static void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
 {
   // TODO: if(genimm(imm,&armval)) ...
   // else
@@ -1278,14 +1220,7 @@ void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
   emit_adcimm(rsh,0,rth);
 }
 
-void emit_sbb(int rs1,int rs2)
-{
-  assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
-  output_byte(0x19);
-  output_modrm(3,rs1,rs2);
-}
-
-void emit_andimm(int rs,int imm,int rt)
+static void emit_andimm(int rs,int imm,int rt)
 {
   u_int armval;
   if(imm==0) {
@@ -1321,7 +1256,7 @@ void emit_andimm(int rs,int imm,int rt)
   }
 }
 
-void emit_orimm(int rs,int imm,int rt)
+static void emit_orimm(int rs,int imm,int rt)
 {
   u_int armval;
   if(imm==0) {
@@ -1338,7 +1273,7 @@ void emit_orimm(int rs,int imm,int rt)
   }
 }
 
-void emit_xorimm(int rs,int imm,int rt)
+static void emit_xorimm(int rs,int imm,int rt)
 {
   u_int armval;
   if(imm==0) {
@@ -1355,7 +1290,7 @@ void emit_xorimm(int rs,int imm,int rt)
   }
 }
 
-void emit_shlimm(int rs,u_int imm,int rt)
+static void emit_shlimm(int rs,u_int imm,int rt)
 {
   assert(imm>0);
   assert(imm<32);
@@ -1364,7 +1299,7 @@ void emit_shlimm(int rs,u_int imm,int rt)
   output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
 }
 
-void emit_lsls_imm(int rs,int imm,int rt)
+static void emit_lsls_imm(int rs,int imm,int rt)
 {
   assert(imm>0);
   assert(imm<32);
@@ -1372,7 +1307,7 @@ void emit_lsls_imm(int rs,int imm,int rt)
   output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
 }
 
-void emit_lslpls_imm(int rs,int imm,int rt)
+static unused void emit_lslpls_imm(int rs,int imm,int rt)
 {
   assert(imm>0);
   assert(imm<32);
@@ -1380,7 +1315,7 @@ void emit_lslpls_imm(int rs,int imm,int rt)
   output_w32(0x51b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
 }
 
-void emit_shrimm(int rs,u_int imm,int rt)
+static void emit_shrimm(int rs,u_int imm,int rt)
 {
   assert(imm>0);
   assert(imm<32);
@@ -1388,7 +1323,7 @@ void emit_shrimm(int rs,u_int imm,int rt)
   output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
 }
 
-void emit_sarimm(int rs,u_int imm,int rt)
+static void emit_sarimm(int rs,u_int imm,int rt)
 {
   assert(imm>0);
   assert(imm<32);
@@ -1396,7 +1331,7 @@ void emit_sarimm(int rs,u_int imm,int rt)
   output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
 }
 
-void emit_rorimm(int rs,u_int imm,int rt)
+static void emit_rorimm(int rs,u_int imm,int rt)
 {
   assert(imm>0);
   assert(imm<32);
@@ -1404,7 +1339,7 @@ void emit_rorimm(int rs,u_int imm,int rt)
   output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
 }
 
-void emit_shldimm(int rs,int rs2,u_int imm,int rt)
+static void emit_shldimm(int rs,int rs2,u_int imm,int rt)
 {
   assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
   assert(imm>0);
@@ -1416,7 +1351,7 @@ void emit_shldimm(int rs,int rs2,u_int imm,int rt)
   output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
 }
 
-void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
+static void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
 {
   assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
   assert(imm>0);
@@ -1428,7 +1363,7 @@ void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
   output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
 }
 
-void emit_signextend16(int rs,int rt)
+static void emit_signextend16(int rs,int rt)
 {
   #ifndef HAVE_ARMV6
   emit_shlimm(rs,16,rt);
@@ -1439,7 +1374,7 @@ void emit_signextend16(int rs,int rt)
   #endif
 }
 
-void emit_signextend8(int rs,int rt)
+static void emit_signextend8(int rs,int rt)
 {
   #ifndef HAVE_ARMV6
   emit_shlimm(rs,24,rt);
@@ -1450,7 +1385,7 @@ void emit_signextend8(int rs,int rt)
   #endif
 }
 
-void emit_shl(u_int rs,u_int shift,u_int rt)
+static void emit_shl(u_int rs,u_int shift,u_int rt)
 {
   assert(rs<16);
   assert(rt<16);
@@ -1459,7 +1394,8 @@ void emit_shl(u_int rs,u_int shift,u_int rt)
   assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
   output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
 }
-void emit_shr(u_int rs,u_int shift,u_int rt)
+
+static void emit_shr(u_int rs,u_int shift,u_int rt)
 {
   assert(rs<16);
   assert(rt<16);
@@ -1467,7 +1403,8 @@ void emit_shr(u_int rs,u_int shift,u_int rt)
   assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
   output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
 }
-void emit_sar(u_int rs,u_int shift,u_int rt)
+
+static void emit_sar(u_int rs,u_int shift,u_int rt)
 {
   assert(rs<16);
   assert(rt<16);
@@ -1475,33 +1412,8 @@ void emit_sar(u_int rs,u_int shift,u_int rt)
   assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
   output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
 }
-void emit_shlcl(int r)
-{
-  assem_debug("shl %%%s,%%cl\n",regname[r]);
-  assert(0);
-}
-void emit_shrcl(int r)
-{
-  assem_debug("shr %%%s,%%cl\n",regname[r]);
-  assert(0);
-}
-void emit_sarcl(int r)
-{
-  assem_debug("sar %%%s,%%cl\n",regname[r]);
-  assert(0);
-}
 
-void emit_shldcl(int r1,int r2)
-{
-  assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
-  assert(0);
-}
-void emit_shrdcl(int r1,int r2)
-{
-  assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
-  assert(0);
-}
-void emit_orrshl(u_int rs,u_int shift,u_int rt)
+static void emit_orrshl(u_int rs,u_int shift,u_int rt)
 {
   assert(rs<16);
   assert(rt<16);
@@ -1509,7 +1421,8 @@ void emit_orrshl(u_int rs,u_int shift,u_int rt)
   assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
   output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
 }
-void emit_orrshr(u_int rs,u_int shift,u_int rt)
+
+static void emit_orrshr(u_int rs,u_int shift,u_int rt)
 {
   assert(rs<16);
   assert(rt<16);
@@ -1518,7 +1431,7 @@ void emit_orrshr(u_int rs,u_int shift,u_int rt)
   output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
 }
 
-void emit_cmpimm(int rs,int imm)
+static void emit_cmpimm(int rs,int imm)
 {
   u_int armval;
   if(genimm(imm,&armval)) {
@@ -1540,85 +1453,79 @@ void emit_cmpimm(int rs,int imm)
   }
 }
 
-void emit_cmovne(u_int *addr,int rt)
-{
-  assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
-  assert(0);
-}
-void emit_cmovl(u_int *addr,int rt)
-{
-  assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
-  assert(0);
-}
-void emit_cmovs(u_int *addr,int rt)
-{
-  assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
-  assert(0);
-}
-void emit_cmovne_imm(int imm,int rt)
+static void emit_cmovne_imm(int imm,int rt)
 {
   assem_debug("movne %s,#%d\n",regname[rt],imm);
   u_int armval;
   genimm_checked(imm,&armval);
   output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
 }
-void emit_cmovl_imm(int imm,int rt)
+
+static void emit_cmovl_imm(int imm,int rt)
 {
   assem_debug("movlt %s,#%d\n",regname[rt],imm);
   u_int armval;
   genimm_checked(imm,&armval);
   output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
 }
-void emit_cmovb_imm(int imm,int rt)
+
+static void emit_cmovb_imm(int imm,int rt)
 {
   assem_debug("movcc %s,#%d\n",regname[rt],imm);
   u_int armval;
   genimm_checked(imm,&armval);
   output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
 }
-void emit_cmovs_imm(int imm,int rt)
+
+static void emit_cmovs_imm(int imm,int rt)
 {
   assem_debug("movmi %s,#%d\n",regname[rt],imm);
   u_int armval;
   genimm_checked(imm,&armval);
   output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
 }
-void emit_cmove_reg(int rs,int rt)
+
+static void emit_cmove_reg(int rs,int rt)
 {
   assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
   output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
 }
-void emit_cmovne_reg(int rs,int rt)
+
+static void emit_cmovne_reg(int rs,int rt)
 {
   assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
   output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
 }
-void emit_cmovl_reg(int rs,int rt)
+
+static void emit_cmovl_reg(int rs,int rt)
 {
   assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
   output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
 }
-void emit_cmovs_reg(int rs,int rt)
+
+static void emit_cmovs_reg(int rs,int rt)
 {
   assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
   output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
 }
 
-void emit_slti32(int rs,int imm,int rt)
+static void emit_slti32(int rs,int imm,int rt)
 {
   if(rs!=rt) emit_zeroreg(rt);
   emit_cmpimm(rs,imm);
   if(rs==rt) emit_movimm(0,rt);
   emit_cmovl_imm(1,rt);
 }
-void emit_sltiu32(int rs,int imm,int rt)
+
+static void emit_sltiu32(int rs,int imm,int rt)
 {
   if(rs!=rt) emit_zeroreg(rt);
   emit_cmpimm(rs,imm);
   if(rs==rt) emit_movimm(0,rt);
   emit_cmovb_imm(1,rt);
 }
-void emit_slti64_32(int rsh,int rsl,int imm,int rt)
+
+static void emit_slti64_32(int rsh,int rsl,int imm,int rt)
 {
   assert(rsh!=rt);
   emit_slti32(rsl,imm,rt);
@@ -1635,7 +1542,8 @@ void emit_slti64_32(int rsh,int rsl,int imm,int rt)
     emit_cmovl_imm(1,rt);
   }
 }
-void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
+
+static void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
 {
   assert(rsh!=rt);
   emit_sltiu32(rsl,imm,rt);
@@ -1651,26 +1559,29 @@ void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
   }
 }
 
-void emit_cmp(int rs,int rt)
+static void emit_cmp(int rs,int rt)
 {
   assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
   output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
 }
-void emit_set_gz32(int rs, int rt)
+
+static void emit_set_gz32(int rs, int rt)
 {
   //assem_debug("set_gz32\n");
   emit_cmpimm(rs,1);
   emit_movimm(1,rt);
   emit_cmovl_imm(0,rt);
 }
-void emit_set_nz32(int rs, int rt)
+
+static void emit_set_nz32(int rs, int rt)
 {
   //assem_debug("set_nz32\n");
   if(rs!=rt) emit_movs(rs,rt);
   else emit_test(rs,rs);
   emit_cmovne_imm(1,rt);
 }
-void emit_set_gz64_32(int rsh, int rsl, int rt)
+
+static void emit_set_gz64_32(int rsh, int rsl, int rt)
 {
   //assem_debug("set_gz64\n");
   emit_set_gz32(rsl,rt);
@@ -1678,13 +1589,15 @@ void emit_set_gz64_32(int rsh, int rsl, int rt)
   emit_cmovne_imm(1,rt);
   emit_cmovs_imm(0,rt);
 }
-void emit_set_nz64_32(int rsh, int rsl, int rt)
+
+static void emit_set_nz64_32(int rsh, int rsl, int rt)
 {
   //assem_debug("set_nz64\n");
   emit_or_and_set_flags(rsh,rsl,rt);
   emit_cmovne_imm(1,rt);
 }
-void emit_set_if_less32(int rs1, int rs2, int rt)
+
+static void emit_set_if_less32(int rs1, int rs2, int rt)
 {
   //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
   if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
@@ -1692,7 +1605,8 @@ void emit_set_if_less32(int rs1, int rs2, int rt)
   if(rs1==rt||rs2==rt) emit_movimm(0,rt);
   emit_cmovl_imm(1,rt);
 }
-void emit_set_if_carry32(int rs1, int rs2, int rt)
+
+static void emit_set_if_carry32(int rs1, int rs2, int rt)
 {
   //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
   if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
@@ -1700,7 +1614,8 @@ void emit_set_if_carry32(int rs1, int rs2, int rt)
   if(rs1==rt||rs2==rt) emit_movimm(0,rt);
   emit_cmovb_imm(1,rt);
 }
-void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
+
+static void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
 {
   //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
   assert(u1!=rt);
@@ -1710,7 +1625,8 @@ void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
   emit_sbcs(u1,u2,HOST_TEMPREG);
   emit_cmovl_imm(1,rt);
 }
-void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
+
+static void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
 {
   //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
   assert(u1!=rt);
@@ -1721,111 +1637,97 @@ void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
   emit_cmovb_imm(1,rt);
 }
 
-void emit_call(int a)
+static void emit_call(int a)
 {
   assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
   u_int offset=genjmp(a);
   output_w32(0xeb000000|offset);
 }
-void emit_jmp(int a)
+
+static void emit_jmp(int a)
 {
   assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
   u_int offset=genjmp(a);
   output_w32(0xea000000|offset);
 }
-void emit_jne(int a)
+
+static void emit_jne(int a)
 {
   assem_debug("bne %x\n",a);
   u_int offset=genjmp(a);
   output_w32(0x1a000000|offset);
 }
-void emit_jeq(int a)
+
+static void emit_jeq(int a)
 {
   assem_debug("beq %x\n",a);
   u_int offset=genjmp(a);
   output_w32(0x0a000000|offset);
 }
-void emit_js(int a)
+
+static void emit_js(int a)
 {
   assem_debug("bmi %x\n",a);
   u_int offset=genjmp(a);
   output_w32(0x4a000000|offset);
 }
-void emit_jns(int a)
+
+static void emit_jns(int a)
 {
   assem_debug("bpl %x\n",a);
   u_int offset=genjmp(a);
   output_w32(0x5a000000|offset);
 }
-void emit_jl(int a)
+
+static void emit_jl(int a)
 {
   assem_debug("blt %x\n",a);
   u_int offset=genjmp(a);
   output_w32(0xba000000|offset);
 }
-void emit_jge(int a)
+
+static void emit_jge(int a)
 {
   assem_debug("bge %x\n",a);
   u_int offset=genjmp(a);
   output_w32(0xaa000000|offset);
 }
-void emit_jno(int a)
+
+static void emit_jno(int a)
 {
   assem_debug("bvc %x\n",a);
   u_int offset=genjmp(a);
   output_w32(0x7a000000|offset);
 }
-void emit_jc(int a)
+
+static void emit_jc(int a)
 {
   assem_debug("bcs %x\n",a);
   u_int offset=genjmp(a);
   output_w32(0x2a000000|offset);
 }
-void emit_jcc(int a)
+
+static void emit_jcc(int a)
 {
   assem_debug("bcc %x\n",a);
   u_int offset=genjmp(a);
   output_w32(0x3a000000|offset);
 }
 
-void emit_pushimm(int imm)
-{
-  assem_debug("push $%x\n",imm);
-  assert(0);
-}
-void emit_pusha()
-{
-  assem_debug("pusha\n");
-  assert(0);
-}
-void emit_popa()
-{
-  assem_debug("popa\n");
-  assert(0);
-}
-void emit_pushreg(u_int r)
-{
-  assem_debug("push %%%s\n",regname[r]);
-  assert(0);
-}
-void emit_popreg(u_int r)
-{
-  assem_debug("pop %%%s\n",regname[r]);
-  assert(0);
-}
-void emit_callreg(u_int r)
+static void emit_callreg(u_int r)
 {
   assert(r<15);
   assem_debug("blx %s\n",regname[r]);
   output_w32(0xe12fff30|r);
 }
-void emit_jmpreg(u_int r)
+
+static void emit_jmpreg(u_int r)
 {
   assem_debug("mov pc,%s\n",regname[r]);
   output_w32(0xe1a00000|rd_rn_rm(15,0,r));
 }
 
-void emit_readword_indexed(int offset, int rs, int rt)
+static void emit_readword_indexed(int offset, int rs, int rt)
 {
   assert(offset>-4096&&offset<4096);
   assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
@@ -1835,37 +1737,44 @@ void emit_readword_indexed(int offset, int rs, int rt)
     output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
   }
 }
-void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
+
+static void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
 {
   assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
 }
-void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
+
+static void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
 {
   assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
 }
-void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
+
+static void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
 {
   assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
 }
-void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
+
+static void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
 {
   assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
 }
-void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
+
+static void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
 {
   assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
 }
-void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
+
+static void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
 {
   assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
 }
-void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
+
+static void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
 {
   if(map<0) emit_readword_indexed(addr, rs, rt);
   else {
@@ -1873,7 +1782,8 @@ void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
     emit_readword_dualindexedx4(rs, map, rt);
   }
 }
-void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
+
+static void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
 {
   if(map<0) {
     if(rh>=0) emit_readword_indexed(addr, rs, rh);
@@ -1885,7 +1795,8 @@ void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
     emit_readword_indexed_tlb(addr, rs, map, rl);
   }
 }
-void emit_movsbl_indexed(int offset, int rs, int rt)
+
+static void emit_movsbl_indexed(int offset, int rs, int rt)
 {
   assert(offset>-256&&offset<256);
   assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
@@ -1895,7 +1806,8 @@ void emit_movsbl_indexed(int offset, int rs, int rt)
     output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
   }
 }
-void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
+
+static void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
 {
   if(map<0) emit_movsbl_indexed(addr, rs, rt);
   else {
@@ -1911,7 +1823,8 @@ void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
     }
   }
 }
-void emit_movswl_indexed(int offset, int rs, int rt)
+
+static void emit_movswl_indexed(int offset, int rs, int rt)
 {
   assert(offset>-256&&offset<256);
   assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
@@ -1921,7 +1834,8 @@ void emit_movswl_indexed(int offset, int rs, int rt)
     output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
   }
 }
-void emit_movzbl_indexed(int offset, int rs, int rt)
+
+static void emit_movzbl_indexed(int offset, int rs, int rt)
 {
   assert(offset>-4096&&offset<4096);
   assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
@@ -1931,12 +1845,14 @@ void emit_movzbl_indexed(int offset, int rs, int rt)
     output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
   }
 }
-void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
+
+static void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
 {
   assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
 }
-void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
+
+static void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
 {
   if(map<0) emit_movzbl_indexed(addr, rs, rt);
   else {
@@ -1948,7 +1864,8 @@ void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
     }
   }
 }
-void emit_movzwl_indexed(int offset, int rs, int rt)
+
+static void emit_movzwl_indexed(int offset, int rs, int rt)
 {
   assert(offset>-256&&offset<256);
   assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
@@ -1958,6 +1875,7 @@ void emit_movzwl_indexed(int offset, int rs, int rt)
     output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
   }
 }
+
 static void emit_ldrd(int offset, int rs, int rt)
 {
   assert(offset>-256&&offset<256);
@@ -1968,53 +1886,48 @@ static void emit_ldrd(int offset, int rs, int rt)
     output_w32(0xe14000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
   }
 }
-void emit_readword(int addr, int rt)
+
+static void emit_readword(int addr, int rt)
 {
   u_int offset = addr-(u_int)&dynarec_local;
   assert(offset<4096);
   assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
   output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
 }
-void emit_movsbl(int addr, int rt)
+
+static unused void emit_movsbl(int addr, int rt)
 {
   u_int offset = addr-(u_int)&dynarec_local;
   assert(offset<256);
   assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
   output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
 }
-void emit_movswl(int addr, int rt)
+
+static unused void emit_movswl(int addr, int rt)
 {
   u_int offset = addr-(u_int)&dynarec_local;
   assert(offset<256);
   assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
   output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
 }
-void emit_movzbl(int addr, int rt)
+
+static unused void emit_movzbl(int addr, int rt)
 {
   u_int offset = addr-(u_int)&dynarec_local;
   assert(offset<4096);
   assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
   output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
 }
-void emit_movzwl(int addr, int rt)
+
+static unused void emit_movzwl(int addr, int rt)
 {
   u_int offset = addr-(u_int)&dynarec_local;
   assert(offset<256);
   assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
   output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
 }
-void emit_movzwl_reg(int rs, int rt)
-{
-  assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
-  assert(0);
-}
 
-void emit_xchg(int rs, int rt)
-{
-  assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
-  assert(0);
-}
-void emit_writeword_indexed(int rt, int offset, int rs)
+static void emit_writeword_indexed(int rt, int offset, int rs)
 {
   assert(offset>-4096&&offset<4096);
   assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
@@ -2024,12 +1937,14 @@ void emit_writeword_indexed(int rt, int offset, int rs)
     output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
   }
 }
-void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
+
+static void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
 {
   assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
 }
-void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
+
+static void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
 {
   if(map<0) emit_writeword_indexed(rt, addr, rs);
   else {
@@ -2037,7 +1952,8 @@ void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
     emit_writeword_dualindexedx4(rt, rs, map);
   }
 }
-void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
+
+static void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
 {
   if(map<0) {
     if(rh>=0) emit_writeword_indexed(rh, addr, rs);
@@ -2053,7 +1969,8 @@ void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int
     }
   }
 }
-void emit_writehword_indexed(int rt, int offset, int rs)
+
+static void emit_writehword_indexed(int rt, int offset, int rs)
 {
   assert(offset>-256&&offset<256);
   assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
@@ -2063,7 +1980,8 @@ void emit_writehword_indexed(int rt, int offset, int rs)
     output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
   }
 }
-void emit_writebyte_indexed(int rt, int offset, int rs)
+
+static void emit_writebyte_indexed(int rt, int offset, int rs)
 {
   assert(offset>-4096&&offset<4096);
   assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
@@ -2073,12 +1991,14 @@ void emit_writebyte_indexed(int rt, int offset, int rs)
     output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
   }
 }
-void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
+
+static void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
 {
   assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
 }
-void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
+
+static void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
 {
   if(map<0) emit_writebyte_indexed(rt, addr, rs);
   else {
@@ -2090,64 +2010,50 @@ void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
     }
   }
 }
-void emit_strcc_dualindexed(int rs1, int rs2, int rt)
+
+static void emit_strcc_dualindexed(int rs1, int rs2, int rt)
 {
   assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
 }
-void emit_strccb_dualindexed(int rs1, int rs2, int rt)
+
+static void emit_strccb_dualindexed(int rs1, int rs2, int rt)
 {
   assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
 }
-void emit_strcch_dualindexed(int rs1, int rs2, int rt)
+
+static void emit_strcch_dualindexed(int rs1, int rs2, int rt)
 {
   assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
 }
-void emit_writeword(int rt, int addr)
+
+static void emit_writeword(int rt, int addr)
 {
   u_int offset = addr-(u_int)&dynarec_local;
   assert(offset<4096);
   assem_debug("str %s,fp+%d\n",regname[rt],offset);
   output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
 }
-void emit_writehword(int rt, int addr)
+
+static unused void emit_writehword(int rt, int addr)
 {
   u_int offset = addr-(u_int)&dynarec_local;
   assert(offset<256);
   assem_debug("strh %s,fp+%d\n",regname[rt],offset);
   output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
 }
-void emit_writebyte(int rt, int addr)
+
+static unused void emit_writebyte(int rt, int addr)
 {
   u_int offset = addr-(u_int)&dynarec_local;
   assert(offset<4096);
   assem_debug("strb %s,fp+%d\n",regname[rt],offset);
   output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
 }
-void emit_writeword_imm(int imm, int addr)
-{
-  assem_debug("movl $%x,%x\n",imm,addr);
-  assert(0);
-}
-void emit_writebyte_imm(int imm, int addr)
-{
-  assem_debug("movb $%x,%x\n",imm,addr);
-  assert(0);
-}
 
-void emit_mul(int rs)
-{
-  assem_debug("mul %%%s\n",regname[rs]);
-  assert(0);
-}
-void emit_imul(int rs)
-{
-  assem_debug("imul %%%s\n",regname[rs]);
-  assert(0);
-}
-void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
+static void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
 {
   assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
   assert(rs1<16);
@@ -2156,7 +2062,8 @@ void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
   assert(lo<16);
   output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
 }
-void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
+
+static void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
 {
   assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
   assert(rs1<16);
@@ -2166,35 +2073,19 @@ void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
   output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
 }
 
-void emit_div(int rs)
-{
-  assem_debug("div %%%s\n",regname[rs]);
-  assert(0);
-}
-void emit_idiv(int rs)
-{
-  assem_debug("idiv %%%s\n",regname[rs]);
-  assert(0);
-}
-void emit_cdq()
-{
-  assem_debug("cdq\n");
-  assert(0);
-}
-
-void emit_clz(int rs,int rt)
+static void emit_clz(int rs,int rt)
 {
   assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
   output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
 }
 
-void emit_subcs(int rs1,int rs2,int rt)
+static void emit_subcs(int rs1,int rs2,int rt)
 {
   assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_shrcc_imm(int rs,u_int imm,int rt)
+static void emit_shrcc_imm(int rs,u_int imm,int rt)
 {
   assert(imm>0);
   assert(imm<32);
@@ -2202,7 +2093,7 @@ void emit_shrcc_imm(int rs,u_int imm,int rt)
   output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
 }
 
-void emit_shrne_imm(int rs,u_int imm,int rt)
+static void emit_shrne_imm(int rs,u_int imm,int rt)
 {
   assert(imm>0);
   assert(imm<32);
@@ -2210,73 +2101,73 @@ void emit_shrne_imm(int rs,u_int imm,int rt)
   output_w32(0x11a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
 }
 
-void emit_negmi(int rs, int rt)
+static void emit_negmi(int rs, int rt)
 {
   assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
   output_w32(0x42600000|rd_rn_rm(rt,rs,0));
 }
 
-void emit_negsmi(int rs, int rt)
+static void emit_negsmi(int rs, int rt)
 {
   assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
   output_w32(0x42700000|rd_rn_rm(rt,rs,0));
 }
 
-void emit_orreq(u_int rs1,u_int rs2,u_int rt)
+static void emit_orreq(u_int rs1,u_int rs2,u_int rt)
 {
   assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_orrne(u_int rs1,u_int rs2,u_int rt)
+static void emit_orrne(u_int rs1,u_int rs2,u_int rt)
 {
   assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
   output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
 }
 
-void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
+static void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
 {
   assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
   output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
 }
 
-void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
+static void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
 {
   assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
   output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
 }
 
-void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
+static void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
 {
   assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
   output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
 }
 
-void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
+static void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
 {
   assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
   output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
 }
 
-void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
+static void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
 {
   assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
   output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
 }
 
-void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
+static void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
 {
   assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
   output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
 }
 
-void emit_teq(int rs, int rt)
+static void emit_teq(int rs, int rt)
 {
   assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
   output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
 }
 
-void emit_rsbimm(int rs, int imm, int rt)
+static void emit_rsbimm(int rs, int imm, int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
@@ -2285,7 +2176,7 @@ void emit_rsbimm(int rs, int imm, int rt)
 }
 
 // Load 2 immediates optimizing for small code size
-void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
+static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
 {
   emit_movimm(imm1,rt1);
   u_int armval;
@@ -2301,7 +2192,7 @@ void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
 
 // Conditionally select one of two immediates, optimizing for small code size
 // This will only be called if HAVE_CMOV_IMM is defined
-void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
+static void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
 {
   u_int armval;
   if(genimm(imm2-imm1,&armval)) {
@@ -2335,13 +2226,7 @@ void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
 }
 
 // special case for checking invalid_code
-void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
-{
-  assert(0);
-}
-
-// special case for checking invalid_code
-void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
+static void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
 {
   assert(imm<128&&imm>=0);
   assert(r>=0&&r<16);
@@ -2350,14 +2235,7 @@ void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
   emit_cmpimm(HOST_TEMPREG,imm);
 }
 
-// special case for tlb mapping
-void emit_addsr12(int rs1,int rs2,int rt)
-{
-  assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
-  output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
-}
-
-void emit_callne(int a)
+static void emit_callne(int a)
 {
   assem_debug("blne %x\n",a);
   u_int offset=genjmp(a);
@@ -2365,191 +2243,21 @@ void emit_callne(int a)
 }
 
 // Used to preload hash table entries
-void emit_prefetch(void *addr)
-{
-  assem_debug("prefetch %x\n",(int)addr);
-  output_byte(0x0F);
-  output_byte(0x18);
-  output_modrm(0,5,1);
-  output_w32((int)addr);
-}
-void emit_prefetchreg(int r)
+static unused void emit_prefetchreg(int r)
 {
   assem_debug("pld %s\n",regname[r]);
   output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
 }
 
 // Special case for mini_ht
-void emit_ldreq_indexed(int rs, u_int offset, int rt)
+static void emit_ldreq_indexed(int rs, u_int offset, int rt)
 {
   assert(offset<4096);
   assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
   output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
 }
 
-void emit_flds(int r,int sr)
-{
-  assem_debug("flds s%d,[%s]\n",sr,regname[r]);
-  output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
-} 
-
-void emit_vldr(int r,int vr)
-{
-  assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
-  output_w32(0xed900b00|(vr<<12)|(r<<16));
-} 
-
-void emit_fsts(int sr,int r)
-{
-  assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
-  output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
-} 
-
-void emit_vstr(int vr,int r)
-{
-  assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
-  output_w32(0xed800b00|(vr<<12)|(r<<16));
-} 
-
-void emit_ftosizs(int s,int d)
-{
-  assem_debug("ftosizs s%d,s%d\n",d,s);
-  output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
-} 
-
-void emit_ftosizd(int s,int d)
-{
-  assem_debug("ftosizd s%d,d%d\n",d,s);
-  output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
-} 
-
-void emit_fsitos(int s,int d)
-{
-  assem_debug("fsitos s%d,s%d\n",d,s);
-  output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
-} 
-
-void emit_fsitod(int s,int d)
-{
-  assem_debug("fsitod d%d,s%d\n",d,s);
-  output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
-} 
-
-void emit_fcvtds(int s,int d)
-{
-  assem_debug("fcvtds d%d,s%d\n",d,s);
-  output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
-} 
-
-void emit_fcvtsd(int s,int d)
-{
-  assem_debug("fcvtsd s%d,d%d\n",d,s);
-  output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
-} 
-
-void emit_fsqrts(int s,int d)
-{
-  assem_debug("fsqrts d%d,s%d\n",d,s);
-  output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
-} 
-
-void emit_fsqrtd(int s,int d)
-{
-  assem_debug("fsqrtd s%d,d%d\n",d,s);
-  output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
-} 
-
-void emit_fabss(int s,int d)
-{
-  assem_debug("fabss d%d,s%d\n",d,s);
-  output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
-} 
-
-void emit_fabsd(int s,int d)
-{
-  assem_debug("fabsd s%d,d%d\n",d,s);
-  output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
-} 
-
-void emit_fnegs(int s,int d)
-{
-  assem_debug("fnegs d%d,s%d\n",d,s);
-  output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
-} 
-
-void emit_fnegd(int s,int d)
-{
-  assem_debug("fnegd s%d,d%d\n",d,s);
-  output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
-} 
-
-void emit_fadds(int s1,int s2,int d)
-{
-  assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
-  output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
-} 
-
-void emit_faddd(int s1,int s2,int d)
-{
-  assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
-  output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
-} 
-
-void emit_fsubs(int s1,int s2,int d)
-{
-  assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
-  output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
-} 
-
-void emit_fsubd(int s1,int s2,int d)
-{
-  assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
-  output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
-} 
-
-void emit_fmuls(int s1,int s2,int d)
-{
-  assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
-  output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
-} 
-
-void emit_fmuld(int s1,int s2,int d)
-{
-  assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
-  output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
-} 
-
-void emit_fdivs(int s1,int s2,int d)
-{
-  assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
-  output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
-} 
-
-void emit_fdivd(int s1,int s2,int d)
-{
-  assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
-  output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
-} 
-
-void emit_fcmps(int x,int y)
-{
-  assem_debug("fcmps s14, s15\n");
-  output_w32(0xeeb47a67);
-} 
-
-void emit_fcmpd(int x,int y)
-{
-  assem_debug("fcmpd d6, d7\n");
-  output_w32(0xeeb46b47);
-} 
-
-void emit_fmstat()
-{
-  assem_debug("fmstat\n");
-  output_w32(0xeef1fa10);
-} 
-
-void emit_bicne_imm(int rs,int imm,int rt)
+static unused void emit_bicne_imm(int rs,int imm,int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
@@ -2557,7 +2265,7 @@ void emit_bicne_imm(int rs,int imm,int rt)
   output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-void emit_biccs_imm(int rs,int imm,int rt)
+static unused void emit_biccs_imm(int rs,int imm,int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
@@ -2565,7 +2273,7 @@ void emit_biccs_imm(int rs,int imm,int rt)
   output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-void emit_bicvc_imm(int rs,int imm,int rt)
+static unused void emit_bicvc_imm(int rs,int imm,int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
@@ -2573,7 +2281,7 @@ void emit_bicvc_imm(int rs,int imm,int rt)
   output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-void emit_bichi_imm(int rs,int imm,int rt)
+static unused void emit_bichi_imm(int rs,int imm,int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
@@ -2581,7 +2289,7 @@ void emit_bichi_imm(int rs,int imm,int rt)
   output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-void emit_orrvs_imm(int rs,int imm,int rt)
+static unused void emit_orrvs_imm(int rs,int imm,int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
@@ -2589,7 +2297,7 @@ void emit_orrvs_imm(int rs,int imm,int rt)
   output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-void emit_orrne_imm(int rs,int imm,int rt)
+static void emit_orrne_imm(int rs,int imm,int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
@@ -2597,7 +2305,7 @@ void emit_orrne_imm(int rs,int imm,int rt)
   output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-void emit_andne_imm(int rs,int imm,int rt)
+static void emit_andne_imm(int rs,int imm,int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
@@ -2605,7 +2313,7 @@ void emit_andne_imm(int rs,int imm,int rt)
   output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-void emit_addpl_imm(int rs,int imm,int rt)
+static unused void emit_addpl_imm(int rs,int imm,int rt)
 {
   u_int armval;
   genimm_checked(imm,&armval);
@@ -2613,7 +2321,7 @@ void emit_addpl_imm(int rs,int imm,int rt)
   output_w32(0x52800000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-void emit_jno_unlikely(int a)
+static void emit_jno_unlikely(int a)
 {
   //emit_jno(a);
   assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
@@ -2631,6 +2339,7 @@ static void save_regs_all(u_int reglist)
   assem_debug("}\n");
   output_w32(0xe88b0000|reglist);
 }
+
 static void restore_regs_all(u_int reglist)
 {
   int i;
@@ -2642,12 +2351,14 @@ static void restore_regs_all(u_int reglist)
   assem_debug("}\n");
   output_w32(0xe89b0000|reglist);
 }
+
 // Save registers before function call
 static void save_regs(u_int reglist)
 {
   reglist&=CALLER_SAVE_REGS; // only save the caller-save registers, r0-r3, r12
   save_regs_all(reglist);
 }
+
 // Restore registers after function call
 static void restore_regs(u_int reglist)
 {
@@ -2655,37 +2366,9 @@ static void restore_regs(u_int reglist)
   restore_regs_all(reglist);
 }
 
-// Write back consts using r14 so we don't disturb the other registers
-void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
-{
-  int hr;
-  for(hr=0;hr<HOST_REGS;hr++) {
-    if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
-      if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
-        if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
-          int value=constmap[i][hr];
-          if(value==0) {
-            emit_zeroreg(HOST_TEMPREG);
-          }
-          else {
-            emit_movimm(value,HOST_TEMPREG);
-          }
-          emit_storereg(i_regmap[hr],HOST_TEMPREG);
-#ifndef FORCE32
-          if((i_is32>>i_regmap[hr])&1) {
-            if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
-            emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
-          }
-#endif
-        }
-      }
-    }
-  }
-}
-
 /* Stubs/epilogue */
 
-void literal_pool(int n)
+static void literal_pool(int n)
 {
   if(!literalcount) return;
   if(n) {
@@ -2717,7 +2400,7 @@ void literal_pool(int n)
   literalcount=0;
 }
 
-void literal_pool_jumpover(int n)
+static void literal_pool_jumpover(int n)
 {
   if(!literalcount) return;
   if(n) {
@@ -2729,10 +2412,12 @@ void literal_pool_jumpover(int n)
   set_jump_target(jaddr,(int)out);
 }
 
-emit_extjump2(u_int addr, int target, int linker)
+static void emit_extjump2(u_int addr, int target, int linker)
 {
   u_char *ptr=(u_char *)addr;
   assert((ptr[3]&0x0e)==0xa);
+  (void)ptr;
+
   emit_loadlp(target,0);
   emit_loadlp(addr,1);
   assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
@@ -2750,11 +2435,12 @@ emit_extjump2(u_int addr, int target, int linker)
   emit_jmp(linker);
 }
 
-emit_extjump(int addr, int target)
+static void emit_extjump(int addr, int target)
 {
   emit_extjump2(addr, target, (int)dyna_linker);
 }
-emit_extjump_ds(int addr, int target)
+
+static void emit_extjump_ds(int addr, int target)
 {
   emit_extjump2(addr, target, (int)dyna_linker_ds);
 }
@@ -2832,12 +2518,10 @@ static void mov_loadtype_adj(int type,int rs,int rt)
   }
 }
 
-#ifdef PCSX
 #include "pcsxmem.h"
 #include "pcsxmem_inline.c"
-#endif
 
-do_readstub(int n)
+static void do_readstub(int n)
 {
   assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
   literal_pool(256);
@@ -2848,18 +2532,13 @@ do_readstub(int n)
   struct regstat *i_regs=(struct regstat *)stubs[n][5];
   u_int reglist=stubs[n][7];
   signed char *i_regmap=i_regs->regmap;
-  int addr=get_reg(i_regmap,AGEN1+(i&1));
-  int rth,rt;
-  int ds;
+  int rt;
   if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
-    rth=get_reg(i_regmap,FTEMP|64);
     rt=get_reg(i_regmap,FTEMP);
   }else{
-    rth=get_reg(i_regmap,rt1[i]|64);
     rt=get_reg(i_regmap,rt1[i]);
   }
   assert(rs>=0);
-#ifdef PCSX
   int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
   reglist|=(1<<rs);
   for(r=0;r<=12;r++) {
@@ -2919,91 +2598,10 @@ do_readstub(int n)
     set_jump_target(restore_jump,(int)out);
   restore_regs(reglist);
   emit_jmp(stubs[n][2]); // return address
-#else // !PCSX
-  if(addr<0) addr=rt;
-  if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
-  assert(addr>=0);
-  int ftable=0;
-  if(type==LOADB_STUB||type==LOADBU_STUB)
-    ftable=(int)readmemb;
-  if(type==LOADH_STUB||type==LOADHU_STUB)
-    ftable=(int)readmemh;
-  if(type==LOADW_STUB)
-    ftable=(int)readmem;
-#ifndef FORCE32
-  if(type==LOADD_STUB)
-    ftable=(int)readmemd;
-#endif
-  assert(ftable!=0);
-  emit_writeword(rs,(int)&address);
-  //emit_pusha();
-  save_regs(reglist);
-#ifndef PCSX
-  ds=i_regs!=&regs[i];
-  int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
-  u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
-  if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
-  wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
-  if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
-#endif
-  emit_shrimm(rs,16,1);
-  int cc=get_reg(i_regmap,CCREG);
-  if(cc<0) {
-    emit_loadreg(CCREG,2);
-  }
-  emit_movimm(ftable,0);
-  emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
-#ifndef PCSX
-  emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
-#endif
-  //emit_readword((int)&last_count,temp);
-  //emit_add(cc,temp,cc);
-  //emit_writeword(cc,(int)&Count);
-  //emit_mov(15,14);
-  emit_call((int)&indirect_jump_indexed);
-  //emit_callreg(rs);
-  //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
-#ifndef PCSX
-  // We really shouldn't need to update the count here,
-  // but not doing so causes random crashes...
-  emit_readword((int)&Count,HOST_TEMPREG);
-  emit_readword((int)&next_interupt,2);
-  emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
-  emit_writeword(2,(int)&last_count);
-  emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
-  if(cc<0) {
-    emit_storereg(CCREG,HOST_TEMPREG);
-  }
-#endif
-  //emit_popa();
-  restore_regs(reglist);
-  //if((cc=get_reg(regmap,CCREG))>=0) {
-  //  emit_loadreg(CCREG,cc);
-  //}
-  if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
-    assert(rt>=0);
-    if(type==LOADB_STUB)
-      emit_movsbl((int)&readmem_dword,rt);
-    if(type==LOADBU_STUB)
-      emit_movzbl((int)&readmem_dword,rt);
-    if(type==LOADH_STUB)
-      emit_movswl((int)&readmem_dword,rt);
-    if(type==LOADHU_STUB)
-      emit_movzwl((int)&readmem_dword,rt);
-    if(type==LOADW_STUB)
-      emit_readword((int)&readmem_dword,rt);
-    if(type==LOADD_STUB) {
-      emit_readword((int)&readmem_dword,rt);
-      if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
-    }
-  }
-  emit_jmp(stubs[n][2]); // return address
-#endif // !PCSX
 }
 
-#ifdef PCSX
 // return memhandler, or get directly accessable address and return 0
-u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
+static u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
 {
   u_int l1,l2=0;
   l1=((u_int *)table)[addr>>12];
@@ -3028,16 +2626,13 @@ u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
     return l2<<1;
   }
 }
-#endif
 
-inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
+static void inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
 {
   int rs=get_reg(regmap,target);
-  int rth=get_reg(regmap,target|64);
   int rt=get_reg(regmap,target);
   if(rs<0) rs=get_reg(regmap,-1);
   assert(rs>=0);
-#ifdef PCSX
   u_int handler,host_addr=0,is_dynamic,far_call=0;
   int cc=get_reg(regmap,CCREG);
   if(pcsx_direct_read(type,addr,CLOCK_ADJUST(adj+1),cc,target?rs:-1,rt))
@@ -3111,90 +2706,9 @@ inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, i
     }
   }
   restore_regs(reglist);
-#else // if !PCSX
-  int ftable=0;
-  if(type==LOADB_STUB||type==LOADBU_STUB)
-    ftable=(int)readmemb;
-  if(type==LOADH_STUB||type==LOADHU_STUB)
-    ftable=(int)readmemh;
-  if(type==LOADW_STUB)
-    ftable=(int)readmem;
-#ifndef FORCE32
-  if(type==LOADD_STUB)
-    ftable=(int)readmemd;
-#endif
-  assert(ftable!=0);
-  if(target==0)
-    emit_movimm(addr,rs);
-  emit_writeword(rs,(int)&address);
-  //emit_pusha();
-  save_regs(reglist);
-#ifndef PCSX
-  if((signed int)addr>=(signed int)0xC0000000) {
-    // Theoretically we can have a pagefault here, if the TLB has never
-    // been enabled and the address is outside the range 80000000..BFFFFFFF
-    // Write out the registers so the pagefault can be handled.  This is
-    // a very rare case and likely represents a bug.
-    int ds=regmap!=regs[i].regmap;
-    if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
-    if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
-    else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
-  }
-#endif
-  //emit_shrimm(rs,16,1);
-  int cc=get_reg(regmap,CCREG);
-  if(cc<0) {
-    emit_loadreg(CCREG,2);
-  }
-  //emit_movimm(ftable,0);
-  emit_movimm(((u_int *)ftable)[addr>>16],0);
-  //emit_readword((int)&last_count,12);
-  emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
-#ifndef PCSX
-  if((signed int)addr>=(signed int)0xC0000000) {
-    // Pagefault address
-    int ds=regmap!=regs[i].regmap;
-    emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
-  }
-#endif
-  //emit_add(12,2,2);
-  //emit_writeword(2,(int)&Count);
-  //emit_call(((u_int *)ftable)[addr>>16]);
-  emit_call((int)&indirect_jump);
-#ifndef PCSX
-  // We really shouldn't need to update the count here,
-  // but not doing so causes random crashes...
-  emit_readword((int)&Count,HOST_TEMPREG);
-  emit_readword((int)&next_interupt,2);
-  emit_addimm(HOST_TEMPREG,-CLOCK_ADJUST(adj+1),HOST_TEMPREG);
-  emit_writeword(2,(int)&last_count);
-  emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
-  if(cc<0) {
-    emit_storereg(CCREG,HOST_TEMPREG);
-  }
-#endif
-  //emit_popa();
-  restore_regs(reglist);
-  if(rt>=0) {
-    if(type==LOADB_STUB)
-      emit_movsbl((int)&readmem_dword,rt);
-    if(type==LOADBU_STUB)
-      emit_movzbl((int)&readmem_dword,rt);
-    if(type==LOADH_STUB)
-      emit_movswl((int)&readmem_dword,rt);
-    if(type==LOADHU_STUB)
-      emit_movzwl((int)&readmem_dword,rt);
-    if(type==LOADW_STUB)
-      emit_readword((int)&readmem_dword,rt);
-    if(type==LOADD_STUB) {
-      emit_readword((int)&readmem_dword,rt);
-      if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
-    }
-  }
-#endif // !PCSX
 }
 
-do_writestub(int n)
+static void do_writestub(int n)
 {
   assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
   literal_pool(256);
@@ -3205,19 +2719,14 @@ do_writestub(int n)
   struct regstat *i_regs=(struct regstat *)stubs[n][5];
   u_int reglist=stubs[n][7];
   signed char *i_regmap=i_regs->regmap;
-  int addr=get_reg(i_regmap,AGEN1+(i&1));
-  int rth,rt,r;
-  int ds;
+  int rt,r;
   if(itype[i]==C1LS||itype[i]==C2LS) {
-    rth=get_reg(i_regmap,FTEMP|64);
     rt=get_reg(i_regmap,r=FTEMP);
   }else{
-    rth=get_reg(i_regmap,rs2[i]|64);
     rt=get_reg(i_regmap,r=rs2[i]);
   }
   assert(rs>=0);
   assert(rt>=0);
-#ifdef PCSX
   int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
   int reglist2=reglist|(1<<rs)|(1<<rt);
   for(rtmp=0;rtmp<=12;rtmp++) {
@@ -3277,89 +2786,14 @@ do_writestub(int n)
   restore_regs(reglist);
   ra=stubs[n][2];
   emit_jmp(ra);
-#else // if !PCSX
-  if(addr<0) addr=get_reg(i_regmap,-1);
-  assert(addr>=0);
-  int ftable=0;
-  if(type==STOREB_STUB)
-    ftable=(int)writememb;
-  if(type==STOREH_STUB)
-    ftable=(int)writememh;
-  if(type==STOREW_STUB)
-    ftable=(int)writemem;
-#ifndef FORCE32
-  if(type==STORED_STUB)
-    ftable=(int)writememd;
-#endif
-  assert(ftable!=0);
-  emit_writeword(rs,(int)&address);
-  //emit_shrimm(rs,16,rs);
-  //emit_movmem_indexedx4(ftable,rs,rs);
-  if(type==STOREB_STUB)
-    emit_writebyte(rt,(int)&byte);
-  if(type==STOREH_STUB)
-    emit_writehword(rt,(int)&hword);
-  if(type==STOREW_STUB)
-    emit_writeword(rt,(int)&word);
-  if(type==STORED_STUB) {
-#ifndef FORCE32
-    emit_writeword(rt,(int)&dword);
-    emit_writeword(r?rth:rt,(int)&dword+4);
-#else
-    SysPrintf("STORED_STUB\n");
-#endif
-  }
-  //emit_pusha();
-  save_regs(reglist);
-#ifndef PCSX
-  ds=i_regs!=&regs[i];
-  int real_rs=get_reg(i_regmap,rs1[i]);
-  u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
-  if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
-  wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
-  if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
-#endif
-  emit_shrimm(rs,16,1);
-  int cc=get_reg(i_regmap,CCREG);
-  if(cc<0) {
-    emit_loadreg(CCREG,2);
-  }
-  emit_movimm(ftable,0);
-  emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
-#ifndef PCSX
-  emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
-#endif
-  //emit_readword((int)&last_count,temp);
-  //emit_addimm(cc,2*stubs[n][5]+2,cc);
-  //emit_add(cc,temp,cc);
-  //emit_writeword(cc,(int)&Count);
-  emit_call((int)&indirect_jump_indexed);
-  //emit_callreg(rs);
-  emit_readword((int)&Count,HOST_TEMPREG);
-  emit_readword((int)&next_interupt,2);
-  emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
-  emit_writeword(2,(int)&last_count);
-  emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
-  if(cc<0) {
-    emit_storereg(CCREG,HOST_TEMPREG);
-  }
-  //emit_popa();
-  restore_regs(reglist);
-  //if((cc=get_reg(regmap,CCREG))>=0) {
-  //  emit_loadreg(CCREG,cc);
-  //}
-  emit_jmp(stubs[n][2]); // return address
-#endif // !PCSX
 }
 
-inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
+static void inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
 {
   int rs=get_reg(regmap,-1);
-  int rth=get_reg(regmap,target|64);
   int rt=get_reg(regmap,target);
   assert(rs>=0);
   assert(rt>=0);
-#ifdef PCSX
   u_int handler,host_addr=0;
   handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
   if (handler==0) {
@@ -3388,85 +2822,9 @@ inline_writestub(int type, int i, u_int addr, signed char regmap[], int target,
   if(cc<0)
     emit_storereg(CCREG,2);
   restore_regs(reglist);
-#else // if !pcsx
-  int ftable=0;
-  if(type==STOREB_STUB)
-    ftable=(int)writememb;
-  if(type==STOREH_STUB)
-    ftable=(int)writememh;
-  if(type==STOREW_STUB)
-    ftable=(int)writemem;
-#ifndef FORCE32
-  if(type==STORED_STUB)
-    ftable=(int)writememd;
-#endif
-  assert(ftable!=0);
-  emit_writeword(rs,(int)&address);
-  //emit_shrimm(rs,16,rs);
-  //emit_movmem_indexedx4(ftable,rs,rs);
-  if(type==STOREB_STUB)
-    emit_writebyte(rt,(int)&byte);
-  if(type==STOREH_STUB)
-    emit_writehword(rt,(int)&hword);
-  if(type==STOREW_STUB)
-    emit_writeword(rt,(int)&word);
-  if(type==STORED_STUB) {
-#ifndef FORCE32
-    emit_writeword(rt,(int)&dword);
-    emit_writeword(target?rth:rt,(int)&dword+4);
-#else
-    SysPrintf("STORED_STUB\n");
-#endif
-  }
-  //emit_pusha();
-  save_regs(reglist);
-#ifndef PCSX
-  // rearmed note: load_all_consts prevents BIOS boot, some bug?
-  if((signed int)addr>=(signed int)0xC0000000) {
-    // Theoretically we can have a pagefault here, if the TLB has never
-    // been enabled and the address is outside the range 80000000..BFFFFFFF
-    // Write out the registers so the pagefault can be handled.  This is
-    // a very rare case and likely represents a bug.
-    int ds=regmap!=regs[i].regmap;
-    if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
-    if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
-    else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
-  }
-#endif
-  //emit_shrimm(rs,16,1);
-  int cc=get_reg(regmap,CCREG);
-  if(cc<0) {
-    emit_loadreg(CCREG,2);
-  }
-  //emit_movimm(ftable,0);
-  emit_movimm(((u_int *)ftable)[addr>>16],0);
-  //emit_readword((int)&last_count,12);
-  emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
-#ifndef PCSX
-  if((signed int)addr>=(signed int)0xC0000000) {
-    // Pagefault address
-    int ds=regmap!=regs[i].regmap;
-    emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
-  }
-#endif
-  //emit_add(12,2,2);
-  //emit_writeword(2,(int)&Count);
-  //emit_call(((u_int *)ftable)[addr>>16]);
-  emit_call((int)&indirect_jump);
-  emit_readword((int)&Count,HOST_TEMPREG);
-  emit_readword((int)&next_interupt,2);
-  emit_addimm(HOST_TEMPREG,-CLOCK_ADJUST(adj+1),HOST_TEMPREG);
-  emit_writeword(2,(int)&last_count);
-  emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
-  if(cc<0) {
-    emit_storereg(CCREG,HOST_TEMPREG);
-  }
-  //emit_popa();
-  restore_regs(reglist);
-#endif
 }
 
-do_unalignedwritestub(int n)
+static void do_unalignedwritestub(int n)
 {
   assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
   literal_pool(256);
@@ -3479,7 +2837,6 @@ do_unalignedwritestub(int n)
   signed char *i_regmap=i_regs->regmap;
   int temp2=get_reg(i_regmap,FTEMP);
   int rt;
-  int ds, real_rs;
   rt=get_reg(i_regmap,rs2[i]);
   assert(rt>=0);
   assert(addr>=0);
@@ -3506,14 +2863,6 @@ do_unalignedwritestub(int n)
   emit_writeword(temp2,(int)&address);
 
   save_regs(reglist);
-#ifndef PCSX
-  ds=i_regs!=&regs[i];
-  real_rs=get_reg(i_regmap,rs1[i]);
-  u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
-  if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
-  wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
-  if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
-#endif
   emit_shrimm(addr,16,1);
   int cc=get_reg(i_regmap,CCREG);
   if(cc<0) {
@@ -3521,10 +2870,6 @@ do_unalignedwritestub(int n)
   }
   emit_movimm((u_int)readmem,0);
   emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
-#ifndef PCSX
-  // pagefault address
-  emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
-#endif
   emit_call((int)&indirect_jump_indexed);
   restore_regs(reglist);
 
@@ -3567,12 +2912,7 @@ do_unalignedwritestub(int n)
 #endif
 }
 
-void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
-{
-  printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
-}
-
-do_invstub(int n)
+static void do_invstub(int n)
 {
   literal_pool(20);
   u_int reglist=stubs[n][3];
@@ -3587,10 +2927,7 @@ do_invstub(int n)
 int do_dirty_stub(int i)
 {
   assem_debug("do_dirty_stub %x\n",start+i*4);
-  u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
-  #ifdef PCSX
-  addr=(u_int)source;
-  #endif
+  u_int addr=(u_int)source;
   // Careful about the code output here, verify_dirty needs to parse it.
   #ifndef HAVE_ARMV7
   emit_loadlp(addr,1);
@@ -3612,7 +2949,7 @@ int do_dirty_stub(int i)
   return entry;
 }
 
-void do_dirty_stub_ds()
+static void do_dirty_stub_ds()
 {
   // Careful about the code output here, verify_dirty needs to parse it.
   #ifndef HAVE_ARMV7
@@ -3630,7 +2967,7 @@ void do_dirty_stub_ds()
   emit_call((int)&verify_code_ds);
 }
 
-do_cop1stub(int n)
+static void do_cop1stub(int n)
 {
   literal_pool(256);
   assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
@@ -3651,105 +2988,9 @@ do_cop1stub(int n)
   emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
 }
 
-#ifndef DISABLE_TLB
-
-/* TLB */
-
-int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
-{
-  if(c) {
-    if((signed int)addr>=(signed int)0xC0000000) {
-      // address_generation already loaded the const
-      emit_readword_dualindexedx4(FP,map,map);
-    }
-    else
-      return -1; // No mapping
-  }
-  else {
-    assert(s!=map);
-    emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
-    emit_addsr12(map,s,map);
-    // Schedule this while we wait on the load
-    //if(x) emit_xorimm(s,x,ar);
-    if(shift>=0) emit_shlimm(s,3,shift);
-    if(~a) emit_andimm(s,a,ar);
-    emit_readword_dualindexedx4(FP,map,map);
-  }
-  return map;
-}
-int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
-{
-  if(!c||(signed int)addr>=(signed int)0xC0000000) {
-    emit_test(map,map);
-    *jaddr=(int)out;
-    emit_js(0);
-  }
-  return map;
-}
-
-int gen_tlb_addr_r(int ar, int map) {
-  if(map>=0) {
-    assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
-    output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
-  }
-}
-
-int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
-{
-  if(c) {
-    if(addr<0x80800000||addr>=0xC0000000) {
-      // address_generation already loaded the const
-      emit_readword_dualindexedx4(FP,map,map);
-    }
-    else
-      return -1; // No mapping
-  }
-  else {
-    assert(s!=map);
-    emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
-    emit_addsr12(map,s,map);
-    // Schedule this while we wait on the load
-    //if(x) emit_xorimm(s,x,ar);
-    emit_readword_dualindexedx4(FP,map,map);
-  }
-  return map;
-}
-int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
-{
-  if(!c||addr<0x80800000||addr>=0xC0000000) {
-    emit_testimm(map,0x40000000);
-    *jaddr=(int)out;
-    emit_jne(0);
-  }
-}
-
-int gen_tlb_addr_w(int ar, int map) {
-  if(map>=0) {
-    assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
-    output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
-  }
-}
-
-// Generate the address of the memory_map entry, relative to dynarec_local
-generate_map_const(u_int addr,int reg) {
-  //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
-  emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
-}
-
-#else
-
-static int do_tlb_r(int a, ...) { return 0; }
-static int do_tlb_r_branch(int a, ...) { return 0; }
-static int gen_tlb_addr_r(int a, ...) { return 0; }
-static int do_tlb_w(int a, ...) { return 0; }
-static int do_tlb_w_branch(int a, ...) { return 0; }
-static int gen_tlb_addr_w(int a, ...) { return 0; }
-
-#endif // DISABLE_TLB
-
 /* Special assem */
 
-void shift_assemble_arm(int i,struct regstat *i_regs)
+static void shift_assemble_arm(int i,struct regstat *i_regs)
 {
   if(rt1[i]) {
     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
@@ -3859,7 +3100,6 @@ void shift_assemble_arm(int i,struct regstat *i_regs)
   }
 }
 
-#ifdef PCSX
 static void speculate_mov(int rs,int rt)
 {
   if(rt!=0) {
@@ -3977,13 +3217,10 @@ static int get_ptr_mem_type(u_int a)
     return MTYPE_A000;
   return MTYPE_8000;
 }
-#endif
 
 static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
 {
-  int jaddr,type=0;
-
-#ifdef PCSX
+  int jaddr=0,type=0;
   int mr=rs1[i];
   if(((smrv_strong|smrv_weak)>>mr)&1) {
     type=get_ptr_mem_type(smrv[mr]);
@@ -4022,7 +3259,6 @@ static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
       type=0;
     }
   }
-#endif
 
   if(type==0)
   {
@@ -4046,7 +3282,7 @@ static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
 
 #define shift_assemble shift_assemble_arm
 
-void loadlr_assemble_arm(int i,struct regstat *i_regs)
+static void loadlr_assemble_arm(int i,struct regstat *i_regs)
 {
   int s,th,tl,temp,temp2,addr,map=-1;
   int offset;
@@ -4072,55 +3308,31 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs)
     c=(i_regs->wasconst>>s)&1;
     if(c) {
       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
-      if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
     }
   }
-  if(!using_tlb) {
-    if(!c) {
-      #ifdef RAM_OFFSET
-      map=get_reg(i_regs->regmap,ROREG);
-      if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
-      #endif
-      emit_shlimm(addr,3,temp);
-      if (opcode[i]==0x22||opcode[i]==0x26) {
-        emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
-      }else{
-        emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
-      }
-      jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
+  if(!c) {
+    #ifdef RAM_OFFSET
+    map=get_reg(i_regs->regmap,ROREG);
+    if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
+    #endif
+    emit_shlimm(addr,3,temp);
+    if (opcode[i]==0x22||opcode[i]==0x26) {
+      emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
+    }else{
+      emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
     }
-    else {
-      if(ram_offset&&memtarget) {
-        emit_addimm(temp2,ram_offset,HOST_TEMPREG);
-        fastload_reg_override=HOST_TEMPREG;
-      }
-      if (opcode[i]==0x22||opcode[i]==0x26) {
-        emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
-      }else{
-        emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
-      }
+    jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
+  }
+  else {
+    if(ram_offset&&memtarget) {
+      emit_addimm(temp2,ram_offset,HOST_TEMPREG);
+      fastload_reg_override=HOST_TEMPREG;
     }
-  }else{ // using tlb
-    int a;
-    if(c) {
-      a=-1;
-    }else if (opcode[i]==0x22||opcode[i]==0x26) {
-      a=0xFFFFFFFC; // LWL/LWR
+    if (opcode[i]==0x22||opcode[i]==0x26) {
+      emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
     }else{
-      a=0xFFFFFFF8; // LDL/LDR
-    }
-    map=get_reg(i_regs->regmap,TLREG);
-    assert(map>=0);
-    reglist&=~(1<<map);
-    map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
-    if(c) {
-      if (opcode[i]==0x22||opcode[i]==0x26) {
-        emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
-      }else{
-        emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
-      }
+      emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
     }
-    do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
   }
   if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
     if(!c||memtarget) {
@@ -4199,7 +3411,7 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs)
 }
 #define loadlr_assemble loadlr_assemble_arm
 
-void cop0_assemble(int i,struct regstat *i_regs)
+static void cop0_assemble(int i,struct regstat *i_regs)
 {
   if(opcode2[i]==0) // MFC0
   {
@@ -4207,23 +3419,7 @@ void cop0_assemble(int i,struct regstat *i_regs)
     char copr=(source[i]>>11)&0x1f;
     //assert(t>=0); // Why does this happen?  OOT is weird
     if(t>=0&&rt1[i]!=0) {
-#ifdef MUPEN64
-      emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
-      emit_movimm((source[i]>>11)&0x1f,1);
-      emit_writeword(0,(int)&PC);
-      emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
-      if(copr==9) {
-        emit_readword((int)&last_count,ECX);
-        emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
-        emit_add(HOST_CCREG,ECX,HOST_CCREG);
-        emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
-        emit_writeword(HOST_CCREG,(int)&Count);
-      }
-      emit_call((int)MFC0);
-      emit_readword((int)&readmem_dword,t);
-#else
       emit_readword((int)&reg_cop0+copr*4,t);
-#endif
     }
   }
   else if(opcode2[i]==4) // MTC0
@@ -4231,16 +3427,7 @@ void cop0_assemble(int i,struct regstat *i_regs)
     signed char s=get_reg(i_regs->regmap,rs1[i]);
     char copr=(source[i]>>11)&0x1f;
     assert(s>=0);
-#ifdef MUPEN64
-    emit_writeword(s,(int)&readmem_dword);
-    wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
-    emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
-    emit_movimm((source[i]>>11)&0x1f,1);
-    emit_writeword(0,(int)&PC);
-    emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
-#else
     wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
-#endif
     if(copr==9||copr==11||copr==12||copr==13) {
       emit_readword((int)&last_count,HOST_TEMPREG);
       emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
@@ -4253,7 +3440,6 @@ void cop0_assemble(int i,struct regstat *i_regs)
     // The interrupt must be taken immediately, because a subsequent
     // instruction might disable interrupts again.
     if(copr==12||copr==13) {
-#ifdef PCSX
       if (is_delayslot) {
         // burn cycles to cause cc_interrupt, which will
         // reschedule next_interupt. Relies on CCREG from above.
@@ -4267,7 +3453,6 @@ void cop0_assemble(int i,struct regstat *i_regs)
         emit_loadreg(rs1[i],s);
         return;
       }
-#endif
       emit_movimm(start+i*4+4,HOST_TEMPREG);
       emit_writeword(HOST_TEMPREG,(int)&pcaddr);
       emit_movimm(0,HOST_TEMPREG);
@@ -4275,16 +3460,12 @@ void cop0_assemble(int i,struct regstat *i_regs)
     }
     //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
     //else
-#ifdef PCSX
     if(s==HOST_CCREG)
       emit_loadreg(rs1[i],1);
     else if(s!=1)
       emit_mov(s,1);
     emit_movimm(copr,0);
     emit_call((int)pcsx_mtc0);
-#else
-    emit_call((int)MTC0);
-#endif
     if(copr==9||copr==11||copr==12||copr==13) {
       emit_readword((int)&Count,HOST_CCREG);
       emit_readword((int)&next_interupt,HOST_TEMPREG);
@@ -4307,25 +3488,6 @@ void cop0_assemble(int i,struct regstat *i_regs)
   else
   {
     assert(opcode2[i]==0x10);
-#ifndef DISABLE_TLB
-    if((source[i]&0x3f)==0x01) // TLBR
-      emit_call((int)TLBR);
-    if((source[i]&0x3f)==0x02) // TLBWI
-      emit_call((int)TLBWI_new);
-    if((source[i]&0x3f)==0x06) { // TLBWR
-      // The TLB entry written by TLBWR is dependent on the count,
-      // so update the cycle count
-      emit_readword((int)&last_count,ECX);
-      if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
-      emit_add(HOST_CCREG,ECX,HOST_CCREG);
-      emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
-      emit_writeword(HOST_CCREG,(int)&Count);
-      emit_call((int)TLBWR_new);
-    }
-    if((source[i]&0x3f)==0x08) // TLBP
-      emit_call((int)TLBP);
-#endif
-#ifdef PCSX
     if((source[i]&0x3f)==0x10) // RFE
     {
       emit_readword((int)&Status,0);
@@ -4334,15 +3496,6 @@ void cop0_assemble(int i,struct regstat *i_regs)
       emit_orrshr_imm(1,2,0);
       emit_writeword(0,(int)&Status);
     }
-#else
-    if((source[i]&0x3f)==0x18) // ERET
-    {
-      int count=ccadj[i];
-      if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
-      emit_addimm(HOST_CCREG,CLOCK_ADJUST(count),HOST_CCREG); // TODO: Should there be an extra cycle here?
-      emit_jmp((int)jump_eret);
-    }
-#endif
   }
 }
 
@@ -4445,7 +3598,7 @@ static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
   }
 }
 
-void cop2_assemble(int i,struct regstat *i_regs)
+static void cop2_assemble(int i,struct regstat *i_regs)
 {
   u_int copr=(source[i]>>11)&0x1f;
   signed char temp=get_reg(i_regs->regmap,-1);
@@ -4535,7 +3688,6 @@ static void c2op_call_rgb_func(void *func,int lm,int need_ir,int need_flags)
 
 static void c2op_assemble(int i,struct regstat *i_regs)
 {
-  signed char temp=get_reg(i_regs->regmap,-1);
   u_int c2op=source[i]&0x3f;
   u_int hr,reglist_full=0,reglist;
   int need_flags,need_ir;
@@ -4654,7 +3806,7 @@ static void c2op_assemble(int i,struct regstat *i_regs)
   }
 }
 
-void cop1_unusable(int i,struct regstat *i_regs)
+static void cop1_unusable(int i,struct regstat *i_regs)
 {
   // XXX: should just just do the exception instead
   if(!cop1_usable) {
@@ -4665,629 +3817,28 @@ void cop1_unusable(int i,struct regstat *i_regs)
   }
 }
 
-void cop1_assemble(int i,struct regstat *i_regs)
+static void cop1_assemble(int i,struct regstat *i_regs)
 {
-#ifndef DISABLE_COP1
-  // Check cop1 unusable
-  if(!cop1_usable) {
-    signed char rs=get_reg(i_regs->regmap,CSREG);
-    assert(rs>=0);
-    emit_testimm(rs,0x20000000);
-    int jaddr=(int)out;
-    emit_jeq(0);
-    add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
-    cop1_usable=1;
-  }
-  if (opcode2[i]==0) { // MFC1
-    signed char tl=get_reg(i_regs->regmap,rt1[i]);
-    if(tl>=0) {
-      emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],tl);
-      emit_readword_indexed(0,tl,tl);
-    }
-  }
-  else if (opcode2[i]==1) { // DMFC1
-    signed char tl=get_reg(i_regs->regmap,rt1[i]);
-    signed char th=get_reg(i_regs->regmap,rt1[i]|64);
-    if(tl>=0) {
-      emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],tl);
-      if(th>=0) emit_readword_indexed(4,tl,th);
-      emit_readword_indexed(0,tl,tl);
-    }
-  }
-  else if (opcode2[i]==4) { // MTC1
-    signed char sl=get_reg(i_regs->regmap,rs1[i]);
-    signed char temp=get_reg(i_regs->regmap,-1);
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],temp);
-    emit_writeword_indexed(sl,0,temp);
-  }
-  else if (opcode2[i]==5) { // DMTC1
-    signed char sl=get_reg(i_regs->regmap,rs1[i]);
-    signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
-    signed char temp=get_reg(i_regs->regmap,-1);
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],temp);
-    emit_writeword_indexed(sh,4,temp);
-    emit_writeword_indexed(sl,0,temp);
-  }
-  else if (opcode2[i]==2) // CFC1
-  {
-    signed char tl=get_reg(i_regs->regmap,rt1[i]);
-    if(tl>=0) {
-      u_int copr=(source[i]>>11)&0x1f;
-      if(copr==0) emit_readword((int)&FCR0,tl);
-      if(copr==31) emit_readword((int)&FCR31,tl);
-    }
-  }
-  else if (opcode2[i]==6) // CTC1
-  {
-    signed char sl=get_reg(i_regs->regmap,rs1[i]);
-    u_int copr=(source[i]>>11)&0x1f;
-    assert(sl>=0);
-    if(copr==31)
-    {
-      emit_writeword(sl,(int)&FCR31);
-      // Set the rounding mode
-      //FIXME
-      //char temp=get_reg(i_regs->regmap,-1);
-      //emit_andimm(sl,3,temp);
-      //emit_fldcw_indexed((int)&rounding_modes,temp);
-    }
-  }
-#else
   cop1_unusable(i, i_regs);
-#endif
 }
 
-void fconv_assemble_arm(int i,struct regstat *i_regs)
+static void fconv_assemble_arm(int i,struct regstat *i_regs)
 {
-#ifndef DISABLE_COP1
-  signed char temp=get_reg(i_regs->regmap,-1);
-  assert(temp>=0);
-  // Check cop1 unusable
-  if(!cop1_usable) {
-    signed char rs=get_reg(i_regs->regmap,CSREG);
-    assert(rs>=0);
-    emit_testimm(rs,0x20000000);
-    int jaddr=(int)out;
-    emit_jeq(0);
-    add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
-    cop1_usable=1;
-  }
-  
-  #if(defined(__VFP_FP__) && !defined(__SOFTFP__)) 
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],temp);
-    emit_flds(temp,15);
-    emit_ftosizs(15,15); // float->int, truncate
-    if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
-      emit_readword((int)&reg_cop1_simple[(source[i]>>6)&0x1f],temp);
-    emit_fsts(15,temp);
-    return;
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],temp);
-    emit_vldr(temp,7);
-    emit_ftosizd(7,13); // double->int, truncate
-    emit_readword((int)&reg_cop1_simple[(source[i]>>6)&0x1f],temp);
-    emit_fsts(13,temp);
-    return;
-  }
-  
-  if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],temp);
-    emit_flds(temp,13);
-    if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
-      emit_readword((int)&reg_cop1_simple[(source[i]>>6)&0x1f],temp);
-    emit_fsitos(13,15);
-    emit_fsts(15,temp);
-    return;
-  }
-  if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],temp);
-    emit_flds(temp,13);
-    emit_readword((int)&reg_cop1_double[(source[i]>>6)&0x1f],temp);
-    emit_fsitod(13,7);
-    emit_vstr(7,temp);
-    return;
-  }
-  
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],temp);
-    emit_flds(temp,13);
-    emit_readword((int)&reg_cop1_double[(source[i]>>6)&0x1f],temp);
-    emit_fcvtds(13,7);
-    emit_vstr(7,temp);
-    return;
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],temp);
-    emit_vldr(temp,7);
-    emit_readword((int)&reg_cop1_simple[(source[i]>>6)&0x1f],temp);
-    emit_fcvtsd(7,13);
-    emit_fsts(13,temp);
-    return;
-  }
-  #endif
-  
-  // C emulation code
-  
-  u_int hr,reglist=0;
-  for(hr=0;hr<HOST_REGS;hr++) {
-    if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
-  }
-  save_regs(reglist);
-  
-  if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_s_w);
-  }
-  if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_d_w);
-  }
-  if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_s_l);
-  }
-  if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_d_l);
-  }
-  
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_d_s);
-  }
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x24) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_w_s);
-  }
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x25) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_l_s);
-  }
-  
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_s_d);
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x24) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_w_d);
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x25) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)cvt_l_d);
-  }
-  
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x08) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)round_l_s);
-  }
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x09) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)trunc_l_s);
-  }
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0a) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)ceil_l_s);
-  }
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0b) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)floor_l_s);
-  }
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0c) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)round_w_s);
-  }
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)trunc_w_s);
-  }
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0e) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)ceil_w_s);
-  }
-  if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0f) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)floor_w_s);
-  }
-  
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x08) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)round_l_d);
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x09) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)trunc_l_d);
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0a) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)ceil_l_d);
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0b) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)floor_l_d);
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0c) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)round_w_d);
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)trunc_w_d);
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0e) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)ceil_w_d);
-  }
-  if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0f) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    emit_call((int)floor_w_d);
-  }
-  
-  restore_regs(reglist);
-#else
   cop1_unusable(i, i_regs);
-#endif
 }
 #define fconv_assemble fconv_assemble_arm
 
-void fcomp_assemble(int i,struct regstat *i_regs)
+static void fcomp_assemble(int i,struct regstat *i_regs)
 {
-#ifndef DISABLE_COP1
-  signed char fs=get_reg(i_regs->regmap,FSREG);
-  signed char temp=get_reg(i_regs->regmap,-1);
-  assert(temp>=0);
-  // Check cop1 unusable
-  if(!cop1_usable) {
-    signed char cs=get_reg(i_regs->regmap,CSREG);
-    assert(cs>=0);
-    emit_testimm(cs,0x20000000);
-    int jaddr=(int)out;
-    emit_jeq(0);
-    add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
-    cop1_usable=1;
-  }
-  
-  if((source[i]&0x3f)==0x30) {
-    emit_andimm(fs,~0x800000,fs);
-    return;
-  }
-  
-  if((source[i]&0x3e)==0x38) {
-    // sf/ngle - these should throw exceptions for NaNs
-    emit_andimm(fs,~0x800000,fs);
-    return;
-  }
-  
-  #if(defined(__VFP_FP__) && !defined(__SOFTFP__)) 
-  if(opcode2[i]==0x10) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],temp);
-    emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
-    emit_orimm(fs,0x800000,fs);
-    emit_flds(temp,14);
-    emit_flds(HOST_TEMPREG,15);
-    emit_fcmps(14,15);
-    emit_fmstat();
-    if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_s
-    if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_s
-    if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_s
-    if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_s
-    if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_s 
-    if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_s
-    if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_s
-    if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_s
-    if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_s
-    if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_s
-    if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_s
-    if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_s
-    if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_s
-    return;
-  }
-  if(opcode2[i]==0x11) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],temp);
-    emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
-    emit_orimm(fs,0x800000,fs);
-    emit_vldr(temp,6);
-    emit_vldr(HOST_TEMPREG,7);
-    emit_fcmpd(6,7);
-    emit_fmstat();
-    if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_d
-    if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_d
-    if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_d
-    if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_d
-    if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_d
-    if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_d
-    if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_d
-    if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_d
-    if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_d
-    if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_d
-    if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_d
-    if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_d
-    if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_d
-    return;
-  }
-  #endif
-  
-  // C only
-  
-  u_int hr,reglist=0;
-  for(hr=0;hr<HOST_REGS;hr++) {
-    if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
-  }
-  reglist&=~(1<<fs);
-  save_regs(reglist);
-  if(opcode2[i]==0x10) {
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
-    if((source[i]&0x3f)==0x30) emit_call((int)c_f_s);
-    if((source[i]&0x3f)==0x31) emit_call((int)c_un_s);
-    if((source[i]&0x3f)==0x32) emit_call((int)c_eq_s);
-    if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_s);
-    if((source[i]&0x3f)==0x34) emit_call((int)c_olt_s);
-    if((source[i]&0x3f)==0x35) emit_call((int)c_ult_s);
-    if((source[i]&0x3f)==0x36) emit_call((int)c_ole_s);
-    if((source[i]&0x3f)==0x37) emit_call((int)c_ule_s);
-    if((source[i]&0x3f)==0x38) emit_call((int)c_sf_s);
-    if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_s);
-    if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_s);
-    if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_s);
-    if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_s);
-    if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_s);
-    if((source[i]&0x3f)==0x3e) emit_call((int)c_le_s);
-    if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_s);
-  }
-  if(opcode2[i]==0x11) {
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
-    if((source[i]&0x3f)==0x30) emit_call((int)c_f_d);
-    if((source[i]&0x3f)==0x31) emit_call((int)c_un_d);
-    if((source[i]&0x3f)==0x32) emit_call((int)c_eq_d);
-    if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_d);
-    if((source[i]&0x3f)==0x34) emit_call((int)c_olt_d);
-    if((source[i]&0x3f)==0x35) emit_call((int)c_ult_d);
-    if((source[i]&0x3f)==0x36) emit_call((int)c_ole_d);
-    if((source[i]&0x3f)==0x37) emit_call((int)c_ule_d);
-    if((source[i]&0x3f)==0x38) emit_call((int)c_sf_d);
-    if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_d);
-    if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_d);
-    if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_d);
-    if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_d);
-    if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_d);
-    if((source[i]&0x3f)==0x3e) emit_call((int)c_le_d);
-    if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_d);
-  }
-  restore_regs(reglist);
-  emit_loadreg(FSREG,fs);
-#else
   cop1_unusable(i, i_regs);
-#endif
 }
 
-void float_assemble(int i,struct regstat *i_regs)
+static void float_assemble(int i,struct regstat *i_regs)
 {
-#ifndef DISABLE_COP1
-  signed char temp=get_reg(i_regs->regmap,-1);
-  assert(temp>=0);
-  // Check cop1 unusable
-  if(!cop1_usable) {
-    signed char cs=get_reg(i_regs->regmap,CSREG);
-    assert(cs>=0);
-    emit_testimm(cs,0x20000000);
-    int jaddr=(int)out;
-    emit_jeq(0);
-    add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
-    cop1_usable=1;
-  }
-  
-  #if(defined(__VFP_FP__) && !defined(__SOFTFP__)) 
-  if((source[i]&0x3f)==6) // mov
-  {
-    if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
-      if(opcode2[i]==0x10) {
-        emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],temp);
-        emit_readword((int)&reg_cop1_simple[(source[i]>>6)&0x1f],HOST_TEMPREG);
-        emit_readword_indexed(0,temp,temp);
-        emit_writeword_indexed(temp,0,HOST_TEMPREG);
-      }
-      if(opcode2[i]==0x11) {
-        emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],temp);
-        emit_readword((int)&reg_cop1_double[(source[i]>>6)&0x1f],HOST_TEMPREG);
-        emit_vldr(temp,7);
-        emit_vstr(7,HOST_TEMPREG);
-      }
-    }
-    return;
-  }
-  
-  if((source[i]&0x3f)>3)
-  {
-    if(opcode2[i]==0x10) {
-      emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],temp);
-      emit_flds(temp,15);
-      if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
-        emit_readword((int)&reg_cop1_simple[(source[i]>>6)&0x1f],temp);
-      }
-      if((source[i]&0x3f)==4) // sqrt
-        emit_fsqrts(15,15);
-      if((source[i]&0x3f)==5) // abs
-        emit_fabss(15,15);
-      if((source[i]&0x3f)==7) // neg
-        emit_fnegs(15,15);
-      emit_fsts(15,temp);
-    }
-    if(opcode2[i]==0x11) {
-      emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],temp);
-      emit_vldr(temp,7);
-      if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
-        emit_readword((int)&reg_cop1_double[(source[i]>>6)&0x1f],temp);
-      }
-      if((source[i]&0x3f)==4) // sqrt
-        emit_fsqrtd(7,7);
-      if((source[i]&0x3f)==5) // abs
-        emit_fabsd(7,7);
-      if((source[i]&0x3f)==7) // neg
-        emit_fnegd(7,7);
-      emit_vstr(7,temp);
-    }
-    return;
-  }
-  if((source[i]&0x3f)<4)
-  {
-    if(opcode2[i]==0x10) {
-      emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],temp);
-    }
-    if(opcode2[i]==0x11) {
-      emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],temp);
-    }
-    if(((source[i]>>11)&0x1f)!=((source[i]>>16)&0x1f)) {
-      if(opcode2[i]==0x10) {
-        emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
-        emit_flds(temp,15);
-        emit_flds(HOST_TEMPREG,13);
-        if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
-          if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
-            emit_readword((int)&reg_cop1_simple[(source[i]>>6)&0x1f],temp);
-          }
-        }
-        if((source[i]&0x3f)==0) emit_fadds(15,13,15);
-        if((source[i]&0x3f)==1) emit_fsubs(15,13,15);
-        if((source[i]&0x3f)==2) emit_fmuls(15,13,15);
-        if((source[i]&0x3f)==3) emit_fdivs(15,13,15);
-        if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
-          emit_fsts(15,HOST_TEMPREG);
-        }else{
-          emit_fsts(15,temp);
-        }
-      }
-      else if(opcode2[i]==0x11) {
-        emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
-        emit_vldr(temp,7);
-        emit_vldr(HOST_TEMPREG,6);
-        if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
-          if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
-            emit_readword((int)&reg_cop1_double[(source[i]>>6)&0x1f],temp);
-          }
-        }
-        if((source[i]&0x3f)==0) emit_faddd(7,6,7);
-        if((source[i]&0x3f)==1) emit_fsubd(7,6,7);
-        if((source[i]&0x3f)==2) emit_fmuld(7,6,7);
-        if((source[i]&0x3f)==3) emit_fdivd(7,6,7);
-        if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
-          emit_vstr(7,HOST_TEMPREG);
-        }else{
-          emit_vstr(7,temp);
-        }
-      }
-    }
-    else {
-      if(opcode2[i]==0x10) {
-        emit_flds(temp,15);
-        if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
-          emit_readword((int)&reg_cop1_simple[(source[i]>>6)&0x1f],temp);
-        }
-        if((source[i]&0x3f)==0) emit_fadds(15,15,15);
-        if((source[i]&0x3f)==1) emit_fsubs(15,15,15);
-        if((source[i]&0x3f)==2) emit_fmuls(15,15,15);
-        if((source[i]&0x3f)==3) emit_fdivs(15,15,15);
-        emit_fsts(15,temp);
-      }
-      else if(opcode2[i]==0x11) {
-        emit_vldr(temp,7);
-        if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
-          emit_readword((int)&reg_cop1_double[(source[i]>>6)&0x1f],temp);
-        }
-        if((source[i]&0x3f)==0) emit_faddd(7,7,7);
-        if((source[i]&0x3f)==1) emit_fsubd(7,7,7);
-        if((source[i]&0x3f)==2) emit_fmuld(7,7,7);
-        if((source[i]&0x3f)==3) emit_fdivd(7,7,7);
-        emit_vstr(7,temp);
-      }
-    }
-    return;
-  }
-  #endif
-  
-  u_int hr,reglist=0;
-  for(hr=0;hr<HOST_REGS;hr++) {
-    if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
-  }
-  if(opcode2[i]==0x10) { // Single precision
-    save_regs(reglist);
-    emit_readword((int)&reg_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
-    if((source[i]&0x3f)<4) {
-      emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
-      emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG3_REG);
-    }else{
-      emit_readword((int)&reg_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
-    }
-    switch(source[i]&0x3f)
-    {
-      case 0x00: emit_call((int)add_s);break;
-      case 0x01: emit_call((int)sub_s);break;
-      case 0x02: emit_call((int)mul_s);break;
-      case 0x03: emit_call((int)div_s);break;
-      case 0x04: emit_call((int)sqrt_s);break;
-      case 0x05: emit_call((int)abs_s);break;
-      case 0x06: emit_call((int)mov_s);break;
-      case 0x07: emit_call((int)neg_s);break;
-    }
-    restore_regs(reglist);
-  }
-  if(opcode2[i]==0x11) { // Double precision
-    save_regs(reglist);
-    emit_readword((int)&reg_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
-    if((source[i]&0x3f)<4) {
-      emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
-      emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG3_REG);
-    }else{
-      emit_readword((int)&reg_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
-    }
-    switch(source[i]&0x3f)
-    {
-      case 0x00: emit_call((int)add_d);break;
-      case 0x01: emit_call((int)sub_d);break;
-      case 0x02: emit_call((int)mul_d);break;
-      case 0x03: emit_call((int)div_d);break;
-      case 0x04: emit_call((int)sqrt_d);break;
-      case 0x05: emit_call((int)abs_d);break;
-      case 0x06: emit_call((int)mov_d);break;
-      case 0x07: emit_call((int)neg_d);break;
-    }
-    restore_regs(reglist);
-  }
-#else
   cop1_unusable(i, i_regs);
-#endif
 }
 
-void multdiv_assemble_arm(int i,struct regstat *i_regs)
+static void multdiv_assemble_arm(int i,struct regstat *i_regs)
 {
   //  case 0x18: MULT
   //  case 0x19: MULTU
@@ -5397,183 +3948,7 @@ void multdiv_assemble_arm(int i,struct regstat *i_regs)
       }
     }
     else // 64-bit
-#ifndef FORCE32
-    {
-      if(opcode2[i]==0x1C) // DMULT
-      {
-        assert(opcode2[i]!=0x1C);
-        signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
-        signed char m1l=get_reg(i_regs->regmap,rs1[i]);
-        signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
-        signed char m2l=get_reg(i_regs->regmap,rs2[i]);
-        assert(m1h>=0);
-        assert(m2h>=0);
-        assert(m1l>=0);
-        assert(m2l>=0);
-        emit_pushreg(m2h);
-        emit_pushreg(m2l);
-        emit_pushreg(m1h);
-        emit_pushreg(m1l);
-        emit_call((int)&mult64);
-        emit_popreg(m1l);
-        emit_popreg(m1h);
-        emit_popreg(m2l);
-        emit_popreg(m2h);
-        signed char hih=get_reg(i_regs->regmap,HIREG|64);
-        signed char hil=get_reg(i_regs->regmap,HIREG);
-        if(hih>=0) emit_loadreg(HIREG|64,hih);
-        if(hil>=0) emit_loadreg(HIREG,hil);
-        signed char loh=get_reg(i_regs->regmap,LOREG|64);
-        signed char lol=get_reg(i_regs->regmap,LOREG);
-        if(loh>=0) emit_loadreg(LOREG|64,loh);
-        if(lol>=0) emit_loadreg(LOREG,lol);
-      }
-      if(opcode2[i]==0x1D) // DMULTU
-      {
-        signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
-        signed char m1l=get_reg(i_regs->regmap,rs1[i]);
-        signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
-        signed char m2l=get_reg(i_regs->regmap,rs2[i]);
-        assert(m1h>=0);
-        assert(m2h>=0);
-        assert(m1l>=0);
-        assert(m2l>=0);
-        save_regs(CALLER_SAVE_REGS);
-        if(m1l!=0) emit_mov(m1l,0);
-        if(m1h==0) emit_readword((int)&dynarec_local,1);
-        else if(m1h>1) emit_mov(m1h,1);
-        if(m2l<2) emit_readword((int)&dynarec_local+m2l*4,2);
-        else if(m2l>2) emit_mov(m2l,2);
-        if(m2h<3) emit_readword((int)&dynarec_local+m2h*4,3);
-        else if(m2h>3) emit_mov(m2h,3);
-        emit_call((int)&multu64);
-        restore_regs(CALLER_SAVE_REGS);
-        signed char hih=get_reg(i_regs->regmap,HIREG|64);
-        signed char hil=get_reg(i_regs->regmap,HIREG);
-        signed char loh=get_reg(i_regs->regmap,LOREG|64);
-        signed char lol=get_reg(i_regs->regmap,LOREG);
-        /*signed char temp=get_reg(i_regs->regmap,-1);
-        signed char rh=get_reg(i_regs->regmap,HIREG|64);
-        signed char rl=get_reg(i_regs->regmap,HIREG);
-        assert(m1h>=0);
-        assert(m2h>=0);
-        assert(m1l>=0);
-        assert(m2l>=0);
-        assert(temp>=0);
-        //emit_mov(m1l,EAX);
-        //emit_mul(m2l);
-        emit_umull(rl,rh,m1l,m2l);
-        emit_storereg(LOREG,rl);
-        emit_mov(rh,temp);
-        //emit_mov(m1h,EAX);
-        //emit_mul(m2l);
-        emit_umull(rl,rh,m1h,m2l);
-        emit_adds(rl,temp,temp);
-        emit_adcimm(rh,0,rh);
-        emit_storereg(HIREG,rh);
-        //emit_mov(m2h,EAX);
-        //emit_mul(m1l);
-        emit_umull(rl,rh,m1l,m2h);
-        emit_adds(rl,temp,temp);
-        emit_adcimm(rh,0,rh);
-        emit_storereg(LOREG|64,temp);
-        emit_mov(rh,temp);
-        //emit_mov(m2h,EAX);
-        //emit_mul(m1h);
-        emit_umull(rl,rh,m1h,m2h);
-        emit_adds(rl,temp,rl);
-        emit_loadreg(HIREG,temp);
-        emit_adcimm(rh,0,rh);
-        emit_adds(rl,temp,rl);
-        emit_adcimm(rh,0,rh);
-        // DEBUG
-        /*
-        emit_pushreg(m2h);
-        emit_pushreg(m2l);
-        emit_pushreg(m1h);
-        emit_pushreg(m1l);
-        emit_call((int)&multu64);
-        emit_popreg(m1l);
-        emit_popreg(m1h);
-        emit_popreg(m2l);
-        emit_popreg(m2h);
-        signed char hih=get_reg(i_regs->regmap,HIREG|64);
-        signed char hil=get_reg(i_regs->regmap,HIREG);
-        if(hih>=0) emit_loadreg(HIREG|64,hih);  // DEBUG
-        if(hil>=0) emit_loadreg(HIREG,hil);  // DEBUG
-        */
-        // Shouldn't be necessary
-        //char loh=get_reg(i_regs->regmap,LOREG|64);
-        //char lol=get_reg(i_regs->regmap,LOREG);
-        //if(loh>=0) emit_loadreg(LOREG|64,loh);
-        //if(lol>=0) emit_loadreg(LOREG,lol);
-      }
-      if(opcode2[i]==0x1E) // DDIV
-      {
-        signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
-        signed char d1l=get_reg(i_regs->regmap,rs1[i]);
-        signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
-        signed char d2l=get_reg(i_regs->regmap,rs2[i]);
-        assert(d1h>=0);
-        assert(d2h>=0);
-        assert(d1l>=0);
-        assert(d2l>=0);
-        save_regs(CALLER_SAVE_REGS);
-        if(d1l!=0) emit_mov(d1l,0);
-        if(d1h==0) emit_readword((int)&dynarec_local,1);
-        else if(d1h>1) emit_mov(d1h,1);
-        if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
-        else if(d2l>2) emit_mov(d2l,2);
-        if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
-        else if(d2h>3) emit_mov(d2h,3);
-        emit_call((int)&div64);
-        restore_regs(CALLER_SAVE_REGS);
-        signed char hih=get_reg(i_regs->regmap,HIREG|64);
-        signed char hil=get_reg(i_regs->regmap,HIREG);
-        signed char loh=get_reg(i_regs->regmap,LOREG|64);
-        signed char lol=get_reg(i_regs->regmap,LOREG);
-        if(hih>=0) emit_loadreg(HIREG|64,hih);
-        if(hil>=0) emit_loadreg(HIREG,hil);
-        if(loh>=0) emit_loadreg(LOREG|64,loh);
-        if(lol>=0) emit_loadreg(LOREG,lol);
-      }
-      if(opcode2[i]==0x1F) // DDIVU
-      {
-      //u_int hr,reglist=0;
-      //for(hr=0;hr<HOST_REGS;hr++) {
-      //  if(i_regs->regmap[hr]>=0 && (i_regs->regmap[hr]&62)!=HIREG) reglist|=1<<hr;
-      //}
-        signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
-        signed char d1l=get_reg(i_regs->regmap,rs1[i]);
-        signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
-        signed char d2l=get_reg(i_regs->regmap,rs2[i]);
-        assert(d1h>=0);
-        assert(d2h>=0);
-        assert(d1l>=0);
-        assert(d2l>=0);
-        save_regs(CALLER_SAVE_REGS);
-        if(d1l!=0) emit_mov(d1l,0);
-        if(d1h==0) emit_readword((int)&dynarec_local,1);
-        else if(d1h>1) emit_mov(d1h,1);
-        if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
-        else if(d2l>2) emit_mov(d2l,2);
-        if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
-        else if(d2h>3) emit_mov(d2h,3);
-        emit_call((int)&divu64);
-        restore_regs(CALLER_SAVE_REGS);
-        signed char hih=get_reg(i_regs->regmap,HIREG|64);
-        signed char hil=get_reg(i_regs->regmap,HIREG);
-        signed char loh=get_reg(i_regs->regmap,LOREG|64);
-        signed char lol=get_reg(i_regs->regmap,LOREG);
-        if(hih>=0) emit_loadreg(HIREG|64,hih);
-        if(hil>=0) emit_loadreg(HIREG,hil);
-        if(loh>=0) emit_loadreg(LOREG|64,loh);
-        if(lol>=0) emit_loadreg(LOREG,lol);
-      }
-    }
-#else
-    assert(0);
-#endif
+      assert(0);
   }
   else
   {
@@ -5588,25 +3963,25 @@ void multdiv_assemble_arm(int i,struct regstat *i_regs)
 }
 #define multdiv_assemble multdiv_assemble_arm
 
-void do_preload_rhash(int r) {
+static void do_preload_rhash(int r) {
   // Don't need this for ARM.  On x86, this puts the value 0xf8 into the
   // register.  On ARM the hash can be done with a single instruction (below)
 }
 
-void do_preload_rhtbl(int ht) {
+static void do_preload_rhtbl(int ht) {
   emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
 }
 
-void do_rhash(int rs,int rh) {
+static void do_rhash(int rs,int rh) {
   emit_andimm(rs,0xf8,rh);
 }
 
-void do_miniht_load(int ht,int rh) {
+static void do_miniht_load(int ht,int rh) {
   assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
   output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
 }
 
-void do_miniht_jump(int rs,int rh,int ht) {
+static void do_miniht_jump(int rs,int rh,int ht) {
   emit_cmp(rh,rs);
   emit_ldreq_indexed(ht,4,15);
   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
@@ -5617,7 +3992,7 @@ void do_miniht_jump(int rs,int rh,int ht) {
   #endif
 }
 
-void do_miniht_insert(u_int return_address,int rt,int temp) {
+static void do_miniht_insert(u_int return_address,int rt,int temp) {
   #ifndef HAVE_ARMV7
   emit_movimm(return_address,rt); // PC into link register
   add_to_linker((int)out,return_address,1);
@@ -5634,36 +4009,10 @@ void do_miniht_insert(u_int return_address,int rt,int temp) {
   #endif
 }
 
-// Sign-extend to 64 bits and write out upper half of a register
-// This is useful where we have a 32-bit value in a register, and want to
-// keep it in a 32-bit register, but can't guarantee that it won't be read
-// as a 64-bit value later.
-void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
-{
-#ifndef FORCE32
-  if(is32_pre==is32) return;
-  int hr,reg;
-  for(hr=0;hr<HOST_REGS;hr++) {
-    if(hr!=EXCLUDE_REG) {
-      //if(pre[hr]==entry[hr]) {
-        if((reg=pre[hr])>=0) {
-          if((dirty>>hr)&1) {
-            if( ((is32_pre&~is32&~uu)>>reg)&1 ) {
-              emit_sarimm(hr,31,HOST_TEMPREG);
-              emit_storereg(reg|64,HOST_TEMPREG);
-            }
-          }
-        }
-      //}
-    }
-  }
-#endif
-}
-
-void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
+static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
 {
   //if(dirty_pre==dirty) return;
-  int hr,reg,new_hr;
+  int hr,reg;
   for(hr=0;hr<HOST_REGS;hr++) {
     if(hr!=EXCLUDE_REG) {
       reg=pre[hr];
@@ -5689,7 +4038,7 @@ void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,
 
 
 /* using strd could possibly help but you'd have to allocate registers in pairs
-void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
+static void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
 {
   int hr;
   int wrote=-1;
@@ -5744,9 +4093,20 @@ void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint
 #define wb_invalidate wb_invalidate_arm
 */
 
+static void mark_clear_cache(void *target)
+{
+  u_long offset = (char *)target - (char *)BASE_ADDR;
+  u_int mask = 1u << ((offset >> 12) & 31);
+  if (!(needs_clear_cache[offset >> 17] & mask)) {
+    char *start = (char *)((u_long)target & ~4095ul);
+    start_tcache_write(start, start + 4096);
+    needs_clear_cache[offset >> 17] |= mask;
+  }
+}
+
 // Clearing the cache is rather slow on ARM Linux, so mark the areas
 // that need to be cleared, and then only clear these areas once.
-void do_clear_cache()
+static void do_clear_cache()
 {
   int i,j;
   for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
@@ -5754,7 +4114,7 @@ void do_clear_cache()
     u_int bitmap=needs_clear_cache[i];
     if(bitmap) {
       u_int start,end;
-      for(j=0;j<32;j++) 
+      for(j=0;j<32;j++)
       {
         if(bitmap&(1<<j)) {
           start=(u_int)BASE_ADDR+i*131072+j*4096;
@@ -5765,7 +4125,7 @@ void do_clear_cache()
               end+=4096;
               j++;
             }else{
-              __clear_cache((void *)start,(void *)end);
+              end_tcache_write((void *)start,(void *)end);
               break;
             }
           }
@@ -5777,13 +4137,7 @@ void do_clear_cache()
 }
 
 // CPU-architecture-specific initialization
-void arch_init() {
-#ifndef DISABLE_COP1
-  rounding_modes[0]=0x0<<22; // round
-  rounding_modes[1]=0x3<<22; // trunc
-  rounding_modes[2]=0x1<<22; // ceil
-  rounding_modes[3]=0x2<<22; // floor
-#endif
+static void arch_init() {
 }
 
 // vim:shiftwidth=2:expandtab
diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index 2254638..bb6114c 100644
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -5,31 +5,10 @@
 
 #define HOST_IMM8 1
 #define HAVE_CMOV_IMM 1
-#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
-#define USE_MINI_HT 1
-//#define REG_PREFETCH 1
 #define HAVE_CONDITIONAL_CALL 1
-#define DISABLE_TLB 1
-//#define MUPEN64
-#define FORCE32 1
-#define DISABLE_COP1 1
-#define PCSX 1
 #define RAM_SIZE 0x200000
 
-#ifndef __ARM_ARCH_7A__
-//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
-//#undef USE_MINI_HT
-#endif
-
-#ifndef BASE_ADDR_FIXED
-#define BASE_ADDR_FIXED 0
-#endif
-
-#ifdef FORCE32
 #define REG_SHIFT 2
-#else
-#define REG_SHIFT 3
-#endif
 
 /* ARM calling convention:
    r0-r3, r12: caller-save
@@ -60,10 +39,19 @@ extern char *invc_ptr;
 #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
 
 // Code generator target address
-#if BASE_ADDR_FIXED
-// "round" address helpful for debug
-#define BASE_ADDR 0x1000000
+#if   defined(BASE_ADDR_FIXED)
+  // "round" address helpful for debug
+  // this produces best code, but not many platforms allow it,
+  // only use if you are sure this range is always free
+  #define BASE_ADDR 0x1000000
+  #define translation_cache (char *)BASE_ADDR
+#elif defined(BASE_ADDR_DYNAMIC)
+  // for platforms that can't just use .bss buffer, like vita
+  // otherwise better to use the next option for closer branches
+  extern char *translation_cache;
+  #define BASE_ADDR (u_int)translation_cache
 #else
-extern char translation_cache[1 << TARGET_SIZE_2];
-#define BASE_ADDR (u_int)translation_cache
+  // using a static buffer in .bss
+  extern char translation_cache[1 << TARGET_SIZE_2];
+  #define BASE_ADDR (u_int)translation_cache
 #endif
diff --git a/libpcsxcore/new_dynarec/fpu.c b/libpcsxcore/new_dynarec/fpu.c
deleted file mode 100644
index a189a53..0000000
--- a/libpcsxcore/new_dynarec/fpu.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- *   Mupen64plus - fpu.c                                                   *
- *   Copyright (C) 2010 Ari64                                              *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
- * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
-
-#include <math.h>
-
-extern int FCR0, FCR31;
-
-void cvt_s_w(int *source,float *dest)
-{
-  *dest = *source;
-}
-void cvt_d_w(int *source,double *dest)
-{
-  *dest = *source;
-}
-void cvt_s_l(long long *source,float *dest)
-{
-  *dest = *source;
-}
-void cvt_d_l(long long *source,double *dest)
-{
-  *dest = *source;
-}
-void cvt_d_s(float *source,double *dest)
-{
-  *dest = *source;
-}
-void cvt_s_d(double *source,float *dest)
-{
-  *dest = *source;
-}
-
-void round_l_s(float *source,long long *dest)
-{
-  *dest = roundf(*source);
-}
-void round_w_s(float *source,int *dest)
-{
-  *dest = roundf(*source);
-}
-void trunc_l_s(float *source,long long *dest)
-{
-  *dest = truncf(*source);
-}
-void trunc_w_s(float *source,int *dest)
-{
-  *dest = truncf(*source);
-}
-void ceil_l_s(float *source,long long *dest)
-{
-  *dest = ceilf(*source);
-}
-void ceil_w_s(float *source,int *dest)
-{
-  *dest = ceilf(*source);
-}
-void floor_l_s(float *source,long long *dest)
-{
-  *dest = floorf(*source);
-}
-void floor_w_s(float *source,int *dest)
-{
-  *dest = floorf(*source);
-}
-
-void round_l_d(double *source,long long *dest)
-{
-  *dest = round(*source);
-}
-void round_w_d(double *source,int *dest)
-{
-  *dest = round(*source);
-}
-void trunc_l_d(double *source,long long *dest)
-{
-  *dest = trunc(*source);
-}
-void trunc_w_d(double *source,int *dest)
-{
-  *dest = trunc(*source);
-}
-void ceil_l_d(double *source,long long *dest)
-{
-  *dest = ceil(*source);
-}
-void ceil_w_d(double *source,int *dest)
-{
-  *dest = ceil(*source);
-}
-void floor_l_d(double *source,long long *dest)
-{
-  *dest = floor(*source);
-}
-void floor_w_d(double *source,int *dest)
-{
-  *dest = floor(*source);
-}
-
-void cvt_w_s(float *source,int *dest)
-{
-  switch(FCR31&3)
-  {
-    case 0: round_w_s(source,dest);return;
-    case 1: trunc_w_s(source,dest);return;
-    case 2: ceil_w_s(source,dest);return;
-    case 3: floor_w_s(source,dest);return;
-  }
-}
-void cvt_w_d(double *source,int *dest)
-{
-  switch(FCR31&3)
-  {
-    case 0: round_w_d(source,dest);return;
-    case 1: trunc_w_d(source,dest);return;
-    case 2: ceil_w_d(source,dest);return;
-    case 3: floor_w_d(source,dest);return;
-  }
-}
-void cvt_l_s(float *source,long long *dest)
-{
-  switch(FCR31&3)
-  {
-    case 0: round_l_s(source,dest);return;
-    case 1: trunc_l_s(source,dest);return;
-    case 2: ceil_l_s(source,dest);return;
-    case 3: floor_l_s(source,dest);return;
-  }
-}
-void cvt_l_d(double *source,long long *dest)
-{
-  switch(FCR31&3)
-  {
-    case 0: round_l_d(source,dest);return;
-    case 1: trunc_l_d(source,dest);return;
-    case 2: ceil_l_d(source,dest);return;
-    case 3: floor_l_d(source,dest);return;
-  }
-}
-
-void c_f_s()
-{
-  FCR31 &= ~0x800000;
-}
-void c_un_s(float *source,float *target)
-{
-  FCR31=(isnan(*source) || isnan(*target)) ? FCR31|0x800000 : FCR31&~0x800000;
-}
-                          
-void c_eq_s(float *source,float *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31&=~0x800000;return;}
-  FCR31 = *source==*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ueq_s(float *source,float *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31|=0x800000;return;}
-  FCR31 = *source==*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_olt_s(float *source,float *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31&=~0x800000;return;}
-  FCR31 = *source<*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ult_s(float *source,float *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31|=0x800000;return;}
-  FCR31 = *source<*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_ole_s(float *source,float *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31&=~0x800000;return;}
-  FCR31 = *source<=*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ule_s(float *source,float *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31|=0x800000;return;}
-  FCR31 = *source<=*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_sf_s(float *source,float *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31&=~0x800000;
-}
-void c_ngle_s(float *source,float *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31&=~0x800000;
-}
-
-void c_seq_s(float *source,float *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source==*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ngl_s(float *source,float *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source==*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_lt_s(float *source,float *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source<*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_nge_s(float *source,float *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source<*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_le_s(float *source,float *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source<=*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ngt_s(float *source,float *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source<=*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_f_d()
-{
-  FCR31 &= ~0x800000;
-}
-void c_un_d(double *source,double *target)
-{
-  FCR31=(isnan(*source) || isnan(*target)) ? FCR31|0x800000 : FCR31&~0x800000;
-}
-                          
-void c_eq_d(double *source,double *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31&=~0x800000;return;}
-  FCR31 = *source==*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ueq_d(double *source,double *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31|=0x800000;return;}
-  FCR31 = *source==*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_olt_d(double *source,double *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31&=~0x800000;return;}
-  FCR31 = *source<*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ult_d(double *source,double *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31|=0x800000;return;}
-  FCR31 = *source<*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_ole_d(double *source,double *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31&=~0x800000;return;}
-  FCR31 = *source<=*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ule_d(double *source,double *target)
-{
-  if (isnan(*source) || isnan(*target)) {FCR31|=0x800000;return;}
-  FCR31 = *source<=*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_sf_d(double *source,double *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31&=~0x800000;
-}
-void c_ngle_d(double *source,double *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31&=~0x800000;
-}
-
-void c_seq_d(double *source,double *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source==*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ngl_d(double *source,double *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source==*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_lt_d(double *source,double *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source<*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_nge_d(double *source,double *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source<*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-void c_le_d(double *source,double *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source<=*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-void c_ngt_d(double *source,double *target)
-{
-  //if (isnan(*source) || isnan(*target)) // FIXME - exception
-  FCR31 = *source<=*target ? FCR31|0x800000 : FCR31&~0x800000;
-}
-
-
-void add_s(float *source1,float *source2,float *target)
-{
-  *target=(*source1)+(*source2);
-}
-void sub_s(float *source1,float *source2,float *target)
-{
-  *target=(*source1)-(*source2);
-}
-void mul_s(float *source1,float *source2,float *target)
-{
-  *target=(*source1)*(*source2);
-}
-void div_s(float *source1,float *source2,float *target)
-{
-  *target=(*source1)/(*source2);
-}
-void sqrt_s(float *source,float *target)
-{
-  *target=sqrtf(*source);
-}
-void abs_s(float *source,float *target)
-{
-  *target=fabsf(*source);
-}
-void mov_s(float *source,float *target)
-{
-  *target=*source;
-}
-void neg_s(float *source,float *target)
-{
-  *target=-(*source);
-}
-void add_d(double *source1,double *source2,double *target)
-{
-  *target=(*source1)+(*source2);
-}
-void sub_d(double *source1,double *source2,double *target)
-{
-  *target=(*source1)-(*source2);
-}
-void mul_d(double *source1,double *source2,double *target)
-{
-  *target=(*source1)*(*source2);
-}
-void div_d(double *source1,double *source2,double *target)
-{
-  *target=(*source1)/(*source2);
-}
-void sqrt_d(double *source,double *target)
-{
-  *target=sqrt(*source);
-}
-void abs_d(double *source,double *target)
-{
-  *target=fabs(*source);
-}
-void mov_d(double *source,double *target)
-{
-  *target=*source;
-}
-void neg_d(double *source,double *target)
-{
-  *target=-(*source);
-}
-
diff --git a/libpcsxcore/new_dynarec/fpu.h b/libpcsxcore/new_dynarec/fpu.h
deleted file mode 100644
index 881ddbe..0000000
--- a/libpcsxcore/new_dynarec/fpu.h
+++ /dev/null
@@ -1,74 +0,0 @@
-void cvt_s_w(int *source,float *dest);
-void cvt_d_w(int *source,double *dest);
-void cvt_s_l(long long *source,float *dest);
-void cvt_d_l(long long *source,double *dest);
-void cvt_w_s(float *source,int *dest);
-void cvt_w_d(double *source,int *dest);
-void cvt_l_s(float *source,long long *dest);
-void cvt_l_d(double *source,long long *dest);
-void cvt_d_s(float *source,double *dest);
-void cvt_s_d(double *source,float *dest);
-void round_l_s(float *source,long long *dest);
-void round_w_s(float *source,int *dest);
-void trunc_l_s(float *source,long long *dest);
-void trunc_w_s(float *source,int *dest);
-void ceil_l_s(float *source,long long *dest);
-void ceil_w_s(float *source,int *dest);
-void floor_l_s(float *source,long long *dest);
-void floor_w_s(float *source,int *dest);
-void round_l_d(double *source,long long *dest);
-void round_w_d(double *source,int *dest);
-void trunc_l_d(double *source,long long *dest);
-void trunc_w_d(double *source,int *dest);
-void ceil_l_d(double *source,long long *dest);
-void ceil_w_d(double *source,int *dest);
-void floor_l_d(double *source,long long *dest);
-void floor_w_d(double *source,int *dest);
-void c_f_s();
-void c_un_s(float *source,float *target);
-void c_eq_s(float *source,float *target);
-void c_ueq_s(float *source,float *target);
-void c_olt_s(float *source,float *target);
-void c_ult_s(float *source,float *target);
-void c_ole_s(float *source,float *target);
-void c_ule_s(float *source,float *target);
-void c_sf_s(float *source,float *target);
-void c_ngle_s(float *source,float *target);
-void c_seq_s(float *source,float *target);
-void c_ngl_s(float *source,float *target);
-void c_lt_s(float *source,float *target);
-void c_nge_s(float *source,float *target);
-void c_le_s(float *source,float *target);
-void c_ngt_s(float *source,float *target);
-void c_f_d();
-void c_un_d(double *source,double *target);
-void c_eq_d(double *source,double *target);
-void c_ueq_d(double *source,double *target);
-void c_olt_d(double *source,double *target);
-void c_ult_d(double *source,double *target);
-void c_ole_d(double *source,double *target);
-void c_ule_d(double *source,double *target);
-void c_sf_d(double *source,double *target);
-void c_ngle_d(double *source,double *target);
-void c_seq_d(double *source,double *target);
-void c_ngl_d(double *source,double *target);
-void c_lt_d(double *source,double *target);
-void c_nge_d(double *source,double *target);
-void c_le_d(double *source,double *target);
-void c_ngt_d(double *source,double *target);
-void add_s(float *source1,float *source2,float *target);
-void sub_s(float *source1,float *source2,float *target);
-void mul_s(float *source1,float *source2,float *target);
-void div_s(float *source1,float *source2,float *target);
-void sqrt_s(float *source,float *target);
-void abs_s(float *source,float *target);
-void mov_s(float *source,float *target);
-void neg_s(float *source,float *target);
-void add_d(double *source1,double *source2,double *target);
-void sub_d(double *source1,double *source2,double *target);
-void mul_d(double *source1,double *source2,double *target);
-void div_d(double *source1,double *source2,double *target);
-void sqrt_d(double *source,double *target);
-void abs_d(double *source,double *target);
-void mov_d(double *source,double *target);
-void neg_d(double *source,double *target);
diff --git a/libpcsxcore/new_dynarec/linkage_arm.S b/libpcsxcore/new_dynarec/linkage_arm.S
index 95af8b4..147b0df 100644
--- a/libpcsxcore/new_dynarec/linkage_arm.S
+++ b/libpcsxcore/new_dynarec/linkage_arm.S
@@ -20,6 +20,7 @@
  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
 
 #include "arm_features.h"
+#include "new_dynarec_config.h"
 #include "linkage_offsets.h"
 
 
@@ -160,9 +161,10 @@ ptr_hash_table:
 #endif
 .endm
 
+/* r0 = virtual target address */
+/* r1 = instruction to patch */
 .macro dyna_linker_main
-	/* r0 = virtual target address */
-	/* r1 = instruction to patch */
+#ifndef NO_WRITE_EXEC
 	load_varadr_ext r3, jump_in
 	/* get_page */
 	lsr     r2, r0, #12
@@ -242,6 +244,11 @@ ptr_hash_table:
 	str	r3, [r6, #12]
 	mov	pc, r1
 8:
+#else
+	/* XXX: should be able to do better than this... */
+	bl	get_addr_ht
+	mov	pc, r0
+#endif
 .endm
 
 
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index 65c8f03..1618b0f 100644
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -23,7 +23,18 @@
 #include <assert.h>
 #include <errno.h>
 #include <sys/mman.h>
+#ifdef __MACH__
+#include <libkern/OSCacheControl.h>
+#endif
+#ifdef _3DS
+#include <3ds_utils.h>
+#endif
+#ifdef VITA
+#include <psp2/kernel/sysmem.h>
+static int sceBlock;
+#endif
 
+#include "new_dynarec_config.h"
 #include "emu_if.h" //emulator interface
 
 //#define DISASM
@@ -42,22 +53,6 @@
 #include "assem_arm.h"
 #endif
 
-#ifdef __BLACKBERRY_QNX__
-#undef __clear_cache
-#define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
-#elif defined(__MACH__)
-#include <libkern/OSCacheControl.h>
-#define __clear_cache mach_clear_cache
-static void __clear_cache(void *start, void *end) {
-  size_t len = (char *)end - (char *)start;
-  sys_dcache_flush(start, len);
-  sys_icache_invalidate(start, len);
-}
-#elif defined(_3DS)
-#include "3ds_utils.h"
-#define __clear_cache(start,end) svcFlushProcessDataCache(0xFFFF8001, start, (u32)(end)-(u32)(start))
-#endif
-
 #define MAXBLOCK 4096
 #define MAX_OUTPUT_BLOCK_SIZE 262144
 
@@ -86,22 +81,29 @@ struct ll_entry
   struct ll_entry *next;
 };
 
-  u_int start;
-  u_int *source;
-  char insn[MAXBLOCK][10];
-  u_char itype[MAXBLOCK];
-  u_char opcode[MAXBLOCK];
-  u_char opcode2[MAXBLOCK];
-  u_char bt[MAXBLOCK];
-  u_char rs1[MAXBLOCK];
-  u_char rs2[MAXBLOCK];
-  u_char rt1[MAXBLOCK];
-  u_char rt2[MAXBLOCK];
-  u_char us1[MAXBLOCK];
-  u_char us2[MAXBLOCK];
-  u_char dep1[MAXBLOCK];
-  u_char dep2[MAXBLOCK];
-  u_char lt1[MAXBLOCK];
+  // used by asm:
+  u_char *out;
+  u_int hash_table[65536][4]  __attribute__((aligned(16)));
+  struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
+  struct ll_entry *jump_dirty[4096];
+
+  static struct ll_entry *jump_out[4096];
+  static u_int start;
+  static u_int *source;
+  static char insn[MAXBLOCK][10];
+  static u_char itype[MAXBLOCK];
+  static u_char opcode[MAXBLOCK];
+  static u_char opcode2[MAXBLOCK];
+  static u_char bt[MAXBLOCK];
+  static u_char rs1[MAXBLOCK];
+  static u_char rs2[MAXBLOCK];
+  static u_char rt1[MAXBLOCK];
+  static u_char rt2[MAXBLOCK];
+  static u_char us1[MAXBLOCK];
+  static u_char us2[MAXBLOCK];
+  static u_char dep1[MAXBLOCK];
+  static u_char dep2[MAXBLOCK];
+  static u_char lt1[MAXBLOCK];
   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
   static uint64_t gte_rt[MAXBLOCK];
   static uint64_t gte_unneeded[MAXBLOCK];
@@ -110,59 +112,47 @@ struct ll_entry
   static u_int smrv_weak; // same, but somewhat less likely
   static u_int smrv_strong_next; // same, but after current insn executes
   static u_int smrv_weak_next;
-  int imm[MAXBLOCK];
-  u_int ba[MAXBLOCK];
-  char likely[MAXBLOCK];
-  char is_ds[MAXBLOCK];
-  char ooo[MAXBLOCK];
-  uint64_t unneeded_reg[MAXBLOCK];
-  uint64_t unneeded_reg_upper[MAXBLOCK];
-  uint64_t branch_unneeded_reg[MAXBLOCK];
-  uint64_t branch_unneeded_reg_upper[MAXBLOCK];
-  uint64_t p32[MAXBLOCK];
-  uint64_t pr32[MAXBLOCK];
-  signed char regmap_pre[MAXBLOCK][HOST_REGS];
+  static int imm[MAXBLOCK];
+  static u_int ba[MAXBLOCK];
+  static char likely[MAXBLOCK];
+  static char is_ds[MAXBLOCK];
+  static char ooo[MAXBLOCK];
+  static uint64_t unneeded_reg[MAXBLOCK];
+  static uint64_t unneeded_reg_upper[MAXBLOCK];
+  static uint64_t branch_unneeded_reg[MAXBLOCK];
+  static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
+  static signed char regmap_pre[MAXBLOCK][HOST_REGS];
   static uint64_t current_constmap[HOST_REGS];
   static uint64_t constmap[MAXBLOCK][HOST_REGS];
   static struct regstat regs[MAXBLOCK];
   static struct regstat branch_regs[MAXBLOCK];
-  signed char minimum_free_regs[MAXBLOCK];
-  u_int needed_reg[MAXBLOCK];
-  uint64_t requires_32bit[MAXBLOCK];
-  u_int wont_dirty[MAXBLOCK];
-  u_int will_dirty[MAXBLOCK];
-  int ccadj[MAXBLOCK];
-  int slen;
-  u_int instr_addr[MAXBLOCK];
+  static signed char minimum_free_regs[MAXBLOCK];
+  static u_int needed_reg[MAXBLOCK];
+  static u_int wont_dirty[MAXBLOCK];
+  static u_int will_dirty[MAXBLOCK];
+  static int ccadj[MAXBLOCK];
+  static int slen;
+  static u_int instr_addr[MAXBLOCK];
   static u_int link_addr[MAXBLOCK][3];
-  int linkcount;
-  u_int stubs[MAXBLOCK*3][8];
-  int stubcount;
-  u_int literals[1024][2];
-  int literalcount;
-  int is_delayslot;
-  int cop1_usable;
-  u_char *out;
-  struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
-  struct ll_entry *jump_out[4096];
-  struct ll_entry *jump_dirty[4096];
-  u_int hash_table[65536][4]  __attribute__((aligned(16)));
-  char shadow[1048576]  __attribute__((aligned(16)));
-  void *copy;
-  int expirep;
-#ifndef PCSX
-  u_int using_tlb;
-#else
-  static const u_int using_tlb=0;
-#endif
-  int new_dynarec_did_compile;
-  int new_dynarec_hacks;
-  u_int stop_after_jal;
+  static int linkcount;
+  static u_int stubs[MAXBLOCK*3][8];
+  static int stubcount;
+  static u_int literals[1024][2];
+  static int literalcount;
+  static int is_delayslot;
+  static int cop1_usable;
+  static char shadow[1048576]  __attribute__((aligned(16)));
+  static void *copy;
+  static int expirep;
+  static u_int stop_after_jal;
 #ifndef RAM_FIXED
   static u_int ram_offset;
 #else
   static const u_int ram_offset=0;
 #endif
+
+  int new_dynarec_hacks;
+  int new_dynarec_did_compile;
   extern u_char restore_candidate[512];
   extern int cycle_count;
 
@@ -174,20 +164,20 @@ struct ll_entry
 #define CSREG 35 // Coprocessor status
 #define CCREG 36 // Cycle count
 #define INVCP 37 // Pointer to invalid_code
-#define MMREG 38 // Pointer to memory_map
+//#define MMREG 38 // Pointer to memory_map
 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 #define TEMPREG 40
 #define FTEMP 40 // FPU temporary register
 #define PTEMP 41 // Prefetch temporary register
-#define TLREG 42 // TLB mapping offset
+//#define TLREG 42 // TLB mapping offset
 #define RHASH 43 // Return address hash
 #define RHTBL 44 // Return address hash table address
 #define RTEMP 45 // JR/JALR address register
 #define MAXREG 45
 #define AGEN1 46 // Address generation temporary register
-#define AGEN2 47 // Address generation temporary register
-#define MGEN1 48 // Maptable address generation temporary register
-#define MGEN2 49 // Maptable address generation temporary register
+//#define AGEN2 47 // Address generation temporary register
+//#define MGEN1 48 // Maptable address generation temporary register
+//#define MGEN2 49 // Maptable address generation temporary register
 #define BTREG 50 // Branch target temporary register
 
   /* instruction types */
@@ -196,7 +186,7 @@ struct ll_entry
 #define STORE 2   // Store
 #define LOADLR 3  // Unaligned load
 #define STORELR 4 // Unaligned store
-#define MOV 5     // Move 
+#define MOV 5     // Move
 #define ALU 6     // Arithmetic/logic
 #define MULTDIV 7 // Multiply/divide
 #define SHIFT 8   // Shift by register
@@ -250,7 +240,6 @@ void *get_addr_ht(u_int vaddr);
 void invalidate_block(u_int block);
 void invalidate_addr(u_int addr);
 void remove_hash(int vaddr);
-void jump_vaddr();
 void dyna_linker();
 void dyna_linker_ds();
 void verify_code();
@@ -259,40 +248,86 @@ void verify_code_ds();
 void cc_interrupt();
 void fp_exception();
 void fp_exception_ds();
-void jump_syscall();
 void jump_syscall_hle();
-void jump_eret();
 void jump_hlecall();
 void jump_intcall();
 void new_dyna_leave();
 
-// TLB
-void TLBWI_new();
-void TLBWR_new();
-void read_nomem_new();
-void read_nomemb_new();
-void read_nomemh_new();
-void read_nomemd_new();
-void write_nomem_new();
-void write_nomemb_new();
-void write_nomemh_new();
-void write_nomemd_new();
-void write_rdram_new();
-void write_rdramb_new();
-void write_rdramh_new();
-void write_rdramd_new();
-extern u_int memory_map[1048576];
-
 // Needed by assembler
-void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
-void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
-void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
-void load_all_regs(signed char i_regmap[]);
-void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
-void load_regs_entry(int t);
-void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
+static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
+static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
+static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
+static void load_all_regs(signed char i_regmap[]);
+static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
+static void load_regs_entry(int t);
+static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
+
+static int verify_dirty(u_int *ptr);
+static int get_final_value(int hr, int i, int *value);
+static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e);
+static void add_to_linker(int addr,int target,int ext);
+
+static int tracedebug=0;
+
+static void mprotect_w_x(void *start, void *end, int is_x)
+{
+#ifdef NO_WRITE_EXEC
+  #if defined(VITA)
+  // *Open* enables write on all memory that was
+  // allocated by sceKernelAllocMemBlockForVM()?
+  if (is_x)
+    sceKernelCloseVMDomain();
+  else
+    sceKernelOpenVMDomain();
+  #else
+  u_long mstart = (u_long)start & ~4095ul;
+  u_long mend = (u_long)end;
+  if (mprotect((void *)mstart, mend - mstart,
+               PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
+    SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
+  #endif
+#endif
+}
+
+static void start_tcache_write(void *start, void *end)
+{
+  mprotect_w_x(start, end, 0);
+}
 
-int tracedebug=0;
+static void end_tcache_write(void *start, void *end)
+{
+#ifdef __arm__
+  size_t len = (char *)end - (char *)start;
+  #if   defined(__BLACKBERRY_QNX__)
+  msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
+  #elif defined(__MACH__)
+  sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
+  #elif defined(VITA)
+  sceKernelSyncVMDomain(sceBlock, start, len);
+  #elif defined(_3DS)
+  ctr_flush_invalidate_cache();
+  #else
+  __clear_cache(start, end);
+  #endif
+  (void)len;
+#endif
+
+  mprotect_w_x(start, end, 1);
+}
+
+static void *start_block(void)
+{
+  u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
+  if (end > (u_char *)BASE_ADDR + (1<<TARGET_SIZE_2))
+    end = (u_char *)BASE_ADDR + (1<<TARGET_SIZE_2);
+  start_tcache_write(out, end);
+  return out;
+}
+
+static void end_block(void *start)
+{
+  end_tcache_write(start, out);
+}
 
 //#define DEBUG_CYCLE_COUNT 1
 
@@ -306,87 +341,21 @@ static int CLOCK_ADJUST(int x)
   return (x * cycle_multiplier + s * 50) / 100;
 }
 
-static void tlb_hacks()
-{
-#ifndef DISABLE_TLB
-  // Goldeneye hack
-  if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
-  {
-    u_int addr;
-    int n;
-    switch (ROM_HEADER->Country_code&0xFF) 
-    {
-      case 0x45: // U
-        addr=0x34b30;
-        break;                   
-      case 0x4A: // J 
-        addr=0x34b70;    
-        break;    
-      case 0x50: // E 
-        addr=0x329f0;
-        break;                        
-      default: 
-        // Unknown country code
-        addr=0;
-        break;
-    }
-    u_int rom_addr=(u_int)rom;
-    #ifdef ROM_COPY
-    // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
-    // in the lower 4G of memory to use this hack.  Copy it if necessary.
-    if((void *)rom>(void *)0xffffffff) {
-      munmap(ROM_COPY, 67108864);
-      if(mmap(ROM_COPY, 12582912,
-              PROT_READ | PROT_WRITE,
-              MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
-              -1, 0) <= 0) {printf("mmap() failed\n");}
-      memcpy(ROM_COPY,rom,12582912);
-      rom_addr=(u_int)ROM_COPY;
-    }
-    #endif
-    if(addr) {
-      for(n=0x7F000;n<0x80000;n++) {
-        memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
-      }
-    }
-  }
-#endif
-}
-
 static u_int get_page(u_int vaddr)
 {
-#ifndef PCSX
-  u_int page=(vaddr^0x80000000)>>12;
-#else
   u_int page=vaddr&~0xe0000000;
   if (page < 0x1000000)
     page &= ~0x0e00000; // RAM mirrors
   page>>=12;
-#endif
-#ifndef DISABLE_TLB
-  if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
-#endif
   if(page>2048) page=2048+(page&2047);
   return page;
 }
 
-#ifndef PCSX
-static u_int get_vpage(u_int vaddr)
-{
-  u_int vpage=(vaddr^0x80000000)>>12;
-#ifndef DISABLE_TLB
-  if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
-#endif
-  if(vpage>2048) vpage=2048+(vpage&2047);
-  return vpage;
-}
-#else
 // no virtual mem in PCSX
 static u_int get_vpage(u_int vaddr)
 {
   return get_page(vaddr);
 }
-#endif
 
 // Get address from virtual address
 // This is called from the recompiled JR/JALR instructions
@@ -400,10 +369,10 @@ void *get_addr(u_int vaddr)
   while(head!=NULL) {
     if(head->vaddr==vaddr) {
   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
-      int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
+      u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
       ht_bin[3]=ht_bin[1];
       ht_bin[2]=ht_bin[0];
-      ht_bin[1]=(int)head->addr;
+      ht_bin[1]=(u_int)head->addr;
       ht_bin[0]=vaddr;
       return head->addr;
     }
@@ -419,22 +388,13 @@ void *get_addr(u_int vaddr)
         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
         invalid_code[vaddr>>12]=0;
         inv_code_start=inv_code_end=~0;
-#ifndef DISABLE_TLB
-        memory_map[vaddr>>12]|=0x40000000;
-#endif
         if(vpage<2048) {
-#ifndef DISABLE_TLB
-          if(tlb_LUT_r[vaddr>>12]) {
-            invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
-            memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
-          }
-#endif
           restore_candidate[vpage>>3]|=1<<(vpage&7);
         }
         else restore_candidate[page>>3]|=1<<(page&7);
-        int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
+        u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
         if(ht_bin[0]==vaddr) {
-          ht_bin[1]=(int)head->addr; // Replace existing entry
+          ht_bin[1]=(u_int)head->addr; // Replace existing entry
         }
         else
         {
@@ -464,7 +424,7 @@ void *get_addr(u_int vaddr)
 void *get_addr_ht(u_int vaddr)
 {
   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
-  int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
+  u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
   return get_addr(vaddr);
@@ -526,7 +486,7 @@ static void flush_dirty_uppers(struct regstat *cur)
   for (hr=0;hr<HOST_REGS;hr++) {
     if((cur->dirty>>hr)&1) {
       reg=cur->regmap[hr];
-      if(reg>=64) 
+      if(reg>=64)
         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
     }
   }
@@ -665,10 +625,6 @@ void lsn(u_char hsn[], int i, int *preferred_reg)
   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
     hsn[FTEMP]=0;
   }
-  // Don't remove the TLB registers either
-  if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
-    hsn[TLREG]=0;
-  }
   // Don't remove the miniht registers
   if(itype[i]==UJUMP||itype[i]==RJUMP)
   {
@@ -683,7 +639,7 @@ int needed_again(int r, int i)
   int j;
   int b=-1;
   int rn=10;
-  
+
   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
   {
     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
@@ -736,6 +692,7 @@ int needed_again(int r, int i)
     }
   }*/
   if(rn<10) return 1;
+  (void)b;
   return 0;
 }
 
@@ -786,7 +743,7 @@ int loop_reg(int i, int r, int hr)
 void alloc_all(struct regstat *cur,int i)
 {
   int hr;
-  
+
   for(hr=0;hr<HOST_REGS;hr++) {
     if(hr!=EXCLUDE_REG) {
       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
@@ -805,119 +762,6 @@ void alloc_all(struct regstat *cur,int i)
   }
 }
 
-#ifndef FORCE32
-void div64(int64_t dividend,int64_t divisor)
-{
-  lo=dividend/divisor;
-  hi=dividend%divisor;
-  //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
-  //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
-}
-void divu64(uint64_t dividend,uint64_t divisor)
-{
-  lo=dividend/divisor;
-  hi=dividend%divisor;
-  //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
-  //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
-}
-
-void mult64(uint64_t m1,uint64_t m2)
-{
-   unsigned long long int op1, op2, op3, op4;
-   unsigned long long int result1, result2, result3, result4;
-   unsigned long long int temp1, temp2, temp3, temp4;
-   int sign = 0;
-   
-   if (m1 < 0)
-     {
-    op2 = -m1;
-    sign = 1 - sign;
-     }
-   else op2 = m1;
-   if (m2 < 0)
-     {
-    op4 = -m2;
-    sign = 1 - sign;
-     }
-   else op4 = m2;
-   
-   op1 = op2 & 0xFFFFFFFF;
-   op2 = (op2 >> 32) & 0xFFFFFFFF;
-   op3 = op4 & 0xFFFFFFFF;
-   op4 = (op4 >> 32) & 0xFFFFFFFF;
-   
-   temp1 = op1 * op3;
-   temp2 = (temp1 >> 32) + op1 * op4;
-   temp3 = op2 * op3;
-   temp4 = (temp3 >> 32) + op2 * op4;
-   
-   result1 = temp1 & 0xFFFFFFFF;
-   result2 = temp2 + (temp3 & 0xFFFFFFFF);
-   result3 = (result2 >> 32) + temp4;
-   result4 = (result3 >> 32);
-   
-   lo = result1 | (result2 << 32);
-   hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
-   if (sign)
-     {
-    hi = ~hi;
-    if (!lo) hi++;
-    else lo = ~lo + 1;
-     }
-}
-
-void multu64(uint64_t m1,uint64_t m2)
-{
-   unsigned long long int op1, op2, op3, op4;
-   unsigned long long int result1, result2, result3, result4;
-   unsigned long long int temp1, temp2, temp3, temp4;
-   
-   op1 = m1 & 0xFFFFFFFF;
-   op2 = (m1 >> 32) & 0xFFFFFFFF;
-   op3 = m2 & 0xFFFFFFFF;
-   op4 = (m2 >> 32) & 0xFFFFFFFF;
-   
-   temp1 = op1 * op3;
-   temp2 = (temp1 >> 32) + op1 * op4;
-   temp3 = op2 * op3;
-   temp4 = (temp3 >> 32) + op2 * op4;
-   
-   result1 = temp1 & 0xFFFFFFFF;
-   result2 = temp2 + (temp3 & 0xFFFFFFFF);
-   result3 = (result2 >> 32) + temp4;
-   result4 = (result3 >> 32);
-   
-   lo = result1 | (result2 << 32);
-   hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
-   
-  //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
-  //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
-}
-
-uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
-{
-  if(bits) {
-    original<<=64-bits;
-    original>>=64-bits;
-    loaded<<=bits;
-    original|=loaded;
-  }
-  else original=loaded;
-  return original;
-}
-uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
-{
-  if(bits^56) {
-    original>>=64-(bits^56);
-    original<<=64-(bits^56);
-    loaded>>=bits^56;
-    original|=loaded;
-  }
-  else original=loaded;
-  return original;
-}
-#endif
-
 #ifdef __i386__
 #include "assem_x86.c"
 #endif
@@ -996,7 +840,7 @@ void *check_addr(u_int vaddr)
 void remove_hash(int vaddr)
 {
   //printf("remove hash: %x\n",vaddr);
-  int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
+  u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
   if(ht_bin[2]==vaddr) {
     ht_bin[2]=ht_bin[3]=-1;
   }
@@ -1011,7 +855,7 @@ void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
 {
   struct ll_entry *next;
   while(*head) {
-    if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || 
+    if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
     {
       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
@@ -1032,7 +876,7 @@ void ll_clear(struct ll_entry **head)
 {
   struct ll_entry *cur;
   struct ll_entry *next;
-  if(cur=*head) {
+  if((cur=*head)) {
     *head=0;
     while(cur) {
       next=cur->next;
@@ -1043,7 +887,7 @@ void ll_clear(struct ll_entry **head)
 }
 
 // Dereference the pointers and remove if it matches
-void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
+static void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
 {
   while(head) {
     int ptr=get_pointer(head->addr);
@@ -1052,10 +896,11 @@ void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
     {
       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
-      u_int host_addr=(u_int)kill_pointer(head->addr);
+      void *host_addr=find_extjump_insn(head->addr);
       #ifdef __arm__
-        needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
+        mark_clear_cache(host_addr);
       #endif
+      set_jump_target((int)host_addr,(int)head->addr);
     }
     head=head->next;
   }
@@ -1079,10 +924,11 @@ void invalidate_page(u_int page)
   jump_out[page]=0;
   while(head!=NULL) {
     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
-    u_int host_addr=(u_int)kill_pointer(head->addr);
+    void *host_addr=find_extjump_insn(head->addr);
     #ifdef __arm__
-      needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
+      mark_clear_cache(host_addr);
     #endif
+    set_jump_target((int)host_addr,(int)head->addr);
     next=head->next;
     free(head);
     head=next;
@@ -1107,21 +953,9 @@ static void invalidate_block_range(u_int block, u_int first, u_int last)
   #ifdef __arm__
     do_clear_cache();
   #endif
-  
+
   // Don't trap writes
   invalid_code[block]=1;
-#ifndef DISABLE_TLB
-  // If there is a valid TLB entry for this page, remove write protect
-  if(tlb_LUT_w[block]) {
-    assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
-    // CHECK: Is this right?
-    memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
-    u_int real_block=tlb_LUT_w[block]>>12;
-    invalid_code[real_block]=1;
-    if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
-  }
-  else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
-#endif
 
   #ifdef USE_MINI_HT
   memset(mini_ht,-1,sizeof(mini_ht));
@@ -1150,14 +984,6 @@ void invalidate_block(u_int block)
           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
         }
       }
-#ifndef DISABLE_TLB
-      if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
-        if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
-          if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
-          if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
-        }
-      }
-#endif
     }
     head=head->next;
   }
@@ -1166,7 +992,6 @@ void invalidate_block(u_int block)
 
 void invalidate_addr(u_int addr)
 {
-#ifdef PCSX
   //static int rhits;
   // this check is done by the caller
   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
@@ -1220,7 +1045,6 @@ void invalidate_addr(u_int addr)
       return;
     }
   }
-#endif
   invalidate_block(addr>>12);
 }
 
@@ -1228,7 +1052,7 @@ void invalidate_addr(u_int addr)
 // Anything could have changed, so invalidate everything.
 void invalidate_all_pages()
 {
-  u_int page,n;
+  u_int page;
   for(page=0;page<4096;page++)
     invalidate_page(page);
   for(page=0;page<1048576;page++)
@@ -1236,25 +1060,9 @@ void invalidate_all_pages()
       restore_candidate[(page&2047)>>3]|=1<<(page&7);
       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
     }
-  #ifdef __arm__
-  __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
-  #endif
   #ifdef USE_MINI_HT
   memset(mini_ht,-1,sizeof(mini_ht));
   #endif
-  #ifndef DISABLE_TLB
-  // TLB
-  for(page=0;page<0x100000;page++) {
-    if(tlb_LUT_r[page]) {
-      memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
-      if(!tlb_LUT_w[page]||!invalid_code[page])
-        memory_map[page]|=0x40000000; // Write protect
-    }
-    else memory_map[page]=-1;
-    if(page==0x80000) page=0xC0000;
-  }
-  tlb_hacks();
-  #endif
 }
 
 // Add an entry to jump_out after making a link
@@ -1264,6 +1072,7 @@ void add_link(u_int vaddr,void *src)
   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
   int *ptr=(int *)(src+4);
   assert((*ptr&0x0fff0000)==0x059f0000);
+  (void)ptr;
   ll_add(jump_out+page,vaddr,src);
   //int ptr=get_pointer(src);
   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
@@ -1283,7 +1092,7 @@ void clean_blocks(u_int page)
       // Don't restore blocks which are about to expire from the cache
       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
         u_int start,end;
-        if(verify_dirty((int)head->addr)) {
+        if(verify_dirty(head->addr)) {
           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
           u_int i;
           u_int inv=0;
@@ -1293,13 +1102,6 @@ void clean_blocks(u_int page)
               inv|=invalid_code[i];
             }
           }
-#ifndef DISABLE_TLB
-          if((signed int)head->vaddr>=(signed int)0xC0000000) {
-            u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
-            //printf("addr=%x start=%x end=%x\n",addr,start,end);
-            if(addr<start||addr>=end) inv=1;
-          }
-#endif
           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
             inv=1;
           }
@@ -1307,19 +1109,16 @@ void clean_blocks(u_int page)
             void * clean_addr=(void *)get_clean_addr((int)head->addr);
             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
               u_int ppage=page;
-#ifndef DISABLE_TLB
-              if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
-#endif
               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
               //printf("page=%x, addr=%x\n",page,head->vaddr);
               //assert(head->vaddr>>12==(page|0x80000));
               ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
-              int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
+              u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
               if(ht_bin[0]==head->vaddr) {
-                ht_bin[1]=(int)clean_addr; // Replace existing entry
+                ht_bin[1]=(u_int)clean_addr; // Replace existing entry
               }
               if(ht_bin[2]==head->vaddr) {
-                ht_bin[3]=(int)clean_addr; // Replace existing entry
+                ht_bin[3]=(u_int)clean_addr; // Replace existing entry
               }
             }
           }
@@ -1646,8 +1445,6 @@ void load_alloc(struct regstat *current,int i)
     }
     else current->is32|=1LL<<rt1[i];
     dirty_reg(current,rt1[i]);
-    // If using TLB, need a register for pointer to the mapping table
-    if(using_tlb) alloc_reg(current,i,TLREG);
     // LWL/LWR need a temporary register for the old value
     if(opcode[i]==0x22||opcode[i]==0x26)
     {
@@ -1664,8 +1461,6 @@ void load_alloc(struct regstat *current,int i)
     {
       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
     }
-    // If using TLB, need a register for pointer to the mapping table
-    if(using_tlb) alloc_reg(current,i,TLREG);
     alloc_reg_temp(current,i,-1);
     minimum_free_regs[i]=1;
     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
@@ -1687,8 +1482,6 @@ void store_alloc(struct regstat *current,int i)
     alloc_reg64(current,i,rs2[i]);
     if(rs2[i]) alloc_reg(current,i,FTEMP);
   }
-  // If using TLB, need a register for pointer to the mapping table
-  if(using_tlb) alloc_reg(current,i,TLREG);
   #if defined(HOST_IMM8)
   // On CPUs without 32-bit immediates we need a pointer to invalid_code
   else alloc_reg(current,i,INVCP);
@@ -1711,8 +1504,6 @@ void c1ls_alloc(struct regstat *current,int i)
   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
     alloc_reg64(current,i,FTEMP);
   }
-  // If using TLB, need a register for pointer to the mapping table
-  if(using_tlb) alloc_reg(current,i,TLREG);
   #if defined(HOST_IMM8)
   // On CPUs without 32-bit immediates we need a pointer to invalid_code
   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
@@ -1727,11 +1518,9 @@ void c2ls_alloc(struct regstat *current,int i)
   clear_const(current,rt1[i]);
   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
   alloc_reg(current,i,FTEMP);
-  // If using TLB, need a register for pointer to the mapping table
-  if(using_tlb) alloc_reg(current,i,TLREG);
   #if defined(HOST_IMM8)
   // On CPUs without 32-bit immediates we need a pointer to invalid_code
-  else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
+  if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
     alloc_reg(current,i,INVCP);
   #endif
   // We need a temporary register for address generation
@@ -2024,7 +1813,7 @@ static void pagespan_alloc(struct regstat *current,int i)
   //else ...
 }
 
-add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
+static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
 {
   stubs[stubcount][0]=type;
   stubs[stubcount][1]=addr;
@@ -2047,12 +1836,6 @@ void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32
         if((dirty>>hr)&1) {
           if(regmap[hr]<64) {
             emit_storereg(r,hr);
-#ifndef FORCE32
-            if((is32>>regmap[hr])&1) {
-              emit_sarimm(hr,31,hr);
-              emit_storereg(r|64,hr);
-            }
-#endif
           }else{
             emit_storereg(r|64,hr);
           }
@@ -2090,12 +1873,6 @@ void rlist()
   for(i=0;i<32;i++)
     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
   printf("\n");
-#ifndef DISABLE_COP1
-  printf("TRACE: ");
-  for(i=0;i<32;i++)
-    printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
-  printf("\n");
-#endif
 }
 
 void enabletrace()
@@ -2129,11 +1906,6 @@ void memdebug(int i)
   //printf("TRACE: %x\n",(&i)[-1]);
 }
 
-void tlb_debug(u_int cause, u_int addr, u_int iaddr)
-{
-  printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
-}
-
 void alu_assemble(int i,struct regstat *i_regs)
 {
   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
@@ -2620,23 +2392,25 @@ void imm16_assemble(int i,struct regstat *i_regs)
                 emit_mov(sh,th);
               }
             }
-            if(opcode[i]==0x0d) //ORI
-            if(sl<0) {
-              emit_orimm(tl,imm[i],tl);
-            }else{
-              if(!((i_regs->wasconst>>sl)&1))
-                emit_orimm(sl,imm[i],tl);
-              else
-                emit_movimm(constmap[i][sl]|imm[i],tl);
+            if(opcode[i]==0x0d) { // ORI
+              if(sl<0) {
+                emit_orimm(tl,imm[i],tl);
+              }else{
+                if(!((i_regs->wasconst>>sl)&1))
+                  emit_orimm(sl,imm[i],tl);
+                else
+                  emit_movimm(constmap[i][sl]|imm[i],tl);
+              }
             }
-            if(opcode[i]==0x0e) //XORI
-            if(sl<0) {
-              emit_xorimm(tl,imm[i],tl);
-            }else{
-              if(!((i_regs->wasconst>>sl)&1))
-                emit_xorimm(sl,imm[i],tl);
-              else
-                emit_movimm(constmap[i][sl]^imm[i],tl);
+            if(opcode[i]==0x0e) { // XORI
+              if(sl<0) {
+                emit_xorimm(tl,imm[i],tl);
+              }else{
+                if(!((i_regs->wasconst>>sl)&1))
+                  emit_xorimm(sl,imm[i],tl);
+                else
+                  emit_movimm(constmap[i][sl]^imm[i],tl);
+              }
             }
           }
           else {
@@ -2815,14 +2589,12 @@ void load_assemble(int i,struct regstat *i_regs)
     c=(i_regs->wasconst>>s)&1;
     if (c) {
       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
-      if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
     }
   }
   //printf("load_assemble: c=%d\n",c);
   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
   // FIXME: Even if the load is a NOP, we should check for pagefaults...
-#ifdef PCSX
-  if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
+  if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
     ||rt1[i]==0) {
       // could be FIFO, must perform the read
       // ||dummy read
@@ -2830,7 +2602,6 @@ void load_assemble(int i,struct regstat *i_regs)
       tl=get_reg(i_regs->regmap,-1);
       assert(tl>=0);
   }
-#endif
   if(offset||s<0||c) addr=tl;
   else addr=s;
   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
@@ -2840,34 +2611,22 @@ void load_assemble(int i,struct regstat *i_regs)
   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
   reglist&=~(1<<tl);
   if(th>=0) reglist&=~(1<<th);
-  if(!using_tlb) {
-    if(!c) {
-      #ifdef RAM_OFFSET
-      map=get_reg(i_regs->regmap,ROREG);
-      if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
-      #endif
-//#define R29_HACK 1
-      #ifdef R29_HACK
-      // Strmnnrmn's speed hack
-      if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
-      #endif
-      {
-        jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
-      }
+  if(!c) {
+    #ifdef RAM_OFFSET
+    map=get_reg(i_regs->regmap,ROREG);
+    if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
+    #endif
+    #ifdef R29_HACK
+    // Strmnnrmn's speed hack
+    if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
+    #endif
+    {
+      jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
     }
-    else if(ram_offset&&memtarget) {
-      emit_addimm(addr,ram_offset,HOST_TEMPREG);
-      fastload_reg_override=HOST_TEMPREG;
-    }
-  }else{ // using tlb
-    int x=0;
-    if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
-    if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
-    map=get_reg(i_regs->regmap,TLREG);
-    assert(map>=0);
-    reglist&=~(1<<map);
-    map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
-    do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
+  }
+  else if(ram_offset&&memtarget) {
+    emit_addimm(addr,ram_offset,HOST_TEMPREG);
+    fastload_reg_override=HOST_TEMPREG;
   }
   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
   if (opcode[i]==0x20) { // LB
@@ -2880,7 +2639,6 @@ void load_assemble(int i,struct regstat *i_regs)
         #endif
         {
           //emit_xorimm(addr,3,tl);
-          //gen_tlb_addr_r(tl,map);
           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
           int x=0,a=tl;
 #ifdef BIG_ENDIAN_MIPS
@@ -2921,7 +2679,6 @@ void load_assemble(int i,struct regstat *i_regs)
           //emit_movswl_indexed_tlb(x,tl,map,tl);
           //else
           if(map>=0) {
-            gen_tlb_addr_r(a,map);
             emit_movswl_indexed(x,a,tl);
           }else{
             #if 1 //def RAM_OFFSET
@@ -2967,7 +2724,6 @@ void load_assemble(int i,struct regstat *i_regs)
         #endif
         {
           //emit_xorimm(addr,3,tl);
-          //gen_tlb_addr_r(tl,map);
           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
           int x=0,a=tl;
 #ifdef BIG_ENDIAN_MIPS
@@ -3008,7 +2764,6 @@ void load_assemble(int i,struct regstat *i_regs)
           //emit_movzwl_indexed_tlb(x,tl,map,tl);
           //#else
           if(map>=0) {
-            gen_tlb_addr_r(a,map);
             emit_movzwl_indexed(x,a,tl);
           }else{
             #if 1 //def RAM_OFFSET
@@ -3052,7 +2807,6 @@ void load_assemble(int i,struct regstat *i_regs)
       if(!dummy) {
         int a=addr;
         if(fastload_reg_override) a=fastload_reg_override;
-        //gen_tlb_addr_r(tl,map);
         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
         #ifdef HOST_IMM_ADDR32
@@ -3097,7 +2851,7 @@ void load_assemble(int i,struct regstat *i_regs)
     emit_call((int)memdebug);
     //emit_popa();
     restore_regs(0x100f);
-  }/**/
+  }*/
 }
 
 #ifndef loadlr_assemble
@@ -3113,7 +2867,7 @@ void store_assemble(int i,struct regstat *i_regs)
   int s,th,tl,map=-1;
   int addr,temp;
   int offset;
-  int jaddr=0,jaddr2,type;
+  int jaddr=0,type;
   int memtarget=0,c=0;
   int agr=AGEN1+(i&1);
   int faststore_reg_override=0;
@@ -3128,7 +2882,6 @@ void store_assemble(int i,struct regstat *i_regs)
     c=(i_regs->wasconst>>s)&1;
     if(c) {
       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
-      if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
     }
   }
   assert(tl>=0);
@@ -3139,48 +2892,12 @@ void store_assemble(int i,struct regstat *i_regs)
   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
   if(offset||s<0||c) addr=temp;
   else addr=s;
-  if(!using_tlb) {
-    if(!c) {
-      #ifndef PCSX
-      #ifdef R29_HACK
-      // Strmnnrmn's speed hack
-      if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
-      #endif
-      emit_cmpimm(addr,RAM_SIZE);
-      #ifdef DESTRUCTIVE_SHIFT
-      if(s==addr) emit_mov(s,temp);
-      #endif
-      #ifdef R29_HACK
-      memtarget=1;
-      if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
-      #endif
-      {
-        jaddr=(int)out;
-        #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
-        // Hint to branch predictor that the branch is unlikely to be taken
-        if(rs1[i]>=28)
-          emit_jno_unlikely(0);
-        else
-        #endif
-        emit_jno(0);
-      }
-      #else
-        jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
-      #endif
-    }
-    else if(ram_offset&&memtarget) {
-      emit_addimm(addr,ram_offset,HOST_TEMPREG);
-      faststore_reg_override=HOST_TEMPREG;
-    }
-  }else{ // using tlb
-    int x=0;
-    if (opcode[i]==0x28) x=3; // SB
-    if (opcode[i]==0x29) x=2; // SH
-    map=get_reg(i_regs->regmap,TLREG);
-    assert(map>=0);
-    reglist&=~(1<<map);
-    map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
-    do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
+  if(!c) {
+    jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
+  }
+  else if(ram_offset&&memtarget) {
+    emit_addimm(addr,ram_offset,HOST_TEMPREG);
+    faststore_reg_override=HOST_TEMPREG;
   }
 
   if (opcode[i]==0x28) { // SB
@@ -3193,7 +2910,6 @@ void store_assemble(int i,struct regstat *i_regs)
       if(!c) a=addr;
 #endif
       if(faststore_reg_override) a=faststore_reg_override;
-      //gen_tlb_addr_w(temp,map);
       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
       emit_writebyte_indexed_tlb(tl,x,a,map,a);
     }
@@ -3213,7 +2929,6 @@ void store_assemble(int i,struct regstat *i_regs)
       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
       //#else
       if(map>=0) {
-        gen_tlb_addr_w(a,map);
         emit_writehword_indexed(tl,x,a);
       }else
         //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
@@ -3248,15 +2963,13 @@ void store_assemble(int i,struct regstat *i_regs)
     }
     type=STORED_STUB;
   }
-#ifdef PCSX
   if(jaddr) {
     // PCSX store handlers don't check invcode again
     reglist|=1<<addr;
     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
     jaddr=0;
   }
-#endif
-  if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
+  if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
     if(!c||memtarget) {
       #ifdef DESTRUCTIVE_SHIFT
       // The x86 shift operation is 'destructive'; it overwrites the
@@ -3273,7 +2986,7 @@ void store_assemble(int i,struct regstat *i_regs)
       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
       emit_callne(invalidate_addr_reg[addr]);
       #else
-      jaddr2=(int)out;
+      int jaddr2=(int)out;
       emit_jne(0);
       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
       #endif
@@ -3334,16 +3047,16 @@ void store_assemble(int i,struct regstat *i_regs)
     #ifdef __arm__
     restore_regs(0x100f);
     #endif
-  }/**/
+  }*/
 }
 
 void storelr_assemble(int i,struct regstat *i_regs)
 {
   int s,th,tl;
   int temp;
-  int temp2;
+  int temp2=-1;
   int offset;
-  int jaddr=0,jaddr2;
+  int jaddr=0;
   int case1,case2,case3;
   int done0,done1,done2;
   int memtarget=0,c=0;
@@ -3359,7 +3072,6 @@ void storelr_assemble(int i,struct regstat *i_regs)
     c=(i_regs->isconst>>s)&1;
     if(c) {
       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
-      if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
     }
   }
   assert(tl>=0);
@@ -3367,41 +3079,26 @@ void storelr_assemble(int i,struct regstat *i_regs)
     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
   }
   assert(temp>=0);
-  if(!using_tlb) {
-    if(!c) {
-      emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
-      if(!offset&&s!=temp) emit_mov(s,temp);
-      jaddr=(int)out;
-      emit_jno(0);
-    }
-    else
-    {
-      if(!memtarget||!rs1[i]) {
-        jaddr=(int)out;
-        emit_jmp(0);
-      }
-    }
-    #ifdef RAM_OFFSET
-    int map=get_reg(i_regs->regmap,ROREG);
-    if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
-    gen_tlb_addr_w(temp,map);
-    #else
-    if((u_int)rdram!=0x80000000) 
-      emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
-    #endif
-  }else{ // using tlb
-    int map=get_reg(i_regs->regmap,TLREG);
-    assert(map>=0);
-    reglist&=~(1<<map);
-    map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
-    if(!c&&!offset&&s>=0) emit_mov(s,temp);
-    do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
-    if(!jaddr&&!memtarget) {
+  if(!c) {
+    emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
+    if(!offset&&s!=temp) emit_mov(s,temp);
+    jaddr=(int)out;
+    emit_jno(0);
+  }
+  else
+  {
+    if(!memtarget||!rs1[i]) {
       jaddr=(int)out;
       emit_jmp(0);
     }
-    gen_tlb_addr_w(temp,map);
   }
+  #ifdef RAM_OFFSET
+  int map=get_reg(i_regs->regmap,ROREG);
+  if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
+  #else
+  if((u_int)rdram!=0x80000000)
+    emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
+  #endif
 
   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
     temp2=get_reg(i_regs->regmap,FTEMP);
@@ -3544,7 +3241,7 @@ void storelr_assemble(int i,struct regstat *i_regs)
   }
   if(!c||!memtarget)
     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
-  if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
+  if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
     #ifdef RAM_OFFSET
     int map=get_reg(i_regs->regmap,ROREG);
     if(map<0) map=HOST_TEMPREG;
@@ -3562,7 +3259,7 @@ void storelr_assemble(int i,struct regstat *i_regs)
     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
     emit_callne(invalidate_addr_reg[temp]);
     #else
-    jaddr2=(int)out;
+    int jaddr2=(int)out;
     emit_jne(0);
     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
     #endif
@@ -3579,194 +3276,12 @@ void storelr_assemble(int i,struct regstat *i_regs)
     emit_call((int)memdebug);
     emit_popa();
     //restore_regs(0x100f);
-  /**/
+  */
 }
 
 void c1ls_assemble(int i,struct regstat *i_regs)
 {
-#ifndef DISABLE_COP1
-  int s,th,tl;
-  int temp,ar;
-  int map=-1;
-  int offset;
-  int c=0;
-  int jaddr,jaddr2=0,jaddr3,type;
-  int agr=AGEN1+(i&1);
-  u_int hr,reglist=0;
-  th=get_reg(i_regs->regmap,FTEMP|64);
-  tl=get_reg(i_regs->regmap,FTEMP);
-  s=get_reg(i_regs->regmap,rs1[i]);
-  temp=get_reg(i_regs->regmap,agr);
-  if(temp<0) temp=get_reg(i_regs->regmap,-1);
-  offset=imm[i];
-  assert(tl>=0);
-  assert(rs1[i]>0);
-  assert(temp>=0);
-  for(hr=0;hr<HOST_REGS;hr++) {
-    if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
-  }
-  if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
-  if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
-  {
-    // Loads use a temporary register which we need to save
-    reglist|=1<<temp;
-  }
-  if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
-    ar=temp;
-  else // LWC1/LDC1
-    ar=tl;
-  //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
-  //else c=(i_regs->wasconst>>s)&1;
-  if(s>=0) c=(i_regs->wasconst>>s)&1;
-  // Check cop1 unusable
-  if(!cop1_usable) {
-    signed char rs=get_reg(i_regs->regmap,CSREG);
-    assert(rs>=0);
-    emit_testimm(rs,0x20000000);
-    jaddr=(int)out;
-    emit_jeq(0);
-    add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
-    cop1_usable=1;
-  }
-  if (opcode[i]==0x39) { // SWC1 (get float address)
-    emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
-  }
-  if (opcode[i]==0x3D) { // SDC1 (get double address)
-    emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
-  }
-  // Generate address + offset
-  if(!using_tlb) {
-    if(!c)
-      emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
-  }
-  else
-  {
-    map=get_reg(i_regs->regmap,TLREG);
-    assert(map>=0);
-    reglist&=~(1<<map);
-    if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
-      map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
-    }
-    if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
-      map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
-    }
-  }
-  if (opcode[i]==0x39) { // SWC1 (read float)
-    emit_readword_indexed(0,tl,tl);
-  }
-  if (opcode[i]==0x3D) { // SDC1 (read double)
-    emit_readword_indexed(4,tl,th);
-    emit_readword_indexed(0,tl,tl);
-  }
-  if (opcode[i]==0x31) { // LWC1 (get target address)
-    emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
-  }
-  if (opcode[i]==0x35) { // LDC1 (get target address)
-    emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
-  }
-  if(!using_tlb) {
-    if(!c) {
-      jaddr2=(int)out;
-      emit_jno(0);
-    }
-    else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
-      jaddr2=(int)out;
-      emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
-    }
-    #ifdef DESTRUCTIVE_SHIFT
-    if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
-      if(!offset&&!c&&s>=0) emit_mov(s,ar);
-    }
-    #endif
-  }else{
-    if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
-      do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
-    }
-    if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
-      do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
-    }
-  }
-  if (opcode[i]==0x31) { // LWC1
-    //if(s>=0&&!c&&!offset) emit_mov(s,tl);
-    //gen_tlb_addr_r(ar,map);
-    //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
-    #ifdef HOST_IMM_ADDR32
-    if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
-    else
-    #endif
-    emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
-    type=LOADW_STUB;
-  }
-  if (opcode[i]==0x35) { // LDC1
-    assert(th>=0);
-    //if(s>=0&&!c&&!offset) emit_mov(s,tl);
-    //gen_tlb_addr_r(ar,map);
-    //emit_readword_indexed((int)rdram-0x80000000,tl,th);
-    //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
-    #ifdef HOST_IMM_ADDR32
-    if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
-    else
-    #endif
-    emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
-    type=LOADD_STUB;
-  }
-  if (opcode[i]==0x39) { // SWC1
-    //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
-    emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
-    type=STOREW_STUB;
-  }
-  if (opcode[i]==0x3D) { // SDC1
-    assert(th>=0);
-    //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
-    //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
-    emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
-    type=STORED_STUB;
-  }
-  if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
-    if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
-      #ifndef DESTRUCTIVE_SHIFT
-      temp=offset||c||s<0?ar:s;
-      #endif
-      #if defined(HOST_IMM8)
-      int ir=get_reg(i_regs->regmap,INVCP);
-      assert(ir>=0);
-      emit_cmpmem_indexedsr12_reg(ir,temp,1);
-      #else
-      emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
-      #endif
-      #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
-      emit_callne(invalidate_addr_reg[temp]);
-      #else
-      jaddr3=(int)out;
-      emit_jne(0);
-      add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
-      #endif
-    }
-  }
-  if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
-  if (opcode[i]==0x31) { // LWC1 (write float)
-    emit_writeword_indexed(tl,0,temp);
-  }
-  if (opcode[i]==0x35) { // LDC1 (write double)
-    emit_writeword_indexed(th,4,temp);
-    emit_writeword_indexed(tl,0,temp);
-  }
-  //if(opcode[i]==0x39)
-  /*if(opcode[i]==0x39||opcode[i]==0x31)
-  {
-    emit_pusha();
-        emit_readword((int)&last_count,ECX);
-        if(get_reg(i_regs->regmap,CCREG)<0)
-          emit_loadreg(CCREG,HOST_CCREG);
-        emit_add(HOST_CCREG,ECX,HOST_CCREG);
-        emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
-        emit_writeword(HOST_CCREG,(int)&Count);
-    emit_call((int)memdebug);
-    emit_popa();
-  }/**/
-#else
   cop1_unusable(i, i_regs);
-#endif
 }
 
 void c2ls_assemble(int i,struct regstat *i_regs)
@@ -3775,7 +3290,7 @@ void c2ls_assemble(int i,struct regstat *i_regs)
   int ar;
   int offset;
   int memtarget=0,c=0;
-  int jaddr2=0,jaddr3,type;
+  int jaddr2=0,type;
   int agr=AGEN1+(i&1);
   int fastio_reg_override=0;
   u_int hr,reglist=0;
@@ -3785,7 +3300,6 @@ void c2ls_assemble(int i,struct regstat *i_regs)
   offset=imm[i];
   assert(rs1[i]>0);
   assert(tl>=0);
-  assert(!using_tlb);
 
   for(hr=0;hr<HOST_REGS;hr++) {
     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
@@ -3857,7 +3371,7 @@ void c2ls_assemble(int i,struct regstat *i_regs)
     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
     emit_callne(invalidate_addr_reg[ar]);
     #else
-    jaddr3=(int)out;
+    int jaddr3=(int)out;
     emit_jne(0);
     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
     #endif
@@ -3918,6 +3432,7 @@ void syscall_assemble(int i,struct regstat *i_regs)
   signed char ccreg=get_reg(i_regs->regmap,CCREG);
   assert(ccreg==HOST_CCREG);
   assert(!is_delayslot);
+  (void)ccreg;
   emit_movimm(start+i*4,EAX); // Get PC
   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
   emit_jmp((int)jump_syscall_hle); // XXX
@@ -3928,6 +3443,7 @@ void hlecall_assemble(int i,struct regstat *i_regs)
   signed char ccreg=get_reg(i_regs->regmap,CCREG);
   assert(ccreg==HOST_CCREG);
   assert(!is_delayslot);
+  (void)ccreg;
   emit_movimm(start+i*4+4,0); // Get PC
   emit_movimm((int)psxHLEt[source[i]&7],1);
   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
@@ -3939,6 +3455,7 @@ void intcall_assemble(int i,struct regstat *i_regs)
   signed char ccreg=get_reg(i_regs->regmap,CCREG);
   assert(ccreg==HOST_CCREG);
   assert(!is_delayslot);
+  (void)ccreg;
   emit_movimm(start+i*4,0); // Get PC
   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
   emit_jmp((int)jump_intcall);
@@ -4007,7 +3524,7 @@ int internal_branch(uint64_t i_is32,int addr)
   if(addr&1) return 0; // Indirect (register) jump
   if(addr>=start && addr<start+slen*4-4)
   {
-    int t=(addr-start)>>2;
+    //int t=(addr-start)>>2;
     // Delay slots are not valid branch targets
     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
     // 64 -> 32 bit transition requires a recompile
@@ -4017,11 +3534,7 @@ int internal_branch(uint64_t i_is32,int addr)
       else printf("optimizable: yes\n");
     }*/
     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
-#ifndef FORCE32
-    if(requires_32bit[t]&~i_is32) return 0;
-    else
-#endif
-      return 1;
+    return 1;
   }
   return 0;
 }
@@ -4156,10 +3669,9 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
     int ra=-1;
     int agr=AGEN1+(i&1);
-    int mgr=MGEN1+(i&1);
     if(itype[i]==LOAD) {
       ra=get_reg(i_regs->regmap,rt1[i]);
-      if(ra<0) ra=get_reg(i_regs->regmap,-1); 
+      if(ra<0) ra=get_reg(i_regs->regmap,-1);
       assert(ra>=0);
     }
     if(itype[i]==LOADLR) {
@@ -4178,17 +3690,11 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
       }
     }
     int rs=get_reg(i_regs->regmap,rs1[i]);
-    int rm=get_reg(i_regs->regmap,TLREG);
     if(ra>=0) {
       int offset=imm[i];
       int c=(i_regs->wasconst>>rs)&1;
       if(rs1[i]==0) {
         // Using r0 as a base address
-        /*if(rm>=0) {
-          if(!entry||entry[rm]!=mgr) {
-            generate_map_const(offset,rm);
-          } // else did it in the previous cycle
-        }*/
         if(!entry||entry[ra]!=agr) {
           if (opcode[i]==0x22||opcode[i]==0x26) {
             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
@@ -4206,22 +3712,6 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
         //  printf("poor load scheduling!\n");
       }
       else if(c) {
-#ifndef DISABLE_TLB
-        if(rm>=0) {
-          if(!entry||entry[rm]!=mgr) {
-            if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
-              // Stores to memory go thru the mapper to detect self-modifying
-              // code, loads don't.
-              if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
-                 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
-                generate_map_const(constmap[i][rs]+offset,rm);
-            }else{
-              if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
-                generate_map_const(constmap[i][rs]+offset,rm);
-            }
-          }
-        }
-#endif
         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
           if(!entry||entry[ra]!=agr) {
             if (opcode[i]==0x22||opcode[i]==0x26) {
@@ -4230,8 +3720,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
             }else{
               #ifdef HOST_IMM_ADDR32
-              if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
-                 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
+              if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
               #endif
               emit_movimm(constmap[i][rs]+offset,ra);
               regs[i].loadedconst|=1<<ra;
@@ -4251,32 +3740,6 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
   // Preload constants for next instruction
   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
     int agr,ra;
-    #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
-    // Mapper entry
-    agr=MGEN1+((i+1)&1);
-    ra=get_reg(i_regs->regmap,agr);
-    if(ra>=0) {
-      int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
-      int offset=imm[i+1];
-      int c=(regs[i+1].wasconst>>rs)&1;
-      if(c) {
-        if(itype[i+1]==STORE||itype[i+1]==STORELR
-           ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
-          // Stores to memory go thru the mapper to detect self-modifying
-          // code, loads don't.
-          if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
-             (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
-            generate_map_const(constmap[i+1][rs]+offset,ra);
-        }else{
-          if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
-            generate_map_const(constmap[i+1][rs]+offset,ra);
-        }
-      }
-      /*else if(rs1[i]==0) {
-        generate_map_const(offset,ra);
-      }*/
-    }
-    #endif
     // Actual address
     agr=AGEN1+((i+1)&1);
     ra=get_reg(i_regs->regmap,agr);
@@ -4291,8 +3754,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
         }else{
           #ifdef HOST_IMM_ADDR32
-          if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
-             (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
+          if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
           #endif
           emit_movimm(constmap[i+1][rs]+offset,ra);
           regs[i+1].loadedconst|=1<<ra;
@@ -4312,7 +3774,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[])
   }
 }
 
-int get_final_value(int hr, int i, int *value)
+static int get_final_value(int hr, int i, int *value)
 {
   int reg=regs[i].regmap[hr];
   while(i<slen-1) {
@@ -4331,9 +3793,6 @@ int get_final_value(int hr, int i, int *value)
         // Load in delay slot, out-of-order execution
         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
         {
-          #ifdef HOST_IMM_ADDR32
-          if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
-          #endif
           // Precompute load address
           *value=constmap[i][hr]+imm[i+2];
           return 1;
@@ -4341,9 +3800,6 @@ int get_final_value(int hr, int i, int *value)
       }
       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
       {
-        #ifdef HOST_IMM_ADDR32
-        if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
-        #endif
         // Precompute load address
         *value=constmap[i][hr]+imm[i+1];
         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
@@ -4493,17 +3949,6 @@ void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
           if((i_dirty>>hr)&1) {
             if(i_regmap[hr]<64) {
               emit_storereg(i_regmap[hr],hr);
-#ifndef FORCE32
-              if( ((i_is32>>i_regmap[hr])&1) ) {
-                #ifdef DESTRUCTIVE_WRITEBACK
-                emit_sarimm(hr,31,hr);
-                emit_storereg(i_regmap[hr]|64,hr);
-                #else
-                emit_sarimm(hr,31,HOST_TEMPREG);
-                emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
-                #endif
-              }
-#endif
             }else{
               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
                 emit_storereg(i_regmap[hr],hr);
@@ -4529,17 +3974,6 @@ void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,in
             if((i_dirty>>hr)&1) {
               if(i_regmap[hr]<64) {
                 emit_storereg(i_regmap[hr],hr);
-#ifndef FORCE32
-                if( ((i_is32>>i_regmap[hr])&1) ) {
-                  #ifdef DESTRUCTIVE_WRITEBACK
-                  emit_sarimm(hr,31,hr);
-                  emit_storereg(i_regmap[hr]|64,hr);
-                  #else
-                  emit_sarimm(hr,31,HOST_TEMPREG);
-                  emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
-                  #endif
-                }
-#endif
               }else{
                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
                   emit_storereg(i_regmap[hr],hr);
@@ -4757,7 +4191,7 @@ int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
           {
             return 0;
           }
-          else 
+          else
           if((i_dirty>>hr)&1)
           {
             if(i_regmap[hr]<TEMPREG)
@@ -4795,9 +4229,6 @@ int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
       }
     }
     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
-#ifndef FORCE32
-    if(requires_32bit[t]&~i_is32) return 0;
-#endif
     // Delay slots are not valid branch targets
     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
     // Delay slots require additional processing, so do not match
@@ -5003,7 +4434,7 @@ void do_ccstub(int n)
       if(rs1[i]) {
         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
           emit_loadreg(rs1[i],s1l);
-      } 
+      }
       else {
         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
           emit_loadreg(rs2[i],s1l);
@@ -5194,7 +4625,7 @@ void do_ccstub(int n)
     load_all_regs(branch_regs[i].regmap);
   }
   emit_jmp(stubs[n][2]); // return address
-  
+
   /* This works but uses a lot of memory...
   emit_readword((int)&last_count,ECX);
   emit_add(HOST_CCREG,ECX,EAX);
@@ -5224,11 +4655,11 @@ void do_ccstub(int n)
   emit_jmpreg(EAX);*/
 }
 
-add_to_linker(int addr,int target,int ext)
+static void add_to_linker(int addr,int target,int ext)
 {
   link_addr[linkcount][0]=addr;
   link_addr[linkcount][1]=target;
-  link_addr[linkcount][2]=ext;  
+  link_addr[linkcount][2]=ext;
   linkcount++;
 }
 
@@ -5254,7 +4685,7 @@ static void ujump_assemble_write_ra(int i)
     #endif
     {
       #ifdef REG_PREFETCH
-      if(temp>=0) 
+      if(temp>=0)
       {
         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
       }
@@ -5269,16 +4700,16 @@ static void ujump_assemble_write_ra(int i)
 
 void ujump_assemble(int i,struct regstat *i_regs)
 {
-  signed char *i_regmap=i_regs->regmap;
   int ra_done=0;
   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
   address_generation(i+1,i_regs,regs[i].regmap_entry);
   #ifdef REG_PREFETCH
   int temp=get_reg(branch_regs[i].regmap,PTEMP);
-  if(rt1[i]==31&&temp>=0) 
+  if(rt1[i]==31&&temp>=0)
   {
+    signed char *i_regmap=i_regs->regmap;
     int return_address=start+i*4+8;
-    if(get_reg(branch_regs[i].regmap,31)>0) 
+    if(get_reg(branch_regs[i].regmap,31)>0)
     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
   }
   #endif
@@ -5329,7 +4760,7 @@ static void rjump_assemble_write_ra(int i)
   assert(rt>=0);
   return_address=start+i*4+8;
   #ifdef REG_PREFETCH
-  if(temp>=0) 
+  if(temp>=0)
   {
     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
   }
@@ -5342,9 +4773,8 @@ static void rjump_assemble_write_ra(int i)
 
 void rjump_assemble(int i,struct regstat *i_regs)
 {
-  signed char *i_regmap=i_regs->regmap;
   int temp;
-  int rs,cc,adj;
+  int rs,cc;
   int ra_done=0;
   rs=get_reg(branch_regs[i].regmap,rs1[i]);
   assert(rs>=0);
@@ -5358,9 +4788,10 @@ void rjump_assemble(int i,struct regstat *i_regs)
   }
   address_generation(i+1,i_regs,regs[i].regmap_entry);
   #ifdef REG_PREFETCH
-  if(rt1[i]==31) 
+  if(rt1[i]==31)
   {
     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
+      signed char *i_regmap=i_regs->regmap;
       int return_address=start+i*4+8;
       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
     }
@@ -5389,6 +4820,7 @@ void rjump_assemble(int i,struct regstat *i_regs)
     rjump_assemble_write_ra(i);
   cc=get_reg(branch_regs[i].regmap,CCREG);
   assert(cc==HOST_CCREG);
+  (void)cc;
   #ifdef USE_MINI_HT
   int rh=get_reg(branch_regs[i].regmap,RHASH);
   int ht=get_reg(branch_regs[i].regmap,RHTBL);
@@ -5419,13 +4851,11 @@ void rjump_assemble(int i,struct regstat *i_regs)
   //assert(adj==0);
   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
-#ifdef PCSX
   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
     // special case for RFE
     emit_jmp(0);
   else
-#endif
-  emit_jns(0);
+    emit_jns(0);
   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
   #ifdef USE_MINI_HT
   if(rs1[i]==31) {
@@ -5492,7 +4922,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
   if(i>(ba[i]-start)>>2) invert=1;
   #endif
-  
+
   if(ooo[i]) {
     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
@@ -5547,7 +4977,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
     cc=get_reg(branch_regs[i].regmap,CCREG);
     assert(cc==HOST_CCREG);
-    if(unconditional) 
+    if(unconditional)
       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
     //assem_debug("cycle count (adj)\n");
@@ -5619,7 +5049,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
           emit_jne(0);
         }
       } // if(!only32)
-          
+
       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
       assert(s1l>=0);
       if(opcode[i]==4) // BEQ
@@ -5749,7 +5179,7 @@ void cjump_assemble(int i,struct regstat *i_regs)
           emit_jne(1);
         }
       } // if(!only32)
-          
+
       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
       assert(s1l>=0);
       if((opcode[i]&0x2f)==4) // BEQ
@@ -5932,7 +5362,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
     }
     cc=get_reg(branch_regs[i].regmap,CCREG);
     assert(cc==HOST_CCREG);
-    if(unconditional) 
+    if(unconditional)
       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
     assem_debug("cycle count (adj)\n");
@@ -6019,7 +5449,7 @@ void sjump_assemble(int i,struct regstat *i_regs)
           }
         }
       } // if(!only32)
-          
+
       if(invert) {
         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
@@ -6267,7 +5697,7 @@ void fjump_assemble(int i,struct regstat *i_regs)
         {
         }
       } // if(!only32)
-          
+
       if(invert) {
         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
@@ -6396,7 +5826,6 @@ static void pagespan_assemble(int i,struct regstat *i_regs)
   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
   int s2l=get_reg(i_regs->regmap,rs2[i]);
   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
-  void *nt_branch=NULL;
   int taken=0;
   int nottaken=0;
   int unconditional=0;
@@ -6413,7 +5842,7 @@ static void pagespan_assemble(int i,struct regstat *i_regs)
     s1h=s2h=-1;
   }
   int hr=0;
-  int addr,alt,ntaddr;
+  int addr=-1,alt=-1,ntaddr=-1;
   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
   else {
     while(hr<HOST_REGS)
@@ -6775,14 +6204,14 @@ void unneeded_registers(int istart,int iend,int r)
     {
       // If subroutine call, flag return address as a possible branch target
       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
-      
+
       if(ba[i]<start || ba[i]>=(start+slen*4))
       {
         // Branch out of this block, flush all regs
         u=1;
         uu=1;
         gte_u=gte_u_unknown;
-        /* Hexagon hack 
+        /* Hexagon hack
         if(itype[i]==UJUMP&&rt1[i]==31)
         {
           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
@@ -7029,364 +6458,10 @@ void unneeded_registers(int istart,int iend,int r)
     }
     printf("\n");*/
   }
-#ifdef FORCE32
   for (i=iend;i>=istart;i--)
   {
     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
   }
-#endif
-}
-
-// Identify registers which are likely to contain 32-bit values
-// This is used to predict whether any branches will jump to a
-// location with 64-bit values in registers.
-static void provisional_32bit()
-{
-  int i,j;
-  uint64_t is32=1;
-  uint64_t lastbranch=1;
-  
-  for(i=0;i<slen;i++)
-  {
-    if(i>0) {
-      if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
-        if(i>1) is32=lastbranch;
-        else is32=1;
-      }
-    }
-    if(i>1)
-    {
-      if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
-        if(likely[i-2]) {
-          if(i>2) is32=lastbranch;
-          else is32=1;
-        }
-      }
-      if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
-      {
-        if(rs1[i-2]==0||rs2[i-2]==0)
-        {
-          if(rs1[i-2]) {
-            is32|=1LL<<rs1[i-2];
-          }
-          if(rs2[i-2]) {
-            is32|=1LL<<rs2[i-2];
-          }
-        }
-      }
-    }
-    // If something jumps here with 64-bit values
-    // then promote those registers to 64 bits
-    if(bt[i])
-    {
-      uint64_t temp_is32=is32;
-      for(j=i-1;j>=0;j--)
-      {
-        if(ba[j]==start+i*4) 
-          //temp_is32&=branch_regs[j].is32;
-          temp_is32&=p32[j];
-      }
-      for(j=i;j<slen;j++)
-      {
-        if(ba[j]==start+i*4) 
-          temp_is32=1;
-      }
-      is32=temp_is32;
-    }
-    int type=itype[i];
-    int op=opcode[i];
-    int op2=opcode2[i];
-    int rt=rt1[i];
-    int s1=rs1[i];
-    int s2=rs2[i];
-    if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
-      // Branches don't write registers, consider the delay slot instead.
-      type=itype[i+1];
-      op=opcode[i+1];
-      op2=opcode2[i+1];
-      rt=rt1[i+1];
-      s1=rs1[i+1];
-      s2=rs2[i+1];
-      lastbranch=is32;
-    }
-    switch(type) {
-      case LOAD:
-        if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
-           opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
-          is32&=~(1LL<<rt);
-        else
-          is32|=1LL<<rt;
-        break;
-      case STORE:
-      case STORELR:
-        break;
-      case LOADLR:
-        if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
-        if(op==0x22) is32|=1LL<<rt; // LWL
-        break;
-      case IMM16:
-        if (op==0x08||op==0x09|| // ADDI/ADDIU
-            op==0x0a||op==0x0b|| // SLTI/SLTIU
-            op==0x0c|| // ANDI
-            op==0x0f)  // LUI
-        {
-          is32|=1LL<<rt;
-        }
-        if(op==0x18||op==0x19) { // DADDI/DADDIU
-          is32&=~(1LL<<rt);
-          //if(imm[i]==0)
-          //  is32|=((is32>>s1)&1LL)<<rt;
-        }
-        if(op==0x0d||op==0x0e) { // ORI/XORI
-          uint64_t sr=((is32>>s1)&1LL);
-          is32&=~(1LL<<rt);
-          is32|=sr<<rt;
-        }
-        break;
-      case UJUMP:
-        break;
-      case RJUMP:
-        break;
-      case CJUMP:
-        break;
-      case SJUMP:
-        break;
-      case FJUMP:
-        break;
-      case ALU:
-        if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
-          is32|=1LL<<rt;
-        }
-        if(op2==0x2a||op2==0x2b) { // SLT/SLTU
-          is32|=1LL<<rt;
-        }
-        else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
-          uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
-          is32&=~(1LL<<rt);
-          is32|=sr<<rt;
-        }
-        else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
-          if(s1==0&&s2==0) {
-            is32|=1LL<<rt;
-          }
-          else if(s2==0) {
-            uint64_t sr=((is32>>s1)&1LL);
-            is32&=~(1LL<<rt);
-            is32|=sr<<rt;
-          }
-          else if(s1==0) {
-            uint64_t sr=((is32>>s2)&1LL);
-            is32&=~(1LL<<rt);
-            is32|=sr<<rt;
-          }
-          else {
-            is32&=~(1LL<<rt);
-          }
-        }
-        else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
-          if(s1==0&&s2==0) {
-            is32|=1LL<<rt;
-          }
-          else if(s2==0) {
-            uint64_t sr=((is32>>s1)&1LL);
-            is32&=~(1LL<<rt);
-            is32|=sr<<rt;
-          }
-          else {
-            is32&=~(1LL<<rt);
-          }
-        }
-        break;
-      case MULTDIV:
-        if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
-          is32&=~((1LL<<HIREG)|(1LL<<LOREG));
-        }
-        else {
-          is32|=(1LL<<HIREG)|(1LL<<LOREG);
-        }
-        break;
-      case MOV:
-        {
-          uint64_t sr=((is32>>s1)&1LL);
-          is32&=~(1LL<<rt);
-          is32|=sr<<rt;
-        }
-        break;
-      case SHIFT:
-        if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
-        else is32|=1LL<<rt; // SLLV/SRLV/SRAV
-        break;
-      case SHIFTIMM:
-        is32|=1LL<<rt;
-        // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
-        if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
-        break;
-      case COP0:
-        if(op2==0) is32|=1LL<<rt; // MFC0
-        break;
-      case COP1:
-      case COP2:
-        if(op2==0) is32|=1LL<<rt; // MFC1
-        if(op2==1) is32&=~(1LL<<rt); // DMFC1
-        if(op2==2) is32|=1LL<<rt; // CFC1
-        break;
-      case C1LS:
-      case C2LS:
-        break;
-      case FLOAT:
-      case FCONV:
-        break;
-      case FCOMP:
-        break;
-      case C2OP:
-      case SYSCALL:
-      case HLECALL:
-        break;
-      default:
-        break;
-    }
-    is32|=1;
-    p32[i]=is32;
-
-    if(i>0)
-    {
-      if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
-      {
-        if(rt1[i-1]==31) // JAL/JALR
-        {
-          // Subroutine call will return here, don't alloc any registers
-          is32=1;
-        }
-        else if(i+1<slen)
-        {
-          // Internal branch will jump here, match registers to caller
-          is32=0x3FFFFFFFFLL;
-        }
-      }
-    }
-  }
-}
-
-// Identify registers which may be assumed to contain 32-bit values
-// and where optimizations will rely on this.
-// This is used to determine whether backward branches can safely
-// jump to a location with 64-bit values in registers.
-static void provisional_r32()
-{
-  u_int r32=0;
-  int i;
-  
-  for (i=slen-1;i>=0;i--)
-  {
-    int hr;
-    if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
-    {
-      if(ba[i]<start || ba[i]>=(start+slen*4))
-      {
-        // Branch out of this block, don't need anything
-        r32=0;
-      }
-      else
-      {
-        // Internal branch
-        // Need whatever matches the target
-        // (and doesn't get overwritten by the delay slot instruction)
-        r32=0;
-        int t=(ba[i]-start)>>2;
-        if(ba[i]>start+i*4) {
-          // Forward branch
-          //if(!(requires_32bit[t]&~regs[i].was32))
-          //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-          if(!(pr32[t]&~regs[i].was32))
-            r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-        }else{
-          // Backward branch
-          if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
-            r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-        }
-      }
-      // Conditional branch may need registers for following instructions
-      if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
-      {
-        if(i<slen-2) {
-          //r32|=requires_32bit[i+2];
-          r32|=pr32[i+2];
-          r32&=regs[i].was32;
-          // Mark this address as a branch target since it may be called
-          // upon return from interrupt
-          //bt[i+2]=1;
-        }
-      }
-      // Merge in delay slot
-      if(!likely[i]) {
-        // These are overwritten unless the branch is "likely"
-        // and the delay slot is nullified if not taken
-        r32&=~(1LL<<rt1[i+1]);
-        r32&=~(1LL<<rt2[i+1]);
-      }
-      // Assume these are needed (delay slot)
-      if(us1[i+1]>0)
-      {
-        if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
-      }
-      if(us2[i+1]>0)
-      {
-        if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
-      }
-      if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
-      {
-        if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
-      }
-      if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
-      {
-        if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
-      }
-    }
-    else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
-    {
-      // SYSCALL instruction (software interrupt)
-      r32=0;
-    }
-    else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
-    {
-      // ERET instruction (return from interrupt)
-      r32=0;
-    }
-    // Check 32 bits
-    r32&=~(1LL<<rt1[i]);
-    r32&=~(1LL<<rt2[i]);
-    if(us1[i]>0)
-    {
-      if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
-    }
-    if(us2[i]>0)
-    {
-      if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
-    }
-    if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
-    {
-      if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
-    }
-    if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
-    {
-      if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
-    }
-    //requires_32bit[i]=r32;
-    pr32[i]=r32;
-    
-    // Dirty registers which are 32-bit, require 32-bit input
-    // as they will be written as 32-bit values
-    for(hr=0;hr<HOST_REGS;hr++)
-    {
-      if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
-        if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
-          if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
-          pr32[i]|=1LL<<regs[i].regmap_entry[hr];
-          //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
-        }
-      }
-    }
-  }
 }
 
 // Write back dirty registers as soon as we will no longer modify them,
@@ -7726,7 +6801,7 @@ void clean_registers(int istart,int iend,int wr)
         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
         if(i>istart) {
-          if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP) 
+          if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
           {
             // Don't store a register immediately after writing it,
             // may prevent dual-issue.
@@ -7760,7 +6835,7 @@ void clean_registers(int istart,int iend,int wr)
               if(r!=EXCLUDE_REG) {
                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
-                }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
+                }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
               }
             }
           }
@@ -7772,7 +6847,7 @@ void clean_registers(int istart,int iend,int wr)
               if(r!=EXCLUDE_REG) {
                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
-                }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
+                }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
               }
             }
           }
@@ -7815,7 +6890,7 @@ void clean_registers(int istart,int iend,int wr)
             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
           } else {
             wont_dirty_i|=1<<r;
-            /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
+            /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
           }
         }
       }
@@ -7921,13 +6996,14 @@ static void disassemble_inst(int i) {}
 static int new_dynarec_test(void)
 {
   int (*testfunc)(void) = (void *)out;
+  void *beginning;
   int ret;
+
+  beginning = start_block();
   emit_movimm(DRC_TEST_VAL,0); // test
   emit_jmpreg(14);
   literal_pool(0);
-#ifdef __arm__
-  __clear_cache((void *)testfunc, out);
-#endif
+  end_block(beginning);
   SysPrintf("testing if we can run recompiled code..\n");
   ret = testfunc();
   if (ret == DRC_TEST_VAL)
@@ -7956,15 +7032,6 @@ void new_dynarec_clear_full()
   stop_after_jal=0;
   inv_code_start=inv_code_end=~0;
   // TLB
-#ifndef DISABLE_TLB
-  using_tlb=0;
-  for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
-    memory_map[n]=-1;
-  for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
-    memory_map[n]=((u_int)rdram-0x80000000)>>2;
-  for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
-    memory_map[n]=-1;
-#endif
   for(n=0;n<4096;n++) ll_clear(jump_in+n);
   for(n=0;n<4096;n++) ll_clear(jump_out+n);
   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
@@ -7973,71 +7040,49 @@ void new_dynarec_clear_full()
 void new_dynarec_init()
 {
   SysPrintf("Init new dynarec\n");
-  out=(u_char *)BASE_ADDR;
-#if BASE_ADDR_FIXED
-  if (mmap (out, 1<<TARGET_SIZE_2,
+
+  // allocate/prepare a buffer for translation cache
+  // see assem_arm.h for some explanation
+#if   defined(BASE_ADDR_FIXED)
+  if (mmap (translation_cache, 1 << TARGET_SIZE_2,
             PROT_READ | PROT_WRITE | PROT_EXEC,
-            MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
-            -1, 0) <= 0) {
+            MAP_PRIVATE | MAP_ANONYMOUS,
+            -1, 0) != translation_cache) {
     SysPrintf("mmap() failed: %s\n", strerror(errno));
+    SysPrintf("disable BASE_ADDR_FIXED and recompile\n");
+    abort();
+  }
+#elif defined(BASE_ADDR_DYNAMIC)
+  #ifdef VITA
+  sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
+  if (sceBlock < 0)
+    SysPrintf("sceKernelAllocMemBlockForVM failed\n");
+  int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&translation_cache);
+  if (ret < 0)
+    SysPrintf("sceKernelGetMemBlockBase failed\n");
+  #else
+  translation_cache = mmap (NULL, 1 << TARGET_SIZE_2,
+            PROT_READ | PROT_WRITE | PROT_EXEC,
+            MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+  if (translation_cache == MAP_FAILED) {
+    SysPrintf("mmap() failed: %s\n", strerror(errno));
+    abort();
   }
+  #endif
 #else
+  #ifndef NO_WRITE_EXEC
   // not all systems allow execute in data segment by default
   if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
     SysPrintf("mprotect() failed: %s\n", strerror(errno));
+  #endif
 #endif
-#ifdef MUPEN64
-  rdword=&readmem_dword;
-  fake_pc.f.r.rs=&readmem_dword;
-  fake_pc.f.r.rt=&readmem_dword;
-  fake_pc.f.r.rd=&readmem_dword;
-#endif
-  int n;
+  out=(u_char *)BASE_ADDR;
   cycle_multiplier=200;
   new_dynarec_clear_full();
 #ifdef HOST_IMM8
   // Copy this into local area so we don't have to put it in every literal pool
   invc_ptr=invalid_code;
 #endif
-#ifdef MUPEN64
-  for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
-    writemem[n] = write_nomem_new;
-    writememb[n] = write_nomemb_new;
-    writememh[n] = write_nomemh_new;
-#ifndef FORCE32
-    writememd[n] = write_nomemd_new;
-#endif
-    readmem[n] = read_nomem_new;
-    readmemb[n] = read_nomemb_new;
-    readmemh[n] = read_nomemh_new;
-#ifndef FORCE32
-    readmemd[n] = read_nomemd_new;
-#endif
-  }
-  for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
-    writemem[n] = write_rdram_new;
-    writememb[n] = write_rdramb_new;
-    writememh[n] = write_rdramh_new;
-#ifndef FORCE32
-    writememd[n] = write_rdramd_new;
-#endif
-  }
-  for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
-    writemem[n] = write_nomem_new;
-    writememb[n] = write_nomemb_new;
-    writememh[n] = write_nomemh_new;
-#ifndef FORCE32
-    writememd[n] = write_nomemd_new;
-#endif
-    readmem[n] = read_nomem_new;
-    readmemb[n] = read_nomemb_new;
-    readmemh[n] = read_nomemh_new;
-#ifndef FORCE32
-    readmemd[n] = read_nomemd_new;
-#endif
-  }
-#endif
-  tlb_hacks();
   arch_init();
   new_dynarec_test();
 #ifndef RAM_FIXED
@@ -8050,9 +7095,15 @@ void new_dynarec_init()
 void new_dynarec_cleanup()
 {
   int n;
-  #if BASE_ADDR_FIXED
-  if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
+#if defined(BASE_ADDR_FIXED) || defined(BASE_ADDR_DYNAMIC)
+  #ifdef VITA
+  sceKernelFreeMemBlock(sceBlock);
+  sceBlock = -1;
+  #else
+  if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0)
+    SysPrintf("munmap() failed\n");
   #endif
+#endif
   for(n=0;n<4096;n++) ll_clear(jump_in+n);
   for(n=0;n<4096;n++) ll_clear(jump_out+n);
   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
@@ -8080,6 +7131,7 @@ static u_int *get_source_start(u_int addr, u_int *limit)
     *limit = (addr & 0x80600000) + 0x00200000;
     return (u_int *)((u_int)rdram + (addr&0x1fffff));
   }
+  return NULL;
 }
 
 static u_int scan_for_ret(u_int addr)
@@ -8097,6 +7149,7 @@ static u_int scan_for_ret(u_int addr)
     if (*mem == 0x03e00008) // jr $ra
       return addr + 8;
   }
+  return addr;
 }
 
 struct savestate_block {
@@ -8190,7 +7243,7 @@ int new_recompile_block(int addr)
   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
-  //if(debug) 
+  //if(debug)
   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
   /*if(Count>=312978186) {
@@ -8210,16 +7263,15 @@ int new_recompile_block(int addr)
   if (Config.HLE && start == 0x80001000) // hlecall
   {
     // XXX: is this enough? Maybe check hleSoftCall?
-    u_int beginning=(u_int)out;
+    void *beginning=start_block();
     u_int page=get_page(start);
+
     invalid_code[start>>12]=0;
     emit_movimm(start,0);
     emit_writeword(0,(int)&pcaddr);
     emit_jmp((int)new_dyna_leave);
     literal_pool(0);
-#ifdef __arm__
-    __clear_cache((void *)beginning,out);
-#endif
+    end_block(beginning);
     ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
     return 0;
   }
@@ -8246,7 +7298,7 @@ int new_recompile_block(int addr)
   unsigned int type,op,op2;
 
   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
-  
+
   /* Pass 1 disassembly */
 
   for(i=0;!done;i++) {
@@ -8294,7 +7346,7 @@ int new_recompile_block(int addr)
           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
-#ifndef FORCE32
+#if 0
           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
@@ -8362,11 +7414,8 @@ int new_recompile_block(int addr)
             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
-#ifdef PCSX
             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
-#else
-            case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
-#endif
+            //case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
           }
         }
         break;
@@ -8485,7 +7534,7 @@ int new_recompile_block(int addr)
           break;
         }
         break;
-#ifndef FORCE32
+#if 0
       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
@@ -8502,14 +7551,14 @@ int new_recompile_block(int addr)
       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
-#ifndef FORCE32
+#if 0
       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
 #endif
       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
-#ifndef FORCE32
+#if 0
       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
 #endif
@@ -8517,19 +7566,18 @@ int new_recompile_block(int addr)
       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
-#ifndef FORCE32
+#if 0
       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
 #endif
       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
-#ifndef FORCE32
+#if 0
       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
 #endif
-#ifdef PCSX
       case 0x12: strcpy(insn[i],"COP2"); type=NI;
         op2=(source[i]>>21)&0x1f;
         //if (op2 & 0x10) {
@@ -8553,7 +7601,6 @@ int new_recompile_block(int addr)
       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
-#endif
       default: strcpy(insn[i],"???"); type=NI;
         SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
         break;
@@ -8824,7 +7871,6 @@ int new_recompile_block(int addr)
     else if(type==CJUMP||type==SJUMP||type==FJUMP)
       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
     else ba[i]=-1;
-#ifdef PCSX
     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
       int do_in_intrp=0;
       // branch in delay slot?
@@ -8858,7 +7904,6 @@ int new_recompile_block(int addr)
         i--; // don't compile the DS
       }
     }
-#endif
     /* Is this the end of the block? */
     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
@@ -8906,7 +7951,7 @@ int new_recompile_block(int addr)
   /* Pass 2 - Register dependencies and branch targets */
 
   unneeded_registers(0,slen-1,0);
-  
+
   /* Pass 3 - Register allocation */
 
   struct regstat current; // Current register allocations/status
@@ -8924,9 +7969,6 @@ int new_recompile_block(int addr)
   int cc=0;
   int hr=-1;
 
-#ifndef FORCE32
-  provisional_32bit();
-#endif
   if((u_int)addr&1) {
     // First instruction is delay slot
     cc=-1;
@@ -8936,7 +7978,7 @@ int new_recompile_block(int addr)
     unneeded_reg_upper[0]=1;
     current.regmap[HOST_BTREG]=BTREG;
   }
-  
+
   for(i=0;i<slen;i++)
   {
     if(bt[i])
@@ -8969,126 +8011,13 @@ int new_recompile_block(int addr)
         }
       }
     }
-#ifndef FORCE32
-    // If something jumps here with 64-bit values
-    // then promote those registers to 64 bits
-    if(bt[i])
-    {
-      uint64_t temp_is32=current.is32;
-      for(j=i-1;j>=0;j--)
-      {
-        if(ba[j]==start+i*4) 
-          temp_is32&=branch_regs[j].is32;
-      }
-      for(j=i;j<slen;j++)
-      {
-        if(ba[j]==start+i*4) 
-          //temp_is32=1;
-          temp_is32&=p32[j];
-      }
-      if(temp_is32!=current.is32) {
-        //printf("dumping 32-bit regs (%x)\n",start+i*4);
-        #ifndef DESTRUCTIVE_WRITEBACK
-        if(ds)
-        #endif
-        for(hr=0;hr<HOST_REGS;hr++)
-        {
-          int r=current.regmap[hr];
-          if(r>0&&r<64)
-          {
-            if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
-              temp_is32|=1LL<<r;
-              //printf("restore %d\n",r);
-            }
-          }
-        }
-        current.is32=temp_is32;
-      }
-    }
-#else
     current.is32=-1LL;
-#endif
 
     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
     regs[i].wasconst=current.isconst;
     regs[i].was32=current.is32;
     regs[i].wasdirty=current.dirty;
     regs[i].loadedconst=0;
-    #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
-    // To change a dirty register from 32 to 64 bits, we must write
-    // it out during the previous cycle (for branches, 2 cycles)
-    if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
-    {
-      uint64_t temp_is32=current.is32;
-      for(j=i-1;j>=0;j--)
-      {
-        if(ba[j]==start+i*4+4) 
-          temp_is32&=branch_regs[j].is32;
-      }
-      for(j=i;j<slen;j++)
-      {
-        if(ba[j]==start+i*4+4) 
-          //temp_is32=1;
-          temp_is32&=p32[j];
-      }
-      if(temp_is32!=current.is32) {
-        //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
-        for(hr=0;hr<HOST_REGS;hr++)
-        {
-          int r=current.regmap[hr];
-          if(r>0)
-          {
-            if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
-              if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
-              {
-                if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
-                {
-                  //printf("dump %d/r%d\n",hr,r);
-                  current.regmap[hr]=-1;
-                  if(get_reg(current.regmap,r|64)>=0) 
-                    current.regmap[get_reg(current.regmap,r|64)]=-1;
-                }
-              }
-            }
-          }
-        }
-      }
-    }
-    else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
-    {
-      uint64_t temp_is32=current.is32;
-      for(j=i-1;j>=0;j--)
-      {
-        if(ba[j]==start+i*4+8) 
-          temp_is32&=branch_regs[j].is32;
-      }
-      for(j=i;j<slen;j++)
-      {
-        if(ba[j]==start+i*4+8) 
-          //temp_is32=1;
-          temp_is32&=p32[j];
-      }
-      if(temp_is32!=current.is32) {
-        //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
-        for(hr=0;hr<HOST_REGS;hr++)
-        {
-          int r=current.regmap[hr];
-          if(r>0)
-          {
-            if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
-              if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
-              {
-                //printf("dump %d/r%d\n",hr,r);
-                current.regmap[hr]=-1;
-                if(get_reg(current.regmap,r|64)>=0) 
-                  current.regmap[get_reg(current.regmap,r|64)]=-1;
-              }
-            }
-          }
-        }
-      }
-    }
-    #endif
     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
       if(i+1<slen) {
         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
@@ -9172,7 +8101,7 @@ int new_recompile_block(int addr)
           }
         } else {
           // First instruction expects CCREG to be allocated
-          if(i==0&&hr==HOST_CCREG) 
+          if(i==0&&hr==HOST_CCREG)
             regs[i].regmap_entry[hr]=CCREG;
           else
             regs[i].regmap_entry[hr]=-1;
@@ -9507,7 +8436,7 @@ int new_recompile_block(int addr)
           pagespan_alloc(&current,i);
           break;
       }
-      
+
       // Drop the upper half of registers that have become 32-bit
       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
@@ -9525,7 +8454,7 @@ int new_recompile_block(int addr)
       // Create entry (branch target) regmap
       for(hr=0;hr<HOST_REGS;hr++)
       {
-        int r,or,er;
+        int r,or;
         r=current.regmap[hr];
         if(r>=0) {
           if(r!=regmap_pre[i][hr]) {
@@ -9568,7 +8497,7 @@ int new_recompile_block(int addr)
           }
         } else {
           // Branches expect CCREG to be allocated at the target
-          if(regmap_pre[i][hr]==CCREG) 
+          if(regmap_pre[i][hr]==CCREG)
             regs[i].regmap_entry[hr]=CCREG;
           else
             regs[i].regmap_entry[hr]=-1;
@@ -9878,7 +8807,7 @@ int new_recompile_block(int addr)
     {
       cc=0;
     }
-#if defined(PCSX) && !defined(DRC_DBG)
+#if !defined(DRC_DBG)
     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
     {
       // GTE runs in parallel until accessed, divide by 2 for a rough guess
@@ -9919,11 +8848,11 @@ int new_recompile_block(int addr)
     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
     regs[i].waswritten=current.waswritten;
   }
-  
+
   /* Pass 4 - Cull unused host registers */
-  
+
   uint64_t nr=0;
-  
+
   for (i=slen-1;i>=0;i--)
   {
     int hr;
@@ -10065,7 +8994,7 @@ int new_recompile_block(int addr)
     }
     // Save it
     needed_reg[i]=nr;
-    
+
     // Deallocate unneeded registers
     for(hr=0;hr<HOST_REGS;hr++)
     {
@@ -10095,12 +9024,6 @@ int new_recompile_block(int addr)
             d1=dep1[i+1];
             d2=dep2[i+1];
           }
-          if(using_tlb) {
-            if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
-               itype[i+1]==STORE || itype[i+1]==STORELR ||
-               itype[i+1]==C1LS || itype[i+1]==C2LS)
-            map=TLREG;
-          } else
           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
             map=INVCP;
@@ -10155,12 +9078,7 @@ int new_recompile_block(int addr)
               d1=dep1[i];
               d2=dep2[i];
             }
-            if(using_tlb) {
-              if(itype[i]==LOAD || itype[i]==LOADLR ||
-                 itype[i]==STORE || itype[i]==STORELR ||
-                 itype[i]==C1LS || itype[i]==C2LS)
-              map=TLREG;
-            } else if(itype[i]==STORE || itype[i]==STORELR ||
+            if(itype[i]==STORE || itype[i]==STORELR ||
                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
               map=INVCP;
             }
@@ -10194,20 +9112,20 @@ int new_recompile_block(int addr)
       }
     }
   }
-  
+
   /* Pass 5 - Pre-allocate registers */
-  
+
   // If a register is allocated during a loop, try to allocate it for the
   // entire loop, if possible.  This avoids loading/storing registers
   // inside of the loop.
-  
+
   signed char f_regmap[HOST_REGS];
   clear_all_regs(f_regmap);
   for(i=0;i<slen-1;i++)
   {
     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
     {
-      if(ba[i]>=start && ba[i]<(start+i*4)) 
+      if(ba[i]>=start && ba[i]<(start+i*4))
       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
@@ -10255,10 +9173,10 @@ int new_recompile_block(int addr)
             }
           }
           if(ooo[i]) {
-            if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) 
+            if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
               f_regmap[hr]=branch_regs[i].regmap[hr];
           }else{
-            if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) 
+            if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
               f_regmap[hr]=branch_regs[i].regmap[hr];
           }
           // Avoid dirty->clean transition
@@ -10428,10 +9346,10 @@ int new_recompile_block(int addr)
                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
                 {
                   if(ooo[j]) {
-                    if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) 
+                    if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
                       break;
                   }else{
-                    if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) 
+                    if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
                       break;
                   }
                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
@@ -10504,7 +9422,7 @@ int new_recompile_block(int addr)
             regs[k].isconst&=~(1<<HOST_CCREG);
             k++;
           }
-          regs[j].regmap_entry[HOST_CCREG]=CCREG;          
+          regs[j].regmap_entry[HOST_CCREG]=CCREG;
         }
         // Work backwards from the branch target
         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
@@ -10546,18 +9464,18 @@ int new_recompile_block(int addr)
       }
     }
   }
-  
+
   // Cache memory offset or tlb map pointer if a register is available
   #ifndef HOST_IMM_ADDR32
   #ifndef RAM_OFFSET
-  if(using_tlb)
+  if(0)
   #endif
   {
     int earliest_available[HOST_REGS];
     int loop_start[HOST_REGS];
     int score[HOST_REGS];
     int end[HOST_REGS];
-    int reg=using_tlb?MMREG:ROREG;
+    int reg=ROREG;
 
     // Init
     for(hr=0;hr<HOST_REGS;hr++) {
@@ -10726,7 +9644,7 @@ int new_recompile_block(int addr)
     }
   }
   #endif
-  
+
   // This allocates registers (if possible) one instruction prior
   // to use, which can avoid a load-use penalty on certain CPUs.
   for(i=0;i<slen-1;i++)
@@ -10787,7 +9705,7 @@ int new_recompile_block(int addr)
               }
             }
           }
-          // Load source into target register 
+          // Load source into target register
           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
             {
@@ -10804,46 +9722,6 @@ int new_recompile_block(int addr)
               }
             }
           }
-          // Preload map address
-          #ifndef HOST_IMM_ADDR32
-          if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
-            hr=get_reg(regs[i+1].regmap,TLREG);
-            if(hr>=0) {
-              int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
-              if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
-                int nr;
-                if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
-                {
-                  regs[i].regmap[hr]=MGEN1+((i+1)&1);
-                  regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
-                  regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
-                  regs[i].isconst&=~(1<<hr);
-                  regs[i].isconst|=regs[i+1].isconst&(1<<hr);
-                  constmap[i][hr]=constmap[i+1][hr];
-                  regs[i+1].wasdirty&=~(1<<hr);
-                  regs[i].dirty&=~(1<<hr);
-                }
-                else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
-                {
-                  // move it to another register
-                  regs[i+1].regmap[hr]=-1;
-                  regmap_pre[i+2][hr]=-1;
-                  regs[i+1].regmap[nr]=TLREG;
-                  regmap_pre[i+2][nr]=TLREG;
-                  regs[i].regmap[nr]=MGEN1+((i+1)&1);
-                  regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
-                  regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
-                  regs[i].isconst&=~(1<<nr);
-                  regs[i+1].isconst&=~(1<<nr);
-                  regs[i].dirty&=~(1<<nr);
-                  regs[i+1].wasdirty&=~(1<<nr);
-                  regs[i+1].dirty&=~(1<<nr);
-                  regs[i+2].wasdirty&=~(1<<nr);
-                }
-              }
-            }
-          }
-          #endif
           // Address for store instruction (non-constant)
           if(itype[i+1]==STORE||itype[i+1]==STORELR
              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
@@ -10901,7 +9779,7 @@ int new_recompile_block(int addr)
             }
           }
           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
-            if(itype[i+1]==LOAD) 
+            if(itype[i+1]==LOAD)
               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
               hr=get_reg(regs[i+1].regmap,FTEMP);
@@ -10925,126 +9803,11 @@ int new_recompile_block(int addr)
       }
     }
   }
-  
+
   /* Pass 6 - Optimize clean/dirty state */
   clean_registers(0,slen-1,1);
-  
-  /* Pass 7 - Identify 32-bit registers */
-#ifndef FORCE32
-  provisional_r32();
 
-  u_int r32=0;
-  
-  for (i=slen-1;i>=0;i--)
-  {
-    int hr;
-    if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
-    {
-      if(ba[i]<start || ba[i]>=(start+slen*4))
-      {
-        // Branch out of this block, don't need anything
-        r32=0;
-      }
-      else
-      {
-        // Internal branch
-        // Need whatever matches the target
-        // (and doesn't get overwritten by the delay slot instruction)
-        r32=0;
-        int t=(ba[i]-start)>>2;
-        if(ba[i]>start+i*4) {
-          // Forward branch
-          if(!(requires_32bit[t]&~regs[i].was32))
-            r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-        }else{
-          // Backward branch
-          //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
-          //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-          if(!(pr32[t]&~regs[i].was32))
-            r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
-        }
-      }
-      // Conditional branch may need registers for following instructions
-      if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
-      {
-        if(i<slen-2) {
-          r32|=requires_32bit[i+2];
-          r32&=regs[i].was32;
-          // Mark this address as a branch target since it may be called
-          // upon return from interrupt
-          bt[i+2]=1;
-        }
-      }
-      // Merge in delay slot
-      if(!likely[i]) {
-        // These are overwritten unless the branch is "likely"
-        // and the delay slot is nullified if not taken
-        r32&=~(1LL<<rt1[i+1]);
-        r32&=~(1LL<<rt2[i+1]);
-      }
-      // Assume these are needed (delay slot)
-      if(us1[i+1]>0)
-      {
-        if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
-      }
-      if(us2[i+1]>0)
-      {
-        if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
-      }
-      if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
-      {
-        if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
-      }
-      if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
-      {
-        if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
-      }
-    }
-    else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
-    {
-      // SYSCALL instruction (software interrupt)
-      r32=0;
-    }
-    else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
-    {
-      // ERET instruction (return from interrupt)
-      r32=0;
-    }
-    // Check 32 bits
-    r32&=~(1LL<<rt1[i]);
-    r32&=~(1LL<<rt2[i]);
-    if(us1[i]>0)
-    {
-      if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
-    }
-    if(us2[i]>0)
-    {
-      if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
-    }
-    if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
-    {
-      if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
-    }
-    if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
-    {
-      if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
-    }
-    requires_32bit[i]=r32;
-    
-    // Dirty registers which are 32-bit, require 32-bit input
-    // as they will be written as 32-bit values
-    for(hr=0;hr<HOST_REGS;hr++)
-    {
-      if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
-        if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
-          if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
-          requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
-        }
-      }
-    }
-    //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
-  }
-#else
+  /* Pass 7 - Identify 32-bit registers */
   for (i=slen-1;i>=0;i--)
   {
     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
@@ -11057,7 +9820,6 @@ int new_recompile_block(int addr)
       }
     }
   }
-#endif
 
   if(itype[slen-1]==SPAN) {
     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
@@ -11076,26 +9838,6 @@ int new_recompile_block(int addr)
         else printf(" r%d",r);
       }
     }
-#ifndef FORCE32
-    printf(" UU:");
-    for(r=1;r<=CCREG;r++) {
-      if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
-        if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    printf(" 32:");
-    for(r=0;r<=CCREG;r++) {
-      //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
-      if((regs[i].was32>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-#endif
     printf("\n");
     #if defined(__i386__) || defined(__x86_64__)
     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
@@ -11111,29 +9853,7 @@ int new_recompile_block(int addr)
     if((needed_reg[i]>>5)&1) printf("ebp ");
     if((needed_reg[i]>>6)&1) printf("esi ");
     if((needed_reg[i]>>7)&1) printf("edi ");
-    printf("r:");
-    for(r=0;r<=CCREG;r++) {
-      //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
-      if((requires_32bit[i]>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
     printf("\n");
-    /*printf("pr:");
-    for(r=0;r<=CCREG;r++) {
-      //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
-      if((pr32[i]>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
-    printf("\n");*/
     #if defined(__i386__) || defined(__x86_64__)
     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
     printf("dirty: ");
@@ -11217,29 +9937,6 @@ int new_recompile_block(int addr)
       #endif
       printf("\n");
     }
-#ifndef FORCE32
-    printf(" 32:");
-    for(r=0;r<=CCREG;r++) {
-      if((regs[i].is32>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    printf("\n");
-#endif
-    /*printf(" p32:");
-    for(r=0;r<=CCREG;r++) {
-      if((p32[i]>>r)&1) {
-        if(r==CCREG) printf(" CC");
-        else if(r==HIREG) printf(" HI");
-        else if(r==LOREG) printf(" LO");
-        else printf(" r%d",r);
-      }
-    }
-    if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
-    else printf("\n");*/
     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
       #if defined(__i386__) || defined(__x86_64__)
       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
@@ -11266,18 +9963,6 @@ int new_recompile_block(int addr)
       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
       #endif
-#ifndef FORCE32
-      printf(" 32:");
-      for(r=0;r<=CCREG;r++) {
-        if((branch_regs[i].is32>>r)&1) {
-          if(r==CCREG) printf(" CC");
-          else if(r==HIREG) printf(" HI");
-          else if(r==LOREG) printf(" LO");
-          else printf(" r%d",r);
-        }
-      }
-      printf("\n");
-#endif
     }
   }
 #endif // DISASM
@@ -11288,14 +9973,13 @@ int new_recompile_block(int addr)
   cop1_usable=0;
   uint64_t is32_pre=0;
   u_int dirty_pre=0;
-  u_int beginning=(u_int)out;
+  void *beginning=start_block();
   if((u_int)addr&1) {
     ds=1;
     pagespan_ds();
   }
   u_int instr_addr0_override=0;
 
-#ifdef PCSX
   if (start == 0x80030000) {
     // nasty hack for fastbios thing
     // override block entry to this code
@@ -11309,7 +9993,6 @@ int new_recompile_block(int addr)
     emit_cmp(0,1);
     emit_jne((int)new_dyna_leave);
   }
-#endif
   for(i=0;i<slen;i++)
   {
     //if(ds) printf("ds: ");
@@ -11323,8 +10006,6 @@ int new_recompile_block(int addr)
       #ifndef DESTRUCTIVE_WRITEBACK
       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
       {
-        wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
-              unneeded_reg[i],unneeded_reg_upper[i]);
         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
               unneeded_reg[i],unneeded_reg_upper[i]);
       }
@@ -11565,7 +10246,7 @@ int new_recompile_block(int addr)
           // replace it with the new address.
           // Don't add new entries.  We'll insert the
           // ones that actually get used in check_addr().
-          int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
+          u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
           if(ht_bin[0]==vaddr) {
             ht_bin[1]=entry_point;
           }
@@ -11582,45 +10263,32 @@ int new_recompile_block(int addr)
   // Align code
   if(((u_int)out)&7) emit_addnop(13);
   #endif
-  assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
+  assert((u_int)out-(u_int)beginning<MAX_OUTPUT_BLOCK_SIZE);
   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
   memcpy(copy,source,slen*4);
   copy+=slen*4;
-  
-  #ifdef __arm__
-  __clear_cache((void *)beginning,out);
-  #endif
-  
+
+  end_block(beginning);
+
   // If we're within 256K of the end of the buffer,
   // start over from the beginning. (Is 256K enough?)
   if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
-  
+
   // Trap writes to any of the pages we compiled
   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
     invalid_code[i]=0;
-#ifndef DISABLE_TLB
-    memory_map[i]|=0x40000000;
-    if((signed int)start>=(signed int)0xC0000000) {
-      assert(using_tlb);
-      j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
-      invalid_code[j]=0;
-      memory_map[j]|=0x40000000;
-      //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
-    }
-#endif
   }
   inv_code_start=inv_code_end=~0;
-#ifdef PCSX
+
   // for PCSX we need to mark all mirrors too
   if(get_page(start)<(RAM_SIZE>>12))
     for(i=start>>12;i<=(start+slen*4)>>12;i++)
       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
-#endif
-  
+
   /* Pass 10 - Free memory by expiring oldest blocks */
-  
+
   int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
   while(expirep!=end)
   {
@@ -11644,7 +10312,7 @@ int new_recompile_block(int addr)
       case 2:
         // Clear hash table
         for(i=0;i<32;i++) {
-          int *ht_bin=hash_table[((expirep&2047)<<5)+i];
+          u_int *ht_bin=hash_table[((expirep&2047)<<5)+i];
           if((ht_bin[3]>>shift)==(base>>shift) ||
              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
@@ -11662,7 +10330,7 @@ int new_recompile_block(int addr)
       case 3:
         // Clear jump_out
         #ifdef __arm__
-        if((expirep&2047)==0) 
+        if((expirep&2047)==0)
           do_clear_cache();
         #endif
         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
diff --git a/libpcsxcore/new_dynarec/new_dynarec_config.h b/libpcsxcore/new_dynarec/new_dynarec_config.h
new file mode 100644
index 0000000..fbd08ac
--- /dev/null
+++ b/libpcsxcore/new_dynarec/new_dynarec_config.h
@@ -0,0 +1,12 @@
+
+
+#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
+#define USE_MINI_HT 1
+//#define REG_PREFETCH 1
+
+#if defined(__MACH__) || defined(VITA)
+#define NO_WRITE_EXEC 1
+#endif
+#ifdef VITA
+#define BASE_ADDR_DYNAMIC 1
+#endif