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| author | notaz | 2011-03-08 15:41:55 +0200 |
|---|---|---|
| committer | notaz | 2011-03-08 15:59:09 +0200 |
| commit | b12c9fb877aa40666d5ad367ecca152cfa2edb64 (patch) | |
| tree | 6d3a68a94fb373b7a030deca329427ba7da30fbc /libpcsxcore | |
| parent | b8e744ce04eaf294d0c06aca6b20b410122bf4ed (diff) | |
| download | pcsx_rearmed-b12c9fb877aa40666d5ad367ecca152cfa2edb64.tar.gz pcsx_rearmed-b12c9fb877aa40666d5ad367ecca152cfa2edb64.tar.bz2 pcsx_rearmed-b12c9fb877aa40666d5ad367ecca152cfa2edb64.zip | |
drc: update invalid_code for RAM when mirrors are touched
the memhandlers always check RAM locations, even when something
writes to the mirrors.
Diffstat (limited to 'libpcsxcore')
| -rw-r--r-- | libpcsxcore/new_dynarec/new_dynarec.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index edd1413..6f5ca8f 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -1186,6 +1186,9 @@ void invalidate_block(u_int block) // Don't trap writes invalid_code[block]=1; +#ifdef PCSX + invalid_code[((u_int)0x80000000>>12)|page]=1; +#endif #ifndef DISABLE_TLB // If there is a valid TLB entry for this page, remove write protect if(tlb_LUT_w[block]) { @@ -11032,6 +11035,12 @@ int new_recompile_block(int addr) } #endif } +#ifdef PCSX + // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE + if(get_page(start)<(RAM_SIZE>>12)) + for(i=start>>12;i<=(start+slen*4)>>12;i++) + invalid_code[((u_int)0x80000000>>12)|i]=0; +#endif /* Pass 10 - Free memory by expiring oldest blocks */ |