diff options
| -rw-r--r-- | libpcsxcore/new_dynarec/assem_arm.c | 9 | ||||
| -rw-r--r-- | libpcsxcore/new_dynarec/emu_if.c | 45 | ||||
| -rw-r--r-- | libpcsxcore/new_dynarec/new_dynarec.c | 2 | ||||
| -rw-r--r-- | libpcsxcore/new_dynarec/pcsxmem.c | 8 | ||||
| -rw-r--r-- | libpcsxcore/new_dynarec/pcsxmem_inline.c | 11 |
5 files changed, 59 insertions, 16 deletions
diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c index 9440bb8..3a86dba 100644 --- a/libpcsxcore/new_dynarec/assem_arm.c +++ b/libpcsxcore/new_dynarec/assem_arm.c @@ -4499,6 +4499,7 @@ static void c2op_assemble(int i,struct regstat *i_regs) int shift = (source[i] >> 19) & 1; int lm = (source[i] >> 10) & 1; switch(c2op) { +#ifndef DRC_DBG case GTE_MVMVA: { int v = (source[i] >> 15) & 3; int cv = (source[i] >> 13) & 3; @@ -4577,11 +4578,13 @@ static void c2op_assemble(int i,struct regstat *i_regs) c2op_prologue(c2op,reglist); c2op_call_rgb_func(shift?gteGPL_part_shift:gteGPL_part_noshift,lm,need_ir,need_flags); break; - +#endif default: c2op_prologue(c2op,reglist); - //emit_movimm(source[i],1); // opcode - //emit_writeword(1,(int)&psxRegs.code); +#ifdef DRC_DBG + emit_movimm(source[i],1); // opcode + emit_writeword(1,(int)&psxRegs.code); +#endif emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op])); break; } diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c index 852d881..38d9492 100644 --- a/libpcsxcore/new_dynarec/emu_if.c +++ b/libpcsxcore/new_dynarec/emu_if.c @@ -429,16 +429,18 @@ void do_insn_trace(void) static psxRegisters oldregs; static u32 old_io_addr = (u32)-1; static u32 old_io_data = 0xbad0c0de; + static u32 event_cycles_o[PSXINT_COUNT]; u32 *allregs_p = (void *)&psxRegs; u32 *allregs_o = (void *)&oldregs; u32 io_data; int i; u8 byte; -//last_io_addr = 0x5e2c8; + //last_io_addr = 0x5e2c8; if (f == NULL) f = fopen("tracelog", "wb"); + // log reg changes oldregs.code = psxRegs.code; // don't care for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) { if (allregs_p[i] != allregs_o[i]) { @@ -447,6 +449,17 @@ void do_insn_trace(void) allregs_o[i] = allregs_p[i]; } } + // log event changes + for (i = 0; i < PSXINT_COUNT; i++) { + if (event_cycles[i] != event_cycles_o[i]) { + byte = 0xfc; + fwrite(&byte, 1, 1, f); + fwrite(&i, 1, 1, f); + fwrite(&event_cycles[i], 1, 4, f); + event_cycles_o[i] = event_cycles[i]; + } + } + // log last io if (old_io_addr != last_io_addr) { byte = 0xfd; fwrite(&byte, 1, 1, f); @@ -525,7 +538,8 @@ void do_insn_cmp(void) u32 *allregs_p = (void *)&psxRegs; u32 *allregs_e = (void *)&rregs; static u32 ppc, failcount; - int i, ret, bad = 0; + int i, ret, bad = 0, which_event = -1; + u32 ev_cycles = 0; u8 code; if (f == NULL) @@ -538,18 +552,20 @@ void do_insn_cmp(void) break; if (code == 0xff) break; - if (code == 0xfd) { - if ((ret = fread(&mem_addr, 1, 4, f)) <= 0) - break; + switch (code) { + case 0xfc: + which_event = 0; + fread(&which_event, 1, 1, f); + fread(&ev_cycles, 1, 4, f); continue; - } - if (code == 0xfe) { - if ((ret = fread(&mem_val, 1, 4, f)) <= 0) - break; + case 0xfd: + fread(&mem_addr, 1, 4, f); + continue; + case 0xfe: + fread(&mem_val, 1, 4, f); continue; } - if ((ret = fread(&allregs_e[code], 1, 4, f)) <= 0) - break; + fread(&allregs_e[code], 1, 4, f); } if (ret <= 0) { @@ -561,7 +577,7 @@ void do_insn_cmp(void) psxRegs.cycle = rregs.cycle; psxRegs.CP0.r[9] = rregs.CP0.r[9]; // Count -//if (psxRegs.cycle == 166172) breakme(); + //if (psxRegs.cycle == 166172) breakme(); if (memcmp(&psxRegs, &rregs, offsetof(psxRegisters, intCycle)) == 0 && mem_val == memcheck_read(mem_addr) @@ -582,6 +598,11 @@ void do_insn_cmp(void) goto end; } + if (which_event >= 0 && event_cycles[which_event] != ev_cycles) { + printf("bad ev_cycles #%d: %08x %08x\n", which_event, event_cycles[which_event], ev_cycles); + goto end; + } + if (psxRegs.pc == rregs.pc && bad < 6 && failcount < 32) { static int last_mcycle; if (last_mcycle != psxRegs.cycle >> 20) { diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 05c83c0..5e6e66e 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -9786,7 +9786,7 @@ int new_recompile_block(int addr) { cc=0; } -#ifdef PCSX +#if defined(PCSX) && !defined(DRC_DBG) else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2) { // GTE runs in parallel until accessed, divide by 2 for a rough guess diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c index 4e22230..c9fb5a8 100644 --- a/libpcsxcore/new_dynarec/pcsxmem.c +++ b/libpcsxcore/new_dynarec/pcsxmem.c @@ -77,6 +77,8 @@ static void io_write_sio32(u32 value) sioWrite8((unsigned char)(value >> 24)); } +#ifndef DRC_DBG + static void map_rcnt_rcount0(u32 mode) { if (mode & 0x100) { // pixel clock @@ -117,6 +119,12 @@ static void map_rcnt_rcount2(u32 mode) } } +#else +#define map_rcnt_rcount0(mode) +#define map_rcnt_rcount1(mode) +#define map_rcnt_rcount2(mode) +#endif + #define make_rcnt_funcs(i) \ static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \ static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \ diff --git a/libpcsxcore/new_dynarec/pcsxmem_inline.c b/libpcsxcore/new_dynarec/pcsxmem_inline.c index 210ce0e..305931a 100644 --- a/libpcsxcore/new_dynarec/pcsxmem_inline.c +++ b/libpcsxcore/new_dynarec/pcsxmem_inline.c @@ -5,6 +5,8 @@ * See the COPYING file in the top-level directory. */ +#ifndef DRC_DBG + static int pcsx_direct_read(int type, u_int addr, int cc_adj, int cc, int rs, int rt) { if ((addr & 0xfffff000) == 0x1f801000) { @@ -52,4 +54,13 @@ dont_care: return 1; } +#else + +static int pcsx_direct_read(int type, u_int addr, int cc_adj, int cc, int rs, int rt) +{ + return 0; +} + +#endif + // vim:shiftwidth=2:expandtab |