aboutsummaryrefslogtreecommitdiff
path: root/plugins/gpu_neon/gpu.h
blob: d9ad416eabc980aad0e650d83b65fef472c1229b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
/*
 * (C) Gražvydas "notaz" Ignotas, 2011
 *
 * This work is licensed under the terms of any of these licenses
 * (at your option):
 *  - GNU GPL, version 2 or later.
 *  - GNU LGPL, version 2.1 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

#define CMD_BUFFER_LEN          1024

struct psx_gpu {
  uint16_t vram[1024 * 512];
  uint16_t guard[1024 * 512]; // overdraw guard
  uint32_t cmd_buffer[CMD_BUFFER_LEN];
  uint32_t regs[16];
  union {
    uint32_t reg;
    struct {
      uint32_t tx:4;        //  0 texture page
      uint32_t ty:1;
      uint32_t abr:2;
      uint32_t tp:2;        //  7 t.p. mode (4,8,15bpp)
      uint32_t dtd:1;       //  9 dither
      uint32_t dfe:1;
      uint32_t md:1;        // 11 set mask bit when drawing
      uint32_t me:1;        // 12 no draw on mask
      uint32_t unkn:3;
      uint32_t width1:1;    // 16
      uint32_t width0:2;
      uint32_t dheight:1;   // 19 double height
      uint32_t video:1;     // 20 NTSC,PAL
      uint32_t rgb24:1;
      uint32_t interlace:1; // 22 interlace on
      uint32_t blanking:1;  // 23 display not enabled
      uint32_t unkn2:2;
      uint32_t busy:1;      // 26 !busy drawing
      uint32_t img:1;       // 27 ready to DMA image data
      uint32_t com:1;       // 28 ready for commands
      uint32_t dma:2;       // 29 off, ?, to vram, from vram
      uint32_t lcf:1;       // 31
    };
  } status;
  uint32_t gp0;
  uint32_t ex_regs[8];
  struct {
    int hres, vres;
    int x, y, w, h;
    int x1, x2;
    int y1, y2;
  } screen;
  struct {
    int x, y, w, h;
    short int offset, is_read;
  } dma, dma_start;
  int cmd_len;
  uint32_t zero;
  struct {
    uint32_t fb_dirty:1;
    uint32_t old_interlace:1;
    uint32_t allow_interlace:2;
    uint32_t *frame_count;
    uint32_t *hcnt; /* hsync count */
    struct {
      uint32_t addr;
      uint32_t cycles;
      uint32_t frame;
      uint32_t hcnt;
    } last_list;
    uint32_t last_vram_read_frame;
  } state;
  struct {
    int32_t set:3; /* -1 auto, 0 off, 1-3 fixed */
    int32_t cnt:3; /* amount skipped in a row */
    uint32_t active:1;
    uint32_t allow:1;
    uint32_t frame_ready:1;
    const int *advice;
    uint32_t last_flip_frame;
  } frameskip;
};

extern struct psx_gpu gpu;

extern const unsigned char cmd_lengths[256];

void do_cmd_list(uint32_t *list, int count);

struct rearmed_cbs;

int  renderer_init(void);
void renderer_sync_ecmds(uint32_t * ecmds);
void renderer_update_caches(int x, int y, int w, int h);
void renderer_flush_queues(void);
void renderer_set_interlace(int enable, int is_odd);
void renderer_set_config(const struct rearmed_cbs *config);

int  vout_init(void);
int  vout_finish(void);
void vout_update(void);
void vout_set_config(const struct rearmed_cbs *config);

/* listing these here for correct linkage if rasterizer uses c++ */
struct GPUFreeze;

long GPUinit(void);
long GPUshutdown(void);
void GPUwriteDataMem(uint32_t *mem, int count);
long GPUdmaChain(uint32_t *rambase, uint32_t addr);
void GPUwriteData(uint32_t data);
void GPUreadDataMem(uint32_t *mem, int count);
uint32_t GPUreadData(void);
uint32_t GPUreadStatus(void);
void GPUwriteStatus(uint32_t data);
long GPUfreeze(uint32_t type, struct GPUFreeze *freeze);
void GPUupdateLace(void);
long GPUopen(void **dpy);
long GPUclose(void);
void GPUvBlank(int is_vblank, int lcf);
void GPUrearmedCallbacks(const struct rearmed_cbs *cbs_);

#ifdef __cplusplus
}
#endif