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| author | neonloop | 2021-11-28 17:59:28 +0000 |
|---|---|---|
| committer | neonloop | 2021-11-28 17:59:28 +0000 |
| commit | 909467d97d7ebd5918e426a27b7fb2e3e6b4ac15 (patch) | |
| tree | d7c851267a77b4bdf531bde1884fa7d169eab2bf /patches/gpsp | |
| parent | 08cd83e4b09e18b1107d5f216c97eb9beb09e40e (diff) | |
| download | picoarch-909467d97d7ebd5918e426a27b7fb2e3e6b4ac15.tar.gz picoarch-909467d97d7ebd5918e426a27b7fb2e3e6b4ac15.tar.bz2 picoarch-909467d97d7ebd5918e426a27b7fb2e3e6b4ac15.zip | |
Updates cores
picodrive now supports GG
Diffstat (limited to 'patches/gpsp')
| -rw-r--r-- | patches/gpsp/1000-trimui-build.patch | 70 |
1 files changed, 4 insertions, 66 deletions
diff --git a/patches/gpsp/1000-trimui-build.patch b/patches/gpsp/1000-trimui-build.patch index ecf9623..31007c8 100644 --- a/patches/gpsp/1000-trimui-build.patch +++ b/patches/gpsp/1000-trimui-build.patch @@ -1,10 +1,10 @@ diff --git a/Makefile b/Makefile -index ecefd12..91fc859 100644 +index a0ed865..95c1438 100644 --- a/Makefile +++ b/Makefile -@@ -451,6 +451,20 @@ else ifeq ($(platform), rs90) +@@ -470,6 +470,20 @@ else ifeq ($(platform), miyoo) HAVE_DYNAREC := 1 - CPU_ARCH := mips + CPU_ARCH := arm +else ifeq ($(platform), trimui) + TARGET := $(TARGET_NAME)_libretro.so @@ -23,7 +23,7 @@ index ecefd12..91fc859 100644 # Windows else TARGET := $(TARGET_NAME)_libretro.dll -@@ -477,7 +491,14 @@ endif +@@ -491,7 +505,14 @@ endif ifeq ($(DEBUG), 1) OPTIMIZE := -O0 -g else @@ -39,65 +39,3 @@ index ecefd12..91fc859 100644 endif DEFINES := -DHAVE_STRINGS_H -DHAVE_STDINT_H -DHAVE_INTTYPES_H -D__LIBRETRO__ -DINLINE=inline -Wall -diff --git a/arm/arm_stub.S b/arm/arm_stub.S -index cb68726..6593cf2 100644 ---- a/arm/arm_stub.S -+++ b/arm/arm_stub.S -@@ -79,8 +79,26 @@ _##symbol: - #define IOREG_OFF 0x8D00 - - --#define extract_u16(rd, rs) \ -+#if __ARM_ARCH >= 6 -+#define extract_u16(rd, rs) ;\ - uxth rd, rs -+#else -+#define extract_u16(rd, rs) ;\ -+ bic rd, rs, #0xff000000 ;\ -+ bic rd, rd, #0x00ff0000 -+#endif -+ -+#if __ARM_ARCH >= 6 -+#define sat_u4(rd, rs, shift) ;\ -+ usat rd, #4, rs, shift -+#else -+#define sat_u4(rd, rs, shift) ;\ -+ mov rd, rs, shift ;\ -+ bic rd, rd, rd, asr #31 ;\ -+ sub rd, rd, #15 ;\ -+ and rd, rd, rd, asr #31 ;\ -+ add rd, rd, #15 -+#endif - - @ Will load the register set from memory into the appropriate cached registers. - @ See arm_emit.h for listing explanation. -@@ -538,7 +556,7 @@ return_to_main: - #define execute_store_builder(store_type, str_op, str_op16, load_op, tnum) ;\ - ;\ - defsymbl(execute_store_u##store_type) ;\ -- usat r2, #4, r0, asr #24 /* r2 contains [0-15] */;\ -+ sat_u4(r2, r0, asr #24) /* r2 contains [0-15] */;\ - add r2, r2, #((STORE_TBL_OFF + 16*4*tnum) >> 2) /* add table offset */;\ - ldr pc, [reg_base, r2, lsl #2] /* load handler addr */;\ - nop ;\ -@@ -627,7 +645,7 @@ execute_store_builder(32, str, str, ldr, 2) - @ This is a store that is executed in a strm case (so no SMC checks in-between) - - defsymbl(execute_store_u32_safe) -- usat r2, #4, r0, asr #24 -+ sat_u4(r2, r0, asr #24) - add r2, r2, #((STORE_TBL_OFF + 16*4*3) >> 2) - ldr pc, [reg_base, r2, lsl #2] - nop -@@ -772,9 +790,9 @@ lookup_pc_arm: - defsymbl(execute_load_##load_type) ;\ - .if albits >= 1 ;\ - ror r1, r0, #(albits) /* move alignment bits to MSB */;\ -- usat r1, #4, r1, asr #(24-albits) /* r1 contains [0-15] */;\ -+ sat_u4(r1, r1, asr #(24-albits)) /* r1 contains [0-15] */;\ - .else ;\ -- usat r1, #4, r0, asr #24 /* r1 contains [0-15] */;\ -+ sat_u4(r1, r0, asr #24) /* r1 contains [0-15] */;\ - .endif ;\ - add r1, r1, #((STORE_TBL_OFF + 16*4*tnum) >> 2) /* add table offset */;\ - ldr pc, [reg_base, r1, lsl #2] /* load handler addr */;\ |