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authorDavid Guillen Fandos2021-03-26 13:00:08 +0100
committerDavid Guillen Fandos2021-03-26 23:13:26 +0100
commitd284c868e9e23fb210b8c448cdace39f394cb895 (patch)
tree9da48c56ab7321b0cb1ff03710168502ee05f7b9
parent7ea6c5e247a742af6f7acfbf215c23264410451f (diff)
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Improve ARM store accesses
-rw-r--r--arm/arm_stub.S23
1 files changed, 20 insertions, 3 deletions
diff --git a/arm/arm_stub.S b/arm/arm_stub.S
index 374daba..1db913e 100644
--- a/arm/arm_stub.S
+++ b/arm/arm_stub.S
@@ -559,7 +559,7 @@ ptr_tbl_##store_type: ;\
.word ext_store_u##store_type /* 0x04: I/O regs */;\
.word ext_store_u##store_type /* 0x05: palette RAM */;\
.word ext_store_vram_u##store_type /* 0x06: vram */;\
- .word ext_store_u##store_type /* 0x07: oam ram */;\
+ .word ext_store_oam_ram_u##store_type /* 0x07: oam ram */;\
.word ext_store_u##store_type /* 0x08: gamepak: ignore */;\
.word ext_store_u##store_type /* 0x09: gamepak: ignore */;\
.word ext_store_u##store_type /* 0x0A: gamepak: ignore */;\
@@ -624,6 +624,15 @@ ext_store_vram_u##store_type: ;\
restore_flags() ;\
add pc, lr, #4 /* return */;\
;\
+ext_store_oam_ram_u##store_type: ;\
+ mask_addr_bus16_##store_type(10) /* Mask to mirror memory (+align)*/;\
+ add r2, reg_base, #256 /* r2 = oam ram base */;\
+ store_op r1, [r0, r2] /* store data */;\
+ str r2, [reg_base, #OAM_UPDATED] /* write non zero to signal */;\
+ ldr lr, [reg_base, #REG_SAVE3] /* pop lr off of stack */;\
+ restore_flags() ;\
+ add pc, lr, #4 /* return */;\
+ ;\
3: ;\
ldr lr, [reg_base, #REG_SAVE3] /* restore lr */;\
ldr r0, [lr] /* load PC */;\
@@ -671,6 +680,14 @@ ext_store_vram_u32_safe:
restore_flags()
ldr pc, [reg_base, #REG_SAVE3] @ return
+ext_store_oam_ram_u32_safe:
+ mask_addr_8(10) @ Mask to mirror memory (no need to align!)
+ add r2, reg_base, #256 @ r2 = oam ram base
+ str r1, [r0, r2] @ store data
+ str r2, [reg_base, #OAM_UPDATED] @ store anything non zero here
+ restore_flags()
+ ldr pc, [reg_base, #REG_SAVE3] @ return
+
write_epilogue:
cmp r0, #0 @ check if the write rose an alert
beq 4f @ if not we can exit
@@ -820,8 +837,6 @@ defsymbl(palette_ram)
.space 0x400
defsymbl(palette_ram_converted)
.space 0x400
-defsymbl(oam_ram)
- .space 0x400
defsymbl(spsr)
.space 24
defsymbl(reg_mode)
@@ -829,6 +844,8 @@ defsymbl(reg_mode)
defsymbl(reg)
.space 0x100, 0
+defsymbl(oam_ram)
+ .space 0x400
@ Vita and 3DS (and of course mmap) map their own cache sections through some
@ platform-speficic mechanisms.