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| author | David Guillen Fandos | 2021-03-05 01:15:55 +0100 |
|---|---|---|
| committer | David Guillen Fandos | 2021-03-05 01:15:55 +0100 |
| commit | 7bebd3051c8723f785263f074ac5b180a9cc0852 (patch) | |
| tree | 1776897391bb6ccdbb9fbbc200785c7ee4e86b8c /arm/arm_emit.h | |
| parent | 89bd699837ed5519b19c5ff7a0bc6fd892de416d (diff) | |
| download | picogpsp-7bebd3051c8723f785263f074ac5b180a9cc0852.tar.gz picogpsp-7bebd3051c8723f785263f074ac5b180a9cc0852.tar.bz2 picogpsp-7bebd3051c8723f785263f074ac5b180a9cc0852.zip | |
Remove dead code
Turns out this was not even used! No need to fix it then!
Diffstat (limited to 'arm/arm_emit.h')
| -rw-r--r-- | arm/arm_emit.h | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/arm/arm_emit.h b/arm/arm_emit.h index 7e90b06..669d422 100644 --- a/arm/arm_emit.h +++ b/arm/arm_emit.h @@ -63,12 +63,6 @@ void execute_store_u32_safe(u32 address, u32 source); (((((u32)offset - (u32)source) - 8) >> 2) & 0xFFFFFF) \ -/* reg_base_offset is the amount of bytes after reg_base where the registers - * actually begin. */ - -#define reg_base_offset 1024 - - #define reg_a0 ARMREG_R0 #define reg_a1 ARMREG_R1 #define reg_a2 ARMREG_R2 @@ -486,8 +480,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) u32 reg_use = arm_register_allocation[reg_index]; \ if(reg_use == mem_reg) \ { \ - ARM_LDR_IMM(0, scratch_reg, reg_base, \ - (reg_base_offset + (reg_index * 4))); \ + ARM_LDR_IMM(0, scratch_reg, reg_base, (reg_index * 4)); \ return scratch_reg; \ } \ \ @@ -517,8 +510,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) { \ if(arm_register_allocation[reg_index] == mem_reg) \ { \ - ARM_STR_IMM(0, scratch_reg, reg_base, \ - (reg_base_offset + (reg_index * 4))); \ + ARM_STR_IMM(0, scratch_reg, reg_base, (reg_index * 4)); \ } \ } \ \ @@ -559,7 +551,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) } \ else \ { \ - ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \ + ARM_LDR_IMM(0, ireg, reg_base, (reg_index * 4)); \ } \ } \ \ @@ -572,7 +564,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) } \ else \ { \ - ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \ + ARM_STR_IMM(0, ireg, reg_base, (reg_index * 4)); \ } \ } \ @@ -583,8 +575,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) u32 reg_use = thumb_register_allocation[reg_index]; \ if(reg_use == mem_reg) \ { \ - ARM_LDR_IMM(0, scratch_reg, reg_base, \ - (reg_base_offset + (reg_index * 4))); \ + ARM_LDR_IMM(0, scratch_reg, reg_base, (reg_index * 4)); \ return scratch_reg; \ } \ \ @@ -614,8 +605,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) { \ if(thumb_register_allocation[reg_index] == mem_reg) \ { \ - ARM_STR_IMM(0, scratch_reg, reg_base, \ - (reg_base_offset + (reg_index * 4))); \ + ARM_STR_IMM(0, scratch_reg, reg_base, (reg_index * 4)); \ } \ } \ \ @@ -628,7 +618,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) } \ else \ { \ - ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \ + ARM_LDR_IMM(0, ireg, reg_base, (reg_index * 4)); \ } \ } \ \ @@ -641,7 +631,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) } \ else \ { \ - ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \ + ARM_STR_IMM(0, ireg, reg_base, (reg_index * 4)); \ } \ } \ |