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| author | David Guillen Fandos | 2021-02-12 21:47:35 +0100 |
|---|---|---|
| committer | David Guillen Fandos | 2021-02-12 21:47:35 +0100 |
| commit | 8d52e613c7e4fd2d2dbac751888c20b7983f5e2c (patch) | |
| tree | 05e699df604ea5aa6d654df03bb942415934c50b /arm | |
| parent | 2c6026cfe5cb89b9041ee40230bfef754c21c83d (diff) | |
| download | picogpsp-8d52e613c7e4fd2d2dbac751888c20b7983f5e2c.tar.gz picogpsp-8d52e613c7e4fd2d2dbac751888c20b7983f5e2c.tar.bz2 picogpsp-8d52e613c7e4fd2d2dbac751888c20b7983f5e2c.zip | |
Minor cleanup in ARM and MIPS
Fix some small issues, mainly associated with undefined behaviour
expressions
Diffstat (limited to 'arm')
| -rw-r--r-- | arm/arm_emit.h | 14 | ||||
| -rw-r--r-- | arm/arm_stub.S | 25 |
2 files changed, 7 insertions, 32 deletions
diff --git a/arm/arm_emit.h b/arm/arm_emit.h index 51987a3..7e90b06 100644 --- a/arm/arm_emit.h +++ b/arm/arm_emit.h @@ -115,7 +115,7 @@ void execute_store_u32_safe(u32 address, u32 source); #define reg_x4 ARMREG_R7 #define reg_x5 ARMREG_R8 -#define mem_reg -1 +#define mem_reg (~0U) /* @@ -157,7 +157,7 @@ r15: 0.091287% (-- 100.000000%) */ -s32 arm_register_allocation[] = +u32 arm_register_allocation[] = { reg_x0, /* GBA r0 */ reg_x1, /* GBA r1 */ @@ -194,7 +194,7 @@ s32 arm_register_allocation[] = mem_reg, }; -s32 thumb_register_allocation[] = +u32 thumb_register_allocation[] = { reg_x0, /* GBA r0 */ reg_x1, /* GBA r1 */ @@ -552,7 +552,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) \ void generate_load_reg(u32 ireg, u32 reg_index) \ { \ - s32 load_src = arm_register_allocation[reg_index]; \ + u32 load_src = arm_register_allocation[reg_index]; \ if(load_src != mem_reg) \ { \ ARM_MOV_REG_REG(0, ireg, load_src); \ @@ -565,7 +565,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) \ void generate_store_reg(u32 ireg, u32 reg_index) \ { \ - s32 store_dest = arm_register_allocation[reg_index]; \ + u32 store_dest = arm_register_allocation[reg_index]; \ if(store_dest != mem_reg) \ { \ ARM_MOV_REG_REG(0, store_dest, ireg); \ @@ -621,7 +621,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) \ void generate_load_reg(u32 ireg, u32 reg_index) \ { \ - s32 load_src = thumb_register_allocation[reg_index]; \ + u32 load_src = thumb_register_allocation[reg_index]; \ if(load_src != mem_reg) \ { \ ARM_MOV_REG_REG(0, ireg, load_src); \ @@ -634,7 +634,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) \ void generate_store_reg(u32 ireg, u32 reg_index) \ { \ - s32 store_dest = thumb_register_allocation[reg_index]; \ + u32 store_dest = thumb_register_allocation[reg_index]; \ if(store_dest != mem_reg) \ { \ ARM_MOV_REG_REG(0, store_dest, ireg); \ diff --git a/arm/arm_stub.S b/arm/arm_stub.S index 95b6d73..5a1f6b2 100644 --- a/arm/arm_stub.S +++ b/arm/arm_stub.S @@ -939,31 +939,6 @@ _execute_patch_bios_protect: str r0, [r1, #-REG_BASE_OFFSET] bx lr - -#define save_reg_scratch(reg) ;\ - ldr r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4))] ;\ - str r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4) + 128)] ;\ - -#define restore_reg_scratch(reg) ;\ - ldr r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4) + 128)] ;\ - str r2, [reg_base, #(REG_BASE_OFFSET + (reg * 4))] ;\ - -#define scratch_regs_thumb(type) ;\ - type##_reg_scratch(0) ;\ - type##_reg_scratch(1) ;\ - type##_reg_scratch(2) ;\ - type##_reg_scratch(3) ;\ - type##_reg_scratch(4) ;\ - type##_reg_scratch(5) ;\ - -#define scratch_regs_arm(type) ;\ - type##_reg_scratch(0) ;\ - type##_reg_scratch(1) ;\ - type##_reg_scratch(6) ;\ - type##_reg_scratch(9) ;\ - type##_reg_scratch(12) ;\ - type##_reg_scratch(14) ;\ - .pool .comm memory_map_read 0x8000 |