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author | Twinaphex | 2014-12-20 09:14:38 +0100 |
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committer | Twinaphex | 2014-12-20 09:14:38 +0100 |
commit | d10c4afea252e0eb714fc5367e49bca5c6142c07 (patch) | |
tree | 5073815fb9062b2156488fa45e33da2191676c82 /arm | |
parent | ba834beeb1550e122ecac62609f34cf7c9717139 (diff) | |
download | picogpsp-d10c4afea252e0eb714fc5367e49bca5c6142c07.tar.gz picogpsp-d10c4afea252e0eb714fc5367e49bca5c6142c07.tar.bz2 picogpsp-d10c4afea252e0eb714fc5367e49bca5c6142c07.zip |
Get rid of function_cc
Diffstat (limited to 'arm')
-rw-r--r-- | arm/arm_emit.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arm/arm_emit.h b/arm/arm_emit.h index fe7cc31..db894d1 100644 --- a/arm/arm_emit.h +++ b/arm/arm_emit.h @@ -43,7 +43,7 @@ u32 execute_spsr_restore(u32 address); void execute_swi_arm(u32 pc); void execute_swi_thumb(u32 pc); -void function_cc execute_store_u32_safe(u32 address, u32 source); +void execute_store_u32_safe(u32 address, u32 source); #define write32(value) \ *((u32 *)translation_ptr) = value; \ @@ -671,7 +671,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations) } \ -u32 function_cc execute_spsr_restore_body(u32 pc) +u32 execute_spsr_restore_body(u32 pc) { set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); check_for_interrupts(); |