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| author | David Guillen Fandos | 2021-03-12 17:59:36 +0100 |
|---|---|---|
| committer | David Guillen Fandos | 2021-03-12 18:05:48 +0100 |
| commit | 1e8097ac79bd9026e6dd2d0046a687b8d7bec1aa (patch) | |
| tree | 53dfc26767e50bb74a34870b19e91f942101c1ab /cpu_threaded.c | |
| parent | 462f0e97843fad1e05b72e4512c99bef3347303d (diff) | |
| download | picogpsp-1e8097ac79bd9026e6dd2d0046a687b8d7bec1aa.tar.gz picogpsp-1e8097ac79bd9026e6dd2d0046a687b8d7bec1aa.tar.bz2 picogpsp-1e8097ac79bd9026e6dd2d0046a687b8d7bec1aa.zip | |
Improve and simplify dynarec JIT area.
Also fix a regression on VITA.
Use gcc/OS cache flushing routines for MIPS32 instead of synci
Diffstat (limited to 'cpu_threaded.c')
| -rw-r--r-- | cpu_threaded.c | 29 |
1 files changed, 8 insertions, 21 deletions
diff --git a/cpu_threaded.c b/cpu_threaded.c index 5bd9aed..80a6b4a 100644 --- a/cpu_threaded.c +++ b/cpu_threaded.c @@ -53,7 +53,7 @@ u8* bios_translation_cache_ptr; u8 *rom_translation_ptr = rom_translation_cache; u8 *ram_translation_ptr = ram_translation_cache; u8 *bios_translation_ptr = bios_translation_cache; -#elif defined(ARM_MEMORY_DYNAREC) +#else #ifdef __ANDROID__ // Workaround for 'attempt to map x bytes at offset y' @@ -75,13 +75,6 @@ u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE] u8 *bios_translation_ptr = bios_translation_cache; __asm__(".section .text"); -#else -u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE]; -u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE]; -u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE]; -u8 *rom_translation_ptr = rom_translation_cache; -u8 *ram_translation_ptr = ram_translation_cache; -u8 *bios_translation_ptr = bios_translation_cache; #endif u32 iwram_code_min = 0xFFFFFFFF; @@ -234,19 +227,13 @@ extern u8 bit_count[256]; #define thumb_decode_branch() \ u32 offset = opcode & 0x07FF \ - -#ifdef PSP - -#include "psp/mips_emit.h" - +/* Include the right emitter headers */ +#if defined(MIPS_ARCH) + #include "psp/mips_emit.h" #elif defined(ARM_ARCH) - -#include "arm/arm_emit.h" - + #include "arm/arm_emit.h" #else - -#include "x86/x86_emit.h" - + #include "x86/x86_emit.h" #endif /* Cache invalidation */ @@ -258,7 +245,7 @@ extern u8 bit_count[256]; } #elif defined(VITA) void platform_cache_sync(void *baseaddr, void *endptr) { - sceKernelSyncVMDomain(baseaddr, ((char*)endptr) - ((char*)baseaddr) + 64); + sceKernelSyncVMDomain(sceBlock, baseaddr, ((char*)endptr) - ((char*)baseaddr) + 64); } #elif defined(_3DS) #include "3ds/3ds_utils.h" @@ -271,7 +258,7 @@ extern u8 bit_count[256]; } #elif defined(MIPS_ARCH) void platform_cache_sync(void *baseaddr, void *endptr) { - icache_region_sync(baseaddr, ((char*)endptr) - ((char*)baseaddr)); + __builtin___clear_cache(baseaddr, endptr); } #else /* x86 CPUs have icache consistency checks */ |