original source from gpsp09-2xb_src.tar.bz2

1 files changed, 184 insertions, 0 deletions

diff --git a/disasm.c b/disasm.c
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index 0000000..601584f
--- /dev/null
+++ b/disasm.c
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+/* gameplaySP
+ *
+ * Copyright (C) 2006 Exophase <exophase@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#define arm_decode_data_proc_reg()                                            \
+  u32 rn = (opcode >> 16) & 0x0F;                                             \
+  u32 rd = (opcode >> 12) & 0x0F;                                             \
+  u32 rm = opcode & 0x0F                                                      \
+
+#define arm_decode_data_proc_imm()                                            \
+  u32 rn = (opcode >> 16) & 0x0F;                                             \
+  u32 rd = (opcode >> 12) & 0x0F;                                             \
+  u32 imm;                                                                    \
+  ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2)                         \
+
+#define arm_decode_psr_reg()                                                  \
+  u32 psr_field = (opcode >> 16) & 0x0F;                                      \
+  u32 rd = (opcode >> 12) & 0x0F;                                             \
+  u32 rm = opcode & 0x0F                                                      \
+
+#define arm_decode_psr_imm()                                                  \
+  u32 psr_field = (opcode >> 16) & 0x0F;                                      \
+  u32 rd = (opcode >> 12) & 0x0F;                                             \
+  u32 imm;                                                                    \
+  ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2)                         \
+
+#define arm_decode_branchx()                                                  \
+  u32 rn = opcode & 0x0F                                                      \
+
+#define arm_decode_multiply()                                                 \
+  u32 rd = (opcode >> 16) & 0x0F;                                             \
+  u32 rn = (opcode >> 12) & 0x0F;                                             \
+  u32 rs = (opcode >> 8) & 0x0F;                                              \
+  u32 rm = opcode & 0x0F                                                      \
+
+#define arm_decode_multiply_long()                                            \
+  u32 rdhi = (opcode >> 16) & 0x0F;                                           \
+  u32 rdlo = (opcode >> 12) & 0x0F;                                           \
+  u32 rn = (opcode >> 8) & 0x0F;                                              \
+  u32 rm = opcode & 0x0F                                                      \
+
+#define arm_decode_swap()                                                     \
+  u32 rn = (opcode >> 16) & 0x0F;                                             \
+  u32 rd = (opcode >> 12) & 0x0F;                                             \
+  u32 rm = opcode & 0x0F                                                      \
+
+#define arm_decode_half_trans_r()                                             \
+  u32 rn = (opcode >> 16) & 0x0F;                                             \
+  u32 rd = (opcode >> 12) & 0x0F;                                             \
+  u32 rm = opcode & 0x0F                                                      \
+
+#define arm_decode_half_trans_of()                                            \
+  u32 rn = (opcode >> 16) & 0x0F;                                             \
+  u32 rd = (opcode >> 12) & 0x0F;                                             \
+  u32 offset = ((opcode >> 4) & 0xF0) | (opcode & 0x0F)                       \
+
+#define arm_decode_data_trans_imm()                                           \
+  u32 rn = (opcode >> 16) & 0x0F;                                             \
+  u32 rd = (opcode >> 12) & 0x0F;                                             \
+  u32 offset = opcode & 0x0FFF                                                \
+
+#define arm_decode_data_trans_reg()                                           \
+  u32 rn = (opcode >> 16) & 0x0F;                                             \
+  u32 rd = (opcode >> 12) & 0x0F;                                             \
+  u32 rm = opcode & 0x0F                                                      \
+
+#define arm_decode_block_trans()                                              \
+  u32 rn = (opcode >> 16) & 0x0F;                                             \
+  u32 reg_list = opcode & 0xFFFF                                              \
+
+#define arm_decode_branch()                                                   \
+  s32 offset = ((s32)(opcode & 0xFFFFFF) << 8) >> 6                           \
+
+#define thumb_decode_shift()                                                  \
+  u32 imm = (opcode >> 6) & 0x1F;                                             \
+  u32 rs = (opcode >> 3) & 0x07;                                              \
+  u32 rd = opcode & 0x07                                                      \
+
+#define thumb_decode_add_sub()                                                \
+  u32 rn = (opcode >> 6) & 0x07;                                              \
+  u32 rs = (opcode >> 3) & 0x07;                                              \
+  u32 rd = opcode & 0x07                                                      \
+
+#define thumb_decode_add_sub_imm()                                            \
+  u32 imm = (opcode >> 6) & 0x07;                                             \
+  u32 rs = (opcode >> 3) & 0x07;                                              \
+  u32 rd = opcode & 0x07                                                      \
+
+#define thumb_decode_imm()                                                    \
+  u32 imm = opcode & 0xFF                                                     \
+
+#define thumb_decode_alu_op()                                                 \
+  u32 rs = (opcode >> 3) & 0x07;                                              \
+  u32 rd = opcode & 0x07                                                      \
+
+#define thumb_decode_hireg_op()                                               \
+  u32 rs = (opcode >> 3) & 0x0F;                                              \
+  u32 rd = ((opcode >> 4) & 0x08) | (opcode & 0x07)                           \
+
+#define thumb_decode_mem_reg()                                                \
+  u32 ro = (opcode >> 6) & 0x07;                                              \
+  u32 rb = (opcode >> 3) & 0x07;                                              \
+  u32 rd = opcode & 0x07                                                      \
+
+#define thumb_decode_mem_imm()                                                \
+  u32 imm = (opcode >> 6) & 0x1F;                                             \
+  u32 rb = (opcode >> 3) & 0x07;                                              \
+  u32 rd = opcode & 0x07                                                      \
+
+#define thumb_decode_add_sp()                                                 \
+  u32 imm = opcode & 0x7F                                                     \
+
+#define thumb_decode_rlist()                                                  \
+  u32 reg_list = opcode & 0xFF                                                \
+
+#define thumb_decode_branch_cond()                                            \
+  s32 offset = (s8)(opcode & 0xFF)                                            \
+
+#define thumb_decode_swi()                                                    \
+  u32 comment = opcode & 0xFF                                                 \
+
+#define thumb_decode_branch()                                                 \
+  u32 offset = opcode & 0x07FF                                                \
+
+const char *condition_table[] =
+{
+  "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
+  "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
+};
+
+const char *data_proc_opcode_table[] =
+{
+  "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc",
+  "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn"
+};
+
+
+u32 print_disasm_arm_instruction(u32 opcode)
+{
+  u32 condition = opcode >> 28;
+
+  switch((opcode >> 25) & 0x07)
+  {
+    // Data processing reg, multiply, bx, memory transfer half/byte, swap,
+    // PSR reg
+    case 0x0:
+
+    // Data processing imm, PSR imm
+    case 0x1:
+
+    // Memory transfer imm
+    case 0x2:
+
+    // Memory transfer reg, undefined
+    case 0x3:
+
+    // Block memory transfer
+    case 0x4:
+
+    // Branch
+    case 0x5:
+
+    // Coprocessor
+    case 0x6:
+
+    // Coprocessor, SWI
+    case 0x7:
+  }
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