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| author | twinaphex | 2014-12-10 01:17:37 +0100 |
|---|---|---|
| committer | twinaphex | 2014-12-10 01:17:37 +0100 |
| commit | fe19474dca84b5d00570e3fb5a04c8a359615f70 (patch) | |
| tree | 97ea724a4515ae9bdb76dd1d72082f6ca3d16d5f /disasm.c | |
| parent | afff31b5087e0e12a42c0301057ea56e7c6d2b75 (diff) | |
| download | picogpsp-fe19474dca84b5d00570e3fb5a04c8a359615f70.tar.gz picogpsp-fe19474dca84b5d00570e3fb5a04c8a359615f70.tar.bz2 picogpsp-fe19474dca84b5d00570e3fb5a04c8a359615f70.zip | |
Add macro parameter 'opcode' to some macros
Diffstat (limited to 'disasm.c')
| -rw-r--r-- | disasm.c | 12 |
1 files changed, 6 insertions, 6 deletions
@@ -18,29 +18,29 @@ */ -#define arm_decode_data_proc_reg() \ +#define arm_decode_data_proc_reg(opcode) \ u32 rn = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 rm = opcode & 0x0F \ -#define arm_decode_data_proc_imm() \ +#define arm_decode_data_proc_imm(opcode) \ u32 rn = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 imm; \ ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2) \ -#define arm_decode_psr_reg() \ +#define arm_decode_psr_reg(opcode) \ u32 psr_field = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 rm = opcode & 0x0F \ -#define arm_decode_psr_imm() \ +#define arm_decode_psr_imm(opcode) \ u32 psr_field = (opcode >> 16) & 0x0F; \ u32 rd = (opcode >> 12) & 0x0F; \ u32 imm; \ ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2) \ -#define arm_decode_branchx() \ +#define arm_decode_branchx(opcode) \ u32 rn = opcode & 0x0F \ #define arm_decode_multiply() \ @@ -181,4 +181,4 @@ u32 print_disasm_arm_instruction(u32 opcode) // Coprocessor, SWI case 0x7: - }
\ No newline at end of file + } |