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author | Autechre | 2021-03-27 00:31:51 +0100 |
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committer | GitHub | 2021-03-27 00:31:51 +0100 |
commit | 08d2fa1ebe9e259da228dfa5e5086bd5b62c4347 (patch) | |
tree | 73d1a6eba45d5ed80a698b254332c8e9de2b7bd2 /psp | |
parent | 53cc4a2475ebc8cc510dc97fe8db95939230cee9 (diff) | |
parent | 452ba76ba898c5fc6d176ae8f8e2d77cf15f64a2 (diff) | |
download | picogpsp-08d2fa1ebe9e259da228dfa5e5086bd5b62c4347.tar.gz picogpsp-08d2fa1ebe9e259da228dfa5e5086bd5b62c4347.tar.bz2 picogpsp-08d2fa1ebe9e259da228dfa5e5086bd5b62c4347.zip |
Merge pull request #120 from davidgfnet/master
Fixes and improvements for MIPS and ARM
Diffstat (limited to 'psp')
-rw-r--r-- | psp/mips_emit.h | 58 | ||||
-rw-r--r-- | psp/mips_stub.S | 14 |
2 files changed, 42 insertions, 30 deletions
diff --git a/psp/mips_emit.h b/psp/mips_emit.h index b996f2b..818b724 100644 --- a/psp/mips_emit.h +++ b/psp/mips_emit.h @@ -2512,7 +2512,8 @@ u8 swi_hle_handle[256] = #define ReOff_SaveR1 (21*4) // 3 save scratch regs #define ReOff_SaveR2 (22*4) #define ReOff_SaveR3 (23*4) -#define ReOff_GP_Save (32*4) // GP_SAVE +#define ReOff_OamUpd (33*4) // OAM_UPDATED +#define ReOff_GP_Save (34*4) // GP_SAVE // Saves all regs to their right slot and loads gp #define emit_save_regs(save_a2) { \ @@ -2629,6 +2630,7 @@ typedef struct { bool check_smc; // Whether the memory can contain code bool bus16; // Whether it can only be accessed at 16bit u32 baseptr; // Memory base address. + u32 baseoff; // Offset from base_reg } t_stub_meminfo; // Generates the stub to access memory for a given region, access type, @@ -2737,7 +2739,11 @@ static void emit_pmemld_stub( } else { // Generate upper bits of the addr and do addr mirroring // (The address hi16 is rounded up since load uses signed offset) - mips_emit_lui(reg_rv, ((base_addr + 0x8000) >> 16)); + if (!meminfo->baseoff) { + mips_emit_lui(reg_rv, ((base_addr + 0x8000) >> 16)); + } else { + base_addr = meminfo->baseoff; + } if (region == 2) { // Can't do EWRAM with an `andi` instruction (18 bits mask) @@ -2760,8 +2766,9 @@ static void emit_pmemld_stub( mips_emit_addu(reg_rv, reg_rv, reg_a0); // addr = base + adjusted offset } else { // Generate regular (<=32KB) mirroring - mips_emit_andi(reg_a0, reg_a0, memmask); // Clear upper bits (mirroring) - mips_emit_addu(reg_rv, reg_rv, reg_a0); // Adds to base addr + mips_reg_number breg = (meminfo->baseoff ? reg_base : reg_rv); + mips_emit_andi(reg_temp, reg_a0, memmask); // Clear upper bits (mirroring) + mips_emit_addu(reg_rv, breg, reg_temp); // Adds to base addr } } @@ -2873,9 +2880,8 @@ static void emit_pmemst_stub( // Post processing store: // Signal that OAM was updated if (region == 7) { - u32 palcaddr = (u32)&oam_update; - mips_emit_lui(reg_temp, ((palcaddr + 0x8000) >> 16)); - mips_emit_sw(reg_base, reg_temp, palcaddr & 0xffff); // Write any nonzero data + // Write any nonzero data + mips_emit_sw(reg_base, reg_base, ReOff_OamUpd); generate_function_return_swap_delay(); } else { @@ -3154,7 +3160,7 @@ static void emit_phand( mips_emit_ins(reg_temp, reg_a0, 6, size); // Alignment bits (1 or 2, to bits 6 (and 7) } - unsigned tbloff = 256 + 2048 + 220 + 4 * toff; // Skip regs and palettes + unsigned tbloff = 256 + 3*1024 + 220 + 4 * toff; // Skip regs and RAMs mips_emit_addu(reg_rv, reg_temp, reg_base); // Add to the base_reg the table offset mips_emit_lw(reg_rv, reg_rv, tbloff); // Read addr from table mips_emit_sll(reg_temp, reg_rv, 4); // 26 bit immediate to the MSB @@ -3229,21 +3235,21 @@ void init_emitter() { // Generate memory handlers const t_stub_meminfo ldinfo [] = { - { emit_pmemld_stub, 0, 0x4000, false, false, (u32)bios_rom }, + { emit_pmemld_stub, 0, 0x4000, false, false, (u32)bios_rom, 0}, // 1 Open load / Ignore store - { emit_pmemld_stub, 2, 0x8000, true, false, (u32)ewram }, // memsize wrong on purpose - { emit_pmemld_stub, 3, 0x8000, true, false, (u32)&iwram[0x8000] }, - { emit_pmemld_stub, 4, 0x400, false, false, (u32)io_registers }, - { emit_pmemld_stub, 5, 0x400, false, true, (u32)palette_ram }, - { emit_pmemld_stub, 6, 0x0, false, true, (u32)vram }, // same, vram is a special case - { emit_pmemld_stub, 7, 0x400, false, true, (u32)oam_ram }, - { emit_pmemld_stub, 8, 0x8000, false, false, 0 }, - { emit_pmemld_stub, 9, 0x8000, false, false, 0 }, - { emit_pmemld_stub, 10, 0x8000, false, false, 0 }, - { emit_pmemld_stub, 11, 0x8000, false, false, 0 }, - { emit_pmemld_stub, 12, 0x8000, false, false, 0 }, + { emit_pmemld_stub, 2, 0x8000, true, false, (u32)ewram, 0 }, // memsize wrong on purpose + { emit_pmemld_stub, 3, 0x8000, true, false, (u32)&iwram[0x8000], 0 }, + { emit_pmemld_stub, 4, 0x400, false, false, (u32)io_registers, 0 }, + { emit_pmemld_stub, 5, 0x400, false, true, (u32)palette_ram, 0x100 }, + { emit_pmemld_stub, 6, 0x0, false, true, (u32)vram, 0 }, // same, vram is a special case + { emit_pmemld_stub, 7, 0x400, false, true, (u32)oam_ram, 0x900 }, + { emit_pmemld_stub, 8, 0x8000, false, false, 0, 0 }, + { emit_pmemld_stub, 9, 0x8000, false, false, 0, 0 }, + { emit_pmemld_stub, 10, 0x8000, false, false, 0, 0 }, + { emit_pmemld_stub, 11, 0x8000, false, false, 0, 0 }, + { emit_pmemld_stub, 12, 0x8000, false, false, 0, 0 }, // 13 is EEPROM mapped already (a bit special) - { emit_pmemld_stub, 14, 0, false, false, 0 }, // Mapped via function call + { emit_pmemld_stub, 14, 0, false, false, 0, 0 }, // Mapped via function call // 15 Open load / Ignore store }; @@ -3267,12 +3273,12 @@ void init_emitter() { } const t_stub_meminfo stinfo [] = { - { emit_pmemst_stub, 2, 0x8000, true, false, (u32)ewram }, - { emit_pmemst_stub, 3, 0x8000, true, false, (u32)&iwram[0x8000] }, + { emit_pmemst_stub, 2, 0x8000, true, false, (u32)ewram, 0 }, + { emit_pmemst_stub, 3, 0x8000, true, false, (u32)&iwram[0x8000], 0 }, // I/O is special and mapped with a function call - { emit_palette_hdl, 5, 0x400, false, true, (u32)palette_ram }, - { emit_pmemst_stub, 6, 0x0, false, true, (u32)vram }, // same, vram is a special case - { emit_pmemst_stub, 7, 0x400, false, true, (u32)oam_ram }, + { emit_palette_hdl, 5, 0x400, false, true, (u32)palette_ram, 0x100 }, + { emit_pmemst_stub, 6, 0x0, false, true, (u32)vram, 0 }, // same, vram is a special case + { emit_pmemst_stub, 7, 0x400, false, true, (u32)oam_ram, 0x900 }, }; // Store only for "regular"-ish mem regions diff --git a/psp/mips_stub.S b/psp/mips_stub.S index 3d046d8..1c4ad4b 100644 --- a/psp/mips_stub.S +++ b/psp/mips_stub.S @@ -40,6 +40,7 @@ .global reg_check .global palette_ram .global palette_ram_converted +.global oam_ram .global init_emitter .global mips_lookup_pc .global smc_write @@ -52,6 +53,7 @@ .global reg .global spsr .global reg_mode +.global oam_update # MIPS register layout: @@ -116,13 +118,15 @@ .equ CPU_HALT_STATE, (30 * 4) .equ CHANGED_PC_STATUS, (31 * 4) .equ COMPLETED_FRAME, (32 * 4) -.equ GP_SAVE, (33 * 4) +.equ OAM_UPDATED, (33 * 4) +.equ GP_SAVE, (34 * 4) -.equ SPSR_BASE, (0x900) -.equ REGMODE_BASE, (0x900 + 24) +.equ SPSR_BASE, (0x100 + 0x400 * 3) +.equ REGMODE_BASE, (SPSR_BASE + 24) .equ SUPERVISOR_SPSR, (3 * 4 + SPSR_BASE) .equ SUPERVISOR_LR, ((3 * (7 * 4)) + (6 * 4) + REGMODE_BASE) -.equ FNPTRS_BASE, (0x900 + 220 + 960) +.equ FNPTRS_MEMOPS, (REGMODE_BASE + 196) +.equ FNPTRS_BASE, (FNPTRS_MEMOPS + 960) .set noat .set noreorder @@ -623,6 +627,8 @@ palette_ram: .space 0x400 palette_ram_converted: .space 0x400 +oam_ram: + .space 0x400 spsr: .space 24 # u32[6] reg_mode: |