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Diffstat (limited to 'gba_memory.c')
-rw-r--r--gba_memory.c199
1 files changed, 101 insertions, 98 deletions
diff --git a/gba_memory.c b/gba_memory.c
index af94585..4376cf8 100644
--- a/gba_memory.c
+++ b/gba_memory.c
@@ -35,7 +35,7 @@
gbc_sound_channel[channel].envelope_status = (envelope_ticks != 0); \
gbc_sound_channel[channel].envelope_volume = initial_volume; \
gbc_sound_update = 1; \
- address16(io_registers, address) = value; \
+ address16(io_registers, address) = eswap16(value); \
} \
#define gbc_sound_tone_control_high(channel, address) \
@@ -56,7 +56,7 @@
} \
\
gbc_sound_update = 1; \
- address16(io_registers, address) = value; \
+ address16(io_registers, address) = eswap16(value); \
} \
#define gbc_sound_tone_control_sweep() \
@@ -68,7 +68,7 @@
gbc_sound_channel[0].sweep_ticks = sweep_ticks; \
gbc_sound_channel[0].sweep_initial_ticks = sweep_ticks; \
gbc_sound_update = 1; \
- address16(io_registers, 0x60) = value; \
+ write_ioreg(REG_SOUND1CNT_L, value); \
} \
#define gbc_sound_wave_control() \
@@ -80,7 +80,7 @@
gbc_sound_channel[2].master_enable = 1; \
\
gbc_sound_update = 1; \
- address16(io_registers, 0x70) = value; \
+ write_ioreg(REG_SOUND3CNT_L, value); \
} \
static u32 gbc_sound_wave_volume[4] = { 0, 16384, 8192, 4096 };
@@ -94,7 +94,7 @@ static u32 gbc_sound_wave_volume[4] = { 0, 16384, 8192, 4096 };
gbc_sound_channel[2].wave_volume = \
gbc_sound_wave_volume[(value >> 13) & 0x03]; \
gbc_sound_update = 1; \
- address16(io_registers, 0x72) = value; \
+ write_ioreg(REG_SOUND3CNT_H, value); \
} \
#define gbc_sound_tone_control_high_wave() \
@@ -110,7 +110,7 @@ static u32 gbc_sound_wave_volume[4] = { 0, 16384, 8192, 4096 };
gbc_sound_channel[2].active_flag = 1; \
} \
gbc_sound_update = 1; \
- address16(io_registers, 0x74) = value; \
+ write_ioreg(REG_SOUND3CNT_X, value); \
} \
#define gbc_sound_noise_control() \
@@ -141,7 +141,7 @@ static u32 gbc_sound_wave_volume[4] = { 0, 16384, 8192, 4096 };
gbc_sound_channel[3].envelope_initial_volume; \
} \
gbc_sound_update = 1; \
- address16(io_registers, 0x7C) = value; \
+ write_ioreg(REG_SOUND4CNT_H, value); \
} \
static void gbc_trigger_sound(u32 value)
@@ -156,7 +156,7 @@ static void gbc_trigger_sound(u32 value)
gbc_sound_channel[channel].status =
((value >> (channel + 8)) & 0x01) | ((value >> (channel + 11)) & 0x03);
}
- address16(io_registers, 0x80) = value;
+ write_ioreg(REG_SOUNDCNT_L, value);
}
#define trigger_sound() \
@@ -175,7 +175,7 @@ static void gbc_trigger_sound(u32 value)
sound_reset_fifo(0); \
if((value >> 15) & 0x01) \
sound_reset_fifo(1); \
- address16(io_registers, 0x82) = value; \
+ write_ioreg(REG_SOUNDCNT_H, value); \
} \
static void sound_control_x(u32 value)
@@ -193,8 +193,8 @@ static void sound_control_x(u32 value)
sound_on = 0;
}
- address16(io_registers, 0x84) =
- (address16(io_registers, 0x84) & 0x000F) | (value & 0xFFF0);
+ address16(io_registers, 0x84) = eswap16(
+ (readaddress16(io_registers, 0x84) & 0x000F) | (value & 0xFFF0));
}
#define sound_update_frequency_step(timer_number) \
@@ -238,7 +238,7 @@ static void trigger_timer(u32 timer_number, u32 value)
timer[timer_number].prescale = prescale;
timer[timer_number].irq = (value >> 6) & 0x01;
- address16(io_registers, 0x100 + (timer_number * 4)) = -timer_reload;
+ write_ioreg(REG_TM0D + (timer_number * 2), (u32)(-timer_reload));
timer_reload <<= prescale;
timer[timer_number].count = timer_reload;
@@ -266,7 +266,7 @@ static void trigger_timer(u32 timer_number, u32 value)
timer[timer_number].stop_cpu_ticks = cpu_ticks;
}
}
- address16(io_registers, 0x102 + (timer_number * 4)) = value;
+ write_ioreg(REG_TM0CNT + (timer_number * 2), value);
}
// This table is configured for sequential access on system defaults
@@ -458,7 +458,7 @@ void function_cc write_eeprom(u32 unused_address, u32 value)
if(eeprom_size == EEPROM_512_BYTE)
{
eeprom_address =
- (address16(eeprom_buffer, 0) >> 2) * 8;
+ (readaddress16(eeprom_buffer, 0) >> 2) * 8;
}
else
{
@@ -508,10 +508,10 @@ void function_cc write_eeprom(u32 unused_address, u32 value)
u32 gamepak_index = address >> 15; \
u8 *map = memory_map_read[gamepak_index]; \
\
- if(!map) \
+ if(!map) \
map = load_gamepak_page(gamepak_index & 0x3FF); \
\
- value = address##type(map, address & 0x7FFF) \
+ value = readaddress##type(map, address & 0x7FFF) \
#define read_open8() \
if(!(reg[REG_CPSR] & 0x20)) \
@@ -580,29 +580,29 @@ u32 function_cc read_eeprom(void)
case 0x00: \
/* BIOS */ \
if(reg[REG_PC] >= 0x4000) \
- value = address##type(&bios_read_protect, address & 0x03); \
+ value = readaddress##type(&bios_read_protect, address & 0x03); \
else \
- value = address##type(bios_rom, address & 0x3FFF); \
+ value = readaddress##type(bios_rom, address & 0x3FFF); \
break; \
\
case 0x02: \
/* external work RAM */ \
- value = address##type(ewram, (address & 0x3FFFF)); \
+ value = readaddress##type(ewram, (address & 0x3FFFF)); \
break; \
\
case 0x03: \
/* internal work RAM */ \
- value = address##type(iwram, (address & 0x7FFF) + 0x8000); \
+ value = readaddress##type(iwram, (address & 0x7FFF) + 0x8000); \
break; \
\
case 0x04: \
/* I/O registers */ \
- value = address##type(io_registers, address & 0x3FF); \
+ value = readaddress##type(io_registers, address & 0x3FF); \
break; \
\
case 0x05: \
/* palette RAM */ \
- value = address##type(palette_ram, address & 0x3FF); \
+ value = readaddress##type(palette_ram, address & 0x3FF); \
break; \
\
case 0x06: \
@@ -611,12 +611,12 @@ u32 function_cc read_eeprom(void)
if(address > 0x18000) \
address -= 0x8000; \
\
- value = address##type(vram, address); \
+ value = readaddress##type(vram, address); \
break; \
\
case 0x07: \
/* OAM RAM */ \
- value = address##type(oam_ram, address & 0x3FF); \
+ value = readaddress##type(oam_ram, address & 0x3FF); \
break; \
\
case 0x08: \
@@ -660,12 +660,12 @@ static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
if(dma[dma_number].start_type == DMA_INACTIVE)
{
u32 start_type = (value >> 12) & 0x03;
- u32 dest_address = address32(io_registers, (dma_number * 12) + 0xB4) &
+ u32 dest_address = readaddress32(io_registers, (dma_number * 12) + 0xB4) &
0xFFFFFFF;
dma[dma_number].dma_channel = dma_number;
dma[dma_number].source_address =
- address32(io_registers, (dma_number * 12) + 0xB0) & 0xFFFFFFF;
+ readaddress32(io_registers, (dma_number * 12) + 0xB0) & 0xFFFFFFF;
dma[dma_number].dest_address = dest_address;
dma[dma_number].source_direction = (value >> 7) & 0x03;
dma[dma_number].repeat_type = (value >> 9) & 0x01;
@@ -686,7 +686,7 @@ static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
}
else
{
- u32 length = address16(io_registers, (dma_number * 12) + 0xB8);
+ u32 length = read_ioreg(REG_DMA0CNT_L + (dma_number * 6));
if((dma_number == 3) && ((dest_address >> 24) == 0x0D) &&
((length & 0x1F) == 17))
@@ -708,7 +708,7 @@ static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
dma[dma_number].dest_direction = (value >> 5) & 0x03;
}
- address16(io_registers, (dma_number * 12) + 0xBA) = value;
+ write_ioreg(REG_DMA0CNT_H + (dma_number * 6), value);
if(start_type == DMA_START_IMMEDIATELY)
return dma_transfer(dma + dma_number);
}
@@ -717,7 +717,7 @@ static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
{
dma[dma_number].start_type = DMA_INACTIVE;
dma[dma_number].direct_sound_channel = DMA_NO_DIRECT_SOUND;
- address16(io_registers, (dma_number * 12) + 0xBA) = value;
+ write_ioreg(REG_DMA0CNT_H + (dma_number * 6), value);
}
return CPU_ALERT_NONE;
@@ -731,10 +731,10 @@ static cpu_alert_type trigger_dma(u32 dma_number, u32 value)
value = ((address8(io_registers, address + 1)) << 8) | value \
#define access_register16_high(address) \
- value = (value << 16) | (address16(io_registers, address)) \
+ value = (value << 16) | (readaddress16(io_registers, address)) \
#define access_register16_low(address) \
- value = ((address16(io_registers, address + 2)) << 16) | value \
+ value = ((readaddress16(io_registers, address + 2)) << 16) | value \
cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
{
@@ -743,7 +743,7 @@ cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
{
case 0x00:
{
- u32 dispcnt = io_registers[REG_DISPCNT];
+ u32 dispcnt = read_ioreg(REG_DISPCNT);
if((value & 0x07) != (dispcnt & 0x07))
reg[OAM_UPDATED] = 1;
@@ -768,28 +768,28 @@ cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
access_register8_low(0x28);
access_register16_low(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x28) = value;
+ address32(io_registers, 0x28) = eswap32(value);
break;
case 0x29:
access_register8_high(0x28);
access_register16_low(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x28) = value;
+ address32(io_registers, 0x28) = eswap32(value);
break;
case 0x2A:
access_register8_low(0x2A);
access_register16_high(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x28) = value;
+ address32(io_registers, 0x28) = eswap32(value);
break;
case 0x2B:
access_register8_high(0x2A);
access_register16_high(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x28) = value;
+ address32(io_registers, 0x28) = eswap32(value);
break;
// BG2 reference Y
@@ -797,28 +797,28 @@ cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
access_register8_low(0x2C);
access_register16_low(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x2C) = value;
+ address32(io_registers, 0x2C) = eswap32(value);
break;
case 0x2D:
access_register8_high(0x2C);
access_register16_low(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x2C) = value;
+ address32(io_registers, 0x2C) = eswap32(value);
break;
case 0x2E:
access_register8_low(0x2E);
access_register16_high(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x2C) = value;
+ address32(io_registers, 0x2C) = eswap32(value);
break;
case 0x2F:
access_register8_high(0x2E);
access_register16_high(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x2C) = value;
+ address32(io_registers, 0x2C) = eswap32(value);
break;
// BG3 reference X
@@ -826,28 +826,28 @@ cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
access_register8_low(0x38);
access_register16_low(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x38) = value;
+ address32(io_registers, 0x38) = eswap32(value);
break;
case 0x39:
access_register8_high(0x38);
access_register16_low(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x38) = value;
+ address32(io_registers, 0x38) = eswap32(value);
break;
case 0x3A:
access_register8_low(0x3A);
access_register16_high(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x38) = value;
+ address32(io_registers, 0x38) = eswap32(value);
break;
case 0x3B:
access_register8_high(0x3A);
access_register16_high(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x38) = value;
+ address32(io_registers, 0x38) = eswap32(value);
break;
// BG3 reference Y
@@ -855,28 +855,28 @@ cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
access_register8_low(0x3C);
access_register16_low(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x3C) = value;
+ address32(io_registers, 0x3C) = eswap32(value);
break;
case 0x3D:
access_register8_high(0x3C);
access_register16_low(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x3C) = value;
+ address32(io_registers, 0x3C) = eswap32(value);
break;
case 0x3E:
access_register8_low(0x3E);
access_register16_high(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x3C) = value;
+ address32(io_registers, 0x3C) = eswap32(value);
break;
case 0x3F:
access_register8_high(0x3E);
access_register16_high(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x3C) = value;
+ address32(io_registers, 0x3C) = eswap32(value);
break;
// Sound 1 control sweep
@@ -1160,18 +1160,17 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
{
case 0x00:
{
- u32 dispcnt = io_registers[REG_DISPCNT];
+ u32 dispcnt = read_ioreg(REG_DISPCNT);
if((value & 0x07) != (dispcnt & 0x07))
reg[OAM_UPDATED] = 1;
- address16(io_registers, 0x00) = value;
+ write_ioreg(REG_DISPCNT, value);
break;
}
// DISPSTAT
case 0x04:
- address16(io_registers, 0x04) =
- (address16(io_registers, 0x04) & 0x07) | (value & ~0x07);
+ write_ioreg(REG_DISPSTAT, (read_ioreg(REG_DISPSTAT) & 0x07) | (value & ~0x07));
break;
// VCOUNT
@@ -1182,26 +1181,26 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
case 0x28:
access_register16_low(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x28) = value;
+ address32(io_registers, 0x28) = eswap32(value);
break;
case 0x2A:
access_register16_high(0x28);
affine_reference_x[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x28) = value;
+ address32(io_registers, 0x28) = eswap32(value);
break;
// BG2 reference Y
case 0x2C:
access_register16_low(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x2C) = value;
+ address32(io_registers, 0x2C) = eswap32(value);
break;
case 0x2E:
access_register16_high(0x2C);
affine_reference_y[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x2C) = value;
+ address32(io_registers, 0x2C) = eswap32(value);
break;
// BG3 reference X
@@ -1209,26 +1208,26 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
case 0x38:
access_register16_low(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x38) = value;
+ address32(io_registers, 0x38) = eswap32(value);
break;
case 0x3A:
access_register16_high(0x38);
affine_reference_x[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x38) = value;
+ address32(io_registers, 0x38) = eswap32(value);
break;
// BG3 reference Y
case 0x3C:
access_register16_low(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x3C) = value;
+ address32(io_registers, 0x3C) = eswap32(value);
break;
case 0x3E:
access_register16_high(0x3C);
affine_reference_y[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x3C) = value;
+ address32(io_registers, 0x3C) = eswap32(value);
break;
// Sound 1 control sweep
@@ -1313,7 +1312,7 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
case 0x9D:
case 0x9E:
gbc_sound_wave_update = 1;
- address16(io_registers, address) = value;
+ address16(io_registers, address) = eswap16(value);
break;
// Sound FIFO A
@@ -1382,7 +1381,7 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
// Interrupt flag
case 0x202:
- address16(io_registers, 0x202) &= ~value;
+ write_ioreg(REG_IF, read_ioreg(REG_IF) & (~value));
break;
// WAITCNT
@@ -1399,7 +1398,7 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
return CPU_ALERT_HALT;
default:
- address16(io_registers, address) = value;
+ address16(io_registers, address) = eswap16(value);
break;
}
@@ -1414,25 +1413,25 @@ cpu_alert_type function_cc write_io_register32(u32 address, u32 value)
// BG2 reference X
case 0x28:
affine_reference_x[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x28) = value;
+ address32(io_registers, 0x28) = eswap32(value);
break;
// BG2 reference Y
case 0x2C:
affine_reference_y[0] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x2C) = value;
+ address32(io_registers, 0x2C) = eswap32(value);
break;
// BG3 reference X
case 0x38:
affine_reference_x[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x38) = value;
+ address32(io_registers, 0x38) = eswap32(value);
break;
// BG3 reference Y
case 0x3C:
affine_reference_y[1] = (s32)(value << 4) >> 4;
- address32(io_registers, 0x3C) = value;
+ address32(io_registers, 0x3C) = eswap32(value);
break;
// Sound FIFO A
@@ -1468,7 +1467,7 @@ cpu_alert_type function_cc write_io_register32(u32 address, u32 value)
#define write_palette16(address, value) \
{ \
u32 palette_address = address; \
- address16(palette_ram, palette_address) = value; \
+ address16(palette_ram, palette_address) = eswap16(value); \
convert_palette(value); \
address16(palette_ram_converted, palette_address) = value; \
} \
@@ -1478,11 +1477,11 @@ cpu_alert_type function_cc write_io_register32(u32 address, u32 value)
u32 palette_address = address; \
u32 value_high = value >> 16; \
u32 value_low = value & 0xFFFF; \
- address32(palette_ram, palette_address) = value; \
+ address32(palette_ram, palette_address) = eswap32(value); \
convert_palette(value_high); \
+ address16(palette_ram_converted, palette_address + 2) = value_high; \
convert_palette(value_low); \
- value = (value_high << 16) | value_low; \
- address32(palette_ram_converted, palette_address) = value; \
+ address16(palette_ram_converted, palette_address) = value_low; \
} \
@@ -1616,13 +1615,13 @@ void function_cc write_backup(u32 address, u32 value)
#define write_vram8() \
address &= ~0x01; \
- address16(vram, address) = ((value << 8) | value) \
+ address16(vram, address) = eswap16((value << 8) | value) \
#define write_vram16() \
- address16(vram, address) = value \
+ address16(vram, address) = eswap16(value) \
#define write_vram32() \
- address32(vram, address) = value \
+ address32(vram, address) = eswap32(value) \
// RTC code derived from VBA's (due to lack of any real publically available
// documentation...)
@@ -1682,7 +1681,7 @@ static u32 encode_bcd(u8 value)
if(!map) \
map = load_gamepak_page(rtc_page_index & 0x3FF); \
\
- address16(map, update_address & 0x7FFF) = _value \
+ address16(map, update_address & 0x7FFF) = eswap16(_value) \
void function_cc write_rtc(u32 address, u32 value)
{
@@ -1897,12 +1896,12 @@ void function_cc write_rtc(u32 address, u32 value)
{ \
case 0x02: \
/* external work RAM */ \
- address##type(ewram, (address & 0x3FFFF)) = value; \
+ address##type(ewram, (address & 0x3FFFF)) = eswap##type(value); \
break; \
\
case 0x03: \
/* internal work RAM */ \
- address##type(iwram, (address & 0x7FFF) + 0x8000) = value; \
+ address##type(iwram, (address & 0x7FFF) + 0x8000) = eswap##type(value); \
break; \
\
case 0x04: \
@@ -1926,7 +1925,7 @@ void function_cc write_rtc(u32 address, u32 value)
case 0x07: \
/* OAM RAM */ \
reg[OAM_UPDATED] = 1; \
- address##type(oam_ram, address & 0x3FF) = value; \
+ address##type(oam_ram, address & 0x3FF) = eswap##type(value); \
break; \
\
case 0x08: \
@@ -2544,26 +2543,26 @@ dma_region_type dma_region_map[16] =
} \
#define dma_read_iwram(type, transfer_size) \
- read_value = address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) \
+ read_value = readaddress##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF)\
#define dma_read_vram(type, transfer_size) \
- read_value = address##transfer_size(vram, type##_ptr & 0x1FFFF) \
+ read_value = readaddress##transfer_size(vram, type##_ptr & 0x1FFFF) \
#define dma_read_io(type, transfer_size) \
- read_value = address##transfer_size(io_registers, type##_ptr & 0x7FFF) \
+ read_value = readaddress##transfer_size(io_registers, type##_ptr & 0x7FFF) \
#define dma_read_oam_ram(type, transfer_size) \
- read_value = address##transfer_size(oam_ram, type##_ptr & 0x3FF) \
+ read_value = readaddress##transfer_size(oam_ram, type##_ptr & 0x3FF) \
#define dma_read_palette_ram(type, transfer_size) \
- read_value = address##transfer_size(palette_ram, type##_ptr & 0x3FF) \
+ read_value = readaddress##transfer_size(palette_ram, type##_ptr & 0x3FF) \
#define dma_read_ewram(type, transfer_size) \
- read_value = address##transfer_size(ewram, type##_ptr & 0x3FFFF) \
+ read_value = readaddress##transfer_size(ewram, type##_ptr & 0x3FFFF) \
#define dma_read_gamepak(type, transfer_size) \
dma_gamepak_check_region(type); \
- read_value = address##transfer_size(type##_address_block, \
+ read_value = readaddress##transfer_size(type##_address_block, \
type##_ptr & 0x7FFF) \
// DMAing from the BIOS is funny, just returns 0..
@@ -2575,17 +2574,20 @@ dma_region_type dma_region_map[16] =
read_value = read_memory##transfer_size(type##_ptr) \
#define dma_write_iwram(type, transfer_size) \
- address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) = read_value; \
+ address##transfer_size(iwram + 0x8000, type##_ptr & 0x7FFF) = \
+ eswap##transfer_size(read_value); \
smc_trigger |= address##transfer_size(iwram, type##_ptr & 0x7FFF) \
#define dma_write_vram(type, transfer_size) \
- address##transfer_size(vram, type##_ptr & 0x1FFFF) = read_value \
+ address##transfer_size(vram, type##_ptr & 0x1FFFF) = \
+ eswap##transfer_size(read_value) \
#define dma_write_io(type, transfer_size) \
write_io_register##transfer_size(type##_ptr & 0x3FF, read_value) \
#define dma_write_oam_ram(type, transfer_size) \
- address##transfer_size(oam_ram, type##_ptr & 0x3FF) = read_value \
+ address##transfer_size(oam_ram, type##_ptr & 0x3FF) = \
+ eswap##transfer_size(read_value) \
#define dma_write_palette_ram(type, transfer_size) \
write_palette##transfer_size(type##_ptr & 0x3FF, read_value) \
@@ -2594,7 +2596,8 @@ dma_region_type dma_region_map[16] =
write_memory##transfer_size(type##_ptr, read_value) \
#define dma_write_ewram(type, transfer_size) \
- address##transfer_size(ewram, type##_ptr & 0x3FFFF) = read_value; \
+ address##transfer_size(ewram, type##_ptr & 0x3FFFF) = \
+ eswap##transfer_size(read_value); \
smc_trigger |= address##transfer_size(ewram, \
(type##_ptr & 0x3FFFF) + 0x40000) \
@@ -3034,8 +3037,8 @@ cpu_alert_type dma_transfer(dma_transfer_type *dma)
(dma->start_type == DMA_START_IMMEDIATELY))
{
dma->start_type = DMA_INACTIVE;
- address16(io_registers, (dma->dma_channel * 12) + 0xBA) &=
- (~0x8000);
+ address16(io_registers, (dma->dma_channel * 12) + 0xBA) =
+ readaddress16(io_registers, (dma->dma_channel * 12) + 0xBA) & (~0x8000);
}
if(dma->irq)
@@ -3208,13 +3211,13 @@ void init_memory(void)
memset(ewram, 0, sizeof(ewram));
memset(vram, 0, sizeof(vram));
- io_registers[REG_DISPCNT] = 0x80;
- io_registers[REG_P1] = 0x3FF;
- io_registers[REG_BG2PA] = 0x100;
- io_registers[REG_BG2PD] = 0x100;
- io_registers[REG_BG3PA] = 0x100;
- io_registers[REG_BG3PD] = 0x100;
- io_registers[REG_RCNT] = 0x8000;
+ write_ioreg(REG_DISPCNT, 0x80);
+ write_ioreg(REG_P1, 0x3FF);
+ write_ioreg(REG_BG2PA, 0x100);
+ write_ioreg(REG_BG2PD, 0x100);
+ write_ioreg(REG_BG3PA, 0x100);
+ write_ioreg(REG_BG3PD, 0x100);
+ write_ioreg(REG_RCNT, 0x8000);
backup_type = BACKUP_NONE;
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 11:58:00 +0000