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2021-05-19Minor optimizationDavid Guillen Fandos
2021-05-17Add ROM mirroring and fix mult. cycle countDavid Guillen Fandos
This should correct some minor issues in some games.
2021-05-07Small optimization (~2-4%) and whitespace cleanup!David Guillen Fandos
Cleans up a ton of whitespace in cpu.c (like 100KB!) and improves readability of some massive decode statements. Added an optimization for PC-relative loads (pool load) in ROM (since it's read only and cannot possibily change) that directly emits an immediate load. This is way faster, specially in MIPS/x86, ARM can be even faster if we rewrite the immediate load macros to also use a pool.
2021-05-05Fix small buf and add cheat error messagesDavid Guillen Fandos
Some minor formating too
2021-05-05Adding Code Breaker cheat supportDavid Guillen Fandos
This works on both interpreter and dynarec. Tested in MIPS, ARM and x86, still needs some more testing, some edge cases can be buggy.
2021-04-27Fix Vita port and likely some Linux/Android hidden issuesDavid Guillen Fandos
Using an invalid SP makes Vita crash (for an unkown reason) and makes things like C signal handlers crash (luckily Retroarch doesn't use them). It is also a violation of the ABI and not a great idea. Recycled some little used registers to free SP. Perf should be roughly the same.
2021-04-03Add instruction tracing, for testing purposesDavid Guillen Fandos
2021-03-16Simplify open load handling for MIPS and fix other archesDavid Guillen Fandos
Also rewrite a bit memory handlers for smaller functions.
2021-03-05Remove dead codeDavid Guillen Fandos
Turns out this was not even used! No need to fix it then!
2021-02-12Minor cleanup in ARM and MIPSDavid Guillen Fandos
Fix some small issues, mainly associated with undefined behaviour expressions
2021-02-10Move r15 to reg_a0 (instead of reg_mem)David Guillen Fandos
I think this does not make a difference at all in the code, since PC is treated in a special way anyway (reloaded with an immediate when read and treated as an indirect branch when written). However for the sake of completeness I'm undoing what I did. (The comma fix stays :P)
2021-02-10Fix ARM dynarecDavid Guillen Fandos
Turns out there were a couple of very interesting and hard to track bugs. A missing comma made the reg list too short, leaving the 31th element at the mercy of the linker ordering algorithm, which seems to work in some cases depending on the compiler version. Also the cache flush code seemed not to work on my machine (OGA), not sure why it wored in the past :/
2020-10-08Add more forward declarationstwinaphex
2020-10-08Add forward declarationstwinaphex
2016-10-03(VITA) Dynarec workingFrancisco José García García
2016-08-14(VITA) Dynarec WIPFrancisco José García García
2016-08-08(VITA) Dynarec WIPFrancisco José García García
2014-12-20Get rid of function_ccTwinaphex
2014-12-11Reimplement cache invalidation codetwinaphex
2014-12-10cleanupsaliaspider
2014-12-10Add macro parameter 'opcode' to some macrostwinaphex
2014-12-10fix compiler error: initializer element is not a compile-time constantaliaspider
2012-09-18merge an assorment of calc84maniac's fixes.notaz
2011-09-08handle div by 0notaz
2011-09-06enable -Wall and fix warnings reported by itnotaz
2011-09-02move platform-independent stuff out of /gp2x.notaz