aboutsummaryrefslogtreecommitdiff
path: root/audio/softsynth/opl/dosbox.cpp
diff options
context:
space:
mode:
authorDreammaster2013-02-15 08:25:09 -0500
committerDreammaster2013-02-15 08:25:09 -0500
commitbb3285d933419b6bdefadc55a6e320855ff0dd27 (patch)
tree2df613c52f854c33cff660ed1b064e2996ed80bb /audio/softsynth/opl/dosbox.cpp
parentd1a19a1d4c3e20b57250e73141d81e8d9b44a2a1 (diff)
parentadc338cd719179a94ff470b28e9584262d7b47e8 (diff)
downloadscummvm-rg350-bb3285d933419b6bdefadc55a6e320855ff0dd27.tar.gz
scummvm-rg350-bb3285d933419b6bdefadc55a6e320855ff0dd27.tar.bz2
scummvm-rg350-bb3285d933419b6bdefadc55a6e320855ff0dd27.zip
Merge branch 'master' into hopkins
Diffstat (limited to 'audio/softsynth/opl/dosbox.cpp')
-rw-r--r--audio/softsynth/opl/dosbox.cpp27
1 files changed, 21 insertions, 6 deletions
diff --git a/audio/softsynth/opl/dosbox.cpp b/audio/softsynth/opl/dosbox.cpp
index e039845b8f..a1a736f9de 100644
--- a/audio/softsynth/opl/dosbox.cpp
+++ b/audio/softsynth/opl/dosbox.cpp
@@ -247,7 +247,7 @@ byte OPL::read(int port) {
}
void OPL::writeReg(int r, int v) {
- byte tempReg = 0;
+ int tempReg = 0;
switch (_type) {
case Config::kOpl2:
case Config::kDualOpl2:
@@ -257,12 +257,27 @@ void OPL::writeReg(int r, int v) {
// Backup old setup register
tempReg = _reg.normal;
- // We need to set the register we want to write to via port 0x388
- write(0x388, r);
- // Do the real writing to the register
- write(0x389, v);
+ // We directly allow writing to secondary OPL3 registers by using
+ // register values >= 0x100.
+ if (_type == Config::kOpl3 && r >= 0x100) {
+ // We need to set the register we want to write to via port 0x222,
+ // since we want to write to the secondary register set.
+ write(0x222, r);
+ // Do the real writing to the register
+ write(0x223, v);
+ } else {
+ // We need to set the register we want to write to via port 0x388
+ write(0x388, r);
+ // Do the real writing to the register
+ write(0x389, v);
+ }
+
// Restore the old register
- write(0x388, tempReg);
+ if (_type == Config::kOpl3 && tempReg >= 0x100) {
+ write(0x222, tempReg & ~0x100);
+ } else {
+ write(0x388, tempReg);
+ }
break;
};
}