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| author | Max Lingua | 2014-01-09 20:57:17 -0500 |
|---|---|---|
| committer | Max Lingua | 2014-01-18 12:40:58 -0500 |
| commit | 17e8a6f220eb524bfebe07067266799268b45e04 (patch) | |
| tree | a2ee7ad07ea1d53005802af113f86d8145200f73 /backends/platform/ps2/sysdefs.h | |
| parent | f5748d16eb55ceca7abc12d8d4ca807106ea3161 (diff) | |
| download | scummvm-rg350-17e8a6f220eb524bfebe07067266799268b45e04.tar.gz scummvm-rg350-17e8a6f220eb524bfebe07067266799268b45e04.tar.bz2 scummvm-rg350-17e8a6f220eb524bfebe07067266799268b45e04.zip | |
PS2: cleaned cast (X*) -> (X *)
Diffstat (limited to 'backends/platform/ps2/sysdefs.h')
| -rw-r--r-- | backends/platform/ps2/sysdefs.h | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/backends/platform/ps2/sysdefs.h b/backends/platform/ps2/sysdefs.h index 0114402233..a4ada47015 100644 --- a/backends/platform/ps2/sysdefs.h +++ b/backends/platform/ps2/sysdefs.h @@ -40,30 +40,30 @@ enum Interrupts { }; // dma 2 registers -#define D2_CHCR (*(volatile uint32*)0x1000A000) -#define D2_QWC (*(volatile uint32*)0x1000A020) -#define D2_TADR (*(volatile uint32*)0x1000A030) -#define D2_MADR (*(volatile uint32*)0x1000A010) -#define D2_ASR1 (*(volatile uint32*)0x1000A050) -#define D2_ASR0 (*(volatile uint32*)0x1000A040) +#define D2_CHCR (*(volatile uint32 *)0x1000A000) +#define D2_QWC (*(volatile uint32 *)0x1000A020) +#define D2_TADR (*(volatile uint32 *)0x1000A030) +#define D2_MADR (*(volatile uint32 *)0x1000A010) +#define D2_ASR1 (*(volatile uint32 *)0x1000A050) +#define D2_ASR0 (*(volatile uint32 *)0x1000A040) -#define D_CTRL (*(volatile uint32*)0x1000E000) -#define D_STAT (*(volatile uint32*)0x1000E010) -#define D_PCR (*(volatile uint32*)0x1000E020) -#define D_SQWC (*(volatile uint32*)0x1000E030) -#define D_RBSR (*(volatile uint32*)0x1000E040) -#define D_RBOR (*(volatile uint32*)0x1000E050) -#define D_STADR (*(volatile uint32*)0x1000E060) +#define D_CTRL (*(volatile uint32 *)0x1000E000) +#define D_STAT (*(volatile uint32 *)0x1000E010) +#define D_PCR (*(volatile uint32 *)0x1000E020) +#define D_SQWC (*(volatile uint32 *)0x1000E030) +#define D_RBSR (*(volatile uint32 *)0x1000E040) +#define D_RBOR (*(volatile uint32 *)0x1000E050) +#define D_STADR (*(volatile uint32 *)0x1000E060) #define CIM2 (1 << 18) #define CIS2 (1 << 2) // timer 0 registers -#define T0_COUNT (*(volatile uint32*)0x10000000) -#define T0_MODE (*(volatile uint32*)0x10000010) -#define T0_COMP (*(volatile uint32*)0x10000020) -#define T0_HOLD (*(volatile uint32*)0x10000030) +#define T0_COUNT (*(volatile uint32 *)0x10000000) +#define T0_MODE (*(volatile uint32 *)0x10000010) +#define T0_COMP (*(volatile uint32 *)0x10000020) +#define T0_HOLD (*(volatile uint32 *)0x10000030) #define TIMER_MODE(clks, gate, gates, gatem, zeroret, cue, cmpe, ovfe, equf, ovff) \ ((clks) | ((gate) << 2) | ((gates) << 3) | ((gatem) << 4) | ((zeroret) << 6) | \ |