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| author | Vladimir | 2011-06-08 01:12:50 +0400 |
|---|---|---|
| committer | Alyssa Milburn | 2011-06-15 17:32:02 +0200 |
| commit | bba7724aec6b6b440e166fdd95b65be5346977c1 (patch) | |
| tree | a68e42a1aee9ffbbd207bb4f15feb112c02a9b42 /devtools | |
| parent | 694c00bd10ec3daaf61445dfdc7c37f6c04a525c (diff) | |
| download | scummvm-rg350-bba7724aec6b6b440e166fdd95b65be5346977c1.tar.gz scummvm-rg350-bba7724aec6b6b440e166fdd95b65be5346977c1.tar.bz2 scummvm-rg350-bba7724aec6b6b440e166fdd95b65be5346977c1.zip | |
DREAMWEB: added fake data register pointing to variables
Diffstat (limited to 'devtools')
| -rw-r--r-- | devtools/tasmrecover/tasm/cpp.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/devtools/tasmrecover/tasm/cpp.py b/devtools/tasmrecover/tasm/cpp.py index a8d225359b..1e77893f89 100644 --- a/devtools/tasmrecover/tasm/cpp.py +++ b/devtools/tasmrecover/tasm/cpp.py @@ -63,7 +63,7 @@ namespace %s { if size == 0: raise Exception("invalid var '%s' size %u" %(name, size)) if self.indirection == 0: - value = "context.ds.%s(%d)" %("byte" if size == 1 else "word", g.offset) + value = "context.data.%s(%d)" %("byte" if size == 1 else "word", g.offset) elif self.indirection == -1: value = "%s" %g.offset self.indirection = 0 |