1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
|
/*
* Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
*
* (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and
* Jerremy Koot (jkoot@snes9x.com)
*
* Super FX C emulator code
* (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and
* Gary Henderson.
* Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_.
*
* DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson.
* C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_.
* C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com).
*
* DOS port code contains the works of other authors. See headers in
* individual files.
*
* Snes9x homepage: http://www.snes9x.com
*
* Permission to use, copy, modify and distribute Snes9x in both binary and
* source form, for non-commercial purposes, is hereby granted without fee,
* providing that this license information and copyright notice appear with
* all copies and any derived work.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event shall the authors be held liable for any damages
* arising from the use of this software.
*
* Snes9x is freeware for PERSONAL USE only. Commercial users should
* seek permission of the copyright holders first. Commercial use includes
* charging money for Snes9x or software derived from Snes9x.
*
* The copyright holders request that bug fixes and improvements to the code
* should be forwarded to them so everyone can benefit from the modifications
* in future versions.
*
* Super NES and Super Nintendo Entertainment System are trademarks of
* Nintendo Co., Limited and its subsidiary companies.
*/
#ifndef _GETSET_H_
#define _GETSET_H_
#include "ppu.h"
#include "dsp1.h"
#include "cpuexec.h"
#include "sa1.h"
extern int oppause;
static INLINE uint8 S9xGetByte(uint32 Address)
{
#if defined(VAR_CYCLES) || defined(CPU_SHUTDOWN)
int block;
uint8* GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
#else
uint8* GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
#endif
if (GetAddress >= (uint8*) MAP_LAST)
{
#ifdef VAR_CYCLES
CPU.Cycles += Memory.MemorySpeed [block];
#endif
#ifdef CPU_SHUTDOWN
if (Memory.BlockIsRAM [block])
CPU.WaitAddress = CPU.PCAtOpcodeStart;
#endif
return (*(GetAddress + (Address & 0xffff)));
}
switch ((intptr_t) GetAddress)
{
case MAP_PPU:
#ifdef VAR_CYCLES
if (!CPU.InDMA)
CPU.Cycles += ONE_CYCLE;
#endif
return (S9xGetPPU(Address & 0xffff));
case MAP_CPU:
#ifdef VAR_CYCLES
CPU.Cycles += ONE_CYCLE;
#endif
return (S9xGetCPU(Address & 0xffff));
case MAP_DSP:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
return (S9xGetDSP(Address & 0xffff));
case MAP_SA1RAM:
case MAP_LOROM_SRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
return (*(Memory.SRAM + ((Address & CPU.Memory_SRAMMask))));
case MAP_HIROM_SRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
return (*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 +
((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)));
case MAP_DEBUG:
#ifdef DEBUGGER
printf("R(B) %06x\n", Address);
#endif
case MAP_BWRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
return (*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)));
//#ifndef __GP32__
case MAP_C4:
return (S9xGetC4(Address & 0xffff));
//#endif
default:
case MAP_NONE:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
#ifdef DEBUGGER
printf("R(B) %06x\n", Address);
#endif
return ((Address >> 8) & 0xff);
}
}
static INLINE uint16 S9xGetWord(uint32 Address)
{
#if defined(VAR_CYCLES) || defined(CPU_SHUTDOWN)
int block;
#endif
uint8 *GetAddress;
if ((Address & 0x1fff) == 0x1fff)
return (S9xGetByte(Address) | (S9xGetByte(Address + 1) << 8));
#if defined(VAR_CYCLES) || defined(CPU_SHUTDOWN)
GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
#else
GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
#endif
if (GetAddress >= (uint8*) MAP_LAST)
{
#ifdef VAR_CYCLES
CPU.Cycles += Memory.MemorySpeed [block] << 1;
#endif
#ifdef CPU_SHUTDOWN
if (Memory.BlockIsRAM [block])
CPU.WaitAddress = CPU.PCAtOpcodeStart;
#endif
#ifdef FAST_LSB_WORD_ACCESS
return (*(uint16*)(GetAddress + (Address & 0xffff)));
#else
return (*(GetAddress + (Address & 0xffff)) |
(*(GetAddress + (Address & 0xffff) + 1) << 8));
#endif
}
switch ((intptr_t) GetAddress)
{
case MAP_PPU:
#ifdef VAR_CYCLES
if (!CPU.InDMA)
CPU.Cycles += TWO_CYCLES;
#endif
return (S9xGetPPU(Address & 0xffff) |
(S9xGetPPU((Address + 1) & 0xffff) << 8));
case MAP_CPU:
#ifdef VAR_CYCLES
CPU.Cycles += TWO_CYCLES;
#endif
return (S9xGetCPU(Address & 0xffff) |
(S9xGetCPU((Address + 1) & 0xffff) << 8));
case MAP_DSP:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
return (S9xGetDSP(Address & 0xffff) |
(S9xGetDSP((Address + 1) & 0xffff) << 8));
case MAP_SA1RAM:
case MAP_LOROM_SRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
return (*(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) |
(*(Memory.SRAM + ((Address + 1) & CPU.Memory_SRAMMask)) << 8));
case MAP_HIROM_SRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
return (*(Memory.SRAM +
(((Address & 0x7fff) - 0x6000 +
((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) |
(*(Memory.SRAM +
((((Address + 1) & 0x7fff) - 0x6000 +
(((Address + 1) & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) << 8));
case MAP_BWRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
return (*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) |
(*(Memory.BWRAM + (((Address + 1) & 0x7fff) - 0x6000)) << 8));
case MAP_DEBUG:
#ifdef DEBUGGER
printf("R(W) %06x\n", Address);
#endif
//#ifndef __GP32__
case MAP_C4:
return (S9xGetC4(Address & 0xffff) |
(S9xGetC4((Address + 1) & 0xffff) << 8));
//#endif
default:
case MAP_NONE:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
#ifdef DEBUGGER
printf("R(W) %06x\n", Address);
#endif
return (((Address >> 8) | (Address & 0xff00)) & 0xffff);
}
}
static INLINE void S9xSetByte(uint8 Byte, uint32 Address)
{
#if defined(VAR_CYCLES)
int block;
#endif
uint8 *SetAddress;
#if defined(CPU_SHUTDOWN)
CPU.WaitAddress = NULL;
#endif
#if defined(VAR_CYCLES)
SetAddress = Memory.WriteMap [block = ((Address >> MEMMAP_SHIFT) & MEMMAP_MASK)];
#else
SetAddress = Memory.WriteMap [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
#endif
if (SetAddress >= (uint8*) MAP_LAST)
{
#ifdef VAR_CYCLES
CPU.Cycles += Memory.MemorySpeed [block];
#endif
#ifdef CPU_SHUTDOWN
SetAddress += Address & 0xffff;
#ifdef USE_SA1
if (SetAddress == SA1.WaitByteAddress1 ||
SetAddress == SA1.WaitByteAddress2)
{
SA1.Executing = SA1.S9xOpcodes != NULL;
SA1.WaitCounter = 0;
}
#endif
*SetAddress = Byte;
#else
*(SetAddress + (Address & 0xffff)) = Byte;
#endif
return;
}
switch ((intptr_t) SetAddress)
{
case MAP_PPU:
#ifdef VAR_CYCLES
if (!CPU.InDMA)
CPU.Cycles += ONE_CYCLE;
#endif
S9xSetPPU(Byte, Address & 0xffff);
return;
case MAP_CPU:
#ifdef VAR_CYCLES
CPU.Cycles += ONE_CYCLE;
#endif
S9xSetCPU(Byte, Address & 0xffff);
return;
case MAP_DSP:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
S9xSetDSP(Byte, Address & 0xffff);
return;
case MAP_LOROM_SRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
if (CPU.Memory_SRAMMask)
{
*(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) = Byte;
CPU.SRAMModified = TRUE;
}
return;
case MAP_HIROM_SRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
if (CPU.Memory_SRAMMask)
{
*(Memory.SRAM + (((Address & 0x7fff) - 0x6000 +
((Address & 0xf0000) >> 3)) & CPU.Memory_SRAMMask)) = Byte;
CPU.SRAMModified = TRUE;
}
return;
case MAP_BWRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = Byte;
CPU.SRAMModified = TRUE;
return;
case MAP_DEBUG:
#ifdef DEBUGGER
printf("W(B) %06x\n", Address);
#endif
case MAP_SA1RAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
*(Memory.SRAM + (Address & 0xffff)) = Byte;
#ifdef USE_SA1
SA1.Executing = !SA1.Waiting;
#endif
break;
//#ifndef __GP32__
case MAP_C4:
S9xSetC4(Byte, Address & 0xffff);
return;
//#endif
default:
case MAP_NONE:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
#ifdef DEBUGGER
printf("W(B) %06x\n", Address);
#endif
return;
}
}
static INLINE void S9xSetWord(uint16 Word, uint32 Address)
{
#if defined (VAR_CYCLES)
int block;
#endif
uint8* SetAddress;
#if defined(CPU_SHUTDOWN)
CPU.WaitAddress = NULL;
#endif
#if defined (VAR_CYCLES)
SetAddress = Memory.WriteMap [block = ((Address >> MEMMAP_SHIFT) & MEMMAP_MASK)];
#else
SetAddress = Memory.WriteMap [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
#endif
if (SetAddress >= (uint8*) MAP_LAST)
{
#ifdef VAR_CYCLES
CPU.Cycles += Memory.MemorySpeed [block] << 1;
#endif
#if defined(CPU_SHUTDOWN) && defined(USE_SA1)
SetAddress += Address & 0xffff;
if (SetAddress == SA1.WaitByteAddress1 ||
SetAddress == SA1.WaitByteAddress2)
{
SA1.Executing = SA1.S9xOpcodes != NULL;
SA1.WaitCounter = 0;
}
SetAddress -= Address & 0xffff;
#ifdef FAST_LSB_WORD_ACCESS
*(uint16*) SetAddress = Word;
#else
*(SetAddress + (Address & 0xffff)) = (uint8) Word;
*(SetAddress + ((Address + 1) & 0xffff)) = Word >> 8;
#endif
#else
#ifdef FAST_LSB_WORD_ACCESS
*(uint16*)(SetAddress + (Address & 0xffff)) = Word;
#else
*(SetAddress + (Address & 0xffff)) = (uint8) Word;
*(SetAddress + ((Address + 1) & 0xffff)) = Word >> 8;
#endif
#endif
return;
}
switch ((intptr_t) SetAddress)
{
case MAP_PPU:
#ifdef VAR_CYCLES
if (!CPU.InDMA)
CPU.Cycles += TWO_CYCLES;
#endif
S9xSetPPU((uint8) Word, Address & 0xffff);
S9xSetPPU(Word >> 8, (Address & 0xffff) + 1);
return;
case MAP_CPU:
#ifdef VAR_CYCLES
CPU.Cycles += TWO_CYCLES;
#endif
S9xSetCPU((uint8) Word, (Address & 0xffff));
S9xSetCPU(Word >> 8, (Address & 0xffff) + 1);
return;
case MAP_DSP:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
S9xSetDSP((uint8) Word, (Address & 0xffff));
S9xSetDSP(Word >> 8, (Address & 0xffff) + 1);
return;
case MAP_LOROM_SRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
if (CPU.Memory_SRAMMask)
{
*(Memory.SRAM + (Address & CPU.Memory_SRAMMask)) = (uint8) Word;
*(Memory.SRAM + ((Address + 1) & CPU.Memory_SRAMMask)) = Word >> 8;
CPU.SRAMModified = TRUE;
}
return;
case MAP_HIROM_SRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
if (CPU.Memory_SRAMMask)
{
*(Memory.SRAM +
(((Address & 0x7fff) - 0x6000 +
((Address & 0xf0000) >> MEMMAP_SHIFT) & CPU.Memory_SRAMMask))) = (uint8) Word;
*(Memory.SRAM +
((((Address + 1) & 0x7fff) - 0x6000 +
(((Address + 1) & 0xf0000) >> MEMMAP_SHIFT) & CPU.Memory_SRAMMask))) = (uint8)(Word >> 8);
CPU.SRAMModified = TRUE;
}
return;
case MAP_BWRAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
*(Memory.BWRAM + ((Address & 0x7fff) - 0x6000)) = (uint8) Word;
*(Memory.BWRAM + (((Address + 1) & 0x7fff) - 0x6000)) = (uint8)(Word >> 8);
CPU.SRAMModified = TRUE;
return;
case MAP_DEBUG:
#ifdef DEBUGGER
printf("W(W) %06x\n", Address);
#endif
case MAP_SA1RAM:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE;
#endif
*(Memory.SRAM + (Address & 0xffff)) = (uint8) Word;
*(Memory.SRAM + ((Address + 1) & 0xffff)) = (uint8)(Word >> 8);
#ifdef USE_SA1
SA1.Executing = !SA1.Waiting;
#endif
break;
//#ifndef __GP32__
case MAP_C4:
S9xSetC4(Word & 0xff, Address & 0xffff);
S9xSetC4((uint8)(Word >> 8), (Address + 1) & 0xffff);
return;
//#endif
default:
case MAP_NONE:
#ifdef VAR_CYCLES
CPU.Cycles += SLOW_ONE_CYCLE * 2;
#endif
#ifdef DEBUGGER
printf("W(W) %06x\n", Address);
#endif
return;
}
}
static INLINE uint8* GetBasePointer(uint32 Address)
{
uint8* GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
if (GetAddress >= (uint8*) MAP_LAST)
return (GetAddress);
switch ((intptr_t) GetAddress)
{
case MAP_PPU:
return (Memory.FillRAM - 0x2000);
case MAP_CPU:
return (Memory.FillRAM - 0x4000);
case MAP_DSP:
return (Memory.FillRAM - 0x6000);
case MAP_SA1RAM:
case MAP_LOROM_SRAM:
return (Memory.SRAM);
case MAP_BWRAM:
return (Memory.BWRAM - 0x6000);
case MAP_HIROM_SRAM:
return (Memory.SRAM - 0x6000);
//#ifndef __GP32__
case MAP_C4:
return (Memory.C4RAM - 0x6000);
//#endif
case MAP_DEBUG:
#ifdef DEBUGGER
printf("GBP %06x\n", Address);
#endif
default:
case MAP_NONE:
#ifdef DEBUGGER
printf("GBP %06x\n", Address);
#endif
return (0);
}
}
static INLINE uint8* S9xGetMemPointer(uint32 Address)
{
uint8* GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
if (GetAddress >= (uint8*) MAP_LAST)
return (GetAddress + (Address & 0xffff));
switch ((intptr_t) GetAddress)
{
case MAP_PPU:
return (Memory.FillRAM - 0x2000 + (Address & 0xffff));
case MAP_CPU:
return (Memory.FillRAM - 0x4000 + (Address & 0xffff));
case MAP_DSP:
return (Memory.FillRAM - 0x6000 + (Address & 0xffff));
case MAP_SA1RAM:
case MAP_LOROM_SRAM:
return (Memory.SRAM + (Address & 0xffff));
case MAP_BWRAM:
return (Memory.BWRAM - 0x6000 + (Address & 0xffff));
case MAP_HIROM_SRAM:
return (Memory.SRAM - 0x6000 + (Address & 0xffff));
//#ifndef __GP32__
case MAP_C4:
return (Memory.C4RAM - 0x6000 + (Address & 0xffff));
//#endif
case MAP_DEBUG:
#ifdef DEBUGGER
printf("GMP %06x\n", Address);
#endif
default:
case MAP_NONE:
#ifdef DEBUGGER
printf("GMP %06x\n", Address);
#endif
return (0);
}
}
static INLINE void S9xSetPCBase(uint32 Address)
{
#ifdef VAR_CYCLES
int block;
uint8* GetAddress = Memory.Map [block = (Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
#else
uint8* GetAddress = Memory.Map [(Address >> MEMMAP_SHIFT) & MEMMAP_MASK];
#endif
if (GetAddress >= (uint8*) MAP_LAST)
{
#ifdef VAR_CYCLES
CPU.MemSpeed = Memory.MemorySpeed [block];
CPU.MemSpeedx2 = CPU.MemSpeed << 1;
#endif
CPU.PCBase = GetAddress;
CPU.PC = GetAddress + (Address & 0xffff);
return;
}
switch ((intptr_t) GetAddress)
{
case MAP_PPU:
#ifdef VAR_CYCLES
CPU.MemSpeed = ONE_CYCLE;
CPU.MemSpeedx2 = TWO_CYCLES;
#endif
CPU.PCBase = Memory.FillRAM - 0x2000;
CPU.PC = CPU.PCBase + (Address & 0xffff);
return;
case MAP_CPU:
#ifdef VAR_CYCLES
CPU.MemSpeed = ONE_CYCLE;
CPU.MemSpeedx2 = TWO_CYCLES;
#endif
CPU.PCBase = Memory.FillRAM - 0x4000;
CPU.PC = CPU.PCBase + (Address & 0xffff);
return;
case MAP_DSP:
#ifdef VAR_CYCLES
CPU.MemSpeed = SLOW_ONE_CYCLE;
CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
#endif
CPU.PCBase = Memory.FillRAM - 0x6000;
CPU.PC = CPU.PCBase + (Address & 0xffff);
return;
case MAP_SA1RAM:
case MAP_LOROM_SRAM:
#ifdef VAR_CYCLES
CPU.MemSpeed = SLOW_ONE_CYCLE;
CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
#endif
CPU.PCBase = Memory.SRAM;
CPU.PC = CPU.PCBase + (Address & 0xffff);
return;
case MAP_BWRAM:
#ifdef VAR_CYCLES
CPU.MemSpeed = SLOW_ONE_CYCLE;
CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
#endif
CPU.PCBase = Memory.BWRAM - 0x6000;
CPU.PC = CPU.PCBase + (Address & 0xffff);
return;
case MAP_HIROM_SRAM:
#ifdef VAR_CYCLES
CPU.MemSpeed = SLOW_ONE_CYCLE;
CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
#endif
CPU.PCBase = Memory.SRAM - 0x6000;
CPU.PC = CPU.PCBase + (Address & 0xffff);
return;
//#ifndef __GP32__
case MAP_C4:
#ifdef VAR_CYCLES
CPU.MemSpeed = SLOW_ONE_CYCLE;
CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
#endif
CPU.PCBase = Memory.C4RAM - 0x6000;
CPU.PC = CPU.PCBase + (Address & 0xffff);
return;
//#endif
case MAP_DEBUG:
#ifdef DEBUGGER
printf("SBP %06x\n", Address);
#endif
default:
case MAP_NONE:
#ifdef VAR_CYCLES
CPU.MemSpeed = SLOW_ONE_CYCLE;
CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2;
#endif
#ifdef DEBUGGER
printf("SBP %06x\n", Address);
#endif
CPU.PCBase = Memory.SRAM;
CPU.PC = Memory.SRAM + (Address & 0xffff);
return;
}
}
#endif
|
