| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2012-12-18 | Un-inline a bunch of stuff. | Nebuleon Fumika | |
| With the MIPS instruction cache, this means that two consecutive SNES CPU instructions using e.g. the same addressing style or the same opcode have a chance that the second one will use the first one's code and that it will be cached. | |||
| 2011-03-05 | first commit | Kitty Draper | |
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index : snes9x2005 | |
| Snes9x 2005. Port of SNES9x 1.43 for libretro (was previously called CAT SFC). Forked from https://github.com/libretro/snes9x2005 | neonloop |
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