Age | Commit message (Collapse) | Author | |
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2012-12-23 | Various optimisations in the CPU emulation. | Nebuleon Fumika | |
Run the opcode as a tail call from the address calculation. This cuts on the needed return instructions. Pass the opcode address as a parameter; this keeps it in a register most of the time and avoids memory stores. | |||
2012-12-18 | Un-inline a bunch of stuff. | Nebuleon Fumika | |
With the MIPS instruction cache, this means that two consecutive SNES CPU instructions using e.g. the same addressing style or the same opcode have a chance that the second one will use the first one's code and that it will be cached. | |||
2011-03-05 | first commit | Kitty Draper | |