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and 'game off the system' - UNDER NO CIRCUMSTANCES WILL ANY
COMMERCIAL RIGHTS EVER BE APPROPRIATED TO ANY ONE PARTY, REGARDLESS
OF ANY E-MAILS, BRIBES, ETC.
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* before rendering a background;
* before rendering sprites;
* while rendering more than 128 samples of audio at once ("Prefer fluid video");
* after every 16 scanlines of CPU execution instead of every 1;
* while waiting for an audio buffer to become available;
* while killing time between frames with fast-forward disabled.
Controller presses and releases are now combined in a DS button bitfield using a shorter 32-bit algorithm. See entry.cpp:NDSSFCAccumulateJoypad and #define ACCUMULATE_JOYPAD in the source.
This is still not suitable for playing platformers frame-perfectly, but it's much better than half a second of latency to press or release a button, and one still needs to press buttons a bit more than just light taps. I'd say 50 milliseconds is the latency now. Platformers requiring more precision can be played with frameskip 0.
DMA does not require double-buffered displaying, so synchronise the controller more often by disabling double-buffered displaying again.
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This makes the menu text in Secret of Mana readable.
Sprites in Background Mode 5 are still messed up. At least they're at the right X coordinate, roughly...
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lose keys entirely sometimes, and could otherwise delay a button press or release by 200 ms.
This was the entire reason I created the fork, and I finally did it! It syncs the controls every scanline of a frame, which costs about 60,000 MIPS instructions per frame to deal with. Luckily, the processor runs at 396 MHz, which means the cost of checking the controls is 1% of the CPU's power.
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SNES Open Bus is a quirk of the memory subsystem that allow reads of invalid addresses to return the last byte read from memory. However, it is seldom needed by a game, and it costs 1 to 3 MIPS instructions per SNES instruction to emulate.
If you need SNES Open Bus, you can remove -DNO_OPEN_BUS from the Makefile.
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With the MIPS instruction cache, this means that two consecutive SNES CPU instructions using e.g. the same addressing style or the same opcode have a chance that the second one will use the first one's code and that it will be cached.
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