aboutsummaryrefslogtreecommitdiff
path: root/source/tile.cpp
AgeCommit message (Collapse)Author
2012-12-18Un-inline a bunch of stuff.Nebuleon Fumika
With the MIPS instruction cache, this means that two consecutive SNES CPU instructions using e.g. the same addressing style or the same opcode have a chance that the second one will use the first one's code and that it will be cached.
2011-03-05first commitKitty Draper