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author | notaz | 2011-01-14 18:32:17 +0200 |
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committer | notaz | 2011-01-16 00:03:53 +0200 |
commit | 076655d17df35d1f40137e88b7beaf5a039b058c (patch) | |
tree | 27a338138797012c1fa9680cfbdf75f68f9e167b | |
parent | fca1aef29ed173264919b7a0b35f92dbe0d4e521 (diff) | |
download | pcsx_rearmed-076655d17df35d1f40137e88b7beaf5a039b058c.tar.gz pcsx_rearmed-076655d17df35d1f40137e88b7beaf5a039b058c.tar.bz2 pcsx_rearmed-076655d17df35d1f40137e88b7beaf5a039b058c.zip |
drc: allow reading r31 in delay slot
as hlide explained it's ok as long as we do DS first.
-rw-r--r-- | libpcsxcore/new_dynarec/new_dynarec.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index f8a67ff..f1a0def 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -8688,7 +8688,8 @@ int new_recompile_block(int addr) if (rt1[i]==31) { alloc_reg(¤t,i,31); dirty_reg(¤t,31); - assert(rs1[i+1]!=31&&rs2[i+1]!=31); + //assert(rs1[i+1]!=31&&rs2[i+1]!=31); + assert(rt1[i+1]!=rt1[i]); #ifdef REG_PREFETCH alloc_reg(¤t,i,PTEMP); #endif @@ -8712,7 +8713,8 @@ int new_recompile_block(int addr) if (rt1[i]!=0) { alloc_reg(¤t,i,rt1[i]); dirty_reg(¤t,rt1[i]); - assert(rs1[i+1]!=31&&rs2[i+1]!=31); + //assert(rs1[i+1]!=31&&rs2[i+1]!=31); + assert(rt1[i+1]!=rt1[i]); #ifdef REG_PREFETCH alloc_reg(¤t,i,PTEMP); #endif |