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| author | notaz | 2010-12-21 15:46:24 +0200 |
|---|---|---|
| committer | notaz | 2010-12-22 01:24:05 +0200 |
| commit | d28b54b1d1d161b3f3acc3299c43106a022451e6 (patch) | |
| tree | 2ba7ad08ffdd0651100206931f99ece3dfa490b2 /libpcsxcore/r3000a.h | |
| parent | 96d9fde1230e5ae6de069ff9e4a0f16185650ab5 (diff) | |
| download | pcsx_rearmed-d28b54b1d1d161b3f3acc3299c43106a022451e6.tar.gz pcsx_rearmed-d28b54b1d1d161b3f3acc3299c43106a022451e6.tar.bz2 pcsx_rearmed-d28b54b1d1d161b3f3acc3299c43106a022451e6.zip | |
core: update to newer interrupt code, seems to affect timings too
pcsxr-svn commit:
Author: weimingzhi
Date: Sat Aug 7 23:52:44 2010 +0000
refactored the interrupt scheduling code a bit to make it a little
more readable than using those "magic" numbers.
Diffstat (limited to 'libpcsxcore/r3000a.h')
| -rw-r--r-- | libpcsxcore/r3000a.h | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/libpcsxcore/r3000a.h b/libpcsxcore/r3000a.h index 9379f45..a2fcca3 100644 --- a/libpcsxcore/r3000a.h +++ b/libpcsxcore/r3000a.h @@ -145,6 +145,17 @@ typedef union { PAIR p[32]; } psxCP2Ctrl; +enum { + PSXINT_SIO = 0, + PSXINT_CDR, + PSXINT_CDREAD, + PSXINT_GPUDMA, + PSXINT_MDECOUTDMA, + PSXINT_SPUDMA, + PSXINT_NEWDRC_CHECK, + PSXINT_COUNT +}; + typedef struct { psxGPRRegs GPR; /* General Purpose Registers */ psxCP0Regs CP0; /* Coprocessor0 Registers */ @@ -154,11 +165,26 @@ typedef struct { u32 code; /* The instruction */ u32 cycle; u32 interrupt; - u32 intCycle[32]; + struct { u32 sCycle, cycle; } intCycle[32]; } psxRegisters; extern psxRegisters psxRegs; +/* new_dynarec stuff */ +extern u32 event_cycles[PSXINT_COUNT]; +extern u32 next_interupt; + +#define new_dyna_set_event(e, c) { \ + s32 c_ = c; \ + u32 abs_ = psxRegs.cycle + c_; \ + s32 odi_ = next_interupt - psxRegs.cycle; \ + event_cycles[e] = abs_; \ + if (c_ < odi_) { \ + /*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \ + next_interupt = abs_; \ + } \ +} + #if defined(__BIGENDIAN__) #define _i32(x) *(s32 *)&x |